JP2022177789A - Circuit and shift register outputting output signal - Google Patents

Abstract

To improve characteristics of a CMOS circuit.SOLUTION: While a first P-type thin-film transistor is ON, an N-type thin-film transistor and a second P-type thin-film transistor are OFF, and a signal of first output signal supply wiring is supplied to an output line. While the N-type thin-film transistor and the second P-type thin-film transistor are ON, the first P-type thin-film transistor is OFF, and a signal of second output signal supply wiring is supplied to the output line.SELECTED DRAWING: Figure 4

Description

The present disclosure relates to circuits and shift registers that output output signals.

As the display device, a liquid crystal display device (LCD) and an OLED (Organic Light-Emitting Diode) display device are widely used. These display devices include shift registers for driving (selecting) the scan lines. Further, an OLED display device is known that measures the characteristics of the elements (drive transistor or OLED) of the display device and corrects the data signal based on the measurement result. OLED displays with external compensation of such data signals include shift registers that output control signals for measurement.

A device using LTPO technology in which a low-temperature polysilicon (LTPS) thin film transistor (TFT) and an oxide semiconductor TFT, such as an IGZO TFT, are integrated on the same substrate has been applied to display panels, and its application range has expanded. is expanding.

These products can be designed according to the device characteristics, for example, applying IGZO where leakage current is a problem and LTPS where drive capability is required. Also, the possibility of realizing a CMOS (Complementary metal-oxide-semiconductor) device by combining a PMOS-type LTPSTFT and an NMOS-type IGZO TFT is being studied.

The node to which the gate of the output transistor is connected is changed to a high potential (or a low potential) during the period from when data is input to the shift register until it is output. At this time, in order to electrically connect to either the high potential power supply or the low potential power supply, the power supply is complementarily connected by CMOS using both N-channel and P-channel transistors. A CMOS circuit can have a smaller circuit scale and higher reliability than a circuit of a single conductive TFT.

U.S. Patent Application No. 2010/0176395 U.S. Patent Application No. 2003/0173995 U.S. Patent Application No. 2019/0204968

However, the CMOS circuit combining the LTPSTFT and the oxide semiconductor TFT has some problems due to the characteristics of those TFTs. One is that the presence of a large difference in mobility between LTPS and an oxide semiconductor increases the area occupied by an oxide semiconductor TFT in a CMOS circuit. For example, the mobility of IGZO is nearly an order of magnitude lower than that of LTPS. Another problem is that the residual electric charge in the output line is difficult to escape as a tradeoff of the low leakage characteristics of the oxide semiconductor TFT. This can lead to malfunctions and reduced reliability.

One aspect of the present disclosure is a circuit that outputs an output signal from an output line, comprising a first output signal supply wiring, a second output signal supply wiring, an output line, the first output signal supply wiring, and the output a first P-type thin film transistor that turns ON/OFF between the line, an N-type thin film transistor that turns ON/OFF between the second output signal supply wiring and the output line, the second output signal supply wiring and the a second P-type thin film transistor that turns ON/OFF between the output line and the second P-type thin film transistor. While the first P-type thin film transistor is ON, the N-type thin film transistor and the second P-type thin film transistor are OFF, and the signal of the first output signal supply line is supplied to the output line. While the N-type thin film transistor and the second P-type thin film transistor are ON, the first P-type thin film transistor is OFF, and the signal of the second output signal supply line is supplied to the output line.

According to one aspect of the present disclosure, it is possible to improve the characteristics of a CMOS circuit.

1 schematically shows a configuration example of an OLED display device. 1 shows a configuration example of a pixel circuit of an OLED display device. 1 shows a configuration example of a pixel circuit of a liquid crystal display device. 1 shows a configuration example of a pixel circuit of a liquid crystal display device. 1 shows a configuration of a CMOS circuit according to one embodiment of the present specification; 3B schematically shows an example of a device layout of the CMOS circuit shown in FIG. 3A; FIG. 3B schematically shows an example of a device layout of the CMOS circuit shown in FIG. 3A; FIG. 4 schematically shows a circuit configuration for each shift register that can be included in the shift register of the scan driver. FIG. 5 shows a timing chart of the circuit shown in FIG. 4; FIG. 4 shows part of a shift register that can be implemented in a scan driver. FIG. 7 shows a timing chart of signals of the shift register shown in FIG. 6; FIG. 3 shows an example of a circuit configuration for each shift register that can be implemented in a scan driver. 9 shows a timing chart of the circuit shown in FIG. 8; 4 shows a timing chart of the signals of the shift register of the scan driver. 3 shows another configuration example of a shift register unit. 12 shows a timing chart of the circuit shown in FIG. 11; FIG. 13 shows a configuration of part of a shift register including the shift register unit described with reference to FIGS. 11 and 12; FIG. 3 shows another configuration example of a shift register unit. 15 shows a timing chart of the circuit shown in FIG. 14; FIG. 16 shows a configuration of part of a shift register including the shift register unit described with reference to FIGS. 14 and 15; FIG.

Embodiments of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the present embodiment is merely an example for realizing the present disclosure and does not limit the technical scope of the present disclosure.

<Overview>
A circuit configuration applicable to a shift register such as a liquid crystal display device (LCD) or an OLED (Organic Light-Emitting Diode) display device will be described below. The circuits disclosed below can be applied to devices other than display devices.

A circuit according to one embodiment herein utilizes LTPO technology that integrates low temperature polysilicon (LTPS) thin film transistors (TFTs) and oxide semiconductor TFTs, eg, IGZO TFTs. The circuit includes a complementary metal-oxide-semiconductor (CMOS) circuit configured by combining a PMOS type (also simply called P-type) LTPSTFT and an NMOS type (also simply called N-type) IGZO TFT.

A CMOS circuit can be made smaller in circuit scale than a circuit composed of TFTs of a single conductivity type. A single-conducting TFT circuit produces a high voltage output signal, so bootstrapping is required to lower the gate potential of the pull-down TFT. In order to bootstrap, it is necessary to provide a capacitance between the gate and source of the pull-down TFT.

In addition, isolation TFTs are implemented so that high voltages during bootstrapping do not apply high voltages between the drain and source of a particular control TFT. These increase the scale of the single-conducting circuit. Also, electrical stress is applied to the TFT, which can reduce reliability.

A CMOS circuit does not require a bootstrap in a single-type circuit, and circuit elements for bootstrapping can be omitted to reduce the circuit scale. However, conventional CMOS circuits that combine LTPSTFTs and oxide semiconductor TFTs have several problems. One is that the area occupied by the oxide semiconductor TFT is large in the CMOS circuit. This is because there is a large difference in mobility between LTPS and an oxide semiconductor. For example, the mobility of IGZO is about 1/10 that of LTPS.

Another problem is that the residual charge in the output line of the conventional CMOS circuit is difficult to discharge, which may cause malfunction and reduce reliability. This is due to the low leak characteristics of oxide semiconductor TFTs. For example, in automotive display devices, when the input signal supplied to the CMOS circuit becomes unstable due to unexpected fluctuations in the power supply voltage during operation, there is a demand for a fail-safe function that switches to black display to prevent abnormal display. ing. Since the off-leakage of the oxide semiconductor TFT is small, display defects may occur due to residual charges.

A CMOS circuit according to an embodiment of the present specification includes a pull-up P-type TFT for supplying a high potential to an output line and a pull-down N-type TFT for supplying a low potential to an output line. and includes a pull-down P-type TFT. The P-type TFT may be an LTPSTFT, and the N-type TFT may be an oxide semiconductor TFT, such as an IGZO TFT. This configuration is particularly effective in a CMOS circuit in which the mobility of the P-type TFT is higher than that of the N-type TFT and the leakage current of the N-type TFT is smaller than that of the P-type TFT. The semiconductor of the P-type TFT may be a material other than polysilicon, and the semiconductor of the N-type TFT may be a material other than an oxide semiconductor.

As described above, the operation of pulling up the potential of the output line to a predetermined high potential level (VH) is performed by the pull-up P-type TFT. The pull-down P-type TFT pulls down the potential of the output line from a predetermined low potential (VL) to a potential higher by a predetermined voltage, specifically to a potential (VL+Vth) substantially higher by the threshold voltage of the pull-down P-type TFT. can. The pull-down N-type TFT continuously pulls down the potential of the output line from the potential (VL+Vth) to a predetermined potential level VL.

Since the pull-down P-type TFT reduces the potential of the output line to (VL+Vth), the operation of the pull-down N-type TFT does not require a large driving capability to pull down the output line potential. Therefore, an increase in circuit area can be suppressed compared to a CMOS configuration.

Embodiments will be specifically described below with reference to the drawings. The same reference numerals are given to the common components in each figure. In order to make the description easier to understand, the dimensions and shapes of the illustrated objects may be exaggerated.

<Embodiment 1>
[overall structure]
FIG. 1 schematically shows a configuration example of an OLED display device 10. As shown in FIG. Although an OLED display device will be described below as an example of a device to which the shift register of the present disclosure is applied, it can be applied to other display devices or devices different from display devices. The OLED display device 10 includes a TFT (Thin Film Transistor) substrate 100 on which OLED elements are formed, and a sealing structure 200 that seals the OLED elements.

Scan drivers 131 and 132, a driver IC 134, and a demultiplexer 136 are arranged around the cathode electrode forming area 114 outside the display area 125 of the TFT substrate 100. FIG. The first scanning driver 131 drives scanning lines of the TFT substrate 100, for example. The second scan driver 132 drives the measurement control line, for example, in order to measure device characteristics such as organic light emitting devices and TFTs.

The driver IC 134 is connected to external equipment via an FPC (Flexible Printed Circuit) 135 . The driver IC 134 is mounted using, for example, an anisotropic conductive film (ACF).

The driver IC 134 supplies power and timing signals (control signals) to the scanning drivers 131 and 132 . In addition, driver IC 134 provides power and data signals to demultiplexer 136 . The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 136 drives d times as many data lines as the number of output pins of the driver IC 134 by switching the output destination data line of the data signal from the driver IC 134 d times within the scanning period.

[Pixel circuit configuration]
A plurality of pixel circuits are formed on the TFT substrate 100 for controlling the currents supplied to the anode electrodes of the plurality of sub-pixels. FIG. 2A shows a configuration example of a pixel circuit. Each pixel circuit includes a drive transistor 21, a selection transistor 22, a measurement transistor 24, and a storage capacitor C. As shown in FIG. The pixel circuit controls light emission of the OLED element E1. The transistors are field effect transistors, more specifically TFTs.

A selection transistor 22 is a switch that selects a sub-pixel. In the configuration example of FIG. 2A, the selection transistor 22 is an N-type TFT, and the gate terminal is connected to the scanning line 106 . One source/drain terminal is connected to data line 105 . Another source/drain terminal is connected to the gate terminal of the driving transistor 21 .

The drive transistor 21 is a transistor (drive TFT) for driving the OLED element E1. The driving transistor 21 is a P-type TFT and its gate terminal is connected to the source/drain terminal of the selection transistor 22 . A source terminal of the drive transistor 21 is connected to the power supply line 108 (Vdd). The drain terminal is connected to the anode of OLED element E1. A storage capacitor C is formed between the gate terminal and the source terminal of the drive transistor 21 .

The measurement transistor 24 is a P-type TFT and controls electrical connection between the reference voltage supply line 110 and the anode of the OLED element E1. This control is performed by supplying a control signal from the measurement control line 109 to the gate of the measurement transistor 24 . The measuring transistor 24 is used for the purpose of measuring the characteristics of the driving transistor 21 and the OLED element E1.

Next, the operation of the pixel circuit will be described. The scanning driver 131 outputs a selection pulse to the scanning line 106 to turn on the selection transistor 22 . A data voltage supplied from the driver IC 134 via the data line 105 is stored in the holding capacitor C. FIG. The holding capacitor C holds the stored voltage throughout one frame period. The holding voltage causes the conductance of the drive transistor 21 to change in an analog manner, and the drive transistor 21 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

The measuring transistor 24 can be used for the purpose of measuring the characteristics of the driving transistor 21 . For example, if the bias conditions are selected so that the drive transistor 21 operates in the saturation region and the measurement transistor 24 operates in the linear region, and the current flowing from the power supply line 108 (Vdd) to the reference voltage supply line 110 (Vref) is measured, The voltage-to-current conversion characteristic of the drive transistor 21 can be accurately measured. If an external circuit generates a data signal that compensates for the difference in the voltage-current conversion characteristics of the driving transistor 21 between sub-pixels, a highly uniform display image can be realized.

Alternatively, if the drive transistor 21 is turned off, the measurement transistor 24 is operated in the linear region, and a voltage that causes the OLED element E1 to emit light is applied from the reference voltage supply line 110, the voltage-current characteristics of the OLED element E1 can be accurately measured. can be measured. For example, even if the OLED element E1 deteriorates due to long-term use, it is possible to extend the life by generating a data signal that compensates for the amount of deterioration in an external circuit.

The pixel circuit of the OLED display device 10 of FIG. 2A is an example, and the pixel circuit may have other circuit configurations. The number of TFTs and capacitive elements forming a pixel circuit and the conductivity type of each TFT are determined according to the design of the TFT substrate.

Next, an example of a pixel circuit of a liquid crystal display device will be described. 2B and 2C each show an example of a pixel circuit of a liquid crystal display device. The pixel circuit example of FIG. 2B includes an N-type switch thin film transistor 202, a holding capacitor Cst, and a liquid crystal LC between the common electrode and the pixel electrode. A common potential Vcom is applied to the common electrode. The scan driver outputs a selection pulse to the scan line 206 to turn on the N-type switch thin film transistor 202 . The data line 205 supplies a data signal to the pixel electrode and the storage capacitor Cst through the N-type switch thin film transistor 202 in ON state.

The pixel circuit example of FIG. 2C includes a P-type switch thin film transistor 212, a holding capacitor Cst, and a liquid crystal LC between the common electrode and the pixel electrode. A common potential Vcom is applied to the common electrode. The scan driver outputs a selection pulse to the scan line 206 to turn on the P-type switch thin film transistor 212 . The data line 205 supplies a data signal to the pixel electrode and the storage capacitor Cst through the P-type switch thin film transistor 212 in ON state.

Scan drivers 131 and 132 include shift registers for sequentially selecting scan line 106 and measurement control line 109, respectively. The shift registers described below can be applied to one or both of scan drivers 131 and 132 .

[CMOS circuit configuration]
FIG. 3A shows a configuration of a CMOS circuit according to one embodiment herein. CMOS circuitry may be included in one or both of the scan drivers 131, 132, for example. The CMOS circuit includes a first P-type TFT 311 , a second P-type TFT 312 and an N-type TFT 315 . The first P-type TFT 311 is a pull-up TFT, and the second P-type TFT 312 and N-type TFT 315 are pull-down TFTs. In the configuration example of FIG. 3A, the P-type TFTs 311 and 312 are LTPSTFTs, and the N-type TFT 315 is an oxide semiconductor TFT such as an IGZO TFT.

A pull-up P-type TFT 311 is present between a high potential line 331 for applying a high potential VH and an output line 321 for outputting an output signal OUT. The two sources/drains of the pull-up P-type TFT 131 are connected to the high potential line 331 and the output line 321, respectively. The high potential line 331 is included in the first output signal supply wiring.

The pull-down P-type TFT 312 is present between the output line 321 and a low potential line 333 that applies a low potential VL lower than the high potential VH. Two sources/drains of the pull-down P-type TFT 312 are connected to the low potential line 333 and the output line 321, respectively. The low potential line 333 is included in the second output signal supply wiring.

The pull-down N-type TFT 315 is present between the low potential line 331 applying the low potential VL and the output line 321 . Two sources/drains of the pull-down N-type TFT 315 are connected to the low potential line 332 and the output line 321, respectively. The low potential line 332 applies a low potential VL like the low potential line 333, and is included in the second output signal supply wiring. The low potential line 332 may be connected to the low potential line 333 . The potential of the intermediate node between the source/drain of the pull-up P-type TFT 311 and the source/drain of each of the pull-down TFTs 312 and 315 is the potential of the signal OUT of the output line 321 .

The same control signal (first gate signal) IN1 is input to the gates of the P-type TFT 311 for pull-up and the N-type TFT 315 for pull-down. A control signal (second gate signal) IN2 different from the control signal IN1 is input to the gate of the pull-down P-type TFT 312 . As will be described later, while the pull-up P-type TFT 311 is ON, the pull-down TFTs 312 and 315 are OFF. Conversely, while pull-down TFTs 312 and 315 are ON, pull-up P-type TFT 311 is OFF.

In the example of FIG. 3A, control signal IN1 and control signal IN2 show opposite time changes. In the example of FIG. 3A, the same control signal IN1 is input. In another configuration example, different control signals indicating the same change transmitted through separate wirings may be input to the gates of the pull-up P-type TFT 311 and the pull-down N-type TFT 315 .

The operation of pulling up the output line 321 to the high potential VH is performed by the pull-up P-type TFT 311 . When the pull-up P-type TFT 311 is ON, the pull-up P-type TFT 311 applies the high potential VH of the high potential line 331 to the output line 321 .

The drive capability of the pull-down P-type TFT 312 is higher than that of the pull-down N-type TFT 315 . The pull-down P-type TFT 312 pulls down the potential of the output line to a potential higher than the low potential VL by a predetermined voltage. The predetermined voltage substantially matches the threshold voltage Vth of the pull-down P-type TFT 312 . That is, the pull-down P-type TFT 312 pulls down the potential of the output line 321 to the potential (VL+Vth). The pull-down N-type TFT 315 continuously pulls down the potential of the output line 321 to the low potential VL.

The oxide semiconductor TFT has a smaller off-leak current than the LTPSTFT. In the configuration shown in FIG. 3A, a pull-down P-type TFT 312 exists between the output line 321 and the low potential line 333 . In other words, there is a leak path passing through the LTPSTFT 312 between the output line 321 and the low potential line 333 . Therefore, it is possible to suppress the occurrence of malfunction and the deterioration of reliability due to the residual charge 341 in the output line 321 during the OFF operation.

Since the pull-down N-type TFT 315 does not require a large driving force, the size of the pull-down N-type TFT 315 can be reduced. For example, the channel width of the N-type TFT 315 for pull-down may be less than the channel width of the P-type TFT 311 for pull-up. The channel widths of the two P-type TFTs 311 and 312 are, for example, the same, and they may have the same structure. In another example, the channel width of the pull-up P-type TFT 311 may be larger than the channel width of the pull-down P-type TFT 312 .

3B and 3C schematically show an example device layout for the CMOS circuit shown in FIG. 3A. In the device layouts shown in FIGS. 3B and 3C, the size (channel width) of the pull-down N-type TFT 315, which is an oxide semiconductor TFT, is smaller than that of the conventional configuration in which the pull-down P-type TFT 312 is not included.

In FIG. 3B, a pull-up P-type TFT 311 and a pull-down P-type TFT 312 have a top gate structure, and a pull-down N-type TFT 315 has a bottom gate structure. Channels of the P-type TFTs 311 and 312 are formed in LTPS films 351 and 352, respectively. A channel of the N-type TFT 315 is formed in the oxide semiconductor film 353 . In the configuration example of FIG. 3B, the channel width of the pull-up P-type TFT 311 is larger than the channel width of the pull-down P-type TFT 312 .

In FIG. 3C, the channels of P-type TFTs 311 and 312 are formed in LTPS films 361 and 362, respectively. A channel of the N-type TFT 315 is formed in the oxide semiconductor film 363 . In the configuration example of FIG. 3C, the channel width of the pull-up P-type TFT 311 may be the same as the channel width of the pull-down P-type TFT 312 .

<Embodiment 2>
A configuration for outputting a gate signal of a P-type TFT in a pixel circuit will be described below. FIG. 4 schematically shows the circuit configuration of a one-stage shift register (also called a flip-flop or shift register unit). The shift register unit shown in FIG. 4 includes the CMOS circuit shown in FIG. 3A. The shift register unit shown in FIG. 4 can be included, for example, in the shift register of the scan driver 132 of an OLED display or the scan driver for the liquid crystal pixel circuit shown in FIG. 2C.

The shift register unit outputs, for example, the gate signal of the P-type TFT 24 shown in FIG. 2A or the P-type TFT 212 shown in FIG. 2C. The shift register unit provides a low potential level output signal pulse to the gate of the P-type TFT 24 or 212 . In the circuit described below, the P-type TFT may be an LTPSTFT, and the N-type TFT may be an oxide semiconductor TFT. The TFT in the shift register unit operates ON/OFF.

Inputs to the shift register unit are the high power supply potential VGH, the low power supply potential VGL, the input signal IN from the previous stage shift register unit, and the clock signals CLK_DRV and CLK_RST that periodically change over time between the high potential and the low potential. . The input signal IN and the clock signals CLK_DRV and CLK_RST switch between a high potential (high level) equal to the high power supply potential VGH and a low potential (low level) equal to the low power supply potential VGL. The output from the output line 321 is a signal to the shift register unit of the next stage.

The shift register unit includes the pull-up P-type TFT 311, the pull-down P-type TFT 312, and the pull-down N-type TFT 315 described with reference to FIG. 3A. The gate of the pull-up P-type TFT 311 and the gate of the pull-down N-type TFT 315 are connected via a node N2. The same potential is applied to these gates. The shift register unit further includes P-type TFTs 411-415.

One of the P-type TFTs 412 and 415 is an example of a first control switch TFT, and the other is an example of a second control switch TFT. The P-type TFT 414 is an example of a third control switch TFT, and the P-type TFT 413 is an example of a fourth control switch TFT.

A constant high power supply potential VGH is applied to one of the source/drain of the pull-up P-type TFT 311 . A clock signal CLK_DRV is applied to one of the source/drain of each of the pull-down TFTs 312 and 315 . As will be described later, when the pull-down TFTs 312 and 315 are ON, the clock signal CLK_DRV is at a low potential level lower than the high power supply potential VGH. Its potential is the same as the low power supply potential VGL.

The gate of the P-type TFT 411 is connected to the output line 321 and they are at the same potential. One source/drain of the P-type TFT 411 is connected to the gate of the pull-up P-type TFT 311 and they are at the same potential. A high power supply potential VGH is applied to the other source/drain of the P-type TFT 411 . High power supply potential VGH is constant. The P-type TFT 411 can prevent the node N2 from floating and the circuit operation from becoming unstable. The P-type TFT 411 may be omitted.

A signal IN is applied to the gate of the P-type TFT 412 . One source/drain of the P-type TFT 412 is connected to the gate of the pull-up P-type TFT 311 and they are at the same potential. A high power supply potential VGH is applied to the other source/drain of the P-type TFT 412 .

The source of the P-type TFT 413 is connected to the gate of the pull-up P-type TFT 311, and they are at the same potential. The gate of the P-type TFT 413 is connected to the drain and is in a diode-connected state. A clock signal CLK_RST is applied to the drain.

The gate of the P-type TFT 414 is connected to the gate of the pull-up P-type TFT 311, and their gate potentials are the same. One source/drain of the P-type TFT 414 is connected to the gate of the pull-down P-type TFT 312 through the node N1, and they are at the same potential. A high power supply potential VGH is applied to the other source/drain of the P-type TFT 414 .

A signal IN is applied to the gate of the P-type TFT 415 . One source/drain of the P-type TFT 415 is connected to the gate of the pull-down P-type TFT 312 through the node N1, and they are at the same potential. A low power supply potential VGL is applied to the other source/drain of the P-type TFT 415 . The low power supply potential VGL is constant.

The operation of the circuit shown in FIG. 4 will be described below. FIG. 5 shows a timing chart of the circuit shown in FIG. In the following, the high potential level of the signal is expressed as H, and the low potential level as L. All signals have a high potential level at the high power supply potential VGH and a low potential level at the low power supply potential VGL. In FIG. 5 all signals are synchronous.

First, the state immediately before time T1 will be described. The input signal IN is H, the clock signal CLK_DRV is H, and the clock signal CLK_RST is L. The potential of the node N1 is H, and the potential of the node N2 is L. P-type TFTs 415 and 412 are OFF. The diode-connected P-type TFT 413 is forward biased. The pull-down P-type TFT 312 is OFF. The pull-down N-type TFT 315 is OFF, and the pull-up P-type TFTs 311 and 414 are ON. The P-type TFT 411 is OFF. The output signal OUT is H.

Next, the operation of the components at time T1 will be described. Input signal IN changes from H to L. Between time T1 and time T2, a transfer pulse (low potential level L in input signal IN) is input from the preceding shift register unit. Also, the clock signal CLK_RST changes from L to H.

In response to the above change in the input signal IN, the P-type TFTs 415 and 412 are turned ON. In response to the change in clock signal CLK_RST, P-type TFT 413 is reverse biased. The potential of the node N1 changes from H to L, and the potential of the node N2 changes from L to H.

Since the potential of the node N1 changes from H to L, the pull-down P-type TFT 312 is turned ON. Since the potential of the node N2 changes from L to H, the pull-down N-type TFT 315 is turned ON. The clock signal CLK_DRV remains H, and the output signal OUT remains H. The output signal OUT remains H, and the P-type TFT 411 remains OFF.

Next, the operation of the components at time T2 will be described. The input signal IN changes from L to H. P-type TFTs 415 and 412 are turned off. The clock signal CLK_RST remains H. The potential of node N1 is L and is in a floating state.

Clock signal CLK_DRV changes from H to L. As a result, the output signal OUT changes from H to L. Furthermore, the P-type TFT 411 is turned ON. The potential of node N2 remains H. During the period from time T2 to time T3, the shift register unit outputs the pulse to be transferred to the control line of the display area 125 and the shift register unit of the next stage.

Next, the operation of the components at time T3 will be described. The input signal IN remains H, and the P-type TFTs 415 and 412 remain OFF. The clock signal CLK_DRV changes from L to H. Also, the clock signal CLK_RST changes from H to L. The P-type TFT 413 is forward biased.

Clock signal CLK_RST is applied to node N2, and the potential of node N2 changes from H to L. The P-type TFT 414 is turned ON, and the potential of the node N1 changes from L to H.

When the potential of the node N2 changes from H to L, the N-type TFT 315 for pull-down is turned OFF and the P-type TFT 311 for pull-up is turned ON. When the potential of the node N1 changes from L to H, the pull-down P-type TFT 312 is turned off. The output signal OUT changes from L to H. The P-type TFT 411 is turned off. The period from time T2 to time T3 is the output period for outputting the signal pulse.

After time T3, clock signals CLK_DRV and CLK_RST change periodically. Since the potential of the node N2 is L, a change in the clock signal CLK_RST does not change the potential of the node N2. The potentials of nodes N1 and N2 are maintained. The TFTs 312 and 315 are OFF, and changes in the clock signal CLK_DRV do not change the potential of the output signal OUT. Thus, the output signal OUT is maintained at H. The node potential in the shift register unit changes according to the next change in the input signal IN.

As described with reference to FIG. 5, the shift register unit operation shown in FIG. 4 does not require bootstrapping. Therefore, the circuit area can be reduced because there is no need to add a capacitance required for bootstrapping.

FIG. 6 shows part of a shift register that can be implemented in scan driver 132 . Specifically, FIG. 6 shows a first-stage shift register unit SR1, a second-stage shift register unit SR2, and a third-stage shift register unit SR3. Each of the shift register units SR1, SR2 and SR3 can have the circuit configuration described with reference to FIGS. Depending on the design, the shift register can be configured in units of n-stage (n is a positive integer) shift registers that are connected.

Each shift register unit includes a plurality of signal terminals. Specifically, they are VGH terminal 611 , IN terminal 612 , VGL terminal 613 , CLK_RST terminal 614 , OUT terminal 615 and CLK_DRV terminal 616 . In FIG. 6, the terminals of the first-stage shift register unit SR1 are indicated by reference numerals as an example.

The OUT terminal 615 outputs the output signal OUT shown in FIG. VGH terminal 611 is supplied with the constant high power supply potential VGH described with reference to FIG. VGL terminal 613 is supplied with the constant low power supply potential VGL described with reference to FIG. A signal from the IN terminal 612 is the input signal IN in FIG. A signal input to the CLK_RST terminal 614 is the clock signal CLK_RST shown in FIG. The signal input to the CLK_DRV terminal 616 is the clock signal CLK_DRV shown in FIG. Some of the input signals to the shift register units are given from driver IC 134 .

Shift register units SR1, SR2 and SR3 output output signals OUT1, OUT2 and OUT3 from OUT terminals 615, respectively. The output signal is applied to the gate of the TFT 24 of the pixel circuit, and further applied to the IN terminal 612 of the next-stage shift register unit. A start signal ST is input to the IN terminal 612 of the first-stage shift register unit SR1.

A clock signal C2 is applied to the CLK_RST terminal 614 of the (3k−2)th stage. k is a positive integer. A clock signal C1 is applied to the CLK_DRV terminal 616 of the (3k−2)th stage. A clock signal C3 is applied to the CLK_RST terminal 614 of the (3k−1)th stage. A clock signal C2 is applied to the CLK_DRV terminal 616 of the (3k−1)th stage. A clock signal C1 is applied to the CLK_RST terminal 614 of the 3kth stage. A clock signal C3 is applied to the CLK_DRV terminal 616 of the 3kth stage.

FIG. 7 shows a timing chart of signals of the shift register shown in FIG. The start signal ST gives a low potential level pulse in one frame period. The clock signals C1, C2 and C3 each give a low potential pulse at a constant cycle within one frame cycle. The pulse widths of the clock signals C1, C2 and C3 are the same, and the pulse width of the start signal ST is also the same.

The periods of the pulses of the clock signals C1, C2 and C3 are the same and their phases are different. The clock signals C1, C2 and C3 are out of phase by one pulse width. That is, the pulse of the clock signal C2 is generated in synchronization with the end of the pulse of the clock signal C1. A pulse of clock signal C3 is generated in time with the end of the pulse of clock signal C2. A pulse of the clock signal C1 is generated coincident with the end of the pulse of the clock signal C3. The start time and end time of each pulse of the start signal ST match the start time and end time of one pulse of the clock signal C3.

FIG. 7 shows temporal changes in the output signals OUT1 to OUTn of each n-stage shift register unit. The output signals OUT1 to OUTn sequentially generate low potential pulses. The pulse widths of the output signals OUT1 to OUTn are the same as the pulse widths of the other signals. The output signal pulse for each shift register unit is generated in accordance with the end of the output signal pulse for the preceding shift register unit.

<Embodiment 3>
A configuration for outputting a gate signal of an N-type TFT in a pixel circuit will be described below. FIG. 8 schematically shows a circuit configuration of a one-stage shift register (also called a flip-flop or shift register unit). The shift register unit shown in FIG. 8 includes the CMOS circuit shown in FIG. 3A. The shift register unit shown in FIG. 8 can be included, for example, in the shift register of the scan driver 131 of an OLED display or the scan driver for the liquid crystal pixel circuit shown in FIG. 2B.

As described with reference to FIG. 2A, the scan driver 131 outputs gate signals for the N-type TFTs 22 in the pixel circuits. The pixel circuit shown in FIG. 2B also includes an N-type TFT 202 as a controlled switch transistor. The shift register unit gives a high potential level output signal pulse to the gate of the N-type TFT 22 or 202 .

In the circuit described below, the P-type TFT may be an LTPSTFT, and the N-type TFT may be an oxide semiconductor TFT. The TFT in the shift register unit operates ON/OFF.

Inputs to the shift register unit are the high power supply potential VGH, the low power supply potential VGL, the input signal IN from the previous stage shift register unit, and the clock signals CLK_DRV and CLK_RST. The input signal IN and the clock signals CLK_DRV and CLK_RST switch between a high potential (high level) equal to the high power supply potential VGH and a low potential (low level) equal to the low power supply potential VGL. The output from the output line 321 is a signal to the shift register unit of the next stage.

The shift register unit includes the pull-up P-type TFT 311, the pull-down P-type TFT 312, and the pull-down N-type TFT 315 described with reference to FIG. 3A. The gate of the pull-up P-type TFT 311 and the gate of the pull-down N-type TFT 315 are connected via a node N4. The same potential is applied to these gates. The shift register unit further includes P-type TFTs 513 and 514 and N-type TFTs 511 , 512 and 515 .

One of the N-type TFTs 512 and 515 is an example of a first control switch TFT, and the other is an example of a second control switch TFT. The P-type TFT 514 is an example of a third control switch TFT, and the P-type TFT 513 is an example of a fourth control switch TFT.

A clock signal CLK_DRV is applied to one of the source/drain of the pull-up P-type TFT 311 . A constant low power supply potential VGL is applied to one of the source/drain of each of the pull-down TFTs 312 and 315 . As will be described later, when the pull-up P-type TFT 311 is ON, the clock signal CLK_DRV is at a high potential level. Its potential is the same as the high power supply potential VGH.

The gate of the N-type TFT 511 is connected to the output line 321 and they are at the same potential. One source/drain of the N-type TFT 511 is connected to the gate of the pull-down P-type TFT 312 via a node N3, and they are at the same potential. A high power supply potential VGH is applied to the other source/drain of the N-type TFT 511 . High power supply potential VGH is constant. The N-type TFT 511 can prevent the node N3 from floating and the circuit operation from becoming unstable. The N-type TFT 511 may be omitted.

A signal IN is applied to the gate of the N-type TFT 512 . One source/drain of the N-type TFT 512 is connected to the gate of the pull-down P-type TFT 312, and they are at the same potential. A high power supply potential VGH is applied to the other source/drain of the N-type TFT 512 .

The source of the P-type TFT 513 is connected to the gate of the pull-down P-type TFT 312, and they are at the same potential. The gate of the P-type TFT 513 is connected to the drain and is in a diode-connected state. A clock signal CLK_RST is applied to the drain.

The gate of the P-type TFT 514 is connected to the gate of the pull-down P-type TFT 312, and their gate potentials are the same. One source/drain of the P-type TFT 514 is connected to the gates of the pull-up P-type TFT 311 and the pull-down N-type TFT 315 through the node N4, and they are at the same potential. A high power supply potential VGH is applied to the other source/drain of the P-type TFT 514 .

A signal IN is applied to the gate of the N-type TFT 515 . One source/drain of the N-type TFT 515 is connected to the gates of the pull-up P-type TFT 311 and the pull-down N-type TFT 315 through a node N4, and they are at the same potential. A low power supply potential VGL is applied to the other source/drain of the N-type TFT 515 . The low power supply potential VGL is constant.

In the circuit of FIG. 8, the potential of the node N3 is the same as the gate potential of the P-type TFT 312 for pull-down. The potential of the node N4 is the same as the gate potential of the P-type TFT 311 for pull-up and the N-type TFT 315 for pull-down.

The operation of the circuit shown in FIG. 8 will be described below. FIG. 9 shows a timing chart of the circuit shown in FIG. In the following, the high potential level of the signal is expressed as H, and the low potential level as L. All signals have a high potential level at the high power supply potential VGH and a low potential level at the low power supply potential VGL. In FIG. 9 all signals are synchronous.

First, the state immediately before time T1 will be described. The input signal IN is L, the clock signal CLK_DRV is H, and the clock signal CLK_RST is L. The potential of the node N3 is L, and the potential of the node N4 is H. N-type TFTs 515 and 512 are OFF. The diode-connected P-type TFT 513 is forward biased. The pull-down P-type TFT 312 is ON. The pull-down N-type TFT 315 is ON, and the pull-up P-type TFTs 311 and 514 are OFF. The N-type TFT 511 is OFF. The output signal OUT is low.

Next, the operation of the components at time T1 will be described. The input signal IN changes from L to H. Between time T1 and time T2, a transfer pulse (high potential level H in input signal IN) is input from the preceding shift register unit. Also, the clock signal CLK_DRV changes from H to L, and the clock signal CLK_RST changes from L to H.

In response to the above change in the input signal IN, the N-type TFTs 515 and 512 are turned ON. In response to the above change in clock signal CLK_RST, P-type TFT 513 is reverse biased. The potential of the node N3 changes from L to H, and the potential of the node N4 changes from H to L. Since the potential of the node N3 changes from L to H, the pull-down P-type TFT 312 is turned off, and the P-type TFT 514 is turned off.

Since the potential of the node N4 changes from H to L, the N-type TFT 315 for pull-down is turned OFF and the P-type TFT 311 for pull-up is turned ON. Since the clock signal CLK_DRV is L, the output signal OUT remains L. The output signal OUT remains L, and the N-type TFT 511 remains OFF.

Next, the operation of the components at time T2 will be described. Input signal IN changes from H to L. The clock signal CLK_RST remains H. The clock signal CLK_DRV changes from L to H.

In response to the change in input signal IN, N-type TFTs 515 and 512 are turned off. The potential of node N3 is maintained at H, and the potential of node N4 is maintained at L. The pull-down TFTs 312 and 315 remain OFF, and the pull-up P-type TFT 311 remains ON.

The clock signal CLK_DRV changes from L to H. As a result, the output signal OUT changes from L to H. Furthermore, the N-type TFT 511 is turned ON. The potential of node N3 remains H. During the period from time T2 to time T3, the shift register unit outputs the pulse to be transferred to the control line of the display area 125 and the shift register unit of the next stage.

Next, the operation of the components at time T3 will be described. The input signal IN remains low. The clock signal CLK_DRV remains H. The clock signal CLK_RST changes from H to L. Since the input signal IN remains L, the N-type TFTs 515 and 512 remain OFF.

The P-type TFT 513 is forward biased in response to the change in the clock signal CLK_RST. Therefore, the clock signal CLK_RST is applied to the node N3, and its potential changes from H to L. The P-type TFT 514 is turned ON, and the potential of the node N4 changes from L to H.

When the potential of the node N4 changes from L to H, the N-type TFT 315 for pull-down is turned ON and the P-type TFT 311 for pull-up is turned OFF. When the potential of the node N3 changes from H to L, the pull-down P-type TFT 312 is turned ON. The output signal OUT changes from H to L. The period from time T2 to time T3 is the output period for outputting the signal pulse.

After time T3, clock signals CLK_DRV and CLK_RST change periodically. The potential of the node N3 is L, and a change in the clock signal CLK_RST does not change the potential of the node N3. Since the N-type TFT 515 is OFF and the P-type TFT 514 is ON, the potential of the node N4 is maintained at H. Thus, the potentials of nodes N3 and N4 are maintained.

The pull-up P-type TFT 311 is OFF, and changes in the clock signal CLK_DRV do not change the potential of the output signal OUT. Therefore, the output signal OUT is maintained at L. The node potential in the shift register unit changes according to the next change in the input signal IN.

As described with reference to FIG. 9, the shift register unit operation shown in FIG. 8 does not require bootstrapping. Therefore, the circuit area can be reduced.

The shift register of the scan driver 131 can have the same configuration as that shown in FIG. The shift register unit has the circuit configuration shown in FIG. 8 and operates according to the signals described with reference to FIG.

FIG. 10 shows a timing chart of signals of the shift register of the scanning driver 131. As shown in FIG. The start signal ST gives a high potential level pulse in one frame period. The clock signals C1, C2 and C3 each give a low potential pulse at a constant cycle within one frame cycle. The pulse widths of the clock signals C1, C2 and C3 are the same, and the pulse width of the start signal ST is also the same.

The periods of the pulses of the clock signals C1, C2 and C3 are the same and their phases are different. The clock signals C1, C2 and C3 are out of phase by one pulse width. That is, the pulse of the clock signal C2 is generated in synchronization with the end of the pulse of the clock signal C1. A pulse of clock signal C3 is generated in time with the end of the pulse of clock signal C2. A pulse of the clock signal C1 is generated coincident with the end of the pulse of the clock signal C3. The start time and end time of each pulse of the start signal ST match the start time and end time of one pulse of the clock signal C3.

FIG. 10 shows temporal changes in the output signals OUT1 to OUTn of each n-stage shift register unit. The output signals OUT1 to OUTn sequentially generate high potential pulses. The pulse widths of the output signals OUT1 to OUTn are the same as the pulse widths of the other signals. The output signal pulse for each shift register unit is generated in accordance with the end of the output signal pulse for the preceding shift register unit.

<Embodiment 4>
FIG. 11 shows another configuration example in shift register units. The shift register unit shown in FIG. 11 can be included, for example, in the scan driver shift register for the scan driver 132 of an OLED display or the liquid crystal pixel circuit shown in FIG. 2C.

The shift register unit outputs, for example, the gate signal of the P-type TFT 24 shown in FIG. 2A or the P-type TFT 212 shown in FIG. 2C. The shift register unit provides a low potential level output signal pulse to the gate of the P-type TFT 24 or 212 . In the circuit described below, the P-type TFT may be an LTPSTFT, and the N-type TFT may be an oxide semiconductor TFT. The TFT in the shift register unit operates ON/OFF.

The inputs to the shift register unit are the high power supply potential VGH, the low power supply potential VGL, the input signal IN1 from the previous stage shift register unit, the input signal IN2 from the next stage shift register unit, and cyclically between the high potential and the low potential. are clock signals CLK_DRV and CLK_RST that change with time. The input signals IN1 and IN2 and the clock signals CLK_DRV and CLK_RST switch between a high potential (high level) equal to the high power supply potential VGH and a low potential (low level) equal to the low power supply potential VGL. The output from the output line 321 is a signal to the previous stage and next stage shift register units.

The shift register unit includes the pull-up P-type TFT 311, the pull-down P-type TFT 312, and the pull-down N-type TFT 315 described with reference to FIG. 3A. The gate of the pull-up P-type TFT 311 and the gate of the pull-down N-type TFT 315 are connected via a node N6. The same potential is applied to these gates. The shift register unit further includes P-type TFTs 552 to 555 and a capacitor 559 . The P-type TFT 554 is an example of a third control switch TFT.

A constant high power supply potential VGH is applied to one of the source/drain of the pull-up P-type TFT 311 . A clock signal CLK_DRV is applied to one of the source/drain of each of the pull-down TFTs 312 and 315 . When the pull-down TFTs 312 and 315 are ON, the clock signal CLK_DRV is at a low potential level lower than the high power supply potential VGH. Its potential is the same as the low power supply potential VGL.

The gate of the P-type TFT 552 is connected to the gate of the pull-down P-type TFT 312, and they are at the same potential. One source/drain of the P-type TFT 552 is connected to the gates of the pull-up P-type TFT 311 and the pull-down N-type TFT 315, and they are at the same potential. A high power supply potential VGH is applied to the other source/drain of the P-type TFT 552 . High power supply potential VGH is constant.

One of the source/drain of the P-type TFT 553 is connected to the gate of the pull-down P-type TFT 312, and they are at the same potential. A signal IN2 is applied to the gate of the P-type TFT 553 . A signal IN2 is an output signal for each shift register of the next stage.

The gate of the P-type TFT 554 is connected to the gate of the pull-up P-type TFT 311, and their gate potentials are the same. One source/drain of the P-type TFT 554 is connected to the gate of the pull-down P-type TFT 312 through the node N5, and they are at the same potential. A high power supply potential VGH is applied to the other source/drain of the P-type TFT 554 . The gates of the P-type TFT 554, the P-type TFT 311, and the N-type TFT 315 are connected to a node N6, and a clock signal CLK_DRV is applied to these through a capacitor 558. FIG.

A signal IN1 is applied to the gate of the P-type TFT 555 . One source/drain of the P-type TFT 555 is connected to the gate of the pull-down P-type TFT 312 through the node N5, and they are at the same potential. A low power supply potential VGL is applied to the other source/drain of the P-type TFT 555 . The low power supply potential VGL is constant.

The operation of the circuit shown in FIG. 11 will be described below. FIG. 12 shows a timing chart of the circuit shown in FIG. In the following, the high potential level of the signal is expressed as H, and the low potential level as L. All signals have a high potential level at the high power supply potential VGH and a low potential level at the low power supply potential VGL. In FIG. 12 all signals are synchronous.

First, the state immediately before time T11 will be described. The input signal IN1 is H, the clock signal CLK_DRV is L, and the input signal IN2 is H. The potential of the node N5 is H, and the potential of the node N6 is L. The pull-down P-type TFT 312 is OFF. P-type TFTs 553 and 555 are OFF. The N-type TFT 315 for pull-down is OFF, and the P-type TFT 311 and P-type TFT 554 for pull-up are ON. The output signal OUT is H.

Next, the operation of the components at time T11 and time T12 immediately after that will be described. The clock signal CLK_DRV changes from L to H at time T11, and the input signal IN1 changes from H to L at time T12 immediately after that. The potential of node N6 changes from L to H in response to the change in clock signal CLK_DRV. The P-type TFT 554 and the pull-up P-type TFT 311 are turned off. The pull-down N-type TFT 315 is turned ON.

In response to the change of the input signal IN1, the P-type TFT 555 is turned ON, and the potential of the node N5 changes from H to L. The P-type TFT 552 is turned ON, and the potential of the node N6 is maintained at H. Also, the pull-down P-type TFT 312 is turned ON. The clock signal CLK_DRV is H, and the output signal OUT remains H.

Next, the operation of the components at time T21 after time T12 and at time T22 immediately thereafter will be described. At time T21, neither signal changes. At time T22, the input signal IN1 changes from L to H, and the clock signal CLK_DRV changes from H to L.

The P-type TFT 555 turns OFF in response to the change in the input signal IN1. The P-type TFT 553 remains OFF. Node N5 is in a floating state and its potential is maintained at L. Therefore, the pull-down P-type TFT 312 remains ON.

Although the clock signal CLK_DRV changes to L as described above, the potential of the node N6 is maintained at H by the capacitor 559 and the ON P-type TFT 552 . Therefore, the P-type TFT 554 and the pull-up P-type TFT 311 remain OFF, and the pull-down N-type TFT 315 remains ON. Since the clock signal CLK_DRV changes from H to L, the output signal OUT changes from H to L.

Next, the operation of the components at time T31 after time T22 and at time T32 immediately thereafter will be described. At time T31, the clock signal CLK_DRV changes from L to H. Output signal OUT changes from L to H in response to the change of clock signal CLK_DRV from L to H.

At time T32, the input signal IN2 changes from H to L. In response to the change of the input signal IN2 from H to L, the P-type TFT 553 is turned ON and the potential of the node N5 changes from L to H. In response to the potential change of the node N5, the P-type TFT 552 is turned off, and the pull-down P-type TFT 312 is turned off.

The node N6 is in a floating state and its potential remains H. Therefore, the pull-up P-type TFT 311 remains OFF, and the pull-down N-type TFT 315 remains ON. Since the clock signal CLK_DRV is H, the output signal OUT is H.

Next, the operation of the components at time T41 after time T32 and at time T42 immediately after that will be described. At time T41, the input signal IN2 changes from L to H. In response to the change of the input signal IN2 from L to H, the P-type TFT 553 is turned off.

Clock signal CLK_DRV changes from H to L at time T42. The change of the clock signal CLK_DRV from H to L causes the potential of the node N6 to change from H to L. In response, the P-type TFT 554 and the pull-up P-type TFT 311 are turned ON, and the pull-down N-type TFT 315 is turned OFF. Since the pull-up P-type TFT 311 is ON and the pull-down TFTs 312 and 315 are OFF, the output OUT remains H.

Next, the operation of the components at time T51 after time T42 and at time T52 immediately thereafter will be described. At time T51, the clock signal CLK_DRV changes from L to H. There is no signal change at time T52.

The potential of the node N6 changes from L to H in response to the change of the clock signal CLK_DRV from L to H. In response to the change of the potential of the node N6 from L to H, the P-type TFT 554 and the pull-up P-type TFT 311 are turned off. Also, the pull-down N-type TFT 315 is turned ON. The pull-down P-type TFT 312 remains OFF. Since the clock signal CLK_DRV is H, the output OUT remains H.

Next, the operation of the components at time T61 after time T52 and at time T62 immediately after that will be described. There is no signal change at time T61. Clock signal CLK_DRV changes from H to L at time T62. Accordingly, the potential of node N6 changes from H to L.

In response to the change of the potential of the node N6 from H to L, the P-type TFT 554 and the pull-up P-type TFT 311 are turned ON. Also, the pull-down N-type TFT 315 is turned off. The pull-down P-type TFT 312 remains OFF. Since the pull-up P-type TFT 311 applies VGH to the output line 312, the output OUT remains H.

After time 62, the operation from time T42 to time T62 is repeated until the next frame. As described above, the P-type TFT 554 and the pull-up P-type TFT 311 are turned ON/OFF between time T42 and time T62. The two P-type TFTs are ON from time T42 to time T51 and OFF from another time T51 to T62 (T42).

If the P-type TFT remains in the ON state, a Vt (threshold) shift may occur due to the Vg+ stress applied. As described above, by turning ON/OFF the two P-type TFTs 554 and 311 in accordance with the clock signal CLK_DRV, the Vg+ stress is alleviated, and the unstable circuit operation due to the Vt shift can be suppressed.

The period from time T11 to T12, the period from time T21 to T22, the period from time T31 to T32, the period from time T41 to T42, the period from time T51 to T52, and the period from time T61 to T62 are: It is a very short period compared to the clock period. The clock cycle is, for example, a period (length) from time T11 to time T31.

In one cycle of clock signal CLK_DRV shown in FIG. 12, the H period is slightly longer than the L period, but the difference is very small, and the duty ratio of clock signal CLK_DRV is substantially 50%. The clock signal CLK_DRV can appropriately generate the output signal OUT and effectively suppress the Vt shift of the TFT.

FIG. 13 shows the configuration of part of a shift register including the shift register units described with reference to FIGS. FIG. 13 shows a first-stage shift register unit SR11, a second-stage shift register unit SR12, and a third-stage shift register unit SR13. Each of the shift register units SR11, SR12 and SR13 can have the circuit configuration described with reference to FIGS. 11 and 12. FIG. Depending on the design, the shift register can be configured in units of n-stage (n is a positive integer) shift registers that are connected.

Each shift register unit includes a plurality of signal terminals. Specifically, they are VGH terminal 631 , IN1 terminal 632 , VGL terminal 633 , OUT terminal 635 , CLK_DRV terminal 636 and IN2 terminal 637 . In FIG. 13, the terminals of the first-stage shift register unit SR11 are indicated by reference numerals as an example.

OUT terminal 635 outputs output signal OUT shown in FIG. A constant high power supply potential VGH is applied to the VGH terminal 631 . A constant low power supply potential VGL is applied to the VGL terminal 633 . A signal from the IN1 terminal 632 is the input signal IN1 in FIG. The signal input to the CLK_DRV terminal 636 is the clock signal CLK_DRV shown in FIG. A signal from the IN2 terminal 637 is the input signal IN2 in FIG. Some of the input signals to the shift register units are given from driver IC 134 .

The shift register units SR11, SR12 and SR13 output output signals OUT11, OUT12 and OUT13 from OUT terminals 635, respectively. The output signal is applied to the gate of the TFT 24 of the pixel circuit, and further applied to the IN1 terminal 632 of the next-stage shift register unit and the IN2 terminal 637 of the previous-stage shift register unit. A start signal ST is input to the IN1 terminal 632 of the first-stage shift register unit SR11.

A clock signal C11 is applied to the CLK_DRV terminal 636 of the (2k−1)th stage, and a clock signal C12 is applied to the CLK_DRV terminal 636 of the 2kth stage. k is a positive integer. Clock signals C11 and C12 respectively show changes corresponding to clock signal CLK_DRV described with reference to FIG. 12 in each shift register unit.

Next, another configuration example for each shift register will be described. FIG. 14 shows a configuration example of each shift register. Differences from the configuration example shown in FIG. 11 will be mainly described below. The shift register unit shown in FIG. 14 includes P-type TFTs 557 and 558 in addition to the configuration example shown in FIG. The gate of the N-type TFT 315 for pull-down is not connected to the gate of the P-type TFT 311 for pull-up. A node N7 is shown on a line connecting the gates of the P-type TFT 554 and the pull-up P-type TFT 311. FIG.

The gate of the P-type TFT 557 is connected to the output line 321 and they are at the same potential. A high power supply potential VGH is applied to one of the source/drain of P-type TFT 557 . The other of the source/drain of the P-type TFT 557 is connected to the gate of the pull-down N-type TFT through a node N8, and they are at the same potential.

A clock signal CLK_RST is applied to the gate of the P-type TFT 558 . A low power supply potential VGL is applied to one of the source/drain of P-type TFT 558 . The other of the source/drain of the P-type TFT 558 is connected to the gate of the pull-down N-type TFT through a node N8, and they are at the same potential.

FIG. 15 shows a timing chart of the circuit shown in FIG. With respect to the timing chart shown in FIG. 12, the time change of the potential of the node N6 is removed, and the time change of the potentials of the clock signal CLK_RST and the nodes N7 and N8 is added.

First, the state immediately before time T11 will be described. The input signal IN1 is H, the clock signal CLK_DRV is L, the clock signal CLK_RST is H, and the input signal IN2 is H. The potential of the node N5 is H, the potential of the node N7 is L, and the potential of the node N8 is L.

The pull-down P-type TFT 312 is OFF. P-type TFTs 553 and 555 are OFF. P-type TFT 558 is OFF. The pull-up P-type TFT 311 and the P-type TFT 554 are ON, and the pull-down N-type TFT 315 is OFF. The output signal OUT is H, and the P-type TFT 557 is OFF.

Next, the operation of the components at time T11 and time T12 immediately after that will be described. Clock signal CLK_DRV changes from L to H at time T11. The potential of node N7 changes from L to H in response to the change in clock signal CLK_DRV. The P-type TFT 554 and the pull-up P-type TFT 311 are turned off.

At time T12, the input signal IN1 changes from H to L, and the clock signal CLK_RST changes from H to L. The P-type TFT 558 turns ON in response to the change in the clock signal CLK_RST. The potential of the node N8 remains L, and the pull-down N-type TFT 315 remains OFF.

In response to the change of the input signal IN1, the P-type TFT 555 is turned ON, and the potential of the node N5 changes from H to L. The pull-down P-type TFT 312 is turned ON. The clock signal CLK_DRV is H, and the output signal OUT remains H.

Next, at time T21 after time T12, the clock signal CLK_RST changes from L to H. The P-type TFT 558 is turned off in response to the change in the clock signal CLK_RST. The potential of the node N8 is maintained at L, and the pull-down N-type TFT 315 remains OFF.

Next, at time T22 immediately after time T21, the input signal IN1 changes from L to H, and the clock signal CLK_DRV changes from H to L. The P-type TFT 555 turns OFF in response to the change in the input signal IN1. The P-type TFT 553 remains OFF. Node N5 is in a floating state and its potential is maintained at L. Therefore, the pull-down P-type TFT 312 remains ON.

Although the clock signal CLK_DRV changes to L as described above, the potential of the node N7 is maintained at H by the capacitor 559 and the P-type TFT 552 which is ON. Therefore, the P-type TFT 554 and the pull-up P-type TFT 311 remain OFF. Since the clock signal CLK_DRV changes from H to L, the output signal OUT changes from H to L. The P-type TFT 557 turns ON, the potential of the node 8 changes from L to H, and the pull-down N-type TFT 315 turns ON.

Next, at time T31 after time T22, the clock signal CLK_DRV changes from L to H. The potential of the node N7 is maintained at H, and the P-type TFT 554 and the pull-up P-type TFT 311 remain OFF. The potential of the node N5 is maintained at L, and the potential of the node N8 is maintained at H. Therefore, the pull-down P-type TFT 312 and the pull-down N-type TFT 315 remain ON.

As the clock signal CLK_DRV changes from L to H, the output signal OUT changes from L to H. In response, P-type TFT 557 turns OFF. The node N8 becomes floating and its potential remains H.

Next, at time T32 immediately after time T31, the input signal IN2 changes from H to L, and the clock signal CLK_RST changes from H to L. In response to the change of the input signal IN2 from H to L, the P-type TFT 553 is turned ON and the potential of the node N5 changes from L to H. In response to the potential change of the node N5, the P-type TFT 552 and the pull-down P-type TFT 312 are turned off.

In response to the clock signal CLK_RST changing from H to L, the P-type TFT 558 is turned ON. The potential of the node N8 changes from H to L, and the pull-down N-type TFT 315 is turned off. The output line 321 is in a floating state, and the output signal OUT is maintained at H.

Next, at time T41 after time T32, the input signal IN2 changes from L to H, and the clock signal CLK_RST changes from L to H. In response to the change of the input signal IN2 from L to H, the P-type TFT 553 is turned off. Node N5 is brought into a floating state and its potential is maintained at H. In response to the clock signal CLK_RST changing from L to H, the P-type TFT 558 is turned OFF. The node N8 becomes floating and its potential is maintained at L.

The clock signal CLK_DRV changes from H to L at time T42 immediately after time T41. The change of the clock signal CLK_DRV from H to L causes the potential of the node N7 to change from H to L. In response, the P-type TFT 554 and the pull-up P-type TFT 311 are turned ON. The potential of node N5 is maintained at H. Node N8 is in a floating state and is kept low. Therefore, the pull-down TFTs 312 and 315 remain OFF. As a result, the output OUT remains H.

Next, at time T51 after time T42, the clock signal CLK_DRV changes from L to H. Accordingly, the potential of node N7 changes from L to H. In response to the change of the potential of the node N7 from L to H, the P-type TFT 554 and the pull-up P-type TFT 311 are turned off. Node N5 is in a floating state and is maintained at H. Node N8 is in a floating state and is kept low. Therefore, the pull-down TFTs 312 and 315 remain OFF. The output line 321 is in a floating state, and the output OUT remains H.

The clock signal CLK_RST changes from H to L at time T52 immediately after time T51. P-type TFT 558 is turned ON. The potential of node N8 is maintained at L. Other TFTs including the pull-down N-type TFT 315 remain OFF. The output line 321 is in a floating state, and the output OUT remains H.

Next, at time T61 after time T52, the clock signal CLK_RST changes from L to H. P-type TFT 558 is turned off. The node N8 is in a floating state and maintained at an L potential. All other TFTs also remain OFF. The output line 321 is in a floating state, and the output OUT remains H.

The clock signal CLK_DRV changes from H to L at time T62 immediately after time T61. Accordingly, the potential of node N7 changes from H to L. In response to the change of the potential of the node N6 from H to L, the P-type TFT 554 and the pull-up P-type TFT 311 are turned ON. Other TFTs remain OFF. The pull-up P-type TFT 311 applies VGH to the output line 312, and the output OUT remains H.

After time 62, the operation from time T42 to time T62 is repeated until the next frame. As described above, the P-type TFT 554 and the pull-up P-type TFT 311 are turned ON/OFF between time T42 and time T62. The two P-type TFTs are ON from time T42 to time T51 and OFF from another time T51 to T62 (T42). By turning ON/OFF the two P-type TFTs 554 and 311 in accordance with the clock signal CLK_DRV, the Vg+ stress is alleviated, and the unstable circuit operation due to the Vt shift can be suppressed.

FIG. 16 shows the configuration of part of a shift register including the shift register units described with reference to FIGS. FIG. 16 shows a first-stage shift register unit SR21, a second-stage shift register unit SR22, and a third-stage shift register unit SR23. Each of the shift register units SR21, SR22, SR23 can have the circuit configuration described with reference to FIGS. 14 and 15. FIG. Depending on the design, the shift register can be configured in units of n-stage (n is a positive integer) shift registers that are connected.

Each shift register unit includes a plurality of signal terminals. Specifically, they are VGH terminal 651 , IN1 terminal 652 , VGL terminal 653 , CLK_RST terminal 654 , OUT terminal 655 , CLK_DRV terminal 656 and IN2 terminal 657 . In FIG. 16, the terminals of the first-stage shift register unit SR21 are indicated by reference numerals as an example.

OUT terminal 655 outputs output signal OUT shown in FIG. A constant high power supply potential VGH is applied to the VGH terminal 651 . A constant low power supply potential VGL is applied to the VGL terminal 653 . A signal from the IN1 terminal 652 is the input signal IN1 in FIG. A signal input to the CLK_RST terminal 654 is the clock signal CLK_RST shown in FIG. The signal input to the CLK_DRV terminal 656 is the clock signal CLK_DRV shown in FIG. A signal from the IN2 terminal 657 is the input signal IN2 in FIG. Some of the input signals to the shift register units are given from driver IC 134 .

The shift register units SR21, SR22 and SR23 output output signals OUT21, OUT22 and OUT23 from OUT terminals 655, respectively. The output signal is applied to the gate of the TFT 24 of the pixel circuit, and further applied to the IN1 terminal 652 of the next-stage shift register unit and the IN2 terminal 657 of the previous-stage shift register unit. A start signal ST is input to the IN1 terminal 652 of the first-stage shift register unit SR21.

A clock signal C21 is applied to the CLK_DRV terminal 656 of the (2k−1)th stage, and a clock signal C22 is applied to the CLK_DRV terminal 656 of the 2kth stage. The clock signal C22 is applied to the CLK_RST terminal 654 of the (2k−1)th stage, and the clock signal C21 is applied to the CLK_RST terminal 654 of the 2kth stage. k is a positive integer. Clock signals C21 and C22 respectively show changes corresponding to clock signal CLK_DRV described with reference to FIG. 15 in each shift register unit.

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above-described embodiments within the scope of the present disclosure. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

10 OLED display device 105 data line 106 scanning line 108 power supply line 109 measurement control line 110 reference voltage supply line 110 reference voltage supply line 125 display area 131, 132 scanning driver 134 driver IC 311 pull Up P-type TFT 312 Pull-down P-type TFT 315 Pull-down N-type TFT 321 Output line 331 High potential line 332 Low potential line 333 Low potential line 341 Residual charge 351, 352, 361, 362 LTPS film, 353, 363 oxide semiconductor film, 611 VGH terminal, 612 IN terminal, 613 VGL terminal, 614 CLK_RST terminal, 615 OUT terminal, 616 CLK_DRV terminal, N1, N2, N3, N4 nodes, SR1-SR3 shift register unit

Claims (13)

A circuit that outputs an output signal from an output line,
a first output signal supply wiring;
a second output signal supply wiring;
an output line;
a first P-type thin film transistor that turns ON/OFF between the first output signal supply wiring and the output line;
an N-type thin film transistor that turns ON/OFF between the second output signal supply wiring and the output line;
a second P-type thin film transistor that turns ON/OFF between the second output signal supply wiring and the output line;
including
While the first P-type thin film transistor is ON, the N-type thin film transistor and the second P-type thin film transistor are OFF, the signal of the first output signal supply wiring is supplied to the output line,
While the N-type thin film transistor and the second P-type thin film transistor are ON, the first P-type thin film transistor is OFF, and the signal of the second output signal supply line is supplied to the output line.
circuit. 2. The circuit of claim 1, wherein
The first P-type thin film transistor and the second P-type thin film transistor are P-type polysilicon thin film transistors,
circuit. 3. The circuit of claim 2, wherein
a first gate signal is input to the gates of the first P-type thin film transistor and the N-type thin film transistor;
A second gate signal indicating a time change opposite to that of the first gate signal is input to the gate of the second P-type thin film transistor.
circuit. 3. A circuit according to claim 1 or 2,
the second P-type thin film transistor sets the potential of the output line to a potential higher than the potential of the second output signal supply line by a predetermined voltage;
The N-type thin film transistor is set to the potential of the second output signal supply wiring from a potential higher than the potential of the second output signal supply wiring by a predetermined voltage,
circuit. a shift register,
comprising a plurality of concatenated shift register units outputting sequential output signals;
Each of the plurality of shift register units includes the circuit of claim 1,
shift register. A shift register according to claim 5,
one of the first output signal supply wiring and the second output signal supply wiring provides a constant potential signal;
the other of the first output signal supply wiring and the second output signal supply wiring provides a signal that periodically changes between a low potential and a high potential;
shift register. A shift register according to claim 5,
Each of the plurality of shift register units,
a first control switch thin film transistor;
a second control switch thin film transistor;
further comprising
the first control switch thin film transistor and the second control switch thin film transistor are of the same conductivity type and are ON/OFF controlled by the same input signal;
one of the first control switch thin film transistor and the second control switch thin film transistor provides a gate signal to the first P-type thin film transistor and the N-type thin film transistor in an ON state;
the other of the first control switch thin film transistor and the second control switch thin film transistor provides a gate signal to the second P-type thin film transistor in an ON state;
shift register. 8. The shift register according to claim 5 or 7,
each of the plurality of shift register units further comprising a third control switch thin film transistor;
a first gate signal is applied to the gates of the first P-type thin film transistor and the N-type thin film transistor;
a second gate signal is applied to the gate of the second P-type thin film transistor;
one of the first gate signal and the second gate signal is applied to the gate of the third control switch thin film transistor;
the third control switch thin film transistor provides the other of the first gate signal and the second gate signal in an ON state;
shift register. 8. The shift register according to claim 5 or 7,
each of the plurality of shift register units further comprising a fourth control switch thin film transistor;
a first gate signal is applied to the gates of the first P-type thin film transistor and the N-type thin film transistor;
a second gate signal is applied to the gate of the second P-type thin film transistor;
the fourth control switch thin film transistor is in a diode-connected state;
a periodically changing signal is input to the drain of the fourth control switch thin film transistor;
the fourth control switch thin film transistor provides one of the first gate signal and the second gate signal in a forward bias state;
shift register. 8. The shift register according to claim 5 or 7,
each of the plurality of shift register units further includes a third control switch thin film transistor and a fourth control switch thin film transistor;
a first gate signal is applied to the gates of the first P-type thin film transistor and the N-type thin film transistor;
a second gate signal is applied to the gate of the second P-type thin film transistor;
one of the first gate signal and the second gate signal is applied to the gate of the third control switch thin film transistor;
the third control switch thin film transistor provides the other of the first gate signal and the second gate signal in an ON state;
the fourth control switch thin film transistor is in a diode-connected state;
a periodically changing signal is input to the drain of the fourth control switch thin film transistor;
the fourth control switch thin film transistor provides one of the first gate signal and the second gate signal in a forward bias state;
shift register. A shift register according to claim 5,
each shift register unit of the plurality of shift register units outputs an L level signal pulse;
the first output signal supply wiring supplies a constant H level signal,
After the output line outputs the L level signal pulse, the first P-type thin film transistor repeats ON/OFF during a predetermined period during which the H level signal is output,
shift register. A shift register according to claim 11, comprising:
the first P-type thin film transistor and the N-type thin film transistor are turned ON/OFF by a clock signal;
the second output signal supply wiring supplies the clock signal;
shift register. A shift register according to claim 11, comprising:
The first P-type thin film transistor is turned ON/OFF by a clock signal,
During the predetermined period, the N-type thin film transistor and the second P-type thin film transistor are OFF.
shift register.

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