JP2022175349A - game machine - Google Patents

Abstract

To secure the capacity of a control area for performing game control processing.SOLUTION: In a game machine of the present invention, a CPU reads a program from a ROM, calls a subroutine on the basis of the program, compares a value of an A-register and a value stored in the address indicated by a predetermined value of a RAM in the subroutine, may return from the subroutine according to the compared result, and multiplies a multiplicand that is varied on the basis of the progress of a game by a multiplier to obtain a ratio related to a game profit. Multiplication is executed by accumulating results of multiplying each of the multiplicand separated in 1-byte units by the multiplier.SELECTED DRAWING: Figure 148

Description

TECHNICAL FIELD The present invention relates to a gaming machine that determines by lottery whether or not to give a game profit to a player.

In general, in a gaming machine (pachinko machine), a game ball is shot toward a game area in a game board by a player's steering wheel operation, and a game ball that has flowed down the game area enters a starting hole. A lottery related to the design is executed. Then, the special symbols are variably displayed on the special symbol display device, and the special symbols determined by the lottery are stopped and displayed to inform the player of the result of the lottery.

At this time, when a specific special symbol indicating a big hit is stopped and displayed on the special symbol display device, a big win game that is more advantageous to the player than a normal game is started. In this big win game, the attacker device opens and closes a predetermined number of times, allowing game balls to enter the big winning opening, so that the player can receive a lot of payout balls.

In such a game machine, it is desired to effectively utilize the limited storage area of the memory in order to enhance the game playability. For example, there is known a technique of associating management values with control information in a data set table to effectively use memory (for example, Patent Literature 1).

JP 2016-214339 A

In a game machine, a program related to game control processing for controlling the progress of a game must be placed in a use area (control area 4.5 kbytes+data area 3.0 kbytes) in the ROM of the main control board.

However, due to the complexity of game information in accordance with the diversity of games, there is a risk that the use area, especially the control area, will be squeezed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gaming machine capable of securing the capacity of a control area for performing game control processing.

In order to solve the above problems, a gaming machine according to the present invention comprises a CPU, a ROM storing a program used by the CPU, and a RAM holding data, on a predetermined board used for progressing a game. , the CPU reads the program from the ROM, calls a subroutine based on the program, and in the subroutine, stores the value of the A register and the value stored in the RAM at the address indicated by the predetermined value. The multiplicand, which varies according to the progress of the game, is multiplied by the multiplier to obtain a ratio relating to the game profit, and the multiplication is separated into 1-byte units. Multiplicand multiplicands are multiplied by multipliers, and the results are multiplied.
In order to solve the above-mentioned problems, another game according to the present invention comprises a CPU, a ROM storing a program used by the CPU, and a RAM holding data on a predetermined board used for progressing the game. In the machine, the CPU reads the program from the ROM, calls a subroutine based on the program, and in the subroutine, the value of the A register and the value stored in the RAM at the address indicated by the predetermined value. and may return from the subroutine according to the result of the comparison, multiplying the multiplicand, which changes based on the progress of the game, by the multiplier to obtain a ratio related to the game profit, and the multiplicand setting register By setting the multiplier in the multiplicand and multiplier setting register, the 16-bit multiplier generates the multiplication result in the multiplication result register after a predetermined time.
In order to solve the above-mentioned problems, another game according to the present invention comprises a CPU, a ROM storing a program used by the CPU, and a RAM holding data on a predetermined board used for progressing the game. In the machine, the CPU reads the program from the ROM, calls a subroutine based on the program, and in the subroutine, the value of the A register and the value stored in the RAM at the address indicated by the predetermined value. and may return from the subroutine according to the result of the comparison, and divides the dividend, which changes based on the progress of the game, by the divisor to obtain a ratio relating to the game profit, and the division is performed by the dividend setting register. By setting the divisor in the dividend and divisor setting register, the 32-bit divider generates the division result in the division result register after a predetermined period of time.
In order to solve the above-mentioned problems, another game according to the present invention comprises a CPU, a ROM storing a program used by the CPU, and a RAM holding data on a predetermined board used for progressing the game. In the machine, the CPU reads the program from the ROM, calls a subroutine based on the program, and in the subroutine, the value of the A register and the value stored in the RAM at the address indicated by the predetermined value. and may return from the subroutine depending on the result of the comparison. Then, the ratio of the multiplicand to the divisor is obtained, and the multiplication is performed by setting the multiplicand in the multiplicand setting register and the multiplier in the multiplier setting register, and after a predetermined time, the multiplication result is generated in the multiplication result register. Executed by a 16-bit multiplier, the maximum value of the multiplication result is 3 bytes or more, and the division is performed by setting the dividend in the dividend setting register and the divisor in the divisor setting register. It is performed by a 32-bit divider that produces the division result in the division result register.
In order to solve the above-mentioned problems, another game according to the present invention comprises a CPU, a ROM storing a program used by the CPU, and a RAM holding data on a predetermined board used for progressing the game. In the machine, the CPU reads the program from the ROM, calls a subroutine based on the program, and in the subroutine, the value of the A register and the value stored in the RAM at the address indicated by the predetermined value. and may return from the subroutine depending on the result of the comparison. Then, the ratio of the multiplicand to the divisor is obtained, and the multiplication is performed by accumulating the results of multiplying each of the multiplicands separated in units of 1 byte by the multiplier, and the maximum value of the multiplicand operation result is 4 bytes. By setting the dividend in the dividend setting register and the divisor in the divisor setting register, the division is executed by a 32-bit divider that generates the division result in the division result register after a predetermined time.

According to the present invention, it is possible to ensure the capacity of the control area for performing the game control process.

FIG. 11 is a perspective view of the gaming machine showing a state in which the door according to the simultaneous turning reference example is opened; It is a front view of the gaming machine according to the simultaneous spinning reference example. It is a figure explaining the 2nd big prize-winning hole based on the simultaneous spinning reference example. FIG. 11 is a block diagram showing the internal configuration of control means for controlling the progress of a game according to the simultaneous spinning reference example; It is an address map of the memory area used by the main CPU according to the simultaneous rotation reference example. It is a diagram for explaining a low-probability jackpot decision random number determination table according to the simultaneous turning reference example. It is a diagram for explaining a high-probability jackpot determination random number determination table according to the simultaneous turning reference example. It is a diagram for explaining a winning symbol random number determination table and a small winning symbol random number determination table according to the simultaneous turning reference example. It is a figure explaining the reach group determination random number determination table based on the simultaneous rotation reference example. It is a figure explaining the reach mode determination random number determination table based on the simultaneous rotation reference example. It is a figure explaining the variation pattern random number determination table based on the simultaneous rotation reference example. FIG. 11 is a diagram for explaining a variable time determination table according to the simultaneous rotation reference example; It is a figure explaining the game state and variation time based on a simultaneous spinning reference example. FIG. 11 is a first diagram for explaining a special electric accessary product operating ramset table according to the simultaneous rotation reference example; It is a second diagram for explaining the special electric accessary product operating ram set table according to the simultaneous rotation reference example. It is a figure explaining the game state setting table based on the simultaneous spinning reference example. It is a figure explaining the hit determination random number determination table based on the simultaneous rotation reference example. (a) is a diagram for explaining a normal symbol fluctuation time data table according to a simultaneous turning reference example, and (b) is a diagram for explaining an opening/closing control pattern table according to a simultaneous turning reference example. It is a figure explaining the transition of the game state according to the original game property based on the simultaneous spinning reference example. FIG. 11 is a diagram illustrating transition of a game state when a game is not properly played according to the simultaneous spinning reference example; It is a figure explaining the gaming machine state flag based on the simultaneous turning reference example. It is the 1st flowchart explaining the CPU initialization process in the main-control board|substrate based on the simultaneous rotation reference example. It is the 2nd flowchart explaining the CPU initialization processing in the main-control board|substrate based on the simultaneous rotation reference example. FIG. 10 is a flowchart for explaining subcommand group set processing in the main control board according to the simultaneous rotation reference example; FIG. FIG. 11 is a flow chart for explaining a power-off saving process in the main control board according to the simultaneous rotation reference example; FIG. It is a flowchart explaining the timer interrupt processing in the main-control board|substrate based on the simultaneous rotation reference example. 10 is a flowchart for explaining setting-related processing in the main control board according to the simultaneous rotation reference example; 10 is a flowchart for explaining switch management processing in the main control board according to the simultaneous rotation reference example; It is a flowchart explaining the gate passage process in the main-control board|substrate based on the simultaneous rotation reference example. FIG. 11 is a flow chart for explaining first starting opening passage processing in the main control board according to the simultaneous rotation reference example; FIG. It is a flowchart explaining the 2nd starting opening passage process in the main-control board|substrate based on the simultaneous rotation reference example. It is a flow chart for explaining a special symbol random number acquisition process in the main control board according to the simultaneous turning reference example. FIG. 11 is a flow chart for explaining effect determination processing at the time of acquisition in the main control board according to the simultaneous turning reference example; FIG. It is a flow chart for explaining the big winning opening passage processing in the main control board according to the simultaneous turning reference example. It is a diagram for explaining a special game management phase and a special electric role product game management phase according to the simultaneous turning reference example. It is a flow chart for explaining a special game management process in the main control board according to the simultaneous spinning reference example. It is a flow chart for explaining a special symbol variation waiting process in the main control board according to the simultaneous turning reference example. It is a flowchart for explaining a special symbol hit determination process in the main control board according to the simultaneous rotation reference example. It is a flow chart for explaining the special symbol variation number determination processing in the main control board according to the simultaneous turning reference example. FIG. 11 is a flowchart for explaining a number cutting management process in the main control board according to the simultaneous rotation reference example; FIG. It is a flow chart for explaining a special symbol variation during processing in the main control board according to the simultaneous turning reference example. It is a flow chart explaining the symbol forced stop processing in the main control board according to the simultaneous rotation reference example. It is a flow chart for explaining a special symbol stop symbol display process in the main control board according to the simultaneous rotation reference example. It is a flow chart for explaining a special electric role product game management process in the main control board according to the simultaneous turning reference example. It is a flow chart for explaining the big winning opening pre-opening processing in the main control board according to the simultaneous turning reference example. FIG. 11 is a flow chart for explaining a big winning opening opening/closing switching process in the main control board according to the simultaneous turning reference example; FIG. It is a flow chart for explaining a large winning opening opening control process in the main control board according to the simultaneous spinning reference example. It is a flow chart for explaining a large winning opening closing effective process in the main control board according to the simultaneous turning reference example. It is a flow chart for explaining a big winning opening end wait process in the main control board according to the simultaneous spinning reference example. It is a diagram for explaining a normal game management phase according to the simultaneous spinning reference example. It is a flow chart for explaining normal game management processing in the main control board according to the simultaneous turning reference example. It is a flow chart for explaining normal symbol variation waiting processing in the main control board according to the simultaneous turning reference example. It is a flow chart for explaining the process during normal symbol fluctuation in the main control board according to the simultaneous rotation reference example. It is a flow chart for explaining normal symbol stop symbol display processing in the main control board according to the simultaneous rotation reference example. It is a flow chart for explaining normal electric accessary prize opening pre-opening processing in the main control board according to the simultaneous turning reference example. It is a flow chart for explaining normal electric accessary prize opening opening and closing switching processing in the main control board according to the simultaneous turning reference example. It is a flow chart for explaining normal electric accessary prize winning opening control processing in the main control board according to the simultaneous turning reference example. It is a flow chart for explaining normal electric accessary prize winning opening closing effective processing in the main control board according to the simultaneous turning reference example. It is a flow chart for explaining normal electric accessory winning opening end wait processing in the main control board according to the simultaneous turning reference example. It is a figure explaining an example of the variation production|presentation of the no reach variation pattern based on the production|presentation reference example. It is a figure explaining an example of the fluctuation production|presentation of the normal reach fluctuation pattern based on the production|presentation reference example. It is a figure explaining an example of the variation production|presentation of the developed reach variation pattern at the time of loss based on the production|presentation reference example. It is a figure explaining an example of the variation production|presentation of the development reach variation pattern at the time of a big hit based on the production|presentation reference example. It is a figure explaining an example of a variable production|presentation in case the ready-to-reach development production|presentation based on a production|presentation reference example is performed twice. It is a figure explaining an example of the fluctuation|variation production|presentation of the pseudo continuous ready-to-reach fluctuation pattern based on the production|presentation reference example. It is a figure explaining the variable production|presentation determination table based on the production|presentation reference example. It is a figure explaining an example of the pending|holding display production|presentation based on the production|presentation reference example. (a) is a diagram for explaining a final pending display pattern determination table according to a reference example of production, and (b) is a diagram for explaining a immediately previous pending display pattern determination table according to a reference example of production. It is a flowchart explaining the sub CPU initialization process in the sub control board which concerns on the production|presentation reference example. It is a flow chart explaining the sub-timer interrupt processing in the sub-control board according to the effect reference example. It is a flow chart explaining the look-ahead designation command reception processing in the sub-control board according to the effect reference example. It is a flow chart explaining the variation command reception processing in the sub-control board according to the effect reference example. 1 is an external view for explaining a schematic mechanical configuration of a slot machine; FIG. FIG. 2 is an external view of the slot machine with the front door opened, for explaining the schematic mechanical configuration of the slot machine; FIG. 10 is a diagram for explaining symbol arrays on reels and activated lines; 1 is a block diagram showing a schematic electrical configuration of a slot machine; FIG. It is an explanatory diagram for explaining a winning combination. It is a figure which shows a prize type lottery table. It is a figure which shows a prize type lottery table. It is an explanatory diagram for explaining the transition of the game state. It is an explanatory view for explaining the transition of the production state. It is a flow chart explaining CPU initialization processing in a main control board. 4 is a flowchart for explaining cold start processing in the main control board; It is a flow chart explaining error stop processing in a main control board. 4 is a flowchart for explaining set value switching processing in a main control board; It is a flow chart explaining initialization start processing in a main control board. It is a flowchart explaining the state return processing in a main control board. It is a flow chart explaining the game start processing in the main control board. It is a flow chart explaining game medal insertion processing in the main control board. It is a flow chart explaining internal lottery processing in a main control board. It is a flow chart explaining the design code setting processing in the main control board. FIG. 10 is a flowchart for explaining processing during rotation of the drum in the main control board; FIG. FIG. 11 is a flow chart for explaining a spinning drum stopping process in a main control board; FIG. It is a flow chart explaining display judging processing in a main control board. It is a flow chart explaining the payout process in the main control board. It is a flow chart explaining the game transition processing in the main control board. FIG. 10 is a flow chart for explaining save processing at power-off in the main control board; FIG. It is a flow chart explaining timer interruption processing in a main control board. FIG. 2 is a diagram for explaining electrical connections around a main CPU; 2 is a block diagram showing the internal configuration of a CPU core; FIG. FIG. 4 is a diagram explaining the configuration of a register; FIG. 4 is an explanatory diagram showing a memory map; It is an explanatory view showing the appearance of a main control board. It is an explanatory view for explaining a display mode of a ratio display part. FIG. 10 is a flowchart showing a first calculation example of a role product ratio; FIG. FIG. 11 is an explanatory diagram for explaining a first operation example using only an 8-bit MUL instruction; FIG. 10 is a flow chart showing specific processing for realizing the first calculation example; FIG. FIG. 10 is a diagram showing an example of a specific command for implementing the first calculation example; FIG. FIG. 11 is an explanatory diagram for explaining a second example of computation using a 16-bit multiplier; FIG. 11 is a flow chart showing specific processing for realizing the second example of computation; FIG. FIG. 10 is a diagram showing an example of specific commands for realizing the second example of computation; FIG. 10 is a diagram showing an example of a specific command for implementing the first calculation example; FIG. FIG. 11 is an explanatory diagram for explaining a third calculation example using repeated subtraction of a number multiplied by a power of 2; FIG. 11 is a flow chart showing specific processing for realizing the third example of calculation; FIG. FIG. 11 is a diagram showing an example of specific commands for realizing the third example of calculation; FIG. 11 is a flow chart showing specific processing for realizing the fourth example of calculation; FIG. FIG. 12 is a diagram showing an example of specific commands for realizing the fourth example of computation; FIG. 14 is a flowchart showing specific processing for realizing the fifth example of calculation; FIG. FIG. 12 is a diagram showing an example of specific commands for realizing the fifth example of calculation; FIG. 13 is a flow chart showing specific processing for realizing the sixth calculation example; FIG. FIG. 13 is a diagram showing an example of specific commands for realizing the sixth example of calculation; 4 is a flow chart showing specific processing of the BYTESEL module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a BYTESEL module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a BYTESEL module; FIG. FIG. 10 is an explanatory diagram for explaining another example of commands for realizing the BYTESEL module; FIG. 11 is an explanatory diagram for explaining still another example of commands for realizing the BYTESEL module; 4 is a flow chart showing specific processing of the WORDSEL module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a WORDSEL module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a WORDSEL module; FIG. FIG. 11 is an explanatory diagram for explaining another example of commands for realizing the WORDSEL module; FIG. 12 is an explanatory diagram for explaining still another example of commands for realizing the WORDSEL module; FIG. 4 is an explanatory diagram for explaining a CAL_MOD module; FIG. 4 is an explanatory diagram for explaining the HID_JUG module; 4 is a flow chart showing specific processing of a RAMSET module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a RAMSET module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a RAMSET module; FIG. FIG. 11 is an explanatory diagram for explaining another example of commands for realizing the RAMSET module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a TABLESET module; FIG. FIG. 11 is an explanatory diagram for explaining another example of commands for realizing the TABLESET module; 4 is a flow chart showing specific processing of the BYTEDEC module; FIG. 10 is an explanatory diagram for explaining a decrement mode and setting of a zero flag and a carry flag in the BYTEDEC module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a BYTEDEC module; FIG. FIG. 10 is an explanatory diagram for explaining another example of commands for realizing the BYTEDEC module; FIG. 4 is an explanatory diagram for explaining a RAM_DEC module; 4 is a flow chart showing specific processing of the WORDDEC module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a WORDDEC module; FIG. FIG. 10 is an explanatory diagram for explaining another example of commands for realizing the WORDDEC module; FIG. 11 is an explanatory diagram for explaining an example of processing for returning from a subroutine; FIG. 4 is an explanatory diagram for explaining a PY_CMDA module; FIG. 4 is an explanatory diagram for explaining a GAT_PAS module; FIG. 4 is an explanatory diagram for explaining a TDN_PAS module; FIG. 4 is an explanatory diagram for explaining an FD_OPN module; FIG. 4 is an explanatory diagram for explaining a TZ_STA module; FIG. 4 is an explanatory diagram for explaining a TZ_RGET module; It is an explanatory view for explaining a TRSVSEL module. FIG. 4 is an explanatory diagram for explaining a TDOVCHK module; FIG. 4 is an explanatory diagram for explaining a BER_CHK module; FIG. 4 is an explanatory diagram for explaining a TEF_SEL module; FIG. 4 is an explanatory diagram for explaining a SET_RIG module; FIG. 4 is an explanatory diagram for explaining a PRE_LOT module; FIG. 4 is an explanatory diagram for explaining a REG_LOT module; FIG. 4 is an explanatory diagram for explaining a BIG_SLT module; FIG. 4 is an explanatory diagram for explaining a NAV_SET module; 4 is a flowchart showing specific processing of the TOK_PRC module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a TOK_PRC module; FIG. 4 is a flow chart showing specific processing of the TEF_SEL module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a TEF_SEL module; FIG. 4 is a flowchart showing specific processing of the SWI_PRC module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a SWI_PRC module; FIG. 4 is a flowchart showing specific processing of a CPUINIT module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a CPUINIT module; FIG. FIG. 4 is an explanatory diagram for explaining a TMR_IPT module; 4 is a flow chart showing specific processing of the FZ_SPN module; FIG. 10 is an explanatory diagram for explaining an example of a command for realizing an FZ_SPN module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a CPUINIT module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an EXE_SET module; FIG. 4 is a flow chart showing specific processing of the HPT_GRP module; (a) and (b) are explanatory diagrams for explaining an example of commands for realizing the HPT_GRP module, and (c) is an explanatory diagram for explaining an example of a reach group determination random number determination table. be. FIG. 4 is an explanatory diagram for explaining an E_ILGER module; FIG. 4 is an explanatory diagram for explaining an E_LEVOT module; 4 is a flowchart showing specific processing of an SBC_OUT module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an SBC_OUT module; FIG. FIG. 11 is an explanatory diagram for explaining an example of another command for realizing the SBC_OUT module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an FZ_OPN module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a TD_OPN module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an HSY_PRC module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an FDN_CHK module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an FZ_STP module; FIG. 3 is a block diagram for explaining the configuration of a random number generator; FIG. It is a figure explaining the combination of a random number generation part. 4 is a flowchart showing specific processing of an SMC_ROT module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an SMC_ROT module; FIG. FIG. 11 is an explanatory diagram for explaining another example of commands for realizing the SMC_ROT module; 4 is a flowchart showing specific processing of an INITIAL module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an INITIAL module; FIG. FIG. 11 is an explanatory diagram for explaining another example of commands for realizing an INITIAL module; FIG. 4 is an explanatory diagram for explaining a RANKSET module; FIG. 4 is an explanatory diagram for explaining a PWRFAIL module; FIG. 4 is an explanatory diagram for explaining a DYM_OUT module; 4 is a flowchart showing specific processing of an IPT_PD module; FIG. 10 is an explanatory diagram for explaining an example of a command for realizing an IPT_PD module; FIG. FIG. 11 is an explanatory diagram for explaining another example of commands for realizing the IPT_PD module; It is an explanatory view for explaining a DYNMOUT module. FIG. 4 is an explanatory diagram for explaining an EXT_PRC module; 4 is a flow chart showing specific processing of a STOPDCT module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a STOPDCT module; FIG. 10 is an explanatory diagram for explaining another example of a command for realizing the STOPDCT module; 10 is a flow chart showing specific processing of the E_SETTM module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an E_SETTM module; FIG. FIG. 11 is an explanatory diagram for explaining another example of commands for realizing the E_SETTM module; FIG. 4 is an explanatory diagram for explaining a DYM_OUT module; FIG. 4 is an explanatory diagram for explaining a DYM_OUT module; 10 is a flow chart showing specific processing of the E_SETTM module; FIG. 11 is an explanatory diagram for explaining still another example of commands for realizing the E_SETTM module; 4 is a flowchart showing specific processing of a RAM_INC module; FIG. 10 is an explanatory diagram for explaining an example of a command for realizing a RAM_INC module; FIG. FIG. 10 is an explanatory diagram for explaining an example of a command for realizing a RAM_INC module; FIG. FIG. 11 is an explanatory diagram for explaining another example of commands for realizing the RAM_INC module; FIG. 11 is an explanatory diagram for explaining another example of commands for realizing the RAM_INC module; 4 is a flow chart showing specific processing of the TABLESET module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a TABLESET module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a TABLESET module; FIG. FIG. 11 is an explanatory diagram for explaining another example of commands for realizing the TABLESET module; 4 is a flow chart showing specific processing of an IPT_PC module; FIG. 10 is an explanatory diagram for explaining an example of a command for realizing an IPT_PC module; FIG. 4 is a flow chart showing specific processing of a CMDPROC module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a CMDPROC module; FIG. 4 is a flowchart showing specific processing of a SET_PLS module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a SET_PLS module; FIG. 4 is a flowchart showing specific processing of an OTM_ATK module; FIG. 4 is an explanatory diagram for explaining an example of a command for realizing an OTM_ATK module; FIG. FIG. 4 is an explanatory diagram for explaining an example of a command for realizing a KRS_JDG module; FIG. FIG. 10 is an explanatory diagram for explaining another example of commands for realizing the KRS_JDG module; FIG. 10 is a diagram showing an example of a command for setting a value in the Q' register; FIG. 10 is a diagram showing an example of a command for setting a value in the Q' register; FIG. 10 is a diagram showing an example of a command for setting a value in the Q' register; FIG. 10 is a diagram showing an example of a command for setting a value in the Q' register; FIG. 4 is a diagram for explaining transitions of register banks and register groups; FIG. FIG. 2 is an explanatory diagram for explaining usage modes of access methods; 9 is a flowchart for explaining an example of subcommand transmission processing; FIG. 10 is a diagram showing an example of specific commands for realizing subcommand transmission processing; FIG. 10 is a diagram showing an example of another command for realizing subcommand transmission processing; FIG. 4 is a diagram showing part of a command group for implementing CPU initialization processing; FIG. 10 is a diagram showing a table referred to in CPU initialization processing; FIG. 10 is a diagram showing another example of part of a command group for implementing CPU initialization processing; FIG. 10 is a diagram showing another example of a table referred to in CPU initialization processing; FIG. 10 is a diagram showing another example of part of a command group for implementing CPU initialization processing; FIG. 4 is an explanatory diagram showing addresses of output ports; FIG. 10 is a diagram showing a part of a command group for realizing save processing at power-off; FIG. 11 is a diagram showing another example of a part of a command group for realizing save processing at power-off;

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in these embodiments are merely examples for facilitating understanding of the invention, and do not limit the invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are given the same reference numerals to omit redundant description, and elements that are not directly related to the present invention are omitted from the drawings. do.

In the embodiment of the present invention, a pachinko machine and a slot machine will be exemplified in that order as gaming machines, and then specific processing will be described in detail.

<Pachinko machine>
In order to facilitate understanding of the embodiments of the present invention, first, as a reference example of simultaneous rotation, the mechanical configuration and electrical configuration of a so-called simultaneous rotation machine, and specific processing for each substrate will be described. Then, as an effect reference example, a specific effect that can be executed in the simultaneous spinning machine and a specific process related to the effect will be described. After that, as examples of the present invention, configurations different from each reference example will be specifically described.

<Simultaneous rotation reference example>
FIG. 1 is a perspective view of a gaming machine 100 according to a simultaneous turning reference example, showing a state in which the door is opened. As shown, the game machine 100 includes an outer frame 102 in which a space is formed by four sides assembled in a substantially rectangular shape, a middle frame 104 attached to the outer frame 102 by a hinge mechanism so as to be freely opened and closed, and the A front frame 106 attached to the middle frame 104 by a hinge mechanism so as to be openable and closable is provided.

Similarly to the outer frame 102, the middle frame 104 has a surrounding space formed by four sides assembled in a substantially rectangular shape, and a game board 108 is held in this surrounding space. Further, the front frame 106 holds a transmission plate 110 made of glass or resin. When the middle frame 104 and the front frame 106 are closed with respect to the outer frame 102, the game board 108 and the transmission plate 110 face each other substantially parallel to each other while maintaining a predetermined distance. , the game board 108 becomes visible through the transparent plate 110 .

FIG. 2 is a front view of the gaming machine 100 according to the simultaneous spinning reference example. As shown in this figure, an operation handle 112 projecting toward the front side of the gaming machine 100 is provided at the lower portion of the front frame 106 . The operating handle 112 is provided so that the player can rotate it, and when the player rotates the operating handle 112 to perform a shooting operation, the strength corresponding to the rotation angle of the operating handle 112 is applied (not shown). A game ball is shot by the shooting mechanism. The game ball shot in this manner rises between rails 114 a and 114 b provided on the game board 108 and is guided to the game area 116 .

The game area 116 is a space formed between the game board 108 and the transmission plate 110, and is an area in which game balls can flow down or roll. A large number of nails and pinwheels (not shown) are provided on the game board 108, and a game ball guided to the game area 116 collides with the nails and pinwheels to flow down and roll in irregular directions. I have to.

The game area 116 is provided with a first game area 116a and a second game area 116b in which the degree of penetration of the game ball is different from each other according to the firing intensity of the shooting mechanism, and the game ball can be hit separately. The first game area 116a is located on the left side of the game area 116 when viewed from the player facing the gaming machine 100, and the second game area 116b is located on the left side of the game area 116 when viewed from the player facing the gaming machine 100. located on the right side of the Since the rails 114a and 114b are located on the left side of the game area 116, the game ball fired by the shooting mechanism with a shooting intensity lower than a predetermined intensity enters the first game area 116a and is shot with a shooting intensity equal to or higher than the predetermined intensity. The played game ball enters the second game area 116b.

In addition, the game area 116 is provided with a general winning opening 118 into which a game ball can enter, a first fixed starting opening 120A, a first variable starting opening 120B, a second starting opening 122, and a normal figure operating opening 125. , These general winning opening 118, the first fixed starting opening 120A, the first variable starting opening 120B, the second starting opening 122, when the game ball enters the normal figure operation opening 125, predetermined prize balls are paid out to the player respectively. be In addition, below, 120 A of 1st fixed starting openings and the 1st variable starting opening 120B are generically called the 1st starting opening 120. As shown in FIG.

Although details will be described later, a first start-up region is provided within the first start-up port 120 and a second start-up region is provided within the second start-up port 122 . Then, when the game ball enters the first start port 120 or the second start port 122 and enters the first start area or the second start area, one of a plurality of special symbols provided in advance is selected. A lottery is held to determine 1 special symbol. Each special symbol is associated with whether or not it is possible to execute a big winning game or a small winning game that is advantageous to the player. Therefore, when a game ball enters the first start hole 120 or the second start hole 122, the player can obtain a predetermined prize ball and at the same time obtain an opportunity to obtain rights to receive various game benefits. becomes.

In addition, the first fixed starting opening 120A, the second starting opening 122 and the normal figure operating opening 125 are constituted by fixed starting openings that are open so that the game ball can be entered at all times. On the other hand, the first variable starting port 120B is provided with a movable piece 120b that can be opened and closed, and the ease with which a game ball enters the first variable starting port 120B changes according to the state of the movable piece 120b. It consists of a variable starting port. Specifically, the movable piece 120b is normally maintained in a closed state, and during this time, it becomes difficult or impossible for the game ball to enter the first variable starting port 120B.

On the other hand, when the game ball passes through the gate 124 provided in the game area 116 (second game area 116b) or the game ball enters the normal pattern operation port 125, the lottery of the normal symbol described later is performed. If a winning lottery is won by this lottery, the movable piece 120b is controlled to be open for a predetermined period of time. When the movable piece 120b is in an open state, it becomes possible to enter the game ball into the first variable starting port 120B. In this way, the movable piece 120b is in an open state that allows the game ball to enter the first variable starting port 120B, and makes it more difficult for the game ball to enter the first variable starting port 120B than in the open state. Alternatively, it functions as a movable member (start variable winning device) that shifts to an impossible closed state.

In addition, the first fixed starting port 120A can enter only the game ball that flows down the first game area 116a, and the first variable starting port 120B and the second starting port 122 are the games that flow down the second game region 116b. It is arranged in a position where only the ball can enter. In addition, the game ball flowing down the second game area 116b may enter the first fixed starting port 120A, but in this case, the game ball flowing down the first game area 116a is the second It is desirable to arrange the game area 116b at a position where it is easier to enter the game ball than the game ball flowing down.

Similarly, the first variable starting port 120B and the second starting port 122 may enter the game ball that flows down the first game area 116a, but in this case, the game that flows down the second game area 116b It is desirable that the ball be arranged at a position where it is easier to enter than the game ball flowing down the first game area 116a. In any case, the first fixed starting port 120A is arranged at a position where at least the game ball flowing down the first game area 116a can enter, and the first variable starting port 120B and the second starting port 122 are at least the first It is preferable that the game ball flowing down the second game area 116b is arranged at a position where it can enter.

Further, a first big winning opening 126 and a second big winning opening 128 are provided in the second game area 116b. The first big winning hole 126 and the second big winning hole 128 are arranged at positions where only game balls flowing down the second game area 116b can enter. However, the first big winning hole 126 and the second big winning hole 128 may be arranged so that any game ball flowing down the first game area 116a and the second game area 116b can enter.

An opening/closing door 126b is provided in the first big winning hole 126 so that it can be opened and closed. Ball is not possible. Specifically, when the opening/closing door 126b is in a closed state, it is flush with the board surface of the game board 108, and the game balls flow down in front of the first big winning hole 126. As shown in FIG. On the other hand, when the above-mentioned big win game is executed, the opening and closing door 126b is opened and functions as a tray for guiding the game ball to the first big winning hole 126, and the game ball enters the first big winning hole 126. ball becomes possible. When a game ball enters the first big winning hole 126, a predetermined prize ball is paid out to the player.

The second big winning hole 128 is provided below the first big winning hole 126 in the second game area 116b. The second big prize winning opening 128 has a movable piece 128b, and normally the movable piece 128b is maintained in a closed state. On the other hand, when a small winning game, which will be described later, is executed, the movable piece 128b is controlled to be in an open state, and a game ball can enter the second big winning hole 128. As shown in FIG. In addition, hereinafter, the first big prize opening 126 and the second big prize opening 128 are collectively referred to simply as the big prize opening.

FIG. 3 is a diagram for explaining the second big winning opening 128 according to the simultaneous spinning reference example. A structure 129 projecting to the front side of the game board 108 is provided in the second game area 116b. The structure 129 surrounds the gaming machine 100 on four sides positioned in the left-right direction and the front-rear direction and the bottom side, and an opening is formed at the top. An opening formed in the upper part of this structure 129 serves as the second prize winning opening 128 . A movable piece 128b is provided on the upper part of the structure 129, and normally, as shown in FIG. .

The movable piece 128b faces above the game machine 100 and protrudes into the game area 116 where the game ball rolls and flows down. Therefore, when the movable piece 128b is maintained in the closed state, the game ball flowing down the game area 116 (second game area 116b) falls on the movable piece 128b. Here, the base of the structure 129 is substantially parallel to the horizontal direction, and the right side of the gaming machine 100 is slightly longer in the height direction than the left side. Therefore, the left side of the gaming machine 100 is slightly lower than the right side of the second big winning opening 128, and the movable piece 128b maintained in the closed state is positioned so that the left side of the gaming machine 100 is slightly lower than the right side. inclined to Therefore, when the movable piece 128b is in the closed state, as indicated by the arrow in FIG. will move.

Then, when a small winning game, which will be described later, is executed, the movable piece 128b shifts to an open state in which the second big winning opening 128 is opened. Here, as shown in FIG. 3(b), the movable piece 128b slides toward the back side of the game board 108 to change from the closed state to the open state. As a result, when the closed state is changed to the open state, the game ball rolling on the movable piece 128b falls into the second big winning hole 128 by its own weight.

Thus, in the simultaneous rotation reference example, the movable piece 128b is slightly inclined to ensure a long time for the game ball to roll on the movable piece 128b. Then, the game ball rolling on the movable piece 128b is guided into the second big winning hole 128 by changing the movable piece 128b from the closed state to the open state. With the above configuration, even if the time for keeping the movable piece 128b in the open state is set slightly, a predetermined number of game balls can be guided into the second big winning hole 128. FIG. In other words, the time for which the movable piece 128b is kept open, which is required for entering a predetermined number of game balls into the second big winning hole 128, can be shortened. A hole communicating with the back side of the game board 108 is formed in the back side of the structure 129, and the game ball entering the second big winning hole 128 is discharged to the back side of the game board 108. . Then, when a game ball enters the second big winning hole 128, a predetermined prize ball is paid out to the player.

Although the configuration of the second big winning opening 128 has been described here, the first variable starting opening 120B also has the same configuration as the second big winning opening 128 . That is, the movable piece 120b of the first variable starting port 120B projects toward the front side of the game board 108 in the closed state, and the game ball rolls on the movable piece 120b. In the open state of the movable piece 120b, the movable piece 120b slides to the back side of the game board 108, allowing the game ball to enter the first variable starting port 120B. However, as shown in FIG. 2, the right side of the movable piece 128b is higher than the left side when the game machine 100 is viewed from the front, while the left side of the movable piece 120b is the right side when the game machine 100 is viewed from the front. located higher than

Here, the board configuration of the second game area 116b will be described in detail. In the simultaneous turning reference example, the second starting port 122 and the gate 124 are arranged in parallel at the top of the second game area 116b. All the game balls guided to the second game area 116b enter the second starting port 122 or pass through the gate 124 and flow downward. In the simultaneous spinning reference example, the second starting port 122 pays out one game ball as a prize ball for one game ball entering.

When a game ball enters the second starting port 122, one game ball is paid out as a prize ball, and a lottery is performed to determine whether or not a big winning game or a small winning game is executed. Further, when the game ball passes through the gate 124, a lottery is performed to determine whether or not the first variable starting port 120B (movable piece 120b) is to be opened.

A first big winning opening 126 is provided directly below the second starting opening 122 and the gate 124 . When the first big winning hole 126 is in the open state, all the game balls that have flowed down through the gate 124 are arranged to enter the first big winning hole 126 . In the simultaneous spinning reference example, the first big winning opening 126 is opened only in the big win game. In other words, the first big winning hole 126 can be said to be a big winning hole dedicated to big role games. When a game ball enters the first big winning hole 126 during a big win game, a predetermined number of two or more (here, 15) game balls are paid out as prize balls for one game ball entering. .

A first variable starting opening 120B is provided below the first big winning opening 126 . In addition, an out port 131 is provided between the first big winning port 126 and the first variable starting port 120B. The out port 131 is an entrance of a passage for discharging game balls from the game area 116, and even if a game ball enters the out port 131, prize balls are not paid out.

Nails are arranged in the second game area 116b so that most of the game balls (for example, 90% or more) that have flowed downward from the first big winning hole 126 fall onto the movable piece 120b. In addition, a portion (eg, 1% to 10%) of the game balls that have flowed downward from the first big winning hole 126 are guided to the out hole 131 by these nails.

In the closed state of the first variable starting port 120B, the game ball rolls on the movable piece 120b. When the movable piece 120b is opened while the game ball is rolling on the movable piece 120b, all the game balls on the movable piece 120b are guided into the first variable starting port 120B. When a game ball enters the first variable starting port 120B, one game ball is paid out as a prize ball for one game ball entering, and whether or not to execute a big win game or a small win game is determined. A lottery will be held.

A game ball that does not enter the first variable starter opening 120B falls from the movable piece 120b to the right side of the game machine 100 when viewed from the front. Below the first variable starter opening 120B, a second large winning opening 128 is provided, and most of the game balls dropped from the movable piece 120b roll on the movable piece 128b of the second large winning opening 128. do. The game ball on the movable piece 128b rolls slowly from the right side to the left side in the front view of the gaming machine 100 due to the inclination of the movable piece 128b.

Although details will be described later, in the simultaneous spinning reference example, the second big winning opening 128 is opened only in the small winning game. That is, the second big winning hole 128 can be said to be a big winning hole dedicated to small winning games. When the movable piece 128b is opened while the game ball is rolling on the movable piece 128b, all the game balls on the movable piece 128b are guided into the second big winning opening 128.例文帳に追加When a game ball enters the second big winning hole 128 during a small winning game, a predetermined number of two or more (here, 15) game balls are paid out as prize balls for one game ball entering. be

A normal figure operation opening 125 is provided at the lower left of the second big winning opening 128 . Here, a nail is arranged in the second game area 116b so that almost all of the game balls dropped downward from the second big winning hole 128 enter the normal figure operation hole 125.例文帳に追加In the simultaneous turning reference example, the normal figure operation opening 125 constitutes a "specific winning opening" in which one game ball is paid out as a prize ball for one game ball entry. In addition, when the game ball enters the normal figure operation port 125, similarly to the case where the game ball passes through the gate 124, it is determined whether the first variable start port 120B (movable piece 120b) is opened. A lottery will be held.

In addition, at the bottom of the game area 116, a game ball that did not enter any of the general winning opening 118, the first starting opening 120, the second starting opening 122, the normal drawing opening 125, and the big winning opening is provided from the game area 116 to the back side of the game board 108.

The game machine 100 includes a performance display device 200 made of a liquid crystal display device, a performance accessory device 202 made of a movable device, and various lighting modes and light emission colors as performance devices for performing performance during the progress of the game. An effect lighting device 204 made up of a lamp, a sound output device 206 made up of a speaker, and an effect operation device 208 that accepts the player's operation are provided.

The effect display device 200 includes a main effect display portion 200a consisting of an image display portion for displaying an image. placed as possible. In the main effect display section 200a, as shown in the figure, various effects such as three effect patterns 210a, 210b, and 210c are variably displayed.

The effect accessory device 202 is arranged in front of the main effect display unit 200a, and is usually retracted at the origin position on the back side of the game board 108 in a state of being divided into a plurality of constituent members. It is no longer visible. During the variable display of the performance patterns 210a, 210b, and 210c, when each constituent member moves to a movable position in front of the main effect display section 200a by driving the actuator, the front surface of the main effect display section 200a Each constituent member is united to give the player a feeling of anticipation of a big win.

The effect lighting device 204 is provided in the effect accessory device 202, the game board 108, etc., and is variously controlled to be lit according to the image displayed on the main effect display section 200a.

The audio output device 206 is provided at an upper position of the front frame 106 or a lowermost position of the outer frame 102, and outputs various sounds toward the front side of the gaming machine 100 according to the image displayed on the main effect display section 200a. Output audio.

The effect operation device 208 is composed of a button that receives a player's pressing operation, and is provided at a substantially central position in the width direction of the gaming machine 100 and at a position lower than the transmission plate 110 . This effect operation device 208 is activated in accordance with the image displayed on the main effect display section 200a, and when the player's operation is received within the operation effective time, various operations are performed according to the operation. A performance is performed.

In the figure, reference numeral 132 denotes an upper plate into which prize balls paid out from the gaming machine 100 and game balls rented from the game ball lending device are guided. It will be guided to the lower plate 134 . Also, the bottom surface of the lower tray 134 is formed with a ball removal hole (not shown) for ejecting game balls from the lower tray 134 . This ball extraction hole is normally closed by an opening/closing plate (not shown), but when the ball removal knob 134a is pressed down, the opening/closing plate slides together with the ball removal knob 134a to open the ball removal hole. It is possible to discharge the game ball from the lower tray 134 from the bottom.

In addition, on the game board 108, a first special symbol display device 160, a second special symbol display device 162, a first special symbol holding device, and a first special symbol display device 160, a second special symbol display device 162, and a first special symbol reserve are provided outside the game area 116 and at positions visible to the player. A display device 164, a second special symbol reservation display device 166, a normal symbol display device 168, a normal symbol reservation display device 170, and a right-handed information display device 172 are provided. Each of these displays 160 to 172 is a device for displaying various situations relating to the game, and the details thereof will be described later.

(Internal configuration of control means)
FIG. 4 is a block diagram showing the internal configuration of control means for controlling the progress of a game according to the simultaneous spinning reference example.

The main control board 300 controls the basic operations of the game. The main control board 300 includes a main CPU 300a, a main ROM 300b, and a main RAM 300c. The main CPU 300a reads the program stored in the main ROM 300b based on the input signals from the detection switches and timers and performs arithmetic processing, and directly controls each device and display, or the result of the arithmetic processing. Send commands to other boards accordingly. The main RAM 300c functions as a data work area during arithmetic processing of the main CPU 300a.

The main control board 300 includes a general winning opening detection switch 118s for detecting that a game ball has entered the general winning opening 118, and a first fixed opening for detecting that a game ball has entered the first fixed starting opening 120A. A starting port detection switch 120As, a first variable starting port detection switch 120Bs that detects that a game ball has entered the first variable starting port 120B, and a second variable starting port that detects that a game ball has entered the second starting port 122. A start opening detection switch 122s, a gate detection switch 124s that detects that a game ball has passed through the gate 124, a normal diagram operation opening detection switch 125s that detects that a game ball has entered the normal diagram operation opening 125, a first large A first big winning hole detection switch 126s for detecting that a game ball has entered the winning hole 126 and a second big winning hole detection switch 128s for detecting that a game ball has entered the second big winning hole 128 are connected. A detection signal is input to the main control board 300 from each of these detection switches.

In addition, the main control board 300 includes a normal electric accessory solenoid 120c that operates the movable piece 120b of the first variable starting port 120B, and a first big prize winning port that operates the open/close door 126b that opens and closes the first big prize winning port 126. The solenoid 126c and the second big prize winning opening solenoid 128c that operates the movable piece 128b that opens and closes the second big winning opening 128 are connected. Opening and closing control of the winning opening 126 and the second big winning opening 128 is performed.

Furthermore, the main control board 300 includes a first special symbol display 160, a second special symbol display 162, a first special symbol reservation display 164, a second special symbol reservation display 166, a normal symbol display 168, and a normal symbol display. A symbol holding indicator 170 and a right-handed information indicator 172 are connected, and the main control board 300 controls the display of each of these indicators.

Furthermore, on the back surface of the game board 108, a setting change switch 180s is provided. The setting change switch 180s is configured to be accessible with a dedicated key. Under the condition that the setting change switch 180s is turned on, the setting value can be changed and confirmed. Although the details will be described later, in the gaming machine 100 of the simultaneous spinning reference example, one of six levels of setting values with different degrees of advantage is stored as a registered setting value in the setting value buffer, and according to the stored registered setting value, Game progresses. Here, it is assumed that there are six levels of setting values, but the setting values may be provided in only two levels of high setting and low setting, or may be provided in a plurality of other levels. Furthermore, the set value is not essential, and the advantage level does not have to be changed.

Further, a RAM clear button is provided on the back surface of the game board 108 so that it can be pressed, and the RAM clear switch 182s detects the pressing operation of the RAM clear button. The RAM clear switch 182s is connected to the main control board 300, and a RAM clear operation signal is input to the main control board 300 from the RAM clear switch 182s. If a RAM clear operation signal is input from the RAM clear switch 182s when power is turned on, the main CPU 300a clears the main RAM 300c.

A performance display monitor 184 is provided on the back of the game board 108 . The main control board 300 displays the registered set values and the base ratio on the performance display monitor 184 .

In addition, the gaming machine 100 of the simultaneous spinning reference example mainly includes a special game that is started by entering a game ball into the first start port 120 or the second start port 122, passing the game ball through the gate 124, or , It is roughly divided into a normal game that is started by entering a game ball into the normal pattern operation port 125. The main ROM 300b of the main control board 300 stores various programs for progressing special games and normal games, data necessary for various games, and tables.

A payout control board 310 and a sub control board 330 are connected to the main control board 300 . The payout control board 310 performs control for shooting game balls and payout prize balls. This payout control board 310 also includes a CPU, ROM, and RAM, and is connected to the main control board 300 so as to be able to communicate bidirectionally. A game information output terminal board 312 is connected to the payout control board 310 , and various information on the progress of the game output from the main control board 300 is transmitted via the payout control board 310 and the game information output terminal board 312 . , is output to a hall computer or the like of the amusement arcade.

The payout control board 310 is also connected with a payout motor 314 for paying out the game balls stored in the storage portion to the player as prize balls. The payout control board 310 controls the payout motor 314 based on the payout number designation command transmitted from the main control board 300 to pay out predetermined prize balls to the player. At this time, the number of put-out game balls is detected by the put-out ball counting switch 316s, and it is grasped whether the prize balls to be put out have been put out to the player.

Further, the payout control board 310 is connected with a full-dish detection switch 318 s for detecting the full state of the lower tray 134 . This plate full detection switch 318 s is provided in a passage leading game balls paid out as prize balls to the lower plate 134 , and a game ball detection signal is input to the payout control board 310 .

Then, when the lower tray 134 is filled with a predetermined amount or more of game balls, the game balls stay in the passage toward the lower tray 134, and are directed toward the payout control board 310 from the tray full detection switch 318s. , the game ball detection signal is continuously input. The payout control board 310 determines that the lower tray 134 is full when the game ball detection signal is continuously input for a predetermined period of time, and transmits a full tray command to the main control board 300 . On the other hand, when the continuous input of the game ball detection signal is interrupted after the full-dish command is transmitted, it is determined that the full-drained state is canceled, and the full-dish full-drain release command is transmitted to the main control board 300 .

Also, the payout control board 310 is provided with a launch control circuit 320 for controlling the launch of game balls. The payout control board 310 is connected with a touch sensor 112s provided on the operating handle 112 for detecting that the player touches the operating handle 112, and an operation volume 112a for detecting the operating angle of the operating handle 112. ing. Then, when a signal is input from the touch sensor 112s and the operation volume 112a, the shooting control circuit 320 controls the shooting solenoid 112c provided in the game ball shooting device to energize and shoot the game ball.

The sub-control board 330 mainly controls each effect such as during a game or during standby. The sub-control board 330 includes a sub-CPU 330a, a sub-ROM 330b, and a sub-RAM 330c, and is connected to the main control board 300 so as to be able to communicate in one direction from the main control board 300 to the sub-control board 330. . The sub CPU 330a reads the program stored in the sub ROM 330b based on the command transmitted from the main control board 300, the input signal from the timer, etc., performs arithmetic processing, and executes and controls the performance. At this time, the sub-RAM 330c functions as a data work area during the arithmetic processing of the sub-CPU 330a.

Specifically, in the sub-control board 330, the sub-CPU 330a, the sub-ROM 330b, and the sub-RAM 330c cooperate to function as a sub-main, an image control section, a character control section, a lighting control section, and a sound control section. The sub-main decides the content of the effect to be executed, and manages and supervises the execution of the effect according to various input commands. The image control section performs image display control for displaying an image on the main effect display section 200a. The sub-ROM 330b stores a large amount of image data such as patterns, backgrounds, subtitles, etc. displayed on the main effect display section 200a. It controls the image display of the effect display section 200a.

In addition, the accessory control unit drives the actuator according to the management of the presentation by the sub-main, and controls the movement of the presentation accessory device 202 . The lighting control unit controls lighting of the production lighting device 204 . Also, the audio control unit performs audio output control for outputting audio from the audio output device 206 . The sub-ROM 330b stores a large amount of audio data such as sounds and music output from the audio output device 206, and the audio control unit reads the audio data from the sub-ROM 330b and controls the audio output of the audio output device 206. do.

Further, the sub-control board 330 executes a predetermined effect when an operation detection signal is input from the effect operation device detection switch 208s that detects that the effect operation device 208 has been pressed or rotated.

A power supply board (not shown) is connected to each board, and power is supplied to each board from a commercial power supply via the power supply board. Also, the power supply board is provided with a backup power supply comprising a capacitor.

FIG. 5 is an address map of a memory area used by the main CPU 300a according to the simultaneous rotation reference example. In FIG. 5, addresses are shown in hexadecimal numbers, and "H" indicates hexadecimal numbers. As shown in FIG. 5, the memory area used by the main CPU 300a includes a memory area (0000H to 2FFFH) allocated to the main ROM 300b and a memory area (F000H to F3FFH) allocated to the main RAM 300c.

The memory area of the main ROM 300b consists of a use area (0000H to 1BF3H) for storing programs and data for controlling the progress of the game, and an area other than the use area, which is used for processing for performing tests stipulated by gaming machine regulations. and an unused area (2000H to 2BFFH) for storing programs and data for executing processing for displaying the performance display monitor 184 (including processing for calculating the base ratio to be displayed on the performance display monitor 184) and are provided.

The area used in the main ROM 300b includes a program area (0000H to 0A89H) that stores programs for controlling the progress of games, an unused area (0A8AH to 11FFH), and a data area (1200H) that stores data other than programs. ~1BF3H) are provided. Note that the used area may not include the unused area (0A8AH to 0FFFH).

The non-use area of the main ROM 300b is a program area (2000H to 27FFH) for storing programs for executing processes for performing tests stipulated by game machine regulations and processes for displaying the performance display monitor 184, A data area (2800H to 2BFFH) is provided for storing data other than these programs.

In addition to the used area and the unused area, the memory area of the main ROM 300b also includes an unused area (1A7BH to 1DFFH), a ROM comment area (1E00H to 1EFFH) in which arbitrary data such as program titles and versions are stored. ), an unused area (1F00H to 1FFFH), an unused area (2C00H to 2FBFH), and a program management area (2FC0H to 2FFFH) in which information necessary for main CPU 300a to execute a program is stored.

The memory area of the main RAM 300c is a use area (F000H to F1FFH) that is temporarily used when a program for controlling the progress of a game is being executed, and an area other than the use area. A non-use area (F210H to F228H) that is temporarily used when a program for performing a predetermined test or processing for displaying the performance display monitor 184 is executed is provided.

The area used in the main RAM 300c includes a work area (F000H to F12AH) that is temporarily used when a program for controlling the progress of the game is executed, an unused area (F12BH to F1D7H), A stack area (F1D8H to F1FFH) is provided for temporarily saving data during execution of a control program. Note that the used area may not include the unused area (F12BH to F1D7H).

In the non-use area of the main RAM 300c, there is a work area (F210H to F21FH), and a stack area (F220H to F228H) for temporarily saving data while these programs are being executed.

The memory area of the main RAM 300c also has unused areas (F200H to F20FH) and unused areas (F229H to F3FFH) in addition to the used area and the unused area.

In this way, the main ROM 300b and the main RAM 300c have a usable area for controlling the progress of the game, a processing for performing a test stipulated by gaming machine regulations, and a processing for controlling the display of the performance display monitor 184. are provided separately from the non-use area used for executing the

In the main RAM 300c, a 16-byte unused area (F200H to F20FH) is provided between the used area and the unused area. This unused area (F200H to F20FH) is set as a boundary area separating the used area and the unused area, and the boundary between the used area and the unused area becomes clear, and the program for controlling the progress of the game When the non-use area is used during execution, and when the program of the processing for performing the test stipulated by the gaming machine regulations and the processing for controlling the display of the performance display monitor 184 is being executed It prevents the used area from being used.

The unused area provided between the used area and the unused area should be at least 1 byte or more, preferably 4 bytes or more from the viewpoint of fraud prevention, and is set to 16 bytes or more. is more desirable. Also, although the unused area is prohibited from writing and reading data, it may be cleared at a predetermined timing from the viewpoint of fraud prevention.

An input/output unit is assigned to the memory space from FE00h to FFFFh. Such an input/output unit will be described in detail later.

Next, a game in the gaming machine 100 of the simultaneous spinning reference example will be described together with various tables stored in the main ROM 300b.

As described above, in the gaming machine 100 of the simultaneous spinning reference example, two types of games, a special game and a normal game, progress in parallel. In the special game, the game progresses in one of the low-probability game state and the high-probability game state, and the normal game is in one of the non-time-saving game state, medium-time-saving game state, and time-saving game state. The game progresses.

The details of each game state will be described later, but the low-probability game state is a game state in which the probability of winning the right to execute the big win game in which the big winning opening is opened is set low, and is called a high-probability game state. 1 is a gaming state in which the probability of winning the right to execute a big win game is set high. In addition, the non-time-saving game state is a game state in which the movable piece 120b is difficult to open, and the game ball is difficult to enter the first variable start port 120B. It is a game state in which the movable piece 120b is more likely to be in the open state than in the state, and the game ball is more likely to enter the first variable starting port 120B. In addition, the time-saving game state is a game state in which the movable piece 120b is more likely to be in an open state than in the middle-time-saving game state, and the game ball is most likely to enter the first variable starting port 120B. In addition, in the time-saving game state, when the game balls are continuously shot toward the second game area 116b during the game, the game balls are set to decrease slightly or hardly decrease. .

As mentioned above, since the special game and the normal game progress in parallel, in the simultaneous turning reference example, the low probability game state or high probability game state, non-time-saving game state, medium-time-saving game state, time-saving game It becomes a game state in which any of the states is combined. Below, in order to facilitate understanding, the game state related to the special game, ie, the low probability game state and the high probability game state is called a special game state, the game state usually related to the game, ie, non-time-saving game state, medium The time-saving game state and the time-saving game state may be called normal game state. The initial state of the gaming machine 100 is set to a low-probability gaming state and a non-time-saving gaming state.

When the player operates the operation handle 112 to shoot the game ball into the game area 116, and the game ball flowing down the game area 116 enters the first start hole 120 or the second start hole 122, the player is asked to play the game. A lottery (hereinafter referred to as a "big role lottery") is held to decide whether or not to give a profit. In this big win lottery, when a big win is won, a big win game is executed in which the big win hole is opened and a game ball can enter the big win hole, and a game state after the big win game ends. is set to one of the above game states. Below, the major role lottery method will be described.

Although details will be described later, when a game ball enters the first start port 120 or the second start port 122, various random numbers related to the big role lottery (jackpot determination random number, winning pattern random number, reach group determination random number, reach mode determination random number, variation pattern random number) are acquired, and each random value is stored in the special figure reservation storage area of the main RAM 300c. Hereinafter, various random numbers stored in the special figure reservation storage area after the game ball enters the first start port 120 are collectively referred to as special 1 reservation, and the game ball enters the second start port 122. Various random numbers stored in the special figure reservation storage area are collectively called special 2 reservation.

The special figure reservation storage area of the main RAM 300c includes a first special figure reservation storage area and a second special figure reservation storage area. The first special figure reservation storage area and the second special figure reservation storage area each have four storage units (first to fourth storage units). Then, when the game ball enters the first start port 120, the special 1 reservation is stored in order from the first storage part of the first special figure reservation storage area, and when the game ball enters the second start port 122, special 2 reservation is stored in order from the first storage part of the second special figure reservation storage area.

For example, when the game ball enters the first start port 120, if the reservation is not stored in any of the first to fourth storage units of the first special figure reservation storage area, the first storage unit Store special 1 hold. Also, for example, in a state where special 1 suspension is stored in the first storage unit to the third storage unit, when the game ball enters the first start port 120, special 1 suspension is stored in the fourth storage unit Remember. Also, when the game ball enters the second start port 122, in the same manner as above, the special 2 reservation is stored in the first to fourth storage units of the second special figure reservation storage area. The special 2 hold is stored in the storage unit with the smallest number (ordinal number) that is not available.

However, the number of special 1 reservations (X1) and the number of special 2 reservations (X2) that can be stored in the first special figure reservation storage area and the second special figure reservation storage area are set to four respectively. Therefore, for example, when a game ball enters the first start port 120, if four special 1 reservations are already stored in the first special figure reservation storage area, to the first start port 120 A special 1 suspension is not newly stored by the entry of a game ball. Similarly, when the game ball enters the second start port 122, if four special 2 reservations are already stored in the second special figure reservation storage area, the game to the second start port 122 A special 2 hold is not newly memorized by the entry of a ball.

FIG. 6 is a diagram illustrating a low-probability jackpot determination random number determination table according to the simultaneous turning reference example. When a game ball enters the first starting port 120 or the second starting port 122, one jackpot determination random number is obtained from within the range of 0-65535. Then, when the big win lottery is started, that is, according to the game state when judging the big win, the big win determination random number determination table is selected, and the selected jackpot determination random number determination table and the acquired jackpot determination random number are used. A lottery will be held.

In the low-probability gaming state, when the big win lottery is started for special 1 suspension and special 2 suspension, the low-probability jackpot determination random number determination table is referred to. Here, in the simultaneous turning reference example, six levels of setting values with different degrees of advantage are provided, and the low-probability jackpot determination random number determination table is provided for each setting value. During the game, the set value is set to one of six levels, and the low-probability jackpot decision random number judgment corresponding to the currently set set value (registered set value stored in the set value buffer) A lottery for major roles is conducted with reference to the table.

In the low-probability gaming state, when set value = 1 (registered set value = 1), refer to the low-probability jackpot determination random number determination table a shown in FIG. is done. According to this low probability jackpot determination random number determination table a, when the jackpot determination random number is 10001 to 10218, it is determined as a jackpot, when the jackpot determination random number is 20001 to 38996, it is determined as a small hit, and others If it is a big hit decision random number, it is determined as a loss. Therefore, the big win probability in this case is about 1/300.6, and the small win probability is about 1/3.45.

In the low-probability gaming state, when the set value is set to 2 (registered set value = 2), the large role lottery with reference to the low-probability jackpot determination random number determination table b shown in FIG. 6(b) is done. According to this low probability jackpot determination random number determination table b, when the jackpot determination random number is 10001 to 10225, it is determined as a jackpot, when the jackpot determination random number is 20001 to 38996, it is determined as a small hit, and others If it is a big hit decision random number, it is determined as a loss. Therefore, the big win probability in this case is about 1/291.2, and the small win probability is about 1/3.45.

In the low-probability gaming state, when the set value is set to 3 (registered set value = 3), the large role lottery with reference to the low-probability jackpot determination random number determination table c shown in FIG. 6(c) is done. According to this low probability jackpot determination random number determination table c, when the jackpot determination random number is 10001 to 10232, it is determined as a jackpot, when the jackpot determination random number is 20001 to 38996, it is determined as a small hit, and others If it is a big hit decision random number, it is determined as a loss. Therefore, the big win probability in this case is about 1/282.4, and the small win probability is about 1/3.45.

In the low-probability gaming state, when set value = 4 (registered set value = 4), refer to the low-probability jackpot determination random number determination table d shown in FIG. is done. According to this low probability jackpot determination random number determination table d, it is determined as a jackpot when the jackpot determination random number is 10001 to 10239, and when the jackpot determination random number is 20001 to 38996, it is determined as a small hit. If it is a big hit decision random number, it is determined as a loss. Therefore, the big win probability in this case is about 1/274.2, and the small win probability is about 1/3.45.

In the low-probability gaming state, when the setting value is set to 5 (registered setting value=5), the large role lottery with reference to the low-probability jackpot decision random number determination table e shown in FIG. 6(e) is done. According to this low probability jackpot determination random number determination table e, when the jackpot determination random number is 10001 to 10246, it is determined as a jackpot, when the jackpot determination random number is 20001 to 38996, it is determined as a small hit, and others If it is a big hit decision random number, it is determined as a loss. Therefore, the big win probability in this case is about 1/266.4, and the small win probability is about 1/3.45.

In the low-probability gaming state, when set value = 6 (registered set value = 6), refer to the low-probability jackpot determination random number determination table f shown in FIG. is done. According to this low probability jackpot determination random number determination table f, when the jackpot determination random number is 10001 to 10253, it is determined as a jackpot, when the jackpot determination random number is 20001 to 38996, it is determined as a small hit, and others If it is a big hit decision random number, it is determined as a loss. Therefore, the big win probability in this case is about 1/259.0, and the small win probability is about 1/3.45.

FIG. 7 is a diagram for explaining a high-probability jackpot determination random number determination table according to the simultaneous turning reference example. In the high-probability gaming state, when the big win lottery is started for special 1 suspension and special 2 suspension, the high-probability jackpot determination random number determination table is referred to. The high-probability jackpot determination random number determination table is also provided for each set value in the same manner as the low-probability jackpot determination random number determination table.

In the high-probability gaming state, when the setting value is set to 1 (registered setting value=1), the large role lottery is performed with reference to the high-probability jackpot determination random number determination table a shown in FIG. 7(a). is done. According to this high probability jackpot determination random number determination table a, when the jackpot determination random number is 10001 to 10620, it is determined as a jackpot, when the jackpot determination random number is 20001 to 38996, it is determined as a small hit, and others If it is a big hit decision random number, it is determined as a loss. Therefore, the big win probability in this case is about 1/105.7, and the small win probability is about 1/3.45.

Similarly, in the high probability gaming state, if the setting value = 2 ~ 6 is set (registration setting value = 2 ~ 6), the high probability jackpot shown in Figure 7 (b) ~ (f) A major winning lottery is performed with reference to the decision random number determination tables b to f. According to these high-probability jackpot determination random number determination tables b to f, when the jackpot determination random number is the value shown in the drawing, it is determined as a jackpot. Therefore, when the set value is 2 to 6, the big win probability is about 1/102.4 to 1/91.0, and the small win probability is about 1/3.45.

As described above, the major role lottery is performed according to the registered setting values. At this time, the probability of winning a big win differs depending on the registered set value, and it is easier to win a big win when the registered set value is larger than when the registered set value is small. Here, even if the registered set values are different, the odds of winning the small win are not changed, but the odds of winning the small win may be changed for each registered set value. Also, the small win is not essential, and only one of the big win and the loss may be determined in the big win lottery.

Also, here, the probability of winning the jackpot in both the low-probability gaming state and the high-probability gaming state is different according to the registered set value. Only the probability of winning may differ according to the registered set value.

FIG. 8 is a diagram for explaining a winning symbol random number determination table and a small winning symbol random number determination table according to the simultaneous spinning reference example. When a game ball enters the first starting port 120 or the second starting port 122, one winning symbol random number is obtained from within the range of 0-99. Then, when the determination result of "big hit" is derived by the big win lottery, the type of special symbol is determined by the acquired winning symbol random number and the winning symbol random number determination table. At this time, when the "big win" is won by the special 1 reservation, as shown in FIG. 8(a), the special 1 winning symbol random number determination table a is selected, and the "big win" is won by the special 2 reservation. In this case, as shown in FIG. 8(b), the winning symbol random number determination table b for special 2 is selected, and when the "small winning" is won by holding the special 1, as shown in FIG. 8(c). Then, the special 1 small winning symbol random number determination table a is selected, and when the "small winning" is won by the special 2 reservation, as shown in FIG. b is selected. In the following, the special pattern determined by the winning pattern random number, that is, the special pattern determined when the judgment result of the big hit is obtained is called the jackpot pattern, and it is decided when the judgment result of the small hit is obtained. A special symbol is called a small winning symbol, and a special symbol determined when a loss determination result is obtained is called a losing symbol.

According to the special 1 per symbol random number determination table a shown in FIG. 8(a) and the special 2 per symbol random number determination table b shown in FIG. 8(b), according to the value of the acquired per symbol random number, As shown in the figure, jackpot symbols (special symbols A to J) are determined as special symbols. Also, according to the special 1 small per symbol random number determination table a shown in FIG. 8 (c) and the special 2 small per symbol random number determination table b shown in FIG. 8 (d), the value of the acquired per symbol random number Accordingly, as shown in the figure, small winning symbols (special symbols Z1 to Z6) are determined as special symbols.

It should be noted that, when the result of the lottery lottery is "losing", when the lottery result is derived by special 1 reservation, the special symbol X is determined as a losing pattern without performing a lottery, and the lottery result is the special 2 When derived by holding, the special symbol Y is determined as a losing symbol without lottery. That is, the winning symbol random number determination table is referred to only when the big win lottery result is "big hit", and is not referred to when the big win lottery result is "loss" or "minor win". Also, the small win symbol random number determination table is referred only when the big win lottery result is "small win", and is not referred to when the big win lottery result is "big win" or "losing". In addition, the special symbols Z1 to Z6, which are the small winning symbols, are collectively referred to simply as the special symbol Z.

FIG. 9 is a diagram for explaining a reach group determination random number determination table according to the simultaneous rotation reference example. A plurality of reach group determination random number determination tables are provided, and a preset table is selected according to the type of reservation, the number of reservations, the game state, and the like. When a game ball enters the first starting port 120 or the second starting port 122, one reach group determination random number is obtained from within the range of 0-10006. As described above, when the key role lottery result is derived, a process of determining a variable effect pattern for reporting the key role lottery result is performed. In the simultaneous spinning reference example, when the big role lottery result is "losing", the group type is first determined by the reach group determination random number and the reach group determination random number determination table in determining the variable performance pattern.

For example, when the game state is set to the normal state, which will be described later in detail, and the result of the "losing" major role lottery is derived based on the special 1 suspension, the special 1 suspension is held when the major role lottery is performed. If the number (hereinafter simply referred to as "retained number") is 0, the reach group determination random number determination table 1 is selected as shown in FIG. 9(a). Similarly, when the normal state is set, if the result of the "losing" big role lottery is derived based on the special 1 reservation, if the number of reservations when performing the big lottery lottery is 1 to 2, As shown in FIG. 9(b), the reach group determination random number determination table 2 is selected, and if the number of reservations is 3, as shown in FIG. 9(c), the reach group determination random number determination table 3 is selected. be. In addition, in FIG. 9, the group x described in the group type column indicates an arbitrary group number. Therefore, various group numbers are determined as group types according to the reach group determination random number obtained and the type of the reach group determination random number determination table to be referred to.

It should be noted that here, in the normal state, based on the Special 1 reservation, the reach group determination random number determination table that is referred to when the "losing" key role lottery result is derived has been described, but the main ROM 300b also stores A large number of reach group determination random number determination tables are stored.

In addition, when the big role lottery result is "big win" or "small win", the group type is not determined when determining the variation production pattern. That is, the reach group determination random number determination table is referred only when the big win lottery result is "losing", and is not referred to when the big win lottery result is "big hit" or "minor win".

FIG. 10 is a diagram for explaining a reach mode determination random number determination table according to the simultaneous rotation reference example. This reach mode determination random number determination table is the reach mode determination random number determination table at the time of losing selected when the big role lottery result is "losing", and the big win selected when the big role lottery result is "big hit" It is roughly divided into a time reach mode determination random number determination table and a small win time reach mode determination random number determination table selected when the big winning lottery result is "small win". In addition, the reach mode determination random number determination table at the time of losing is provided for each group type determined as described above, and the reach mode determination random number determination table at the time of the big hit and the reach mode determination random number determination table at the time of the small hit are the game state , are provided for each hold type.

In addition, each ready-to-win mode decision random number determination table is provided for each game state and type of symbol. Here, FIG. 10A shows an example of the reach mode determination random number determination table for group x that is referred to in a predetermined game state and symbol type, and an example of the reach mode determination random number determination table for special 1 jackpot Shown in FIG. 10 (b), an example of a reach mode determination random number determination table for special 2 jackpot is shown in FIG. 10 (c), an example of a reach mode determination random number determination table for special 1 small hit is FIG. , and an example of the reach mode determination random number determination table for small hits for special 2 is shown in FIG. 10(e).

When a game ball enters the first starting port 120 or the second starting port 122, one reach mode determination random number is obtained from within the range of 0-250. Then, when the result of the big role lottery is "losing", as shown in FIG. A determination table is selected, and a variation mode number is determined based on the selected reach mode determination random number determination table at loss and the reach mode determination random number. In addition, when the result of the big win lottery is "jackpot", as shown in FIGS. A big hit reach mode determination random number determination table is selected, and a variation mode number is determined based on the selected big hit reach mode determination random number determination table and reach mode determination random number.

Furthermore, when the result of the big win lottery is "small win", as shown in FIGS. A small hit reach mode determination random number determination table corresponding to is selected, and a variation mode number is determined based on the selected small hit reach mode determination random number determination table and reach mode determination random number.

Further, in each reach mode determination random number determination table, the reach mode determination random number is associated with a variation mode number and a variation pattern random number determination table described later. A random number decision table is determined. In FIG. 10, the table x described in the column of variation pattern random number determination table indicates an arbitrary table number. Therefore, the variation mode number and the table number of the variation pattern random number determination table are determined according to the acquired reach group determination random number and the type of the reach mode determination random number determination table to be referred to. Further, in the simultaneous turning reference example, the variation mode number and the variation pattern number, which will be described later, are set in hexadecimal. In the following description, hexadecimal numbers are indicated by "H", but ◯◯H in FIGS. 10 to 12 indicates arbitrary values represented by hexadecimal numbers.

As described above, when the winning lottery result is "lost", first, the group type is determined by the reach group determination random number determination table shown in FIG. 9 and the reach group determination random number. Then, according to the determined group type and gaming state, the variation mode number and the variation pattern random number determination table are determined by the reach mode determination random number determination table and the reach mode determination random number at the time of losing shown in FIG. 10(a).

On the other hand, if the big win lottery result is "big win" or "small win", the determined big win pattern or small win pattern (type of special pattern), the game state at the time of winning the big win or small win, etc. With reference to the corresponding reach mode determination random number determination table shown in FIG. 10, the reach mode determination random number is used to determine the variation mode number and the variation pattern random number determination table.

FIG. 11 is a diagram for explaining a fluctuation pattern random number determination table according to the simultaneous rotation reference example. Here, a fluctuation pattern random number determination table x of a predetermined table number x is shown, but many other fluctuation pattern random number determination tables are provided for each table number.

When a game ball enters the first starting port 120 or the second starting port 122, one variation pattern random number is obtained from within the range of 0-238. Then, based on the fluctuation pattern random number determination table determined at the same time as the fluctuation mode number and the obtained fluctuation pattern random number, the fluctuation pattern number is determined as shown in the figure.

Thus, when the big role lottery is performed, the variation mode number and the variation pattern number are determined according to the big role lottery result, the determined symbol type, the game state, the number of reservations, the type of reservation, and the like. These variable mode number and variable pattern number specify the variable effect pattern, and each of them is associated with the mode and time of the variable effect.

FIG. 12 is a diagram for explaining a variable time determination table according to the simultaneous rotation reference example. As described above, when the variable mode number is determined, variable time 1 is determined according to the variable time 1 determination table shown in FIG. 12(a). According to this variable time 1 determination table, variable time 1 is associated with each variable mode number, and the corresponding variable time 1 is determined according to the determined variable mode number.

Further, as described above, when the variation pattern number is determined, the variation time 2 is determined according to the variation time 2 determination table shown in FIG. 12(b). According to this variation time 2 determination table, variation time 2 is associated with each variation pattern number, and the corresponding variation time 2 is determined according to the determined variation pattern number. The total time of the variable times 1 and 2 determined in this way is the time of the variable effect for informing the result of the big role lottery, that is, the variable time. This fluctuation time is the time until the determined special symbol is stopped and displayed on the first special symbol display device 160 or the second special symbol display device 162 .

Although it will be described later in detail, the special design is determined based on the special 1 reservation, and when the variation mode number and the variation pattern number, that is, the variation time are determined, the first special design display over the determined variation time The variable display of the symbol is performed in the device 160, and when the variable time elapses, the determined special symbol is stopped and displayed on the first special symbol display device 160. - 特許庁In addition, when the special symbol is determined based on the special 2 hold and the variation pattern number, that is, the variation time is determined, the variation display of the symbol is performed on the second special symbol display 162 over the determined variation time. After the variation time has elapsed, the determined special symbol is stopped and displayed on the second special symbol display device 162 . At this time, the losing pattern is stop-displayed on the first special symbol display device 160, so that the losing is determined as a result of the major role lottery, and the major role lottery based on the next special 1 reserve can be executed, and the losing symbol is the second. By stop-displaying on the special symbol display device 162, a loss is determined as a result of the major role lottery, and the major role lottery based on the next special 2 reservation can be executed. On the other hand, when the jackpot pattern is stopped and displayed on the first special pattern display device 160 or the second special pattern display device 162, the jackpot is determined as a result of the big win lottery, the big win game is executed, and the small win pattern is the first special. When the symbol display device 160 or the second special symbol display device 162 is stop-displayed, a small win is confirmed as a result of the big win lottery, and a small win game is executed.

In this way, the variable time defines the time for the variable display of the symbols on the first special symbol display device 160 or the second special symbol display device 162, in other words, the time until the result of the major role lottery is determined. Become.

When the variation mode number is determined as described above, a variation mode command corresponding to the determined variation mode number is transmitted to the sub control board 330, and when the variation pattern number is determined, the determined variation A variation pattern command corresponding to the pattern number is transmitted to the sub control board 330 . In the sub control board 330, mainly the first half of the variable performance is determined based on the received variable mode command, and the second half of the variable performance is mainly determined based on the received variable pattern command. However, the details will be described later. In the following description, the variation mode number and variation pattern number may be collectively referred to as variation information, and the variation mode command and variation pattern command may be collectively referred to as variation command.

FIG. 13 is a diagram for explaining the game state and variation time according to the simultaneous spinning reference example. As described above, the special game state and the normal game state are combined into one game state, and the progress of the game is controlled according to the game state being set. As already explained, the special game state is provided in two types, a low-probability game state and a high-probability game state, in which the odds of winning a jackpot are different. In addition, the normal game state is provided with three types: a non-time-saving game state, a medium-time-saving game state, and a time-saving game state, in which the easiness (ball-entering frequency) of the game ball to the first variable start port 120B is different from each other. It is

Here, in the normal game, the ease of entry of the game ball into the first variable starter opening 120B is determined by three factors: winning probability, fluctuation time, and opening time. Although details will be described later, in the normal game, when the game ball passes through the gate 124 or the game ball enters the normal pattern operation port 125, normal pattern suspension is stored. Then, based on the stored general pattern reservation, a general pattern lottery for determining whether or not to open the movable piece 120b is performed. The result of this normal drawing lottery is determined when a predetermined fluctuation time has elapsed. When winning is determined as a result of the normal drawing lottery, the movable piece 120b is released. At this time, the winning probability in the normal drawing lottery, the fluctuation time, and the opening time when opening the movable piece 120b are set for each normal game state.

In the simultaneous spinning reference example, as shown in FIG. 13(a), six types of game states are provided by combining the special game state and the normal game state. The initial state of the gaming machine 100 is a low-probability gaming state and a non-time-saving gaming state. In addition, in the non-time-saving game state, the winning probability in the normal drawing lottery is low, the fluctuation time is long, and the opening time of the movable piece 120b is short. In the simultaneous turning reference example, the game state in which the low-probability game state and the non-time-saving game state are combined is called a normal state.

Also, in the simultaneous turning reference example, it may be set to a high probability game state and a non-time-saving game state, and the game state in which both are combined is called the most dominant state. This highest priority state has the highest degree of advantage among the six game states, and if the game balls are shot appropriately, the number of game balls gradually increases during the game even if the jackpot is not won. It is set to go.

Also, in the simultaneous turning reference example, it may be set to a low probability game state and a time saving game state. In addition, in the time-saving game state, the winning probability in the normal drawing lottery is high, the fluctuation time is short, and the opening time of the movable piece 120b is long. Below, the game state in which the low-probability game state and the time-saving game state are combined is called a low-probability time-saving state.

Also, in the simultaneous turning reference example, it may be set to a high probability game state and a time saving game state. Below, the game state in which the high probability game state and the time saving game state are combined is called a high probability time saving state or a high probability omen state. In addition, the high-probability time saving state and the high-probability omen state will be described later in detail.

In addition, in the simultaneous turning reference example, it may be set to a high probability game state and a medium time reduction game state. In addition, in the medium time-saving game state, the winning probability in the normal drawing lottery is higher than the non-time-saving game state and lower than the time-saving game state, the fluctuation time is short, and the opening time of the movable piece 120b is long. This game state can be set when an unforeseen situation occurs, such as when the game ball is not properly shot. In the following, the game state in which the high probability game state and the medium time reduction game state are combined is called a penalty state.

Incidentally, in the sub-control board 330, an effect mode corresponding to the game state set in the main control board 300 is set. The effect mode defines the background image, BGM, etc. displayed on the main effect display section 200a, and the content of the effect differs for each effect mode. That is, the player can identify the current game state by the effect mode.

As described above, in the simultaneous spinning reference example, six game states are provided. Then, as described above, the variation mode number and variation pattern number, that is, the variation time is determined according to the game state, the reservation type, the number of variations in the game state, and the type of symbol when the big role lottery is performed. be.

Here, in the gaming machine 100, a substantial variation target is set for each gaming state. The subject of substantial variation originally indicates the type of suspension for which the major role lottery should be performed, and either special 1 suspension or special 2 suspension is set as the substantial variation subject for each game state. In the normal state, Special 1 hold is set as a substantial fluctuation target. Also, in the normal state, since the normal game state is a non-time-saving game state, the first variable starter opening 120B is hardly opened. Therefore, in the normal state, the player needs to launch the game ball toward the first game area 116a in order to enter the game ball into the first fixed starting port 120A.

In the normal state, when the big winning lottery is performed by the special 1 reservation which is the object of substantial fluctuation, and the losing pattern or the small winning pattern is determined, the fluctuation time is determined within the range of 3 to 100 seconds. Also, in the normal state, when the big win lottery is performed by the special 1 reservation and the big winning pattern is determined, the fluctuation time is determined within the range of 40 to 100 seconds.

On the other hand, in the normal state, when the major role lottery is performed by the special 2 reserve which is not subject to actual variation, the variation time is always determined to be 10 minutes regardless of the determined symbol type. In this way, by setting the variable time to a long time such as 10 minutes, in the normal state, even if the player enters the game ball into the second start port 122, the major role lottery based on the special 2 reservation Very few opportunities to do so.

Specifically, the second starter opening 122 is provided in the second game area 116b, and the second starter opening 122 is always configured as a fixed starter opening into which game balls can enter. Furthermore, due to the playability of the gaming machine 100, the second starting hole 122 is arranged at a position where a game ball enters more easily than the first starting hole 120.例文帳に追加Therefore, if the fluctuation time for the special 2 hold is shortened in the normal state, the player will be given more chances than necessary for the winning lottery. Therefore, in accordance with the original playability in the normal state, the variation time is set to a long time such as 10 minutes in order to appropriately shoot the game ball toward the first game area 116a.

In the highest priority state, Special 2 hold is set as a substantial fluctuation target. Therefore, in the highest priority state, the player needs to launch the game ball toward the second game area 116b in order to enter the game ball into the second starting hole 122.例文帳に追加In the highest priority state, when a major role lottery is performed by special 1 reservation which is not subject to actual variation, the variation time is always determined to be 10 seconds regardless of the determined symbol type. In addition, in the case where the major role lottery is performed by special 1 suspension that is not subject to substantial fluctuation in the most dominant state, compared to the case where the major role lottery is performed by special 2 suspension that is not subject to substantial fluctuation in the normal state, the game performance is improved. little impact. Therefore, in the highest priority state, the fluctuation time when the major role lottery is performed by the special 1 reservation that is not subject to real fluctuation is set as short as 10 seconds.

In the highest priority state, a large winning lottery is performed by the special 2 reservation which is the object of substantial fluctuation, and when the losing pattern or the small winning pattern is determined, the fluctuation time is determined within the range of 1 to 3 seconds. Also, in the highest priority state, when the big winning lottery is performed by special 2 reservation and the big winning pattern is determined, the variation time is determined within the range of 3 seconds to 10 seconds.

In both the low probability short working hours state and the high certainty short working hours state, special 1 suspension is set as a real fluctuation target. In addition, in the low probability time saving state and the high probability time saving state, the normal game state is set to the time saving game state, and the first variable starting port 120B is frequently controlled to the open state. Therefore, in these two game states, the player needs to shoot the game ball toward the second game area 116b in order to enter the game ball into the first variable starting port 120B. In these two game states, the same variation pattern random number determination table is selected, but these two game states are common in that the normal game state is the time-saving game state. In other words, when the normal game state is the time-saving game state, the big role lottery is performed by the special 1 reservation that is the actual fluctuation target, and when the losing pattern or the small winning pattern is determined, the fluctuation time of 1 second is always determined. be. In addition, in the case of the low-probability short working hours state and the high-probable short working hours state, when the big winning lottery is performed by the special 1 reservation and the big winning pattern is determined, the fluctuation time is always set to 30 seconds.

In the highly probable omen state, the special 1 hold is set as a substantial fluctuation target. Further, in the high-probability omen state, the normal game state is set to the time-saving game state, and the first variable starting port 120B is frequently controlled to the open state. Therefore, in the high-probability omen state, the player needs to launch the game ball toward the second game area 116b in order to enter the game ball into the first variable starting port 120B. In the high-probability omen state, when a large role lottery is performed by special 1 reservation which is a real fluctuation object, and a losing pattern or a small winning pattern is determined, a fluctuation time is determined within the range of 3 seconds to 10 seconds. In addition, in the high-probability omen state, when the big winning lottery is performed by special 1 reservation and the big winning pattern is determined, the fluctuation time is always determined to be 30 seconds.

On the other hand, when the low-probability short-time state, high-probability short-time state and high-probability omen state, that is, when the normal game state is the time-saving game state, when the big role lottery is performed by the special 2 hold that is not subject to real fluctuation, Regardless of the determined symbol type, the variable time is always determined to be 10 minutes.

In the penalty state, special 1 suspension is set as a substantial fluctuation target. In addition, in the penalty state, the normal game state is set to the medium time-saving game state, and the first variable starting port 120B is controlled to the open state at a constant frequency. Therefore, in the penalty state, the player needs to shoot the game ball toward the second game area 116b in order to enter the game ball into the first variable starting port 120B. In the penalty state, a large winning lottery is performed by holding special 1, which is the object of substantial fluctuation, and when a losing pattern or a small winning pattern is determined, a fluctuation time is determined within the range of 3 to 100 seconds. In addition, in the penalty state, when the big winning lottery is performed by special 1 suspension and the big winning pattern is determined, the fluctuation time is determined within the range of 40 to 100 seconds.

On the other hand, in the penalty state, when the big role lottery is performed by the special 2 reserve which is not subject to actual fluctuation, the fluctuation time is always determined to be 10 minutes regardless of the determined symbol type.

As described above, a substantial variation target is set for each game state, and when a major role lottery based on a reservation type as a substantial variation target is performed, the maximum variation time is 100 seconds. On the other hand, when the big role lottery based on the reservation type which is not subject to actual variation is performed, the variation time is approximately 10 minutes, so that the game contrary to the original game characteristics is not performed.

In addition, in the simultaneous turning reference example, the average of the fluctuation time of the high-probability short-time state is shorter than the average of the fluctuation time of the high-probability omen state, but the average of the fluctuation time of the high-probability short-time state is highly probable It may be longer than the average of the fluctuation time of the precursor state. That is, the average of the fluctuation time of the high probability short working hours state and the average of the fluctuation time of the high probability precursor state may be different.

FIG. 14 is the first diagram for explaining the special electric accessory operating ramset table according to the simultaneous rotation reference example, and FIG. 15 is the first diagram for explaining the special electric accessory operating ramset table according to the simultaneous rotation reference example. 2. FIG. In addition, the special electric role product operating ram set table stores various data for controlling the big role game or the small winning game, and the special electric role product operating ram set By referring to the table, the energization of the first big winning opening solenoid 126c or the second big winning opening solenoid 128c is controlled. In fact, a plurality of special electric accessory actuating ramset tables are provided for each type of special symbols (both jackpot symbols and small winning symbols), and depending on the type of special symbol determined, the corresponding table plays a major role. Although it is set at the start of a game or a small winning game, here, for convenience of explanation, control data of special symbols are shown for each type of symbol.

As shown in FIG. 14, the big winning game is composed of a plurality of round games in which the big winning opening is opened and closed a predetermined number of times, and the small winning game is executed only once. According to this special electric role product operation ram set table, the opening time (waiting time until the first round game is started), the maximum number of times of special electric role product operation (executed during one big role game or small winning game number of round games played), number of times of opening and closing of special electric accessories (number of times the large winning opening is opened in one round), solenoid energization time (first large winning opening solenoid 126c or second Energizing time of the large winning opening solenoid 128c, that is, opening time of one large winning opening), specified number (maximum number of possible winnings to the large winning opening in one round game), effective time of closing the large winning opening (round Closing time of the big winning opening between games, that is, interval time), ending time (waiting time from the end of the last round game to the restart of the normal special game (fluctuation display of symbols described later)) However, as control data, it is stored in advance as shown in the figure for each type of special symbol.

Incidentally, when a jackpot is won by special 1 reservation and special symbols A, B, and D are determined as jackpot symbols, a big win game consisting of four round games is executed. In this big win game, the first big winning opening 126 is opened only once in each of the first to fourth round games. In each round game, the first big prize opening 126 is opened for a maximum of 29.0 seconds. The first prize winning opening 126 is closed and one round game ends.

Further, when a jackpot is won by special 1 reservation and special symbols C and E are determined as jackpot symbols, a big win game consisting of 10 round games is executed. In these big win games, the first big winning opening 126 is opened only once in each of the 1st to 10th round games. In each round game, the first big prize opening 126 is opened for a maximum of 29.0 seconds. The first prize winning opening 126 is closed and one round game ends.

In addition, when a small winning is won by special 1 reservation and special symbols Z1 to Z3 are determined as small winning symbols, a small winning game composed of one round game is executed. In this small winning game, the second big winning opening 128 is opened once for 0.1 seconds in one round game.

Also, as shown in FIG. 15, when a jackpot is won by special 2 reservation and special patterns F, G, and I are determined as jackpot patterns, a big win game consisting of four round games is executed. be. In this big win game, the first big winning opening 126 is opened only once in each of the first to fourth round games. In each round game, the first big prize opening 126 is opened for a maximum of 29.0 seconds. The first prize winning opening 126 is closed and one round game ends.

In addition, when a jackpot is won by special 2 reservation and special patterns H and J are determined as jackpot patterns, a big win game consisting of 10 round games is executed. In this big win game, the first big winning opening 126 is opened only once in each of the 1st to 10th round games. In each round game, the first big prize opening 126 is opened for a maximum of 29.0 seconds. The first prize winning opening 126 is closed and one round game ends.

Further, even when a small winning is won by special 2 reservation and special symbols Z4 to Z6 are determined as small winning symbols, a small winning game consisting of one round game is executed. Here, in the small winning game when the special symbol Z4 is determined as the small winning symbol, the second big winning opening 128 is opened twice for 0.1 seconds in one round game. It should be noted that the interval time during the round, which is the pause time between opening the second big winning hole 128 twice, is set to 1.78 seconds. Since the game ball is shot at an interval of 0.6 seconds at the shortest, considering the opening time of the second big winning hole 128 and the shooting interval of the game ball, the game ball will be the second big winning during this small winning game. The probability of hitting the ball in the mouth 128 is low.

However, in the simultaneous turning reference example, the structure is such that game balls tend to stay on the movable piece 128b that maintains the second big winning hole 128 in the closed state, and the movable piece 128b is moved to the open state, so that the movable piece 128b can move. A game ball staying on the piece 128b is guided into the second big winning hole 128. - 特許庁Therefore, by opening the second big winning hole 128 twice for 0.1 seconds, 2 to 3 game balls enter the second big winning hole 128 on average.

Further, in the small winning game when the special symbol Z5 is determined as the small winning symbol, the second big winning opening 128 is opened 0.1 seconds×3 times in one round game. In this case, the in-round interval time is set to 0.84 seconds. In this small winning game, 3 to 4 game balls enter the second big winning hole 128 on average.

Furthermore, in the small winning game when the special symbol Z6 is determined as the small winning symbol, the second big winning opening 128 is opened 0.1 seconds×12 times in one round game. In this case, the in-round interval time is set to 0.84 seconds. In this small winning game, by continuing to shoot game balls toward the second game area 116b, it is almost certain that a specified number (for example, 10) of game balls can enter the second big winning hole 128. can.

In the design stage of the gaming machine 100, it is necessary to strictly manage and adjust the shot prize ball ratio, which is the ratio between the number of game balls shot and the number of prize balls paid out. Therefore, in the simultaneous turning reference example, a special symbol Z4 in which the opening of 0.1 seconds is performed twice in the small winning game, and a special symbol Z5 in which the opening of 0.1 seconds is performed three times in the small winning game are provided, Only by changing these selection ratios, the shot prize ball ratio can be easily adjusted and changed.

FIG. 16 is a diagram for explaining a game state setting table for setting the game state after the end of the big win game according to the simultaneous spinning reference example. In the simultaneous spinning reference example, when the big win game is executed, the game state setting table is referred to according to the game state at the time of winning the jackpot, the type of reservation, and the type of special pattern (jackpot pattern), and after the big win game ends Set the game state of

When the game state at the time of winning the jackpot is the normal state or the penalty state, when the jackpot is won by holding special 1 which is the object of substantial variation, the game state after the big win game is set according to the type of the jackpot pattern. Specifically, when the special symbol A is determined as the jackpot symbol, it is set to a low-probability time-saving state (the special game state is a low-probability game state, and the normal game state is a time-saving game state). At this time, the number of continuation times of the time saving game state (hereinafter referred to as "time saving number of times") is set to 100 times. This means that the time-saving gaming state continues until the big win lottery is performed 100 times. However, the number of times of time saving described above indicates the maximum number of times of continuation in the time saving game state of 1, and if the jackpot is won before the number of times of continuation is reached, the game state is set again. It will happen. Therefore, when the time-saving game state is set after the end of the big role game, when the lottery result other than the big win is derived 100 times without deriving the jackpot lottery result in the time-saving game state, the non-time-saving game state The game state is changed to (normal state).

In addition, when the special symbols B and D are determined as the jackpot symbols, a high-probability time-saving state (the special game state is a high-probability game state, and the normal game state is a time-saving game state) is set. At this time, "next time" is set as the high-probability number of times, and the high-probability game state continues until the next big win is won. In addition, "next time" is set as the number of time-saving games, and the time-saving game state continues until the next big win is won. Therefore, when the special symbols B and D are determined, the high-probability time-saving state continues until the next big win is won after the big win game.

In addition, when the special symbols C and E are determined as the jackpot symbols, the high probability precursor state (the special game state is the high probability game state, and the normal game state is the time saving game state) is set. At this time, "next time" is set as the high probability number of times, and the time saving number of times is set to 100 times. When the special symbols C and E are determined, the high-probability game state continues until the next big win is won, while the time-saving game state ends after 100 times. Therefore, when the special symbols C and E are determined, after the big win game, the game state shifts to the highest priority state when the result of the big win lottery is derived 100 times.

In addition, when the game state at the time of winning the big win is the normal state or the penalty state, if the big win is won by holding special 2 which is not subject to real variation, the game state after the big win game is set as follows. That is, when the special symbol F is determined as the jackpot symbol, it is set to the normal state (the special game state is the low probability game state, and the normal game state is the non-time-saving game state). Also, when the special symbols G to J are determined as the jackpot symbols, the penalty state is set (the special game state is the high-probability game state, and the normal game state is the medium-short-time game state). At this time, both the high-probability number of times and the time-saving number of times are set to "next time".

In addition, when the game state at the time of winning the jackpot is the highest priority state, if the jackpot is won by special 1 reservation, which is not subject to real variation, the game state after the big win game is set as follows. That is, when the special symbol A is determined as the jackpot symbol, it is set to a low-probability time-saving state (the special game state is a low-probability game state, and the normal game state is a time-saving game state). At this time, the number of times of time saving is set to 100 times. Further, when the special symbols B to E are determined as the jackpot symbols, the game state after the big win game is set in the same manner as the normal state and the penalty state.

On the other hand, when the game state at the time of winning the jackpot is the highest priority state, when the jackpot is won by holding special 2, which is the object of substantial variation, the game state after the big win game is set as follows. That is, when the special symbol F is determined as the jackpot symbol, it is set to a low-probability time-saving state (the special game state is a low-probability game state, and the normal game state is a time-saving game state). At this time, the number of times of time saving is set to 100 times. Further, when the special symbols G and I are determined as the jackpot symbols, the high-probability time-saving state (the special game state is the high-probability game state, and the normal game state is the time-saving game state) is set. At this time, the high probability number of times and the time saving number of times are set to "next time".

In addition, when the special symbols H and J are determined as the jackpot symbols, the high probability precursor state (the special game state is the high probability game state, and the normal game state is the time saving game state) is set. At this time, the high probability number of times is set to "next time", and the time saving number of times is set to 100 times.

Also, if the game state at the time of jackpot winning is a low-probability short-time state, high-probability short-time state, high-probability omen state, that is, if the normal game state is a short-time game state, the game state after the big win game is the normal state and penalty conditions.

FIG. 17 is a diagram for explaining a winning determination random number determination table according to the simultaneous spinning reference example. When the game ball flowing down the game area 116 passes through the gate 124 or enters the normal figure operation opening 125, it is associated whether or not the movable piece 120b of the first variable starting opening 120B is energized and controlled. Normal design determination processing (hereinafter referred to as "normal drawing lottery") is performed.

In addition, although it will be described in detail later, when the game ball passes through the gate 124 or enters the normal pattern operation port 125, one hit determination random number is acquired from within the range of 0 to 99, and this random Numerical values are stored up to four in the general map reservation storage area of the main RAM 300c. That is, the general pattern reservation storage area has four storage units for saving the hit determination random numbers. Therefore, in the state in which the determined random number is stored in all four storage units of the normal pattern reservation storage area, the game ball passes through the gate 124 or enters the normal pattern operation port 125, the game No hit decision random numbers are stored based on ball passage. In the following, the game ball passes through the gate 124 or the game ball enters the normal pattern operation port 125 and the hit decision random number stored in the normal pattern reservation storage area is called normal pattern reservation.

When the normal game state is a non-time-saving game state, when the normal drawing lottery is started, as shown in FIG. According to this non-time-saving gaming state hit determination random number determination table, when the hit determination random number is 0, the hit design is determined as the type of normal design, and when the hit determination random number is 1 to 99, A lost pattern is determined as the type of the normal pattern. Therefore, the probability that winning symbols are determined in the non-time-saving gaming state, that is, the winning probability is 1/100. Although details will be described later, when the winning pattern is determined in this normal pattern lottery, the movable piece 120b of the first variable starting port 120B is controlled to the open state, and when the losing pattern is determined, the first variable starting The movable piece 120b of the mouth 120B is kept closed.

In addition, when starting the normal drawing lottery in the medium time-saving game state, as shown in FIG. According to this middle-time-saving gaming state hit determination random number determination table, when the hit determination random number is 0 to 49, the hit design is determined as the normal design type, and when the hit determination random number is 50 to 99 Then, a lost symbol is determined as the type of the normal symbol. Therefore, the probability that winning symbols are determined in the middle-time-saving gaming state, that is, the winning probability is 50/100.

In addition, when starting the normal figure lottery in the time saving game state, as shown in FIG. According to this time-saving gaming state hit determination random number determination table, when the hit determination random number is 0 to 98, the hit design is determined as the type of normal design, and when the hit determination random number is 99, normal A lost pattern is determined as the type of the pattern. Therefore, the probability that winning symbols are determined in the time-saving gaming state, that is, the winning probability is 99/100.

FIG. 18(a) is a diagram for explaining a normal symbol fluctuation time data table according to the simultaneous rotation reference example, and FIG. 18(b) is a diagram for explaining an opening/closing control pattern table according to the simultaneous rotation reference example. As described above, when the general pattern lottery is performed, the fluctuation time of the normal pattern is determined. The normal symbol variation time data table is referred to when determining the normal symbol variation time when a winning symbol or a losing symbol is determined by a normal symbol lottery. According to this normal symbol variation time data table, when the game state is set to the non-time-saving game state and the medium-time-saving game state, the variation time is determined to be 10 seconds, and the game state is set to the time-saving game state. If so, the variation time is determined to be 1 second. When the variable time is determined in this way, the normal symbol display 168 is variable-displayed (blinking-displayed) over the determined time. Then, when a winning symbol is determined, the normal symbol display 168 is lit, and when a losing symbol is determined, the normal symbol display 168 is extinguished.

Then, when the winning pattern is determined by the normal pattern lottery and the normal pattern display 168 is lit, the movable piece 120b of the first variable starting port 120B is controlled to open and close as shown in FIG. 18(b). The energization is controlled by referring to the pattern table. Actually, the opening/closing control pattern table is provided for each game state, and the corresponding table is set at the start of energization of the normal electric accessory solenoid 120c according to the game state when the normal symbol is determined. .

When the winning pattern is determined, as shown in FIG. 18(b), the opening/closing of the first variable starting port 120B is controlled with reference to the opening/closing control pattern table. According to this opening/closing control pattern table, the time before normal electric opening (waiting time until the opening of the first variable starting port 120B is started), the maximum number of opening/closing switching times of normal electric accessories (opening of the first variable starting port 120B number of times), solenoid energization time (energization time of the ordinary electric accessory solenoid 120c for each number of times the first variable starter opening 120B is opened, that is, opening time of the first variable starter 120B once), specified number (first variable The maximum number of winnings to the first variable starting port 120B while the starting port 120B is fully open), the normal power closing effective time (the closing time between each opening of the first variable starting port 120B, that is, the rest time), the normal power Effective state time (waiting time from the end of the last opening of the first variable start port 120B), normal electric end wait time (after the normal electric effective state time elapses, waiting until the fluctuation display of the normal symbol described later is resumed time) is stored in advance as shown in the figure for each game state as the control data for the first variable start port 120B.

In this way, by setting the winning probability, variation time, and release time of normal symbols, as shown in the lower part of FIG. 1st variable starting port 120B, 2nd starting port 122, normal pattern operation port 125 and the ratio of the number of prize balls paid out to the player by entering the game ball in the normal pattern operation port 125 and the big winning port) is the number of shots : number of prize balls = 100:20, number of shots in medium time-saving game state: number of prizes = 100:40, number of shots in time-saving game state: number of prize balls = 100:99.

The open/close condition of the first variable starting port 120B defines three elements: winning probability of normal symbols, variable display time of normal symbols, and opening time of the first variable starting port 120B. In other words, by combining the three elements of the winning probability of normal symbols, the time of variable display of normal symbols, and the opening time of the first variable start port 120B, in each of the non-time-saving game state, medium-time-saving game state, and time-saving game state, It is possible to set the entry frequency of game balls to the first variable starting port 120B and the launch prize ball ratio. In any case, the combination of the three elements shown here is only an example, and if the three elements are combined so that the shot prize ball ratio is higher in the time-saving gaming state than in the non-time-saving gaming state good.

FIG. 19 is a diagram for explaining the transition of the game state according to the original game property according to the simultaneous spinning reference example. With the configuration described above, the gaming machine 100 realizes the following gameplay. Here, a case where the registration setting value is set to "1" will be described. First, in the initial state of the gaming machine 100, the normal state shown in FIG. 19(a) is set. In the normal state, since the substantial variable object is set to special 1 reservation, the player shoots the game ball toward the first game area 116a in order to enter the game ball into the first fixed starting port 120A. Since the first game area 116a is located on the left side of the game board 108, the player normally performs so-called "left-handed".

When the game ball enters the first fixed starting port 120A, the special 1 reservation is stored in the first special figure reservation storage area. The special 1 reservation stored in the first special figure reservation storage area is sequentially read out when the starting condition is established, and a major role lottery based on the read special 1 reservation is performed. At this time, the probability of winning the jackpot is set to approximately 1/300.6. In the normal state, the game is played for the purpose of winning a big win in the big win lottery based on this special 1 reservation. In addition, the shot prize ball ratio is set to 100:20 when the game balls are shot toward the first game area 116a, and the number of game balls decreases during the game.

Then, in a normal state, when a big win is won in a big win lottery with special 1 reservation, a big win game is executed. In this big win game, the round game in which the first big winning hole 126 is opened is executed 4 times or 10 times, and the player can win prize balls for 4 rounds or 10 rounds. Then, when a jackpot is won by special 1 reservation, one of the special patterns A to E is determined as a jackpot pattern.

In the normal state, when the jackpot symbol stop-displayed on the first special symbol display 160 is the special symbol A, the game state after the big win game becomes the low-probability time-saving state shown in FIG. 19(b). When a jackpot is won with special 1 reservation, the probability that the special pattern A is determined as a jackpot pattern is 30%. Therefore, when a jackpot is won in the normal state, the game state shifts to the low-probability short-time state with a probability of 30%. In the low probability time saving state, the real fluctuation target is set to special 1 reservation, but since the normal game state is the time saving game state, the player enters the game ball into the first variable start port 120B. A right-handed shot is made aiming at the second game area 116b.

That is, in this low-probability short-time state, as in the normal state, in the big role lottery based on special 1 reservation, the game will be played for the purpose of winning the jackpot. In the low-probability time-saving state, the winning probability of the jackpot is about 1/300.6, but since the normal game state is the time-saving game state, the movable piece 120b is frequently opened. Therefore, the shot prize ball ratio is 100:99, and the player can aim for a big win while reducing consumption of game balls.

In addition, when moving to a low-probability time-saving state, the number of times of time-saving is set to 100 times, and if the jackpot is not won in 100 times of the big role lottery, the game state will shift to the normal state again (time-saving omission ).

Also, in the normal state, when the jackpot symbols stopped and displayed on the first special symbol display device 160 are the special symbols B and D, the game state after the big win game is the high-accuracy time-saving shown in (c) of FIG. state. When a jackpot is won with the special 1 reservation, the probability that the special symbols B and D are determined as the jackpot symbols is 35%. Therefore, when a jackpot is won in the normal state, the game state shifts to the high-probability time-saving state with a probability of 35%. In the high-probability time-saving state, the real variable target is set to special 1 reservation, but since the normal game state is the time-saving game state, the player enters the game ball into the first variable start port 120B. A right-handed shot is made aiming at the second game area 116b.

In other words, in this high-probability time-saving state, as in the normal state, the game is played for the purpose of winning the jackpot in the big role lottery based on the special 1 reservation. In addition, the probability of winning the jackpot is about 1/105.7, and the normal game state is the time saving game state, so that the movable piece 120b is frequently opened. Therefore, the shot prize ball ratio is 100:99, and the player can perform the big role lottery while reducing consumption of game balls. Therefore, in the high-probability short-time state, substantially, it can be said that the winning of the next jackpot is guaranteed.

Also, in the normal state, when the jackpot symbols stopped and displayed on the first special symbol display device 160 are the special symbols C and E, the game state after the big win game is a high certainty omen shown in (d) of FIG. state. When a jackpot is won with the special 1 reservation, the probability that the special symbols C and E are determined as the jackpot symbols is 35%. Therefore, when a jackpot is won in the normal state, the game state shifts to the high probability portent state with a probability of 35%. In the high probability omen state, the real fluctuation target is set to special 1 reservation, but since the normal game state is the time-saving game state, the player has to enter the game ball into the first variable start port 120B. A right-handed shot is made aiming at the second game area 116b.

Then, when the special symbols C and E are determined, the state is set to the high-probability portent state, and the number of times of time saving is set to 100 times. At this time, when the number of fluctuations after the big win game reaches 100 times, the time-saving game state ends, and the normal game state becomes a non-time-saving game state. As a result, the game state shifts to the highest priority state shown in (e) of FIG. 19 due to time saving. As will be described later in detail, in the highest priority state, the number of game balls can be increased simply by continuously shooting game balls toward the second game area 116b. Therefore, in the high-probability omen state, the purpose of the game is not to win the jackpot, but to get out of the game quickly without winning the jackpot.

According to the special 1 reservation of the real fluctuation target in the high probability omen state, high probability short working hours state, low probability short working hours state, special symbols A to E are determined as jackpot symbols when winning the jackpot. When the special symbol A is determined, four round games are executed in the big win game, and the game state after the big win game becomes the low probability time saving state shown in FIG. 19(b). Further, when the special symbols B and D are determined, the round game is executed 4 times or 10 times in the big win game, and the game state after the big win game becomes a high probability time saving state. Further, when the special symbols C and E are determined, the round game is executed 4 times or 10 times in the big win game, and the game state after the big win game becomes a high probability precursor state.

In the highest priority state, when the game ball enters the second starting port 122, the special 2 reservation is stored in the second special figure reservation storage area. The special 2 reserve stored in the second special figure reserve storage area is sequentially read out when the starting condition is established, and a major role lottery is performed based on the read special 2 reserve. At this time, the probability of winning the big prize is set to approximately 1/105.7, and the probability of winning the small prize is set to approximately 1/3.45. In the highest priority state, winning a small win is the most important purpose of the game in the big win lottery based on this special 2 reservation.

Specifically, when the game ball is launched into the second game area 116b, the ratio of the prize balls paid out by the game ball entering the second start port 122 to the number of launched balls is 100:60-80. is set to an extent. Then, in the highest priority state, in the big win lottery with special 2 reservation, a small winning game is frequently played because a small winning is won with a probability of about 1/3.45. Here, when a small win is won by special 2 reservation, small win symbols Z4 to Z6 are determined. As described above, in the small winning game when the small winning symbol Z4 is stopped and displayed on the second special symbol display device 162, an average of 2 to 3 game balls enter the second big winning hole 128. In the small winning game when the small winning symbol Z5 is stop-displayed on the second special symbol display 162, an average of 3 to 4 game balls enter the second big winning hole 128.例文帳に追加Furthermore, in the small winning game when the small winning symbol Z6 is stopped and displayed on the second special symbol display device 162, almost a specified number of game balls enter the second big winning opening 128.例文帳に追加

When a game ball enters the second big winning hole 128, for example, 15 prize balls are paid out for one game ball entering the game ball. As a result, in the highest priority state, the shot prize ball ratio, which is the ratio of the number of all prize balls to the number of shot balls, becomes 100:120. can be increased.

In addition, in this most dominant state, the normal game state is a non-time-saving game state, and the movable piece 120b is almost never in an open state. In addition, in the highest priority state, the special game state is a high probability game state, and the winning probability of the jackpot in the highest priority state is about 1/105.7. It can be said that the winning of the jackpot is guaranteed.

According to the special 2 reservation of the real variation object in this highest priority state, when the big win is won, the special symbols F to J are determined as the big win symbols. When the special symbol F is determined, four round games are executed in the big win game, and the game state after the big win game becomes the low-probability time-saving state shown in FIG. 19(b). Further, when the special symbols G and I are determined, the round game is executed 4 times or 10 times in the big win game, and the game state after the big win game becomes a high probability time saving state. Also, when the special symbols H and J are determined, the round game is executed 4 times or 10 times in the big win game, and the game state after the big win game becomes a high probability precursor state.

Since the most dominant state has an extremely high degree of advantage compared to other game states, the most important purpose of the game in the gaming machine 100 is to shift the game state to the most dominant state. As described above, the game is first started in the normal state, but the normal state does not suddenly transition to the highest priority state. Therefore, the transition route to the most dominant state via the high probability portent state is the transition route to the most dominant state in the gaming machine 100 .

Furthermore, in the simultaneous turning reference example, winning a specific small winning symbol is set as a transition condition from the high probability omen state to the most dominant state, apart from the time saving omission in the high probability omen state. Specifically, when a small hit is won by special 1 reservation, which is a real fluctuation target in a high certainty omen state, the special pattern Z1 is 1%, the special pattern Z2 is 69%, and the special pattern Z3 is 30 as a small winning pattern. % probability (see FIG. 8(c)).

At this time, when the special symbol Z1 is determined as the small winning symbol, the time saving game state ends with the end of the small winning game, and as a result, the game state shifts to the highest priority state.

In this way, since the state is shifted to the highest priority state by winning a specific small win, compared to the case where the state is shifted to the highest priority state only when the number of fluctuations reaches the specified number of times (100 times), it is easier for the player. Therefore, a sense of anticipation and a sense of tension are constantly imparted.

In addition, in the above-mentioned high probability omen state, high probability short working hours state, low probability short working hours state, a small hit is won with a probability of about 1/3.45. Therefore, in the high-probability omen state, the high-probability short working hours state, and the low-probable short working hours state, similarly to the most dominant state, the small winning game is frequently executed. However, the high-probability portent state, the high-probability short working hours state, and the low-probable short working hours state are all normal game states in the short working hours gaming state. In addition, although it will be described later in detail, even during the small winning game, the normal game state is maintained in the time saving game state. Therefore, although the second big winning opening 128 is opened during the small winning game, the first variable starting opening 120B is also opened during this time.

As described above, the first variable starting port 120B is provided above the second big winning port 128, and in the time saving game state, the opening time of the first variable starting port 120B is the second big winning much longer than the opening time of mouth 128. Therefore, in the high-probability omen state, high-probability short-time state, and low-probability short-time state, most of the game balls flowing down the second game area 116b enter the first variable starting port 120B, and enter the second big winning port 128. Almost no game ball enters. As a result, in the high-probability portent state, the high-probability short-time state, and the low-probability short-time state, unlike the most dominant state, even if the player hits right during the game, the number of game balls gradually decreases.

As described above, when the game progresses by the real variation object in accordance with the original game nature, when the jackpot is won, the gaming state after the big role game is a low probability time saving state, a high probability time saving state, a high probability omen state set to either. And, the high probability time saving state and the high probability omen state have in common that the special game state is the high probability game state and the normal game state is the time saving game state. On the other hand, the high-probability time-saving state continues until the next jackpot is won, whereas the high-probability omen state is the winning of a specific small hit (special symbol Z1) or the time-saving omission. The difference is that the state is shifted to the highest priority state.

Also, in the high-probability short-time state, the fluctuation time at the time of small hit and loss is set to 1 second, while in the high-probability omen state, the fluctuation time at the time of small hit and loss is 3 to 10 seconds. It differs in that it is set within the range (see FIG. 13(b)). That is, the average of the variable time in the high-probability short-time state is set shorter than the average of the variable time in the high-probability omen state.

Therefore, in the high-probability time-saving state, since the fluctuation time at the time of the small hit and the loss is relatively short, the real fluctuation object can be digested at high speed until the big hit is won. Although detailed description is omitted, during the special symbol variation time, the sub-control board 330 performs variable display of the effect symbols 210a, 210b, and 210c. In the high probability time saving state, the variable display of the production patterns 210a, 210b, and 210c is also relatively short. Therefore, in the high probability time saving state, as long as the special 1 reservation continues to be stored, the special 1 reservation (variable display of the production patterns 210a, 210b, 210c) will continue to be digested at high speed, and the time until winning the jackpot It can be shortened, and the game can be played until the next big win without (reduced) stress on the player.

On the other hand, in the high-probability omen state, the variation time is relatively long at the time of small win and at the time of loss, but in the sub-control board 330, an effect is performed as to whether or not to shift to the highest priority state. Therefore, the player can play while expecting that the game will shift to the highest priority state.

Thus, in the high-probability short-time state, even if a specific small hit (special pattern Z1) is won, it does not shift to the most dominant state, but by setting the average of the fluctuation time short, the next big hit It is possible to shorten the time until winning the prize, and reduce the stress on the player. In addition, in the high-probability omen state, the average of the fluctuation time is set longer than in the high-probability short-time state. It can give people a sense of expectation and a sense of tension.

As described above, the special game state is a high-probability game state, and the high-probability time-saving state and high-probability precursor state that are common to the normal game state being a time-saving game state are provided, and the fluctuation of the high-probability time-saving state By making the average of the time shorter than the average of the fluctuation time of the high-probability portent state, new playability can be provided.

FIG. 20 is a diagram for explaining the transition of the game state when the game is not properly played according to the simultaneous spinning reference example. As described above, in the gaming machine 100, the symbol variation display on the first special symbol display device 160 and the symbol variation display on the second special symbol display device 162 are performed in parallel. At this time, if there is a possibility that the player will be disadvantaged as a result of the large winning lottery being held due to the hold other than the actual variable object, the variable time is set to a long time such as 10 minutes. However, after the big win lottery is performed due to the holding other than the real fluctuation target, for example, as a result of interrupting the game, the jackpot due to the holding other than the real fluctuation target may be decided. In this case, the game state changes as shown in FIG.

The main processing of the main control board 300 for realizing the above-described game characteristics will be described below.

FIG. 21 is a diagram for explaining gaming machine state flags according to the simultaneous spinning reference example. In the main control board 300, whether or not the game is ready to progress is managed by a gaming machine state flag. One of six types of flag values from 00H to 05H is set in the gaming machine state flag. The flag value of the gaming machine state flag=00H indicates a playable state. When the gaming machine state flag is 00H, the progress of the game is controlled. be stopped.

The flag value of the game machine state flag=01H indicates a setting change state, and when the game machine state flag is 01H, the change operation of the registered setting value is possible. The flag value of the gaming machine state flag=02H indicates the setting confirmation state, and when the gaming machine state flag is 02H, the registered set value is displayed on the performance display monitor 184, and the registered set value is confirmed. It is possible to confirm. The flag value of the gaming machine state flag=03H indicates a setting abnormality state, and when the gaming machine state flag is 03H, the game is stopped as the registered setting value is abnormal. The flag value of the gaming machine state flag=04H indicates a RAM abnormal state, and when the gaming machine state flag is 04H, the game is stopped. The flag value of the gaming machine status flag=05H indicates an abnormal checksum status, and if the gaming machine status flag is 05H, the game is stopped. When the power is turned on, the game machine state flag is set to any flag value, and processing corresponding to the game machine state flag is performed.

(CPU initialization processing of main control board 300)
FIG. 22 is a first flowchart illustrating CPU initialization processing in the main control board 300 according to the simultaneous rotation reference example, and FIG. 23 illustrates CPU initialization processing in the main control board 300 according to the simultaneous rotation reference example. It is the 2nd flowchart which carries out.

When power is supplied from the power board, a system reset occurs in the main CPU 300a, and the main CPU 300a performs the following CPU initialization processing (S100).

(Step S100-1)
When the power is turned on, the main CPU 300a reads a startup program from the main ROM 300b as an initial setting process, and performs setting processes necessary for executing various processes.

(Step S100-3)
The main CPU 300a sets the wait processing time in the timer counter.

(Step S100-5)
The main CPU 300a determines whether a power-off warning signal is detected. A power interruption detection circuit is provided in the main control board 300, and a power interruption warning signal is output from the power interruption detection circuit when the power supply voltage drops below a predetermined value. If the power-off notice signal is detected, the process proceeds to step S100-3, and if the power-off notice signal is not detected, the process proceeds to step S100-7.

(Step S100-7)
The main CPU 300a determines whether or not the wait time set in step S100-3 has elapsed. As a result, when it is determined that the wait time has elapsed, the process proceeds to step S100-9, and when it is determined that the wait time has not elapsed, the process proceeds to step S100-5.

(Step S100-9)
The main CPU 300a executes necessary processing to permit access to the main RAM 300c.

(Step S100-11)
The main CPU 300a loads the flag value of the gaming machine state flag before power-off to the D register.

(Step S100-13)
The main CPU 300a calculates the checksum and determines whether the calculated checksum matches (is normal) the checksum saved at the time of power failure and whether the backup flag is normal. As a result, if it is determined that the backup flag and checksum are normal, the process moves to step S100-15, and if either or both are determined to be abnormal, the process moves to step S100-25. .

(Step S100-15)
The main CPU 300a sets an address that does not include the setting value and the gaming machine status flag as the top address to be cleared in the main RAM 300c.

(Step S100-17)
The main CPU 300a determines whether a RAM clear operation signal has been input from the RAM clear switch 182s (whether the RAM clear button has been pressed). As a result, if it is determined that the RAM clear operation signal has been input, the process proceeds to step S100-31, and if it is determined that the RAM clear operation signal has not been input, the process proceeds to step S100-19. .

(Step S100-19)
The main CPU 300a checks whether the value of the gaming machine status flag loaded in step S100-11 is 00H (game ready status), whether the setting change switch 180s is on, and whether the middle frame 104 is open. judge. As a result, when it is determined that all three conditions are satisfied, the process moves to step S100-21, and when it is determined that even one of the three conditions is not satisfied, the process moves to step S100-23.

(Step S100-21)
The main CPU 300a sets the gaming machine state flag to 02H (setting confirmation state). That is, when the power is normally turned on in a state in which the middle frame 104 is open, the setting change switch 180s is on, and the RAM clear button is not pressed, the setting confirmation state is entered.

(Step S100-23)
The main CPU 300a executes an initialization process of clearing the areas to be cleared at the time of power return, which are the areas after the head address set in step S100-15 in the main RAM 300c, and shifts the process to step S100-49.

(Step S100-25)
The main CPU 300a sets 05H (checksum abnormal state) in the D register.

(Step S100-27)
The main CPU 300a performs out-of-area read/write check processing for checking and clearing the read/write memory in the out-of-use area.

(Step S100-29)
The main CPU 300a sets an address including a set value and a gaming machine state flag to the leading address to be cleared in the main RAM 300c.

(Step S100-31)
The main CPU 300a checks and clears the read/write memory of the used area.

(Step S100-33)
The main CPU 300a determines whether the check result of the read/write memory in step S100-31 is normal. As a result, if it is determined to be normal, the process moves to step S100-37, and if it is determined to be not normal, the process moves to step S100-35.

(Step S100-35)
The main CPU 300a sets 04H (RAM abnormal state) in the D register, and shifts the process to step S100-45.

(Step S100-37)
The main CPU 300a determines whether 02H (setting confirmation state) is set in the D register. As a result, when it is determined that 02H is set, the process moves to step S100-39, and when it is determined that 02H is not set, the process moves to step S100-41.

(Step S100-39)
The main CPU 300a sets 00H (game ready state) in the D register.

(Step S100-41)
The main CPU 300a determines whether the setting change condition is satisfied. As a result, when it is determined that the setting change condition is satisfied, the process proceeds to step S100-43, and when it is determined that the setting change condition is not satisfied, the process proceeds to step S100-45. Here, at least the setting change conditions include that the setting change switch 180s is turned on, that the middle frame 104 is open, and that the RAM clear operation signal is input from the RAM clear switch 182s. included.

(Step S100-43)
The main CPU 300a sets 01H (setting change state) in the D register.

(Step S100-45)
The main CPU 300a saves the value set in the D register in the gaming machine state flag.

(Step S100-47)
The main CPU 300a executes an initialization process of clearing the clear target of the main RAM 300c when clearing the RAM, and shifts the process to step S100-49.

(Step S100-49)
The main CPU 300a performs a process of transmitting a payout command (RAM clear designation command) for transmitting to the payout control board 310 that the main RAM 300c has been cleared (stores the RAM clear designation command in a transmission buffer).

(Step S100-51)
The main CPU 300a loads the gaming machine state flag.

(Step S100-53)
The main CPU 300a determines whether or not the gaming machine state flag loaded in step S100-51 is 00H (playable state). As a result, if it is determined to be 00H, the process moves to step S110, and if it is determined not to be 00H, the process moves to step S100-55.

(Step S110)
The main CPU 300a performs subcommand group set processing. This subcommand group set process will be described later.

(Step S100-55)
The main CPU 300 a performs sub-command group set processing for transmitting a predetermined command to the sub-control board 330 .

(Step S100-57)
The main CPU 300a sets the cycle of the timer interrupt.

(Step S100-59)
The main CPU 300a performs processing for prohibiting interrupts.

(Step S100-61)
The main CPU 300a updates the initial value update random number for the winning symbol random number. The initial value update random number for the winning symbol random number is for determining the initial value and the end value of the winning symbol random number. In other words, when the winning design random number is updated from the winning design random number initial value update random number to the winning design random number initial value update random number -1, the winning design random number is at that time. It will be updated to the initial value update random number for the winning design random number.

(Step S100-63)
The main CPU 300a analyzes the received data (main command) received from the payout control board 310 and executes various processes according to the received data.

(Step S100-65)
The main CPU 300 a performs processing for transmitting the sub-commands stored in the transmission buffer to the sub-control board 330 .

(Step S100-67)
The main CPU 300a performs processing for permitting interrupts.

(Step S100-69)
The main CPU 300a updates the reach group determination random number, the reach mode determination random number, and the fluctuation pattern random number, and thereafter repeats the processing from step S100-59. In the following description, the reach group determination random number, the reach mode determination random number, and the variation pattern random number for determining the variable effect pattern are collectively referred to as variable effect random numbers.

FIG. 24 is a flowchart for explaining subcommand group set processing (S110) in the main control board 300 according to the simultaneous rotation reference example.

(Step S110-1)
The main CPU 300a loads the flag value of the gaming machine state flag.

(Step S110-3)
The main CPU 300 a performs sub-command group set processing for transmitting a predetermined command to the sub-control board 330 .

(Step S110-5)
The main CPU 300a performs a model command setting process of setting a model command indicating model information of the gaming machine 100 in a transmission buffer.

(Step S110-7)
The main CPU 300a performs setting value designation command setting processing for setting a setting value designation command indicating a registered setting value in a transmission buffer.

(Step S110-9)
The main CPU 300a performs a special figure 1 reservation designation command setting process for setting a special figure 1 reservation designation command indicating the number of special 1 reservations in the transmission buffer.

(Step S110-11)
The main CPU 300a performs a special figure 2 reservation designation command setting process for setting a special figure 2 reservation designation command indicating the number of special 2 reservations in the transmission buffer.

(Step S110-13)
The main CPU 300a performs a number command setting process of setting a number command indicating the remaining number of times of the time saving game state in the transmission buffer.

(Step S110-15)
The main CPU 300a performs a variation pattern selection state designation command setting process for setting a variation pattern selection state designation command indicating a variation pattern selection state in a transmission buffer.

(Step S110-17)
The main CPU 300a performs a special figure phase specification command setting process for setting a special figure phase specification command indicating a special game management phase in a transmission buffer. Incidentally, the special game management phase will be described later.

(Step S110-19)
The main CPU 300a determines whether the special game management phase is waiting for a special symbol variation. As a result, when it is determined that it is in the special symbol variation waiting state, the processing is moved to step S110-21, and when it is determined that it is not in the special symbol variation waiting state, the subcommand group set processing is terminated.

(Step S110-21)
The main CPU 300a sets the customer waiting designation command in the transmission buffer, and terminates the subcommand group set process.

Next, interrupt processing in the main control board 300 will be described. Here, save processing (XINT interrupt processing) and timer interrupt processing at power failure will be described.

(Evacuation processing (XINT interrupt processing) when main control board 300 is powered off)
FIG. 25 is a flowchart for explaining save processing (XINT interrupt processing) at power-off in the main control board 300 according to the simultaneous rotation reference example. The main CPU 300a monitors the power failure detection circuit, and when the power supply voltage drops below a predetermined value, it interrupts the CPU initialization process and executes the save process at power failure.

(Step S300-1)
When the power-off warning signal is input, the main CPU 300a saves the register.

(Step S300-3)
The main CPU 300a checks the power-off warning signal.

(Step S300-5)
The main CPU 300a determines whether a power-off warning signal is detected. As a result, when it is determined that the power cut warning signal is detected, the process is moved to step S300-11, and when it is determined that the power cut warning signal is not detected, the process is moved to step S300-7. .

(Step S300-7)
The main CPU 300a restores the register.

(Step S300-9)
The main CPU 300a performs processing for permitting an interrupt, and terminates the power-off save processing.

(Step S300-11)
The main CPU 300a executes output port clear processing to stop output from the output port.

(Step S300-13)
The main CPU 300a executes checksum setting processing for calculating and storing a checksum.

(Step S300-15)
The main CPU 300a executes RAM protection setting processing necessary to prohibit access to the main RAM 300c.

(Step S300-17)
The main CPU 300a sets the counter value of the loop counter to the predetermined number of power failure detection signal detections in order to set the power failure occurrence monitoring time.

(Step S300-19)
The main CPU 300a checks the power-off notice signal.

(Step S300-21)
The main CPU 300a determines whether a power-off warning signal is detected. As a result, when it is determined that the power cut warning signal is detected, the process is moved to step S300-17, and when it is determined that the power cut warning signal is not detected, the process is moved to step S300-23. .

(Step S300-23)
The main CPU 300a subtracts 1 from the value of the loop counter set in step S300-17.

(Step S300-25)
The main CPU 300a determines whether or not the counter value of the loop counter is zero. As a result, if it is determined that the counter value is not 0, the process proceeds to step S300-19, and if it is determined that the counter value is 0, the above-described CPU initialization process (step S100) is performed.

It should be noted that when the power is actually cut off, the operation of the game machine 100 is stopped while the steps S300-17 to S300-25 are being looped.

(Timer interrupt processing of main control board 300)
FIG. 26 is a flowchart for explaining timer interrupt processing in the main control board 300 according to the simultaneous rotation reference example. The main control board 300 is provided with a reset clock pulse generation circuit that generates a clock pulse at predetermined intervals (4 milliseconds in the simultaneous rotation reference example, hereinafter referred to as "4 ms"). Then, when a clock pulse is generated by the reset clock pulse generation circuit, the CPU initialization process (step S100) is interrupted, and the following timer interrupt process is executed.

(Step S400-1)
The main CPU 300a saves the register.

(Step S400-3)
The main CPU 300a performs processing for permitting interrupts.

(Step S400-5)
The main CPU 300a outputs the common data set in the common output buffer to the output port, the first special symbol indicator 160, the second special symbol indicator 162, the first special symbol reserve indicator 164, the second special symbol reserve. A dynamic port output process for controlling lighting of the display 166, the normal symbol display 168, the normal symbol reservation display 170, the right-handed information display 172, and the performance display monitor 184 is executed.

(Step S400-7)
The main CPU 300a reads various types of input port information and executes port input processing for accurately acquiring the latest switch state.

(Step S400-9)
The main CPU 300a loads the flag value of the gaming machine state flag.

(Step S400-11)
The main CPU 300a determines whether the flag value loaded in step S400-9 is 00H (playable state). As a result, when it is determined to be 00H, the process moves to step S400-15, and when it is determined not to be 00H, the process moves to step S400-13.

(Step S400-13)
The main CPU 300a determines whether the flag value loaded in step S400-9 is 03H (set abnormal state) or higher. As a result, if it is determined that it is 03H or more, the process moves to step S400-29, and if it is determined that it is not 03H or more, the process moves to step S450.

(Step S450)
The main CPU 300a executes setting-related processing, and shifts the processing to step S400-29. Note that the setting-related processing will be described later.

(Step S400-15)
The main CPU 300a performs timer update processing for updating various timer counters. Here, the various timer counters are decremented each time the timer interrupt processing of the main control board 300 is executed, and the decrementation is stopped when it reaches 0, unless otherwise specified.

(Step S400-17)
The main CPU 300a executes the process of updating the initial value update random number for the winning symbol random number in the same manner as in step S100-61.

(Step S400-19)
The main CPU 300a performs a process of updating the winning symbol random number. Specifically, the random number counter is updated by adding 1, and if the result of the addition exceeds the maximum value of the random number range, the random number counter is reset to 0. The random number is updated from the value of the initial value update random number for the winning design random number.

Although detailed description is omitted, in the simultaneous spinning reference example, the jackpot determination random number and the winning determination random number use hardware random numbers updated by a hardware random number generator built in the main control board 300. The hardware random number generator updates both the jackpot determined random numbers and the winning determined random numbers according to a fixed rule, automatically changes the random number sequence each time the random number sequence completes a cycle, and resets the start value each time the system is reset. are changing.

(Step S500)
The main CPU 300a includes a first fixed start opening detection switch 120As, a first variable start opening detection switch 120Bs, a second start opening detection switch 122s, a gate detection switch 124s, a normal figure operation opening detection switch 125s, and a first big winning opening detection switch. 126s, a switch management process for determining whether or not a signal has been input from the second big winning opening detection switch 128s is executed. The details of this switch management processing will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of the special symbols based on the special game reserved 2. The details of this special game management process will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of the special symbols based on the special game reserved 1st. In addition, here, the same program (module) as the special game management processing for controlling the progress of the variable display of the special symbols based on the special 2 reserve is read out, and the variable display of the special symbols based on the special 1 reserve is progressed. A special game management process for controlling is executed.

(Step S700)
The main CPU 300a executes a special electric role product game management process for controlling the progress of the big winning game and the small winning game in the special game. The details of this special electric role product game management process will be described later.

(Step S800)
The main CPU 300a executes normal game management processing for controlling the progress of the normal game. The details of this normal game management process will be described later.

(Step S400-21)
The main CPU 300a executes error management processing for determining various errors and making settings according to the error determination results.

(Step S400-23)
The main CPU 300a checks the general winning opening detection switch 118s, the first starting opening detection switch 120s, the second starting opening detection switch 122s, the first big winning opening detection switch 126s, and the second big winning opening detection switch 128s. Execute winning opening switch processing for adding a counter or the like for controlling winning balls.

(Step S400-25)
The main CPU 300a executes a payout control management process for creating and transmitting a payout command based on the counter value of the prize ball control counter set in step S400-23.

(Step S400-27)
The main CPU 300a sends a launching position specification command to the sub control board 330 to instruct the launching position of the game ball, that is, to which of the first game area 116a and the second game area 116b the game ball is to be launched. Execute position designation management processing.

(Step S400-29)
The main CPU 300a executes external information management processing for setting output data for external information to be output from the game information output terminal board 312 to the outside.

(Step S400-31)
The main CPU 300a has a first special symbol display 160, a second special symbol display 162, a first special symbol reservation display 164, a second special symbol reservation display 166, a normal symbol display 168, and a normal symbol reservation display 170. , LED display setting processing for setting display data for controlling the lighting of various indicators (LEDs) such as the right-handed information indicator 172 to the output buffer corresponding to each common.

(Step S400-33)
The main CPU 300a synthesizes the solenoid output images of the normal electric accessory solenoid 120c, the first big winning opening solenoid 126c, and the second big winning opening solenoid 128c, and executes the solenoid output image synthesis processing for storing in the output port buffer. .

(Step S400-35)
The main CPU 300a executes port output processing for outputting the common output buffer value stored in each output port buffer to the output port.

(Step S400-37)
The main CPU 300a performs processing for prohibiting interrupts.

(Step S400-39)
The main CPU 300a uses the non-use area of the main RAM 300c to perform processing for calculating the base ratio to be displayed on the performance display monitor 184, and common data for displaying the calculated base ratio on the performance display monitor 184. Executes performance display monitor control processing to be set in the output buffer. Note that in the performance display monitor control process, the base ratio is calculated for each predetermined period. Here, the performance display monitor 184 may alternately display the base ratio for the current period and the base ratio for the previous period at predetermined time intervals. Also, the base ratio displayed on the performance display monitor 184 may be switched according to a predetermined operation.

(Step S400-41)
The main CPU 300a restores the register and terminates the timer interrupt processing.

FIG. 27 is a flowchart for explaining the setting-related processing (S450) according to the simultaneous rotation reference example.

(Step S450-1)
The main CPU 300a determines whether the flag value of the gaming machine state flag is 01H (setting change state). As a result, if it is determined to be 01H, the process moves to step S450-3, and if it is determined not to be 01H, the process moves to step S450-15.

(Step S450-3)
The main CPU 300a loads the registered set values stored in the set value buffer into a predetermined processing area.

(Step S450-5)
The main CPU 300a determines whether the RAM clear switch 182s has been pressed (whether a RAM clear operation signal has been input). As a result, when it is determined that the RAM clear switch 182s has been pressed, the process proceeds to step S450-7, and when it is determined that the RAM clear switch 182s has not been pressed, the process proceeds to step S450-9. .

(Step S450-7)
The main CPU 300a adds 1 to the set value of the processing area.

(Step S450-9)
The main CPU 300a determines whether the set value of the processing area is in the range of 1-6. As a result, when it is determined that the set value is within the range of 1 to 6, the process proceeds to step S450-13, and when it is determined that the set value is not within the range of 1 to 6, the process proceeds to step S450-11. to move.

(Step S450-11)
The main CPU 300a sets the set value of the processing area to one.

(Step S450-13)
The main CPU 300a sets the set value of the processing area in the set value buffer.

(Step S450-15)
The main CPU 300a determines whether the setting change switch 180s is turned on. As a result, if it is determined that the setting change switch 180s is turned on, the setting-related processing is terminated, and if it is determined that the setting change switch 180s is not turned on, the process proceeds to step S450-17.

(Step S450-17)
The main CPU 300a sets a setting-related end designation command indicating the end of the setting-related processing in the transmission buffer.

(Step S110)
The main CPU 300a executes the subcommand group set process of FIG. That is, if the setting related process is executed, at the end, model command, setting value designation command, special figure 1 reserve designation command, special figure 2 reserve designation command, number of times command, variation pattern selection state designation command, special figure phase A designation command and a customer waiting designation command are transmitted to the sub control board 330 .

(Step S450-19)
The main CPU 300a sets the gaming machine state flag to 00H (game ready state), and terminates the setting-related processing.

As described above, according to the simultaneous turning reference example, when the power is normally turned on with the middle frame 104 opened, the setting change switch 180s turned on, and the RAM clear button depressed, the CPU initializes. In the change processing (FIG. 22), 01H (setting change state) is set to the gaming machine state flag. After that, timer interrupt processing is executed, but since 01H (setting change state) is set in the gaming machine state flag, all processing related to the progress of the game (steps S400-15 to S400-27 in FIG. 26) ) is stopped and configuration related processing is executed.

The setting-related processing is repeatedly executed while the setting change switch 180s is on, and during this setting-related processing, the operation of pressing the RAM clear button is accepted as the setting change operation of the registered set value. That is, during the setting change process (S450-1 to S450-13) for accepting the setting change operation, the registered setting value stored in the setting value buffer is one of the setting values provided in a plurality of stages according to the setting change operation. can be switched to

When the setting change switch 180s is turned off while the gaming machine state flag is set to 01H (setting change state), the setting change processing is terminated and the gaming machine state flag is set to 00H (playable state). set. As a result, from the next timer interrupt process, the process relating to the progress of the game can be executed.

Here, in the setting-related processing of the simultaneous rotation reference example, after the operation of pressing the RAM clear button, that is, after accepting the setting change operation of the registered setting value, in the subcommand group set processing, the setting value corresponding to the registered setting value is specified. A command is sent to the sub control board 330 . On the other hand, no setting value designation command is transmitted to the sub control board 330 while the setting change operation is being accepted. In this way, the setting value designation command is not transmitted while the setting change operation is being accepted, and the setting value designation command is transmitted when the acceptance of the setting change operation is completed and the state shifts to a state in which the game can be progressed. By doing so, it is possible to reduce the risk of unauthorized acquisition of registered setting values.

Further, in the simultaneous turning reference example, a plurality of flag values including at least 01H (setting change state) are switched. Then, when 01H (setting change state) is set in the gaming machine state flag, the setting-related processing can be executed and the progress of the game is stopped. In this way, since the setting-related processing is not executed while the game is in progress, the setting value designation command is not transmitted while the game is in progress, and the risk of illegally acquiring the registered setting values is reduced. be done.

Next, among the above timer interrupt processes, the switch management process at step S500, the special game management process at step S600, the special electric role product game management process at step S700, and the normal game management process at step S800 will be described in detail. .

FIG. 28 is a flowchart for explaining switch management processing (step S500) in the main control board 300 according to the simultaneous rotation reference example.

(Step S500-1)
The main CPU 300a determines whether the gate detection switch ON is detected, that is, whether the game ball passes through the gate 124 and the detection signal from the gate detection switch 124s is turned ON. As a result, when it is determined that the gate detection switch-on is detected, the process proceeds to step S510, and when it is determined that the gate detection switch-on is not detected, the process proceeds to step S500-7.

(Step S510)
The main CPU 300 a executes gate passage processing based on passage of the game ball through the gate 124 . The details of this gate passage processing will be described later.

(Step S500-3)
The main CPU 300a determines whether the normal pattern operation opening detection switch is turned on, that is, whether a game ball enters the normal pattern operation opening 125 and the detection signal from the normal pattern operation opening detection switch 125s is turned on. . As a result, if it is determined that the normal pattern operation port detection switch is turned on, the process proceeds to step S510, and if it is determined that the normal pattern operation port detection switch is not turned on, the process proceeds to step S500-5. to move.

(Step S510)
The main CPU 300 a executes gate passing processing based on the entry of a game ball into the normal pattern operation opening 125 .

(Step S500-5)
The main CPU 300a detects whether the first fixed starting hole detection switch is turned on, that is, whether a game ball enters the first fixed starting hole 120A and a detection signal is input from the first fixed starting hole detection switch 120As. judge. As a result, if it is determined that it is time to detect the first fixed starting port detection switch ON, the process proceeds to step S520, and if it is determined that it is not time to detect the first fixed starting port detection switch ON, step S500-7. to process.

(Step S520)
The main CPU 300a executes the first starting hole passing process based on the entry of the game ball into the first fixed starting hole 120A. The details of the first starting opening passage processing will be described later.

(Step S500-7)
The main CPU 300a detects whether the first variable starting hole detection switch is turned on, that is, whether a game ball enters the first variable starting hole 120B and a detection signal is input from the first variable starting hole detection switch 120Bs. judge. As a result, when it is determined that the first variable starter detection switch is turned on, the process proceeds to step S520, and when it is determined that the first variable starter detection switch is not turned on, step S500-11. to process.

(Step S520)
The main CPU 300a executes the first starting opening passing process based on the entry of the game ball into the first variable starting opening 120B. The details of the first starting opening passage processing will be described later.

(Step S500-9)
The main CPU 300a determines whether the game ball has been properly entered into the first variable starting port 120B, and if it is determined that the game ball has not been properly entered, the first A confirmation process at the time of normal electric accessary prize winning is executed for transmitting to the sub control board 330 a general electric fraudulent prize winning error generation designation command indicating the entry of an illegal game ball to the variable start port 120B.

(Step S500-11)
The main CPU 300a determines whether or not the second starting hole detection switch is turned on, that is, whether a game ball enters the second starting hole 122 and a detection signal is input from the second starting hole detection switch 122s. As a result, if it is determined that it is time to detect the second starting port detection switch ON, the process proceeds to step S530, and if it is determined that it is not time to detect the second starting port detection switch ON, the process proceeds to step S500-13. to move.

(Step S530)
The main CPU 300 a executes the second starting hole passing process based on the entry of the game ball into the second starting hole 122 . The details of the second starting opening passage processing will be described later.

(Step S500-13)
The main CPU 300a detects when the big winning hole detection switch is turned on, that is, when a game ball enters the first big winning hole 126 or the second big winning hole 128, the first big winning hole detection switch 126s or the second big winning hole detection switch 126s or the second big winning hole detection switch 126s It is determined whether or not a detection signal is input from the big winning opening detection switch 128s. As a result, if it is determined that the large winning opening detection switch is turned on, the process proceeds to step S540, and if it is determined that the large winning opening detection switch is not turned on, the switch management process is terminated.

(Step S540)
When the main CPU 300a determines whether the game ball has been properly entered into the first big winning hole 126 or the second big winning hole 128, and determines that the game ball has been properly entered. , a large winning hole passing process for transmitting a large winning hole entry command indicating the entry of a game ball into the first big winning hole 126 or the second big winning hole 128 to the sub control board 330 is executed. The details of this special winning opening passage processing will be described later.

FIG. 29 is a flowchart for explaining the gate passing process (step S510) in the main control board 300 according to the simultaneous turning reference example.

(Step S510-1)
The main CPU 300a loads the winning determination random number updated by the hardware random number generator.

(Step S510-3)
The main CPU 300a determines whether the counter value of the normal symbol reserved ball number counter is greater than or equal to the maximum value, that is, whether the counter value of the normal symbol reserved ball number counter is 4 or more. As a result, when it is determined that the counter value of the normal symbol reserved ball number counter is equal to or higher than the maximum value, the gate passing process is terminated, and when it is determined that the normal symbol reserved ball number counter is not equal to or higher than the maximum value. The process moves to step S510-5.

(Step S510-5)
The main CPU 300a updates the counter value of the normal symbol reserved ball number counter to a value obtained by adding "1" to the current counter value.

(Step S510-7)
The main CPU 300a calculates a target storage unit for saving the acquired winning determination random number, among the four storage units of the normal-pattern reservation storage area.

(Step S510-9)
The main CPU 300a saves the winning determination random number obtained in step S510-1 in the target storage section calculated in step S510-7.

(Step S510-11)
The main CPU 300a sets a general pattern reservation specification command indicating the general pattern reservation number stored in the general pattern reservation storage area in the transmission buffer, and ends the gate passage processing.

FIG. 30 is a flow chart for explaining the first starting opening passing process (step S520) in the main control board 300 according to the simultaneous turning reference example.

(Step S520-1)
The main CPU 300a sets "00H" as the special symbol identification value. In addition, the special symbol identification value is for identifying whether the reservation type is special 1 reservation or special 2 reservation, special symbol identification value (00H) indicates special 1 reservation, special symbol identification value ( 01H) indicates special 2 reservation.

(Step S520-3)
The main CPU 300a sets the address of the special symbol 1 reserved ball number counter.

(Step S535)
The main CPU 300a executes the special symbol random number acquisition process, and ends the first starting opening passage process. It should be noted that this special symbol random number acquisition process is executed using a module common to the second start opening passage process (step S530). Therefore, the details of the special symbol random number acquisition process will be described after the description of the second start opening passage process.

FIG. 31 is a flow chart for explaining the second start opening passing process (step S530) in the main control board 300 according to the simultaneous turning reference example.

(Step S530-1)
The main CPU 300a sets "01H" as the special symbol identification value.

(Step S530-3)
The main CPU 300a sets the address of the special symbol 2 reserved ball number counter.

(Step S535)
The main CPU 300a executes a special symbol random number acquisition process, which will be described later, and ends the second start opening passage process.

FIG. 32 is a flowchart for explaining the special symbol random number acquisition process (step S535) in the main control board 300 according to the simultaneous turning reference example. This special symbol random number acquisition process is executed using a common module in the above-described first starting opening passing process (step S520) and second starting opening passing process (step S530).

(Step S535-1)
The main CPU 300a loads the special symbol identification value set in step S520-1 or step S530-1.

(Step S535-3)
The main CPU 300a loads the number of target special symbol reserved balls. Here, if the special symbol identification value loaded in step S535-1 is "00H", the counter value of the special symbol 1 reserved ball number counter, that is, the special 1 reserved number is loaded. Also, if the special symbol identification value loaded in step S535-1 is "01H", the counter value of the special symbol 2 reserved ball number counter, that is, the special 2 reserved number is loaded.

(Step S535-5)
The main CPU 300a loads the jackpot determination random number updated by the hardware random number generator.

(Step S535-7)
The main CPU 300a determines whether or not the number of target special symbol reserved balls loaded in step S535-3 is equal to or greater than the upper limit. As a result, when it is determined that it is above the upper limit value, the special symbol random number acquisition process is terminated, and when it is determined that it is not above the upper limit value, the process is moved to step S535-9.

(Step S535-9)
The main CPU 300a updates the counter value of the target special symbol reserved ball number counter to a value obtained by adding "1" to the current counter value.

(Step S535-11)
The main CPU 300a calculates a target storage section for saving the acquired jackpot decision random number among the storage sections of the special figure reservation storage area.

(Step S535-13)
The main CPU 300a acquires the jackpot determination random number loaded in step S535-5, the winning pattern random number updated in step S400-19, and the variation pattern random number updated in step S100-69, and obtains the variation pattern random number updated in step S535-11. Store in the target storage unit calculated in .

(Step S535-15)
The main CPU 300a loads the counter values of the special symbol 1 reserved ball number counter and the special symbol 2 reserved ball number counter.

(Step S535-17)
The main CPU 300a sets the special figure reserve designation command in the transmission buffer based on the counter value loaded in step S535-15. Here, based on the counter value of the special symbol 1 reserved ball number counter (special 1 reserved number), the special figure 1 reserved designation command is set, and based on the counter value of the special symbol 2 reserved ball number counter (special 2 reserved number) to set the special figure 2 hold designation command. As a result, the number of special 1 reservations and the number of special 2 reservations are transmitted to the sub control board 330 each time special 1 reservations or special 2 reservations are stored.

(Step S536)
The main CPU 300a performs the effect determination process at the time of acquisition, and ends the special symbol random number acquisition process. In this acquisition time effect determination process, the result of the big role lottery, the variation pattern number, etc. are tentatively determined, and a prefetch designation command according to the result of the tentative determination is transmitted to the sub control board 330 . This effect determination process at the time of acquisition will be described with reference to FIG.

FIG. 33 is a flowchart for explaining the effect determination process (step S536) at the time of acquisition in the main control board 300 according to the simultaneous turning reference example.

(Step S536-1)
The main CPU 300a selects a corresponding jackpot determination random number determination table based on the set value being set. Specifically, based on the current game state and the set value being set, the corresponding big hit determination random number determination table is selected. Then, based on the selected table and the big hit determination random number stored in the target storage unit in step S535-13, a special symbol winning temporary determination process for temporarily determining any one of big win, small win, and loss is performed.

(Step S536-3)
The main CPU 300a executes a special symbol temporary determination process for temporarily determining a special symbol. Here, if the result of the temporary major role lottery in step S536-1 (the result derived by the special symbol per temporary determination process) is a big hit or a small hit, it is stored in the target storage unit in step S535-13. Load the hit symbol random number, winning type (whether it is a big win or a small win), and hold type, select the corresponding winning symbol random number determination table, extract the special symbol determination data, and extract the special symbol determination data. Save (type of jackpot pattern or small hit pattern). In addition, when the result of the provisional key role lottery in step S536-1 is a loss, predetermined special symbol determination data for loss (type of losing symbol) is saved.

(Step S536-5)
The main CPU 300a sets a look-ahead symbol type specification command (a look-ahead specification command) corresponding to the special symbol determination data saved in step S536-3 in the transmission buffer.

(Step S536-7)
The main CPU 300a determines whether the result derived by the special symbol winning temporary determination process in step S536-1 is a big win or a small win. As a result, if it is determined to be a big win or a small win, the process moves to step S536-9, and if it is determined to be neither a big win or a small win (it is a loss), the process moves to step S536-11.

(Step S536-9)
The main CPU 300a sets the reach mode determination random number determination table (see FIGS. 10(b) and (c)) or the reach mode determination random number determination table (see FIGS. 10(d) and (e)) at the time of the small hit, and step The process moves to S536-19.

(Step S536-11)
The main CPU 300a loads the reach group determination random number stored in the target storage unit in step S535-13.

(Step S536-13)
The main CPU 300a determines whether the reach group determination random number loaded in step S536-11 is a fixed value (9000 or more). Here, the group type is determined by referring to the reach group determination random number determination table, and this reach group determination random number determination table is selected according to the stored number of reservations. At this time, the reach group determination random number is obtained from the range of 0 to 10006, and if the value of the reach group determination random number is 9000 or more, regardless of the number of reservations, the same reach group determination random number determination table is selected, and reach If the value of the group determination random number is less than 9000, different reach group determination random number determination tables are selected according to the number of reservations. In the following, among the reach group determination random numbers, a value in the range of 0 to 8999 in which a different reach group determination random number determination table is selected according to the number of reservations is an indefinite value, and the same reach group determination random number determination is performed regardless of the number of reservations. A value in the range of 9000 to 10006 from which the table is selected is called a fixed value. If it is determined that the reach group determination random number loaded in step S536-11 is a fixed value (9000 or more), the process moves to step S536-15, and the reach group determination random number loaded in step S536-11 is fixed. If it is determined not to be the value (9000 or more), the process moves to step S536-27.

(Step S536-15)
The main CPU 300a sets a reach group determination random number determination table (see FIG. 9). Although a plurality of reach group determination random number determination tables are provided according to the number of reservations, here, the table used when the number of reservations is 0 is selected. Then, the reach group (group type) is tentatively determined based on the set reach group determination random number determination table and the reach group determination random number stored in the target storage unit in step S535-13.

(Step S536-17)
The main CPU 300a sets the losing reach mode determination random number determination table (see FIG. 10A) corresponding to the group type provisionally determined in step S536-15, and shifts the process to step S536-19.

(Step S536-19)
The main CPU 300a determines the variation mode number based on the reach mode determination random number determination table set in step S536-9 or step S536-17 and the reach mode determination random number stored in the target storage unit in step S535-13. provisionally determined. Further, here, along with the variation mode number, a variation pattern random number determination table is tentatively determined.

(Step S536-21)
The main CPU 300a sets, in the transmission buffer, the prefetch designation variation mode command (prefetch designation command) corresponding to the variation mode number tentatively determined in step S536-19.

(Step S536-23)
The main CPU 300a temporarily determines the variation pattern number based on the variation pattern random number determination table provisionally determined in step S536-19 and the variation pattern random number stored in the target storage unit in step S535-13.

(Step S536-25)
The main CPU 300a sets the look-ahead specified variation pattern command (pre-read specification command) corresponding to the variation pattern number tentatively determined in step S536-23 in the transmission buffer, and ends the effect determination process at the time of acquisition.

(Step S536-27)
The main CPU 300a, regarding the suspension newly stored in the target storage unit, according to the number of suspensions when the suspension is read out, changes the group type, that is, the variable effect pattern (undefined value command (prefetch Specified variation mode command and look-ahead specified variation pattern command = 7FH) is set in the transmission buffer, and the effect determination process at the time of acquisition is terminated.

FIG. 34 is a flowchart for explaining the big winning opening passage processing (step S540) in the main control board 300 according to the simultaneous spinning reference example.

(Step S540-1)
When the main CPU 300a determines in step S500-13 that the large winning opening detection switch is turned on, it loads a special electric accessory game management phase, which will be described later in detail. In addition, although it will be described later in detail, the special electric role product game management phase indicates the stage of execution processing of the big role game or the small winning game, that is, the progress status of the big role game or the small winning game. It is updated according to the stage of the execution process of the winning game.

(Step S540-3)
The main CPU 300a determines whether or not the special electric role product game management phase loaded in step S540-1 indicates the stage of the execution process above the big winning hole opening pre-process. The special electric accessory game management phase is provided with 9 stages from 00H to 08H. Of these, 01H to 08H correspond to the stage of execution processing above the big winning opening pre-opening processing. Since the big win game or the small winning game is executed when the special electric role product game management phase is 01H to 08H, it is determined whether it is currently in the big winning game or the small winning game. Become. If it is determined that the special electric role product game management phase indicates the stage of execution processing above the big winning opening pre-processing, the process is moved to step S540-5, and the special electric role product game management phase is If it is determined that it does not indicate the stage of the execution process above the big winning opening pre-opening process, the process proceeds to step S540-7.

(Step S540-5)
The main CPU 300a sets, in the transmission buffer, a big winning hole entry command indicating that the game ball has properly entered the first big winning hole 126 or the second big winning hole 128, and ends the big winning hole passage processing. .

(Step S540-7)
The main CPU 300a determines that the entry of the game ball into the first big winning hole 126 or the second big winning hole 128 is inappropriate, executes a predetermined error process, and ends the big winning hole passing process.

FIG. 35 is a diagram for explaining the special game management phase according to the simultaneous spinning reference example. As already explained, in the simultaneous turning reference example, the special game triggered by the entry of the game ball to the first start port 120 or the second start port 122, the passage of the game ball to the gate 124 or the normal figure operation port A normal game triggered by the entry of a game ball into 125 progresses in parallel. The processing related to the special game is executed step by step and repeatedly, but in the main control board 300, each processing related to such a special game is managed by a special game management phase and a special electric accessory game management phase. .

As shown in FIG. 35, the main ROM 300b stores a plurality of special game control modules for executing and controlling the variable display of special symbols in the special game. Management phase is associated. Specifically, when the special game management phase is "00H", a module for executing the "special symbol variation waiting process" is called, and when the special game management phase is "01H", A module for executing a "special symbol fluctuating process" is called, and when the special game management phase is "02H", a module for executing a "special symbol stop symbol display process" is called.

Also, the main ROM 300b stores a plurality of special electric role product game control modules for executing and controlling the big win game and the small winning game among the special games, and for each of these special electric role product game control modules, A special electric accessory game management phase is associated. Specifically, when the special electric role product game management phase is "01H" or "05H", a module for executing the "pre-processing for opening the big prize opening" is called, and the special electric role product game management is performed. When the phase is ``02H'' or ``06H'', a module for executing the ``large winning opening opening control process'' is called, and the special electric accessory game management phase is ``03H'' or ``07H''. In this case, a module for executing the "large winning opening closing effective process" is called, and when the special electric role product game management phase is "04H" or "08H", the "big winning opening closing wait process ” is called. In addition, when the special electric role product game management phase is "00H", none of the special electric role product game control modules are called.

FIG. 36 is a flowchart for explaining the special game management process (step S600) in the main control board 300 according to the simultaneous spinning reference example.

(Step S600-1)
The main CPU 300a loads the special electric accessory game management phase.

(Step S600-3)
The main CPU 300a determines whether the special electric role product game management phase loaded in step S600-1 is other than "00H". That is, here, it is determined whether it is currently in the big win game or in the small winning game. If it is determined that the special electric role product game management phase is other than "00H", the special game management process is terminated, and if it is determined that the special electric role product game management phase is not other than "00H", step S600. -5 is processed.

(Step S600-5)
The main CPU 300a loads a special game special symbol determination flag. It should be noted that the special game special symbol determination flag is for determining whether the special game special symbol determination flag (00H ) indicates special 1 suspension, and the special game special symbol determination flag (01H) indicates special 2 suspension.

(Step S600-7)
The main CPU 300a inverts the special game special symbol determination flag loaded in step S600-5. Here, when the special game special symbol determination flag is "00H", it is reversed to "01H", and when the special game special symbol determination flag is "01H", it is reversed to "00H". Since the initial value of the special game special symbol determination flag is set to "00H", the special game special symbol determination is performed in the first special game management process S600 of the two special game management processes S600 shown in FIG. The flag is set to "01H", the subsequent processing is executed for the special 2 reservation, the special game special symbol determination flag is set to "00H" in the second special game management processing S600, and the subsequent processing is executed for the special 1 reservation. be done. In other words, the special 2 reservation is preferentially processed.

(Step S600-9)
The main CPU 300a saves the special game special symbol determination flag reversed in step S600-7.

(Step S600-11)
The main CPU 300a loads the special game management phase.

(Step S600-13)
The main CPU 300a selects the special game control module corresponding to the special game management phase loaded in step S600-11.

(Step S600-15)
The main CPU 300a calls the special game control module selected in step S600-13 and starts processing.

(Step S600-17)
The main CPU 300a loads a special game timer that manages the special game control time, and terminates the special game management process.

FIG. 37 is a flowchart for explaining the special symbol variation waiting process in the main control board 300 according to the simultaneous turning reference example. This special symbol variation waiting process is executed when the special game management phase is "00H".

(Step S610-1)
The main CPU 300a determines whether or not the number of special symbol reserved balls of the reservation (special 1 reservation or special 2 reservation, hereinafter referred to as target reservation) subject to special game management processing is 1 or more. As a result, when it is determined that the number of special symbol reserved balls is 1 or more, the process is moved to step S610-3, and when it is determined that the number of special symbol reserved balls is not 1 or more, the special symbol variation waiting process exit.

(Step S610-3)
The main CPU 300a is finalizing a special symbol (hereinafter referred to as a non-target special symbol) based on a suspension (special 2 suspension or special 1 suspension, hereinafter referred to as non-target suspension) that is not subject to special game management processing. Determine if there is As a result, when it is determined that the non-target special symbol is being determined, the process is shifted to step S610-5, and when it is determined that the special symbol based on the non-target special symbol is not being determined, step S610-9. to process.

(Step S610-5)
The main CPU 300a determines whether the non-target special symbol is a jackpot symbol. As a result, when it is determined that it is a jackpot pattern, the special symbol variation waiting process is terminated, and when it is determined that it is not a jackpot pattern, the process is moved to step S610-7.

(Step S610-7)
The main CPU 300a determines whether the non-target special symbol is a small winning symbol. As a result, when it is determined that it is a small winning pattern, the special symbol variation waiting process is terminated, and when it is determined that it is not a small winning pattern, the process is moved to step S610-9.

(Step S610-9)
The main CPU 300a block-transfers the target suspension stored in the first to fourth storage units of the special figure suspension storage area corresponding to the target suspension to the storage unit with a smaller ordinal number. Specifically, the object holds stored in the second to fourth storage units are transferred to the first to third storage units. In addition, the main RAM 300c is provided with a 0th storage unit to be processed, and the object suspension stored in the 1st storage unit is block-transferred to the 0th storage unit. In addition, in this special symbol storage area shift process, the counter value of the target special symbol retention ball number counter corresponding to the target retention is decremented by "1", and the retention decrement indicating that the target retention is decremented by "1" Sets the specified command in the transmission buffer.

(Step S611)
The main CPU 300a executes a special symbol hit determination process for performing a big winning lottery. This special symbol hitting determination processing will be described later.

(Step S610-11)
The main CPU 300a executes special symbol determination processing for determining special symbols. Here, if the result of the big win lottery in step S611 is a big win or a small win, the winning symbol random number and the reserved type transferred to the 0th storage unit are loaded, and the corresponding winning symbol random number judgment table or small winning symbol is loaded. A random number determination table is selected to extract special symbol determination data, and the extracted special symbol determination data (type of jackpot symbol) is saved. Further, when the result of the big winning lottery in step S611 is a loss, the special symbol determination data for a loss is saved. After saving the special symbol determination data, a symbol type designation command corresponding to the special symbol determination data is set in the transmission buffer.

(Step S610-13)
The main CPU 300a saves the special symbol stop symbol number corresponding to the special symbol determination data extracted in step S610-11. In addition, the first special symbol display 160 and the second special symbol display 162 are each composed of 7 segments, and each segment constituting the 7 segments is associated with a number (counter value). The special symbol stop symbol number determined here indicates the number (counter value) of the segment that is finally lit.

(Step S612)
The main CPU 300a executes a special symbol variation number determination process for determining a variation mode number and a variation pattern number. The details of this special symbol variation number determination process will be described later.

(Step S610-15)
The main CPU 300a loads the variation mode number and variation pattern number determined in step S612, and determines variation time 1 and variation time 2 with reference to the variation time determination table. Then, the total time of the determined variable times 1 and 2 is set in the special symbol variable timer.

(Step S610-17)
The main CPU 300a determines whether or not the result of the big win lottery is a big win, and if it is a big win, loads the special symbol determination data saved in step S610-11 and confirms the type of the big win symbol. do. Then, with reference to the game state setting table and the current game state, to determine the game state and the high probability number of times to be set after the end of the big role game, the number of times of time reduction, the determination result is the special pattern probability state preliminary flag, time reduction state preliminary Save to the flag, high-precision cut spare counter, and time-saving cut spare counter. It should be noted that, when the lost pattern is saved, the process proceeds to the next process without executing the process.

(Step S610-19)
The main CPU 300a executes a process of setting a special symbol display symbol counter in the first special symbol display device 160 or the second special symbol display device 162 in order to start variable display of special symbols. A counter value is associated with each segment of the 7 segments that constitute the first special symbol display device 160 and the second special symbol display device 162, and the segment corresponding to the counter value set in the special symbol display symbol counter is Lighting is controlled. Here, the counter value corresponding to the segment to be lit at the start of the variable display of the special symbols is set in the special symbol display symbol counter. As for the special symbol display symbol counter, a special symbol 1 display symbol counter corresponding to the first special symbol display device 160 and a special symbol 2 display symbol counter corresponding to the second special symbol display device 162 are separately provided. Here, the counter value is set to the counter corresponding to the hold type.

(Step S613)
The main CPU 300a executes a number cutting management process. Here, processing for ending the time-saving gaming state is performed according to the number of fluctuations. This number cutting management process will be described later.

(Step S610-21)
The main CPU 300a sets a frequency command indicating the remaining frequency (actual remaining frequency) until the high probability frequency and the time saving frequency become 0 in the transmission buffer.

(Step S610-23)
The main CPU 300a sets a game state change designation command indicating the game state at the start of the variable display of special symbols in the transmission buffer.

(Step S610-25)
The main CPU 300a updates the special game management phase to "01H" and terminates the special symbol variation waiting process.

FIG. 38 is a flowchart for explaining the special symbol hit determination process (S611) according to the simultaneous spinning reference example.

(Step S611-1)
The main CPU 300a loads the special symbol probability state flag.

(Step S611-3)
The main CPU 300a loads the registered setting values in the setting value buffer.

(Step S611-5)
The main CPU 300a determines whether the registered set value loaded in step S611-3 is within the normal range. As a result, when it is determined that the value is within the normal range, the process proceeds to step S611-11, and when it is determined that the value is not within the normal range, the process proceeds to step S611-7.

(Step S611-7)
The main CPU 300a sets the gaming machine state flag to 03H (set abnormal state).

(Step S611-9)
The main CPU 300a sets the setting abnormal state command (subcommand) in the transmission buffer, and terminates the special symbol hit determination process. When this abnormal setting state command is transmitted to the sub control board 330, notification of the abnormal setting is made.

(Step S611-11)
The main CPU 300a refers to the big win determination random number determination table corresponding to the information loaded in steps S611-1 and S611-3, and sets the lower limit and upper limit when determining a big win or a small win.

(Step S611-13)
The main CPU 300a compares the jackpot determination random number transferred to the 0th storage unit with the above-described lower and upper limit values, and performs determination processing (big win lottery) to determine whether or not a jackpot or small win has been won.

(Step S611-15)
The main CPU 300a determines whether the non-target special symbol is a jackpot symbol. As a result, when it is determined to be a jackpot pattern, the process moves to step S611-17, and when it is determined not to be a jackpot pattern, the process moves to step S611-21.

(Step S611-17)
The main CPU 300a determines whether the big winning lottery result in step S611-13 is a small win or a loss. As a result, if it is determined to be a small win or a loss, the process moves to step S611-21, and if it is determined to be neither a small win nor a loss, the process moves to step S611-19.

(Step S611-19)
The main CPU 300a changes the big role lottery result in step S611-13 to lose.

(Step S611-21)
The main CPU 300a sets the result of the determination process in step S611-13 or the result changed in step S611-19 as determination information, and ends the special symbol win determination process.

FIG. 39 is a flowchart for explaining the special symbol variation number determination process (step S612) in the main control board 300 according to the simultaneous turning reference example.

(Step S612-1)
The main CPU 300a determines whether the result of the big win lottery in step S611 is a big win or a small win. As a result, when it is determined that it is a big hit or a small hit, the process is moved to step S612-3, and when it is determined that it is neither a big hit nor a small hit (it is a loss), the process goes to step S612-5. Transfer.

(Step S612-3)
The main CPU 300a sets a ready-to-win mode determination random number determination table corresponding to the current gaming state and pending type.

(Step S612-5)
The main CPU 300a confirms the counter value of the special symbol 2 reserved ball number counter when the read reservation type is Special 2 reservation, and when the read reservation type is Special 1 reservation, Check the counter value of the special symbol 1 reserved ball number counter.

(Step S612-7)
The main CPU 300a sets the corresponding reach group determination random number determination table based on the current gaming state, the number of pending games confirmed in step S612-5, and the type of pending game. Then, the reach group (group type) is determined based on the set reach group determination random number determination table and the reach group determination random number transferred to the 0th storage unit in step S610-9.

(Step S612-9)
The main CPU 300a sets the reach mode determination random number determination table at the time of losing corresponding to the group type determined in step S612-7.

(Step S612-11)
The main CPU 300a determines the variable mode based on the reach mode determination random number determination table set in step S612-3 or step S612-9 and the reach mode determination random number transferred to the 0th storage unit in step S610-9. Decide on a number. Also, here, along with the variation mode number, a variation pattern random number determination table is determined.

(Step S612-13)
The main CPU 300a sets the variable mode command corresponding to the variable mode number determined in step S612-11 in the transmission buffer.

(Step S612-15)
The main CPU 300a determines the variation pattern number based on the variation pattern random number determination table determined in step S612-11 and the variation pattern random number transferred to the 0th storage unit in step S610-9.

(Step S612-17)
The main CPU 300a sets the variation pattern command corresponding to the variation pattern number determined in step S612-15 in the transmission buffer, and terminates the special symbol variation number determination process.

FIG. 40 is a flowchart for explaining the number cutting management process (step S613) in the main control board 300 according to the simultaneous rotation reference example.

(Step S613-1)
The main CPU 300a determines whether or not the number of times of time saving, that is, the counter value of the time saving number cutting counter is greater than zero. As a result, when it is determined that the number of times of time saving is greater than 0, the process proceeds to step S613-3, and when it is determined that the number of times of time saving is 0, the number cutting management process is ended.

(Step S613-3)
The main CPU 300a decrements the time-saving cut-off counter.

(Step S613-5)
The main CPU 300a determines whether the counter value (number of times of time saving) has been updated to 0 in step S613-3. As a result, when it is determined that the number of times of time saving is 0, the process proceeds to step S613-7, and when it is determined that the number of times of time saving is not 0, the number cutting management process ends.

(Step S613-7)
The main CPU 300a sets the time saving state flag in order to set the normal game state to the non time saving game state. As a result, after the normal game state is set to the time-saving game state, the normal game state is changed to a non-time-saving game state at the start of fluctuation when the number of fluctuations reaches the time-saving number of times (here, 50 times or 100 times). The Rukoto. For example, if it is set to the highly probable portent state, it will be set to the highest priority state.

(Step S613-9)
The main CPU 300a turns on the time saving end flag and ends the number cutting management process.

FIG. 41 is a flow chart for explaining the processing during special symbol fluctuation in the main control board 300 according to the simultaneous turning reference example.

(Step S620-1)
The main CPU 300a determines whether the interrupted flag is on. Although details will be described later, in the simultaneous spinning reference example, while the first special symbol display 160 is displaying the symbols fluctuating, the second special symbol display 162 may stop displaying the small winning symbols. In this case, when the small winning symbol is stopped and displayed on the second special symbol display device 162, the small winning game is executed. , After the end of the small winning game, the variable display of the symbols on the first special symbol display device 160 is resumed. The interrupted flag is turned on when the first special symbol display 160 is in the process of changing symbols when the small winning symbol is stopped and displayed on the second special symbol display 162 . Here, when it is determined that the interrupting flag is ON, the special symbol variation process is ended, and when it is determined that the interrupting flag is not ON, the process is moved to step S620-3.

(Step S620-3)
The main CPU 300a executes processing for updating the special symbol variation base counter. In addition, the counter value of the special symbol variation base counter is set so as to make one round at a predetermined period (for example, 100 ms). Specifically, when the counter value of the special symbol variation base counter is "0", a predetermined counter value (for example, 25) is set, and when the counter value is "1" or more, Update the counter value to the value obtained by subtracting "1" from the current counter value.

(Step S620-5)
The main CPU 300a determines whether the counter value of the special symbol variation base counter updated in step S620-3 is "0". As a result, if the counter value is "0", the process proceeds to step S620-7, and if the counter value is not "0", the process proceeds to step S620-11.

(Step S620-7)
The main CPU 300a performs a special symbol variation timer update process of subtracting a predetermined value from the timer value of the special symbol variation timer set in step S610-15.

(Step S620-9)
The main CPU 300a determines whether the timer value of the special symbol variation timer updated in step S620-7 is "0". As a result, if the timer value is "0", the process moves to step S620-17, and if the timer value is not "0", the process moves to step S620-11.

(Step S620-11)
The main CPU 300a updates the special symbol display timer that counts the lighting time of each segment of the 7 segments that constitute the first special symbol display 160 and the second special symbol display 162. FIG. Specifically, when the timer value of the special symbol display timer is "0", a predetermined timer value is set, and when the timer value is "1" or more, from the current timer value Update the timer value to the value decremented by "1".

(Step S620-13)
The main CPU 300a determines whether the timer value of the special symbol display timer is "0". As a result, when it is determined that the timer value of the special symbol display timer is "0", the processing is moved to step S620-15, and when it is determined that the timer value of the special symbol display timer is not "0", the End the process during special symbol fluctuation.

(Step S620-15)
The main CPU 300a updates the counter value of the special symbol display symbol counter to be updated, and ends the special symbol changing process. As a result, the segments that make up the 7 segments are sequentially lit at predetermined time intervals.

(Step S620-17)
The main CPU 300a determines whether or not the non-target special symbol is being variably displayed. As a result, when it is determined that the non-target special symbol is being variably displayed, the process is moved to step S621, and when it is determined that the non-target special symbol is not being variably displayed, the process is moved to step S620-19.

(Step S621)
The main CPU 300a executes symbol forced stop processing. This symbol forced stop processing will be described later with reference to FIG.

(Step S620-19)
The main CPU 300a updates the special game management phase to "02H".

(Step S620-21)
The main CPU 300a saves the special symbol stop symbol number (counter value) determined in step S610-13 in the target special symbol display symbol counter. As a result, the determined special symbol is stop-displayed on the first special symbol display 160 or the second special symbol display 162 .

(Step S620-23)
The main CPU 300a sets a special symbol stop designation command indicating that the special symbols are stopped and displayed on the first special symbol display device 160 or the second special symbol display device 162 in the transmission buffer.

(Step S620-25)
The main CPU 300a sets the special symbol variation stop time, which is the time during which the special symbols are stopped and displayed, in the special game timer, and terminates the special symbol variation process.

FIG. 42 is a flowchart for explaining the pattern forced stop processing (step S621) in the main control board 300 according to the simultaneous rotation reference example.

(Step S621-1)
The main CPU 300a determines whether the special symbol that is being displayed (in question) is a small winning symbol. As a result, when it is determined that it is a small winning pattern, the process is moved to step S621-3, and when it is determined that it is not a small winning pattern, the process is moved to step S621-11.

(Step S621-3)
The main CPU 300a determines whether the special game special symbol determination flag is 00H, that is, whether the small winning symbol is stopped and displayed on the first special symbol display device 160 or not. As a result, when it is determined that the special game special symbol determination flag is 00H, the process is moved to step S621-11, and when it is determined that the special game special symbol determination flag is not 00H, the process proceeds to step S621-5. to move.

(Step S621-5)
The main CPU 300a determines whether the (other) special symbol during variable display is a jackpot symbol. As a result, when it is determined that it is a jackpot pattern, the process is shifted to step S621-11, and when it is determined that it is not a jackpot pattern, the process is shifted to step S621-7.

(Step S621-7)
The main CPU 300a turns on the interrupted flag.

(Step S621-9)
The main CPU 300a executes a fluctuation interruption process for interrupting the fluctuation display of the special symbols, and terminates the forced symbol stop process. Here, a process of temporarily saving the remaining time of the fluctuation time and the information related to the special symbol in a predetermined storage area is performed.

(Step S621-11)
The main CPU 300a forces the first special symbol display device 160 or the second special symbol display device 162 on which the symbols are displayed to variably stop losing symbols, and forcibly terminates the remaining variation time. A process for turning on the stop flag is performed, and the symbol forced stop process is terminated.

By the above processing, when the small winning symbol is stop-displayed on the first special symbol display 160, the second special symbol display 162 is forcibly stopped-displayed the losing symbol. Further, when the small winning design is stop-displayed on the second special design display device 162, if the big winning design is finally stopped and displayed on the first special design display device 160 during the variable display, the first special design display. A lost symbol is displayed on the device 160 for forced stop. On the other hand, when the small winning design is stop-displayed on the second special design display device 162, if the small winning design or the losing design is in the fluctuation display that is finally stopped and displayed on the first special design display device 160, the second The variable display on the 1 special symbol display 160 is temporarily interrupted.

FIG. 43 is a flowchart for explaining a special symbol stop symbol display process in the main control board 300 according to the simultaneous rotation reference example.

(Step S630-1)
The main CPU 300a determines whether the timer value of the special game timer set in step S620-25 is not "0". As a result, when it is determined that the timer value of the special game timer is not "0", the special symbol stop symbol display process is terminated, and when it is determined that the timer value of the special game timer is "0". The process moves to step S630-3.

(Step S630-3)
The main CPU 300a determines whether the variable time special stop flag is ON. As a result, when it is determined that the variable time special stop flag is ON, the process is moved to step S630-5, and when it is determined that the variable time special stop flag is not ON, the special symbol stop symbol display process is terminated. do.

(Step S630-5)
The main CPU 300a confirms the result of the big role lottery.

(Step S630-7)
The main CPU 300a determines whether the result of the big role lottery is a loss. As a result, if it is determined to be a loss, the process moves to step S630-27, and if it is determined to be not a loss, the process moves to step S630-9.

(Step S630-9)
The main CPU 300a performs a game state update process for updating the game state. Here, the game state is set to the initial state when the special symbol being stopped and displayed is a big winning symbol, and when the special symbol being stopped and displayed is a small winning symbol, the next processing is performed as it is.

(Step S630-11)
The main CPU 300a sets the data of the special electric accessary product operating ram set table according to the determined special symbol type. Note that the main CPU 300a turns off the variable time special stop flag when it is on.

(Step S630-13)
The main CPU 300a performs a special electric accessary product maximum number of times setting process. Specifically, referring to the data set in the above step S630-11, a predetermined number (counter value corresponding to the type of special symbol = number of rounds) is set as a counter value in the special electric accessory maximum operation counter. . It should be noted that this special electric accessory maximum operation number counter indicates the number of rounds that can be executed in the big winning game to be started from now on. On the other hand, the main RAM 300c is provided with a special electric accessory continuous operation number counter, and at the start of each round game, by adding "1" to the counter value of the special electric accessory continuous operation number counter, the current The number of round games is managed. Here, a process of resetting (updating to "0") the counter value of the special electric role product continuous operation number counter is executed together with the start of the big winning game.

(Step S630-15)
The main CPU 300a refers to the data set in step S630-11 and saves a predetermined opening time as a timer value in the special electric accessory game timer.

(Step S630-17)
The main CPU 300a sets an opening designation command for transmitting the start of the big win game to the sub control board 330 in the transmission buffer.

(Step S630-19)
The main CPU 300a updates the special electric role product game management phase to "01H" when starting the big win game, and updates the special electric role product game management phase to "05H" when starting the small winning game. .

(Step S630-21)
The main CPU 300a updates the special game management phase to "00H".

(Step S630-23)
The main CPU 300a determines whether the special electric role product game management phase updated in step S630-19 is "01H", that is, whether it is a big win. As a result, when it is determined that the special electric role product game management phase is "01H", the process is shifted to step S630-25, and when it is determined that the special electric role product game management phase is not "01H" , the process moves to step S630-27.

(Step S630-25)
The main CPU 300a performs a jackpot signal output start process for outputting a jackpot signal from the game information output terminal plate 312, and ends the special symbol stop symbol display process. By this process, a big hit signal is output with the start of the big win game (opening). Although a plurality of signals are provided to be output from the game information output terminal board 312, only a predetermined jackpot signal will be described here.

(Step S630-27)
The main CPU 300a sets, in the transmission buffer, a game state confirmation designation command at the time of special symbol determination, which indicates the game state when the special symbol is determined.

(Step S630-29)
The main CPU 300a determines whether the time saving end flag is turned on. As described above, the time saving end flag is turned on in step S613-9 of FIG. 40 at the start of fluctuation when changing from the time saving game state to the non-time saving game state. That is, if the time saving end flag is turned on here, at the time of the 50th or 100th fluctuation start in the high probability omen state, the normal game state is changed from the time saving game state to the non-time saving game state due to the time saving omission is the case. That is, here, it is determined that the time saving end flag is ON only when the fluctuation at the time of time saving time ends. If it is determined that the time saving end flag is turned on, the process moves to step S630-31, and if it is determined that the time saving end flag is not turned on, the process moves to step S630-35.

(Step S630-31)
The main CPU 300 a performs jackpot signal output stop processing for stopping the jackpot signal output from the game information output terminal plate 312 . That is, the jackpot signal is output during the big win game or during the time saving game state.

(Step S630-33)
The main CPU 300a turns off the time saving end flag.

(Step S630-35)
The main CPU 300a updates the special game management phase to "00H" and terminates the special symbol stop symbol display process.

FIG. 44 is a flowchart for explaining the special electric role product game management process (step S700) in the main control board 300 according to the simultaneous turning reference example.

(Step S700-1)
The main CPU 300a loads the special electric accessory game management phase.

(Step S700-3)
The main CPU 300a determines whether the special electric role product game management phase loaded in step S700-1 is "00H". That is, here, it is now determined whether or not during the big win game and during the small winning game. When it is determined that the special electric role product game management phase is "00H", the special electric role product game management process is terminated, and when it is determined that the special electric role product game management phase is not "00H", step The process moves to S700-5.

(Step S700-5)
The main CPU 300a selects the special electric role product game control module corresponding to the special electric role product game management phase loaded in step S700-1.

(Step S700-7)
The main CPU 300a calls the special electric accessory game control module selected in step S700-5 and starts processing.

(Step S700-9)
The main CPU 300a loads a special electric role product game timer that manages the control time of the special electric role product game, and ends the special electric role product game management process.

FIG. 45 is a flowchart for explaining the big winning opening pre-opening process in the main control board 300 according to the simultaneous spinning reference example. This big winning hole pre-opening process is executed when the special electric role product game management phase is "01H" and "05H".

(Step S710-1)
The main CPU 300a determines whether the timer value of the special electric role product game timer set in step S630-15 or the like is not "0". As a result, when it is determined that the timer value of the special electric role-playing game timer is not "0", the big winning opening pre-opening process is terminated, and the timer value of the special electric role-playing game timer is "0". If so, the process moves to step S710-3.

(Step S710-3)
The main CPU 300a updates the counter value of the special electric accessory continuous operation number counter to a value obtained by adding "1" to the current counter value.

(Step S710-5)
The main CPU 300a sets, in the transmission buffer, a command for specifying the opening of the large winning opening (the start of the round game) to the sub-control board 330. FIG.

(Step S711)
The main CPU 300a executes the big winning opening opening/closing switching process. This special winning opening opening/closing switching process will be described later.

(Step S710-7)
The main CPU 300a updates the special electric role product game management phase to a value obtained by adding 01H to the current value ("02H" or "06H"), and terminates the pre-opening processing for the big winning opening.

FIG. 46 is a flowchart for explaining the big winning opening open/close switching process (S711) in the main control board 300 according to the simultaneous spinning reference example.

(Step S711-1)
The main CPU 300a determines whether the counter value of the special electric role product opening/closing switching frequency counter is the upper limit value of the special electric role product opening/closing switching frequency (the number of opening/closing times of the big winning opening during one round game). As a result, when it is determined that the counter value is the upper limit value, the big winning opening opening/closing switching process is terminated, and when it is determined that the counter value is not the upper limit value, the process is shifted to step S711-3.

(Step S711-3)
The main CPU 300a refers to the data in the special electric role product operating ramset table, and energizes the first big prize opening solenoid 126c and the second big prize opening solenoid 128c based on the counter value of the special electric role product opening/closing switching frequency counter. Solenoid control data for control and time data representing the energization time or energization stop time are extracted.

(Step S711-5)
Based on the solenoid control data extracted in step S711-3, the main CPU 300a starts energizing the first big winning opening solenoid 126c or the second big winning opening solenoid 128c, or determines whether to stop the energization. Winning opening solenoid energization control processing is executed. By executing this big winning opening solenoid energization control process, in steps S400-33 and S400-35, energization start or stop of the first big winning opening solenoid 126c or the second big winning opening solenoid 128c is controlled. It will happen.

(Step S711-7)
The main CPU 300a saves the timer value based on the time data extracted in step S711-3 in the special electric accessory game timer. It should be noted that the timer value saved in the special electric accessory game timer here is the maximum opening time for one time of the big winning opening.

(Step S711-9)
The main CPU 300a determines whether the energization of the first big winning opening solenoid 126c or the second big winning opening solenoid 128c is started, that is, the first big winning opening solenoid 126c or the second big winning opening solenoid 128c in step S711-5. It is determined whether a control process for starting energization has been performed. As a result, when it is determined that it is in the energization start state, the process is moved to step S711-11, and when it is determined that it is not in the energization start state, the big winning opening opening/closing switching process is ended.

(Step S711-11)
The main CPU 300a updates the counter value of the special electric accessory opening/closing switching frequency counter to a value obtained by adding "1" to the current counter value, and ends the big winning opening opening/closing switching process.

FIG. 47 is a flowchart for explaining the big winning opening opening control process in the main control board 300 according to the simultaneous spinning reference example. This big winning opening control process is executed when the special electric role product game management phase is "02H" or "06H".

(Step S720-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer saved in step S711-7 is not "0". As a result, if it is determined that the timer value of the special electric auditors game timer is not "0", the process is shifted to step S720-5, and it is determined that the timer value of the special electric auditors game timer is "0". If so, the process moves to step S720-3.

(Step S720-3)
The main CPU 300a determines whether the counter value of the special electric accessory opening/closing switching frequency counter is the upper limit value of the special electric accessory opening/closing switching frequency. As a result, if it is determined that the counter value is the upper limit value, the process moves to step S720-7, and if it is determined that the counter value is not the upper limit value, the process moves to step S711.

(Step S711)
In the above step S720-3, when it is determined that the counter value of the special electric role product open/close switching frequency counter is not the upper limit value of the special electric role product opening/closing switching frequency, the main CPU 300a executes the processing of step S711. do.

(Step S720-5)
The main CPU 300a determines whether the counter value of the big winning hole winning ball number counter updated in step S500-9 has reached the specified number. It is determined whether or not the game ball has entered. As a result, when it is determined that the specified number has not been reached, the big winning opening opening control process is terminated, and when it is determined that the specified number has been reached, the process proceeds to step S720-7.

(Step S720-7)
The main CPU 300a stops the energization of the first big winning opening solenoid 126c or the second big winning opening solenoid 128c, and executes the big winning opening closing process necessary to close the big winning opening. As a result, the big winning opening is closed.

(Step S720-9)
The main CPU 300a saves the large winning opening closing valid time (interval time) in the special electric accessory game timer.

(Step S720-11)
The main CPU 300a updates the special electric role product game management phase to a value obtained by adding 01H to the current value ("03H" or "07H").

(Step S720-13)
The main CPU 300a sets, in the transmission buffer, a large winning opening closing designation command indicating that the large winning opening is closed, and ends the special winning opening opening control process.

FIG. 48 is a flowchart for explaining the large winning opening closing effective process in the main control board 300 according to the simultaneous spinning reference example. This big winning opening closing valid process is executed when the special electric role product game management phase is "03H" or "07H".

(Step S730-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer saved in step S720-9 is not "0". As a result, when it is determined that the timer value of the special electric role-playing game timer is not "0", the big winning opening closing effective process is terminated, and the timer value of the special electric role-playing game timer is "0". If so, the process moves to step S730-3.

(Step S730-3)
The main CPU 300a determines whether the counter value of the special electric role product continuous operation frequency counter matches the counter value of the special electric role product maximum operation frequency counter, that is, whether the preset number of round games has ended. . As a result, if it is determined that the counter value of the special electric accessory continuous operation number counter matches the counter value of the special electric accessory maximum operation number counter, the process is moved to step S730-9, and if it is determined that they do not match to step S730-5.

(Step S730-5)
The main CPU 300a updates the special electric accessory game management phase to "01H". In addition, when the special electric role product game management phase is 07H, that is, during the control of the small winning game, the number of round games of the small winning game is "1", so the step S730-3 is always YES. It is determined, and the process does not move to the step concerned.

(Step S730-7)
The main CPU 300a saves a predetermined large winning opening closing time in the special game timer, and ends the special winning opening closing effective process. As a result, the next round game is started.

(Step S730-9)
The main CPU 300a executes an ending time setting process for saving the ending time in the special electric accessory game timer.

(Step S730-11)
The main CPU 300a updates the special electric accessory game management phase to a value obtained by adding 01H to the current value ("04H" or "08H").

(Step S730-13)
The main CPU 300a sets an ending designation command indicating the start of the ending in the transmission buffer, and terminates the special winning opening closing enable process.

FIG. 49 is a flowchart for explaining the big winning opening end wait process in the main control board 300 according to the simultaneous spinning reference example. This big winning opening end wait process is executed when the special electric role product game management phase is "04H" or "08H".

(Step S740-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer saved in step S730-9 is not "0". As a result, when it is determined that the timer value of the special electric role-playing game timer is not "0", the big winning opening end wait process is terminated, and the timer value of the special electric role-playing game timer is "0". If so, the process moves to step S740-3.

(Step S740-3)
The main CPU 300a determines whether the special electric role product game management phase is "08H", that is, whether the small winning game is finished. As a result, when it is determined that the special electric role product game management phase is "08H", the process is moved to step S740-11, and when it is determined that the special electric role product game management phase is not "08H" The process moves to step S740-5.

(Step S740-5)
The main CPU 300a executes state setting processing for setting the game state after the end of the big win game. Here, the game state set in the preliminary area in step S610-17, the number of times of high accuracy, and the number of times of time saving are loaded, and the setting of each flag and the counter value are set as the game state after the big win game.

(Step S740-7)
The main CPU 300a determines whether or not the normal game state has been set to the non-time-saving game state in step S740-5. As a result, when it is determined that the non-time-saving gaming state has been set, the process proceeds to step S740-9, and when it is determined that the non-time-saving gaming state is not set, the process proceeds to step S740-21.

(Step S740-9)
The main CPU 300 a performs jackpot signal output stop processing for stopping the jackpot signal output from the game information output terminal plate 312 . That is, when the highest priority state is set after the big win game, the output of the big win signal is stopped with the end of the big win game.

(Step S740-11)
The main CPU 300a determines whether the current gaming state is a high-probability precursor state (high-probability gaming state and time-saving gaming state). As a result, if it is determined that the state is a highly probable portent state, the process proceeds to step S740-13, and if it is determined that the state is not a highly probable portent state, the process proceeds to step S740-21.

(Step S740-13)
The main CPU 300a determines whether or not the stop-displayed small winning symbol is the special symbol Z1. As a result, when it is determined that it is the special design Z1, the process is moved to step S740-15, and when it is determined that it is not the special design Z1, the process is moved to step S740-21.

(Step S740-15)
The main CPU 300a sets a time saving state flag in order to change the normal game state to a non time saving game state. As a result, when the special symbol Z1 is determined in the high-probability portent state, the game state is changed to the most dominant state at the end of the small winning game.

(Step S740-17)
The main CPU 300a performs a counter reset process for resetting the time saving number counter.

(Step S740-19)
The main CPU 300 a performs jackpot signal output stop processing for stopping the jackpot signal output from the game information output terminal plate 312 . That is, when the special symbol Z1 is won and the highest priority state is set after the small winning game is played, the output of the big winning signal is stopped when the small winning game ends.

(Step S740-21)
The main CPU 300a sets, in the transmission buffer, a game state change designation command for transmitting the game state to be set after the end of the big win game.

(Step S740-23)
The main CPU 300a sets a frequency command corresponding to the high accuracy frequency and the time saving frequency in the transmission buffer.

(Step S740-25)
The main CPU 300a updates the special electric role product game management phase to "00H", and ends the big winning opening end wait process. As a result, when special 1 suspension or special 2 suspension is stored, the variable display of the symbols is resumed.

FIG. 50 is a diagram for explaining the normal game management phase according to the simultaneous spinning reference example. As already explained, in the simultaneous turning reference example, the processing related to the normal game triggered by the passage of the game ball to the gate 124 or the entry of the game ball to the normal pattern operation port 125 is stepwise and repeated. Although it is executed, in the main control board 300, each process related to such a normal game is managed by the normal game management phase.

As shown in FIG. 50, the main ROM 300b stores a plurality of normal game control modules for controlling execution of a normal game, and each normal game control module is associated with a normal game management phase. . Specifically, when the normal game management phase is "00H", a module for executing the "normal symbol variation waiting process" is called, and when the normal game management phase is "01H", A module for executing a "normal symbol fluctuating process" is called, and when the normal game management phase is "02H", a module for executing a "normal symbol stop symbol display process" is called and normal When the game management phase is "03H", a module for executing "ordinary electric accessory winning opening preprocessing" is called, and when the normal game management phase is "04H", "normal When the module for executing the "Electric Accessory Item Winning Portion Open Control Process" is called and the normal game management phase is "05H", the module for executing the "Normal Electric Accessory Item Winning Portion Closing Effective Processing" is called, and when the normal game management phase is "06H", a module for executing "normal electric accessory winning opening end wait process" is called.

FIG. 51 is a flowchart for explaining normal game management processing (step S800) in the main control board 300 according to the simultaneous spinning reference example.

(Step S800-1)
The main CPU 300a loads the normal game management phase.

(Step S800-3)
The main CPU 300a selects the normal game control module corresponding to the normal game management phase loaded in step S800-1.

(Step S800-5)
The main CPU 300a calls the normal game control module selected in step S800-3 and starts processing.

(Step S800-7)
The main CPU 300a loads a normal game timer that manages the normal game control time.

FIG. 52 is a flowchart for explaining normal symbol variation waiting processing in the main control board 300 according to the simultaneous turning reference example. This normal symbol variation waiting process is normally executed when the game management phase is "00H".

(Step S810-1)
The main CPU 300a loads the counter value of the normal symbol reserved ball number counter and determines whether the counter value is "0", that is, whether the normal pattern reserved ball number counter is "0". As a result, when it is determined that the counter value is "0", the normal symbol variation waiting process is ended, and when it is determined that the counter value is not "0", the process is moved to step S810-3.

(Step S810-3)
The main CPU 300a block-transfers the general pattern reservation (hitting decision random number) stored in the first to fourth storage units of the general pattern reservation storage area to the storage unit with a lower ordinal number. Specifically, the general map hold stored in the second to fourth storage units is transferred to the first to third storage units. In addition, the main RAM 300c is provided with a 0th storage unit to be processed, and transfers the normal pattern suspension stored in the 1st storage unit to the 0th storage unit. In addition, in this normal design storage area shift process, the counter value of the normal design reservation ball number counter is decremented by "1", and a normal design reservation reduction designation command is transmitted to indicate that the normal design reservation has subtracted "1". set in the buffer.

(Step S810-5)
The main CPU 300a loads the winning determination random number transferred to the 0th storage unit, selects a winning determination random number determination table corresponding to the current game state, performs a general pattern lottery, and stores the lottery result. Execute the judgment process.

(Step S810-7)
The main CPU 300a saves the normal symbol stop symbol number corresponding to the result of the normal symbol lottery in step S810-5. In the simultaneous turning reference example, the normal symbol display 168 is composed of one LED lamp. Let The normal symbol stop symbol number determined here indicates whether or not the normal symbol display 168 is finally lit. is determined, and in the case of a loss, "1" is determined as the normal symbol stop symbol number.

(Step S810-9)
The main CPU 300a confirms the current game state, selects and sets the corresponding normal symbol variation time data table.

(Step S810-11)
The main CPU 300a determines the normal symbol variation time based on the hit determination random number transferred to the 0th storage unit in step S810-3 and the normal symbol variation time data table set in step S810-9.

(Step S810-13)
The main CPU 300a saves the normal symbol fluctuation time determined in step S810-11 in the normal game timer.

(Step S810-15)
The main CPU 300a executes a process of setting a normal symbol display symbol counter in the normal symbol display device 168 in order to start variable display of normal symbols. For example, when "0" is set as the counter value in this normal design display pattern counter, the lighting of the normal design display 168 is controlled, and when "1" is set as the counter value, the normal design is displayed. device 168 is controlled to turn off. Here, a predetermined counter value is set in the normal symbol display symbol counter at the start of variable display of normal symbols.

(Step S810-17)
The main CPU 300a sets a general pattern reservation specification command indicating the general pattern reservation number stored in the general pattern reservation storage area in the transmission buffer.

(Step S810-19)
The main CPU 300a sends a normal symbol designation command to the transmission buffer based on the normal symbol stop symbol number determined in step S810-7, that is, the symbol type (hit symbol or losing symbol) determined by the normal symbol win determination process. set to

(Step S810-21)
The main CPU 300a updates the normal game management phase to "01H" and terminates the normal symbol variation waiting process.

FIG. 53 is a flow chart for explaining the process during normal symbol fluctuation in the main control board 300 according to the simultaneous turning reference example. This process during normal symbol fluctuation is normally executed when the game management phase is "01H".

(Step S820-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S810-13 is "0". As a result, if the timer value is "0", the process moves to step S820-9, and if the timer value is not "0", the process moves to step S820-3.

(Step S820-3)
The main CPU 300a updates the normal symbol display timer that times the lighting time and the extinguishing time of the normal symbol display 168 . Specifically, when the timer value of the normal symbol display timer is "0", a predetermined timer value is set, and when the timer value is "1" or more, from the current timer value Update the timer value to the value decremented by "1".

(Step S820-5)
The main CPU 300a determines whether the timer value of the normal symbol display timer is "0". As a result, when it is determined that the timer value of the normal symbol display timer is "0", the processing is shifted to step S820-7, and when it is determined that the timer value of the normal symbol display timer is not "0", the The process during normal design fluctuation is ended.

(Step S820-7)
The main CPU 300a updates the counter value of the normal symbol display symbol counter. Here, when the counter value of the normal symbol display symbol counter is a counter value indicating that the normal symbol display 168 is turned off, the counter value is updated to indicate lighting, and the counter value indicating that the normal symbol display 168 is lit. When it is, it updates to the counter value which shows lighting-out, ends the processing during the normal design fluctuation. As a result, the normal symbol display 168 repeats lighting and extinguishing (blinking) at predetermined time intervals over the normal symbol fluctuation time.

(Step S820-9)
The main CPU 300a saves the normal symbol stop symbol number (counter value) determined in step S810-7 in the normal symbol display symbol counter. As a result, the normal symbol display 168 is finally controlled to light or extinguish, and the result of the normal symbol lottery is notified.

(Step S820-11)
The main CPU 300a sets the normal symbol fluctuation stop time, which is the time during which the normal symbols are stopped and displayed, in the normal game timer.

(Step S820-13)
The main CPU 300a sets a normal pattern stop specifying command indicating that the stop display of the normal pattern is started in the transmission buffer.

(Step S820-15)
The main CPU 300a updates the normal game management phase to "02H", and terminates the normal symbol changing process.

FIG. 54 is a flowchart for explaining normal symbol stop symbol display processing in the main control board 300 according to the simultaneous rotation reference example. This normal symbol stop symbol display process is executed when the normal game management phase is "02H".

(Step S830-1)
The main CPU 300a determines whether the timer value of the normal game timer set in step S820-11 is not "0". As a result, when it is determined that the timer value of the normal game timer is not "0", the normal symbol stop symbol display process is terminated, and when it is determined that the timer value of the normal game timer is "0". The process moves to step S830-3.

(Step S830-3)
The main CPU 300a confirms the result of the normal drawing lottery.

(Step S830-5)
The main CPU 300a determines whether the result of the general pattern lottery is winning. As a result, if it is determined to be a hit, the process moves to step S830-9, and if it is determined to be not a win (lost), the process moves to step S830-7.

(Step S830-7)
The main CPU 300a updates the normal game management phase to "00H" and terminates the normal symbol stop symbol display process. As a result, the normal game management processing based on one normal pattern reservation is completed, and when the normal pattern reservation is stored, the processing for starting the variable display of the normal pattern based on the next reservation is performed. becomes.

(Step S830-9)
The main CPU 300a refers to the data of the opening/closing control pattern table, and saves the time before opening the general electric power to the normal game timer as a timer value.

(Step S830-11)
The main CPU 300a updates the normal game management phase to "03H" and terminates the normal symbol stop symbol display process. As a result, the opening/closing control of the first variable starting port 120B is started.

FIG. 55 is a flowchart for explaining normal electric accessory winning opening pre-opening processing in the main control board 300 according to the simultaneous turning reference example. This normal electric accessory winning opening pre-opening process is executed when the normal game management phase is "03H".

(Step S840-1)
The main CPU 300a determines whether the timer value of the normal game timer set in step S830-9 is not "0". As a result, when it is determined that the timer value of the normal game timer is not "0", the normal electric accessory winning opening pre-opening process is terminated, and the timer value of the normal game timer is determined to be "0". If so, the process moves to step S841.

(Step S841)
The main CPU 300a executes normal electric accessory winning opening opening/closing switching processing. This ordinary electric accessory winning opening opening/closing switching process will be described later.

(Step S840-3)
The main CPU 300a updates the normal game management phase to "04H", and terminates the normal electric accessory winning opening pre-opening process.

FIG. 56 is a flowchart for explaining normal electric accessory winning opening opening/closing switching processing in the main control board 300 according to the simultaneous turning reference example.

(Step S841-1)
The main CPU 300a determines that the counter value of the normal electric accessory opening/closing switching frequency counter is the upper limit value of the normal electric accessory opening/closing switching frequency (the number of opening/closing times of the movable piece 120b of the first variable starting port 120B during one opening/closing control). Determine if there is As a result, when it is determined that the counter value is the upper limit value, the normal electric accessory winning opening opening/closing switching process is terminated, and when it is determined that the counter value is not the upper limit value, the process proceeds to step S841-3. Transfer.

(Step S841-3)
The main CPU 300a refers to the data in the opening/closing control pattern table, and based on the counter value of the normal electric accessory opening/closing switching counter, the solenoid control data (energization control data or energization control data) for controlling the energization of the normal electric accessory solenoid 120c. stop control data), and the time data that is the energization time (solenoid energization time) or the energization stop time of the normal electric accessories solenoid 120c (normal power closing valid time = pause time) is extracted.

(Step S841-5)
Based on the solenoid control data extracted in step S841-3, the main CPU 300a starts energizing the normal electric accessory solenoid 120c, or the normal electric role for stopping the energization of the normal electric accessory solenoid 120c. Executes an object solenoid energization control process. By executing this ordinary electric accessory solenoid energization control process, in the above steps S400-33 and S400-35, control of the energization start or energization stop of the ordinary electric accessory solenoid 120c is performed.

(Step S841-7)
The main CPU 300a saves the timer value based on the time data extracted in step S841-3 in the normal game timer. In addition, the timer value saved in the normal game timer here is the maximum opening time of the first variable starting port 120B.

(Step S841-9)
The main CPU 300a determines whether the normal electric accessory solenoid 120c is in the energization start state, that is, whether the control process for starting the energization of the normal electric accessory solenoid 120c has been performed in step S841-5. As a result, when it is determined that it is in the energization start state, the process is moved to step S841-11, and when it is determined that it is not in the energization start state, the normal electric accessory winning opening opening/closing switching process ends.

(Step S841-11)
The main CPU 300a updates the counter value of the normal electric accessory open/close switching frequency counter to a value obtained by adding "1" to the current counter value.

FIG. 57 is a flowchart for explaining normal electric accessory winning opening control processing in the main control board 300 according to the simultaneous turning reference example. This normal electric accessory winning opening control process is executed when the normal game management phase is "04H".

(Step S850-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S841-7 is not "0". As a result, when it is determined that the timer value of the normal game timer is not "0", the process proceeds to step S850-5, and when it is determined that the timer value of the normal game timer is "0", step S850 -3 is processed.

(Step S850-3)
The main CPU 300a determines whether the counter value of the normal electric accessory opening/closing switching frequency counter is the upper limit value of the normal electric accessory opening/closing switching frequency. As a result, if it is determined that the counter value is the upper limit value, the process moves to step S850-7, and if it is determined that the counter value is not the upper limit value, the process moves to step S841.

(Step S841)
If it is determined in step S850-3 that the counter value of the normal electric accessory opening/closing switching frequency counter is not the upper limit value of the normal electric accessory opening/closing switching frequency, the main CPU 300a executes the processing of step S841. do.

(Step S850-5)
The main CPU 300a determines whether the counter value of the normal electric accessory winning ball number counter updated in step S530-9 has reached the specified number, that is, the first variable starting port 120B is under control of opening and closing once. It is determined whether or not the same number of game balls as the maximum number of possible wins have entered. As a result, if it is determined that the specified number has not been reached, the normal electric accessory winning opening control process is terminated, and if it is determined that the specified number has been reached, the process proceeds to step S850-7.

(Step S850-7)
The main CPU 300a stops energizing the normal electric accessory solenoid 120c and executes normal electric accessory closing processing necessary to close the first variable starting port 120B. As a result, the first variable starting port 120B is closed.

(Step S850-9)
The main CPU 300a saves the normal electric valid state time in the normal game timer.

(Step S850-11)
The main CPU 300a updates the normal game management phase to "05H", and terminates the normal electric accessory winning opening control process.

FIG. 58 is a flowchart for explaining normal electric accessory winning opening closing effective processing in the main control board 300 according to the simultaneous turning reference example. This normal electric accessory winning opening closing effective process is executed when the normal game management phase is "05H".

(Step S860-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S850-9 is not "0". As a result, when it is determined that the timer value of the normal game timer is not "0", the normal electric accessory winning opening closing effective process is terminated, and the timer value of the normal game timer is determined to be "0". If so, the process moves to step S860-3.

(Step S860-3)
The main CPU 300a saves the normal electric end wait time in the normal game timer.

(Step S860-5)
The main CPU 300a updates the normal game management phase to "06H", and terminates the normal electric accessory winning opening closing valid process.

FIG. 59 is a flowchart for explaining normal electric accessory winning opening end wait processing in the main control board 300 according to the simultaneous turning reference example. This normal electric accessory winning opening end wait process is executed when the normal game management phase is "06H".

(Step S870-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S860-3 is not "0". As a result, when it is determined that the timer value of the normal game timer is not "0", the normal electric accessory winning opening end wait process is terminated, and the timer value of the normal game timer is determined to be "0". If so, the process moves to step S870-3.

(Step S870-3)
The main CPU 300a updates the normal game management phase to "00H", and ends the normal electric accessory winning opening end wait process. As a result, when normal pattern suspension is stored, the variable display of normal patterns is resumed. Next, as a reference example of effects, a specific effect that can be executed in the above-described first-class game machine, first-class and second-class game machine, and simultaneous spinning machine, and specific processing related to the effect will be described.

<Production reference example>
FIG. 60 is a diagram for explaining an example of the variation effect of the non-reach variation pattern according to the effect reference example. As described above, when the main control board 300 carries out the big win lottery, during the variable display of the special symbols, that is, over the time period during which the special symbols fluctuate, the variable performance for notifying the result of the big win lottery is executed. In this variable effect, various background images are displayed in the main effect display section 200a, and effect patterns 210a, 210b, and 210c are displayed superimposed on the background image. During the variable effect, along with the image displayed on the main effect display unit 200a, sound is output from the audio output device 206, the lighting of the effect lighting device 204 is controlled, and the effect accessory device 202 is turned on. The movement is controlled, but detailed description is omitted here.

The variation production according to the production reference example is roughly divided into a reach-less variation pattern and a reach variation pattern. In the variation effect of the non-reach variation pattern, a background image (not shown) is displayed on the main effect display section 200a, and the effect patterns 210a, 210b, and 210c are superimposed on the background image and variably displayed. For example, as shown in FIG. 60(a), it is assumed that performance symbols 210a, 210b, and 210c are stop-displayed in a combination indicating that the winning lottery result is lost. In this state, when the variable display of the special symbols is newly performed, three performance symbols 210a, 210b, and 210c are variably displayed as shown in FIG. (scroll display). Note that the downward white arrows in the drawing indicate that the effect symbols 210a, 210b, and 210c are scroll-displayed in the height direction.

Then, as shown in FIG. 60(c), the effect symbol 210a is first stopped and displayed, and then, as shown in FIG. 60(d), the effect symbol 210c different from the effect symbol 210a is stopped and displayed. Then, at almost the same timing as when the variable display of the special symbols is completed and the special symbols are stopped and displayed on the first special symbol display device 160 or the second special symbol display device 162, as shown in FIG. , and the effect symbol 210b is stopped and displayed, and the player is notified of the big role lottery result by the final stop display mode of the three effect symbols 210a, 210b, and 210c at this time.

FIG. 61 is a diagram for explaining an example of the variation effect of the normal reach variation pattern according to the effect reference example. In the production reference example, the reach fluctuation pattern is roughly classified into a normal reach fluctuation pattern, a developed reach fluctuation pattern, and a pseudo-continuous reach fluctuation pattern. In the variation effect of the normal reach variation pattern, similar to the variation effect of the non-reach variation pattern, the variation display of the effect symbols 210a, 210b, and 210c is started along with the start of the variation display of the special symbols, and FIG. As shown, the effect symbol 210a is first stopped and displayed. After that, as shown in FIG. 61(b), a performance symbol 210c identical to the performance symbol 210a is stop-displayed.

Thus, when the main effect display portion 200a displays the same effect symbols 210a and 210c in the stop-display ready-to-win state, as shown in FIG. "Reach" is displayed superimposed on 210a and 210c. A plurality of ready-to-win modes are provided, and the same performance symbols 210a and 210c marked with any of the numbers "1" to "9" are stopped and displayed. After that, as shown in FIG. 61(d), the variable display is continued with the shapes of the effect symbols 210a and 210c different from those before the ready-to-win mode. Then, as shown in FIG. 61(e), finally, a performance symbol 210b different from the performance symbols 210a and 210c is stop-displayed, and the player is notified that the result of the big role lottery is a loss.

FIG. 62 is a diagram for explaining an example of a variable performance of the developed reach variation pattern at the time of losing according to the performance reference example, and FIG. It is a figure explaining. As shown in FIGS. 62(a) to (d) and FIGS. 63(a) to (d), the variation effect of the developed reach variation pattern is similar to the variation effect of the normal reach variation pattern, in the main effect display section 200a, The effect symbols 210a and 210c are displayed in a ready-to-win mode, and then a ready-to-win development effect is executed in which a predetermined developed image (moving image) is reproduced and displayed. In this reach development effect, for example, as shown in FIGS. As shown in f) and (g), an image for accomplishing the mission is displayed.

Here, the development images for the ready-to-win development production are roughly classified into a losing pattern and a big win pattern. In the development image of the losing pattern, as shown in FIG. After that, as shown in FIG. 62(i), performance symbols 210a, 210b, and 210c are stop-displayed in a combination that notifies a failure. On the other hand, in the development image of the jackpot pattern, as shown in FIG. 63(h), an image showing the success of the mission is finally displayed, and then, as shown in FIG. 210c is stop-displayed with a combination of notifying a big win.

In addition, as described above, the ready-to-reach development production includes, for example, a mission production in which an advanced image of the content of challenging the mission is displayed, and a battle production in which an advanced image of a friendly character and an enemy character fighting each other is displayed. It is The mission presentation is provided with a plurality of execution patterns with different mission contents, and the battle presentation is provided with a plurality of execution patterns with different appearing characters and fighting methods. Further, as described above, the execution pattern of the mission production is roughly divided into a big win pattern for achieving the mission and a losing pattern for failing the mission. It is roughly divided into a jackpot pattern in which a player wins against a player and a losing pattern in which a friendly character is defeated by an enemy character.

The big hit pattern and the losing pattern have the same contents until the final stage of the production, and differ in points such as whether the ally character wins or loses in the end, or whether the mission is accomplished. . Therefore, during the ready-to-win development production, the player cannot identify the result of the big role lottery until the final stage of the variable production, and the player is given an expectation of a big win.

The big win pattern is selected only when the result of the big win lottery is a big win, and the losing pattern is selected only when the result of the big win lottery is a loss. However, in one variable production, the reach development production may be executed twice, and in this case, the first reach development production is executed in a losing pattern, and the second reach development production is a losing pattern. Or run in a jackpot pattern. Below, the flow of the effect when the ready-to-win development effect is executed twice in one variable effect will be described.

FIG. 64 is a diagram for explaining an example of a variable effect when the ready-to-win development effect according to the effect reference example is executed twice. For example, assume that the mission effects are executed as shown in FIGS. 64(a) and (b) after the effect symbols 210a and 210c are displayed in the ready-to-win mode. So far, there is no difference from the case where the reach development effect is executed only once in one variable effect, but immediately after being informed that the mission could not be achieved, as shown in FIG. , "REACH UP" is displayed on the main effect display section 200a.

After that, as shown in FIG. 64(d), the main effect display section 200a displays the development image for the battle effect, and the second ready-to-win development effect is started. The developed image for the battle production has a content in which an ally character and an enemy character fight each other, and when the jackpot is won, the ally character finally wins over the enemy character as shown in FIG. 64(e). , and as shown in FIG. 64(f), performance symbols 210a, 210b, and 210c are stop-displayed in a combination that notifies a big win. On the other hand, in the event of a failure, as shown in FIG. 64(g), the friendly character is finally defeated by the enemy character, and as shown in FIG. A stop display is displayed in combination.

FIG. 65 is a diagram illustrating an example of a variation effect of a pseudo-continuous reach variation pattern according to the reference example of effect. As shown in FIG. 65(a), when the variable display of the production patterns 210a, 210b, and 210c is started, as shown in FIG. 65(b), the production patterns 210a, 210b and 210c are temporarily stopped and displayed in one of a plurality of preset pseudo modes. In this pseudo mode, for example, the same production patterns 210a and 210b and a production pattern 210c with a number "2" larger than these production patterns 210a and 210b are temporarily stopped and displayed.

When the effect symbols 210a, 210b, 210c are temporarily stopped and displayed in the pseudo mode, the variable display of the effect symbols 210a, 210b, 210c is resumed as shown in FIG. 65(c). That is, it can be said that the pseudo mode shows the re-variation display of the performance symbols 210a, 210b, and 210c. After that, as shown in FIG. 65(d), the effect symbols 210a, 210b, and 210c are temporarily stopped and displayed again in a pseudo manner.

Then, as shown in FIG. 65(e), when the variable display of the performance symbols 210a, 210b, and 210c is resumed, the performance symbols 210a and 210c are displayed in the ready-to-win mode, as shown in FIG. 65(f). After that, as shown in FIGS. 65(g) to (i), the reach development effect is executed in the same manner as the development reach variation pattern, and the player is informed of the result of the winning lottery.

Thus, the variation effect of the pseudo-continuous reach variation pattern is different from the variation effect of the development reach variation pattern until the production patterns 210a and 210c become the reach mode, and after becoming the reach mode, the development Variation production will proceed in the same manner as the reach variation pattern.

In the pseudo-continuous reach variation pattern, a plurality of variable display patterns of the production patterns 210a, 210b, and 210c until reaching the reach mode are provided, and the production patterns 210a, 210b, and 210c are temporarily stopped for each fluctuation display pattern. The number of times of display, in other words, the number of variable display times of the effect symbols 210a, 210b, and 210c are different. This variable display pattern is determined by a variable mode command. The selection ratio of the variation mode command at the time of winning the jackpot and at the time of losing is set so that the degree") is high.

Specifically, when the result of the big win lottery is a big hit, the selection ratio of the variable mode command with a large number of variable display times is set higher than the selection ratio of the variable mode command with a small number of variable display times, When the result of the big role lottery is a loss, the selection ratio of the variation mode command with a small number of variations display is set higher than the selection ratio of the variation mode command with a large number of variations display.

Further, in the main control board 300, the reliability of the pseudo-continuous reach variation pattern is set to be higher than the reliability of the developed reach variation pattern. Therefore, the reliability is suggested by the number of temporary stop displays (fluctuation displays) of the performance symbols 210a, 210b, and 210c, and the player is expected to see more temporary stop displays (variation displays) of the performance symbols 210a, 210b, and 210c. While expecting to be done, we will watch the whereabouts of the production.

The execution pattern of the variable performance described above is determined and executed by the sub control board 330 based on the variation command determined by the main control board 300 . That is, it can be said that the execution pattern of the variable effect is determined in cooperation with the main control board 300 and the sub control board 330 .

66A and 66B are diagrams for explaining the variable effect determination table according to the effect reference example, FIG. 66A shows the first half variable effect determination table, and FIG. 66B shows the second half variable effect determination table. As described above, when the main control board 300 conducts the big win lottery, variation commands are determined based on the results of the big win lottery, and each determined command is sent to the sub control board 330 . In the sub-control board 330, when receiving the variation mode command, it acquires a production random number of 1 from the range of 0 to 249, refers to the first half variation production determination table, and outputs the acquired production random number and the received variation mode command. Based on, the execution pattern of the variable performance in the first half is determined. In addition, when receiving the variation pattern command, it acquires a production random number of 1 from the range of 0 to 249, refers to the second half variation production determination table, and based on the acquired production random number and the received variation pattern command, The execution pattern of the variable performance in the second half is determined. In addition, in FIG. 66, only a part of the first half variable effect determination table and the second half variable effect determination table are extracted and shown.

As shown in FIG. 66, according to the first half variation performance determination table, the selection ratio for the execution pattern of the first half variation performance is set for each variation mode number (variation mode command), and according to the second half variation performance determination table For example, for each variation pattern number (variation pattern command), the selection ratio for the second half variation performance execution pattern is set. By combining and executing the execution patterns of the determined first half and second half of the variable performance, one variable performance is executed.

As for the variation effect of the reachless variation pattern, "none" indicating that the first half variation effect is not executed is determined as the first half execution pattern, and "normal loss 1" corresponding to the reachless variation pattern is determined as the second half execution pattern. , "Normal Loss 2", "Special Loss 1", and "Special Loss 2" are determined. For example, when receiving a variation mode command corresponding to a variation mode number of "01H" indicating that the first half variation performance is not executed, the sub control board 330 always determines "none" as the first half execution pattern. Also, at this time, in the fluctuation pattern command that can be received at the same time, only one of "normal loss 1", "normal loss 2", "special loss 1", and "special loss 2" is determined. A selection ratio is set in the variable effect determination table. Therefore, "none" is determined as the execution pattern in the first half, and "normal loss 1", "normal loss 2", "special loss 1", and "special loss 2" are determined as the execution pattern in the second half. The effect execution pattern is determined to be the non-reach variation pattern described above.

On the other hand, for the reach variation pattern variation effects, the first half of the execution pattern is determined to be anything other than "none", and the second half of the execution pattern is determined to be one of the reach development effects (indicated by developments 1 to 5 in the figure). is executed if In other words, in the main effect display section 200a, when the variation effect of the reach variation pattern is executed, the variation mode command corresponding to the variation mode number other than the variation mode number = 01H is always received, and the variation mode command is received. A variation pattern command corresponding to the variation pattern number for which one of 1 to 5 is determined is received.

Here, in FIG. 66(a), "Normal reach 1", "Normal reach 2", etc. in the first half of the execution pattern, respectively, among the fluctuation effects of the normal reach fluctuation pattern, the production patterns 210a, 210b, 210c are in the reach mode. More specifically, it shows the changing display patterns of the background image and the effect symbols 210a, 210b, and 210c displayed on the main effect display section 200a until the reach development effect is started. These image patterns are designed in advance to match the variable display time of the special symbol associated with the variable mode number, for example, when "normal reach 1" is determined, FIG. The image shown in (d) is displayed on the main effect display section 200a.

In addition, in FIG. 66(a), "pseudo 2a" and the like in the first half of the execution pattern are displayed on the main effect display section 200a until the reach development effect is started among the variable effects of the pseudo continuous reach variation pattern. This shows the display pattern of the main fluctuation effect image, that is, the execution pattern of the symbol display effect in which the effect symbols 210a, 210b, and 210c are variably displayed. For example, "pseudo 2a" is a pseudo continuous reach fluctuation pattern of "pseudo 2" in which the number of times of fluctuation display of the production patterns 210a, 210b, and 210c is two, and that the main fluctuation production image is the display pattern a. showing. In addition, "pseudo 3b" is a pseudo continuous reach fluctuation pattern of "pseudo 3" in which the number of times of fluctuation display of the production patterns 210a, 210b, and 210c is 3, and that the main fluctuation production image is the display pattern b. showing.

In addition, in the first half variation performance determination table and the second half variation performance determination table shown in FIG. 66, the variation performance of the non-reach variation pattern and the normal reach variation pattern is executed only when the result of the big role lottery is a loss. , the selection ratio is set. In addition, the development reach variation pattern and the pseudo-continuous reach variation pattern are determined both at the time of loss and at the time of the big hit, but the development reach variation pattern has a higher selection ratio at the time of loss than the pseudo-continuous reach variation pattern, and the jackpot The time selection ratio is set low. In this way, by setting the selection ratio at the time of losing and at the time of the big hit, the pseudo-continuous reach variation pattern is set with higher reliability than the development reach variation pattern.

Furthermore, among the pseudo continuous reach fluctuation patterns, the higher the number of times of simulation, the higher the selection ratio at the time of the big win, and the lower the selection ratio at the time of losing, and the more the number of times of simulation, the higher the reliability is done.

As described above, the rough flow of the variable performance is determined by the variable performance determination table. Execution availability and execution patterns are further determined. Here, the element effect is, for example, the variable display of the effect patterns 210a, 210b, and 210c in the main effect display section 200a, the development image displayed in the main effect display section 200a in the reach development effect, Furthermore, it refers to all effects that constitute variable effects, such as effects that move the effect accessory device 202 . In the embodiment, as an elemental effect that constitutes the variable effect, an advance notice effect (suggestive effect) is executed at various timings during the variable effect.

This notice effect is the start of the variable effect, the re-variation display of the effect patterns 210a, 210b, and 210c in the variable effect of the pseudo continuous reach variation pattern, and the main effect display section 200a during the reach development effect. It is an effect such as displaying a predetermined image at the time and moving the effect accessory device 202 at a predetermined timing, and whether or not it can be executed and an execution pattern are determined for each advance notice effect. A plurality of types of execution patterns are provided for each of the advance notice effects, and for each of the plurality of types of execution patterns, a selection ratio is set for each variation pattern command or variation mode command, in other words, for each whether or not a jackpot is won. An expected value is set for each execution pattern by the selection ratio.

As described above, in the sub-control board 330, when the variable command is received, the execution pattern of the variable performance, whether or not each element performance can be executed, and the execution pattern are determined, and the variable performance is executed during the variable display of the special symbols. The Rukoto. In this way, the variable performance is performed once for one time of variable display of the special symbols, but in the embodiment, the performance over multiple times of variable display of the special symbols is also performed.

FIG. 67 is a diagram illustrating an example of a pending display effect according to the effect reference example. A pending display area 211 is provided at the bottom of the main effect display section 200a. Although not shown in FIGS. 60 to 65, the holding display area 211 is always displayed on the main effect display section 200a during the variable effect and during the game standby. A suspension display effect is performed in the suspension display area 211 during the variable effect. In the pending display effect, the pending display 212a indicating the pending read out to the processing area (0th storage unit) at the time of the big role lottery, stored in the first to fourth storage units of the first special figure pending storage area A first pending display 212b, a second pending display 212c, a third pending display 212d, and a fourth pending display 212e are displayed in the pending display area 211, respectively, indicating the pending. In the following description, the pending display 212a and the first pending display 212b to the fourth pending display 212e are collectively referred to as the pending display 212. FIG.

For example, when the special symbols are displayed in a variable manner and four special 1 reserves are stored in the main RAM 300c, the reserve display 212a and the first reserve display are displayed as shown in FIG. A total of five pending displays 212 from 212b to a fourth pending display 212e are displayed in the pending display area 211. FIG. Then, from this state, the variable display of the special symbol ends, the special 1 reservation stored in the first memory is read out to the processing area (0th memory), and the big win lottery is performed, and the main RAM 300c. When the hold shift process is executed, as shown in FIG. 67(b), the hold display 212a is erased, and the first hold display 212b to the fourth hold display 212e are moved to the left by one. . Further, when the next special 1 suspension is read from this state, each suspension display 212 is further moved and displayed as shown in FIG. 67(c). In this way, the pending display effect is an effect of informing the player of the special 1 pending number stored in the main RAM 300c.

In addition, a plurality of display patterns are provided for the pending display 212, and the display colors are different for each display pattern. In the main control board 300, when the hold is stored, the effect determination process at the time of acquisition (step S536) is executed, and the change information determined when the newly stored hold is read out to the 0th storage unit. to the sub control board 330. In the sub control board 330, upon receiving the prefetch designation command, the display pattern of the hold display 212 corresponding to the newly stored hold is determined based on the received command. At this time, the selection ratio of each display pattern is set for each look-ahead designation command, that is, for each variation information determined when the newly stored hold is read out in the big role lottery. That is, since the selection ratio of each display pattern is set according to whether or not the jackpot is won and the execution pattern of the variable effect, the display pattern of the pending display 212 suggests the reliability (expected value) of the jackpot. It will happen.

FIG. 68(a) is a diagram for explaining the final pending display pattern determination table, and FIG. 68(b) is a diagram for explaining the previous pending display pattern determination table. As described above, in the effect determination process at the time of acquisition in the main control board 300, the pre-reading designation command indicating the variation mode number and the variation pattern number determined when the newly stored hold is read is sent to the sub control board 330 Send to That is, the prefetch designation command is a command to transmit to the sub control board 330 the variation mode number and variation pattern number determined when the suspension is read. According to the final pending display pattern determination table, the selection ratio of the display pattern of the pending display 212 is set for each prefetching designation command (variation pattern number). The display pattern, that is, the final display pattern of the pending display 212a is determined.

According to the final pending display pattern determination table shown in FIG. Rainbow)” is determined. Then, when the final display pattern of the pending display 212a is determined, the display pattern of the pending display 212 to be displayed before that is determined by referring to the previous pending display pattern determination table shown in FIG. 68(b). determined by According to this one-preceding pending display pattern determination table, the selection ratio of the display pattern of the pending display 212 to be displayed before the moving display is set for each display pattern of the pending display 212 .

For example, in the main control board 300, when the suspension is stored in the second storage unit of the first special figure suspension storage area, referring to the final suspension display pattern determination table, the final display pattern of the suspension display 212a is determined. In this case, next, the display pattern of the first pending display 212b is determined with reference to the previous pending display pattern determination table. At this time, the display pattern of the first pending display 212b is determined based on the final display pattern of the pending display 212a previously determined. For example, when the final display pattern of the pending display 212a is "blue", according to the previous pending display pattern determination table, the display pattern of the first pending display 212b is "flashing" at 200/250. , and "blue" is determined with a probability of 50/250.

After the display pattern of the first reserved display 212b is determined in this manner, the immediately previous reserved display pattern determination table is again based on the previously determined display pattern of the first reserved display 212b. The display pattern of the second pending display 212c is determined with reference to this.

As described above, when the hold is stored, first, the final display pattern of the hold display 212a is determined, and then, based on the determined final display pattern of the hold display 212a, the first hold The display patterns are sequentially determined such that the display pattern of the display 212b is determined, and the display order is reversed. According to the immediately preceding pending display pattern determination table, the selection ratio is set so that only the display pattern that is the same as the display pattern of the previously determined pending display 212 or has a low reliability is determined. It is

As described above, in the pending display effect, the pending display 212 is provided with a plurality of display patterns with different expected values for the provision of a predetermined game profit. The pending display 212 may be displayed in one display pattern from the time it is first displayed on the main effect display section 200a until it is finally erased, or the display pattern may change during the display period. sometimes.

In the production reference example, the timing at which the change in the display pattern of the hold display 212 occurs is that the newly stored special 1 hold (hereinafter also referred to as target hold) moves to the first hold display 212b to the third hold display 212d. It is roughly divided into the timing when the target is held and during the target change effect related to the target hold.

Next, the processing in the sub-control board 330 for executing the variable effect will be described. In addition, below, among the processes in the sub-control board 330, the description of the processes irrelevant to the variation effect will be omitted.

(Sub CPU initialization processing of sub control board 330)
FIG. 69 is a flow chart for explaining the sub-CPU initialization process (S1000) of the sub-control board 330 according to the production reference example.

(Step S1000-1)
When the power is turned on, the sub CPU 330a reads a CPU initialization processing program from the sub ROM 330b and initializes and sets flags stored in the sub RAM 330c.

(Step S1000-3)
Next, the sub CPU 330a performs processing for updating each effect random number, and thereafter repeatedly performs the processing of step S1000-3 until interrupt processing is performed. A plurality of types of effect random numbers are provided, and here, each effect random number is asynchronously updated.

(Sub-timer interrupt processing of sub-control board 330)
FIG. 70 is a flowchart for explaining the sub-timer interrupt processing (S1100) of the sub-control board 330 according to the production reference example. The sub-control board 330 is provided with a reset clock pulse generation circuit (not shown) that generates a clock pulse at a predetermined cycle (30 times per second). When the reset clock pulse generating circuit generates a clock pulse, the sub CPU 330a reads the timer interrupt processing program and starts the sub timer interrupt processing.

(Step S1100-1)
The sub CPU 330a saves the register.

(Step S1100-3)
The sub CPU 330a performs processing for permitting interrupts.

(Step S1100-5)
The sub CPU 330 a updates various timer counters used in the sub control board 330 . Here, the various timer counters are decremented by 1 each time the sub-timer interrupt processing of the sub-control board 330 is executed, and the decrementation is stopped when it reaches 0, unless otherwise specified.

(Step S1200)
The sub CPU 330a analyzes the commands stored in the reception buffer of the sub RAM 330c and performs various processes according to the received commands. In the sub control board 330, when a command is transmitted from the main control board 300, command reception interrupt processing is performed, and the command transmitted from the main control board 300 is stored in the reception buffer. Here, the command stored in the reception buffer is analyzed by command reception interrupt processing.

(Step S1100-7)
The sub CPU 330a refers to the timetable and performs a time schedule management process for executing the process corresponding to the time stored in the timetable. Here, based on the time data set in the timetable, various flags are turned on and off, or by sending commands to each production device, various productions such as variable production and large role production It will control the execution of the production.

(Step S1100-9)
The sub CPU 330a restores the register and terminates the sub timer interrupt process.

FIG. 71 is a flow chart for explaining a read-ahead designation command reception process according to a reference example of effect executed when a read-ahead designation command is received in the command analysis process. As described above, the prefetching designation command (prefetching designation variation pattern command) is set in the main control board 300 in the effect determination process (steps S536-21, S536-25, and S536-27 in FIG. 33). After that, it is transmitted to the sub-control board 330 by sub-command transmission processing (step S100-65 in FIG. 23).

(Step S1210-1)
The sub CPU 330a first analyzes the received prefetch designation command.

(Step S1210-3)
Sub CPU 330a stores advance determination information based on the analysis result of step S1210-1. The sub-RAM 330c of the sub-control board 330 includes a first preliminary determination information storage unit corresponding to the first special figure reservation storage area of the main control board 300, and a second preliminary determination corresponding to the second special figure reservation storage area. An information storage unit is provided. The first prior determination information storage section has four storage sections, ie, a first storage section to a fourth storage section. The first to fourth storage units of these first advance determination information storage units correspond to the first to fourth storage units of the first special figure reservation storage area, respectively. Similarly, the second pre-determination information storage unit includes four storage units, the first storage unit to the fourth storage unit, and the first storage unit to the fourth storage unit of the second pre-determination information storage unit are: It corresponds to each of the first to fourth storage units of the second special figure reservation storage area. Here, of the first to fourth storage units of the first special figure reservation storage area or the second special figure reservation storage area of the main control board 300, the storage unit corresponding to the storage unit in which the new suspension is stored pre-determination information is stored in.

(Step S1210-5)
The sub CPU 330 a performs final pending display pattern determination processing for determining the final display pattern of the pending display 212 . Here, based on the received prefetch designation command, the final pending display pattern determination table (FIG. 68(a)) is referred to determine and store the final display pattern of the pending display 212a.

(Step S1210-7)
The sub CPU 330a derives the number of times the display pattern of the pending display 212 is determined, that is, the change timing of the pending display 212, based on the storage unit in which the pending is stored. With reference to (FIG. 68(b)), the display pattern of the pending display 212 is determined. Then, the determined display pattern information of the pending display 212 is stored in a predetermined storage unit, and the process proceeds to step S1210-9.

(Step S1210-9)
Sub CPU 330a performs a hold display start process for starting the display of hold display 212 based on the determinations in steps S1210-5 and S1210-7, and ends the prefetch designation command reception process. Thus, when the hold is stored, the display of the corresponding hold display 212 is started.

FIG. 72 is a flow chart for explaining the variable command reception process executed when a variable command is received, among the command analysis processes according to the reference example of effect. As described above, the variation command is set in the special symbol variation number determination processing (steps S612-13 and S612-17 in FIG. 39) in the main control board 300, and then the sub-command transmission processing (step S100- in FIG. 23). 65) to the sub control board 330.

(Step S1220-1)
Upon receiving the variation command, the sub CPU 330a first analyzes and stores the received variation pattern command.

(Step S1220-3)
The sub CPU 330a acquires the effect random number (0 to 249) updated in step S1000-3, and based on the acquired effect random number and the analysis result in step S1220-1, determines the execution pattern of the second half of the variable effect. Decide, memorize.

(Step S1220-5)
Sub CPU 330a analyzes and stores the received variation mode command.

(Step S1220-7)
The sub CPU 330a acquires the effect random number (0 to 249) updated in step S1000-3, and based on the acquired effect random number and the analysis result in step S1220-5, determines the execution pattern of the first half of the variable effect. Decide, memorize.

(Step S1220-9)
The sub CPU 330a acquires the effect random number (0 to 249) updated in step S1000-3 for each advance notice effect, and based on the obtained effect random number and the analysis results in steps S1220-1 and S1220-5. , with reference to each notice effect determination table, the presence or absence of execution of each notice effect and the execution pattern are determined and stored.

(Step S1220-11)
Sub CPU 330a executes shift processing for shifting the prior determination information stored in the prior determination information storage unit. Here, when starting the variable production based on the special 1 suspension, the advance judgment information stored in the fourth storage unit to the second storage unit of the first advance judgment information storage unit, respectively, the first advance judgment information When shifting to the third storage unit to the first storage unit of the storage unit and starting the variable production based on the special 2 hold, the fourth storage unit to the second storage unit of the second advance determination information storage unit is stored. The pre-determination information stored therein is shifted to the third storage unit to the first storage unit of the second pre-determination information storage unit.

(Step S1220-13)
The sub CPU 330a performs a hold display shift process for moving the hold display 212 for display. Further, here, when the display pattern of the pending display 212 changes, execution data for changing the display pattern at a predetermined timing is set.

(Step S1220-15)
The sub CPU 330a sets the time data in the timetable based on the determinations made in the above steps, and terminates the variation command reception process. Based on the timetable set here, in step S1100-7, the process of displaying the image for the variable effect on the main effect display unit 200a, the sound output process, the lighting control process of the effect lighting device 204, etc. Production execution control is performed.

<Slot machine 400>
As shown in the external views of FIGS. 73 and 74, a slot machine 400 as a game machine includes a housing 402 with an open front surface and a front surface arranged vertically at one end of the front surface of the housing 402 so as to be rotatable. An upper door 404 and a lower front door 406 are provided. A colorless and transparent pattern display window 408 made of a glass plate, a transparent resin plate, or the like is provided at approximately the center of the lower portion of the front upper door 404. , three reels 410 (a left reel 410a, a middle reel 410b, and a right reel 410c) are independently rotatable. As shown in the pattern arrangement of FIG. 75(a), a plurality of types of symbols are arranged in each area divided into 20 on the outer peripheral surface of the left reel 410a, the middle reel 410b, and the right reel 410c. Through the symbol display window 408, the player can visually recognize a total of nine symbols, each of which is located in the upper, middle and lower stages, and which are three continuous reels 410a, 410b and 410c, respectively.

An operation unit installation table 412 is formed on the upper part of the front lower door 406, and the operation unit installation table 412 is provided with a medal insertion unit 414, a bet switch 416, a start switch 418, a stop switch 420, a production switch 422, and the like. there is The medal insertion unit 414 receives insertion of medals as game value through a medal insertion slot 414a. The bet switch 416 inserts (bets) a prescribed number of medals required for one game among the medals electrically stored (hereinafter simply referred to as credits) inside the slot machine 400 .

The start switch 418 is composed of, for example, a lever capable of detecting a tilting operation, and detects a game start operation by the player. The stop switch 420 (stop switch 420a, stop switch 420b, stop switch 420c) is provided corresponding to each of the left reel 410a, the middle reel 410b, and the right reel 410c, and detects the player's stop operation. In addition, when the stop switch 420 can be stopped, the player first stops any one of the stop switch 420a, the stop switch 420b, and the stop switch 420c, which is called a first stop. After that, stopping one of the two stop switches 420 that have not been stopped is called a second stop, and after the second stop, stopping the last remaining stop switch 420 is called a third stop. . The effect switch 422 is composed of, for example, a press switch and a jog dial switch rotatably arranged around it, and detects a player's press operation or rotation operation.

A liquid crystal display section 424 for displaying various images associated with the effects is provided in the upper approximate center of the front upper door 404 . In addition, on the upper part and on the left and right of the front upper door 404, there are provided lamps 426 for effect, which are made up of, for example, high-intensity light-emitting diodes (LEDs). Speakers 428 are provided at the left and right positions of the liquid crystal display section 424 on the rear surface of the upper front door 404 and at the left and right positions on the rear surface of the lower front door 406 to produce auditory effects such as sound effects and musical tones.

A main credit display section 430 and a main payout display section 432 are provided on the operating section installation table 412 . A sub-credit display section 434 and a sub-payout display section 436 are provided between the symbol display window 408 and the operating section installation table 412 . The main credit display portion 430 and the sub-credit display portion 434 display the number of credited medals (the number of credits), and the main payout display portion 432 and the sub-payout display portion 436 display the number of payout medals. .

Below the reel 410 in the housing 402, a medal payout device (medal hopper) 442 for paying out medals from the medal outlet 440a is provided. In addition, at the front lower portion of the front lower door 406, a saucer portion 440 for storing medals dispensed from the medal discharge port 440a is provided. A power switch 444 is also provided in the housing 402 . The power switch 444 is operated by an administrator who manages the slot machine 400 and is used to switch between two states, a power-off state and a power-on state.

In the housing 402, a main control board 500, which will be described later, is provided with a setting door key and a setting change switch (not shown) (collectively referred to as setting value setting means). In the slot machine 400, when a predetermined key (operation key) is inserted into the setting door key and turned from the OFF position to the ON position, the power is turned on via the power switch 444, and the setting change mode is entered. , the setting value can be changed (simply referred to as setting change). The set value indicates the degree of advantage of the player (machine ratio) in stages, and is represented, for example, in six stages from 1 to 6. In general, the higher the value of the set value, the more advantageous the game as a whole. It is set to be high (expected acquisition number is high). The set value is incremented by one each time the setting change switch is pressed in a state in which the setting can be changed. Then, the set value is determined, and the set door key is returned to the original position (OFF position) to terminate the setting change mode and enable the game. It should be noted that setting change is possible only for a certain period of time after the power switch 444 is operated and the power is turned on.

In the slot machine 400, when a game can be started and a specified number of medals are betted, the activated line A is activated and the operation of the start switch 418 is activated. Here, bets are made by inserting credited medals through operation of the bet switch 416, inserting medals through the medal inserting unit 414, and replay combinations, which will be described later in detail, are displayed on the activated line A. This includes any case where medals are automatically inserted based on Also, the active line A is a line for judging the winning of a winning combination, and there is one in this embodiment. As shown in FIG. 75(b), the activated line A has nine symbols (three reels×three rows of upper, middle, and lower) facing the symbol display window 408, the middle row of the left reel 410a, the middle row of the middle reel 410b, and the middle row of the middle reel 410b. The line is set to connect the positions corresponding to the symbols stopped on the upper stage of the right reel 410c. The invalid line is used to determine the winning combination by displaying other symbol combinations that make it easier to grasp the winning combination when it is difficult to grasp the winning combination only from the combination of symbols displayed on the valid line A. In this embodiment, five invalid lines B1, B2, B3, C1 and C2 shown in FIG. 75(b) are assumed.

When the player operates the start switch 418, the game is started, the left reel 410a, the middle reel 410b, and the right reel 410c are rotated, and the winning type lottery and the like are executed. After that, according to the operation of the stop switches 420a, 420b, 420c, the corresponding left reel 410a, middle reel 410b, and right reel 410c are respectively stopped. Then, when a winning combination that can receive medals wins according to the combination of the lottery results of the winning type lottery and the symbols displayed on the activated line A, the medals are paid out, and the winning type that can receive the medals is paid out. , or if the player wins but does not win, the left reel 410a, the middle reel 410b, and the right reel 410c all come to a stop, and the game ends.

In the present embodiment, the above-mentioned one game is the insertion of medals through the medal insertion unit 414, the insertion of credited medals through the operation of the bet switch 416, or the replay combination displayed on the activated line A. After one of the medals is automatically inserted based on the above, the left reel 410a, the middle reel 410b, and the right reel 410c are controlled to rotate according to the player's operation of the start switch 418, and the winning type lottery is executed. The left reel 410a, the middle reel 410b, and the right reel corresponding to the operated stop switches 420a, 420b, and 420c according to the lottery result of the winning type lottery and the operation of the plurality of stop switches 420a, 420b, and 420c by the player. 410c are respectively controlled to be stopped, and when a winning combination that can receive the payout of medals wins, the game is played until the payout of the medals is executed. In addition, when the winning type for which medals can be paid out is not won, or when the player wins but does not win, the left reel 410a, the middle reel 410b, and the right reel 410c all stop, and one game ends. However, the start of one game may be read as the operation of the start switch 418 by the player instead of the insertion of medals or the winning of a replay combination. Also, the number of times such one game is repeated is the number of games.

FIG. 76 is a block diagram showing a schematic electrical configuration of the slot machine 400. As shown in FIG. As shown in FIG. 76, the slot machine 400 includes a main control board 500 (main control section) for controlling the progress of the game, and a sub-control board 502 (sub-control section) for controlling the effect according to the progress of the game. A control board is provided that includes. In addition, electrical signal transmission between the main control board 500 and the sub control board 502 is limited to one direction only from the main control board 500 to the sub control board 502 from the viewpoint of fraud prevention.

(Main control board 500)
The main control board 500 has a semiconductor integrated circuit including a main CPU 500a as a central processing unit, a main ROM 500b storing programs and the like, a main RAM 500c functioning as a work area, etc., and controls the entire slot machine 400. . The data in the main RAM 500c is retained without being erased even when the power is turned off, unless the setting is changed and the RAM is cleared.

In addition, the main control board 500 functions by the main CPU 500a cooperating with the main RAM 500c based on the program stored in the main ROM 500b. 606, determination means 608, payout control means 610, game state control means 612, effect state control means 614, command transmission means 616 and other functional units.

The main control board 500 receives various detection signals from an inserted medal detector 414b that detects the insertion of medals into the medal slot 414a, a bet switch 416, a start switch 418, and stop switches 420a, 420b, and 420c. The main CPU 500a executes various processes based on the received detection signal.

The initialization means 600 executes initialization processing in the main control board 500 . The betting means 602 bets medals to be used for games. Based on the operation of the start switch 418, the winning type lottery means 604 performs a winning type lottery for determining the suitability of the winning combination, more specifically, the suitability of the winning combination including the winning combination, as will be described in detail later.

The reel control means 606 controls the rotation of the left reel 410a, the middle reel 410b and the right reel 410c according to the operation of the start switch 418, corresponding to the rotating left reel 410a, the middle reel 410b and the right reel 410c. Depending on the operation of the stop switches 420a, 420b and 420c, the corresponding left reel 410a, middle reel 410b and right reel 410c are controlled to stop. In addition, the reel control means 606 activates the operation of the stop switches 420a, 420b, and 420c in the previous game in response to the operation of the start switch 418, and then, to display the lottery result of the winning type lottery. The time until the operation of the stop switches 420a, 420b, and 420c is validated (invalidated by the completion of the operation of the stop switches 420a, 420b, and 420c in the previous game) is extended beyond the specified time, and during that time, the reel 410a , 410b, and 410c are rotated in various ways (freeze effect). In the reel performance, an arbitrary switch that should be enabled is not enabled for a predetermined time, processing that should be executed is suspended for a predetermined time, or a signal of an arbitrary switch that should be transmitted and received is transmitted or received for a predetermined time. It can be realized by doing or not.

A reel drive control section 450 is also connected to the main control board 500 . This reel drive control unit 450 drives a stepping motor 452 based on the rotation start signal of the left reel 410a, the middle reel 410b, and the right reel 410c, which is transmitted from the reel control means 606 in response to the operation signal of the start switch 418. do. In addition, the reel drive control unit 450 detects the respective stop signals of the left reel 410a, the middle reel 410b, and the right reel 410c, which are transmitted from the reel control means 606, and the rotation position detection circuit 454 in response to the operation signal of the stop switch 420. Drive of the stepping motor 452 is stopped based on the signal.

The determining means 608 determines whether or not the symbol combination corresponding to the winning combination is displayed on the activated line A. Here, the fact that the symbol combination corresponding to the winning combination is displayed on the activated line A may simply be called winning. A payout control means 610 pays out medals in the number (amount of value) corresponding to the winning combination based on the symbol combination corresponding to the winning combination being displayed on the activated line A (winning). A medal payout device 442 is connected to the main control board 500, and the payout control means 610 discharges medals while counting the number of payout medals.

The game state control means 612 refers to the result of the winning type lottery and the determination result of the determination means 608, and shifts the game state to one of a plurality of types of game states. Also, the effect state control means 614 refers to the result of the winning type lottery, the determination result of the determination means 608, and the transition information of the game state, and shifts the effect state to one of a plurality of types of effect states.

The command transmission means 616 is a game-related command associated with the operation of the betting means 602, winning type lottery means 604, reel control means 606, determination means 608, payout control means 610, game state control means 612, effect state control means 614, and the like. are sequentially determined, and the determined commands are sequentially transmitted to the sub control board 502 .

Further, the main control board 500 is provided with a random number generator (random number generating means) 500d. The random number generator 500d sequentially increments the count value, loops within a predetermined numerical range, and extracts the count value at a predetermined point in time to obtain a random number. A random number generated by the random number generator 500d of the main control board 500 (hereinafter referred to as a winning type lottery random number) is used to determine the game profit to be given to the player, for example, the winning type lottery means 604 determines the winning type. .

(Sub control board 502)
The sub-control board 502, like the main control board 500, has various semiconductor integrated circuits including a sub-CPU 502a that is a central processing unit, a sub-ROM 502b that stores programs and the like, and a sub-RAM 502c that functions as a work area. , based on the command from the main control board 500, especially controls the performance. A backup power supply (not shown) is connected to the sub-RAM 502c as well as the main RAM 500c, so that data is retained without being erased even when the power is turned off. The sub control board 502 is also provided with a random number generator (random number generating means) 502d, similar to the main control board 500. It is used to determine the mode of production.

Also, in the sub-control board 502, the sub-CPU 502a functions by cooperating with the sub-RAM 502c based on the program stored in the sub-ROM 502b. It has a functional part.

The initialization determining means 630 executes initialization processing in the sub control board 502 . The command receiving means 632 receives commands from other control boards such as the main control board 500 and processes the commands. The effect control means 634 receives the detection signal from the effect switch 422, and determines the effect of the game performed by each device of the liquid crystal display unit 424, the speaker 428, and the effect lamp 426 based on the received command. Specifically, the effect control means 634 controls the image data displayed on the liquid crystal display unit 424, the effect lamps 426, the sub-credit display unit 434, the sub-payout display unit 436, and other illumination devices for effects. Along with determining the decoration data, the audio data constituting the audio to be output from the speaker 428 is also determined. And the production|presentation control means 634 performs the production|presentation of the determined game. Note that the production includes an auxiliary production. In the winning type lottery, when winning a selected winning type in which a correct combination (a specific combination) and an incorrect combination are duplicated, the correct operation of the stop switches 420a, 420b, and 420c, which is a winning condition for the correct combination, is performed. This is an effect for notifying the operation mode. With such an auxiliary effect, the player can easily display the symbol combination corresponding to the correct combination on the activated line A. An effect state in which such an assist effect is executed is called an AT (assist time) effect state. Also, a so-called ART game state may be used in which an AT effect state and an RT (replay time) game state with a high probability of winning a replay combination progress in parallel.

In the following description, information managed by a board other than the main control board 500, including the sub control board 502, such as the liquid crystal display section 424, the performance lamp 426, the speaker 428, the sub credit display section 434, and the sub payout display section 436 The means may be called other notification means. On the other hand, the notification means managed by the main control board 500, such as the main credit display section 430 and the main payout display section 432, may be called main notification means (instruction monitor). Also, the main notification means and other notification means capable of executing the auxiliary effect may be collectively referred to as the auxiliary effect executing means. The effect state control means 614 causes the auxiliary effect executing means to execute the auxiliary effect in the AT effect state.

(Table used in main control board 500)
FIG. 77 is an explanatory diagram for explaining the winning combination, and FIGS. 78 and 79 are explanatory diagrams for explaining the winning type lottery table.

As will be described later in detail, the slot machine 400 is provided with a plurality of types of game states and effect states, and the game states and effect states are changed in accordance with the progress of the game. In the main control board 500, the main ROM 500b stores a plurality of winning type lottery tables corresponding to the game states managed and controlled by the game state control means 612. FIG. The winning type lottery means 604 stores the corresponding winning type lottery table in the main ROM 500b according to the current set value (indicating the easiness of obtaining a game profit in stages) stored in the main RAM 500c and the current gaming state. and based on the extracted winning type lottery table, it is determined which winning type in the winning type lottery table the winning type lottery random number acquired in response to the operation signal of the start switch 418 corresponds to.

Here, the winning combination constituting the winning type extracted from the winning type lottery table includes a replay combination, a minor combination, and a bonus combination. The replay combination is a combination in which, when the symbol combination corresponding to the replay combination is displayed on the activated line A, the game can be played again without the player betting new medals. A small combination is a combination in which a predetermined number of medals can be paid out according to the symbol combination by displaying a symbol combination corresponding to the minor combination on the activated line A. In addition, the bonus combination is changed to a bonus game state (a game state during RBB operation to be described later), which is managed by the game state control means 612, by displaying a symbol combination corresponding to the bonus combination on the activated line A. It is a role that can be transferred to

As shown in FIG. 77, the winning combination according to the present embodiment includes winning combinations "replay 1" to "replay 7" as replay combinations. In addition, as the small winning combination, winning combinations “small winning combination 1” to “small winning combination 39” are provided. In addition, a winning combination “RBB” is provided as a bonus combination. In FIG. 77, the left reel 410a, the middle reel 410b, and the right reel 410c are associated with one or a plurality of symbols forming each winning combination.

Here, in the present embodiment, when the stop switch 420 is operated by the player, if the symbols forming the symbol combination corresponding to the possible winning combination are on the effective line A, the reel control means By 606, stop control is performed so that the symbol is stopped on the activated line A. Further, when the stop switch 420 is operated, there are 4 symbols in the direction opposite to the rotating direction of the reel 410, although the symbols constituting the symbol combination corresponding to the winning combination that can be won are not on the activated line A. If it exists within the range (pull-in range) corresponding to the winning combination, the reel control means 606 makes the number of symbols that are separated become the number of sliding symbols, and the symbols that make up the combination of symbols corresponding to the winning combination are valid. Stop control is performed so as to stop after maintaining the rotation for the number of sliding frames so as to draw onto the line A. Further, when there are a plurality of symbols corresponding to winning combinations that can be won in the reel 410, and all of them are within the retraction range of the reel 410, which symbol is placed on the effective line A according to a predetermined priority. It is determined whether to pull it upward, and stop control is performed so as to stop after maintaining the rotation for the number of sliding frames so as to pull the prioritized symbol onto the effective line A. - 特許庁Incidentally, when the stop switch 420 is pressed, if a symbol constituting a symbol combination corresponding to a winning combination other than a winable winning combination is present on the activated line A, the reel control means 606 controls the symbol. is not stopped on the effective line A, so-called kicking processing is also executed in parallel. In addition, as will be described later, when an operation mode (operation order or operation timing) is set as a winning condition for a winning combination included in the winning type, the reel control means 606 controls the winning combination according to the player's operation mode. The symbol combination corresponding to is controlled to be displayed on the activated line A.

Then, for example, symbols constituting symbol combinations corresponding to winning hands "replay 1" to "replay 4", winning hands "small hand 1" to "small hand 6", and "small hand 35" to "small hand 39". are arranged so that they can always be displayed on the effective line A by the above-described stop control on each reel 410 . Such a winning combination may be expressed as PB=1. On the other hand, for example, the symbols constituting the symbol combination corresponding to the winning combination “Replay 5” to “Replay 7”, the winning combination “Small combination 7” to “Small combination 34”, and the winning combination “RBB” are displayed on each reel 410. , the above-mentioned stop control does not always allow the arrangement to be displayed on the effective line A, so that a so-called dropout may occur. Such a winning combination may be expressed as PB≠1.

As shown in FIGS. 78 and 79, in the winning type lottery table, a plurality of winning areas are divided, and the winning type to be the target of the lottery differs depending on each game state, and the presence or absence of non-winning (losing) differs. or In FIGS. 78 and 79, the winning areas ( Winning type lottery tables corresponding to each of a plurality of gaming states are actually stored in the main ROM 500b. In addition, "◎" indicates that it is possible to draw a lottery to move to an advantageous section, and "○" indicates that it is impossible to draw a lottery to move to an advantageous section. It shows that it is a winning type.

In the winning type lottery table, each partitioned winning area is associated with a predetermined number (winning range value), which is a numerical value indicating a winning range, and a winning type. The total number of winning type lottery random numbers (65536) is obtained by summing up the numbers set in the winning areas. Therefore, the probability that each winning type is determined is a value obtained by dividing the number associated with the winning area by the total number of winning type lottery random numbers. A winning-type lottery means 604 sequentially acquires numbers from a plurality of winning regions in the winning-type lottery table in descending order of numbers based on the game state at that time, and converts the numbers to winning-type lottery random numbers. When the value after subtraction becomes less than 0, the winning type associated with the winning area at that time is taken as the lottery result of the winning type lottery. Also, the set numbers of all the winning areas of 1 or more winning areas are subtracted from the winning type lottery random number, and if the value after subtraction is 0 or more, the winning type "losing" of the winning area 0 is the winning type lottery. lottery result.

Here, the winning combination "RBB" constituting the winning type "RBB" will be supplemented. Predetermined Type 1 Special Accessory RB is an accessory that increases the number of combinations of symbols related to winning for each specified number, or increases the probability of operating the conditional device related to winning for each specified number. It is activated when the game is played, and can continue to operate until the result of the game is obtained not more than 12 times. Here, the conditional device is a device whose operation is a necessary condition for displaying a combination of symbols related to winning, replay, the operation of the accessory or the operation of the accessory continuous operation device, and the winning type lottery ( It means a winning flag that operates when winning a lottery by an electronic computer performed in a game machine. And the role product continuous operating device (winning role "RBB") related to the first type special role product constituting the winning type "RBB" is a device capable of continuously operating the first type special role product RB. It is activated when a specific combination of symbols is displayed, and ends when it is determined in advance.

According to the winning type lottery table of FIG. 78, for example, the winning area 0 is associated with the winning type "lost". No combination is displayed on the activated line A, and medals are not paid out. However, as will be described later, if the RBB internal winning flag is carried over to the next game, the symbol combination corresponding to the winning combination "RBB" can be displayed on the activated line A by winning the winning type "lost". It becomes possible.

In addition, the winning area 1 is associated with the winning type "small winning combination ALL" in which the winning combinations "small winning combination 1" to "small winning combination 39" are duplicated, and the winning area 2 corresponds to the winning combination " The winning type "1 piece ALLA" in which the "small winning combination 11" to "small winning combination 39" are included in duplicate is associated with the winning area 3, and the winning combination "small winning combination 12" to "small winning combination 27" are associated with the winning area 3. The winning type "one card ALLB", which is redundantly included, is associated with it. In addition, the winning area 4 is associated with the winning type "choice 1 sheet 1" in which the winning combination "small combination 12" and "small combination 20" are duplicated, and the winning area 5 is associated with the winning combination "small combination Winning type "Choice 1 sheet 2" in which "Hand 13" and "Small win 21" are overlapped is associated, and winning area 6 is associated with winning combination "Small win 14" and "Small win 22". The winning type "choice 1 3" included in the winning area 7 is associated with the winning type "choice 1 4" in which the winning combination "small combination 15" and "small combination 23" are duplicated. are mapped. The winning area 8 is associated with the winning type "weak cherry" in which the winning combination "small combination 35" and "small combination 36" are duplicated, and the winning area 9 is associated with the winning combination "small combination 37". to "small win 39" are associated with the winning type "strong cherry", and the winning area 10 contains the winning wins "small win 7", "small win 8", and "small win 11". The winning type "watermelon A" that overlaps is associated, and the winning area 11 is associated with the winning type "watermelon B" that overlaps the winning combination "small combination 7" to "small combination 10". The winning area 12 is associated with the winning type "strong bell" in which the winning combinations "small combination 1", "small combination 3", and "small combination 5" are overlapped. In addition, the winning area 13 is associated with the winning type "common bell A" in which the winning hands "small hand 1" to "small hand 6" are overlapped, and the winning area 14 is associated with the winning hand "small hand 1” to “small winning combination 6” and “small winning combination 11” are included in duplicate, and are associated with the winning type “common bell B”.

In addition, in the winning areas 15 to 26, the correct combination (winning combination "small combination 1" to "small combination 6") with the number of payouts of 11 and the incorrect combination (winning combination "small combination") with the number of payouts of 1 Selected winning types (winning types "batting order bell 1A" to "batting order bell 6A", "batting order bell 1B" to "batting order bell 6B") that overlap with "hand 12" to "small win 34") are associated with each other. It is

Further, according to the winning type lottery table of FIG. 79, winning areas 27 to 39 include winning combinations "replay 1" to "replay 7" in duplicate. ”, and “symbol replay B1” to “symbol replay B6” are associated with each other. In addition, the winning area 40 is associated with the winning type "normal replay" in which the winning combination "replay 1" and "replay 2" are overlapped.

Further, the winning areas 41 to 46 are associated with the winning types "RBB1" to "RBB6" in which the winning combination "RBB" is included singly or overlapped with other minor combinations.

Then, when a winning type in which a plurality of winning hands are overlapped is won, a winning condition, such as stop The order in which the switches 420a, 420b, and 420c are operated is set.

In the following description, the operations of the stop switches 420a, 420b, and 420c that stop the reels in the order of the left reel 410a, the middle reel 410b, and the right reel 410c are referred to as "batting order 1". The operations of the stop switches 420a, 420b, and 420c that sequentially stop the reels are referred to as "batting order 2", and the operations of the stop switches 420a, 420b, and 420c that stop the reels in the order of the middle reel 410b, the left reel 410a, and the right reel 410c are referred to as the "batting order." 3", and the operation of the stop switches 420a, 420b, 420c for stopping the reels in the order of the middle reel 410b, the right reel 410c, and the left reel 410a is set as "hitting order 4", and the right reel 410c, the left reel 410a, and the middle reel 410b are operated in this order. The operation of the stop switches 420a, 420b, and 420c for stopping the reels is referred to as "batting order 5", and the operation of the stop switches 420a, 420b, and 420c for stopping the reels in the order of the right reel 410c, middle reel 410b, and left reel 410a is referred to as "batting order 6". ”.

For example, in the non-internal game state, if the winning type "batting order bell 1A" in the winning area 15 is won and an operation is performed according to the correct operation mode (batting order 1), the payout number is 11, which is the correct winning combination. Stop control is performed so that the symbol combination corresponding to the "small win 1" is preferentially displayed on the activated line A. - 特許庁Further, when the operation of the batting order 2 is performed, the stop control is performed so that the symbol combination corresponding to the winning combination "small combination 28" which is the incorrect combination with the number of payouts of 1 is preferentially displayed on the activated line A. is performed, and when the operation according to the batting order 3, 4 is performed, the symbol combination corresponding to the winning combination "small combination 12", which is an incorrect combination of the number of payouts of 1, is preferentially placed on the activated line A by 1/4. Stop control is performed so as to be displayed with a probability, and when operations are performed according to the batting order of 5 and 6, the symbol combination corresponding to the winning combination "small combination 16", which is an incorrect combination of the number of payouts of 1, is on the valid line A. Stop control is performed so that it is preferentially displayed on the top with a probability of 1/4.

It should be noted that the winning probability (set number) of each winning type in the winning areas 15 to 26 is set to be equal. Since the player usually cannot know which type of winning has been won, by providing the above-described winning areas 15 to 26, it is made difficult for the correct combination to win. Further, as described above, even if the stop switches 420a, 420b, and 420c are operated in the batting order in which the incorrect combination is preferentially displayed, the symbol combination corresponding to the incorrect combination is necessarily displayed on the activated line A. However, depending on the mode of operation, there are cases where a failure occurs (PB≠1).

When one of the winning types described above is won, the internal winning flag corresponding to each winning type is established (ON), and each reel 410 is controlled to stop according to the state of establishment of this internal winning flag. The Rukoto. At this time, if a winning type including a minor winning combination is won, but the symbol combination corresponding to these winning combinations cannot be displayed on the activated line A in the game, after the end of the game. The internal winning flag is turned OFF. In other words, the right to win a minor winning combination is limited only within the game in which the winning type including the minor winning combination has been won, and the right cannot be carried over to the next game. On the other hand, if the winning type including the winning combination "RBB" is won, the RBB internal winning flag is established (ON) and the symbol combination corresponding to the winning combination "RBB" is displayed on the activated line A. The RBB internal winning flag is carried over across games until it is displayed. In addition, when the internal winning flag corresponding to the winning type including the replay combination is established, the symbol combination corresponding to any of the replay combinations included in the winning type is always on the activated line A. After the display is performed and the processing required to play the next game without medals is performed, the internal winning flag is turned OFF.

(Transition of game state)
Here, the game state transition will be described with reference to FIG. Here, a plurality of game states such as a non-internal game state, an RBB internal game state, and an RBB active game state are prepared. Each game state is changed according to winning of a bonus combination, winning (activation), and termination, as described later.

The non-internal game state is a game state corresponding to an initial state in a plurality of game states. In such a non-internal game state, the winning probability of the replay combination is set to approximately 1/7.3. In addition, in the non-internal game state, the winning combination "RBB" is determined with a predetermined probability (for example, approximately 1/30).

The game state control means 612 changes the game state according to winning of the winning combination “RBB”. For example, in a game in which the winning combination "RBB" is won, when the symbol combination corresponding to the winning combination "RBB" is displayed on the activated line A, the game state control means 612 changes the game state to the RBB active game state. Migrate (1).

In the RBB active gaming state, the probability of winning the replay combination is set to zero. In the gaming state during the RBB operation, the winning types that can be won are the winning type "small hand ALL" in the winning area 1, and the winning types "1 card ALLA" and "1 card ALLB" in the winning areas 2 and 3. is set. When the winning type ``small hand ALL'' is won, the symbol combination corresponding to any of the winning hand ``small hand 1'' to ``small hand 39'' is displayed on the effective line A, and the winning type ``1 card ALL'' is won. Then, stop control is performed so that the symbol combination corresponding to any one of the winning combination “small combination 11” to “small combination 39” is displayed on the activated line A. Here, the expected winning number per unit game in the RBB-activated game state is lowered by such a configuration of the small combination.

When the conditions for ending the RBB-activated gaming state are met, that is, when the acquired number reaches a predetermined number, the gaming state control means 612 shifts the gaming state to the non-internal gaming state (2).

On the other hand, in the game in which the winning combination "RBB" is won, if the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the activated line A, the game state control means 612 changes the game state to the inside of the RBB. Transition to a middle game state (special game state) (3).

In the RBB internal gaming state, the winning probability of the replay combination is set to about 1/5.9. In addition, in the RBB internal gaming state, the winning type "loss" is not won. In other words, when the symbol combination corresponding to the winning hand "RBB" cannot be displayed on the activated line A in the winning game of the winning hand "RBB", after that, the winning hand "RBB" is replaced by a smaller combination or a smaller combination. Since the replay combination is preferentially stopped on the activated line A, the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the activated line A. - 特許庁Therefore, once the gaming state shifts to the RBB inside gaming state, the RBB inside gaming state is maintained without transition of the gaming state thereafter. Here, while maintaining the RBB inside game state, the AT effect state is realized in the RBB inside game state.

Here, in the RBB internal middle game state, since a plurality of types of correct hands are won without overlapping each other, the chances of winning the correct hands can be increased. By performing the auxiliary performance in the AT performance state in the state, it is possible to easily obtain medals. On the other hand, in the game state during RBB operation, since a plurality of types of correct hands are won in duplicate, there are few opportunities for winning the correct hands, so the correct hands are awarded more than in the AT presentation state in other game states. This reduces the number of chances that a player can play, which makes it difficult for a player to increase the number of medals he or she owns. Therefore, while providing the function of the RBB operating game state that the probability of winning a winning combination is higher than that of the RBB inside game state, the RBB operating game state is equivalent to the RBB inside game state in terms of medal acquisition performance. A specification (acceleration RBB) of being inferior can be realized.

(Transition of production state)
FIG. 81 is an explanatory diagram for explaining the transition of the effect state. Hereinafter, the effect state (non-AT effect state, AT effect state) to be changed by the effect state control means 614 in the main control board 500 will be described in detail. In addition, below, the case where the game state is the RBB inside game state will be described.

Here, in order to comprehensively and uniformly determine whether or not the game state with high medal acquisition performance is biased, the game section having the performance related to the instruction function, that is, the auxiliary performance (instruction function) is executed. A game section that is advantageous to the player, including a game section, is defined as an advantageous section (specific section). In the advantageous section, as a result of performing a lottery related to the operation of the auxiliary effect on the main control board 500, when the auxiliary effect is activated, the main control board 500 can identify the content of the instruction, for example, the main notification This is a game section in which instruction information may be transmitted to peripheral boards such as the sub-control board 502 only when it is displayed on the means. A game section different from the advantageous section is defined as a non-advantageous section. Therefore, a plurality of production states (non-AT production state, AT production state) belong to either the advantageous section or the non-advantageous section which are game sections. In this embodiment, almost all production states belong to the advantageous section, and the non-advantageous section is realized in a part of the non-AT production state (here, the non-advantageous production state).

In the advantageous section, among the winning modes in which the correct role is lost if there is no assistance effect, in the selected winning type in which the payout for the correct role is the maximum (here, 11), the assistance that assists the winning of the correct role When an effect (auxiliary effect for obtaining the maximum number of coins to be paid out) is performed, for example, the section indicator 460 must be turned on to notify that fact.

In addition, in the non-advantageous section, it is possible to change the winning probability of the winning type for each set value, but the probability of determining the transition to the effect state (AT effect state) accompanied by the auxiliary effect in the same winning type must not be different for each set value. On the other hand, in the advantageous section, the winning probability of the winning type and the probability of determining the transition (or addition) to the production state (AT production state) with the auxiliary production in the same winning type are different for each set value. It is possible to

Therefore, the production state control means 614 manages the transition between the non-advantageous section and the advantageous section in addition to managing the transition of the production state. In addition, regardless of such management, the advantageous section is forcibly terminated by satisfying the following termination conditions. For example, the value counted in the advantageous section reaches a predetermined value (for example, the number of staying games (the number of game executions) reaches 1500 games, or the number of acquired sheets (net increase number) exceeds 2400) to force quit. In either case, the effect state control means 614 resets all the information updated in the advantageous section (all variables affecting the performance related to the instruction function) by shifting from the advantageous section to the non-advantageous section. .

(Non-AT production state, AT production state)
In the non-AT production state, the execution frequency of the auxiliary production is much lower than in the AT production state, and the auxiliary production is almost not performed, so the number of medals that can be obtained is limited. Here, six performance states such as a normal performance state, a non-advantageous performance state, a preparation performance state, a first interval performance state, a continuous lottery performance state, and a second interval performance state are provided as non-AT performance states.

In the AT performance state, it is possible to obtain a large number of medals while suppressing the consumption of medals by causing the assistance performance executing means to execute the assistance performance when all the selected winning types are won. Therefore, by shifting to the AT effect state, the player can progress the game more advantageously than in the non-AT effect state. Here, a pseudo bonus effect state is provided as the AT effect state. Each effect state (normal effect state, pseudo-bonus effect state, non-advantageous effect state, preparation effect state, first interval effect state, continuous lottery effect state, second interval effect state) will be individually described below.

(Each production state)
The normal rendering state is a rendering state corresponding to the initial state among a plurality of rendering states. The production state control means 614 performs AT lottery in the normal production state. The AT lottery is a lottery for determining transition to the AT performance state, and the performance state control means 614 performs the AT lottery with different probabilities for each winning type determined by the winning type lottery. Then, when the AT lottery is won, the performance state control means 614 shifts the performance state to the pseudo bonus performance state which is the AT performance state after the predetermined number of precursor games has passed (1). Further, when a predetermined ceiling condition (for example, a predetermined number of games are played continuously in the normal production state) is satisfied in the normal production state without transitioning to the pseudo-bonus production state (so-called ceiling reached), the production state control means 614 shifts the performance state to a pseudo-bonus performance state (1).

In the pseudo-bonus effect state, an auxiliary effect is executed until a predetermined end condition (for example, the number of games played reaches a predetermined number of games) is satisfied, and the player can, for example, expect to win in the pseudo-bonus effect state. A number of 3.5 sheets can be obtained. Incidentally, in the pseudo bonus effect state, mainly two end conditions are prepared. For example, if the end condition is that the number of games played reaches the predetermined number of games, two levels of 30 and 80 are provided as the predetermined number of games, and either one is determined by lottery. In the pseudo-bonus effect state, the player naturally obtains more game profits as the number of games played increases. Therefore, the player would want the predetermined number of games to be 80, not 30. However, even if 30 is determined as the predetermined number of games, a promotion lottery is also performed to increase the predetermined number of games of the auxiliary effect from 30 to 80 during the completion of the predetermined number of games. Here, as an example of the termination condition of the pseudo-bonus effect state, the number of games played has reached the predetermined number of games. Reaching a certain number or reaching a predetermined number of acquired sheets (net increased number of sheets) may be employed.

Then, when a predetermined end condition is satisfied in the pseudo-bonus effect state, the effect state control means 614 may shift the effect state to a non-advantageous effect state (2). At this time, the effect state control means 614 temporarily shifts the advantageous section to the non-advantageous section, and resets all the information updated in the advantageous section. For example, if the preceding pseudo-bonus effect state is the initial pseudo-bonus effect state, that is, if it is the pseudo-bonus effect state immediately after shifting from the normal effect state, the effect state control means 614 changes the effect state to a non-advantageous state. While shifting to the performance state, the advantageous section is temporarily shifted to the non-advantageous section. In addition, even if the pseudo-bonus effect state in the previous stage is the pseudo-bonus effect state of the multiples of 3 (3, 6, . . . ) that does not go through the normal effect state, , shifts to a non-advantageous section, and temporarily shifts the advantageous section to a non-advantageous section.

Then, the effect state control means 614 draws a lottery for the transition to the advantageous section with a high probability (for example, 1/2), returns to the advantageous section after playing a few games, and shifts the effect state to the preparation effect state ( 3). This is to avoid the pseudo-bonus effect state from being forcibly terminated when the value counted in the advantageous section reaches a predetermined value.

On the other hand, if the pseudo-bonus effect state in the preceding stage is not the first time, or if it is not the pseudo-bonus effect state of the multiple times of 3 that does not pass through the normal effect state, the effect state control means 614 shifts the effect state to the non-advantageous effect state. (4). This is to prevent the pseudo-bonus effect state from being forcibly terminated when the value counted in the advantageous interval reaches a predetermined value, and to prevent the advantageous interval from ending unnecessarily.

In the preparation production state, the production state control means 614 draws a lottery for transition to the first interval production state with a high probability (for example, 1/2), and based on the determination of the transition to the first interval production state, the production state is changed. to the first interval effect state (5).

The first interval effect state continues until a predetermined end condition (for example, completion of 40 games) is satisfied, during which a continuation lottery for the pseudo-bonus effect state is executed. Unlike the pseudo-bonus effect state, the first interval effect state is different from the pseudo-bonus effect state in that the number of expected wins per unit game is small and may have a negative value. In addition, in the present embodiment, the effect state is set to always be the first interval effect state when the advantageous section is won in the non-advantageous section. Therefore, after the pseudo-bonus effect state ends, even if the advantageous section continues, or if the transition to the non-advantageous section is made once as described above, the transition to the first interval effect state is made. becomes. Then, when a predetermined termination condition in the first interval effect state is satisfied, the effect state control means 614 shifts the effect state to the continuous lottery effect state (6).

The continuous lottery effect state continues until a predetermined termination condition (for example, completion of 5 games) is satisfied, and finally, the result of the continuous lottery of the pseudo-bonus effect state in the first interval effect state is reported. Unlike the pseudo-bonus effect state, the expected winning number per unit game is small in such a continuous lottery effect state, and the value may be negative. In the first interval effect state, if the transition (continuation) to the pseudo-bonus effect state is determined, the effect state control means 614 shifts the effect state to the pseudo-bonus effect state (7), and the pseudo-bonus effect state. , the production state control means 614 returns the production state to the normal production state (8).

As described above, in the present embodiment, once the pseudo bonus effect state is entered, the pseudo bonus effect state→preparation effect state→first interval effect state→continuous lottery effect state, unless the continuous lottery of the continuous lottery effect state is missed. By repeating the transition of , the player can accumulate medals.

In addition, in the preparation production state, the production state control means 614 performs a lottery for the transition to the second interval production state in addition to the lottery for the transition to the first interval production state. However, the probability of transition to the second interval effect state (eg, 1/20) is set smaller than the probability of transition to the first interval effect state (eg, 1/2). In the preparation production state, when the transition to the second interval production state is determined before the transition to the first interval production state is determined, the production state control means 614 determines the transition to the second interval production state. Based on (9), the production state is shifted to the second interval production state. Here, an example is given in which the lottery for transition to the second interval effect state is performed in the preparatory effect state, but similarly, the lottery for transition to the second interval effect state may be performed in the non-advantageous effect state.

Like the first interval effect state, the second interval effect state continues until a predetermined end condition (for example, completion of 40 games) is satisfied, during which a continuation lottery for the pseudo-bonus effect state is executed. Like the first interval effect state, the second interval effect state differs from the pseudo bonus effect state in that the number of expected wins per unit game is small and may have a negative value.

However, in the second interval effect state, the pseudo bonus effect state is determined with a higher probability than in the first interval effect state. For example, in the first interval effect state, the pseudo-bonus effect state is determined at 1/58 every game for 40 games (winning probability 50%), and in the second interval effect state, the pseudo-bonus effect state is determined for 40 games. is determined at every game 1/25 (winning probability 80%). Then, when a predetermined termination condition is satisfied, the effect state control means 614 shifts the effect state to the continuous lottery effect state (10). Once it is decided to shift to the second interval effect state, after that, there is no transition to the non-advantageous effect state, the preparation effect state, or the first interval effect state until it leaks to the continuous lottery effect state. From the pseudo-bonus effect state, only the second interval effect state is entered (11). Therefore, the player can always receive a continuous lottery with a high probability. Further, once the transition to the second interval effect state is determined, even if the transition to the pseudo bonus effect state is not determined in the continuous lottery effect state, the effect state control means 614 immediately changes the effect state. The state is shifted to a non-advantageous performance state without returning to the normal performance state (12). Therefore, when the transition to the pseudo-bonus effect state is not determined in the continuous lottery effect state, the pseudo-bonus effect state→preparation effect state→first interval effect state→continuation until the continuous lottery of the continuous lottery effect state fails again. The transition of the lottery effect state can be repeated. In this way, once the state is shifted to the second interval effect state, the transition from the pseudo bonus effect state→the second interval effect state→continuous lottery effect state can be repeated with high probability, and further, the pseudo bonus effect state→the second interval effect state→continuous lottery effect state can be repeated, and further, the pseudo bonus effect state can be repeated in the continuous lottery effect state. Even if the transition to the bonus performance state is not determined, at least, the transition from the pseudo bonus performance state→preparation performance state→first interval performance state→continuous lottery performance state can be repeated again, so that the player can play more games. medals can be accumulated. That is, it can be said that the second interval effect state is more advantageous than the first interval effect state.

Further, as described above, the effect state control means 614, when shifting from the pseudo-bonus effect state to the second interval effect state, can shift to the non-advantageous section unlike the transition to the first interval effect state. do not have. In the present embodiment, when the pseudo-bonus effect state is the initial pseudo-bonus effect state, the effect state control means 614 does not shift to the second interval effect state, and temporarily changes the advantageous section to the non-advantageous section. , and be sure to shift to the first interval performance state. Then, the advantageous section is reset once. Therefore, even if the advantageous section is not reset when shifting to the second interval presentation state, the pseudo-bonus presentation state passing through the second interval presentation state will not be terminated in a short period of time due to the limitation of the advantageous section, and the player will be able to A lot of medals can be obtained by a loop of pseudo bonus effect state→second interval effect state→continuous lottery effect state.

Specific processing in the main control board 500 and the sub-control board 502 will be described below with reference to flowcharts.

(CPU initialization processing of main control board 500)
FIG. 82 is a flow chart for explaining CPU initialization processing in the main control board 500 . When power is supplied from the power board, a system reset occurs in the main CPU 500a, and the main CPU 500a performs the following CPU initialization processing (S2000).

(Step S2000-1)
When the power is turned on, the main CPU 500a reads a startup program from the main ROM 500b as an initial setting process, and performs setting processes necessary for executing various processes.

(Step S2000-3)
The main CPU 500a sets the wait processing time in the timer counter.

(Step S2000-5)
The main CPU 500a determines whether a power-off warning signal is detected. A power interruption detection circuit is provided in the main control board 500, and when the power supply voltage drops below a predetermined value, a power interruption warning signal is output from the power interruption detection circuit. If the power-off notice signal is detected, the process proceeds to step S2000-3, and if the power-off notice signal is not detected, the process proceeds to step S2000-7.

(Step S2000-7)
The main CPU 500a determines whether or not the wait processing time set in step S2000-3 has elapsed. As a result, if it is determined that the wait processing time has elapsed, the process proceeds to step S2000-9, and if it is determined that the wait time has not elapsed, the process proceeds to step S2000-5.

(Step S2000-9)
The main CPU 500a executes necessary processing to permit access to the main RAM 500c.

(Step S2000-11)
The main CPU 500a executes checksum confirmation processing. Here, the main CPU 500a calculates the checksum and determines whether the calculated checksum does not match the checksum saved at the time of power failure (abnormality) and whether the backup is abnormal. If the main CPU 500a determines that either one or both of the backup and the checksum are abnormal, the main CPU 500a turns on the backup abnormality flag. Turn off.

(Step S2000-13)
The main CPU 500a determines whether the backup abnormality flag is on. As a result, when it is determined that the backup abnormality flag is on, the process proceeds to step S2010, and when it is determined that the backup abnormality flag is not on, the process proceeds to step S2020.

(Step S2010)
The main CPU 500a executes cold start processing. This cold start processing will be described later.

(Step S2020)
The main CPU 500a executes setting value switching processing for switching setting values. This set value switching process will be described later.

(Step S2030)
The main CPU 500a executes a state recovery process for returning to the state immediately before the power was turned off. This state return processing will be described later.

FIG. 83 is a flow chart for explaining cold start processing (S2010) in the main control board 500. FIG.

(Step S2010-1)
The main CPU 500a clears the used area in the main RAM 500c and executes used area RAM check processing for detecting an abnormality in the used area.

(Step S2010-3)
The main CPU 500a clears another area (unused area) in the main RAM 500c, and executes a separate area RAM check process for detecting an abnormality in the separate area. If an abnormality is detected in another area in the separate area RAM check process, the main CPU 500a turns on the RAM read/write error flag.

(Step S2010-5)
The main CPU 500a sets an error code "EA" indicating an abnormality in the main RAM 500c.

(Step S2010-7)
The main CPU 500a determines whether an abnormality has been detected in step S2010-1. As a result, when it is determined in step S2010-1 that an abnormality has been detected, the process proceeds to step S2011, and when it is determined in step S2010-1 that no abnormality has been detected, the process proceeds to step S2010-9. transfer processing.

(Step S2010-9)
The main CPU 500a acquires a RAM read/write error flag that is turned on when an abnormality is detected in step S2010-3.

(Step S2010-11)
The main CPU 500a determines whether the RAM read/write error flag is on. As a result, when it is determined that the RAM read/write error flag is ON, the process proceeds to step S2011, and when it is determined that the RAM read/write error flag is not ON, the process proceeds to step S2020.

(Step S2020)
The main CPU 500a executes setting value switching processing for switching setting values. This set value switching process will be described later.

(Step S2010-13)
The main CPU 500a sets an error code "E7" indicating a backup error.

(Step S2011)
The main CPU 500a executes error stop processing for stopping the progress of the game due to an error. This error stop processing will be described later.

FIG. 84 is a flowchart for explaining the error stop processing (S2011) in the main control board 500. FIG.

(Step S2011-1)
The main CPU 500a sets the initial stack pointer value as the address of the stack pointer.

(Step S2011-3)
The main CPU 500a executes error setting processing for setting error display and warning sound.

(Step S2011-5)
The main CPU 500a sets the external signal 1-3 output bit off to turn off the output image of the bit corresponding to the external signal 1-3.

(Step S2011-7)
The main CPU 500a executes output port image setting processing for updating the output image for the bit set in step S2011-5.

(Step S2011-9)
The main CPU 500a shifts to an endless loop. As a result, the progress of the game is stopped.

FIG. 85 is a flowchart for explaining the setting value switching process (S2020) in the main control board 500. FIG.

(Step S2020-1)
The main CPU 500a acquires the signal of the input port 1, and determines whether or not the set value switching condition is satisfied based on the acquired signal of the input port 1. FIG. As a result, if it is determined that the set value switching condition is not satisfied, the set value switching process is terminated, and if it is determined that the set value switching condition is satisfied, the process proceeds to step S2020-3. . Here, the signal of the input port 1 includes a signal indicating whether the front upper door 404 and the front lower door 406 are open and a signal indicating whether the setting door key is turned on. Here, when a signal indicating that the front upper door 404 and the front lower door 406 are open and a signal indicating that the setting door key is turned on are obtained, the setting value switching condition is satisfied. It is determined that

(Step S2020-3)
The main CPU 500a executes a RAM clearing process for clearing a used area to be cleared when changing settings in the main RAM 500c.

(Step S2020-5)
The main CPU 500a executes a table content setting process for transferring the table data of the setting value switching time data table to the main RAM 500c.

(Step S2020-7)
The main CPU 500a sets, in the transmission buffer, a setting change start command indicating to start changing setting values.

(Step S2020-9)
The main CPU 500a executes edge check processing for detecting the rising edge (ON edge) and falling edge (OFF edge) of the signal of the input port.

(Step S2020-11)
The main CPU 500a acquires setting value data indicating the current setting value.

(Step S2020-13)
The main CPU 500a determines whether or not the ON edge of the setting change switch is detected in step S2020-9. As a result, if it is determined that the ON edge of the setting change switch has not been detected, the process proceeds to step S2020-17, and if it is determined that the ON edge of the setting change switch has been detected, the process proceeds to step S2020-15. .

(Step S2020-15)
The main CPU 500a increments the set value data by one.

(Step S2020-17)
The main CPU 500a determines whether the set value data is within the range (1 to 6) that can be set as the set value. As a result, if it is determined that the set value data is within the range, the process moves to step S2020-21, and if it is determined that the set value data is not within the range, the process moves to step S2020-19.

(Step S2020-19)
The main CPU 500a sets the set value data to zero.

(Step S2020-21)
The main CPU 500a updates the set value data to the value incremented or set in step S2020-15 or step S2020-19.

(Step S2020-23)
The main CPU 500 a executes display data conversion processing for displaying the set value on the main credit display section 430 .

(Step S2020-25)
The main CPU 500a determines whether or not the ON edge of the setting change switch is detected. As a result, if it is determined that the ON edge of the setting change switch has not been detected, the process proceeds to step S2020-31, and if it is determined that the ON edge of the setting change switch has been detected, the process proceeds to step S2020-27. to move.

(Step S2020-27)
The main CPU 500a determines whether the setting change switch is on. As a result, when it is determined that the setting change switch is on, the process proceeds to step S2020-27, and when it is determined that the setting change switch is not on, the process proceeds to step S2020-29.

(Step S2020-29)
The main CPU 500a sets a setting change switch interval timer.

(Step S2020-31)
The main CPU 500a executes timer wait processing to wait until the setting change switch interval timer reaches zero.

(Step S2020-33)
The main CPU 500a determines whether the ON edge of the start switch 418 is detected. As a result, if it is determined that the ON edge of the start switch 418 has not been detected, the process proceeds to step S2020-9, and if it is determined that the ON edge of the start switch 418 has been detected, the process proceeds to step S2020-35. to move.

(Step S2020-35)
The main CPU 500a determines whether the set door key is off. As a result, when it is determined that the set door key is off, the process proceeds to step S2020-35, and when it is determined that the set door key is not off, the process proceeds to step S2020-37.

(Step S2020-37)
The main CPU 500a determines whether the set door key is on. As a result, when it is determined that the set door key is on, the process proceeds to step S2020-37, and when it is determined that the set door key is not on, the process proceeds to step S2021.

(Step S2021)
The main CPU 500a executes initialization start processing for starting initialization. This initialization start process will be described later.

FIG. 86 is a flow chart for explaining the initialization start process (S2021) in the main control board 500. FIG.

(Step S2021-1)
The main CPU 500a sets, in the transmission buffer, a setting change end command indicating that the change of the setting value has been completed.

(Step S2021-3)
The main CPU 500a sets, in the transmission buffer, a setting change state command indicating the state when the change of the setting value is completed.

(Step S2021-5)
The main CPU 500a sets a wait timer at the start of initialization.

(Step S2021-7)
The main CPU 500a executes a timer wait process of waiting until the wait timer reaches 0 at the start of initialization.

(Step S2021-9)
The main CPU 500a executes RAM clear processing at the time of setting change to clear another area of the main RAM 500c.

(Step S2021-11)
The main CPU 500a executes a RAM clearing process for clearing a used area to be cleared when changing settings in the main RAM 500c.

(Step S2021-13)
The main CPU 500a sets a game state command indicating the current game state in the transmission buffer.

(Step S2100)
The main CPU 500a executes a game start process for starting a game. Note that this game start processing will be described later.

FIG. 87 is a flow chart for explaining the state return processing (S2030) in the main control board 500. FIG.

(Step S2030-1)
The main CPU 500a restores the stack pointer.

(Step S2030-3)
The main CPU 500a executes unused area clearing processing for clearing unused areas in the main RAM 500c.

(Step S2030-5)
The main CPU 500a clears the stack pointer save buffer.

(Step S2030-7)
The main CPU 500a sets (turns on) the post-power-off recovery flag.

(Step S2030-9)
The main CPU 500a executes port input processing for updating the image of the input port.

(Step S2030-11)
The main CPU 500a executes operation target bit extraction processing for extracting information on the operation target bit based on the image of the input port updated in step S2030-9.

(Step S2030-13)
The main CPU 500a sets the operation target bit extracted in step S2030-11 as the operation target bit of the previous state.

(Step S2030-15)
The main CPU 500a acquires the motor phases of the reels 410a, 410b, and 410c. Here, motor phases are set as the states of the reels 410a, 410b, and 410c. The motor phase indicates the operating state of the reels 410a, 410b, 410c, ie, during acceleration, during steady rotation, during stop, and during standby. Specifically, the 1-byte (storage unit) variable assigned to the motor phase is accelerated = 3, steady rotation = 2, stopped = 1, and waiting = It changes to a value such as 0.

(Step S2030-17)
The main CPU 500a determines whether or not any of the reels 410a, 410b, and 410c are rotating normally and accelerating based on the motor phase acquired in step S2030-15. As a result, if it is determined that none of the reels 410a, 410b, and 410c are in steady rotation or acceleration, the process proceeds to step S2030-21, and any one of the reels 410a, 410b, and 410c is in steady rotation or acceleration. If it is determined to be in the middle, the process moves to step S2030-19.

(Step S2030-19)
The main CPU 500a executes rotation error processing for making settings when an error is detected for the reels 410a, 410b, and 410c.

(Step S2030-21)
The main CPU 500a restores the saved register group.

(Step S2030-23)
The main CPU 500a permits the interrupt and terminates the state return processing. As a result, the main CPU 500a returns to the state immediately before the power was turned off.

FIG. 88 is a flowchart for explaining the game start process (S2100) in the main control board 500. FIG.

(Step S2100-1)
The main CPU 500a executes a replay state identification signal output setting process for outputting a replay state identification signal indicating whether or not it is a replay.

(Step S2100-3)
The main CPU 500a sets an input number display output bit OFF for turning off (turning off) the bit corresponding to the input number display indicating the number of inserted medals (number of bets).

(Step S2100-5)
The main CPU 500a executes output port image setting processing for updating the output image for the bit set in step S2100-3.

(Step S2100-7)
The main CPU 500a sets a game start wait timer.

(Step S2100-9)
The main CPU 500a executes timer wait processing for waiting until the game start wait timer reaches zero.

(Step S2100-11)
The main CPU 500a executes a 1-game RAM clearing process for clearing an area to be cleared for each game out of the used area in the main RAM 500c.

(Step S2100-13)
The main CPU 500a executes bonus signal setting processing for setting a bonus signal.

(Step S2100-15)
The main CPU 500a executes edge clear processing for clearing the edge information of the input port image.

(Step S2200)
The main CPU 500a executes a game medal insertion process for accepting insertion of medals. This game medal insertion process will be described later.

FIG. 89 is a flow chart for explaining the game medal insertion process (S2200) in the main control board 500. FIG.

(Step S2200-1)
The main CPU 500a executes error confirmation processing for confirming detection results of various errors.

(Step S2200-3)
The main CPU 500a executes edge check processing for detecting the rising edge (ON edge) and falling edge (OFF edge) of the signal of the input port.

(Step S2200-5)
The main CPU 500a acquires a door open error detection flag that is set to 1 when the front upper door 404 or the front lower door 406 is open.

(Step S2200-7)
Main CPU 500a determines whether front upper door 404 and front lower door 406 are closed based on the door open error detection flag obtained in step S2200-5. As a result, when it is determined that the front upper door 404 and the front lower door 406 are closed, the process moves to step S2200-17, and at least one of the front upper door 404 or the front lower door 406 is not closed. If so, the process moves to step S2200-9.

(Step S2200-9)
The main CPU 500a sets an error code "E8" indicating that at least one of the front upper door 404 and the front lower door 406 is open.

(Step S2200-11)
The main CPU 500a performs error display, request for warning sound, and error wait processing for waiting for error recovery.

(Step S2200-13)
The main CPU 500a executes setting value confirmation processing for confirming the setting values.

(Step S2200-15)
The main CPU 500a executes edge clear processing for clearing the edge information of the input port image.

(Step S2200-17)
The main CPU 500a executes a credit button check process for withdrawing accumulated medals when a credit switch (not shown) for withdrawing accumulated (credited) medals is pressed.

(Step S2200-19)
The main CPU 500a executes game medal insertion button related processing for betting medals. Here, when the bet switch 416 is pressed, a specified number of accumulated (credited) medals is betted, and the number of accumulated medals is subtracted by the number of bets. Also, when medals are inserted through the medal slot 414a, the medals are bet up to a specified number, and if more medals than the specified number are inserted, that amount is added to the number of stored medals.

(Step S2200-21)
The main CPU 500a executes game medal acquisition processing for confirming whether the number of inserted coins is a specified number.

(Step S2200-23)
The main CPU 500a determines whether or not the number of inserted coins is not the specified number based on the confirmation result of step S2200-21. As a result, if it is determined that the inserted number is not the specified number, the process proceeds to step S2200-1, and if it is determined that the inserted number is the specified number, the process is transferred to step S2200-25.

(Step S2200-25)
The main CPU 500a sets a start indicator output bit for turning on (lighting) a start indicator (not shown) that indicates whether the operation of the start switch 418 is valid.

(Step S2200-27)
The main CPU 500a determines whether the falling edge (depression) of the start switch 418 is detected. As a result, if it is determined that the falling edge of start switch 418 has not been detected, the process proceeds to step S2200-1, and if it is determined that the falling edge of start switch 418 has been detected, step S2200. -29 is processed.

(Step S2200-29)
The main CPU 500 a clears the main payout display buffer to clear the display of the main payout display 432 .

(Step S2200-31)
The main CPU 500a executes re-gaming state identification signal clear processing for clearing the re-gaming state identification signal.

(Step S2200-33)
The main CPU 500a executes blocker blocking preprocessing for turning off (extinguishing) the start indicator.

(Step S2200-35)
The main CPU 500a sets a lever depression command indicating that the start switch 418 has been depressed in the transmission buffer.

(Step S2300)
The main CPU 500a executes an internal lottery process for performing a lottery by winning type. This internal lottery process will be described later.

FIG. 90 is a flowchart for explaining internal lottery processing (S2300) in main control board 500. FIG.

(Step S2300-1)
The main CPU 500a acquires set value data.

(Step S2300-3)
The main CPU 500a sets an error code "EC" indicating a setting value abnormality error.

(Step S2300-5)
The main CPU 500a determines whether the set value data obtained in step S2300-1 is abnormal. As a result, if it is determined that the set value data is abnormal, the process proceeds to step S2011, and if it is determined that the set value data is not abnormal, the process proceeds to step S2300-7.

(Step S2300-7)
The main CPU 500a acquires the winning type lottery random number updated by the random number generator 500d.

(Step S2300-9)
The main CPU 500a executes state offset acquisition processing for acquiring an offset value related to the game state.

(Step S2300-11)
The main CPU 500a sets the address of the internal lottery area definition table (winning type lottery table).

(Step S2300-13)
The main CPU 500a sets, as the initial value of the winning area, the value indicated by the address obtained by adding the offset value obtained in step S2300-9 to the address set in step S2300-11. Here, the first winning area in the winning type lottery table in the current gaming state is set as the initial value.

(Step S2300-15)
The main CPU 500a acquires lottery data, which is a numerical value indicating the winning range of the winning area, and executes lottery data acquisition processing for shifting the winning area by one.

(Step S2300-17)
The main CPU 500a determines whether or not the winning type lottery is performed. As a result, when it is determined that the winning type lottery will not be performed, the process is moved to step S2300-21, and when it is determined that the winning type lottery is to be performed, the process is moved to step S2300-19.

(Step S2300-19)
The main CPU 500a subtracts the lottery data from the random number value.

(Step S2300-21)
The main CPU 500a determines whether the result of the subtraction in step S2300-19 is negative, that is, whether the winning region has been won by the winning type lottery. As a result, when it is determined that the winning type lottery has been won, the process moves to step S2400, and when it is determined that the winning type lottery has not been won, the process moves to step S2300-23.

(Step S2300-23)
The main CPU 500a determines whether or not the winning type lottery has ended. As a result, when it is determined that the winning type lottery has not ended, the process moves to step S2300-15, and when it is determined that the winning type lottery has ended, the process moves to step S2300-25.

(Step S2300-25)
The main CPU 500a clears the trigger role type.

(Step S2400)
The main CPU 500a executes a symbol code setting process for setting a symbol code based on the winning area and the game state. This symbol code setting process will be described later.

FIG. 91 is a flow chart for explaining the symbol code setting process (S2400) in the main control board 500. FIG.

(Step S2400-1)
The main CPU 500a acquires the winning area that was won in step S2300, and if the acquired winning area includes a bonus combination, executes a game state setting process of setting the game state to the internal middle game state.

(Step S2400-3)
The main CPU 500a sets the winning area obtained in step S2400-1 as the stop control number.

(Step S2400-5)
The main CPU 500a determines (sets) the winning type based on the winning area acquired in step S2400-1.

(Step S2400-7)
The main CPU 500a executes a symbol code initial setting process for setting a symbol code indicating a symbol that can be displayed and a symbol to be drawn based on the stop control number set in step S2400-3.

(Step S2400-9)
The main CPU 500a executes display symbol bit initial value setting processing for setting display symbol bits.

(Step S2400-11)
The main CPU 500a executes an execution flag setting process for setting an execution flag, various processes related to the effect state, processing related to the auxiliary effect, and the like.

(Step S2400-13)
The main CPU 500a sets an effect command, which is a command relating to the advantageous section, in the transmission buffer.

(Step S2400-15)
The main CPU 500a sets a winning information command indicating the winning type in the transmission buffer.

(Step S2400-17)
The main CPU 500a checks the one-game timer.

(Step S2400-19)
The main CPU 500a sets a reel before rotation command indicating that the reels 410a, 410b and 410c are before rotation in the transmission buffer.

(Step S2400-21)
The main CPU 500a executes an excitation release waiting process for waiting for the excitation release of the stepping motor 452. FIG.

(Step S2400-23)
The main CPU 500a determines whether the one-game timer is not zero. As a result, when it is determined that the one-game timer is not 0, the process moves to step S2400-23, and when it is determined that the one-game timer is 0, the process moves to step S2400-25.

(Step S2400-25)
The main CPU 500a executes reel start processing for starting rotation of the reels 410a, 410b, and 410c. Here, the motor phases of the reels 410a, 410b, and 410c are set to acceleration to start the rotation of each reel, and the one-game timer is set to a value corresponding to 4.1 seconds.

(Step S2400-27)
The main CPU 500a sets a reel start command indicating that the reels 410a, 410b, and 410c have started rotating in the transmission buffer.

(Step S2500)
The main CPU 500a executes processing during reel rotation, which is processing during rotation of the reels 410a, 410b, and 410c. Note that this process during rotation of the drum will be described later.

FIG. 92 is a flowchart for explaining the process during drum rotation (S2500) in main control board 500. FIG.

(Step S2500-1)
The main CPU 500a sets the stop indicator output bit off (output image) to turn off (light off) the bit corresponding to the indicator (not shown) of the stop switches 420a, 420b, 420c. Here, the stop indicator output bit is composed of a 3-bit bit string, each bit corresponding to the emission color of the three stop switches 420a, 420b, and 420c, represented by blue=1 and red=0. be done.

(Step S2500-3)
Main CPU 500a executes output port image setting processing for updating the output image for the bit set in step S2500-1.

(Step S2500-5)
The main CPU 500a executes error confirmation processing for confirming detection results of various errors.

(Step S2500-7)
The main CPU 500a refers to the index flags and obtains the indexes of the rotating reels 410a, 410b, and 410c. Note that the index flag is set only after the reels 410a, 410b, and 410c reach the constant rotation speed. It also indicates that the speed has been reached.

(Step S2500-9)
The main CPU 500a determines whether the index flags of all the reels 410a, 410b, and 410c have been detected. As a result, if it is determined that all index flags have not been detected, the process proceeds to step S2500-1, and if it is determined that all index flags have been detected, the process proceeds to step S2500-11.

(Step S2500-11)
The main CPU 500a acquires a stop spinning reel bit indicating the reels 410a, 410b, and 410c that are stopping or starting to stop. Here, the stop reel bit is composed of a 3-bit bit string, and each bit is associated with one of the three reels 410a, 410b, and 410c. Or it is represented by stop state=0.

(Step S2500-13)
The main CPU 500a saves the stop reel bit acquired in step S2500-11 as a reel rotating flag.

(Step S2500-15)
The main CPU 500a sets the stop indicator output bit ON (output image) to turn on (light off) the bit corresponding to the indicator (not shown) of the stop switches 420a, 420b, 420c.

(Step S2500-17)
The main CPU 500a acquires the image of the input port 0, and executes operation target bit extraction processing for extracting the operation target bit from the acquired image. Here, the operation target bit is composed of a 3-bit bit string, and each bit is associated with one of the three stop switches 420a, 420b, and 420c. =0.

(Step S2500-19)
The main CPU 500a performs a logical product operation between the spinning drum flag obtained in step S2500-13 and the operation target bit extracted in step S2500-17. Here, if the reel 410 is rotating and the stop switch 420 corresponding to the reel is operated, that is, if the operated stop switch 420 corresponds to the effectively rotating reel 410 , the logical AND is 1.

(Step S2500-21)
The main CPU 500a determines whether the AND calculated in step S2500-19 is 0, that is, whether the stop switch 420 corresponding to the rotating reel 410 has been operated. As a result, when it is determined that the stop switch 420 corresponding to the rotating reel 410 is not operated, the process is shifted to step S2500-3, and the stop switch 420 corresponding to the rotating reel 410 is operated. If it is determined that there is, the process moves to step S2500-23.

(Step S2500-23)
The main CPU 500a acquires the output image including the stop indicator output bit, and computes the logical product of the acquired output image and the logical product computed in step S2500-19. Here, the logical product bit is 0 when the operated stop switch 420 is lit in red, and the bit of logical product is 1 when it is lit in blue.

(Step S2500-25)
The main CPU 500a determines whether the logical product calculated in step S2500-23 is 0, that is, whether the operated stop switch 420 is lit in red. As a result, if it is determined that the operated stop switch 420 is lit in red, the process proceeds to step S2500-1, and if it is determined that the operated stop switch 420 is not lit in red, step S2500- 27 is processed.

(Step S2500-27)
The main CPU 500a determines whether the operated stop switch 420 is not valid. As a result, if it is determined that the operated stop switch 420 is not valid, the process proceeds to step S2500-1, and if it is determined that the operated stop switch 420 is valid, the process proceeds to step S2500-29. Transfer. Here, it is determined whether or not one stop switch 420 has been operated. If it is determined that one stop switch 420 has been operated, the process proceeds to step S2500-29, and if it is determined that there are two or more stop switches 420 operated to step S2500-1.

(Step S2500-29)
The main CPU 500a executes stop control reel setting processing for acquiring various parameters for stopping the reel 410 corresponding to the operated stop switch 420. FIG.

(Step S2500-31)
The main CPU 500a prohibits interrupts.

(Step S2500-33)
The main CPU 500a executes a depression reference position acquisition process for deriving the symbol number of the symbol positioned on the activated line A as the depression reference position.

(Step S2500-35)
The main CPU 500 a executes a sliding frame number acquisition process for determining the number of sliding frames of the reel 410 .

(Step S2600)
The main CPU 500a executes reel stop processing for stopping the reel 410 corresponding to the stop switch 420 that has been operated. Note that this spinning drum stop processing will be described later.

FIG. 93 is a flow chart for explaining the spinning drum stopping process (S2600) in the main control board 500. FIG.

(Step S2600-1)
The main CPU 500a acquires the depression reference position derived in step S2500-35.

(Step S2600-3)
The main CPU 500a calculates the stop request number by correcting the number of sliding frames determined in step S2500-37 with respect to the depression reference position acquired in step S2600-1.

(Step S2600-5)
The main CPU 500a sets (sets to 1) a stop request flag. The stop request flag is a flag for requesting the stop processing of the target reel 410 to the programs that operate in parallel. By setting the stop request flag to 1, the symbol corresponding to the stop request number is enabled. It becomes possible to stop on line A. The stop request flag and the stop request number are read out by a program running in parallel, and the reel 410 is stopped. When the stop processing is completed, the program resets the stop request flag to 0 (OFF).

(Step S2600-7)
The main CPU 500a permits interrupts.

(Step S2600-9)
The main CPU 500a sets a stop information command indicating the stop order of the reels 410 in the transmission buffer.

(Step S2600-11)
The main CPU 500a sets the stop indicator output bit off (output image) to turn off (light off) the bit corresponding to the indicator (not shown) of the stop switch 420. FIG.

(Step S2600-13)
The main CPU 500a executes output port image setting processing for updating the output image for the bit set in step S2600-11.

(Step S2600-15)
The main CPU 500a executes display symbol bit setting processing for setting display symbol bits.

(Step S2600-17)
The main CPU 500a executes the next cylinder setting preprocessing for stopping the next reel 410. FIG.

(Step S2600-19)
The main CPU 500a determines whether the stop processing of all the reels 410 has been completed. As a result, if it is determined that the stop processing for all the reels 410 has not been completed, the process proceeds to step S2500, and if it is determined that the stop processing for all the reels 410 has been completed, the process proceeds to step S2600-21. transfer processing.

(Step S2600-21)
The main CPU 500a determines whether the stop request flag is ON for any reel 410, that is, whether all the reels 410 have stopped. As a result, if it is determined that all the reels 410 have not stopped, the process moves to step S2600-21, and if it is determined that all the reels 410 have stopped, the process moves to step S2600-23.

(Step S2600-23)
The main CPU 500a executes error confirmation processing for confirming detection results of various errors.

(Step S2600-25)
The main CPU 500a executes an operation target bit extraction process for extracting information on the operation target bit.

(Step S2600-27)
The main CPU 500a determines whether the stop switch 420 is pressed based on the operation target bit obtained in step S2600-25. As a result, if it is determined that stop switch 420 has been pressed, the process proceeds to step S2600-23, and if it is determined that stop switch 420 has not been pressed, the process proceeds to step S2700.

(Step S2700)
The main CPU 500a executes a display determination process for determining a winning winning combination. Note that this display determination processing will be described later.

FIG. 94 is a flow chart for explaining the display determination process (S2700) in main control board 500. FIG.

(Step S2700-1)
The main CPU 500 a clears the buffer of the main payout display section 432 .

(Step S2700-3)
The main CPU 500a determines whether or not a display determination abnormality has occurred, depending on whether or not the symbol combination displayed on the activated line A matches the symbol combination permitted to be displayed on the activated line A. Execute the detection process.

(Step S2700-5)
The main CPU 500a sets an error code "EE" indicating display determination abnormality (error).

(Step S2700-7)
The main CPU 500a determines whether display determination is abnormal based on the determination result of step S2700-3. As a result, if it is determined that the display determination is abnormal, the process moves to step S2011, and if it is determined that the display determination is not abnormal, the process moves to step S2700-9.

(Step S2700-9)
The main CPU 500a executes display symbol identification and generation processing for determining a winning combination based on the symbol combination stopped (displayed) on the activated line A.

(Step S2700-11)
The main CPU 500a sets 0 as the initial value of the payout number.

(Step S2700-13)
The main CPU 500a determines whether or not a minor win has been won. As a result, when it is determined that a minor winning combination has been won, the process proceeds to step S2700-15, and when it is determined that a minor winning combination has not been won, the process proceeds to step S2700-35.

(Step S2700-15)
The main CPU 500a turns on a winning flag indicating that a minor winning combination has been won.

(Step S2700-17)
The main CPU 500a executes payout number setting processing for setting the number of payouts according to the winning minor combination.

(Step S2700-19)
The main CPU 500a determines whether it is an advantageous section. As a result, if it is determined that it is not an advantageous section, the process moves to step S2800, and if it is determined that it is an advantageous section, the process moves to step S2700-21.

(Step S2700-21)
The main CPU 500a acquires the value of the advantageous section MY counter that counts the net increase in the number of coins during the advantageous section.

(Step S2700-23)
The main CPU 500a adds the payout number to the value of the advantageous section MY counter acquired in step S2700-23.

(Step S2700-25)
The main CPU 500a acquires the number of inserted cards in the game.

(Step S2700-27)
The main CPU 500a subtracts the inserted number from the value added in step S2700-23.

(Step S2700-29)
The main CPU 500a determines whether the subtraction result in step S2700-27 is negative. As a result, if it is determined that the subtraction result is not negative, the process moves to step S2700-33, and if it is determined that the subtraction result is negative, the process moves to step S2700-31.

(Step S2700-31)
The main CPU 500a clears (sets to 0) the value of the advantageous section MY counter.

(Step S2700-33)
The main CPU 500a updates the value of the advantageous section MY counter to the value subtracted in step S2700-27 or the value cleared in step S2700-31.

(Step S2700-35)
The main CPU 500a determines whether or not the replay combination has won. As a result, when it is determined that the replay combination has not won, the process moves to step S2800, and when it is determined that the replay combination has won, the process moves to step S2700-37.

(Step S2700-37)
The main CPU 500a sets the inserted number as the payout number.

(Step S2700-39)
The main CPU 500a turns on the replay flag.

(Step S2700-41)
The main CPU 500a sets the number of sheets automatically inserted.

(Step S2800)
The main CPU 500a executes payout processing for paying out medals. This payout process will be described later.

FIG. 95 is a flow chart explaining the payout process (S2800) in the main control board 500. FIG.

(Step S2800-1)
The main CPU 500a acquires the replaying flag.

(Step S2800-3)
The main CPU 500a sets a payout start command indicating that the payout of medals has started in the transmission buffer.

(Step S2800-5)
The main CPU 500a determines whether or not the replay combination has won based on the replay operation flag acquired in step S2800-1. As a result, when it is determined that the replay combination has won, the process moves to step S2800-41, and when it is determined that the replay combination has not won, the process moves to step S2800-7.

(Step S2800-7)
The main CPU 500 a executes a main indicator display process for displaying 0 on the main payout display section 432 .

(Step S2800-9)
The main CPU 500a determines that there is no payout (the number of payouts is 0). As a result, when it is determined that there is no payout, the process moves to step S2800-35, and when it is determined that there is a payout, the process moves to step S2800-11.

(Step S2800-11)
The main CPU 500a determines whether the number of stored coins is 50 or more. As a result, if it is determined that the number of stored sheets is 50 or more, the process moves to step S2800-13, and if it is determined that the number of stored sheets is not 50 or more, the process moves to step S2800-15.

(Step S2800-13)
The main CPU 500a executes medal payout device control processing to pay out one medal from the medal payout device 442, and shifts the processing to step S2800-23.

(Step S2800-15)
The main CPU 500a sets a payout start interval timer.

(Step S2800-17)
The main CPU 500a determines whether the payout start timer is not 0, that is, whether it is the first payout. As a result, when it is determined that it is the time of the first payout, the process moves to step S2800-21, and when it is determined that it is not the time of the first payout, the process moves to step S2800-19.

(Step S2800-19)
The main CPU 500a executes timer wait processing for waiting until the payout start interval timer reaches zero.

(Step S2800-21)
The main CPU 500a increments the stored number by one.

(Step S2800-23)
The main CPU 500a sets a payout execution command indicating that one medal has been paid out in the transmission buffer.

(Step S2800-25)
The main CPU 500a executes main display pre-display processing for displaying the number of payouts that have already been paid out on the main payout display section 432. FIG.

(Step S2800-27)
The main CPU 500a determines whether it is in the bonus game state. As a result, when it is determined that the game is not in the bonus game state, the process moves to step S2800-31, and when it is determined to be in the bonus game state, the process moves to step S2800-29.

(Step S2800-29)
The main CPU 500a increments, by one, the number of medals paid out during bonus operation, which is the number of medals paid out in the bonus game state.

(Step S2800-31)
The main CPU 500a determines whether or not the payout of the number of medals to be paid out has been completed. As a result, if it is determined that the payout has not ended, the process moves to step S2800-11, and if it is determined that the payout has ended, the process moves to step S2800-33.

(Step S2800-33)
The main CPU 500a executes payout end processing for ending the payout of medals.

(Step S2800-35)
The main CPU 500a determines whether an over error has been detected. As a result, if it is determined that no over error has been detected, the process proceeds to step S2800-41, and if it is determined that an over error has been detected, the process proceeds to step S2800-37.

(Step S2800-37)
The main CPU 500a sets an error code "E5" indicating an over error.

(Step S2800-39)
The main CPU 500a performs error display, request for warning sound, and error wait processing for waiting for error recovery.

(Step S2800-41)
The main CPU 500a sets a payout end command indicating that the payout of medals has ended in the transmission buffer.

(Step S2900)
The main CPU 500a executes a game transition process for transitioning a game state, managing an advantageous interval, and the like. This game transition processing will be described later.

FIG. 96 is a flow chart for explaining game transition processing (S2900) in the main control board 500. FIG.

(Step S2900-1)
The main CPU 500a acquires a replay flag and turns on or off a bit corresponding to a replay indicator (not shown) indicating that the next game is a replay, based on the acquired replay flag. For this purpose, the stop indicator output bit off (output image) is set, and replay indicator control processing is executed to update the output bit of the set output image.

(Step S2900-3)
When a bonus combination is won, the main CPU 500a executes a role product actuation symbol display process for setting various parameters for controlling the bonus game state.

(Step S2900-5)
The main CPU 500a executes a bonus operation end process for shifting the game state to a non-internal game state when the number of coins obtained during bonus operation reaches a predetermined number in the bonus game state.

(Step S2900-7)
The main CPU 500a executes advantageous section update processing for managing advantageous sections.

(Step S2900-9)
The main CPU 500a determines whether or not the next game is in the AT effect state. As a result, when it is determined that the next game is not in the AT effect state, the process is shifted to step S2900-15, and when it is determined that the next game is in the AT effect state, the process is shifted to step S2900-11.

(Step S2900-11)
The main CPU 500a determines whether it is in the bonus game state. As a result, when it is determined that it is not in the bonus game state, the process moves to step S2900-15, and when it is determined that it is in the bonus game state, the process moves to step S2900-13.

(Step S2900-13)
The main CPU 500a sets on an advantageous lamp flag for lighting the section indicator 460. FIG.

(Step S2900-15)
The main CPU 500a executes an effect command setting process for setting an effect command, which is a command relating to the advantageous section, in the transmission buffer.

(Step S2900-17)
The main CPU 500a sets a game end command indicating that one game has ended in the transmission buffer.

(Step S2900-19)
The main CPU 500a executes terminal board signal output processing for outputting an external signal.

(Step S2900-21)
The main CPU 500a determines whether or not the effect wait timer that is set when ending the advantageous section in step S2900-7 is not 0. As a result, when it is determined that the effect wait timer is not 0, the process moves to step S2900-21, and when it is determined that the effect wait timer is 0, the process moves to step S2900-23.

(Step S2900-23)
The main CPU 500a sets a game state command indicating a game state in the transmission buffer.

(Step S2900-25)
The main CPU 500a sets a game start command indicating the start of the next game in the transmission buffer, and shifts the process to step S2100.

One game is executed through a series of processes from step S2100 to step S2900. Thereafter, steps S2100 to S2900 are repeated.

Next, save processing and timer interrupt processing in the main control board 500 will be described.

(Evacuation processing when main control board 500 is powered off)
FIG. 97 is a flow chart for explaining the saving process at power-off in the main control board 500. FIG. The main CPU 500a monitors the power-off detection circuit, and when the power supply voltage drops below a predetermined value, it interrupts and executes the power-off saving process.

(Step S3000-1)
When the power-off warning signal is input, the main CPU 500a saves the register.

(Step S3000-3)
The main CPU 500a checks the power-off warning signal.

(Step S3000-5)
The main CPU 500a determines whether a power-off warning signal is detected. As a result, if it is determined that the power cut warning signal has been detected, the process moves to step S3000-11, and if it is determined that the power cut warning signal has not been detected, the process moves to step S3000-7. .

(Step S3000-7)
The main CPU 500a restores the register.

(Step S3000-9)
The main CPU 500a performs a process for permitting an interrupt, and terminates the power-off saving process.

(Step S3000-11)
The main CPU 500a executes output port clear processing to stop output from the output port.

(Step S3000-13)
The main CPU 500a executes save processing for the separate area when the power is turned off.

(Step S3000-15)
The main CPU 500a executes RAM protection setting processing necessary to prohibit access to the main RAM 300c.

(Step S3000-17)
The main CPU 500a sets the counter value of the loop counter to the predetermined number of power failure detection signal detections in order to set the power failure occurrence monitoring time.

(Step S3000-19)
The main CPU 500a subtracts 1 from the value of the loop counter set in step S3000-17.

(Step S3000-21)
The main CPU 500a determines whether or not the counter value of the loop counter is zero. As a result, if it is determined that the counter value is not 0, the process proceeds to step S3000-19, and if it is determined that the counter value is 0, the above-described CPU initialization process (step S1000) is performed.

It should be noted that if the power is actually turned off, the operation of the slot machine 400 is stopped during the loop of steps S3000-19 to S3000-21.

(Timer interrupt processing of main control board 500)
FIG. 98 is a flowchart for explaining timer interrupt processing in the main control board 500. FIG. The main control board 500 is provided with a reset clock pulse generating circuit that generates a clock pulse every predetermined period (1.49 milliseconds in the simultaneous rotation reference example, hereinafter referred to as "1.49 ms"). Then, when a clock pulse is generated by the reset clock pulse generation circuit, it interrupts and the following timer interrupt processing is executed.

(Step S3100-1)
The main CPU 500a saves the register.

(Step S3100-3)
The main CPU 500a clears the interrupt flag.

(Step S3100-5)
The main CPU 500a reads various input port images and executes port input processing for accurately acquiring the latest switch states.

(Step S3100-7)
The main CPU 500a outputs the set output image to the output port, the main credit display section 430, the main payout display section 432, the input number display, the start display, the display of the stop switches 420a, 420b, and 420c, and the replay display. dynamic port output processing for controlling the lighting of the section indicator 460.

(Step S3100-9)
The main CPU 500a updates the timer interrupt phase. The timer interrupt phase is one of 0 to 3. Here, when the timer interrupt phase is 0, 1, or 2, 1 is added, and when the timer interrupt phase is 3, it is set to 0. Be changed.

(Step S3100-11)
The main CPU 500 a performs sub-command transmission processing for transmitting the command stored in the transmission buffer to the sub-control board 502 .

(Step S3100-13)
The main CPU 500 a executes stepping motor control processing for controlling the stepping motor 452 .

(Step S3100-15)
The main CPU 500 a executes output port image output processing for outputting an output image to be output to the medal payout device 442 .

(Step S3100-17)
The main CPU 500a executes random number update processing for updating various random numbers.

(Step S3100-19)
The main CPU 500a executes fraud monitoring processing for detecting errors in order to output external signals (external signals 4 and 5) corresponding to errors to the outside.

(Step S3100-21)
The main CPU 500a executes a module (subroutine) corresponding to the timer interrupt processing phase updated in step S3100-9. Here, the timer interrupt processing phase is set to one of 0 to 3, and one module corresponding to each of the timer interrupt processing phases 0 to 3 is provided (four in total). One module will be executed once every four timer interrupt processing (every 5.96ms). For example, a module that executes time monitoring processing for subtracting various timers is associated with one timer interrupt processing phase.

(Step S3100-23)
The main CPU 500a executes test signal output processing for outputting the test signal to the outside.

(Step S3100-25)
The main CPU 500a reads various input port images and executes port input processing for accurately acquiring the latest switch states.

(Step S3100-27)
The main CPU 500a restores the register.

(Step S3100-29)
The main CPU 300a permits the interrupt and terminates the timer interrupt process.

Further, in the above-described embodiment, the main control board 500 and the sub control board 502 are arranged so as to share the functional part for progressing the game. Alternatively, the functional units of the sub control substrate 502 may be arranged on the main control substrate 500, or all the functional units may be collectively arranged on one control substrate.

In addition, in the above-described embodiment, only one type of AT effect state is provided. good too.

Further, in the above-described embodiment, the game is played using medals as game value, but the game value may be electrical information (so-called medalless). In this case, when the winning combination wins, the amount of value corresponding to the winning combination may be given to the player as electrical information.

Further, each process performed by the main control board 500 and the sub control board 502 described above does not necessarily have to be processed in time series according to the order described as the flowchart, and may include parallel or subroutine processing.

Further, each process performed by the main control board 500 and the sub control board 502 described above does not necessarily have to be processed in time series according to the order described as the flowchart, and may include parallel or subroutine processing.

<Configuration around the CPU of the main control board>
FIG. 99 is a diagram for explaining electrical connections around the main CPU 300a. The main CPU 300 a includes a CPU core 700 and a bus controller 702 . The CPU core 700 controls the bus controller 702 through a bus control signal (Bus Cont) output from the BC terminal, reads data from the main ROM 300b, the main RAM 300c, or the input/output unit 704, or reads data from the main RAM 300c or the input/output unit 704. Data is written to the portion 704 . Here, as the main CPU 300a, a microprocessor based on the Z80 series CPU sold by LETech is used. Although the main CPU 300a, main ROM 300b, and main RAM 300c of the pachinko machine will be described here, it goes without saying that they can be replaced with the main CPU 500a, main ROM 500b, and main RAM 500c of the slot machine 400.

For example, when reading data from the main ROM 300b, the main RAM 300c, or the input/output unit 704, the bus controller 702 outputs a 16-bit address (A[16]) signal and outputs the main ROM 300b, Either the main RAM 300c or the input/output unit 704 is specified, and the read (RD) signal is controlled to read the data (D[8]) signal from the main ROM 300b, the main RAM 300c, or the input/output unit 704. . When data is written to the main RAM 300c or the input/output unit 704, the bus controller 702 outputs an address (A[16]) signal and a data (D[8]) signal to the main RAM 300c through decoders 706b and 706c. , or specifies one of the input/output units 704 and controls the write (WR) signal to write the data (D[8]) signal to the main RAM 300 c or the input/output unit 704 .

Here, as will be described later, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 300b and the main RAM 300c. Therefore, conventionally, a memory request (MREQ) terminal and an I/O request (IORQ) terminal for outputting a signal for specifying whether to access memory or I/O are not provided. By reassigning these two terminals to arbitrary other signals, the degree of freedom in program development can be increased.

The CPU core 700 also includes an interrupt/wait (INT/WAIT) signal that triggers the start of interrupt processing, a non-maskable interrupt (NMI) signal that allows interrupt processing to be executed with the highest priority, and bus signals that are set to high impedance. An external signal such as a transitionable bus request (BUSREQ) signal is also input.

FIG. 100 is a block diagram showing the internal configuration of the CPU core 700. As shown in FIG. CPU core 700 includes external input unit 710 , state control unit 712 , central control unit 714 , register unit 716 and arithmetic logic unit (ALU) 718 . The external input unit 710 receives external signals and outputs control information based on the external signals to the state control unit 712 and the central control unit 714 .

State control unit 712 manages and transitions internal states (RESET, instruction fetch, instruction decode, operation, memory load, memory store, HALT, etc.) based on input control information to change the operating state of CPU core 700. It determines and outputs control information to the central control unit 714 based on its operating state.

Central control unit 714 extracts an operation code (instruction) from input data (DI[8]) input via bus controller 702 and controls ALU 718 based on the command decoded by the instruction decoder. Also, the central control unit 714 acquires necessary information from each register of the register unit 716 and updates each register according to the decoded command.

Register unit 716 includes selector ports 722 a , 722 b , 722 c , input bank selector 724 , first register bank 726 , second register bank 728 , output bank selector 730 , address port 732 and individual registers 734 . The individual register 734 includes a 16-bit program counter (PC) that indicates the address of the next program to be executed, an 8-bit interrupt (I) register that is used in interrupt mode, and an 8-bit counter that counts opcode fetch cycles. It includes a bit refresh (R) register and an 8-bit interrupt enable (IFF) register that controls interrupt enable/disable.

In addition, the register unit 716 has a random number generator for obtaining various random numbers (jackpot determination random number, winning pattern random number, reach group determination random number, reach mode determination random number, variation pattern random number, winning determination random number) related to the big win lottery. A device (not shown) is associated with the input port (FE73h-FE9Ch) to obtain the latched random value.

The random number generator operates with a system clock (a clock obtained by dividing an external input by two) and generates random numbers less than a predetermined maximum value. The random number generator is a random number generator capable of setting the maximum value of random numbers. A configurable random number generator is provided with eight channels. Here, the 16-bit maximum value setting random number generator can select the random number update period within the range of 32 to 47 clocks, and the maximum value setting range can be set within the range of 256 to 65,535. In addition, the 8-bit maximum value setting random number generator can select the random number update period in the range of 16 to 31 clocks, and the maximum value setting range can be set in the range of 16 to 255 for 4 channels. It can be set in the range of 64-255. In addition, as a random number generator with a fixed maximum value of random numbers, a random number generator capable of setting a maximum value of 16 bits has four channels and a random number generator capable of setting a maximum value of 8 bits. The instrument is prepared for 8 channels. Here, the 16-bit fixed maximum value random number generator has a fixed random number update cycle of 1 clock and a maximum value of 65,535. The 8-bit fixed maximum value random number generator has a fixed random number update cycle of 1 clock and a maximum value of 255.

If the number of types of random numbers is insufficient, the random number obtained from the hardware random number generator (random number generator) is multiplied by a predetermined number in the program, or divided to generate another random number (software random number generator).

FIG. 101 is a diagram explaining the structure of a register. The register unit 716 is provided with a first register bank (bank 0) 726 and a second register bank (bank 1) 728 paired with the first register bank 726 . The first register bank 726 is provided with a main register group (front register group) 726a and a sub-register group (back register group) 726b paired with the main register group 726a. A main register group 728a and a sub-register group 728b paired with the main register group 728a are provided. The main register group 726a and sub-register group 726b of the first register bank 726 and the main register group 728a and sub-register group 728b of the second register bank 728 are both 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY). However, unlike the sub-register groups 726b and 728b, the main register groups 726a and 728a further include an 8-bit register (U) and a 16-bit register (SP). The main CPUs 300a and 500a switch between the first register bank 726 and the second register bank 728 and can access only one of the register banks indicated by the register bank designation register RB in the F register, which will be described later. cannot be accessed at the same time.

Among the registers shown in FIG. 101, Q registers are 8-bit registers that are provided in two sets in each register bank as extended registers and store the high-order bytes of addresses used in some commands. If, for example, F0h is set as the value of the Q register, the main CPU 300a, 500a can use the Q register to access F000h to F0FFh of the main RAM 300c. The U register is an 8-bit register that is provided in each register bank as an extension register and stores the upper byte of the address used in some commands. For example, when FEh is set as the value of the U register, the main CPUs 300a and 500a include built-in devices (timers, random number generators, external input/output circuits, etc.) connected to the input/output units 704 of FE00h to FFFFh. A U register can be used to access the . The A register is a general-purpose register that also functions as an 8-bit accumulator used for arithmetic processing and data transfer. The F register is an 8-bit flag register that holds various calculation results. Here, as shown in FIG. 101, each bit of the F register, from the most significant bit (MSB: Most Significant Bit) to the least significant bit (LSB: Least Significant Bit), S is 1 when the operation result is negative. , Z is a zero flag (first zero flag) that is set to 1 when all bits are 0 as a result of the operation, and TZ is a data transfer instruction (LD; load) executed by , is a specific bit flag (second zero flag) of extended specifications for gaming machines, which is set to 1 (value changes) when all bits are 0, and is sometimes called a teeze flag. H is a half-carry flag that cannot be touched by the programmer, and RB (register bank designation register) is a register bank monitor that indicates the current register bank (first register bank 726=0, second register bank 728=1). , P/V is a parity overflow flag, N is an addition/subtraction flag that cannot be touched by the programmer, and C is a carry flag that is set to 1 when a carry or borrow occurs as a result of an operation. The F register constitutes the A register and the pair register AF.

The B register, C register, D register, E register, H register, and L register are two sets of 8-bit general-purpose registers provided in each register bank, each of which is a predetermined combination of 16-bit pairs. Registers (eg, registers BC, DE, HL, and multiple combinations exist) are configured and utilized. The IX and IY registers are 16-bit general-purpose registers used for index addressing. The SP (stack pointer) register is 16 bits and stores an address that serves as a stack pointer. Q' register, A' register, F' register, B' register, C' register, D' register, E' register, H' register, L' register, IX' register, IY' register are Q register, A register , F register, B register, C register, D register, E register, H register, L register, IX register, and IY register. Possible sub-register groups 726b, 728b, where the A' and F' registers form a pair register AF', the B' and C' registers form a pair register BC', and the D' and E' registers. constitute a pair register DE', and the H' register and L' register constitute a pair register HL'. Note that the pair registers are not limited to BC', DE', and HL', and there are other combinations. On the other hand, one set of U register and SP register is provided for each register bank.

By the way, as described above, in the main control boards 300 and 500, the main CPU 300a controls the progress of the game in cooperation with the main RAM 300c based on the programs stored in the main ROM 300b. Programs for executing these functional units are arranged in predetermined areas (used areas) of the main ROM 300b and the main RAM 300c.

FIG. 102 is an explanatory diagram showing a memory map. Since the memory map of the pachinko machine has already been described with reference to FIG. 5, the memory map of the slot machine 400 will be described here. The main ROM 500b is allocated a memory space of 0000h to 3FFFh (12 kbytes), the main RAM 500c is allocated a memory space of F000h to F3FFh (1 kbyte), and the input/output unit 704 is allocated FE00h to FFFFh (512 bytes). Allocated memory space. The instruction code of the program is written in assembler language. Here, the program is composed of instruction codes, is read by a computer, and can realize predetermined processing in cooperation with data and a work area.

A memory space from 0000h to 1DF3h of the main ROM 500b is assigned a usable area. The use area is an area for storing programs and data for executing game control processing for controlling the progress of the game. Specifically, initialization means 600, betting means 602, winning type lottery means 604, reel control means 606, determination means 608, payout control The instruction code of the program for executing the game control process for controlling the progress of the game by making the means 610, the game state control means 612, the effect state control means 614, and the command transmission means 616 function is stored, and 1200h to 1DF3h (3 0 kbytes), data used for the game control processing program is stored in the memory space (data area). A comment area is allocated to the memory space of 1E00h to 1FFFh, and a program management area is allocated to the memory space of 3FC0h to 3FFFh. Another area (unused area) is allocated to the memory space from 2000h to 3FBFh. The separate area is an area for storing programs and data that are not specified to be stored in the use area, as will be described later. Specifically, in the memory space from 2000h to 3FBFh, some or all of the game machine test processing and security-related processing that do not affect the progress of the game (hereinafter simply referred to as non-game control processing) is stored) and the instruction code and program data of the program that executes the Here, the gaming machine test processing is the testing processing of the slot machine 400 described in the connection specifications (4th edition) of the reel-type gaming machine testing machine. The security-related processing is processing to identify an abnormal state for the purpose of preventing fraud by a third party and finding defects, and includes, for example, determination of the above-described backup flag and execution of checksum. Note that there is no limitation on the storage capacity of the separate area, and in the example of FIG. 102, it can be freely allocated to storage areas other than the use area, comment area, and program management area.

As described above, the main CPU 500a may perform not only the game control process, but also the game machine test process and the security-related process (non-game control process). However, the storage capacity of the used area is predetermined. For example, as shown in FIG. 102, the control area is limited to 4.5 kbytes and the data area is limited to 3.0 kbytes. Therefore, if not only the game control process but also the game machine test process and the security-related process programs and data are allocated to the use area, the storage area for performing the game control process is limited accordingly. Here, the program (program used) and data for executing the game control process must be stored in the use area, but the process outside the game control (game control process) that does not affect the progress of the game other than the game control process A program (another program) and data for executing machine test processing, security-related processing, etc. can be stored in both the use area and the separate area. Therefore, at least part of the programs and data for executing backup flag judgment processing and checksum execution processing, which are processing corresponding to security-related processing, are stored in a storage area different from the used area (other than the used area). It is described in another area that is a part of it.

If the processing (here, game control processing) performed in the use area and the processing (here, security-related processing) that does not necessarily have to be performed in the use area are mixed, the game control processing The program (used program) and data for executing the is stored in the used area, and the processing outside the game control (security related processing) that does not affect the progress of the game other than the game control processing that does not need to be performed in the used area It is desirable to store a program (another program) and data to be executed in a separate area. By partitioning the storage area into a plurality of areas in this way, there is a margin in the storage area (capacity) of the used area corresponding to the amount of the program moved to another area. Therefore, it is possible to allocate the use area to the game control process (use program) accordingly.

However, the fairness of the gaming machine must be ensured even when the storage area is divided into the use area and the other area as described above. Therefore, the following conditions (1) to (6) are stipulated in order to properly divide roles between the usage area and the other area while ensuring the fairness of the gaming machine.

Condition (1): Programs placed in a separate area are used for the purpose of outputting signals necessary for gaming machine testing (game machine testing processing) and fraud prevention (security-related processing), and are used to impair the fairness of gaming. It must not be damaged (damaged). Condition (2): The control area and data area, which are separate from the used area, must be placed in clearly separated areas. Condition (3): The program to be placed in the separate area (separate program) must be statically called from the program in the used area (used program) and then executed. Also, in the program list at that time, the call destination address must be clearly described. Condition (4): Programs placed in separate areas should be modularized for each function, and when called, the contents of all registers used in the used area should be protected. Condition (5): Access to RAMs in each other's area from the used area or another area is permitted only for reference, and update is prohibited. Condition (6): It is not possible to call a subroutine in the control area of the used area from the control area of another area. Since a subroutine for performing interrupt processing is provided in the used area, it is necessary to disable interrupts when using a control area in another area. It should be noted that, in order to properly perform the game control process, the time from performing interrupt prohibition to releasing the interrupt prohibition must be within the interval of the interrupt process in the game control process (for example, 1.49 msec). must. Therefore, when calling a subroutine that uses the control area of another area, the total time required for one call is set to be within the interval of the interrupt process of the game control process.

In addition, the memory space of F000h to F1FFh of the main RAM 500c is allocated with a use area. Specifically, the memory space of F000h to F13Fh is assigned a work area for the game control process, and is used for variable management such as timers, counters, and flags. A stack area for the game control process is assigned to the memory space of F1C0h to F1FFh. Another area is allocated to the memory space of F200h to F3FFh of the main RAM 500c. More specifically, the memory spaces F210h to F22Fh are allocated work areas for some or all of the security-related processes, and are used for managing variables such as timers, counters, and flags. A stack area for part or all of the security-related processing is allocated to the memory spaces F230h to F246h.

An input/output unit 704 is assigned to the memory space from FE00h to FFFFh. Conventionally, an I/O space of 512 bytes was provided independently of the memory space in order to access the device corresponding to the input/output unit 704 . On the other hand, in this embodiment, the MREQ and IORQ signals are eliminated, and access to the memory and the input/output unit 704 is made common and performed by the RD and WR signals. A U register is provided as hardware for designating the upper 8-bit address for accessing the device connected to the input/output unit 704, and the 8-bit upper address is designated in advance. As a result, the I/O space provided independently of the memory space is integrated into the memory space to form one address space, and when the IN instruction and the OUT instruction are executed, the input/output unit 704 is assigned to the memory space. On the other hand, the upper 8 bits are specified by the U register, and the lower 8 bits can be accessed using the lower 8 bits specified by the operands of the IN and OUT instructions.

In this embodiment, the LDQ instruction uses the value of the Q register to access the memory space (mainly the data area and work area), and the IN and OUT instructions use the U register to access the device (timer, random number generator, external It becomes possible to describe a program so as to access the I/O of an input/output circuit, etc.). Such a configuration makes it easier to grasp the program at the time of design. In addition, memory and I/O that have been accessed by specifying them with 16-bit addresses can now be accessed with lower 8-bit operands, and the program capacity can be compressed. Furthermore, by having a plurality of high-order designated registers such as the Q register, Q' register, and U register, the number of exchanges due to reuse of the high-order register is reduced compared to when there is only one high-order register, and the program capacity is further compressed. be able to.

Although the memory space corresponding to the I/O space is accessed by the IN instruction and the OUT instruction in the above example, the memory space may be directly accessed by the IN instruction and the OUT instruction. For example, when accessing three 256-byte areas on the memory, the upper 8 bits are specified in the Q register, Q' register, and U register, respectively, and the LDQ instruction, IN instruction, and OUT instruction respectively This can be achieved by accessing the area of

(Display of game information)
By the way, in a gaming machine, for example, the slot machine 400, if the frequency of transition to the bonus game state or the AT effect state as described above is uneven, there is a concern that the projectileness will be excessively increased. Therefore, in order to comprehensively and uniformly determine whether or not the game state with high medal acquisition performance is biased, the advantageous section ratio, the instructed accessory ratio, the continuous accessory ratio, the accessory ratio, the accessory, etc. Establish judgment criteria such as condition ratio. The advantageous section ratio is the number of games staying in the advantageous section since the first start, divided by the total number of games, which is the total number of games, and is expressed as a percentage. The product ratio is the number of instructed accessory payouts, which is the number of medals paid out by the payout control means 610 based on the operation of the accessory and the operation of the instruction function, such as a bonus game, in a predetermined reference aggregation period from the time of the first startup. , the total number of medals paid out by the payout control means 610 is divided by the total number of payouts, and the value is expressed in %. , the number of continuous bonuses paid out, which is the number of medals paid out by the payout control means 610 by the operation of the type 1 special bonus, is divided by the total number of payouts, which is the total number of medals paid out by the payout control means 610, and is expressed as a percentage. The role ratio is the number of medals paid out by the payout control means 610 based on the operation of the role, such as a bonus game, during a predetermined reference tally period from the time of initial activation. is divided by the total number of payouts, which is the total number of medals paid out by the payout control means 610, and is expressed in %. Etc., the value obtained by dividing the number of active games, which is the number of games in which the accessory is activated, by the total number of games, which is the total number of games, and is expressed as a percentage. Note that the advantageous section ratio, the instructed accessory ratio, the continuous accessory ratio, the accessory ratio, and the accessory state ratio are not cleared by changing the settings.

Such display of the advantageous section ratio, the instructed accessory ratio, the continuous accessory ratio, the accessory ratio, and the accessory state ratio is performed by the dynamic port output processing (SYNMOUT module) of the timer interrupt processing S3100 shown in FIG. It is executed in the used area corresponding role ratio display acquisition process (E_SDPST module) in S3100-7.

Here, the advantageous section refers to a section in which the player stays in all of the non-AT production states excluding some production states (here, the non-advantageous production state). Note that the non-advantageous effect state may be referred to as a non-advantageous section as opposed to the advantageous section. However, the advantageous section is not limited to the AT effect state or the non-AT effect state, and may be arbitrarily set to any of the game state and the effect state in which the game progresses advantageously for the player.

Also, the accessory is a device for facilitating winning, and corresponds to a regular bonus (RB), a challenge bonus (CB), a single bonus (SB), and the like. In addition, among such accessories, the regular bonus (RB) corresponds to the first class special accessory. In addition, the regular big bonus (RBB) is a type 1 special accessory, which is a regular bonus (RB) that operates continuously regardless of the display of the symbol combination indicating the winning form of the regular bonus (RB). The Challenge Big Bonus (CBB) is a series of Challenge Bonuses (CB) regardless of the display of the symbol combination indicating the winning form of the Challenge Bonus (CB), which is a type 2 special accessory (one of the accessories). It works with Therefore, the continuous accessory ratio represents the ratio of the number of continuous accessory payouts paid out by the operation of the type 1 special accessory to the total number of payouts paid out in a predetermined reference aggregation period. represents the ratio of the number of bonus items paid out by the operation of the bonus to the total number of bonuses paid out during a predetermined reference aggregation period.

The reference tallying period is a target period for accumulating the number of medals paid out by the payout control means 610 . In this embodiment, for example, 6000 games, which is a finite value, and the entire period after installation of the slot machine 400 in the game hall (hall) (hereinafter referred to as "total cumulative total") are given. Therefore, as the continuous accessory ratio, the continuous accessory ratio of 6000 games and the continuous accessory ratio of the total cumulative total are derived. and However, it goes without saying that an arbitrary number of games can be set as the reference tallying period.

In order to obtain the advantageous section ratio, the instructed role ratio, the continuous role ratio, the role ratio, and the state ratio of the role, etc., the accumulating means (not shown) calculates the total number of games, the number of staying games, the operating The number of games, the total number of payouts, the number of instructed accessory payouts, the number of continuous accessory payouts, and the number of accessory payouts are accumulated. At this time, a counter is associated with each of the total number of games, the number of staying games, the number of active games, the total number of payouts, the number of instructed role payouts, the number of continuous role payouts, and the number of role payouts. Specifically, when one game is started, the accumulating means increments a total number-of-games counter indicating the total number of games by one. Then, it is determined whether or not the current game is a game in the advantageous section, and if it is a game in the advantageous section, the staying game number counter indicating the number of staying games is incremented by one. It should be noted that updating of the number-of-stayed-games counter is started from the next game of the game that wins the advantageous section in the case of the non-advantageous section (the game that has undergone the transition processing to the advantageous section). However, if you win an advantageous section based on winning a regular big bonus (RBB) or a challenge big bonus (CBB), the next game after the game in which the bonus was won (a game that has been processed to transition to the advantageous section) is started from Also, it is determined whether or not the current game is a game in which the role product is activated, and if it is a game in which the role product is activated, the activated game number counter indicating the number of activated games is incremented by one.

Further, when medals are paid out in the game, the accumulating means increments a total payout number counter indicating the total number of payouts by the number of payouts. Then, if the payout of the medals is based on the operation of the role and the operation of the instruction function, the instructed role payout number counter indicating the number of the instructed role payouts is incremented by the number of payouts, and the medals are paid out. is based on an accessory, the accessory payout number counter indicating the number of accessory payouts is incremented by the number of payouts; A continuous accessory payout number counter indicating the number of accessory payouts is incremented by the number of payouts.

It should be noted that the total cumulative total can be counted only by such a counter, but with regard to the continuous accessory ratio and the accessory ratio, not only the total cumulative total but also the standard aggregation period, here, a limited period such as 6000 games, must be covered. must. Therefore, the 6000 games are evenly divided into, for example, 400 games, and a plurality of (for example, 15) counters for counting 400 games are provided and used as a ring buffer. Here, an example is given in which 6000 games are divided into 400 games and counted, but it goes without saying that the number of divided games can be arbitrarily set as long as it is a factor (divisor) of 6000.

Specifically, when medals are paid out in the game, the accumulating means performs processing for updating the total payout counter, the continuous accessory payout counter, and the accessory payout counter up to 400 games, and when the 400 games are reached, The total number of payouts, the number of continuous award payouts, and the number of award payouts are derived by summing up the 14 counters counted in the past. Then, of the 14 counters, the counter counted in the oldest game is initialized, and the initialized counter newly sets the total payout number counter, the continuous accessory payout number counter, and the accessory payout number counter for 400 games. Update. In this way, it is possible to refer to game information for new 400 games and game information for past 5600 games every 400 games. It becomes possible to derive the number of items to be paid out. It should be noted that the counting by such a counter is always executed regardless of the specified number or set value. In this way, the total number of games played, the number of staying games, the number of active games, the total number of payouts, the number of instructed role payouts, the number of continuous role payouts, and the number of role payouts are accumulated.

Subsequently, the ratio derivation means (not shown) calculates the total number of games accumulated by the accumulating means, the number of staying games, the number of active games, the total number of payouts, the number of instructed role payouts, the number of consecutive role payouts, and the number of payouts. Based on the number of payouts, the advantageous section ratio, the instructed accessory ratio, the continuous accessory ratio, the accessory ratio, and the accessory state ratio are derived. Specifically, the ratio derivation means divides the number of staying games by the total number of games, converts it into a percentage, derives the advantageous section ratio, and divides the total number of instructed accessory payouts by the total total number of payouts. , convert to % to derive the total cumulative instructed role ratio, divide the total cumulative total number of consecutive bonuses paid out by the total cumulative total number of payouts, and convert to % to derive the total cumulative continuous bonus ratio , Divide the total cumulative number of payouts by the total number of payouts, convert to % to derive the total cumulative role ratio, divide the number of activated games by the total number of games, convert to %, and convert Derive the equistate ratio. In addition, the ratio deriving means divides the number of continuous role payouts for 6000 games by the total number of payouts for 6000 games, converts it into a percentage, and derives the continuous role ratio for 6000 games. The number of payouts is divided by the total number of payouts for 6000 games, and converted into a percentage to derive the accessory ratio for 6000 games.

Next, the ratio display means (not shown) displays the advantageous section ratio derived by the ratio deriving means, the instructed role ratio, the continuous role ratio of 6000 games, the role of 6000 games, and The ratio, total cumulative continuous accessory ratio, total cumulative accessory ratio, and accessory state ratio are displayed on the ratio display section 860 .

FIG. 103 is an explanatory diagram showing the appearance of the main control board 500. As shown in FIG. As shown in FIG. 103( a ), a plurality of connectors 870 are provided on the end side of the main control board 500 , and a ratio display section 860 is provided near the center of the main control board 500 . The ratio display portion 860 is configured by juxtaposing four 7-segments each composed of 7-segments capable of representing decimal Arabic numerals and a dot segment (DP) positioned to the lower right of the 7-segments. When the main control board 500 is incorporated into the slot machine 400, the main control board 500 is accommodated in the board case 872, and the main control board 500 is mounted on the front portion 872a of the board case 872, as shown in FIG. 103(b). It is fixed with screws 874 from the back. A transmissive window 872b through which the ratio display portion 860 is visible is provided at a position corresponding to the ratio display portion 860 in the front portion 872a of the substrate case 872 . Therefore, as shown in FIG. 74, the administrator can visually recognize the display contents of the ratio display section 860 through the transmissive window 872b with the front upper door 404 open. Instead of the transmission window 872b, the substrate case 872 as a whole may be made of a transmissive or semi-transmissive material.

Here, with only the four 7 segments that constitute the ratio display section 860, the advantageous section ratio, the continuous accessory ratio of 6000 games, the accessory ratio of 6000 games, the total cumulative continuous accessory ratio, and the total cumulative accessory ratio In order to display the five pieces of game information, each ratio is associated with an identifier, and the ratio display section 860 sequentially displays the identifier and each ratio. Each ratio is shown in the range of 0-99. Therefore, of the four 7-segments, the two 7-segments located on the left indicate the identifier, and the two 7-segments located on the right indicate the ratio.

FIG. 104 is an explanatory diagram for explaining the display mode of the ratio display section 860. As shown in FIG. When the power switch 444 is turned on, as shown in FIG. 104(a), the ratio display means displays the identifier "7U" corresponding to the advantageous section ratio and its ratio, for example "70"%, at once. (so-called 7U type). Further, depending on the slot machine 100, it is also possible to display the instructed accessory ratio instead of the advantageous section ratio. In this case, the ratio display means displays the identifier "7P" corresponding to the instructed accessory ratio and its ratio, for example, "70"% at once (so-called 7P type). Here, in the 7U type, it is possible to perform a lottery to shift to an advantageous section by referring to the winning type with a set difference, but it is not possible to perform a lottery to shift to an advantageous section by directly referring to the set value. . On the other hand, in the 7P type, it is possible to perform a lottery to move to an advantageous section by referring to both the winning type with a set difference and the set value. The ratio display means separates the identifier from the ratio by lighting the second 7-segment dot segment of the ratio display section 860 .

In this state, when a predetermined time (for example, 5.0 sec) has passed, the ratio display means displays "6Y", which is the identifier corresponding to the continuous role ratio of 6000 games, and the ratio as shown in FIG. Display some "60"% at a time. Then, every time a predetermined time elapses, the combination of the identifier "7Y" corresponding to the role product ratio of 6000 games and the ratio "70"% as shown in FIG. As shown in (d), the combination of the identifier "6A" corresponding to the total cumulative continuous role product ratio and its ratio "60"%, as shown in FIG. A combination of "7A", which is an identifier corresponding to the object ratio, and "70"%, which is the ratio thereof, and "5H", which is an identifier corresponding to the state ratio of the character, etc., as shown in FIG. 104(f), Combinations with the ratio "50"% are displayed sequentially. Further, as shown in FIG. 104(f), in a state in which a combination of "5H", which is an identifier corresponding to the state ratio of the role product, and "50"%, which is the ratio thereof, is displayed, When the time elapses, the identifier "7U" corresponding to the advantageous section ratio and the ratio "70"% shown in FIG. 104(a) are displayed again. Displayed in the order of advantageous section ratio (indicated accessory ratio), continuous accessory ratio of 6000 games, accessory ratio of 6000 games, continuous accessory ratio of total cumulative total, accessory ratio of total cumulative, condition ratio of accessory etc. is switched.

Here, an example in which the identifier and the ratio are simultaneously displayed using four 7-segments has been described. In this case, the ratio display section 860 displays, for example, "7U"→"70"→"6Y"→"60"→"7Y"→"70"→"6A" each time a predetermined time elapses. ”→“60”→“7A”→“70”→“5H”→“50”.

Note that the ratio display means displays the identifier and the ratio on four existing display units (main credit display unit 430 and main payout display unit 432) corresponding to the four 7 segments instead of the ratio display unit 860 of the main control board 500. It can also be displayed by switching. In this case, after the result of one game is notified, before the start of the next game, the front upper door 404 is opened, and in that state, an existing switch, for example, an operation to set or change the set value is executed. By operating the switch, the identifier corresponding to the advantageous section ratio and its ratio are displayed, and after that, every time a predetermined time passes, the advantageous section ratio (instruction role ratio) → continuous role ratio of 6000 games →6000 game role item ratio→total cumulative continuous accessory ratio→total cumulative accessory ratio→instructed accessory ratio. In addition, the ratio display means can display the advantageous section ratio (instruction role ratio), the continuous role ratio of 6000 games, the role ratio of 6000 games, the total cumulative continuous role ratio, and the total cumulative role ratio. Even while the item ratio and the condition ratio of the accessory etc. are being displayed, if there is a change in the state of the slot machine 400 such as insertion of medals, the display is deleted.

Through such a ratio display unit 860 or the existing display unit, the administrator can display the advantageous section ratio, the instructed role ratio, the continuous role ratio of 6000 games, the role ratio of 6000 games, the total continuous role ratio , the total cumulative accessory ratio, and the accessory state ratio can be visually recognized. Then, it is possible to determine whether or not the game information is within an appropriate range, and to determine whether the slot machine 400 is operating properly.

Such an appropriate range is, for example, the advantageous section ratio <70%, the instructed accessory ratio <70%, the continuous accessory ratio of 6000 games <60%, the accessory ratio of 6000 games <70%, the total cumulative continuous It is set as follows: the accessory ratio <60%, the total cumulative accessory ratio <70%, and the accessory state ratio <50%. If the appropriate range is exceeded, the ratio display means may cause each segment of the ratio display section 860 to blink, for example, at intervals of 0.6 sec for the target ratio. Such a blinking display enables the administrator to quickly grasp the identifiers deviating from the appropriate range and the ratio thereof.

By the way, as described above, the ratio deriving means divides the number of staying games by the total number of games to derive the advantageous section ratio, and divides the total number of instructed accessory payouts by the total total number of payouts. Deriving the total cumulative number of instructed bonus payouts, dividing the total cumulative continuous bonus payout number by the total cumulative total payout number to derive the total cumulative continuous bonus payout number, and the total cumulative bonus payout number The number is divided by the total total number of payouts to derive the total cumulative payout number of accessories, and the number of active games is divided by the total number of games to derive the condition ratio of the accessory. However, the main CPU 500a in the main control board 500 has a low processing capability, and the multiplicand, multiplier, dividend, and divisor of multiplicands, multipliers, dividends, and divisors that can be used by the main CPU 500a are limited. For example, in the DIV instruction for executing division, which is prepared in advance as an operation instruction in the main CPU 500a, the numeric range of both the dividend and the divisor may be limited to 2 bytes. Sometimes it can only handle up to a range. Then, if the total number of games played is, for example, 175,000 games or more, the numerical range is exceeded, and a 2-byte DIV instruction cannot simply be used. In this case, a separate program for repeating addition and subtraction must be prepared, similar to a human performing division by hand, resulting in an increase in processing load. Therefore, in the present embodiment, it is an object to appropriately obtain game information while suppressing an increase in processing load.

In the above, in the slot machine 400, for example, the advantageous section ratio, the instructed accessory ratio, the continuous accessory ratio of 6000 games, the accessory ratio of 6000 games, the total cumulative continuous accessory ratio, the total cumulative accessory An example of displaying the game information such as the ratio and the condition ratio of the accessory etc. on the ratio display section 860 has been described. In a pachinko machine, for example, the number of prize balls (the number of low-probability payouts, which is the number of payouts when low-probability and no time-saving) is calculated in a predetermined reference aggregation period, and the number of outs (the number of outs when low-probability and no time-saving It may be divided by the number of low-probability outs, and the base value shown in % may be displayed on the performance display monitor (ratio display unit 860). It should be noted that the base value of the pachinko machine is not rounded down to the nearest decimal point as in the slot machine 400, but is rounded off.

(Derivation process of each ratio)
Here, a plurality of processing examples for deriving each ratio (advantageous section ratio, instructed accessory ratio, continuous accessory ratio, accessory ratio, accessory state ratio) will be described. The common parts are described in detail. In the present embodiment, values converted into % are finally obtained as the advantageous section ratio, the instructed accessory ratio, the continuous accessory ratio, the accessory ratio, and the accessory state ratio. This indicates that only two decimal places are required for the result of the division. Further, in the slot machine 400, values below the decimal point when converted to % are rounded down. This means that if only two digits after the decimal point can be derived from the result of division, calculations for three digits after the decimal point are not required. Therefore, in this embodiment, the result of division is multiplied by a predetermined multiplier (here, 100) in order to carry it up by two digits. In this example, since only two decimal places are required, the multiplier is multiplied by "100". can be changed.

Also, here, the "accessory ratio" is described as a target of the derivation process, but the same processing can be applied to the advantageous section ratio, the instructed accessory ratio, the continuous accessory ratio, and the accessory state ratio. Needless to say. As described above, the role product ratio is derived by dividing the number of payouts by the total number of payouts and converting it into a percentage. Such a "% conversion" point corresponds to multiplying the multiplier "100". Therefore, it can be represented by a formula such as the role ratio=the number of payouts/total number of payouts×100. However, since the number of goods paid out ≤ the total number of goods paid out, unless the number of goods paid out = the total number of goods paid out, the order of this formula will always be the value below the decimal point at the time of the number of goods paid out ÷ total number of goods paid out. As a result, for example, the main CPU 500a cannot perform calculations.

Therefore, the order of calculation is changed, and the order of the number of payouts = the number of payouts x 100 ÷ the total number of payouts. ) is divided by the total number of payouts. By doing so, it is possible to complete the calculation result using only integers without performing calculations after the decimal point, and as a result, truncation of the decimal point can be easily realized.

FIG. 105 is a flowchart showing an example of calculation of the role product ratio. In the example of FIG. 105, the role product ratio is derived on the assumption that the number of payouts is "7123" and the total number of payouts is "10000". Here, for example, by replacing division with subtraction, division of numbers exceeding the numerical range (0 to 65535) is realized. Numerical values of step S in this figure are used only in the explanation of this figure.

First, the ratio deriving means determines whether or not the number of payouts of the accessory is greater than the total number of payouts (S1). As a result, if it is determined that the number of bonuses paid out is greater than the total number of bonuses paid out (YES in S1), the number of bonuses paid out or the total number of bonuses paid out is not an appropriate number, and the result is that the ratio of bonus characters is abnormal. It is derived, and the arithmetic processing is terminated (S2). If it is determined that the number of payouts of the accessory is equal to or less than the total number of payouts (NO in S1), the ratio deriving means determines whether or not the total number of payouts is 0 (S3). As a result, if the total number of payouts is 0, that is, if the medals have not been paid out yet (YES in S3), it is determined that the role ratio is 0%, and the arithmetic processing ends (S4). ). If it is determined that the total number of payouts is not 0 (NO in S3), the ratio deriving means determines whether or not the number of payouts of the accessory is equal to the total number of payouts (S5). As a result, if it is determined that the number of payouts of the accessory is equal to the total number of payouts (YES in S5), the ratio of the accessory is determined to be 99%, and the arithmetic processing is terminated (S6). As described above, in the present embodiment, when the number of payouts of the accessory is equal to the total number of payouts, the ratio of the accessory is expressed as 99% instead of originally 100%. By doing so, it becomes possible to express all the character product ratios in two digits.

If it is determined that the number of bonus payouts is not equal to the total number of payouts (NO in S5), the ratio deriving means multiplies the number of bonus payouts “7123” by the multiplier “100” (=“712300”), and obtains the dividend (variable) (S7). Subsequently, the ratio deriving means divides the dividend "712300" by the total number of payouts "10000", which is the divisor, to obtain the quotient (="71") (S8). This quotient "71" is the role product ratio. This corresponds to the integer part of 71.23% obtained by dividing the payout number "7123" by the total payout number "10000" and converting it into a percentage, so it can be understood that such calculation is correct.

With such an example of calculation of the role ratio, it is possible to realize division using only simple calculations such as addition, subtraction, and multiplication, and using only integers.

In the above, it is assumed that the decimal point of the role ratio is rounded off. −7700”) is rounded down if the absolute value is larger than 1/2 of the divisor (total number of payouts, here “10000”), and rounded up if less than 1/2.

Here, furthermore, there are two steps of calculation procedure for calculating the role ratio, that is, the calculation of the number of payouts of the role×multiplier (S7 in FIG. 105), and the result of multiplication/total number of payouts (S8 in FIG. 105). , and search for an effective operation procedure. Specifically, first, the effectiveness of a plurality of calculation procedures for executing the number of payouts×multiplier is examined, and then the effectiveness of a plurality of calculation procedures for executing the multiplication result÷total number of payouts is examined.

(Number of goods paid out x multiplier)
When representing the number of payouts as a numerical value, the maximum value is 3 bytes due to the numerical range, and 3 bytes (24 bits) are required as the memory capacity. Also, since the multiplier is 100 here, it can be represented by 1 byte (8 bits). Then, the calculation of the number of payouts×multiplier is a calculation of 24 bits×8 bits. Here, the main CPU 500a can execute a 24-bit by 8-bit operation using an 8-bit MUL instruction that obtains a 16-bit operation result from an 8-bit by 8-bit multiplication.

In addition, as described above, the main CPU 500a incorporates a multiplier and a divider capable of executing calculations independently and in parallel with the main CPU 500a as built-in devices. Here, the multiplier performs, for example, 16-bit×16-bit multiplication in parallel with command processing. Multiplication is executed in the multiplier when a multiplier is written in (multiplier setting register), and after a predetermined time, a 32-bit multiplication result, for example, is set in a different specified address (multiplication result register). . The divider performs, for example, 32-bit/32-bit division in parallel with command processing, and writes the dividend to the specified address (dividend setting register) of the built-in register, and writes the dividend to another specified address ( When a divisor is written in a divisor setting register), division is executed in the divider, and after a predetermined time, a 32-bit division result, for example, is set in a different designated address (division result register). Therefore, the main CPU 500a can employ a 16-bit.times.16-bit multiplier (hereinafter simply referred to as a 16-bit multiplier) in addition to the 8-bit MUL instruction.

Here, a first example of operation using only an 8-bit MUL instruction and a second example of operation using a 16-bit multiplier will be presented and their effectiveness will be compared.

(First calculation example for executing the number of payouts x multiplier)
FIG. 106 is an explanatory diagram for explaining a first operation example using only an 8-bit MUL instruction. In the first operation example using only the 8-bit MUL instruction, multiplicand (3 bytes)×multiplicand (1 byte) operations are performed. Therefore, as shown in FIG. register), and using an 8-bit MUL instruction, the D register value, C register value, and B register value separated in 1-byte units are multiplied by the multiplier (100) in that order. Then, by adding (accumulating) the D register value x 100, the C register value x 100, and the B register value x 100, which are the multiplication results, the calculation result of the BCD register value x 100 (4 bytes ) can be obtained.

FIG. 107 is a flowchart showing specific processing for implementing the first example of calculation, and FIG. 108 is a diagram showing an example of specific commands for implementing the first example of calculation. be. The numerical values of step S in the description of FIG. 107 are used only in the description of this figure.

As shown in FIG. 107, first, the value of the total bonus counter is read to the BCD register (S1). Specifically, the command "LD A, (_EX_YAKR)" on the second line in FIG. , A” copies the value of the A register to the D register, and the 2-byte value stored at the address “_EX_YAKR+1” is read to the BC register by the command “LD BC, (_EX_YAKR+1)” on the fourth line.

Next, as shown in FIG. 107, it is determined whether or not the value of the total bonus counter stored in the BCD register is 0 (S2). Since the result does not change (because it is 0), the first operation example ends. Specifically, the command "OR A, B" on the fifth line in FIG. By command "OR A, C", the logical sum of the value of register A and the value of register C, which are the operation results on the 5th line, is calculated. If the logical sum is 0, it moves to an index "E_PYSAV28" (not shown) indicating another process. If the processing differs depending on the contents of the F register, such as the command "JR Z, E_PYSAV28", the number of cycles will also differ. For example, the command "JR Z, E_PYSAV28" requires 3 cycles as shown to the left of the slash of the cycle number in FIG. becomes a cycle. The following commands are similarly displayed when the processing differs depending on the contents of the F register.

Subsequently, as shown in FIG. 107, the value of the D register, which is the least significant byte of the multiplicand, is multiplied by the multiplier (100) (S3), and the operation result is set in the DE register (S4). Specifically, the command "LD A, D" on the eighth line in FIG. and 100 is held in the HL register, and the value of the HL register is set in the DE register by the command "EX DE, HL" on the 10th line.

Next, as shown in FIG. 107, the value of the C register, which is the middle byte of the multiplicand, is multiplied by the multiplier (100) (S5), and the result of adding the value of the D register to the operation result is returned to the D register. (S6), set in the main RAM 500c (S7). Specifically, the command "LD A, C" on the 11th line in FIG. and 100 are multiplied and held in the HL register. Only the upper 1 byte (value of D register) of the registers is added, and the lower 1 byte of the addition result is returned to the D register by the command "LD D, L" on the 14th line, and the command " The DE register value corresponding to the lower 2 bytes of the multiplication result is moved to the HL register by the command "EX DE, HL", and the 2-byte value of the HL register is addressed by the command "LD (_EX_WRK2), HL" on the 16th line. Store in "_EX_WRK2".

Subsequently, as shown in FIG. 107, the value of the B register, which is the most significant byte of the multiplicand, is multiplied by the multiplier (100) (S8), and the result of the operation is added to the upper 1 byte (H (S9) and set in the main RAM 500c (S10). Specifically, the command "LD A, B" on the 17th line in FIG. and 100 is held in the HL register, and DE set by the command "EX DE, HL" on the 15th line is stored in the HL register of the multiplication result by the command "ADDWB HL, D" on the 19th line. HL Store the 2-byte value of the register at address "_EX_WRK2+2". In this way, it is possible to obtain the operation result of the 4-byte BCD register value×100 at the address “_EX_WRK2”.

Here, in this command example, as shown in FIG. 108, the total command size is 38 bytes, and the simple total of the number of cycles (simply totaling the number of cycles without considering move instructions) is 49/48. becomes a cycle.

(Second calculation example for executing the number of payouts x multiplier)
FIG. 109 is an explanatory diagram for explaining a second operation example using a 16-bit multiplier. In the second operation using a 16-bit multiplier, the multiplicand (3 bytes)×multiplicand (1 byte) is calculated, so the multiplicand is stored in the BCD register (BC register and D register) as shown in FIG. Then, the value of the BC register (2-byte value) and the multiplier (100) are multiplied using a 16-bit multiplier, and each value of the D register is multiplied by the multiplier (100) using the 8-bit MUL instruction. . Then, by adding the BC register value x 100 and the D register value x 100 as a result of the multiplication, the operation result of the 4-byte BCD register value x 100 can be obtained.

FIG. 110 is a flowchart showing specific processing for implementing the second example of computation, and FIG. 111 is a diagram showing an example of specific commands for implementing the second example of computation. be. The numerical values of step S in the description of FIG. 110 are used only in the description of this figure.

As shown in FIG. 110, first, the value of the total bonus counter is read to the BCD register (S1). Specifically, the command "LD A, (_EX_YAKR)" on the second line in FIG. , A” copies the value of the A register to the D register, and the 2-byte value stored at the address “_EX_YAKR+1” is read to the BC register by the command “LD BC, (_EX_YAKR+1)” on the fourth line.

Next, as shown in FIG. 110, it is determined whether or not the value of the total bonus counter stored in the BCD register is 0 (S2). Since the result does not change (because it is 0), the second example of operation ends. Specifically, the command "OR A, B" on the fifth line in FIG. By command "OR A, C", the logical sum of the value of register A and the value of register C, which are the results of the operation on line 5, is calculated. If the logical sum is 0, it moves to an index "E_PYSAV28" (not shown) indicating another process.

Subsequently, as shown in FIG. 110, the upper two bytes of the multiplicand are set in the multiplicand setting register (S3), the multiplier (100) is set in the multiplier setting register, and multiplication is executed (S4). Specifically, the value of the BC register is set in the multiplicand setting register "@MULA16_" by the command "LD (@MULA16_), BC" on the eighth line in FIG. sets the multiplier "100" in the A register, and the command "OUT (LOW @MULB16_), A" on the 10th line sets the value of the U register to the upper 1 byte of the address, and sets the address "@MULB16_" to the lower 1 byte, and outputs the value of the A register to the multiplier setting register indicated by that address. It should be noted that "00H" is set as a default value in the high-order 1 byte of the multiplier setting register "@MULB16_". Thus, the 16-bit multiplier is operated and the multiplication result is stored in the multiplication result register.

Next, as shown in FIG. 110, the value of the D register, which is the least significant byte of the multiplier, is multiplied by the multiplier (100) (S5). Specifically, the command "LD A, D" on the 11th line in FIG. and 100 are multiplied and held in the HL register.

Subsequently, as shown in FIG. 110, the lower 3 bytes of the multiplication result stored in the multiplication result register are read into the DEA register (S6), and the value of the A register and the higher 1 byte (H (S7) and set in the main RAM 500c (S8). Specifically, the command “IN A, (LOW @MUL32 — +0” on the 13th line in FIG. The value of the multiplication result register is read into the A register, and the 2nd and 3rd bytes from the lowest of the multiplication result register are read into the DE register by the command "LD ED, (LOW @MUL32__+1" on the 14th line. The second command "ADD A, H" adds the upper 1 byte (H register value) of the multiplication result set by the command "MUL HL, A, 100" on the 12th line to the value of the A register, The command "LD H, A" on the 16th line returns the addition result (the value of the A register) to the H register, and the command "OUT (LOW @DIVA32_+0), HL" on the 17th line returns the value of the U register to the address. , and the address "@DIVA32_" is set as the lower 1 byte, and the value of the HL register is output to the dividend setting register "@DIVA32_" indicated by that address.

Next, as shown in FIG. 110, the value of the DE register set in step S6 is duplicated in the HL register (S9), and it is determined whether or not the value has been rounded up in the addition of step S7 (S10). If yes (YES in S10), the carry-up amount is added to the HL register (S11) and set in the main RAM 500c (S12). Specifically, the command "EX DE, HL" on the 18th line in FIG. ADD A, H" determines whether or not the carry flag is set. If the carry flag is not set, move to the index "E_PYSAVX1" on the 21st line. If the carry flag is set, the command on the 20th line By "INC HL", the value of the HL register is incremented by 1, and by the command "OUT (LOW @DIVA32_+2), HL" on the 22nd line, the value of the U register is set to the upper 1 byte of the address, and the address is "@DIVA32_+2". is the lower 1 byte, and the value of the HL register is output to the divisor setting register indicated by that address.

Here, in this command example, as shown in FIG. 111, the total command size is 43 bytes, and the simple sum of the number of cycles is 59/57 cycles.

As described above, comparing the first calculation example of executing the number of payouts x multiplier with the second example of calculation of executing the number of payouts x multiplier, the total command size and the number of cycles are simple. Both of the totals are smaller in the first calculation example. Therefore, when the slot machine 400 executes the payout number×multiplier, it is preferable to execute only the 8-bit MUL instruction as described with reference to FIGS. 106-108.

In the above-described first calculation example, the command "LD" was used as the command on the 16th and 20th lines of FIG. Therefore, the command "OUT" may be used as the commands on the 16th and 20th lines. In the case of FIG. 112 as well, the total command size is 38 bytes, and the simple sum of the number of cycles is 49/48 cycles, similar to FIG.

(multiplication result / total number of payouts)
Next, the effectiveness of the multiplication result of (number of payouts×multiplier)÷total number of payouts among the multi-stage calculation procedures for calculating the role product ratio will be examined. As described above, the multiplication result of the number of payouts (3 bytes)×multiplier (1 byte) is a maximum of 4 bytes, so a memory capacity of 4 bytes or more is required. Therefore, here, the multiplication result is represented by 4 bytes (32 bits). Also, since the total number of payouts has a maximum value of 3 bytes, a memory capacity of 3 bytes or more is required. Therefore, the total number of payouts is also represented by 4 bytes. Then, the multiplication result/total number of payouts is a 32-bit/32-bit calculation. The main CPU 500a repeatedly subtracts the total number of payouts from the multiplication result, and can realize an operation of 32 bits/32 bits by the number of subtractions.

However, in the method of simply repeatedly subtracting the total number of payouts from the multiplication result, the total number of payouts must be repeatedly subtracted from the multiplication result the number of times corresponding to the role ratio. Then, the subtraction process is executed 100 times at maximum. Therefore, it is conceivable to reduce the number of subtraction processes by multiplying the total number of payouts, which is a divisor, by an integral number. For example, when the number of payouts is "7123" and the total number of payouts is "10000", the total number of payouts "10000" is not simply subtracted from the multiplication result "712300" which is the dividend. By subtracting "100000" obtained by multiplying "10000" by the integer "10", it is possible to derive "7" corresponding to the second digit (ten's digit) of the role item ratio. Also, by subtracting the original total number of payouts "10000" from the updated (subtracted) multiplication result, it is possible to derive "1" corresponding to the first digit (1's digit) of the character ratio. can. By multiplying the total number of payouts (divisor) by an integer in this way, it is possible to reduce the number of subtraction processes to 20 times at most.

However, since the main CPU 500a performs operations in binary numbers, here, instead of the number "10" corresponding to the carry of the decimal number, the number "2" corresponding to the carry of the binary number is used. Therefore, here, from the multiplication result “712300”, subtract the number obtained by multiplying the total number of payouts “10000” by a predetermined integer “64 (2 to the sixth power)” which is a power of 2, and then subtract the integer "32 (2 to the 5th power)" → "16 (2 to the 4th power)" → "8 (2 to the 3rd power)" → "4 (2 to the 2nd power)" → "2 (2 to the 1st power)" → Multiply the total number of payouts by changing the order of "1 (2 to the 0th power)", and subtract from the multiplication result. Here, the reason why the integer to be multiplied by the total number of payouts starts from 64, which is a power of 2, is because the character ratio falls within the range of 0 to 99, so the number of "128 (2 to the 7th power)" or more This is because there is no need to subtract numerical values.

Further, as described above, the main CPU 500a incorporates, for example, a 32-bit/32-bit divider (hereinafter simply referred to as a 32-bit divider). Therefore, in the main CPU 500a, instead of repeatedly subtracting the total number of payouts multiplied by a power of 2 from the above multiplication result (hereinafter simply referred to as repeated subtraction of the number multiplied by a power of 2), A 32-bit divider can be employed.

Here, a third calculation example using repeated subtraction of a number multiplied by a power of 2 and a fourth calculation example using a 32-bit divider will be presented and their effectiveness will be compared.

(Third calculation example for executing multiplication result/total number of payouts)
FIG. 113 is an explanatory diagram for explaining a third calculation example using repeated subtraction of a number multiplied by a power of 2. FIG. In the third calculation example using repeated subtraction of a number multiplied by a power of 2, an example of calculation of the multiplicand (4 bytes) that is the result of multiplication divided by the divisor (4 bytes) that is the total payout number is shown. Here, it is assumed that the dividend is "712300" and the divisor is "64×10000" obtained by multiplying the original divisor "10000" by 64.

As shown in FIG. 113, if it is determined that the dividend≧the divisor in the first determination, the divisor can be subtracted from the multiplicand. The dividend is updated to "72300", and "64" is added to the quotient "0" to update the quotient to "64 (1000000B in binary)". In the second to fourth determinations, since the dividend<the divisor, subtraction of the divisor is not performed. In the fifth determination, if it is determined that the dividend≧the divisor, the ratio deriving means subtracts the divisor "4×10000" from the dividend "72300" to update the dividend to "32300" and the quotient to "64". Add "4" to update the quotient to "68 (1000100B in binary)". Similarly, if it is determined that the dividend≧the divisor in the sixth determination, the ratio deriving means subtracts the divisor "2×10000" from the dividend "32300" to update the dividend to "12300" and the quotient " "68" is added with "2" to update the quotient to "70 (1000110B in binary)". In the seventh determination, if it is determined that the dividend≧the divisor, the ratio deriving means subtracts the divisor "1×10000" from the dividend "12300" to update the dividend to "2300" and the quotient to "70". Add "1" to update the quotient to "71 (1000111B in binary)".

When the subtraction step and the addition step are repeated 7 times from the integer = "64", the integer is rounded down to 0 (<1). It becomes "71". This corresponds to the integer part of 71.23% obtained by dividing the payout number "7123" by the total payout number "10000" and converting it into a percentage, so it can be understood that such calculation is correct.

FIG. 114 is a flowchart showing specific processing for implementing the third example of calculation, and FIG. 115 is a diagram showing an example of specific commands for implementing the third example of calculation. be. The numerical values of step S in the description of FIG. 114 are used only in the description of this figure. Here, it is assumed that an address "_EX_WRK1" storing a 4-byte divisor and an address "_EX_WRK2" storing a 4-byte dividend are arranged consecutively.

As shown in FIG. 114, first, the quotient is initialized to 0 and the integer (power of 2) is initialized to 64 (S1), the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are read out (S2), and the upper 2 bytes of the dividend are read out. It is determined whether or not the 2 bytes are less than the upper 2 bytes of the divisor (S3). If the upper two bytes of the dividend are less than the upper two bytes of the divisor (YES in S3), the process moves to step S10. Specifically, the command "XOR A, A" on the first line in FIG. "64" is set, and by the command "LD HL, _EX_WRK2+2" on the 4th line, the value obtained by adding 2 to the value of the address "_EX_WRK2" that stores the dividend (the result of multiplication of the payout number x multiplier) ( The value of the upper 2 bytes) is read into the HL register, and the address "_EX_WRK1" located 4 bytes below the address "_EX_WRK2" where the dividend is stored is read by the command "LD DE, (HL-4)" on the fifth line. read the upper 2 bytes of the divisor stored in the DE register, and read the value of the address indicated by the HL register (the upper 2 bytes of the dividend) and , DE register value (upper 2 bytes of the divisor), and if the carry flag is set, that is, if the upper 2 bytes of the dividend are less than the upper 2 bytes of the divisor, the index "E_PYSAV27" on the 20th line ”.

Next, as shown in FIG. 114, if the upper 2 bytes of the dividend are greater than or equal to the upper 2 bytes of the divisor (NO in S3), the lower 2 bytes of the dividend and the lower 2 bytes of the divisor are read out for subsequent calculation. (S4) It is determined whether the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are not equal, that is, whether the upper 2 bytes of the dividend are greater than the upper 2 bytes of the divisor (S5). If the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are not equal (YES in S5), the process moves to step S8. Specifically, by the command "LD HL, _EX_WRK1" on the seventh line in FIG. HL+4)” reads the lower two bytes of the dividend stored at the address “_EX_WRK2” located four bytes higher than the address “_EX_WRK1” storing the divisor to the DE register, and the command “JR NZ, E_PYSAV26” moves to the index “E_PYSAV26” on the 12th line if the zero flag is not set by execution of the command on the 6th line.

Subsequently, as shown in FIG. 114, it is determined whether or not the lower 2 bytes of the dividend read in step S4 are greater than the lower 2 bytes of the divisor (S6), and the lower 2 bytes of the dividend are greater than the lower 2 bytes of the divisor. If the lower 2 bytes of the divisor are equal to or less than the lower 2 bytes of the divisor (NO in S6), in step S6 the lower 2 bytes of the dividend and the lower 2 bytes of the divisor are It is determined whether they are not equal, that is, whether the lower 2 bytes of the dividend are less than the lower 2 bytes of the divisor (S7). If the lower 2 bytes of the dividend and the lower 2 bytes of the divisor are not equal (YES in S7), the process moves to step S10. Specifically, the command "JCP C, (HL), DE, E_PYSAV26" on line 10 in FIG. lower 2 bytes) and the carry flag is set, i.e., if the lower 2 bytes of the dividend are greater than the lower 2 bytes of the dividend, move to the index "E_PYSAV26" on the 12th line, and move to the index "E_PYSAV26" on the 11th line. With the command "JR NZ, E_PYSAV27", if the execution of the command on the 10th line does not set the zero flag, the process moves to the index "E_PYSAV27" on the 20th line.

Next, as shown in FIG. 114, if the dividend is greater than or equal to the divisor, the current integer is added to the quotient (S8), the divisor is subtracted from the dividend, and the subtraction result is updated as a new dividend ( S9). Specifically, the command "ADD A, C" on the 13th line in FIG. ' updates the DE register by subtracting the value of the lower 2 bytes of the divisor stored at the address indicated by the HL register from the value of the DE register storing the lower 2 bytes of the dividend, and the command on line 15. "LD (HL+4), DE" stores the lower 2 bytes of the updated dividend, which is the subtraction result, at the address indicating the dividend located 4 bytes higher than the address storing the divisor indicated by the HL register. , by the command "LD DE, (HL+2)" on the 16th line, the upper two bytes of the divisor stored at the address indicated by the HL register are read out to the DE register, and the command "LD HL, (HL+6)" on the 17th line is read. reads the upper 2 bytes of the dividend located 6 bytes higher than the address where the divisor indicated by the HL register is stored to the HL register. The value of the DE register, which stores the upper 2 bytes of the divisor, is subtracted from the value of the HL register, which stores the , to update the HL register. _EX_WRK2” stores the updated upper 2 bytes of the dividend, which is the subtraction result, in the higher 2 bytes of the dividend.

Subsequently, as shown in FIG. 114, the divisor is divided by 2 (bit-shifted to the right), updated as a new divisor (S10), the integer is divided by 2 (bit-shifted to the right), and the new integer is update (S11), determine whether or not the integer is 0 (S12), if not 0 (YES in S12), repeat the process from step S2, and if 0 (NO in S12), The ratio is set in the main RAM 500c (S13), and the process of repeatedly subtracting the number obtained by multiplying the power of 2 is terminated. Specifically, the command "LD HL, _EX_WRK1+3" on the 21st line in FIG. The value of the address indicated by the HL register (4th byte of the divisor) is shifted to the right by 1 bit, the command "DEC HL" on the 23rd line decrements the value of the HL register by 1, and the command "RR (HL)" shifts the value of the address indicated by the HL register (3rd byte from the lowest part of the divisor) by 1 bit to the right, and the command "DEC HL" on the 25th line shifts the value of the HL register to 1. , and the value of the address indicated by the HL register (second byte from the lowest divisor) is shifted right by 1 by the command "RR (HL)" on the 26th line, and the command "DEC HL" on the 27th line is shifted to the right. , the value of the HL register is decremented by 1, and the value of the address indicated by the HL register (lowest 1 byte of the divisor) is shifted right by 1 by the command "RR (HL)" on the 28th line, The command "SRL C" on the 29th line shifts the value of the C register indicating an integer to the right by one bit, and the command "JR NZ, E_PYSAV25" on the 30th line clears the zero flag by executing the command on the 29th line. If not, move to the index "E_PYSAV25" on the 3rd line and store the value of the A register, which is the quotient, at the address "_EX_DPA7" by "LD (_EX_DPA7), A" on the 32nd line.

According to the third operation example, it is possible to realize division using only simple operations such as addition, subtraction, and multiplication, and using only integers. Further, here, since it is sufficient to repeat the subtraction and addition processing seven times, the arithmetic processing can be performed quickly. Furthermore, assuming that the decimal point of the character product ratio is rounded down, no error occurs, so it is possible to derive the character product ratio accurately.

Here, in this command example, as shown in FIG. 115, the total command size is 59 bytes, and the simple sum of the number of cycles is 95/90 cycles. Also, the actual number of cycles is as follows. That is, in the processing, the command (4th line) following the index "E_PYSAV25" to the command (30th line) immediately preceding the index "E_PYSAV28" is looped seven times. At this time, in all 7 loops, when the command "JCP C, (HL), DE, E_PYSAV27" on the 6th line moves to the index "E_PYSAV27", the commands on the 7th to 19th lines are not executed. , the minimum number of cycles is 321 (3+45 (first 6 loops)×6+44 (7th loop)+4) cycles. On the other hand, in all loops, if the command "JCP C, (HL), DE, E_PYSAV27" on the 6th line does not move to the index "E_PYSAV27", the number of cycles will be maximum. However, the role ratio never exceeds 100%, and the maximum processing load is at 95% and 63%. loop)×6+4) cycles. Therefore, the practical total number of cycles ranges from 321 to 566 cycles.

It should be noted that here also, it is assumed that the decimal part of the role ratio is rounded off, but not limited to this case, when the decimal part of the role ratio is rounded off, the subtraction and addition process is repeated eight times, and the eighth determination can be realized by adding 1 to the quotient if it is determined that the dividend≧the divisor.

(Fourth calculation example of executing multiplication result/total number of payouts)
FIG. 116 is a flowchart showing specific processing for realizing the fourth example of calculation, and FIG. 117 is a diagram showing an example of specific commands for realizing the fourth example of calculation. be. The numerical values of step S in the description of FIG. 116 are used only in the description of this figure. Here, as described with reference to FIG. 112, it is assumed that the dividend, which is the multiplication result of the number of payouts×multiplier, has already been set in the dividend setting register "DIVA32".

As shown in FIG. 116, first, the value of the total bonus counter is read into a register and set in the divisor setting register "DIVB32" (S1). Specifically, the command "LD HL, (_EX_PRZR)" on the first line in FIG. By the command "LD A, (_EX_PRZR+2)", the value stored at the address "_EX_PRZR+2" indicating the upper 1 byte of the total bonus counter is read to the A register, and the command "OUT (LOW @DIVB32_+0 ), HL” sets the value of the U register to the upper 1 byte of the address, sets the address “@DIVB32_” to the lower 1 byte, outputs the value of the HL register to that address, and outputs the value of the HL register to the address. @DIVB32_+2),A" sets the value of the U register as the upper 1 byte of the address, sets the address "@DIVB32_+2" as the lower 1 byte, and outputs the value of the A register to that address. Note that the upper 1 byte of the divisor setting register "@DIVB32_" is set to "00H" as a default value.

Next, as shown in FIG. 116, division is waited for (S2), and after a predetermined period of time has passed, the calculation result is set in the main RAM 500c (S3). Specifically, the command "NOP" on the 5th to 8th lines in FIG. 1 byte, the address "@DIV32__+0" is set to the lower 1 byte, the value of the division result register indicated by that address is read into the A register, and the quotient A register is stored in the address "_EX_DPA7".

Here, in this command example, as shown in FIG. 117, the total command size is 20 bytes, and the total number of cycles is 28 cycles.

As described above, when comparing the third calculation example of executing the multiplication result/total number of payouts and the fourth calculation example of executing the multiplication result/total number of payouts, the total command size and the total number of cycles are are smaller in the fourth calculation example. Therefore, when the multiplication result÷total number of payouts is executed in the slot machine 400, it is preferable to use a 32-bit divider as described with reference to FIGS.

The manner of calculating the role product ratio in the slot machine 400 has been described above with reference to the first to fourth examples of calculation. The base value of the pachinko machine will be described below. It should be noted that the advantageous section ratio, the instructed character ratio, the continuous character ratio, the character ratio, and the condition ratio of the character, etc. in the slot machine 400 are all rounded down to the nearest whole number. number/out number) is rounded off to the nearest whole number. Therefore, in a pachinko machine, "200" is used instead of "100" as a multiplier for the number of winning balls, and whether or not the number after the decimal point is 0.5 or more is determined by replacing it with an integer (least significant bit). Therefore, the base value is obtained by multiplying the number of prize balls by a multiplier (200), then dividing the result (dividend) by the number of outs, and rounding up or down depending on the least significant bit (MLB).

Here, a fifth operation example using an 8-bit MUL instruction and repeated subtraction of a number multiplied by a power of 2, and a sixth operation example using a 16-bit multiplier and a 32-bit divider will be presented. Compare effectiveness.

(Fifth calculation example for executing the number of prize balls x multiplier / number of outs)
FIG. 118 is a flow chart showing specific processing for realizing the fifth operation example using an 8-bit MUL instruction and repeated subtraction of a number multiplied by a power of 2. FIG. FIG. 10 is a diagram showing an example of a specific command for realizing the calculation example of . The numerical values of step S in the description of FIG. 118 are used only in the description of this figure. Here, the address "R_ERW_BF1" storing a 3-byte dividend (calculation result obtained by multiplying the number of winning balls by a multiplier) and the address "R_ERW_BF2" storing a 3-byte divisor (number of outs) are used. are arranged consecutively.

As shown in FIG. 118, first, the value of the normal ball counter is read into the BC register (S1), the value of the normal out counter is read into the HL register (S2), and it is determined whether the HL register is 0 ( S3), if it is 0 (YES in S3), the process proceeds to step S23. Specifically, the command "XOR A, A" on the second line in FIG. The value of the normal prize ball counter indicated by the address "R_ERW_TJS" (the number of prize balls) is read to the BC register, and the normal out counter indicated by the address "R_ERW_TJO" is read by the command "LD HL, (R_ERW_TJO" on the fourth line. (number of outs) is read to the HL register, and if the value of the HL register is 0 by the command "JR TZ, E_SHYMT-- 60" on the fifth line, it moves to the index "E_SHYMT-- 60" on the 49th line.

Next, as shown in FIG. 118, the out number is multiplied by an integer (a power of 2, here 128) (S4), and the result of the calculation is stored in the main RAM 500c as a divisor buffer (S5). Specifically, the command "SRL H" on the 6th line in FIG. 119 shifts the value of the H register to the right by 1 bit, and the command "RR L" on the 7th line shifts the value of the H register to L including the carrier from the H register. The value of the register is shifted to the right by 1 bit, and the value of the A register including the carrier from the L register is shifted to the right by 1 bit by the command "RRA" on the 8th line. Here, if the numerical value is judged in terms of the HLA register, the value of the HL register is multiplied by 256, and since it can be regarded as being shifted by 1 to the right, the out number is multiplied by 128 (256/2). This is the divisor. Then, the value of the A register, which is the lower byte of the divisor, is stored in the address "R_ERW_BF2" by the command "LD (R_ERW_BF2), A" on the ninth line in FIG. HL” stores the value of the HL register, which is the upper two bytes of the divisor, at the address “R_ERW_BF2+1”.

Subsequently, as shown in FIG. 118, the value of the C register, which is the lower byte of the multiplicand (the number of prize balls), is multiplied by the multiplier (200) (S6), and the result is set in the DE register (S7). Specifically, the command "LD A, C" on the 11th line in FIG. and 200 is held in the HL register, and the value of the HL register is set in the DE register by the command "EX DE, HL" on the 13th line.

Next, as shown in FIG. 118, the value of the B register, which is the upper byte of the multiplicand, is multiplied by the multiplier (200) (S8), and the value of the D register is added to the operation result to update the operation result ( S9), the calculation result is stored in the main RAM 500c as a dividend buffer (S10). Specifically, the command "LD A, B" on the 14th line in FIG. and 200 is held in the HL register. Only the high-order 1 byte (the value of the D register) of the registers is added, and the DE register set by the command "EX DE, HL" on the 13th line is added by the command "LD A, E" on the 17th line. The lower 1 byte is set in the A register, and the value of the A register, which is the lower byte of the dividend, is stored in the address "R_ERW_BF1" by the command "LD (R_ERW_BF1), A" on the 18th line, and the command " LD (R_ERW_BF1+1), HL" stores the value of the HL register, which is the upper two bytes of the dividend, at the address "R_ERW_BF1+1".

Subsequently, as shown in FIG. 118, the loop count is initialized to 8 and the quotient is initialized to 0 (S11), the quotient is doubled (S12), and the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are read out (S13). ), and it is determined whether or not the upper two bytes of the dividend are less than the upper two bytes of the divisor (S14). If the upper two bytes of the dividend are less than the upper two bytes of the divisor (YES in S14), the process moves to step S20. Specifically, the command "LD BC, 8*256+0" on the 20th line in FIG. C" shifts the value of the C register to the left by 1 bit (0 is entered in the MSB), and the command "LD HL, R_ERW_BF1+1" on the 23rd line stores the dividend (the result of multiplying the number of prize balls by the multiplier). The value obtained by adding 1 to the value of the address "R_ERW_BF1" stored is read into the HL register. The upper 2 bytes of the divisor stored at the address "R_ERW_BF2" located in , are read to the DE register, and the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line reads the value of the address indicated by the HL register ( The upper 2 bytes of the dividend) and the DE register value (the upper 2 bytes of the divisor) are compared, and if the carry flag is set, that is, if the upper 2 bytes of the dividend are less than the upper 2 bytes of the divisor, Go to the index "E_SHYMT_55" on the 38th line.

Next, as shown in FIG. 118, if the upper 2 bytes of the dividend are greater than or equal to the upper 2 bytes of the divisor (NO in S14), the lower 1 byte of the divisor and the lower 1 byte of the dividend are read out for subsequent calculation. (S15) In step S14, it is determined whether or not the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are not equal, that is, whether or not the upper 2 bytes of the dividend are greater than the upper 2 bytes of the divisor (S16). . If the upper 2 bytes of the dividend and the upper 2 bytes of the divisor are not equal (YES in S16), the process proceeds to step S18. It is determined whether or not the lower 1 byte of the dividend is less than the lower 1 byte of the divisor (S17). If the lower 1 byte of the dividend is less than the lower 1 byte of the divisor (YES in S17), the process moves to step S20. Move to S18. Specifically, the lower 1 byte of the address "R_ERW_BF2" storing the divisor is read to the L register by the command "LD L, LOW R_ERW_BF2" on the 26th line in FIG. The upper 1 byte of "R_ERW_BF2" is already held by the second command "LD HL, R_ERW_BF1+1"), and the address storing the divisor by the command "LD A, (HL-3)" on the 27th line. The lower 1 byte of the dividend stored at the address "R_ERW_BF1" located 3 bytes lower than "R_ERW_BF2" is read into the A register, and the command "JR NZ, E_SHYMT_50" on the 28th line and the command on the 25th line are executed. If the zero flag is not set, move to the index "E_SHYMT_50" on the 31st line, and execute the command "CP A, (HL)" on the 29th line with the value of the A register (lower 1 byte of the dividend) and the The value of the indicated address (lower 1 byte of the divisor) is compared, and if the carry flag is set by the command "JRC, E_SHYMT_55" on the 30th line, that is, the lower 1 byte of the dividend becomes the lower 1 byte of the divisor. If it is less than bytes, go to the index "E_SHYMT_55" on the 38th line.

Subsequently, as shown in FIG. 118, if the dividend is greater than or equal to the divisor, the divisor is subtracted from the dividend, the subtraction result is updated as a new dividend (S18), and 1 is added to the quotient (S19). Specifically, the command "SUB A, (HL)" on the 32nd line in FIG. By the command "LD (HL-3), A" on the 33rd line, the address indicating the dividend located 3 bytes lower than the address storing the divisor indicated by the HL register is updated as the result of the subtraction. The lower 1 byte of the obtained dividend is stored, and the command "LD HL, (HL-2)" on the 34th line stores the upper 1 byte of the dividend located 2 bytes lower than the address where the divisor indicated by the HL register is stored. The address indicating 2 bytes is read out to the HL register, and the command "SBC HL, DE" on the 35th line converts the value of the HL register, which stores the upper 2 bytes of the dividend, to the DE register, which stores the upper 2 bytes of the divisor. and stores the updated upper 2 bytes of the dividend, which is the subtraction result, in the upper 2 bytes of the dividend indicated by the address "R_ERW_BF1" by the command "LD (R_ERW_BF1+1), HL" on the 36th line, The command "INC C" on the 37th line increments the value of the C register, which indicates the quotient, by one.

Next, as shown in FIG. 118, the divisor is divided by 2 (bit-shifted to the right), updated as a new divisor (S20), the loop count is subtracted, and it is determined whether or not the loop count is 0. (S21), if not 0 (YES in S21), the process from step S12 is repeated. (S23), the process ends. Specifically, the command "LD HL, R_ERW_BF2+2" on the 39th line in FIG. The value of the address indicated by the register (the third byte of the divisor) is shifted right by 1, the command "DEC HL" on the 41st line decrements the value of the HL register by 1, and the command " RR (HL)" shifts the value of the address indicated by the HL register (the second byte of the divisor) by 1 bit to the right, and the command "DEC HL" on the 43rd line decrements the value of the HL register by 1. , the value of the address indicated by the HL register (the first byte of the divisor) is shifted to the right by 1 bit by the command "RR (HL)" on the 44th line, and the loop count is changed by the command "DJNZ E_SHYMT_45" on the 45th line. is decremented by 1, and if the value is not 0, go to the index "E_SHYMT_45" on the 21st line. On the other hand, when the loop count becomes 0, the value of the C register indicating the quotient is duplicated in the A register by the command "LD A, C" on the 46th line in FIG. If the value of the address indicated by the register is shifted to the right by 1 bit and the carry flag is set by the command "ADC A, 0" on the 48th line and the command "SRL A" on the 47th line, that is, the decimal point If the following is 0.5 or more, 1 is added to the A register, the address "R_ERW_BAS" indicating the base value is set in the HL register by the command "LD HL, R_ERW_BAS" on the 50th line, and The command "LD (HL), A" stores the value of the A register indicating the base value at the address "R_ERW_BAS".

According to the fifth example of calculation, it is possible to derive the base value by using only simple calculations such as addition, subtraction, and multiplication, and by using repeated subtraction of numbers multiplied by powers of 2.

Here, in this command example, as shown in FIG. 119, the total command size is 97 bytes, and the simple sum of the number of cycles is 136/131 cycles. Also, the actual number of cycles is as follows. That is, in this process, the command (22nd line) following the index "E_SHYMT_45" to the command "DJNZ E_SHYMT_45" on the 45th line is looped eight times. At this time, in all eight loops, when the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line moves to the index "E_SHYMT_55", the commands on the 26th to 37th lines are not executed. , the number of cycles is a minimum of 367 (54+38 (first 7 loops)×7+37 (8th loop)+10) cycles. On the other hand, in all loops, if the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line does not move to the index "E_SHYMT_55", the number of cycles is maximum. However, due to possible numerical values, in the first and second loops, the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line does not move, and the command "JR NZ, E_SHYMT_50" on the 28th line does not move. , and in the 3rd to 8th loops, the command "JCP C, (HL), DE, E_SHYMT_55" on the 25th line, the command "JR NZ, E_SHYMT_50" on the 28th line, and the command "JR C , E_SHYMT_55”, the maximum number of cycles is 601 (54+65 (first two loops)×2+68 (five loops after that)×5+67 (eighth loop)+10). ) cycle. Therefore, the practical total number of cycles ranges from 367 to 601 cycles.

(Sixth calculation example for executing the number of prize balls × multiplier / number of outs)
FIG. 120 is a flow chart showing specific processing for implementing the sixth example of operation using a 16-bit multiplier and a 32-bit divider, and FIG. is a diagram showing an example of a specific command of . The numerical values of step S in the description of FIG. 120 are used only in the description of this figure.

As shown in FIG. 120, first, the number of prize balls is set in the multiplicand register (S1), and the multiplier "200" is set in the multiplier register (S2). Specifically, the command "LD HL, (R_ERW_TJS)" on the first line of FIG. The second command "OUT (LOW @MULA16_)" sets the value of the U register to the upper 1 byte of the address, sets the address "@MULA16_" to the lower 1 byte, and outputs the value of the HL register to the multiplier setting register indicated by that address. Then, the command "EX DE, HL" on the third line copies the value of the HL register to the DE register, and the command "LD A, 200" on the fourth line sets the multiplier "200" in the A register, The command "OUT (LOW @MULB16_), A" on the fifth line sets the value of the U register to the upper 1 byte of the address, sets the address "@MULB16_" to the lower 1 byte, and sets A to the multiplier setting register indicated by that address. Print the value of a register. It should be noted that "00H" is set as a default value in the high-order 1 byte of the multiplier setting register "@MULB16_".

Next, as shown in FIG. 120, assuming that the normal winning ball counter is 0, 0 is set as the initial value of the base value (S3), and it is determined whether or not the number of outs is 0 (S4 ), if it is 0 (YES in S4), the result does not change even if it is multiplied by the multiplier (because it is 0), the process moves to step S13, and if it is not 0 (NO in S4), the base value is set to 100. (S5), it is determined whether or not the number of outs is less than the number of prize balls (S6), and if the number of outs is less than the number of prize balls (YES in S6), the process moves to step S13. Specifically, the value of the A register indicating the base value is set to 0 by the command "XOR A, A" on the sixth line in FIG. 121, and the address " R_ERW_TJO" is read into the HL register, and if the value of the HL register is 0 by the command "JR TZ, E_SHYMT_60" on line 8, then the index on line 23 Move to "E_SHYMT_60", set 100 as the initial value in the A register indicating the base value by the command "LD A, 100" on the 9th line, and set the command "JCP C, HL, DE, E_SHYMT_60" on the 10th line. compares the value of the HL register (the number of outs) and the value of the DE register (the number of prize balls), and if the carry flag is set, that is, if the number of outs is less than the number of prize balls, line 23 index "E_SHYMT_60".

Subsequently, as shown in FIG. 120, the out number is set in the divisor setting register (S7), the multiplication result by the 16-bit multiplier is read out to the HLA register (HL register and A register) (S8), and the dividend is set. Set in the register (S9). Specifically, the command "OUT (LOW @DIVB32_), HL" on the 11th line in FIG. The value of the HL register is output to the indicated divisor setting register "@DIVB32__", the value of the U register is set to the upper 1 byte of the address by the command "IN A, (LOW @MUL32__" on the 12th line, and the address "@MULB32__" , and read the 1-byte value of the multiplication result register indicated by that address into the A register. 2-byte value of the multiplication result register indicated by that address is read to the HL register, and the command "OUT (LOW @DIVA32_+0), A" on the 14th line causes U The register value is set to the upper 1 byte of the address, the address "@DIVA32_" is set to the lower 1 byte, the value of the A register is output to the dividend setting register "@DIVA32_" indicated by that address, and the command "OUT (LOW @DIVA32_+1), HL" sets the value of the U register to the upper 1 byte of the address, sets the address "@DIVA32_+1" to the lower 1 byte, and sets the value of the HL register to the dividend setting register "@DIVA32_+1" indicated by that address. Thus, the 16-bit multiplier is operated and the multiplication result is stored in the multiplication result register.

Next, as shown in FIG. 120, division is waited for (S10), and after a predetermined time has elapsed, the calculation result is read out to the A register (S11), rounded off (S12), and the base value is stored in the main RAM 500c. After setting (S13), the process ends. Specifically, the command "NOP" on the 16th to 19th lines in FIG. , the value of the address indicated by the A register is shifted by 1 bit to the right by the command "SRL A" on the 21st line, and the command "ADC A, 0" on the 22nd line causes the command "SRL If the carry flag is set by "A", that is, if the number after the decimal point is 0.5 or more, 1 is added to the A register, and the command "LD HL, R_ERW_BAS" on the 24th line outputs the address indicating the base value. "R_ERW_BAS" is set in the HL register, and the value of the A register indicating the base value is stored in the address "R_ERW_BAS" by the command "LD (HL), A" on the 25th line.

Here, in this command example, as shown in FIG. 121, the total command size is 49 bytes, and the simple sum of the number of cycles is 68/66 cycles.

As described above, comparing the fifth calculation example for deriving the base value and the sixth calculation example for deriving the base value, both the sum of the command sizes and the simple sum of the number of cycles require 16-bit multiplication. The sixth operation example using a 32-bit divider and a 32-bit divider is smaller. Therefore, when executing the base value in a pachinko machine, it is preferable to use a 16-bit multiplier and a 32-bit divider as described with reference to FIGS.

As described above, according to the present embodiment, by suppressing an increase in the processing load, it is possible to shorten the interval in which timer interrupts are prohibited, and to obtain game information appropriately while stabilizing the operation of the gaming machine. become possible.

In the above-described embodiments, in the fourth operation example and the sixth operation example, the "NOP" that consumes one cycle of time waiting for division by the 32-bit divider is used four times in succession. ing. However, other commands may be used as long as four cycles are secured. For example, a command with a command size of 1 byte and 2 cycles may be used twice consecutively, or a command with a command size of 1 byte and 4 cycles may be used, or a command with a command size of 2 bytes and 4 cycles may be used. Thus, the command size can be reduced.

Further, in the above-described embodiment, the first example of operation using only the 8-bit MUL instruction and the second example of operation using a 16-bit multiplier are given as examples of the operation of executing the payout number of the prize x multiplier. Also, as examples of operations for executing multiplication result/total number of payouts, a third operation example using repeated subtraction of a number multiplied by a power of 2 and a fourth operation example using a 32-bit divider are given. rice field. In the above-described embodiment, after multiplying the number of payouts by the multiplier, the multiplication result is used to execute the multiplication result÷total number of payouts. , or the fourth calculation example. Combinations of such calculation examples can be set arbitrarily. For example, a combination of the first calculation example and the third calculation example, a combination of the first calculation example and the fourth calculation example, a combination of the second calculation example and the third calculation example, a combination of the second calculation example and the third calculation example, A combination of the calculation example and the fourth calculation example can be employed. Further, both the fifth and sixth examples of calculation can be divided into the number of payouts of the prize x multiplier and the result of multiplication/total number of payouts, and the combination of these examples of calculation can be set arbitrarily. For example, a combination of the above-described combination of the number of payouts x multiplier in the fifth example of calculation and the multiplication result÷total number of payouts in the fifth example of calculation, the number of number of payouts x multiplier in the sixth example of calculation, and the sixth In addition to the combination of the multiplication result/total number of payouts in the example of calculation 2, the combination of the number of payouts of the prizes x multiplier in the fifth example of calculation and the combination of the result of multiplication/total number of payouts in the sixth example of calculation, and the sixth calculation It is possible to employ a combination of the number of prizes paid out×multiplier in the example and the multiplication result÷total number of payouts in the fifth calculation example.

Further, in the above-described embodiment, various calculations (first calculation example to fourth calculation example) are executed by taking the role product ratio of the slot machine 400 as an example. Each ratio of the machine 400 (advantageous section ratio, instructed accessory ratio, continuous accessory ratio of 6000 games, accessory ratio of 6000 games, total cumulative continuous accessory ratio, total cumulative accessory ratio, accessory status ratio). In addition, it is applicable not only to the slot machine 400 but also to the base value of a pachinko machine, as explained using the fifth example of calculation and the sixth example of calculation.

<Description of modules and commands>
Hereinafter, specific instruction codes (command groups) for realizing each process (module) described above will be described for each command mainly used in the module.

<Command "ADDALD">
The BYTESEL module is a general-purpose module for byte data selection processing, that is, for offsetting the selected address and reading the 1-byte value stored at the offset address. A general-purpose module is a subroutine of the same processing used to execute a program, and indicates a module that is particularly frequently called from other modules. General-purpose modules are often arranged near the lowest address 0000H on the memory map shown in FIG. 5 (or FIG. 102). This is because by arranging a general-purpose module that is called frequently near 0000H, it can be called using not only the command "CALL" used for calling but also another command "RST". Here, an example in which the BYTESEL module is arranged at 0008H on the memory map will be described.

Here, the command "RST" is a low numerical address in the vicinity of 0000H in the memory map, and any of a plurality of addresses separated by 8 bytes (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H, 0040H). is a command that can invoke The command "RST" has the same execution cycle of "4" as the normal command "CALL" used for calling, but the command size of the normal command "CALL" is "3". command size is "1". Therefore, the program can be shortened by using the command "RST".

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the BYTESEL module as a subroutine in arbitrary processing, and executes the BYTESEL module. The BYTESEL module offsets the selected address by a predetermined value and holds the 1-byte value stored at the offset address. Thus, a value can be set according to the offset.

FIG. 122 is a flow chart showing specific processing of the BYTESEL module. Here, as an arbitrary process, part of the LED_PRC module that executes the LED display setting process shown in S400-31 of FIG. 26 will be described. Numerical values of step S in this figure are used only in the explanation of this figure. Also, in the description of the BYTESEL module, the first register is the HL register and the second register is the A register.

As shown in FIG. 122(a), the main CPU 300a sets an offset in the A register (S1), and sets the top address of the address group to be read in the HL register (S2). Then, the BYTESEL module is called as a subroutine (S3).

As shown in FIG. 122(b), the main CPU 300a updates the HL register by adding the value of the A register to the value of the HL register in the BYTESEL module, and adds the 1-byte value stored at the address indicated by the HL register. is read into the A register (S4). Subsequently, the main CPU 300a sets a zero flag (first zero flag) according to whether the value of the A register is 0 (zero) (S5). Then, the BYTESEL module is terminated and the routine returns to the routine one level above (S6).

123 and 124 are explanatory diagrams for explaining an example of commands for realizing the BYTESEL module. Among them, FIG. 123(a) shows a command group for arbitrary processing to call the BYTESEL module, FIG. 123(b) shows a command group for the BYTESEL module, and FIG. 123(c) shows the program data of the main ROM 300b. shows the arrangement of a 1-byte data group in . The flowchart shown in FIG. 122 is realized by the program shown in FIG. 123, for example.

The command "LDQ A, (LOW R_TZ1_DSP)" on the first line of FIG. Then, the value stored at that address (the counter value of the special symbol 1 display symbol counter) is read to the A register. Such a command on the first line corresponds to step S1 in FIG. 122(a). By the command "LD HL, D_DSP_TZ" on the second line, the top address "D_DSP_TZ" of the data group of the special symbol display LED output data table, which is the read source, is set in the HL register. The command on the second line corresponds to step S2 in FIG. 122(a). Then, the BYTESEL module is called as a subroutine by the command "RST BYTESEL" on the third line. The command on the third line corresponds to step S3 in FIG. 122(a).

The index "BYTESEL:" on the first line in FIG. 123(b) indicates the start address of the BYTESEL module. The command "ADDWB HL, A" on the second line adds the value of the A register to the value of the HL register and updates the value of the HL register. Then, the 1-byte value stored at the address indicated by the HL register is read to the A register by the command "LD A, (HL)" on the third line. The commands on the second and third lines correspond to step S4 in FIG. 122(b). The logical sum of the value of the A register and the value of the A register is calculated by the command "OR A, A" on the fourth line. With such a command "OR A, A", the value of the A register does not change because it is a logical sum of the values of the A register. On the other hand, the OR can change the zero flags (the first zero flag and the second zero flag). That is, in such a BYTESEL module, it is possible to determine whether or not the read value of the A register is zero by the zero flag. The command on the fourth line corresponds to step S5 in FIG. 122(b). Then, the command "RET" on the fifth line returns to the routine one level above. The command on the fifth line corresponds to step S6 in FIG. 122(b).

It should be noted that the table starting from the index "D_DSP_TZ" in FIG. 123(c) shows, for example, information on the special 1 jackpot pattern and the special 2 jackpot pattern. For example, when the variable "R_TZ1_DSP", that is, the counter value of the special symbol 1 display symbol counter is "02H", the table (2AH, A2H, A8H , 36H . can be read. Thus, here, it is possible to acquire a desired 1-byte value in a table in which a plurality of values of the same byte length are consecutively arranged side by side.

The BYTESEL module is called as a subroutine from multiple modules. For example, the SBCMDST module that executes the subcommand group set process shown in step S100-55 of FIG. 23, the LED_PRC module that executes the LED display setting process shown in step S400-31 of FIG. 26, and the step S400-33 of FIG. A SOL_SET module for executing the solenoid data setting process (solenoid output image synthesis process) shown in , and a MEM_DAT module for executing the pending ball number bit data synthesis process, which is a subroutine of the LED display setting process shown in step S400-31 in FIG. , the TDN_PAS module that executes the count switch passage processing (the second starting opening passage processing, the big winning opening passage processing) shown in steps S530 and S540 of FIG. 28, and the special symbol stop symbol display processing shown in step S630 of FIG. TZ_STP module to be executed, TD_OPN module to execute the big winning opening control process shown in step S720 in FIG. 47, normal symbol fluctuation time setting process (normal symbol fluctuation time determination process) shown in step S810-11 in FIG. FSPNTMR module for executing, THPTSEL module for executing special symbol variation pattern determination processing (special symbol variation number determination processing) shown in step S612 of FIG. 39, preliminary area setting processing shown in step S610-17 of FIG. TRSVSEL module, TENDTMR module for executing the ending time setting process shown in step S730-9 in FIG. 48, step S630-13 in FIG. It is called from the ZUGOFFS module that executes processing (not shown), the RGETTCHK module that executes the effect determination processing at the time of acquisition shown in step S536 of FIG. 33, and the like.

In this way, the total command size of the BYTESEL module commands shown in FIG. + 1 byte of the command "OR A, A" on the 4th line + 1 byte of the command "RET" on the 5th line = 4 bytes, and the total execution cycle is 1 cycle on the 2nd line + 2 cycles on the 3rd line + 1 cycle on the 4th line + 5 lines 3 cycles = 7 cycles. By providing such a BYTESEL module, the command "RST BYTESEL" with a command size of 1 byte can be used without performing byte data selection processing in each module described above. It becomes possible to secure the capacity of the control area for performing

FIG. 125 is an explanatory diagram for explaining another example of commands for realizing the BYTESEL module. Here, the command group of the BYTESEL module in FIG. 123(b) is replaced with the command group of the BYTESEL module in FIG. , and the 1-byte data group in the program data of the main ROM 300b in FIG. 123(c) are used as they are in FIGS. 125(a) and 125(c). Here, as shown in FIGS. 125(a) and 125(c), descriptions of processes substantially equivalent to those in FIGS. Only processing will be described.

The index "BYTESEL:" on the first line in FIG. 125(b) indicates the start address of the BYTESEL module. By the command "ADDALD A, (HL)" on the second line, the value of the A register is added to the value of the HL register, and the 1-byte value stored at the address indicated by the HL register after the addition is read out to the A register. . The command on the second line corresponds to step S4 in FIG. 122(b). The logical sum of the value of the A register and the value of the A register is calculated by the command "OR A, A" on the third line. Such a logical sum can change the zero flags (the first zero flag and the second zero flag). That is, in the BYTESEL module, it is possible to determine whether or not the read value of the A register is zero by the zero flag. The command on the third line corresponds to step S5 in FIG. 122(b). Then, the command "RET" on the fourth line returns to the routine one level above. The command on the fourth line corresponds to step S6 in FIG. 122(b).

Here, the command "ADDALD A, (HL)" updates the HL register by adding the value of the A register to the value of the HL register, and reads the value stored at the address indicated by the HL register to the A register. is a command. Such a command has a command size of "1" and an execution cycle of "3".

The total command size of the commands of the BYTESEL module in FIG. RET" 1 byte=3 bytes, and the total execution cycle is 2nd line 3 cycles+3rd line 1 cycle+4th line 3 cycles=7 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte compared to the case of FIG. 123(b). With such a BYTESEL module, it is possible to further shorten commands and secure the capacity of the control area for performing game control processing.

Also, as can be understood by comparing FIG. 123(b) and FIG. 125(b), the command group occupying two lines (second and third lines) in FIG. In b), it can be expressed in one line (second line), which makes it possible to reduce the number of commands and the design load.

FIG. 126 is an explanatory diagram for explaining still another example of commands for realizing the BYTESEL module. Here, the command group for arbitrary processing to call the BYTESEL module in FIG. 125(a) and the command group for the BYTESEL module in FIG. 125(b) are replaced with the command group for arbitrary processing in FIG. 126(a). The other 1-byte data group in the program data of the main ROM 300b shown in FIG. 125(c) is used as it is as shown in FIG. 126(b). Here, as shown in FIG. 126(b), the description of the processing that is substantially the same as that of FIG. 125(c) is omitted, and only the processing different from that of FIG. 126(a) is described.

The command "LDQ A, (LOW R_TZ1_DSP)" on the first line of FIG. , and the value stored at that address is read to the A register. Such a command on the first line corresponds to step S1 in FIG. 122(a). The command "LD HL, D_DSP_TZ" on the second line sets the start address "D_DSP_TZ" of the 1-byte data group to be read from in the HL register. The command on the second line corresponds to step S2 in FIG. 122(a). Then, by the command "ADDALD A, (HL)" on the third line, the value of the A register is added to the value of the HL register, and the 1-byte value stored at the address indicated by the HL register after the addition is stored in the A register. read out. The command on the third line corresponds to step S4 in FIG. 122(b).

In the example of FIG. 126, the command "RST BYTESEL" corresponding to step S3 of FIG. 122(a), the command "OR A, A" corresponding to step S5 of FIG. 122(b), and the command The command "RET" corresponding to step S6 is omitted.

The total command size of the command group for arbitrary processing in FIG. 126(a) is: 1st line command "LDQ A, (LOW R_TZ1_DSP)" 2 bytes + 2nd line command "LD HL, D_DSP_TZ" 3 bytes + 3rd line command "ADDALD A, (HL)" 1 byte = 6 bytes, and the total execution cycle is 1st line 2 cycles + 2nd line 3 cycles + 3rd line 3 cycles = 8 cycles.

On the other hand, the total command size of arbitrary processing and BYTESEL module commands in FIGS. 2 bytes + 2nd line command "LD HL, D_DSP_TZ" 3 bytes + 3rd line command "RST BYTESEL" 1 byte + 2nd line command "ADDALD A, (HL)" 1 byte + 3 lines in Fig. 125(b) 1st command "OR A, A" 1 byte + 4th line command "RET" 1 byte = 9 bytes. 4 cycles+2nd line 3 cycles+3rd line 1 cycle+4th line 3 cycles=16 cycles. Therefore, in the example of FIG. 126, the total command size is reduced by 3 bytes and the total execution cycle is reduced by 8 cycles compared to the case of FIG. By embedding the BYTESEL module itself as a command in any process in this way, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing the game control process. .

Also, as can be understood by comparing FIGS. 125 and 126, the command group occupying four lines (1st to 4th lines) in FIG. 125(b) does not need to be described in FIG. Therefore, it is possible to reduce the number of commands and lighten the design load.

Also, the BYTESEL module is a general-purpose module that is the target of the command "RST", but by omitting such a general-purpose module, a valuable general-purpose module area can be vacated and another module can be placed in that area. . In this way, effective utilization of resources becomes possible.

However, in the example of FIG. 126, omitting the command "OR A, A" makes it impossible to change the first zero flag. That is, it becomes impossible to determine by the first zero flag whether or not the read value of the A register is zero. However, if there is no need to determine whether the value of the A register is zero after the byte data selection process, this function is not required in the first place. Also, the command "ADDALD A, (HL)" can change the second zero flag simply by executing the command. Therefore, when it is necessary to determine whether the value of the A register is zero, it is possible to determine whether the value of the A register is zero by referring to the second zero flag.

Such BYTESEL modules are used not only in pachinko machines but also in slot machines, for example, as modules for executing register addition processing.

<Command "ADDALDW">
The WORDSEL module is a general module for word data selection processing, that is, offsetting the selection address and setting the 2-byte value stored at the offset address. Here, an example in which the WORDSEL module is arranged at 0018H on the memory map will be described.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the WORDSEL module as a subroutine in arbitrary processing, and executes the WORDSEL module. The WORDSEL module offsets the selected address by a predetermined value and holds the 2-byte value stored at the offset address. Thus, a value can be set according to the offset.

FIG. 127 is a flow chart showing specific processing of the WORDSEL module. Here, as arbitrary processing, a part of the FUT_PRC module for executing the normal game management processing shown in step S800 of FIG. 51 will be described. Numerical values of step S in this figure are used only in the explanation of this figure. Also, in the description of the WORDSEL module, the first register is the HL register and the second register is the A register.

As shown in FIG. 127(a), the main CPU 300a sets an offset in the A register (S1), and sets the top address of the address group to be read in the HL register (S2). Then, the WORDSEL module is called as a subroutine (S3).

As shown in FIG. 127(b), in the WORDSEL module, the main CPU 300a doubles the value of the HL register to the value of the A register, or doubles the value of the A register to set the HL register. (S4), and the 2-byte value stored at the address indicated by the HL register is read to the HL register (S5). Subsequently, the main CPU 300a sets the value of the L register to the A register (S6). Then, the WORDSEL module is terminated and the routine returns to the routine one level above (S7).

When the WORDSEL module sets a 2-byte value in the HL register, the main CPU 300a uses the value in the HL register to perform various processes. For example, here, as shown in FIG. 127(a), the address indicated by the HL register is called as a subroutine (S8).

128 and 129 are explanatory diagrams for explaining an example of commands for realizing the WORDSEL module. Among them, FIG. 128(a) shows a command group for arbitrary processing to call the WORDSEL module, FIG. 128(b) shows a command group for the WORDSEL module, and FIG. 128(c) shows the program data of the main ROM 300b. shows the arrangement of 2-byte data groups in . The flowchart shown in FIG. 127 is realized by the program shown in FIG. 128, for example.

The command "LDQ A, (LOW R_FUT_PHS)" on the first line in FIG. , and the value stored at that address is read to the A register. Such a command on the first line corresponds to step S1 in FIG. 127(a). The command "LD HL, J_JMP_FUT" on the second line sets the start address "J_JMP_FUT" of the 2-byte data group to be read from in the HL register. The command on the second line corresponds to step S2 in FIG. 127(a). Then, the WORDSEL module is called as a subroutine by the command "RST WORDSEL" on the third line. The command on the third line corresponds to step S3 in FIG. 127(a).

The index "WORDSEL:" on the first line in FIG. 128(b) indicates the start address of the WORDSEL module. The command "ADDWB HL, A" on the second line adds the value of the A register to the value of the HL register and updates the HL register. Furthermore, the command "ADDWB HL, A" on the third line adds the value of the A register to the value of the HL register to update the HL register. Here, the reason why the value of the A register is added twice to the HL register is that the read source value is a 2-byte value. That is, since data is assigned to the table in units of 2 bytes, it is necessary to offset the address by 2 in order to read the data. Here, by executing the command "ADDWB HL, A" twice, the value of the A register is added twice to the HL register. It can also be realized by using the command "ADD A, A" to pre-double the value of the A register and then adding it to the HL register. The commands on the second and third lines correspond to step S4 in FIG. 127(b).

Then, the 2-byte value stored at the address indicated by the HL register is read to the HL register by the command "LD HL, (HL)" on the fourth line in FIG. 128(b). The command on the fourth line corresponds to step S5 in FIG. 127(b). The command "LD A, L" on the fifth line sets the value of the L register among the HL registers to the A register. Thus, the lower 1 byte of the value of the HL register is set in the A register in advance. The command on the fifth line corresponds to step S6 in FIG. 127(b). Then, the command "RET" on the 6th line returns to the routine one level above. The sixth line command corresponds to step S7 in FIG. 127(b).

It should be noted that the table starting from the index "J_JMP_FUT" in FIG. 128(c) indicates, for example, addresses indicating normal game states. For example, if the variable "R_FUT_PHS", that is, the normal game management phase value is "02H", the table (FZ_STA, FZ_SPN, FZ_STP, FD_PRE, FD_OPN, FD_END), the value stored in the selected address (eg, 1270H) plus the value obtained by doubling the value of the A register (eg, 04H) (5th and 6th addresses from the lowest), here Now 0832H (FZ_STP) can be held in the HL register. Thus, here, it is possible to obtain a desired 2-byte value in a table in which a plurality of values of the same byte length are consecutively arranged side by side.

Here, FZ_STA indicates the address value of normal symbol variation waiting processing shown in step S810 of FIG. 52, FZ_SPN indicates the address value of normal symbol variation processing shown in step S820 of FIG. Indicates the address value of the normal symbol stop symbol display process shown in step S830 of FIG. 54, FD_PRE represents the address value of the normal electric accessory winning opening pre-opening process shown in step S840 of FIG. FD_CLS indicates the address value of the normal electric accessory winning opening control process shown in step S850 of 57, FD_CLS indicates the address value of the normal electric accessory winning opening closing effective process illustrated in step S860 of FIG. 58, and FD_END is , indicates the address value of the normal electric accessory winning opening end wait process shown in step S870 of FIG.

Subsequently, the command "CALL (HL)" on the 4th line in FIG. 128(a) calls the acquired 2-byte value, that is, the address value corresponding to the normal game state. For example, as described above, when 0832H (FZ_STP) is read to the HL register in the table, the address indicated by "FZ_STP" is called by the command "CALL (HL)", and normal symbol stop symbol display processing is executed. becomes. The command on the fourth line corresponds to step S8 in FIG. 127(a).

The WORDSEL module is called as a subroutine from multiple modules. For example, the DBLBYTE module that executes the double byte selection process (not shown) executed in the special symbol stop symbol display process shown in step S630 of FIG. 43, the subcommand transmission shown in step S100-65 of FIG. SBC_OUT module for executing processing, DYM_OUT module for executing dynamic port output processing shown in step S400-5 in FIG. 26, FUT_PRC module for executing normal game management processing shown in step S800 in FIG. 51, step S600 in FIG. TOK_PRC module that executes the special game management process shown in , TDN_PRC module that executes the special electric role product game management process in step S700 of FIG. 44, and STA_PAS that executes the second start opening passage process shown in step S530 of FIG. module, TDN_PAS module for executing count switch passage processing (large winning opening passage processing) shown in step S540 in FIG. 34, TZ_RGET module for executing special symbol random number acquisition processing shown in step S535 in FIG. 32, normal symbol fluctuation time The FSPNTMR module that executes the setting process, the FDNCHG module that executes the normal electric accessory winning opening opening/closing switching process shown in step S841 of FIG. 56, and the special symbol storage area shift process shown in step S610-9 of FIG. TMEMSFT module, THPTSEL module for executing special symbol variation pattern determination processing shown in step S612 of FIG. 39, special symbol variation time setting processing shown in step S610-15 of special symbol variation waiting processing shown in step S610 of FIG. TSPNTM module for executing, TSTATMR module for executing the opening time setting process shown in step S630-15 in FIG. 43, TDNCHG module for executing the big winning opening opening/closing switching process shown in step S711 in FIG. 46, and steps in FIG. The TCLSTMR module that executes the big winning opening closing time setting process shown in S730-7, the TENDTMR module that executes the ending time setting process shown in step S730-9 in FIG. 48, and the variation pattern shown in S612-15 in FIG. HPT_MOD module that executes selection 2 processing (variation pattern number determination processing), HPT_PAT module that executes variation pattern selection 3 processing (variation pattern number determination processing) shown in S612-15 in FIG. 39, step S in FIG. WORDJDG module for executing word data determination processing (not shown) executed in 810-5, RGETTCHK module for executing acquisition effect determination processing shown in step S536 of FIG. 33, step S720-9 of FIG. is called from the TEF_SEL module or the like that executes the big winning opening closing effective time selection process, which is a subroutine of the big winning opening closing effective time setting process shown in .

Thus, the total command size of the commands of the WORDSEL module shown in FIG. 2nd command "LD HL, (HL)" 2 bytes + 5th line command "LD A, L" 1 byte + 6th line command "RET" 1 byte = 6 bytes. Cycle + 3rd row 1 cycle + 4th row 4 cycle + 5th row 1 cycle + 6th row 3 cycle = 10 cycles. By providing such a WORDSEL module, the command "RST WORDSEL" with a command size of 1 byte can be used without performing word data selection processing in each module described above. It becomes possible to secure the capacity of the control area for performing

FIG. 130 is an explanatory diagram for explaining another example of commands for realizing the WORDSEL module. Here, the command group of the WORDSEL module in FIG. 128(b) is replaced with the command group of the WORDSEL module in FIG. , and the 2-byte data group in the program data of the main ROM 300b in FIG. 128(c) are used as they are in FIGS. 130(a) and 130(c). Here, as shown in FIGS. 130(a) and 130(c), descriptions of the processes that are substantially the same as those in FIGS. 128(a) and 128(c) are omitted. Only processing will be described.

The index "WORDSEL:" on the first line in FIG. 130(b) indicates the top address of the WORDSEL module. By the command "ADDALDW HL, (HL)" on the second line, the value of the A register is added twice to the value of the HL register, and the 2-byte value stored at the address indicated by the HL register after the addition is stored in the HL register. read out. The commands on the second line correspond to steps S4 and S5 in FIG. 127(b). The command "LD A, L" on the third line sets the value of the L register of the HL registers to the A register. Thus, the lower 1 byte of the value of the HL register is set in the A register in advance. The command on the third line corresponds to step S6 in FIG. 127(b). Then, the command "RET" on the fourth line returns to the routine one level above. The sixth line command corresponds to step S7 in FIG. 127(b).

Here, the command "ADDALDW HL, (HL)" updates the HL register by adding the value of the A register to the value of the HL register twice, and updates the value stored at the address indicated by the HL register after the addition. This is a command to read to the HL register. Such a command has a command size of "2" and an execution cycle of "6".

Subsequently, the command "CALL (HL)" on the 4th line of FIG. 130(a) calls the acquired 2-byte value, that is, the address value corresponding to the normal game state. The command on the fourth line corresponds to step S8 in FIG. 127(a).

The total command size of the commands of the WORDSEL module in FIG. RET" 1 byte=4 bytes, and the total execution cycle is 2nd line 6 cycles+3rd line 1 cycle+4th line 3 cycles=10 cycles. Therefore, compared with the case of FIG. 128(b), the total command size is reduced by 2 bytes. With such a WORDSEL module, it is possible to further shorten commands and secure the capacity of the control area for performing game control processing.

128(b) and FIG. 130(b), the command group occupying three lines (2nd, 3rd, and 4th lines) in FIG. 130(b) can be expressed in one line (second line), which makes it possible to reduce the number of commands and the design load.

FIG. 131 is an explanatory diagram for explaining still another example of commands for realizing the WORDSEL module. Here, the command group for arbitrary processing to call the WORDSEL module in FIG. 130(a) and the command group for the WORDSEL module in FIG. 130(b) are replaced with the command group for arbitrary processing in FIG. 131(a). The other 2-byte data group in the program data of the main ROM 300b in FIG. 130(c) is used as it is as in FIG. 131(b). Here, as shown in FIG. 131(b), the description of the processing that is substantially the same as that of FIG. 130(c) is omitted, and only the processing that is different from that of FIG. 131(a) is described.

The command "LDQ A, (LOW R_FUT_PHS)" on the first line of FIG. , and the value stored at that address is read to the A register. Such a command on the first line corresponds to step S1 in FIG. 127(a). The second line command "LD HL
, J_JMP_FUT” sets the head address “J_JMP_FUT” of the 1-byte data group to be read from in the HL register. The command on the second line corresponds to step S2 in FIG. 127(a). Then, by the command "ADDALDW HL, (HL)" on the third line, the value of the A register is added twice to the value of the HL register, and the 2-byte value stored at the address indicated by the HL register after addition becomes HL Read out into a register. The command on the third line corresponds to steps S4 and S5 in FIG. 127(b). The command "CALL (HL)" on the fourth line calls the acquired 2-byte value, that is, the address value corresponding to the normal game state. The command on the fourth line corresponds to step S8 in FIG. 127(a).

In the example of FIG. 131, the command "RST WORDSEL" corresponding to step S3 of FIG. 127(a), the command "LD A, L" corresponding to step S6 of FIG. The command "RET" corresponding to step S7 is omitted.

The total command size of arbitrary processing and commands of the WORDSEL module in FIG. 2 bytes of the command "ADDALDW HL, (HL)" on the line + 2 bytes of the command "CALL (HL)" on the 4th line = 9 bytes. 6 cycles + 5 cycles in the 4th row = 16 cycles.

On the other hand, the total command size of arbitrary processing and WORDSEL module commands in FIGS. 2 bytes + 2nd line command "LD HL, J_JMP_FUT" 3 bytes + 3rd line command "RST WORDSEL" 1 byte + 4th line command "CALL (HL)" 2 bytes + 2nd line in Fig. 130(b) Command "ADDALDW HL, (HL)" 2 bytes + 3rd line command "LD A, L" 1 byte + 4th line command "RET" 1 byte = 12 bytes. 1st row 2 cycles+2nd row 3 cycles+3rd row 4 cycles+4th row 5 cycles+2nd row 6 cycles+3rd row 1 cycle+4th row 3 cycles=24 cycles. Therefore, in the example of FIG. 131, the total command size is reduced by 3 bytes and the total execution cycle is reduced by 8 cycles compared to the case of FIG. By embedding the WORDSEL module itself as a command in any process in this way, it is possible to further shorten the command and reduce the processing load, and to secure the capacity of the control area for performing the game control process. .

Also, as can be understood by comparing FIGS. 130 and 131, the command group occupying four lines (1st to 4th lines) in FIG. 130(b) does not need to be described in FIG. Therefore, it is possible to reduce the number of commands and lighten the design load.

Also, the WORDSEL module is a general-purpose module that is the target of the command "RST", but by omitting such a general-purpose module, a valuable area for general-purpose modules can be vacated and other modules can be arranged in that area. . In this way, effective utilization of resources becomes possible.

However, in the example of FIG. 131, the command "LD A, L" is omitted. Therefore, if it is necessary to set the value of the L register to the A register, it is necessary to add the command "LD A, L" separately. However, the command "LD A, L" has a command size of "1" and an execution cycle of "1", so the additional impact of such a command is small.

Note that the WORDSEL module is not only a pachinko machine, but also a slot machine, for example, a CAL_MOD module for executing the state-specific module execution process shown in step S3100-21 in FIG. It is used in the HID_JUG module for executing this precursor start determination process.

FIG. 132 is an explanatory diagram for explaining the CAL_MOD module. The CAL_MOD module shown in FIG. 132 executes state-specific module execution processing, that is, a module corresponding to the state.

At the stage of executing the CAL_MOD module, the offset value is already held in a predetermined register (eg, A register). The index "CAL_MOD:" on the first line in FIG. 132(a) indicates the head address of the CAL_MOD module. The command "LD HL, T_INT_PHASE" on the second line sets the start address "T_INT_PHASE" of the 2-byte data group to be read from in the HL register. The command "ADD A, A" on the third line adds the value of the A register to the value of the A register, doubling the value of the A register. Here, the reason why the value of the A register is doubled is that the read source value is a 2-byte value. That is, since data is assigned to the table in units of 2 bytes, it is necessary to offset the address by 2 in order to read the data. The command "ADDWB HL, A" on the fourth line adds the value of the A register to the value of the HL register and updates the HL register.

Then, the 2-byte value stored at the address indicated by the HL register is read to the HL register by the command "LD HL, (HL)" on the fifth line in FIG. 132(a). The command "JP (HL)" on the sixth line moves to the address indicated by the HL address.

Here, by replacing with the command "ADDALDW", the command group of FIG. 132(a) can be changed as shown in FIG. 132(b). The index "CAL_MOD:" on the first line in FIG. 132(b) indicates the start address of the CAL_MOD module. The command "LD HL, T_INT_PHASE" on the second line sets the start address "T_INT_PHASE" of the 2-byte data group to be read from in the HL register. By the command "ADDALDW HL, (HL)" on the third line, the value of the A register is added twice to the value of the HL register, and the 2-byte value stored at the address indicated by the HL register after the addition is stored in the HL register. read out. Then, the command "JP (HL)" on the fourth line moves to the address indicated by the HL address.

Here, the total command size of the commands of the CAL_MOD module shown in FIG. command "ADDWB HL, A" 1 byte + 5th line command "LD HL, (HL)" 2 bytes + 6th line command "JP (HL)" 2 bytes = 9 bytes, total execution cycle is 2 lines 3rd cycle+3rd line 1st cycle+4th line 1st cycle+5th line 4th cycle+6th line 2nd cycle=11 cycles. On the other hand, the total command size of the commands of the CAL_MOD module shown in FIG. The second command "JP (HL)" 2 bytes=7 bytes, and the total execution cycle is 2nd line 3 cycles+3rd line 6 cycles+4th line 2 cycles=11 cycles. Therefore, by replacing the command group of FIG. 132(a) with the command group of FIG. 132(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 133 is an explanatory diagram for explaining the HID_JUG module. The HID_JUG module shown in FIG. 133 executes this precursor start determination process.

The index "HID_JUG:" on the first line in FIG. 133(a) indicates the head address of the HID_JUG module. By the command "LDQ A, (LOW_NMD_KND)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_NMD_KND" is set as the lower 1 byte of the address, and stored at that address. read the value (normal mode type) to the A register. By the command "LD HL, T_DAT_PGM-2" on the third line, the head address of the 2-byte data group to be read (a value obtained by subtracting 2 from "T_DAT_PGM") is set in the HL register. The command "ADD A, A" on the fourth line adds the value of the A register to the value of the A register, doubling the value of the A register. Here, the reason why the value of the A register is doubled is that the read source value is a 2-byte value. That is, since data is assigned to the table in units of 2 bytes, it is necessary to offset the address by 2 in order to read the data. The command "ADDWB HL, A" on the fifth line adds the value of the A register to the value of the HL register and updates the HL register. Then, the 2-byte value stored at the address indicated by the HL register is read to the HL register by the command "LD HL, (HL)" on the sixth line in FIG. 133(a).

Here, by replacing with the command "ADDALDW", the command group of FIG. 133(a) can be changed as shown in FIG. 133(b). The index "HID_JUG:" on the first line in FIG. 133(b) indicates the start address of the HID_JUG module. By the command "LDQ A, (LOW_NMD_KND)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_NMD_KND" is set as the lower 1 byte of the address, and stored at that address. read the value (normal mode type) to the A register. The command "LD HL, T_DAT_PGM-2" on the third line sets the start address of the 2-byte data group to be read (a value obtained by subtracting 2 from "T_DAT_PGM") in the HL register. By the command "ADDALDW HL, (HL)" on the fourth line, the value of the A register is added twice to the value of the HL register, and the 2-byte value stored at the address indicated by the HL register after the addition is stored in the HL register. read out.

Here, the total command size of the commands of the HID_JUG module shown in FIG. 133(a) is the second line command "LDQ A, (LOW_NMD_KND)" 2 bytes + the third line command "LD HL, T_DAT_PGM-2". 3 bytes + 4th line command "ADD A, A" 1 byte + 5th line command "ADDWB HL, A" 1 byte + 6th line command "LD HL, (HL)" 2 bytes = 9 bytes, total execution The cycle is 2nd row 2 cycles+3rd row 3 cycles+4th row 1 cycle+5th row 1 cycle+6th row 4 cycles=11 cycles. On the other hand, the total command size of the commands of the HID_JUG module shown in FIG. Bytes+4th line command "ADDALDW HL, (HL)" 2 bytes=7 bytes, and the total execution cycle is 2nd line 2 cycles+3rd line 3 cycles+4th line 6 cycles=11 cycles. Therefore, by replacing the command group of FIG. 133(a) with the command group of FIG. 133(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

<Command "INLD", "INLDTQR">
The RAMSET module is a general-purpose module for setting predetermined values (initial values) to variables in the main RAM 300c, that is, RAMSET processing. Here, an example in which the RAMSET module is arranged at 0020H on the memory map will be described.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the RAMSET module as a subroutine in arbitrary processing, and executes the RAMSET module. The RAMSET module transfers a plurality of 1-byte values described in the program data of the main ROM 300b to an area holding a plurality of data treated as variables in the work area of the main RAM 300c. Thus, the values of multiple variables are set. Here, the number of data to be transferred is simply called the number of data.

FIG. 134 is a flow chart showing specific processing of the RAMSET module. Here, as arbitrary processing, a part of the CPUINIT module that executes the CPU initialization processing shown in step S100 of FIG. 22 will be described. Numerical values of step S in this figure are used only in the explanation of this figure. Also, during the description of the RAMSET module, the first register is the B register, the second register is the HL register, the first value is "1" and the second value is "2". It goes without saying that the first value and the second value can be arbitrarily set.

As shown in FIG. 134(a), the main CPU 300a sets the start address of the 1-byte data group to be the transfer source in the HL register in arbitrary processing (S1). Then, the RAMSET module is called as a subroutine (S2).

As shown in FIG. 134(b), the main CPU 300a reads the 1-byte value stored at the address indicated by the HL register in the RAMSET module to the B register (S3). This 1-byte value indicates the number of data. Subsequently, the main CPU 300a adds "2" to the HL register to the address specified by the value stored in the address indicated by adding "1" to the HL register. 2 is added to the value of the HL register to set the next transfer address (S4). Subsequently, the main CPU 300a decrements the value of the B register (subtracts "1") and determines whether or not the result of the decrement is 0 (S5). Here, if the decremented result is not 0 (NO in S5), the processing from step S4 is repeated, and if the decremented result is 0 (YES in S5), the RAMSET module is terminated and Return to routine (S6).

135 and 136 are explanatory diagrams for explaining an example of commands for realizing the RAMSET module. Among them, FIG. 135(a) shows a command group for arbitrary processing to call the RAMSET module, FIG. 135(b) shows a command group for the RAMSET module, and FIG. 135(c) shows the program data of the main ROM 300b. 135(d) shows the arrangement of a 1-byte data group in the work area of the main RAM 300c. The flowchart shown in FIG. 134 is realized by the program shown in FIG. 135, for example.

The command "LD HL, D_RAM_RST_INI" on the first line in FIG. 135(a) sets the start address "D_RAM_RST_INI" of the 1-byte data group to be the transfer source in the HL register. Such a command on the first line corresponds to step S1 in FIG. 134(a). Then, the RAMSET module is called as a subroutine by the command "RST RAMSET" on the second line. The command on the second line corresponds to step S2 in FIG. 134(a).

The index "RAMSET:" on the first line in FIG. 135(b) indicates the start address of the RAMSET module. The 1-byte value stored at the address indicated by the HL register is read to the B register by the command "LD B, (HL)" on the second line. At this time, the address "D_RAM_RST_INI" is set in the HL register as shown in FIG. 135(a). Therefore, the 1-byte value "(@D_RAM_RST_INI-D_RAM_RST_INI-1)/2" on the second line in FIG. 135(c) is read to the B register as the number of data (the number of repetitions of transfer). Note that "@D_RAM_RST_INI" is the address next to the last address of the transfer source 1-byte data group, and D_RAM_RST_INI is the start address of the transfer source 1-byte data group, so the value of @D_RAM_RST_INI-D_RAM_RST_INI-1 A 1-byte value indicating the number of data) is the total number of bytes of the 1-byte value, and the number of data is derived by dividing this value by 2, which is the number of combinations of addresses and values. In the example of FIG. 135(c), the number of data is (11-1)/2=5. The command on the second line in FIG. 135(c) corresponds to step S3 in FIG. 134(b).

The index “RAMSET — 10:” on the third line in FIG. 135(b) indicates the start address of the repeated processing. By the command "INLD AC, (HL)" on the 4th line and the command "LDQ (C), A" on the 5th line, it is specified by the value stored at the address indicated by adding "1" to the HL register. The value stored at the address indicated by the value obtained by adding "2" to the HL register is stored in the address to be transferred, and "2" is added to the value of the HL register to set the next transfer address. The commands on the 4th and 5th lines correspond to step S4 in FIG. 134(b).

Here, the command "INLD AC, (HL)" stores the value stored at the address indicated by the value obtained by adding "1" to the HL register in the C register, and stores the value obtained by adding "2" to the HL register. This command stores the value stored at the address indicated by , in the A register, adds "2" to the value of the HL register, and updates the value of the HL register. Such a command has a command size of "2" and an execution cycle of "4".

For example, if the HL register has the value of the address "D_RAM_RST_INI", the lower 1-byte value of the 2-byte variable "R_TZ1_STP" in the third line of FIG. 135(c) is stored in the C register, and The value of "@DSP_HAZ" in the third line is stored in the A register.

The command "LDQ (C), A" on the 5th line in FIG. , A command to store the value of the A register. Such a command has a command size of "2" and an execution cycle of "3".

For example, the value of the C register, that is, the value of the lower 1 byte of "R_TZ1_STP" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "@DSP_HAZ" is stored at that address.

Here, in FIGS. 135(c) and 135(d), the variable "R_TZ1_STP" indicates the special symbol 1 stop symbol number, the variable "R_TZ2_STP" indicates the special symbol 2 stop symbol number, and the variable "R_TZ1_DSP". indicates the counter value of the special symbol 1 display symbol counter, the variable "R_TZ2_DSP" indicates the counter value of the special symbol 2 display symbol counter, and the variable "R_EXT_SEC_TMR" indicates the security external signal timer value. Note that the arrangement of variables shown in FIG. 135(d) does not have to be continuous as shown, and may be separated.

Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ RAMSET_10" on the 6th line of FIG. , if the decremented result is 0, the process is shifted to the command following the command. Here, since the number of data is "5", the value of the B register becomes 0 when the processing from "RAMSET_10" is repeated five times. The sixth line command corresponds to step S5 in FIG. 134(b). Then, the command "RET" on the 7th line returns to the routine one level above. The command on the seventh line corresponds to step S6 in FIG. 134(b).

Thus, as shown in FIG. 136, a plurality of 1-byte values (55H, 77H, 66H, 22H, AAH) described in the program data of the main ROM 300b are converted to variables ("R_TZ1_STP", "R_TZ2_STP") in the work area of the main RAM 300c. , "R_TZ1_DSP", "R_TZ2_DSP", and "R_EXT_SEC_TMR").

The RAMSET module is called as a subroutine from multiple modules. For example, the CPUINIT module for executing the CPU initialization process shown in step S100 in FIG. 22, the SEC_SET module for executing security setting process, and the state management process (error management process) shown in step S400-21 in FIG. STC_PRC module, FZ_STA module for executing normal symbol variation waiting process shown in step S810 of FIG. 52, FZ_SPN module for executing normal symbol variation process shown in step S820 of FIG. FZ_STP module for executing symbol stop symbol display processing, FD_PRE module for executing normal electric accessory winning opening pre-opening process shown in step S840 in FIG. 55, normal electric accessory winning opening opening control shown in step S850 in FIG. FD_OPN module that executes the process, TZ_STA module that executes the special symbol variation waiting process shown in step S610 of FIG. 37, TZ_SPN module that executes the special symbol variation process shown in step S620 of FIG. 41, step S630 of FIG. The TZ_STP module that executes the special symbol stop symbol display process shown in , the TD_PRE module that executes the big winning opening pre-opening process shown in step S710 of FIG. 45, and the big winning opening opening control process shown in step S720 of FIG. TD_OPN module to be executed, TD_EFF module to execute the big winning opening closing effective process shown in step S730 of FIG. 48, TD_END module to execute the big winning opening end wait process shown in step S740 of FIG. 49, step S630 of FIG. TOKZERO module that executes the special symbol variation waiting state transition processing (not shown) executed in, CHGSTS module that executes the number cutting management processing shown in step S613 of FIG. 40, shown in step S450 of FIG. It is called from the RNK_PRC module or the like that executes setting-related processing.

Thus, the total command size of the commands of the RAMSET module shown in FIG. 135(b) is the command "LD B, (HL)" on the second line + 1 byte + the command "INLD AC, (HL)" on the fourth line. 2 bytes + 5th line command "LDQ (C), A" 2 bytes + 6th line command "DJNZ RAMSET_10" 2 bytes + 7th line command "RET" 1 byte = 8 bytes, total execution cycle is 2 lines 2nd cycle + 4th row 4th cycle + 5th row 3rd cycle + 6th row 3rd cycle (or 2 cycles) + 7th row 3rd cycle = 15 cycles (or 14 cycles). The number of cycles in parentheses indicates the number of execution cycles when no movement is performed by the command "DJNZ RAMSET_10". By providing such a RAMSET module, the command "RST RAMSET" with a command size of 1 byte can be used without performing the RAMSET processing in each module described above. It becomes possible to secure the capacity of the control area for performing the processing.

FIG. 137 is an explanatory diagram for explaining another example of commands for realizing the RAMSET module. Here, the command group of the RAMSET module in FIG. 135(b) is replaced with the command group of the RAMSET module in FIG. , the 1-byte data group in the program data of the main ROM 300b in FIG. 135(c) and the 1-byte data group in the work area of the main RAM 300c in FIG. It is used as it is as FIG. 137(d). Here, as shown in FIGS. 137(a), 137(c), and 137(d), the processes substantially equivalent to those in FIGS. 135(a), 135(c), and 135(d) are Description is omitted, and only the different processing in FIG. 137(b) will be described.

The index "RAMSET:" on the first line in FIG. 137(b) indicates the top address of the RAMSET module. The 1-byte value stored at the address indicated by the HL register is read to the B register by the command "LD B, (HL)" on the second line. At this time, the address "D_RAM_RST_INI" is set in the HL register as shown in FIG. 137(a). Therefore, the 1-byte value "(@D_RAM_RST_INI-D_RAM_RST_INI-1)/2" on the second line in FIG. 137(c) is read to the B register as the number of data. The command on the second line in FIG. 137(b) corresponds to step S3 in FIG. 134(b).

By the command "INLDTQRAC, (HL)" on the third line of FIG. 137(b), the The value stored at the address indicated by adding "2" is transferred, the next transfer address is set by adding "2" to the value of the HL register, and the value of the B register is decremented ("1"). subtraction), and the process is repeated until the decremented result becomes zero. Such commands on the third line correspond to steps S4 and S5 in FIG. 134(b).

Here, the command "INLDTQRAC, (HL)" sets the value of the Q register to the upper 1 byte of the address, and sets the value stored at the address indicated by adding "1" to the HL register to the lower 1 byte of the address. byte, and transfer the value stored at the address indicated by the value of the HL register plus "2" to that address, add "2" to the value of the HL register to update the value of the HL register, and This command decrements the value of the register (subtracts "1") and repeats the transfer of the value until the decremented result becomes 0. Such a command has a command size of "2" and an execution cycle of "5".

For example, when the HL register has the value of the address "D_RAM_RST_INI", the value of the Q register is the upper 1 byte of the address, and the lower 1 byte of "R_TZ1_STP" in the third line of FIG. 137(c), the value of "@DSP_HAZ" in the third line of FIG. " is subtracted), and the transfer is repeated until the decremented result becomes 0, that is, five times.

Then, the command "RET" on the fourth line in FIG. 137(b) returns to the routine one level above. The command on the fourth line corresponds to step S6 in FIG. 134(b).

The total command size of the commands of the RAMSET module in FIG. 1 byte of the command "RET"=4 bytes, and the total execution cycle is 2 cycles on the 2nd line+5 cycles on the 3rd line+3 cycles on the 4th line=10 cycles. Therefore, compared with the case of FIG. 135(b), the total command size is reduced by 4 bytes, and the total execution cycle is also reduced by at least 4 cycles. In particular, in the example of FIG. 135(b), if the value of the B register in the command "DJNZ RAMSET_10" is 2 or more, then 10 cycles (4th line 4 cycles + 5th line 3 cycles + 6th line 3 cycles) Since the total execution cycle increases by the amount multiplied by , the amount of reduction in the total execution cycle in FIG. 137(b) also increases. With such a RAMSET module, it is possible to further shorten commands, reduce processing load, and secure the capacity of the control area for performing game control processing.

Also, unlike the example in FIG. 135, the A and C registers are not used here. Therefore, the value of the A register and the value of the C register are not unintentionally updated. Also, in the example of FIG. 135, if the A and C registers were already in use, it was necessary to stack and save the values of the A and C registers. No stack processing is required. In this way, it becomes possible to effectively use resources.

135(b) and FIG. 137(b), the command group that occupied four lines (third to sixth lines) in FIG. 135(b) is 137(b) can be expressed in one line (the third line), which makes it possible to reduce the number of commands themselves and the design load.

This RAMSET module is used not only in pachinko machines but also in slot machines as a TABLESET module (general-purpose module) for executing table setting processing for setting predetermined values (initial values) to variables in the main RAM 500c. ing.

FIG. 138 is an explanatory diagram for explaining an example of commands for realizing the TABLESET module. Among them, FIG. 138(a) shows a command group for arbitrary processing to call the TBLSET module, FIG. 138(b) shows a command group for the TBLSET module, and FIG. 138(c) shows the program data of the main ROM 500b. 138(d) shows the arrangement of a 1-byte data group in the work area of the main RAM 500c.

Here, as arbitrary processing, the error wait processing shown in step S2200-11 of FIG. 89 and step S2800-39 of FIG. some are mentioned.

The command "LD HL, T_ERR_RCV" on the first line in FIG. 138(a) sets the start address "T_ERR_RCV" of the 1-byte data group to be the transfer source in the HL register. Then, the command "RST TABLET" on the second line calls the TABLET module as a subroutine.

The index "TABLSET:" on the first line in FIG. 138(b) indicates the top address of the TBLSET module. The value of the BC register is saved in the stack area by the command "PUSH BC" on the second line. Interrupts are disabled by the command "DI" on the third line.

The 1-byte value stored at the address indicated by the HL register is read to the B register by the command "LD B, (HL)" on the fourth line in FIG. 138(b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 138(a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" on the second line in FIG. 138(c) is read out to the B register as the number of data (number of repetitions of transfer). Note that "T_ERR_RCV_" is the address next to the last address of the transfer source 1-byte data group, and T_ERR_RCV is the start address of the transfer source 1-byte data group. 1-byte value) is the total number of bytes of the 1-byte value, and the number of data is derived by dividing that value by 2, which is the number of combinations of addresses and values. In the example of FIG. 138(c), the number of data is 9/2=4.

The index "TABLSET10:" on the fifth line in FIG. 138(b) indicates the start address of the repeated processing. Specified by the value stored at the address indicated by the HL register plus "1" by the command "INLD AC, (HL)" on the 6th line and the command "LDQ (C), A" on the 7th line. The value stored at the address indicated by the value obtained by adding "2" to the HL register is stored in the address to be transferred, and "2" is added to the value of the HL register to set the next transfer address.

For example, if the HL register has the value of the address "T_ERR_RCV", the lower 1-byte value of the 2-byte variable "_ERR_NUM" in the third line of FIG. 138(c) is stored in the C register, and A value of "0" in the third row is stored in the A register.

The command "LDQ (C), A" on the 7th line in FIG. , A command to store the value of the A register.

For example, the value of the C register, that is, the value of the lower 1 byte of "_ERR_NUM" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "0" is stored at that address.

Here, in FIGS. 138(c) and 138(d), the variable "_ERR_NUM" indicates an error number, the variable "_CRE_TMR" indicates a credit button detection timer, and the variable "_CRE_FLG" indicates a credit button detection flag. , and the variable “_SNS_OLD” indicates the previous medal passing sensor bit state. Note that the arrangement of variables shown in FIG. 138(d) does not have to be continuous as shown, and may be separated.

Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ TABLESET10" on the eighth line in FIG. , if the decremented result is 0, the process is shifted to the command following the command. Here, since the number of data is "4", the value of the B register becomes 0 when the processing from "TABLSET10" is repeated four times.

The interrupt is enabled by the command "EI" on the ninth line of FIG. 138(b). The data saved in the stack area by the command "POP BC" on the 10th line is restored to the BC register. Then, the command "RET" on the 11th line returns to the routine one level above.

Here, if the command "INLDTQR" is replaced, the command group can be described as follows.

FIG. 139 is an explanatory diagram for explaining another example of commands for realizing the TABLESET module. Here, the command group of the TBLSET module in FIG. 138(b) is replaced with the command group of the TBLSET module in FIG. 139(a) and 139(c). , is used as it is as FIG. 139(d). Here, as shown in FIGS. 139(a), 139(c), and 139(d), the processes substantially equivalent to those in FIGS. 138(a), 138(c), and 138(d) are Explanation is omitted, and only the different processing in FIG. 139(b) is explained.

The index "TABLSET:" on the first line in FIG. 139(b) indicates the head address of the TBLSET module. The value of the BC register is saved in the stack area by the command "PUSH BC" on the second line. Interrupts are disabled by the command "DI" on the third line.

The 1-byte value stored at the address indicated by the HL register is read to the B register by the command "LD B, (HL)" on the fourth line in FIG. 139(b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 139(a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" on the second line in FIG. 139(c) is read out to the B register as the number of data (number of repetitions of transfer). In the example of FIG. 139(c), the number of data is four.

By the command "INLDTQR (HL)" on the fifth line in FIG. 139(b), "2" " is added to the value stored in the address indicated by the value added, "2" is added to the value of the HL register to set the next address to be transferred, and the value of the B register is decremented (subtracted by "1"). This process is repeated until the decremented result becomes zero.

Subsequently, the interrupt is permitted by the command "EI" on line 6 of FIG. 139(b). The data saved in the stack area by the command "POP BC" on the 7th line is restored to the BC register. Then, the command "RET" on the eighth line returns to the routine one level above.

Here, the total command size of the commands of the TABLESET module shown in FIG. , (HL)” 1 byte + 6th line command “INLD AC, (HL)” 2 bytes + 7th line command “LDQ (C), A” 2 bytes + 8th line command “DJNZ TABLESET10” 2 bytes + 9th line 1st command "EI" 1 byte + 10th line command "POP BC" 1 byte + 11th line command "RET" 1 byte = 12 bytes, the total execution cycle is 2nd line 3 cycles + 3rd line 1 cycle + 4 Row 2 cycles+6th row 4 cycles+7th row 3 cycles+8th row 3 cycles (or 2 cycles)+9th row 1 cycle+10th row 3 cycles+11th row 3 cycles=23 cycles (or 22 cycles). On the other hand, the total command size of the commands of the TABLESET module shown in FIG. (HL)" 1 byte + 5th line command "INLDTQR (HL)" 2 bytes + 6th line command "EI" 1 byte + 7th line command "POP BC" 1 byte + 8th line command "RET" 1 byte = 8 bytes, and the total execution cycle is: 2nd line 3 cycles + 3rd line 1 cycle + 4th line 2 cycles + 5th line 5 cycles + 6th line 1 cycle + 7th line 3 cycles + 8th line 3 cycles = 18 cycles . Therefore, compared with the case of FIG. 138(b), the total command size is reduced by 4 bytes, and the total execution cycle is also reduced by at least 5 cycles. In particular, in the example of FIG. 138(b), if the value of the B register in the command "DJNZ TABLESET10" is 2 or more, then 10 cycles (6th line 4 cycles + 7th line 3 cycles + 8th line 3 cycles) Since the total execution cycle increases by the amount multiplied by , the amount of reduction in the total execution cycle in FIG. 139(b) also increases. With such a TABLESET module, it is possible to shorten commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

Also, unlike the example in FIG. 138, the A and C registers are not used here. Therefore, the value of the A register and the value of the C register are not unintentionally updated. Also, in the example of FIG. 138, if the A and C registers were already used, it was necessary to stack and save the values of the A and C registers. No stack processing is required. In this way, it becomes possible to effectively use resources.

Also, as can be understood by comparing FIG. 138(b) and FIG. 139(b), the command group occupying four lines (5th to 8th lines) in FIG. 139(b) can be expressed in one line (fifth line), which makes it possible to reduce the number of commands themselves and the design load.

The TABLESET module is called as a subroutine not only by the ERRWAIT module but also by a plurality of modules. For example, the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 selectively shifts according to the game state and the effect state, and executes the present precursor process (AT state=“3”). and the EXE_SET module for executing the execution flag setting process shown in step S2400-11 in FIG. , and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ), and the EXE_SET module for executing the execution flag setting process shown in step S2400-11 in FIG. ”), and the EXE_SET module for executing the execution flag setting process shown in step S2400-11 in FIG. 7”), the RANKSET module for executing the set value switching process shown in step S2020 in FIG. 85, the FGSETUP module for executing the symbol code setting process shown in step S2400 in FIG. 91, and step S2900 in FIG. is called from the GAMESET module that executes the game transition processing shown in , the JCGMSET module that executes the role product operation symbol display processing shown in step S2900-3 of FIG. 96, and the like.

<Command "DECM", "DECWM">
The BYTEDEC module is a general-purpose module for byte counter subtraction processing, that is, for decrementing the 1-byte variable of the main RAM 300c by one. The BYTEDEC module not only decrements, but also sets a zero flag and a carry flag as a result of decrementing.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the BYTEDEC module as a subroutine in arbitrary processing, and executes the BYTEDEC module. The BYTEDEC module decrements the 1-byte value held in the main RAM 300c.

FIG. 140 is a flow chart showing specific processing of the BYTEDEC module. Here, as an arbitrary process, a part of the TZ_STP module that executes the special symbol stop symbol display process shown in step S630 of FIG. 43 will be described. Numerical values of step S in this figure are used only in the explanation of this figure. Also, in the description of the BYTEDEC module, the predetermined register is the HL register.

The main CPU 300a executes arbitrary processing as shown in FIG. 140(a). The main CPU 300a first sets the address of the variable to be decremented in the HL register (S1). Then, the BYTEDEC module is called as a subroutine (S2).

As shown in FIG. 140(b), the main CPU 300a decrements by 1 the 1-byte value stored at the address indicated by the HL register in the BYTEDEC module and sets the zero flag and carry flag (S3). Then, the BYTEDEC module is finished, and the process returns to the routine one level above (S4). The decrement mode and flag setting will be described in detail below.

FIG. 141 is an explanatory diagram for explaining the decrement mode and setting of the zero flag and carry flag in the BYTEDEC module. Here, if the value before decrementation is 1 or more (1 or 2 or more), the value is decremented by 1 after decrementation. However, if it was 0 before decrementation, it becomes 0 after decrementation instead of -1. That is, the lower limit value is 0 and never becomes a negative value. Such maintenance of 0 can be realized by decrementing and then incrementing the value when it was 0 before decrementing, by forcibly reading 0, or by not performing decrementation.

If the value before decrementation is 2 or more, the value after decrementation is 1 or more, so the zero flag is not set and the value becomes 0. However, if the value before decrementation is 1 or 0, the value becomes 0 after decrementation, so the zero flag is set. becomes 1. In the BYTEDEC module, if the value is 1 before decrementing, it becomes 0 after decrementing. If the value before decrement is 2 or more or 0, the carry flag is set to 0 without raising the carry flag.

Returning to FIG. 140(a), when the BYTEDEC module sets the zero flag and the carry flag, the main CPU 300a uses the flag values to perform various processes. For example, here, it is determined that the decrement is not the process of subtracting 1 to 0 (S5), and as a result, if it is not the process of subtracting 1 to 0 (YES in S5), a special symbol hit Move to a predetermined address (TZ_STP_10) for flag check processing (S6), and if the processing is to subtract 1 to 0 (NO in S5), perform the next processing without moving.

FIG. 142 is an explanatory diagram for explaining an example of commands for realizing the BYTEDEC module. Among them, FIG. 142(a) shows a command group of arbitrary processing to call the BYTEDEC module, and FIG. 142(b) shows a command group of the BYTEDEC module. The flowchart shown in FIG. 140 is realized by the program shown in FIG. 142, for example.

By the command "LDQ HL, LOW R_EXT_HCT" on the first line in FIG. 142(a), the value of the Q register is read to the H register, and the value of the lower 1 byte of the address "R_EXT_HCT" is read to the L register. The command on the first line corresponds to step S1 in FIG. 140(a). Then, the BYTEDEC module is called as a subroutine by the command "CALLF BYTEDEC" on the second line. The command on the second line corresponds to step S2 in FIG. 140(a).

Here, the command "CALLF BYTEDEC" is a command that can call only the range from 0000H to 11FFH in the memory map. The command "CALLF" used for calling has the same execution cycle as the normal command "CALL", which is "4". The command size is "2". Therefore, the program can be shortened. Instead of the command "CALLF BYTEDEC", the BYTEDEC module may be called by "RST BYTEDEC" similar to the general-purpose module described above. By doing so, the command size can be set to "1".

The index "BYTEDEC:" on the first line in FIG. 142(b) indicates the top address of the BYTEDEC module. The 1-byte value stored at the address indicated by the HL register is read to the A register by the command "LD A, (HL)" on the second line. Execution of such a command "LD A, (HL)" changes the second zero flag. Then, if the value of the A register is 0 (if the second zero flag is 1) according to the command "RT Z, A" on the third line, the process returns to the routine one step above. At this time, if the value of the A register is 0, the command "RT Z, A" sets the zero flag (first zero flag) to 1 and the carry flag to 0. Thus, if the value stored at the address indicated by the HL register is 0, zero flag=1 and carry flag=0 can be set without decrementing.

The value of the A register is compared with 2 by the command "CP A, 2" on the fourth line in FIG. 142(b). , the carry flag is set to 1. Note that the command "CP A, 2" is a command in which the carry flag is set when the value of the A register is less than 2, but at the stage of execution of the command "CP A, 2", the value of the A register is 1 or 2 or more. (because it is not 0), by setting the carry flag when less than 2, the carry flag is set when the value is 1 as a result. Thus, if the value of the A register is 1, the carry flag can be set to 1. The command "DEC (HL)" on the fifth line decrements the 1-byte value stored at the address indicated by the HL register by 1 to update the value stored at the address indicated by the HL register. Here, if the value stored at the address indicated by the HL register is 2 or more, the decremented value is 1 or more. The zero flag is set to 1. The carry flag does not change depending on the command "DEC (HL)". Thus, if the value stored at the address indicated by the HL register is 2 or more, zero flag=0 and carry flag=0, and if it is 1, zero flag=1 and carry flag=1. The commands on the second to fifth lines correspond to step S3 in FIG. 140(b). Then, the command "RET" on the sixth line returns to the routine one level above. The sixth line command corresponds to step S4 in FIG. 140(b). Thus, the value stored at the address indicated by the HL register can be decremented by 1 and the zero flag and carry flag can be set.

Subsequently, if the carry flag is 0 (NC) by the command "JR NC, TZ_STP_10" on the third line in FIG. 142(a), the process moves to TZ_STP_10. The command on the third line corresponds to steps S5 and S6 in FIG. 140(a). This allows processing based on the results of the BYTEDEC module.

The BYTEDEC module is called as a subroutine from multiple modules. For example, the TMR_NEW module that executes the timer update processing shown in step S400-15 of FIG. 26, the STC_PRC module that executes the state management processing (error management processing) shown in step S400-21 of FIG. 26, and step S630 of FIG. The TZ_STP module that executes the special symbol stop symbol display process shown in , the CHGSTS module that executes the number cutting management process shown in step S613 of FIG. 40, the count switch passage process shown in step S540 of FIG. processing), the TDOVCHK module that executes the large winning opening excessive winning monitoring process executed after setting the large winning opening ball entry command (S540-3), the state management process (error management processing ), which is a subroutine of BER_CHK module for executing the base abnormality error monitoring process.

In this way, the total command size of the commands of the BYTEDEC module shown in FIG. + 2 bytes of the command "CP A, 2" on the 4th line + 1 byte of the command "DEC (HL)" on the 5th line + 1 byte of the command "RET" on the 6th line = 6 bytes. Cycle+3rd row 4 cycles (or 2 cycles)+4th row 2 cycles+5th row 4 cycles+6th row 3 cycles=15 cycles (or 13 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RT Z, A" does not move to the routine one level above. By providing such a BYTEDEC module, the command "CALLF BYTEDEC" with a command size of 2 bytes can be used without performing the byte counter subtraction processing in each module described above, so the command can be shortened and the game control processing It becomes possible to secure the capacity of the control area for performing

FIG. 143 is an explanatory diagram for explaining another example of commands for realizing the BYTEDEC module. Here, the command group of the BYTEDEC module in FIG. 142(b) is replaced with the command group of the BYTEDEC module in FIG. is used as it is as FIG. 143(a). Here, as shown in FIG. 143(a), the description of the processing that is substantially the same as in FIG. 142(a) is omitted, and only the different processing in FIG. 143(b) is described.

The index "BYTEDEC:" on the first line in FIG. 143(b) indicates the head address of the BYTEDEC module. If the value stored at the address indicated by the HL register is 1 or more, the value stored at the address indicated by the HL register is decremented by 1, and if it is 0, 0 is maintained by the command "DECM (HL)" on the second line.

Here, the command "DECM (HL)" decrements the 1-byte value stored at the address indicated by the HL register, and if the carry flag is set (-1), the address indicated by the HL register This command forces 0 to be stored in the 1-byte value stored in . Then, if the value stored at the address indicated by the HL register is 1 or more, it is decremented by 1, and if it is 0, 0 is maintained. By executing the command "DECM (HL)", if the value after decrementation is zero (if the value before decrementation is 1 or 0), zero flags (first zero flag and second zero flag) are set. If the value before decrement is zero, the carry flag is set and the value is set to one. Such a command has a command size of "2" and an execution cycle of "5".

If the zero flag is not 1 (the value after decrementation is not zero) by the command "RET NZ" on the third line in FIG. Here, since decrementation has already been performed by the command "DECM (HL)", the fact that the zero flag is not 1 indicates that the value before decrementation is 2 or more. In this case, the zero flag is not set to 0 and the carry flag is not set to 0, so the routine may be returned to the routine one step above. Here, "NZ" is mentioned and the first zero flag is referred to. Normally, when the first zero flag is changed, the second zero flag is also changed. "NTZ" can be used instead.

In the command "DECM (HL)", if the value stored in the address indicated by the HL register before decrementing is 1, it becomes 0 after decrementing, and the zero flag=1 and the carry flag=0. If there is, it is not decremented and is maintained at 0, with zero flag=1 and carry flag=1. That is, the specification of the carry flag is opposite to that shown in FIG. Therefore, the carry flag is inverted (1→0, 0→1) by the command "CCF" on the fourth line in FIG. 143(b). Note that the zero flag does not change depending on the command "CCF". Thus, if the value stored at the address indicated by the HL register before decrementing is 1, zero flag=0 and carry flag=1, and if it is 0, zero flag=1 and carry flag=0. . The commands on the second to fourth lines correspond to step S3 in FIG. 140(b). Then, the command "RET" on the fifth line returns to the routine one level above. The command on the fifth line corresponds to step S4 in FIG. 140(b). Thus, the value stored at the address indicated by the HL register can be decremented by 1 and the zero flag and carry flag can be set.

Subsequently, if the carry flag is 0 (NC) by the command "JR NC, TZ_STP_10" on the third line in FIG. 143(a), the process moves to TZ_STP_10. The command on the third line corresponds to steps S5 and S6 in FIG. 140(a). This allows processing based on the results of the BYTEDEC module.

The total command size of the commands of the BYTEDEC module in FIG. 143(b) is 2 bytes of the command "DECM (HL)" on the second line + 1 byte of the command "RET NZ" on the third line + 2 bytes of the command "CCF" on the fourth line. + 1 byte of the command "RET" on the 5th line = 6 bytes. ). The number of cycles in parentheses indicates the execution cycle when the command "RET NZ" does not move to the routine one level above. Therefore, the total execution cycle is reduced by at least 2 cycles compared to the case of FIG. 142(b). With such a BYTEDEC module, it is possible to secure the capacity of the control area for performing the game control process while reducing the processing load.

Also, unlike the example in FIG. 142, the A register is not used here. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 142, if the A register has already been used, it was necessary to stack and save the value of the A register. In this way, it becomes possible to effectively use resources.

142(b) and FIG. 143(b), the command group occupying four lines (second to fifth lines) in FIG. 143(b) can be expressed in three lines (2nd to 4th lines), which makes it possible to reduce the number of commands and the design load.

The BYTEDEC module is not only used in pachinko machines, but also in slot machines. Then, the REG_LOT module that executes the REG process (AT state=“6”) and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. BIG_LOT module that shifts and executes BIG intermediate processing (AT state = "7"), JCGMSET module that executes the role product operating symbol display processing shown in step S2900-3 in Fig. 96, and JCGMSET module shown in step S3100 in Fig. 98 In the TMR_IPT module for executing timer interrupt processing and the CAL_MOD module for executing state-specific module execution processing shown in step S3100-21 in FIG. times (every 5.96 msec), the IPT_PA module for executing the terminal board output control process, and the CAL_MOD module for executing the status-specific module execution process shown in step S3100-21 in FIG. An IPT_PC module that selectively shifts once every four times (every 5.96 msec) according to the interrupt processing phase (0 to 3) and executes time monitoring processing, and the IPT_PC module shown in step S3100-21 in FIG. In the CAL_MOD module for executing the state-specific module execution processing, it selectively shifts once every four times (every 5.96 msec) according to the timer interrupt processing phase (0 to 3), and external signal output control It is used as a RAM_DEC module (general-purpose module) that executes counter subtraction processing called by the command "RST" from the IPT_PD module that executes processing.

FIG. 144 is an explanatory diagram for explaining the RAM_DEC module. The RAM_DEC module shown in FIG. 144 is a general-purpose module for counter subtraction processing, that is, for decrementing the 1-byte variable of the main RAM 500c by 1, like the BYTEDEC module described above. Note that the RAM_DEC module, like the BYTEDEC module, not only decrements, but also sets the zero flag and carry flag shown in FIG. 141 as a result of the decrement.

The index "RAM_DEC:" on the first line in FIG. 144(a) indicates the start address of the RAM_DEC module. The 1-byte value stored at the address indicated by the HL register is read to the A register by the command "LD A, (HL)" on the second line. Execution of such a command "LD A, (HL)" changes the second zero flag. Then, if the value of the A register is 0 (if the second zero flag is 1) according to the command "RT Z, A" on the third line, the process returns to the routine one step above. At this time, if the value of the A register is 0, the command "RT Z, A" sets the zero flag (first zero flag) to 1 and the carry flag to 0. Thus, if the value stored at the address indicated by the HL register is 0, zero flag=1 and carry flag=0 can be set without decrementing.

The value of the A register is compared with 2 by the command "CP A, 2" on the fourth line of FIG. 144(a). , the carry flag is set to 1. Note that the command "CP A, 2" is a command in which the carry flag is set when the value of the A register is less than 2, but at the stage of execution of the command "CP A, 2", the value of the A register is 1 or 2 or more. (because it is not 0), by setting the carry flag when less than 2, the carry flag is set when the value is 1 as a result. Thus, if the value of the A register is 1, the carry flag can be set to 1. The 1-byte value stored at the address indicated by the A register is decremented by one by the command "DEC A" on the fifth line. The command "LD (HL), A" on the sixth line stores the value of the A register at the address indicated by the HL register. Here, if the value stored at the address indicated by the HL register is 2 or more, the decremented value is 1 or more. The zero flag is set to 1. The carry flag does not change depending on the command "DEC A". Thus, if the value stored at the address indicated by the HL register is 2 or more, zero flag=0 and carry flag=0, and if it is 1, zero flag=1 and carry flag=1. Then, the command "RET" on the 7th line returns to the routine one level above. Thus, the value stored at the address indicated by the HL register can be decremented by 1 and the zero flag and carry flag can be set.

Here, by replacing with the command "DECM", the command group of FIG. 144(a) can be changed as shown in FIG. 144(b). The index "RAM_DEC:" on the first line in FIG. 144(b) indicates the start address of the RAM_DEC module. If the value stored at the address indicated by the HL register is 1 or more, the value stored at the address indicated by the HL register is decremented by 1, and if it is 0, 0 is maintained by the command "DECM (HL)" on the second line.

If the zero flag is not 1 (the value after decrementation is not zero) by the command "RET NZ" on the third line in FIG. Here, since decrementation has already been performed by the command "DECM (HL)", the fact that the zero flag is not 1 indicates that the value before decrementation is 2 or more. In this case, the zero flag is not set to 0 and the carry flag is not set to 0, so the routine may be returned to the routine one step above. Subsequently, the carry flag is inverted (1→0, 0→1) by the command "CCF" on the fourth line. Note that the zero flag does not change depending on the command "CCF". Thus, if the value stored at the address indicated by the HL register before decrementing is 1, zero flag=0 and carry flag=1, and if it is 0, zero flag=1 and carry flag=0. . Then, the command "RET" on the fifth line returns to the routine one level above. Thus, the value stored at the address indicated by the HL register can be decremented by 1 and the zero flag and carry flag can be set.

Here, the total command size of the commands of the RAM_DEC module shown in FIG. Command "CP A, 2" 2 bytes on line + Command "DEC A" 1 byte on line 5 + Command "LD (HL), A" 1 byte on line 6 + Command "RET" 1 byte on line 7 = 7 The total execution cycle is 2 cycles on the 2nd line + 4 cycles on the 3rd line (or 2 cycles) + 2 cycles on the 4th line + 1 cycle on the 5th line + 2 cycles on the 6th line + 3 cycles on the 7th line = 14 cycles (or 12 cycles). ). The number of cycles in parentheses indicates the execution cycle when the command "RT Z, A" does not move to the routine one level above. On the other hand, the total command size of the RAM_DEC module commands shown in FIG. CCF" 2 bytes + 5th line command "RET" 1 byte = 6 bytes, and the total execution cycle is 2nd line 5 cycles + 3rd line 3 cycles (1 cycle) + 4th line 2 cycles + 6th line 3 cycles = 13 cycle (11 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RET NZ" does not move to the routine one level above. Therefore, by replacing the command group of FIG. 144(a) with the command group of FIG. 144(b), the total command size is reduced by 1 byte and the total execution cycle is reduced by at least 1 cycle. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

The WORDDEC module is a general-purpose module for word counter subtraction processing, that is, for decrementing a 2-byte variable in the main RAM 300c by one. The WORDDEC module not only decrements, but also sets a zero flag and a carry flag as a result of decrementing.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the WORDDEC module as a subroutine in arbitrary processing, and executes the WORDDEC module. The WORDDEC module decrements the 2-byte data held in the main RAM 300c.

FIG. 145 is a flow chart showing specific processing of the WORDDEC module. Here, as an arbitrary process, part of the NHI_CHK module that executes the winning frequency abnormality error determination process, which is a subroutine of the state management process (error management process) shown in step S400-21 in FIG. 26, will be described. Numerical values of step S in this figure are used only in the explanation of this figure. Also, in the description of the WORDDEC module, the predetermined register is the HL register.

The main CPU 300a executes arbitrary processing as shown in FIG. 145(a). The main CPU 300a first sets the address of the variable to be decremented in the HL register (S1). Then, the WORDDEC module is called as a subroutine (S2).

As shown in FIG. 145(b), the main CPU 300a decrements by 1 the 2-byte value stored at the address indicated by the HL register in the WORDDEC module, and sets the zero flag and carry flag (S3). Then, the WORDDEC module is terminated and the subroutine one level above is returned to (S4). Note that the decrement mode and flag setting are explained in FIG. 141, similarly to the BYTEDEC module.

When the WORDDEC module sets the zero flag and the carry flag, the main CPU 300a uses the value of the HL register to perform various operations. For example, here, it is determined that the decrement result is not 0 (S5). Execute the next process without moving.

FIG. 146 is an explanatory diagram for explaining an example of commands for realizing the WORDDEC module. Of these, FIG. 146(a) shows a command group for arbitrary processing, and FIG. 146(b) shows a command group for the WORDDEC module. The flowchart shown in FIG. 145 is realized by the program shown in FIG. 146, for example.

By command "POP HL" on the first line in FIG. 146(a), the address value of the winning frequency abnormality error monitoring timer saved in the stack area is returned to the HL register. Such a command on the first line corresponds to step S1 in FIG. 145(a). Then, the WORDDEC module is called as a subroutine by the command "CALLF WORDDEC" on the second line. The command on the second line corresponds to step S2 in FIG. 145(a).

The index "WORDDEC:" on the first line in FIG. 146(b) indicates the head address of the WORDDEC module. The command "JTW Z, (HL), WORDDEC_99" on the second line determines if the two-byte value stored at the address indicated by the HL register is 0, and if so, moves to the index "WORDDEC_99:". . Execution of the command "JTW Z, (HL), WORDDEC_99" changes the zero flag. For example, if the value stored at the address indicated by the HL register is 0, the zero flag becomes 1 and the carry flag becomes 0. Also, if the value stored at the address indicated by the HL register is 0, the process moves to the index "WORDDEC_99:" and returns to the subroutine one level higher by the command "RET" on the seventh line. Thus, if the value stored at the address indicated by the HL register is 0, zero flag=1 and carry flag=0 can be set without decrementing.

By the command "DECW (HL)" on the third line in FIG. 146(b), the 2-byte value stored at the address indicated by the HL register is decremented by 1 to obtain the value stored at the address indicated by the HL register. update. Here, if the value stored at the address indicated by the HL register is 2 or more, the decremented value is 1 or more. A zero flag (second zero flag) is set to 1. Then, if the zero flag is not 1 by the command "RET NTZ" on the 4th line, the process returns to the subroutine one step above. The reason why "NTZ" is used here is that the command "DECW (HL)" changes the second zero flag but does not change the first zero flag. Note that neither the zero flag nor the carry flag changes depending on the command "RET NTZ". At this time, the zero flag does not become 1 (returns to the subroutine one level above) when the value stored in the address indicated by the HL register before decrementing is 2 or more. Therefore, if the number before decrement is 2 or more, the zero flag=0 and the carry flag=0, so there is no problem in returning to the subroutine one level above.

If the zero flag is 1, the value stored in the address indicated by the HL register before decrementing is 1, the zero flag=1, and the carry flag=0. That is, the specification of the carry flag is opposite to that shown in FIG. Therefore, the carry flag is forcibly set to 1 by the command "SCF" on the fifth line. Thus, if the value stored at the address indicated by the HL register before decrementing is 1, the zero flag=1 and the carry flag=1. Note that the zero flag does not change depending on the command "SCF". The commands on the 2nd to 6th lines correspond to step S3 in FIG. 145(b). Then, the command "RET" on the 7th line returns to the subroutine one level above. Such a command on the seventh line corresponds to step S4 in FIG. 145(b). Thus, the value stored at the address indicated by the HL register can be decremented by 1 and the zero flag and carry flag can be set.

Subsequently, if the zero flag (second zero flag) is not 1 (if it is 0) by the command "RET NTZ" on the third line of FIG. The command on the third line corresponds to steps S5 and S6 in FIG. 145(a). This allows processing based on the results of the WORDDEC module.

The WORDDEC module is called as a subroutine from multiple modules. For example, the TMR_NEW module that executes the timer update process shown in step S400-15 of FIG. 26, the TZ_SPN module that executes the special symbol changing process shown in step S620 of FIG. 41, and the It is called from the NHI_CHK module or the like that executes the winning frequency abnormality error determination process, which is a subroutine of the state management process (error management process).

In this way, the total command size of the WORDDEC module commands shown in FIG. 2 bytes + 4th line command "RET NTZ" 1 byte + 5th line command "SCF" 2 bytes + 7th line command "RET" 1 byte = 9 bytes, total execution cycle is 6 cycles of 2nd line (or 5 cycles)+3rd row 7 cycles+4th row 3 cycles (or 1 cycle)+5th row 2 cycles+7th row 3 cycles=21 cycles (or 18 cycles). The number of cycles in parentheses indicates the execution cycle when the command "JTW Z, (HL), WORDDEC — 99" or the command "RET NTZ" does not move to the next higher routine. By providing such a WORDDEC module, the command "CALLF WORDDEC" with a command size of 2 bytes can be used without performing word counter subtraction processing in each module described above. It becomes possible to secure the capacity of the control area for performing

FIG. 147 is an explanatory diagram for explaining another example of commands for realizing the WORDDEC module. Here, the command group of the WORDDEC module in FIG. 146(b) is replaced with the command group of the WORDDEC module in FIG. is used as it is as FIG. 147(a). Here, as shown in FIG. 147(a), the description of the processing that is substantially the same as in FIG. 146(a) will be omitted, and only the processing that is different in FIG. 147(b) will be described.

The index "WORDDEC:" on the first line in FIG. 147(b) indicates the top address of the WORDDEC module. If the value stored at the address indicated by the HL register is 1 or more, the value stored at the address indicated by the HL register is decremented by 1, and if it is 0, 0 is maintained by the command "DECWM (HL)" on the second line.

Here, the command "DECWM (HL)" decrements the 2-byte value stored at the address indicated by the HL register, and if the carry flag is set (-1), the address indicated by the HL register This command forces 0 to be stored in the 2-byte value stored in . Then, if the value stored at the address indicated by the HL register is 1 or more, it is decremented by 1, and if it is 0, 0 is maintained. By executing the command "DECWM (HL)", if the value after decrement is zero (if the value before decrement is 1 or 0), zero flags (first zero flag and second zero flag) are set. If the value before decrement is zero, the carry flag is set and the value is set to one. Such a command has a command size of "2" and an execution cycle of "7".

If the zero flag is not 1 (the value after decrementation is not zero) by the command "RET NZ" on the third line in FIG. Here, since decrementation has already been performed by the command "DECWM (HL)", the fact that the zero flag is not 1 indicates that the value before decrementation is 2 or more. In this case, the zero flag is not set to 0, and the carry flag is not set to 0, so that the subroutine may be returned to one level higher.

In the command "DECWM (HL)", if the value stored in the address indicated by the HL register before decrementing is 1, it becomes 0 after decrementing, and the zero flag=1 and the carry flag=0. If there is, it is not decremented and is maintained at 0, with zero flag=1 and carry flag=1. That is, the specification of the carry flag is opposite to that shown in FIG. Therefore, the carry flag is inverted (1→0, 0→1) by the command "CCF" on the fourth line in FIG. 147(b). Note that the zero flag does not change depending on the command "CCF". Thus, if the value stored at the address indicated by the HL register before decrementing is 1, then zero flag=1 and carry flag=1, and if it is 0, then zero flag=1 and carry flag=0. . The commands on the second to fourth lines correspond to step S3 in FIG. 145(b). Then, the command "RET" on the fifth line returns to the subroutine one level above. The command on the fifth line corresponds to step S4 in FIG. 145(b). Thus, the value stored at the address indicated by the HL register can be decremented by 1 and the zero flag and carry flag can be set.

Subsequently, if the zero flag (second zero flag) is not 1 (if it is 0) by the command "RET NTZ" on the third line of FIG. The command on the third line corresponds to steps S5 and S6 in FIG. 145(a). This allows processing based on the results of the WORDDEC module.

The total command size of the command of the WORDDEC module in FIG. Cycle + 3rd row 3 cycles (1 cycle) + 4th row 2 cycles + 6th row 3 cycles = 15 cycles (13 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RET NZ" does not move to the routine one level above. Therefore, the total command size is reduced by 3 bytes and the total execution cycle is reduced by at least 6 cycles compared to the case of FIG. 146(b). With such a WORDDEC module, it is possible to further shorten commands and secure the capacity of the control area for performing game control processing.

146(b) and FIG. 147(b), the command group that occupied five lines (second to sixth lines) in FIG. 147(b) can be expressed in three lines (second to fourth lines), which makes it possible to reduce the number of commands and the design load.

<Command “RCP”>
FIG. 148 is an explanatory diagram for explaining an example of processing for returning from a subroutine. The command "CP A,n" in FIG. 148(a) is a command for comparing the value of the A register with a predetermined value n. In this case, the carry flag is set to 1. The command size of such command "CP A,n" is "2" and the execution cycle is "2".

The command "RET cc" in FIG. 148(a) refers to the zero flag or carry flag, and if the target flag is 1, returns from the subroutine to the routine one level above. Such a command "RET cc" has a command size of "1" and an execution cycle of "3" (or "1"). Note that the number of cycles in parentheses indicates the execution cycle when the command "RET cc" does not move to a routine higher by one (does not return from a subroutine).

Here, as shown in FIG. 148(a), the value of the A register is compared with a predetermined value n by the command "CP A,n" on the first line, and the command "RET cc" on the second line , whether or not to return from the subroutine is determined according to the result of the comparison. Here, these two commands can be integrated (replaced) into one command "RCP cc, A, n" as shown in FIG. 148(b).

The command "RCP cc, A, n" in FIG. 148(b) is a command that compares the value of the A register with a predetermined value n, and returns from the subroutine to the routine one level above according to the comparison result. . The command size of such command "RCP cc, A, n" is "2" and the execution cycle is "5" (or "3"). The number of cycles in parentheses indicates the execution cycle when the command "RCP cc, A, n" does not move to the routine one level above.

Here, the total command size of the command group shown in FIG. 148(a) is 2 bytes of the command "CP A, n" on the first line + 1 byte of "RET cc" on the second line=3 bytes, and the total execution cycle is 1st row 2 cycles+2nd row 3 cycles (1 cycle)=5 cycles (3 cycles). On the other hand, the command size of the command "RCP cc, A, n" shown in FIG. 148(b) is 2 bytes, and the execution cycle is 5 cycles (3 cycles). Therefore, by replacing the command group of FIG. 148(a) with the command of FIG. 148(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process. A plurality of modules capable of such replacement will be described below.

FIG. 149 is an explanatory diagram for explaining the PY_CMDA module. The PY_CMDA module shown in FIG. 149 executes the main command analysis process shown in step S100-63 in FIG. 23, that is, the process of analyzing the main command and detecting an abnormality in the main command.

The index "PY_CMDA:" on the first line in FIG. 149(a) indicates the start address of the PY_CMDA module. The command "LDQ A, (LOW R_BCR_BUF)" on the second line sets the value of the Q register to the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_BCR_BUF" that stores the buffer value of the main command to the lower address. 1 byte, and the value (main command) stored at that address is read to the A register.

Then, when the buffer is cleared and the payout activation designation command confirmation process is executed, as the received data confirmation process, the command "SUB A, @BCR_PAY_CLR" on the third line of FIG. BCR_PAY_CLR”, here 20H is subtracted. Then, the decremented value of the A register is compared with 0CH by the command "CP A, 00CH" on the fourth line. Here, it is confirmed that the main command is included in the range from 20H to 2BH. That is, if the value of the A register is less than 20H, the command "SUB A, @BCR_PAY_CLR" causes the value of the A register to become a negative value, which is greater than 0CH when viewed as a 1-byte value. Therefore, if the subtracted value of the A register is less than 0CH, the carry flag is set to 1 by the command "CP A, 00CH". Then, if the carry flag is not 1 by "RET NC" on the fifth line, the routine returns to the routine one level above. If the carry flag is 1 (if it is included in the range of 20H to 2BH), the payout error specification command set process and payout radio wave error flag setting process are executed, and the routine returns to the upper stage.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 149(a) can be changed as shown in FIG. 149(b). The index "PY_CMDA:" on the first line in FIG. 149(b) indicates the start address of the PY_CMDA module. The command "LDQ A, (LOW R_BCR_BUF)" on the first line sets the value of the Q register to the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_BCR_BUF" that stores the buffer value of the main command to the lower address. 1 byte, and the value (main command) stored at that address is read to the A register.

Then, after clearing the buffer and executing a predetermined process for the payout activation designation command, the command "SUB A, @BCR_PAY_CLR" on the third line in FIG. subtract a fixed value, here 20H. A command "RCP NC, A, 00CH" on the fourth line compares the subtracted value of the A register with 0CH, and if the carry flag is not 1, returns to the routine one step above. Here, it is confirmed that the main command is included in the range of 20H to 2BH, and if it is not within that range, the processing after that is not performed and the routine returns to the upper step. If the carry flag is 1, the payout error specification command set process and the payout radio wave error flag setting process are executed, and the routine returns to the upper level.

Here, the total command size of the command group shown in FIG. 149(a) is the command "LDQ A, (LOW R_BCR_BUF)" 2 bytes on the second line + the command "SUB A, @BCR_PAY_CLR" 2 bytes on the third line + 4 bytes. 2 bytes of the command "CP A, 00CH" on the line + 1 byte of "RET NC" on the 5th line = 7 bytes. 3 cycles (1 cycle)=10 cycles (8 cycles). On the other hand, the total command size of the command group shown in FIG. 149(b) is the command "LDQ A, (LOW R_BCR_BUF)" 2 bytes on the second line + the command "SUB A, @BCR_PAY_CLR" 2 bytes + 4 lines on the third line. The second command "RCP NC, A, 00CH" 2 bytes = 6 bytes, and the total execution cycle is: 2nd line 3 cycles + 3rd line 2 cycles + 4th line 5 cycles (3 cycles) = 10 cycles (8 cycles) Become. Therefore, by replacing the command group of FIG. 149(a) with the command group of FIG. 149(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 150 is an explanatory diagram for explaining the GAT_PAS module. The GAT_PAS module shown in FIG. 150 performs gate switch passage processing (gate passage processing) shown in step S510 of FIG. , Usually, the process related to the design is executed.

As memory count check processing, the index "GAT_PAS:" on the first line in FIG. 150(a) indicates the start address of the GAT_PAS module. By the command "LDQ DE, LOW R_FZ_MEM" on the second line, the value of the Q register is set as the upper 1 byte of the address and the value of the lower 1 byte of the address "R_FZ_MEM" is set as the lower 1 byte of the address. A 2-byte value (the address of the normal symbol reserved ball number counter) is read to the DE register. By the command "LD A, (DE)" on the third line, the value stored in the address indicated by the DE register (that is, R_FZ_MEM) (the counter value of the normal symbol holding ball number counter) is read to the A register.

Then, the command "CP A, @FZ_MEM_MAX" on the fourth line in FIG. 150(a) compares the value of the A register with the fixed value "@FZ_MEM_MAX", which is "4" here. That is, if the value of the A register is less than 4, the carry flag is set to 1. Then, if the carry flag is not 1 by "RET NC" on the fifth line, the routine returns to the routine one level above. That is, if the counter value of the normal symbol reserved ball number counter is 4 or more, the normal symbol reserved ball number counter is no longer counted, so the GAT_PAS module is terminated. If the carry flag is 1, random number acquisition processing, storage number addition processing, winning determination random number acquisition processing, transfer destination address calculation processing, and storage area storage processing are executed, and the routine returns to the routine one level above. .

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 150(a) can be changed as shown in FIG. 150(b). The index "GAT_PAS:" on the first line in FIG. 150(b) indicates the start address of the GAT_PAS module. By the command "LDQ DE, LOW R_FZ_MEM" on the first line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FZ_MEM" is set as the lower 1 byte of the address, and the A 2-byte value (the address of the normal symbol reserved ball number counter) is read to the DE register. By the command "LD A, (DE)" on the third line, the value (counter value of the normal symbol holding ball number counter) stored in the address indicated by the DE register (that is, R_FZ_MEM) is read to the A register.

Then, according to the command "RCP NC, A, @FZ_MEM_MAX" on the fourth line in FIG. Return to routine above. That is, if the counter value of the normal symbol reserved ball number counter is 4 or more, the normal symbol reserved ball number counter is no longer counted, so the GAT_PAS module is terminated. If the carry flag is 1, the memory number addition process, the winning determination random number acquisition process, the transfer destination address calculation process, and the storage area storage process are executed, and the routine returns to the upper stage.

Here, the total command size of the command group shown in FIG. 150(a) is the command "LDQ DE, LOW R_FZ_MEM" on the second line 2 bytes + the command "LD A, (DE)" on the third line 1 byte + 4 lines. 2nd command "CP A, @FZ_MEM_MAX" 2 bytes + 5th line "RET NC" 1 byte = 6 bytes. 3 cycles (1 cycle)=9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. command "RCP NC, A, @FZ_MEM_MAX" 2 bytes = 5 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 2 cycles + 4th line 5 cycles (3 cycles) = 9 cycles (7 cycles) Become. Therefore, by replacing the command group of FIG. 150(a) with the command group of FIG. 150(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 151 is an explanatory diagram for explaining the TDN_PAS module. The TDN_PAS module shown in FIG. 151 executes the count switch passing process (large winning opening passing process) shown in step S540 of FIG. .

The index "TDN_PAS:" on the first line in FIG. 151(a) indicates the top address of the TDN_PAS module. Then, when the count switch determination value confirmation process, the special electric accessory continuous operation number determination process, the large winning opening winning designation command set process, and the large winning opening excessive winning monitoring process are executed, two lines are executed as the special electric accessory operation check process. By the second command "LDQ A, (LOW R_TDN_PHS)", the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "R_TDN_PHS" is set as the lower 1 byte of the address, and the Read the value (special electric accessory game management phase) to the A register.

By the command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on the third line of FIG. Go to address "TDN_PAS_10". In this way, if the value of the A register is the jackpot jackpot opening control state designation value (the special electric accessory game management phase is 02H), the subsequent processing is omitted and the process moves to the index "TDN_PAS_10:" on the 6th line. be able to. By the command "CP A, @TD_OPN_SHT" on the 4th line, the value of the A register and the fixed value "@TD_OPN_SHT" indicating the small winning big winning opening control state designation value, here, 6 are compared, and if they are equal (The special electric accessory game management phase is 06H), the zero flag is set to 1. Then, if the zero flag is not 1 by "RET NZ" on the fifth line, the process returns to the routine one step above. That is, if the value of the A register is not the specified value of the control state for opening the big winning opening and the specified value for opening the control state of the small winning opening, the TDN_PAS module is terminated. If the zero flag is 1, the special electric accessary item winning ball count processing, the special electric fraudulent prize detection condition confirmation processing, and the special electric fraudulent prize winning error processing are executed, and the routine returns to the routine one step above.

Here, if the replacement in FIG. 148 is performed, the command group in FIG. 151(a) can be changed as shown in FIG. 151(b). The index "TDN_PAS:" on the first line in FIG. 151(b) indicates the top address of the TDN_PAS module. Then, when the count switch determination value confirmation processing, the special electric accessory continuous operation number determination processing, the large winning opening winning designation command set processing, and the large winning opening excessive winning monitoring processing are executed, the command "LDQ A, (LOW R_TDN_PHS)”, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address “R_TDN_PHS” is set to the lower 1 byte of the address, and the value stored at that address (special electric role game management phase ) into the A register.

By the command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10" on the third line of FIG. Go to address "TDN_PAS_10". In this way, if the value of the A register is the jackpot jack opening control state designation value, it is possible to omit the subsequent processing and move to the index "TDN_PAS_10:" on the fifth line. By the command "RCP NZ, A, @TD_OPN_SHT" on the 4th line, the value of the A register is compared with the fixed value "@TD_OPN_SHT" indicating the small winning big winning opening control state specified value, here 6, If equal, return to the routine above. That is, if the value of the A register is not the specified value of the control state for opening the big winning opening and the specified value for opening the control state of the small winning opening, the TDN_PAS module is terminated. If the zero flag is 0, the special electric accessory winning ball number count processing, the special electric unauthorized winning detection condition confirmation processing, and the special electric unauthorized winning error processing are executed, and the routine returns to the routine one step above.

Here, the total command size of the command group shown in FIG. 151(a) is the command "LDQ A, (LOW R_TDN_PHS)" on the second line + 2 bytes + the command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10 on the third line". 3 bytes + 4th line command "CP A, @TD_OPN_SHT" 2 bytes + 5th line "RET NZ" 1 byte = 8 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 4 cycles (or 3 cycle)+4th row 2nd cycle+5th row 3rd cycle (1 cycle)=12 cycles (9 cycles). On the other hand, the total command size of the command group shown in FIG. 151(b) is the second line command "LDQ A, (LOW R_TDN_PHS)" 2 bytes + the third line command "JCP Z, A, @TD_OPN_BHT, TDN_PAS_10". 3 bytes + 4th line command "RCP NZ, A, @TD_OPN_SHT" 2 bytes = 7 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 4 cycles (or 3 cycles) + 4th line 5 cycles (3 cycles)=12 cycles (9 cycles). Therefore, by replacing the command group of FIG. 151(a) with the command group of FIG. 151(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 152 is an explanatory diagram for explaining the FD_OPN module. The FD_OPN module shown in FIG. 152 performs the normal electric accessory winning opening control process shown in step 850 of FIG. to run.

The index “FD_OPN:” on the first line in FIG. 152(a) indicates the start address of the FD_OPN module. Then, when the normal electric accessory winning opening opening and closing operation switching process is executed, as the specified winning number confirmation process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_FDN_CNT)" on the second line. , the value of the lower 1 byte of the address "R_FDN_CNT" is set as the lower 1 byte of the address, and the value stored at that address (counter value of the normal electric accessory winning ball counter) is read to the A register.

By the command "CP A, @FDN_CNT" on the third line of FIG. Now, it is compared with 8, and if it is less than 8, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the 4th line, the process returns to the routine one level above. That is, if the value of the A register is less than the number of prize winning balls associated with the normal electric accessory, the FD_OPN module is terminated. In addition, if the carry flag is 0, the normal electric accessary product operation end time setting process is executed, and the routine returns to the routine one step above.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 152(a) can be changed as shown in FIG. 152(b). The index “FD_OPN:” on the first line in FIG. 152(b) indicates the top address of the FD_OPN module. Then, when the normal electric accessory winning opening opening and closing operation switching process is executed, as the specified winning number confirmation process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_FDN_CNT)" on the second line. , the value of the lower 1 byte of the address "R_FDN_CNT" is set as the lower 1 byte of the address, and the value stored at that address (counter value of the normal electric accessory winning ball counter) is read to the A register.

By the command "RCP C, A, @FDN_CNT" on the third line in FIG. 152(b), the value of the A register and the fixed value "@FDN_CNT" indicating the maximum number of winning balls for the normal electric accessory. , here, 8, and if less than 8, return to the routine one level above. That is, if the value of the A register is less than the number of winning balls for the winning opening for the normal electric accessory, the FD_OPN module is terminated. In addition, if the carry flag is 0, the normal electric accessary product operation end time setting process is executed, and the routine returns to the routine one step above.

Here, the total command size of the command group shown in FIG. 152(a) is the command "LDQ A, (LOW R_FDN_CNT)" 2 bytes on the second line + the command "CP A, @FDN_CNT" 2 bytes on the third line + 4 bytes. 1 byte of "RET C" on the line = 5 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 3 cycles on the 4th line (1 cycle) = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 152(b) is the command "LDQ A, (LOW R_FDN_CNT)" 2 bytes on the second line + the command "RCP C, A, @FDN_CNT" 2 bytes on the third line. = 4 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 5 cycles (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group of FIG. 152(a) with the command group of FIG. 152(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 153 is an explanatory diagram for explaining the TZ_STA module. The TZ_STA module shown in FIG. 153 executes the special symbol variation waiting process shown in step S610 of FIG. 37, that is, the special symbol variation preparation process based on the number of special symbol reserved balls.

The index "TZ_STA:" on the first line in FIG. 153(a) indicates the top address of the TZ_STA module. Then, when the special symbol reserved ball number confirmation process is executed, the DATSEL module, which is a general-purpose module, is called by the command "RST DATSEL" on the second line as the special symbol state confirmation process that is not subject to processing, and the selection result of the control data is Stored in the A register.

By the command "CP A, @TZ_BHT" on the 3rd line of FIG. If they are equal, the zero flag is set to one. Then, if the zero flag is 1 by "RET Z" on the 4th line, the process returns to the routine one level above. That is, if the jackpot is being confirmed, the TZ_STA module is terminated. By the command "CP A, @TZ_SHT" on the fifth line, the value of the A register and the fixed value "@TZ_SHT" indicating the special symbol small hit information, here, are compared with 02H, and if equal to 02H, the zero flag is Stand up and be 1. Then, if the zero flag is 1 by "RET Z" on the sixth line, the process returns to the routine one level above. That is, if the small hit is being confirmed, the TZ_STA module is terminated. If the zero flag is not 1, the special symbol variation start time setting process, the number command set process, and the special symbol variation preparation process are executed, and the routine returns to the upper level.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 153(a) can be changed as shown in FIG. 153(b). The index "TZ_STA:" on the first line in FIG. 153(b) indicates the head address of the TZ_STA module. Then, when the special symbol reserved ball number confirmation processing is executed, the DATSEL module is called by the command "RST DATSEL" on the second line as the processing non-target special symbol state confirmation processing, and the selection result of the control data is stored in the A register. be done.

By the command "RCP Z, A, @TZ_BHT" on the 3rd line in FIG. 153(b), the value of the A register and the fixed value "@TZ_BHT" indicating special symbol jackpot information, here, 01H, are compared, If equal to 01H, return to the routine one level above. That is, if the jackpot is being determined, the TZ_STA module is terminated. By the command "RCP Z, A, @TZ_SHT" on the 4th line, the value of the A register and the fixed value "@TZ_SHT" indicating the special symbol small winning information, here, 02H are compared, and if they are equal to 02H, Return to the routine one level above. That is, if the small hit is being confirmed, the TZ_STA module is terminated. If the zero flag is not 1, the special symbol variation start time setting process, the number command set process, and the special symbol variation preparation process are executed, and the routine returns to the upper level.

Here, the total command size of the command group shown in FIG. 153(a) is the command "RST DATSEL" 1 byte on the second line + the command "CP A, @TZ_BHT" on the third line 2 bytes + "RET Z" 1 byte + 5th line command "CP A, @TZ_SHT" 2 bytes + 6th line "RET Z" 1 byte = 7 bytes, total execution cycle is 2nd line 4 cycles + 3rd line 2 cycles + 4 lines 3rd cycle (1 cycle)+5th row 2nd cycle+6th row 3rd cycle (1 cycle)=14 cycles (10 cycles). On the other hand, the total command size of the command group shown in FIG. "RCP Z, A, @TZ_SHT" 2 bytes = 5 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 5 cycles (3 cycles) + 4th line 5 cycles (3 cycles) = 14 cycles (10 cycles) ). Therefore, by replacing the command group of FIG. 153(a) with the command group of FIG. 153(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 154 is an explanatory diagram for explaining the TZ_RGET module. The TZ_RGET module shown in FIG. 154 performs the special symbol random number acquisition process shown in step S535 of FIG. Execute the process that stores the numeric value.

The index "TZ_RGET:" on the first line in FIG. 154(a) indicates the start address of the TZ_RGET module. Execute the jackpot determination random number acquisition process, and as the special symbol reserved ball number update process, the value stored at the address indicated by the DE register (target special symbol reserved ball counter value of the number counter) to the A register. It should be noted that when the TZ_RGET module is called, it is assumed that the address indicating the counter value of the target special symbol reserved ball number counter is stored in advance in the DE register.

Then, the command "CP A, @TZ_MEM_MAX" on the 3rd line of FIG. 154(a) sets the value of the A register and the fixed value "@TZ_MEM_MAX" indicating the upper limit of the number of special symbol reserved balls, here "4". Compare with That is, if the value of the A register is less than 4, the carry flag is set to 1. Then, if the carry flag is not 1 by "RET NC" on the 4th line, it returns to the routine one level above. That is, if the counter value of the target special symbol reserved ball number counter is 4 or more, the target special symbol reserved ball number counter is no longer counted, so the TZ_RGET module is terminated. In addition, if the carry flag is 1, variation pattern random number acquisition processing, reach group determination random number acquisition processing, reach mode determination random number acquisition processing, transfer destination address calculation processing, storage area storage processing, acquisition time effect determination processing, and special Execute the drawing hold specification command set process and return to the routine one level above.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 154(a) can be changed as shown in FIG. 154(b). The index "TZ_RGET:" on the first line in FIG. 154(b) indicates the head address of the TZ_RGET module. Execute the jackpot determination random number acquisition process, and as the special symbol retention ball number update process, the value (target The counter value of the special symbol holding ball number counter) is read to the A register.

Then, the command "RCP NC, A, @TZ_MEM_MAX" on the third line of FIG. 4", and if the value of the A register is 4 or more, the process returns to the routine one level above. That is, if the counter value of the target special symbol reserved ball number counter is 4 or more, the target special symbol reserved ball number counter is no longer counted, so the TZ_RGET module is terminated. In addition, if the value of the A register is less than 4, variation pattern random number acquisition processing, reach group determination random number acquisition processing, reach mode determination random number acquisition processing, transfer destination address calculation processing, storage area storage processing, effect determination processing at acquisition, And, execute the special figure reservation designation command set processing, and return to the routine one level above.

Here, the total command size of the command group shown in FIG. 154(a) is the command "LD A, (DE)" 1 byte on the second line + the command "CP A, @TZ_MEM_MAX" 2 bytes on the third line + 4 lines. 1st byte of "RET NC"=4 bytes, and the total execution cycle is 2nd line 2 cycles+3rd line 2 cycles+4th line 3 cycles (1 cycle)=7 cycles (5 cycles). On the other hand, the total command size of the group of commands shown in FIG. 3 bytes, and the total execution cycle is 2 cycles on the 2nd line + 5 cycles on the 3rd line (3 cycles) = 7 cycles (5 cycles). Therefore, by replacing the command group of FIG. 154(a) with the command group of FIG. 154(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 155 is an explanatory diagram for explaining the TRSVSEL module. The TRSVSEL module shown in FIG. 155 executes preliminary area setting processing shown in step S610-17 of FIG. 37, that is, confirmation of special symbol hits and preliminary setting processing of special symbol probability state and special symbol state.

The index "TRSVSEL:" on the first line in FIG. 155(a) indicates the start address of the TRSVSEL module. Then, when the state offset check flag setting process is executed, the DATSEL module, which is a general-purpose module, is called by the command "RST DATSEL" on the second line as a special symbol per confirmation process, and the control data selection result is stored in the A register. be done.

By the command "CP A, @TZ_BHT" on the third line of FIG. If they are equal, the zero flag is set to one. Then, if the zero flag is not 1 by "RET NZ" on the 4th line, the process returns to the routine one step above. That is, if the jackpot is not being confirmed, the TRSVSEL module is terminated. In addition, if the zero flag is 1, the special symbol probability state preliminary setting process and the special symbol state preliminary setting process are executed, and the routine returns to the routine one level above.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 155(a) can be changed as shown in FIG. 155(b). The index "TRSVSEL:" on the first line in FIG. 155(b) indicates the top address of the TRSVSEL module. Then, when the state offset check flag setting process is executed, the DATSEL module is called by the command "RST DATSEL" on the second line, and the selection result of the control data is stored in the A register as the special symbol per confirmation process.

By the command "RCP NZ, A, @TZ_BHT" on the third line of FIG. If not equal to 01H, return to the routine one step above. That is, if the jackpot is not being confirmed, the TRSVSEL module is terminated. If it is equal to 01H, the special symbol probability state preliminary setting process and the special symbol state preliminary setting process are executed, and the process returns to the routine one step above.

Here, the total command size of the command group shown in FIG. 155(a) is the command "RST DATSEL" 1 byte on the second line + the command "CP A, @TZ_BHT" on the third line 2 bytes + "RET NZ" 1 byte=4 bytes, and the total execution cycle is 2nd row 4 cycles+3rd row 2 cycles+4th row 3 cycles (1 cycle)=9 cycles (7 cycles). On the other hand, the total command size of the group of commands shown in FIG. The total execution cycle is 2nd line 4 cycles+3rd line 5 cycles (3 cycles)=9 cycles (7 cycles). Therefore, by replacing the command group of FIG. 155(a) with the command group of FIG. 155(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 156 is an explanatory diagram for explaining the TDOVCHK module. The TDOVCHK module shown in FIG. 156 executes the large winning opening excessive after setting the large winning opening entering ball command (S540-5) in the count switch passage processing (large winning opening passage processing) shown in step S540 in FIG. Winning monitor processing, that is, update processing of the large winning opening winning ball number counter and the large winning opening excess winning times counter are executed.

The index "TDOVCHK:" on the first line in FIG. 156(a) indicates the top address of the TDOVCHK module. Then, as a special electric accessory game management phase confirmation process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_TDN_PHS)" on the second line, and the lower 1 byte of the address "R_TDN_PHS" The value is the lower 1 byte of the address, and the value stored at that address (special electric accessory game management phase) is read to the A register.

By the command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on the third line of FIG. If there is, move to address "TDOVCHK_10". In this way, if the value of the A register is a designated value after the state designated value before opening the small winning big winning opening, the subsequent processing can be omitted and the index "TDOVCHK_10" on the sixth line can be moved to. According to the command "CP A, @TD_OPN_BHT" on the fourth line, the value of the A register is compared with a fixed value "@TD_OPN_BHT" indicating the jackpot opening control state designation value, here 2, and if they are equal, The zero flag is set to 1. Then, if the zero flag is 1 by "RET Z" on the 5th line, the process returns to the routine one level above. That is, if the value of the A register is the jackpot jack opening control state designation value, the TDOVCHK module is terminated. If the zero flag is not 1, the process of updating the number of winning balls counter of the big winning opening, the processing of updating the number of winning balls counter of the big winning opening, the processing of updating the number of times of winning of the big winning opening counter, and the processing of the large winning opening excessive winning error time are executed, and the routine goes to the next step up. return.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 156(a) can be changed as shown in FIG. 156(b). The index "TDOVCHK:" on the first line in FIG. 156(b) indicates the top address of the TDOVCHK module. Then, as a special electric accessory game management phase confirmation process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_TDN_PHS)" on the second line, and the lower 1 byte of the address "R_TDN_PHS" The value is the lower 1 byte of the address, and the value stored at that address (special electric accessory game management phase) is read to the A register.

By the command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on the third line of FIG. If there is, move to address "TDOVCHK_10". In this way, if the value of the A register is a specified value after the specified value of the state before opening the small winning big winning opening, the subsequent processing can be omitted and the process can be moved to the index "TDOVCHK_10" on the fifth line. By the command "RCP Z, A, @TD_OPN_BHT" on the 4th line, the value of the A register and the fixed value "@TD_OPN_BHT" indicating the jackpot opening control state designation value, here, 2, are compared, and if they are equal If so, return to the routine one level above. That is, if the value of the A register is the jackpot jack opening control state designation value, the TDOVCHK module is terminated. If the zero flag is not 1, the process of updating the number of winning balls counter of the big winning opening, the processing of updating the number of winning balls counter of the big winning opening, the processing of updating the number of times of winning of the big winning opening counter, and the processing of the large winning opening excessive winning error time are executed, and the routine goes to the next step up. return.

Here, the total command size of the command group shown in FIG. 156(a) is the second line command "LDQ A, (LOW R_TDN_PHS)" 2 bytes + the third line command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10 3 bytes + 4th line command "CP A, @TD_OPN_BHT" 2 bytes + 5th line "RET Z" 1 byte = 8 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 4 cycles (or 3 cycle)+4th row 2nd cycle+5th row 3rd cycle (1 cycle)=12 cycles (9 cycles). On the other hand, the total command size of the command group shown in FIG. 156(b) is the command "LDQ A, (LOW R_TDN_PHS)" on the second line + the command "JCP NC, A, @TD_PRE_SHT, TDOVCHK_10" on the third line. 3 bytes + 4th line command "RCP Z, A, @TD_OPN_BHT" 2 bytes = 7 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 4 cycles (or 3 cycles) + 4th line 5 cycles (3 cycles)=12 cycles (9 cycles). Therefore, by replacing the command group of FIG. 156(a) with the command group of FIG. 156(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 157 is an explanatory diagram for explaining the BER_CHK module. The BER_CHK module shown in FIG. 157 performs base abnormality error monitoring processing, which is a subroutine of the state management processing (error management processing) shown in step S400-21 in FIG. to run.

As out switch confirmation processing, the index "BER_CHK:" on the first line in FIG. 157(a) indicates the start address of the BER_CHK module. The command "LDQ HL, LOW R_BAS_CNT" on the second line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "R_BAS_CNT" to the L register. The command "LD A, (HL)" on the third line reads the value (the counter value of the base abnormality confirmation counter) stored at the address indicated by the HL register (that is, R_BAS_CNT) to the A register.

Then, the value of the A register is compared with the fixed value "@BAS_CHK_CNT" (here, 20) indicating the base error detection ball number by the command "CP A, @BAS_CHK_CNT" on the fourth line in FIG. 157(a). That is, if the value of the A register is less than 20, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the fifth line, the process returns to the routine one level above. That is, if the counter value of the base abnormality confirmation counter is less than 20, the BER_CHK module is terminated. If the carry flag is not 1, security setting processing is executed, and the routine returns to the routine one level above.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 157(a) can be changed as shown in FIG. 157(b). The index "BER_CHK:" on the first line in FIG. 157(b) indicates the head address of the BER_CHK module. By the command "LDQ HL, LOW R_BAS_CNT" on the second line, the value of the Q register is read into the H register, and the value of the lower 1 byte of the address "R_BAS_CNT" (address for storing the base abnormality confirmation counter) is read into the L register. The command "LD A, (HL)" on the third line reads the value (the counter value of the base abnormality confirmation counter) stored at the address indicated by the HL register (that is, R_BAS_CNT) to the A register.

157(b), the command "RCP C, A, @BAS_CHK_CNT" on the 4th line compares the value of the A register with the fixed value "@BAS_CHK_CNT" indicating the number of balls detected as base failure, here 20. However, if the value of the A register is less than 20, the routine returns to the upper level. Incidentally, if the value of the A register is 20 or more, the security setting process is executed and the routine returns to the routine one level above.

Here, the total command size of the command group shown in FIG. 157(a) is the command "LDQ HL, LOW R_BAS_CNT" on the second line 2 bytes + the command "LD A, (HL)" on the third line 1 byte + 4 lines. 2nd command "CP A, @BAS_CHK_CNT" 2 bytes + 5th line "RET C" 1 byte = 6 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 2 cycles + 4th line 2 cycles + 5 lines 3rd cycle (1 cycle)=9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. command "RCP C, A, @BAS_CHK_CNT" 2 bytes = 5 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 2 cycles + 4th line 5 cycles (3 cycles) = 9 cycles (7 cycles) Become. Therefore, by replacing the command group of FIG. 157(a) with the command group of FIG. 157(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 158 is an explanatory diagram for explaining the TEF_SEL module. The TEF_SEL module shown in FIG. 158 is a subroutine of the large winning opening closing effective time setting process shown in step S720-9 in FIG. Execute the process to select valid time from the table.

The index "TEF_SEL:" on the first line in FIG. 158(a) indicates the top address of the TEF_SEL module. Then, as the big winning mouth closed valid time data selection process, the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line sets the value of the Q register to the upper 1 byte of the address, and the lower 1 byte of the address "R_ZUG_CHK_FIX". The value is the lower 1 byte of the address, and the value (special symbol determination flag) stored at that address is read to the A register.

By the command "CP A, @ZUG_SML1" on the third line of FIG. If it is less than 07H, the carry flag is set to 1. Then, if the carry flag is not 1 by "RET NC" on the 4th line, it returns to the routine one level above. That is, if the value of the A register is equal to or greater than the small winning symbol 1 designating data, the TEF_SEL module is terminated. If the carry flag is 1, the word data selection process is executed, and the process returns to the routine one level above.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 158(a) can be changed as shown in FIG. 158(b). The index "TEF_SEL:" on the first line in FIG. 158(b) indicates the top address of the TEF_SEL module. Then, as the big winning mouth closing effective time data selection process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line, and the lower 1 byte of the address "R_ZUG_CHK_FIX" is set. The value is the lower 1 byte of the address, and the value (special symbol determination flag) stored at that address is read to the A register.

By the command "RCP NC, A, @ZUG_SML1" on the 3rd line of FIG. If the value is 07H or more, the routine returns to the routine one step above. That is, if the value of the A register is equal to or greater than the small winning symbol 1 designating data, the TEF_SEL module is terminated. If the value of the A register is less than the small winning symbol 1 designated data, the word data selection process is executed, and the routine returns to the upper stage.

Here, the total command size of the command group shown in FIG. 158(a) is the command "LDQ A, (LOW R_ZUG_CHK_FIX)" 2 bytes on the second line + the command "CP A, @ZUG_SML1" 2 bytes on the third line + 4 bytes. 1 byte of "RET NC" on the row=5 bytes, and the total execution cycle is 3 cycles on the 2nd row+2 cycles on the 3rd row+3 cycles on the 4th row (1 cycle)=8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 158(b) is the second line command "LDQ A, (LOW R_ZUG_CHK_FIX)" 2 bytes + the third line command "RCP NC, A, @ZUG_SML1" 2 bytes. = 4 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 5 cycles (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group of FIG. 158(a) with the command group of FIG. 158(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

The replacement shown in FIG. 148 is called as a subroutine from a plurality of modules not only in pachinko machines but also in slot machines. For example, in the SET_RIG module for executing reverse push data setting processing in the number of sliding frames acquisition processing in step S2500-35 in FIG. 92, the game state and PRE_LOT module that selectively shifts according to the effect state and executes the in-preparation process (AT state=“5”), and the game state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. And the REG_LOT module that selectively shifts according to the effect state and executes the REG process (AT state=“6”), and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. A BIG_SLT module for executing BIG stock number lottery processing in the BIT_LOT module that selectively shifts according to the state and effect state and executes BIG medium processing (AT state=“7”), shown in step S2400-11 in FIG. It is called from the NAV_SET module or the like that executes the instruction information setting process in the execution flag setting process.

FIG. 159 is an explanatory diagram for explaining the SET_RIG module. The SET_RIG module shown in FIG. 159 executes reverse push data setting processing, that is, processing for setting data necessary for stop control.

The index “SET_RIG:” on the first line in FIG. 159(a) indicates the start address of the SET_RIG module. By the command "LDQ A, (LOW_HIT_NUM)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_HIT_NUM" storing the stop control number is set to the lower 1 byte of the address. , and the value (stop control number) stored at that address is read to the A register.

Then, as the second stop operation use bit data update process, the fixed value "10" is subtracted from the value of the A register by the command "SUB A, 10" on the third line in FIG. 159(a). Then, the subtracted value of the A register is compared with 48 (57-10+1) by the command "CP A, 57-10+1" on the fourth line. Here, it is confirmed that the stop control number is within the range of 10-57. That is, if the value of the A register is less than 10, the command "SUB A, 10" will cause the value of the A register to become a negative value, which is greater than 48 as a 1-byte value. Therefore, if the subtracted value of the A register is less than 10, the carry flag is set to 1 by the command "CP A, 57-10+1". Then, if the carry flag is not 1 by "RET NC" on the fifth line, the routine returns to the routine one level above. If the carry flag is 1 (if the stop control number is within the range of 10 to 57), the following processing is executed.

159(a), the command "LDQ A, (LOW_HIT_NUM)" on the sixth line sets the value of the Q register to the upper 1 byte of the address and sets the lower 1 of the address "_HIT_NUM" storing the stop control number. The byte value is the lower 1 byte of the address, and the value (stop control number) stored at that address is read to the A register. The command "CP A, 34" on the seventh line compares the value of the A register with the fixed value "34". Here, it is confirmed that the stop control number is less than 34. If the value of the A register is less than 34, the command "CP A, 34" sets the carry flag to 1. Then, if the carry flag is not 1 by "RET NC" on the 8th line, the process returns to the routine one level above. If the carry flag is 1 (if the stop control number is less than 34), the rest of the processing is executed and the routine returns to the routine one step above.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 159(a) can be changed as shown in FIG. 159(b). The index "SET_RIG:" on the first line in FIG. 159(b) indicates the head address of the SET_RIG module. By the command "LDQ A, (LOW_HIT_NUM)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_HIT_NUM" storing the stop control number is set to the lower 1 byte of the address. , and the value (stop control number) stored at that address is read to the A register.

Then, as the second stop operation use bit data update process, the fixed value "10" is subtracted from the value of the A register by the command "SUB A, 10" on the third line in FIG. 159(b). By the command "RCP NC, A, 57-10+1" on the 4th line, the subtracted value of the A register is compared with 48 (57-10+1), and if the carry flag is not 1, the routine goes to the next higher routine. return. Here, it is confirmed that the stop control number is within the range of 10 to 57, and if it is not within that range, the processing after that is not performed and the routine returns to the upper step. If the carry flag is 1 (if the stop control number is within the range of 10 to 57), the following processing is executed.

Subsequently, by the command "LDQ A, (LOW_HIT_NUM)" on the fifth line in FIG. 159(b), the value of the Q register is set to the upper 1 byte of the address, and the lower 1 of the address "_HIT_NUM" storing the stop control number. The byte value is the lower 1 byte of the address, and the value (stop control number) stored at that address is read to the A register. The command "RCP NC, A, 34" on the sixth line compares the value of the A register with the fixed value "34", and if the carry flag is not 1, returns to the routine one step above. Here, it is confirmed that the stop control number is less than 34, and if it is 34 or more, the process after that is not performed and the routine returns to the one step above. If the carry flag is 1 (if the stop control number is less than 34), the rest of the processing is executed and the routine returns to the routine one step above.

Here, the total command size of the command group shown in FIG. 159(a) is the command "LDQ A, (LOW_HIT_NUM)" 2 bytes on the 2nd line + the command "SUB A, 10" 2 bytes on the 3rd line + 4 lines. 2nd command "CP A, 57-10+1" 2 bytes + 5th line "RET NC" 1 byte + 6th line command "LDQ A, (LOW_HIT_NUM)" 2 bytes + 7th line command "CP A, 34" 2 bytes + 1 byte of "RET NC" on the 8th line = 12 bytes, and the total execution cycle is: 2nd line 3 cycles + 3rd line 2 cycles + 4th line 2 cycles + 5th line 3 cycles (1 cycle) + 6th line 3 Cycle+7th row 2nd cycle+8th row 3rd cycle (1 cycle)=18 cycles (14 cycles). On the other hand, the total command size of the command group shown in FIG. 159(b) is the second line command "LDQ A, (LOW_HIT_NUM)" 2 bytes + the third line command "SUB A, 10" 2 bytes + 4 lines. 2nd command "RCP NC, A, 57-10+1" 2 bytes + 5th line command "LDQ A, (LOW_HIT_NUM)" 2 bytes + 6th line command "RCP NC, A, 34" 2 bytes = 10 bytes Thus, the total execution cycle is 2nd line 3 cycles+3rd line 2 cycles+4th line 5 cycles (3 cycles)+5th line 3 cycles+6th line 5 cycles (3 cycles)=18 cycles (14 cycles). Therefore, by replacing the command group of FIG. 159(a) with the command group of FIG. 159(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 160 is an explanatory diagram for explaining the PRE_LOT module. The PRE_LOT module shown in FIG. 160 selectively shifts according to the game state and the effect state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. A lottery process is executed when the state is a predetermined value (eg, 5).

The index "PRE_LOT:" on the first line in FIG. 160(a) indicates the start address of the PRE_LOT module. By the command "LDQ A, (LOW_TRG_KND)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_TRG_KND" is set as the lower 1 byte of the address, and stored at that address. read out the value (trigger role type) to the A register.

The command "CP A, @LOT_OFS_1FK" on the third line of FIG. As a result of comparison, if the number is less than 3, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the 4th line, the process returns to the routine one level above. That is, if the value of the A register is less than the fixed value indicating "one fake", the PRE_LOT module ends. If the carry flag is 0, the REG start time setting process, the BIG start time BIG stock lottery process, and the BIG start time setting process are executed, and the process returns to the routine one level above.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 160(a) can be changed as shown in FIG. 160(b). The index "PRE_LOT:" on the first line in FIG. 160(b) indicates the top address of the PRE_LOT module. By the command "LDQ A, (LOW_TRG_KND)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_TRG_KND" is set as the lower 1 byte of the address, and stored at that address. read out the value (trigger role type) to the A register.

The command "RCP C, A, @LOT_OFS_1FK" on the third line in FIG. and if it is less than 3, it returns to the routine one level above. That is, if the value of the A register is less than the fixed value indicating "one fake", the PRE_LOT module ends.

Here, the total command size of the command group shown in FIG. 160(a) is the command "LDQ A, (LOW_TRG_KND)" on the second line 2 bytes + the command "CP A, @LOT_OFS_1FK" on the third line 2 bytes + 3. 1 byte of "RET C" on the line = 5 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 3 cycles on the 4th line (1 cycle) = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 160(b) is the second line command "LDQ A, (LOW_TRG_KND)" 2 bytes + the third line command "RCP C, A, @LOT_OFS_1FK" 2 bytes. = 4 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 5 cycles (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group of FIG. 160(a) with the command group of FIG. 160(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 161 is an explanatory diagram for explaining the REG_LOT module. The REG_LOT module shown in FIG. 161 selectively shifts according to the game state and the effect state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. A lottery process is executed when the state is a predetermined value (eg, 6).

The index "REG_LOT:" on the first line in FIG. 161(a) indicates the start address of the REG_LOT module. By the command "LDQ A, (LOW_TRG_KND)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_TRG_KND" is set as the lower 1 byte of the address, and stored at that address. read out the value (trigger role type) to the A register.

By the command "CP A, @LOT_OFS_PDJ" on the third line of FIG. 161(a), the value of the A register is compared with the fixed value "@LOT_OFS_PDJ" indicating "batting order bell" as the trigger role type, here 5. If it is 5, the zero flag is set and becomes 1. Then, if the zero flag is not 1 by "RET NZ" on the 4th line, the process returns to the routine one step above. That is, if the value of the A register is not a fixed value indicating the "batting order bell", the REG_LOT module is terminated. If the zero flag is 0, the REG remaining navigation count subtraction process and the REG end time setting process are executed, and the routine returns to the upper level.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 161(a) can be changed as shown in FIG. 161(b). The index "REG_LOT:" on the first line in FIG. 161(b) indicates the start address of the REG_LOT module. By the command "LDQ A, (LOW_TRG_KND)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_TRG_KND" is set as the lower 1 byte of the address, and stored at that address. read out the value (trigger role type) to the A register.

The command "RCP NZ, A, @LOT_OFS_PDJ" on the third line in FIG. is compared, and if it is not 5, it returns to the routine one level above. That is, if the value of the A register is not a fixed value indicating the "batting order bell", the REG_LOT module is terminated.

Here, the total command size of the command group shown in FIG. 161(a) is the second line command "LDQ A, (LOW_TRG_KND)" 2 bytes + the third line command "CP A, @LOT_OFS_PDJ" 2 bytes+4. 1 byte of "RET NZ" on the line=5 bytes, and the total execution cycle is 3 cycles on the 2nd line+2 cycles on the 3rd line+3 cycles on the 4th line (1 cycle)=8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 161(b) is the second line command "LDQ A, (LOW_TRG_KND)" 2 bytes + the third line command "RCP NZ, A, @LOT_OFS_PDJ" 2 bytes. = 4 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 5 cycles (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group of FIG. 161(a) with the command group of FIG. 161(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 162 is an explanatory diagram for explaining the BIG_SLT module. The BIG_SLT module shown in FIG. 162 executes the BIG stock lottery process.

The index "BIG_SLT:" on the first line in FIG. 162(a) indicates the start address of the BIG_SLT module. By the command "LDQ A, (LOW_TRG_KND)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_TRG_KND" is set as the lower 1 byte of the address, and stored at that address. read out the value (trigger role type) to the A register.

The command "CP A, @LOT_OFS_LCY" on the third line in FIG. 162(a) compares the value of the A register with a fixed value "@LOT_OFS_LCY" indicating "weak cherry" as the trigger role type, here 6. If it is less than 6, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the 4th line, the process returns to the routine one level above. That is, if the value of the A register is less than the fixed value indicating "weak cherry", the BIG_SLT module is terminated. If the carry flag is 0, stock lottery processing during BIG is executed, and the routine returns to the routine one level above.

Here, if the replacement of FIG. 148 is performed, the command group of FIG. 162(a) can be changed as shown in FIG. 162(b). The index "BIG_SLT:" on the first line in FIG. 162(b) indicates the start address of the BIG_SLT module. By the command "LDQ A, (LOW_TRG_KND)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_TRG_KND" is set as the lower 1 byte of the address, and stored at that address. read out the value (trigger role type) to the A register.

The command "RCP C, A, @LOT_OFS_LCY" on the third line in FIG. is compared, and if it is less than 6, it returns to the routine one level above. That is, if the value of the A register is less than the fixed value indicating "weak cherry", the BIG_SLT module is terminated.

Here, the total command size of the command group shown in FIG. 162(a) is the command "LDQ A, (LOW_TRG_KND)" 2 bytes on the second line + the command "CP A, @LOT_OFS_LCY" 2 bytes on the third line + 4 bytes. 1 byte of "RET C" on the line = 5 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 3 cycles on the 4th line (1 cycle) = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 162(b) is the second line command "LDQ A, (LOW_TRG_KND)" 2 bytes + the third line command "RCP C, A, @LOT_OFS_LCY" 2 bytes. = 4 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 5 cycles (3 cycles) = 8 cycles (6 cycles). Therefore, by replacing the command group of FIG. 162(a) with the command group of FIG. 162(b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 163 is an explanatory diagram for explaining the NAV_SET module. The NAV_SET module illustrated in FIG. 163 executes instruction information setting processing, that is, instruction information type setting processing.

The index "NAV_SET:" on the first line in FIG. 163(a) indicates the start address of the NAV_SET module. By the command "LDQ A, (LOW_YRI_LMP)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_YRI_LMP" is set as the lower 1 byte of the address, and stored at that address. The value (effective lamp flag) is read to the A register.

The command "CP A, @AT_MOD_PRE" on the 3rd line of FIG. 163(a) compares the value of the A register with the fixed value "@AT_MOD_PRE" indicating that the AT state definition is "preparing", here 5. If it is less than 5, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the 4th line, the process returns to the routine one level above. That is, if the value of the A register is less than the fixed value indicating "preparing", the NAV_SET module is terminated. Incidentally, if the carry flag is 0, the remaining processing is executed and the routine returns to the routine one level above.

Here, if the replacement in FIG. 148 is performed, the command group in FIG. 163(a) can be changed as shown in FIG. 163(b). The index "NAV_SET:" on the first line in FIG. 163(b) indicates the top address of the NAV_SET module. By the command "LDQ A, (LOW_YRI_LMP)" on the second line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_YRI_LMP" is set as the lower 1 byte of the address, and stored at that address. The value (effective lamp flag) is read to the A register.

The command "RCP C, A, @AT_MOD_PRE" on the third line in FIG. is compared, and if it is less than 5, it returns to the routine one level above. That is, if the value of the A register is less than the fixed value indicating "preparing", the NAV_SET module is terminated.

Here, the total command size of the command group shown in FIG. 163(a) is the command "LDQ A, (LOW_YRI_LMP)" 2 bytes on the second line + the command "CP A, @AT_MOD_PRE" 2 bytes on the third line + 4 bytes. 1 byte of "RET C" on the line = 5 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 3 cycles on the 4th line (1 cycle) = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 163(b) is the command "LDQ A, (LOW_YRI_LMP" 2 bytes on the second line + the command "RCP C, A, @AT_MOD_PRE" 2 bytes on the third line = 163(a) is 4 bytes, and the total execution cycle is 3 cycles on the 2nd line + 5 cycles (3 cycles) on the 3rd line = 8 cycles (6 cycles). By replacing the commands with the command group, the total command size is reduced by 1 byte.This replacement makes it possible to further shorten the commands and secure the capacity of the control area for game control processing.

<XORQ>
FIG. 164 is a flow chart showing specific processing of the TOK_PRC module. The TOK_PRC module executes the special game management process (see FIG. 36) of step S600. Numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 164, the main CPU 300a loads the special game special symbol determination flag (S1), inverts the loaded special game special symbol determination flag (S2), and saves the inverted special game special symbol determination flag ( S3). Note that step S1 corresponds to step S600-5 in FIG. 36, step S2 corresponds to step S600-7 in FIG. 36, and step S3 corresponds to step S600-9 in FIG.

FIG. 165 is an explanatory diagram for explaining an example of commands for implementing the TOK_PRC module. The flowchart shown in FIG. 164 is realized by the program shown in FIG. 165, for example.

The index "TOK_PRC:" on the first line in FIG. 165(a) indicates the start address of the TOK_PRC module. Then, as a special game management process, the command "LDQ A, (LOW R_STA_TZ)" on the second line of FIG. is the lower 1 byte of the address, and the value (special game special symbol determination flag) stored at that address is read to the A register. The command on the second line corresponds to step S1 in FIG. By the command "XOR 001H" on the 3rd line, the exclusive OR between the read value (special game special symbol determination flag) and the fixed value (here 001H) is calculated. Thereby, the special game special symbol determination flag is reversed. The command on the second line corresponds to step S2 in FIG. Then, according to the command "LDQ (LOW R_STA_TZ), A" on the fourth line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_STA_TZ" is set to the lower 1 byte of the address, and the address , store the value of the A register. Such a command on the fourth line corresponds to step S3 in FIG.

Here, the command group of FIG. 165(a) can be changed as shown in FIG. 165(b). The index "TOK_PRC:" on the first line in FIG. 165(b) indicates the start address of the TOK_PRC module. Then, when the special game management process is executed, the value of the Q register is set to the upper 1 byte of the address and the value of the lower 1 byte of the address "R_STA_TZ" is set to the address by the command "XORQ (LOW R_STA_TZ), 001H" on the second line. , and the exclusive OR of the value (special game special symbol determination flag) stored at that address and the fixed value (here, 001H) is calculated, and the calculation result is stored at the same address.

Here, the total command size of the command group shown in FIG. 165(a) is the second line command "LDQ A, (LOW R_STA_TZ)" 2 bytes + the third line command "XOR 001H" 2 bytes + the fourth line command "LDQ (LOW R_STA_TZ), A" 2 bytes=6 bytes, and the total execution cycle is 2nd line 3 cycles+3rd line 2 cycles+4th line 3 cycles=8 cycles. On the other hand, the total command size of the command group shown in FIG. 165(b) is "XORQ (LOW R_STA_TZ), 001H" 4 bytes=4 bytes, and the total execution cycle is 2nd row 7 cycles=7 cycles. Therefore, by replacing the command group of FIG. 165(a) with the command group of FIG. 165(b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

165(a) and 165(b), the command group occupying three lines (2nd to 4th lines) in FIG. 165(a) is 165(b) can be expressed in one line (second line), which makes it possible to reduce the number of commands themselves and the design load.

Also, here, in the example of FIG. 165(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 165(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

<CPQ>
FIG. 166 is a flow chart showing specific processing of the TEF_SEL module. The TOK_PRC module is executed when setting the special electric role game timer for the closing effective time of the large winning opening in the large winning opening opening control process (see FIG. 47) (step S720-9). Numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 166, the main CPU 300a sets the large winning opening closing effective time of the small winning game (S1), loads the special symbol determination flag (S2), and uses the loaded special symbol determination flag and the small winning symbol. It compares with a predetermined value (here, 007H) indicating that there is (S3). The special symbol determination flag is set to 00H in the case of a losing symbol, any of 01H to 06H in the case of a big winning symbol, and any of 07H to 09H in the case of a small winning symbol.

Then, if the comparison result is a small winning pattern (YES in S4), the TEF_SEL module is ended (S6), and if the comparison result is not a small winning pattern (NO in S4), that is, if it is a big winning pattern, A big winning opening closing valid time table for the big winning game is set (S5), and the TEF_SEL module is terminated (S6).

FIG. 167 is an explanatory diagram for explaining an example of commands for realizing the TEF_SEL module. The flowchart shown in FIG. 166 is realized by the program shown in FIG. 167, for example.

The index "TEF_SEL:" on the first line in FIG. 167(a) indicates the top address of the TEF_SEL module. Then, the command "LD HL, @TMR_TDN_EF3" on the second line in FIG. 167(a) stores the value of "@TMR_TDN_EF3" in the HL register. It should be noted that, in "@TMR_TDN_EF3", the valid time for closing the big winning opening of the small winning game is set. Such a command on the first line corresponds to step S1 in FIG.

The command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the third line in FIG. , and the value (special symbol determination flag) stored at that address is read to the A register. Such a command on the third line corresponds to step S2 in FIG.

By the command "CP A, @ZUG_SML1" on the 4th line of FIG. 167 (a), the value of the A register and the fixed value "@ZUG_SML1" indicating the small winning design 1 designation data (small winning design), here, 07H is compared, and if the value of the A register is less than 07H, the carry flag is set to 1. Such a command on the fourth line corresponds to step S3 in FIG.

Then, if the carry flag is not 1 by the command "RET NC" on the fifth line of FIG. That is, if the value of the A register is equal to or greater than the small winning symbol 1 designating data, the TEF_SEL module is terminated. The command on the fifth line corresponds to YES in step S4 and step S6 in FIG.

On the other hand, if the carry flag is 1, the command "LDQ A, (LOW R_TDN_FLG)" on the sixth line in FIG. The value of 1 byte is set as the lower 1 byte of the address, and the value (special electric accessory designation flag) stored at that address is read to the A register, and the command "LD HL, D_EFF_TMR- 2” sets the start address “D_EFF_TMR-2” of the 1-byte data group to be the transfer source in the HL register.

The WORDSEL module is called as a subroutine by the command "RST WORDSEL" on the eighth line of FIG. After the value is read into the A register, the command "RET" on the ninth line of FIG. 167(a) returns to the routine one level above. It should be noted that, in the subsequent routine (in subsequent processing), the valid time for closing the big winning opening of the big winning game is set to the timer. The sixth to eighth lines correspond to step S5 in FIG.

Here, the command group of FIG. 167(a) can be changed as shown in FIG. 167(b). 167(a) will be omitted here, and only the different processing in FIG. 167(b) will be described.

The command "CPQ (LOW R_ZUG_CHK_FIX), @ZUG_SML1" on the third line in FIG. byte, and the value (special design determination flag) stored at that address is compared with the fixed value "@ZUG_SML1" indicating the small winning design 1 designation data (small winning design), here, 07H, and less than 07H If there is, the carry flag is set to 1. Such commands on the third line correspond to steps S2 and S3 in FIG. Such a command has a command size of "3" and an execution cycle of "4".

Here, the total command size of the command group shown in FIG. 167(a) is the second line command "LD HL, @TMR_TDN_EF3" 3 bytes + the third line command "LDQ A, (LOW R_ZUG_CHK_FIX)" 2 bytes + 4 lines. 2nd command "CP A, @ZUG_SML1" 2 bytes + 5th line "RET NC" 1 byte + 6th line command "LDQ A, (LOW R_TDN_FLG)" 2 bytes + 7th line command "LD HL, D_EFF_TMR-2" " 3 bytes + command "RST WORDSEL" 1 byte on line 8 + "RET" 1 byte on line 9 = 15 bytes, and the execution cycle is 3 cycles on line 2 + 2 cycles on line 3 + 2 cycles on line 4 + 3 Cycle (1 cycle) + 6th row 2nd cycle + 7th row 3rd cycle + 8th row 4th cycle + 9th row 3rd cycle = 22 cycles (20 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RET NC" does not move to the routine one level higher.

On the other hand, the total command size of the command group shown in FIG. 167(b) is: 2nd line command "LD HL, @TMR_TDN_EF3" 3 bytes + 3rd line command "CPQ (LOW R_ZUG_CHK_FIX), @ZUG_SML1" 3 bytes + 4 lines 1st "RET NC" 1 byte + 5th line command "LDQ A, (LOW R_TDN_FLG)" 2 bytes + 6th line command "LD HL, D_EFF_TMR-2" 3 bytes + 7th line command "RST WORDSEL" 1 byte + 8th line "RET" 1 byte = 14 bytes, and the execution cycle is: 2nd line 3 cycles + 3rd line 4 cycles + 4th line 3 cycles (1 cycle) + 5th line 2 cycles + 6th line 3 cycles + 7th line 4 Cycle+8th row 3rd cycle=22 cycles (20 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RET NC" does not move to the routine one level higher.

Therefore, by replacing the command group of FIG. 167(a) with the command group of FIG. 167(b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

167(a) and 167(b), the command group occupying two lines (third and fourth lines) in FIG. 167(b) can be expressed in one line (the third line), which makes it possible to reduce the number of commands themselves and the design load.

Also, here, in the example of FIG. 167(b), the A register is not used in the command on the third line. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 167(a), if the A register was already used when executing the command on the third line, it was necessary to stack and save the value of the A register. Since the A register is not used, no stack processing is required. In this way, it becomes possible to effectively use resources.

<JTANDQ>
FIG. 168 is a flow chart showing specific processing of the SWI_PRC module. The SWI_PRC module executes the switch management process of step S500 (see FIG. 28). Numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 168, the main CPU 300a determines whether the first variable starting port detection switch 120Bs is detected (S1), and if the first variable starting port detection switch 120Bs is detected (YES in S1). , 1st start opening passage processing (S2) and confirmation processing (S3) at the time of normal electric accessory winning is executed. On the other hand, if the first variable starting opening detection switch 120Bs is not detected (NO in S1), the first starting opening passage processing (S2) and the normal electric accessory winning confirmation processing (S3) are skipped. Note that step S1 corresponds to step S500-7 in FIG. 28, step S2 corresponds to step S520 in FIG. 28, and step S3) corresponds to step S500-9 in FIG.

FIG. 169 is an explanatory diagram for explaining an example of commands for implementing the SWI_PRC module. The flowchart shown in FIG. 168 is realized by the program shown in FIG. 169, for example.

The index "SWI_PRC:" on the first line in FIG. 169(a) indicates the head address of the SWI_PRC module. Then, the command "LDQ A, (LOW R_IN3_PON)" on the second line in FIG. 1 byte, and the value stored at that address is read to the A register. Here, in the value stored at the same address, for example, the least significant bit holds the detection result of the first fixed starting opening detection switch 120As (input section), and the second lower bit holds the second starting opening detection switch 120As. The detection result of the opening detection switch 122s (input section) is held, and the detection result of the first variable start opening detection switch 120Bs (input section) is held in the lower third bit. Each of these bits becomes "1" when the detection switch detects that the game ball has entered, and becomes "0" when the detection switch does not detect that the game ball has entered.

The command "AND A, @IN3_ST2_BIT" on the third line calculates the logical product of the read value and the fixed value "@IN3_ST2_BIT (here, 00000100b). As a result, all bits other than the lower third bit of the read value are set to 0. If the third low-order bit of the read value is 0, the zero flag is set to 1, and if the third low-order bit of the read value is 1, the zero flag is set to 0. That is, the first variable start. If the detection result of the opening detection switch 120Bs is 1 (if the game ball is detected), the zero flag is set to 0, and if the detection result of the first variable start opening detection switch 120Bs is 0 (the game ball is Zero flag=0 if no incoming ball is detected.

Then, if the zero flag is 1 (Z) by the command "JR Z, SWI_PRC_20" on the 4th line, the process moves to SWI_PRC_20 (7th line). The commands on the second to fourth lines correspond to step S1 in FIG.

On the other hand, if the zero flag is not 1 by the command "JR Z, SWI_PRC_20" on the fourth line, the STA_PAS module is called as a subroutine by the command "CALLF STA_PAS" on the fifth line. is executed. The fifth line command corresponds to step S2 in FIG. Also, the FDN_CHK module is called as a subroutine by the command "CALLF FDN_CHK" on the 6th line, and the FDN_CHK module executes normal electric accessory winning confirmation processing. The sixth line command corresponds to step S3 in FIG.

Here, the command group of FIG. 169(a) can be changed as shown in FIG. 169(b). 169(a) will be omitted here, and only the different processing in FIG. 169(b) will be described.

By command "JTANDQ Z, (LOW R_IN3_PON), @IN3_ST2_BIT, SWI_PRC_20" on the second line in FIG. The lower 1 byte of the address is used, and the logical AND of the value stored at that address and the fixed value "@IN3_ST2_BIT" is calculated. The command on the second line corresponds to step S1 in FIG. Such a command has a command size of "4" and an execution cycle of "5 (6)". Note that the number of cycles in parentheses indicates the execution cycle when the zero flag is 1 and the process moves to SWI_PRC_20.

Here, the total command size of the command group shown in FIG. 169(a) is the second line command "LDQ A, (LOW R_IN3_PON)" 2 bytes + the third line command "AND A, @IN3_ST2_BIT" 2 bytes + 4 lines. 2 bytes of the 2nd command "JR Z, SWI_PRC_20" + 2 bytes of the command "CALLF STA_PAS" of the 5th line + 2 bytes of the command "CALLF FDN_CHK" of the 6th line = 10 bytes, and the total execution cycle is 3 cycles of the 2nd line + 3 lines 2nd cycle + 4th row 2 (3) cycles + 5th row 4 cycles + 6th row 4 cycles = 15 (16) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the zero flag is 1 and the process moves to SWI_PRC_20.

On the other hand, the total command size of the command group shown in FIG. 169(b) is the command "JTANDQ Z, (LOW R_IN3_PON), @IN3_ST2_BIT, SWI_PRC_20" 4 bytes on the second line + the command "CALLF STA_PAS" 2 bytes on the third line. + 2 bytes of the command "CALLF FDN_CHK" on the 4th line = 8 bytes, and the total execution cycle is 5 (6) cycles on the 2nd line + 4 cycles on the 3rd line + 4 cycles on the 4th line = 13 (14) cycles.

Therefore, by replacing the command group of FIG. 169(a) with the command group of FIG. 169(b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least 2 cycles. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

169(a) and 169(b), the command group occupying 3 lines (2nd to 4th lines) in FIG. 169(a) is 169(b) can be expressed in one line (second line), which makes it possible to reduce the number of commands themselves and the design load.

Also, in the example of FIG. 169(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 169(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

<OUT>
FIG. 170 is a flow chart showing specific processing of the CPUINIT module. The CPUINIT module executes the CPU initialization process (see FIG. 22). Numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 170, the main CPU 300a executes access permission processing to permit access to the RAM 300c (S1). Note that step S1 corresponds to step S100-9 in FIG.

FIG. 171 is an explanatory diagram for explaining an example of commands for implementing the CPUINIT module. The flowchart shown in FIG. 170 is realized by the program shown in FIG. 171, for example.

The index "CPUINIT:" on the first line in FIG. 171(a) indicates the start address of the CPUINIT module. Then, the command "LD A, (@RAMENBL)" on the second line in FIG. 171(a) reads the fixed value "@RAMENBL" (here, 1) indicating permission of access to the A register. Then, the command "OUT (@RAP____), A" on the third line of FIG. A fixed value "@RAP____" indicating the lower 1 byte of the address is set as the lower 1 byte, and the value (1) of the A register is output to that address. Note that the upper 1 byte (for example, "FEH") of the address of the RAM access protect register port (internal register I/O port) is preset in the U register.

Here, the command group of FIG. 171(a) can be changed as shown in FIG. 171(b). 171(a) will be omitted here, and only the different processing in FIG. 171(b) will be described.

The command "OUT (@RAP____),@RAMENBL" on the second line in FIG. 171(b) sets the value of the U register to the upper 1 byte of the address, and the address of the RAM access protect register port (internal register I/O port). The fixed value "@RAP____" indicating the lower 1 byte of . Such a command has a command size of "3" and an execution cycle of "4".

Here, the total command size of the command group shown in FIG. 171(a) is the second line command "LD A, (@RAMENBL)" 2 bytes + the third line command "OUT (@RAP_____), A" 2 bytes. = 4 bytes, and the total execution cycle is 2 cycles on the 2nd line + 3 cycles on the 3rd line = 5 cycles.

On the other hand, the total command size of the group of commands shown in FIG. = 4 cycles.

Therefore, by replacing the command group of FIG. 171(a) with the command group of FIG. 171(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

171(a) and 171(b), the command group that occupied two lines (2nd to 3rd lines) in FIG. 171(b) can be expressed in one line (second line), which makes it possible to reduce the number of commands themselves and the design load.

Also, in the example of FIG. 171(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 171(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

FIG. 172 is an explanatory diagram for explaining the TMR_IPT module. The TMR_IPT module shown in FIG. 172 executes timer interrupt processing shown in FIG.

The index "TMR_IPT:" on the first line in FIG. 172(a) indicates the top address of the TMR_IPT module. Then, the command "LD A, @TOCRVAL" on the second line in FIG. 172(a) reads the fixed value "@TOCRVAL" (here, 1) indicating permission of access to the A register. Then, the command "OUT (@PTOCR__), A" on the third line in FIG. A fixed value "@PTOCR__" indicating the lower 1 byte of the address is set as the lower 1 byte of the address, and the value (1) of the A register is output to that address. Note that the upper 1 byte (for example, "FEH") of the address of the RAM access protect register port (internal register I/O port) is preset in the U register.

Here, the command group of FIG. 172(a) can be changed as shown in FIG. 172(b). 172(a) will be omitted here, and only the different processing in FIG. 172(b) will be described.

The command "OUT (@PTOCR__), @TOCRVAL" on the second line in FIG. The fixed value "@PTOCR__" indicating the lower 1 byte of the address is set as the lower 1 byte of the address, and the fixed value "@TOCRVAL", that is, 1 is output to that address. Such a command has a command size of "3" and an execution cycle of "4".

Here, the total command size of the command group shown in FIG. 172(a) is: command "LD A, @TOCRVAL" 2 bytes on the second line + command "OUT (@PTOCR__), A" 2 bytes on the third line = 4 bytes, and the total execution cycle is 2 cycles on the 2nd line + 3 cycles on the 3rd line = 5 cycles.

On the other hand, the total command size of the group of commands shown in FIG. = 4 cycles.

Therefore, by replacing the command group of FIG. 172(a) with the command group of FIG. 172(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

172(a) and 172(b), the command group occupying two lines (2nd to 3rd lines) in FIG. 172(a) is 172(b) can be expressed in one line (second line), which makes it possible to reduce the number of commands themselves and the design load.

Also, in the example of FIG. 172(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 172(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

<LDQ>
FIG. 173 is a flow chart showing specific processing of the FZ_SPN module. The FZ_SPN module executes the normal symbol fluctuation process (see FIG. 53). Numerical values of step S in this figure are used only in the explanation of this figure.

As shown in FIG. 173, the main CPU 300a saves the normal symbol stop symbol number (counter value) in the normal symbol display symbol counter. (S1). Note that step S1 corresponds to step S820-9 in FIG.

FIG. 174 is an explanatory diagram for explaining an example of commands for realizing the FZ_SPN module. The flowchart shown in FIG. 173 is realized by the program shown in FIG. 174, for example.

The index "FZ_SPN:" on the first line in FIG. 174(a) indicates the start address of the FZ_SPN module. Then, according to the command "LDQ A, (LOW R_FZ_STP)" on the second line in FIG. 1 byte, and the value (normal symbol stop symbol number) stored at that address is read to the A register.

Then, the command "LDQ (LOW R_FZ_DSP), A" on the second line in FIG. It is assumed to be 1 byte, and the value of the A register is stored at that address (the address of the normal symbol display symbol counter).

Here, the command group of FIG. 174(a) can be changed as shown in FIG. 174(b). 174(a) will be omitted here, and only the different processing in FIG. 174(b) will be described.

The command "LDQ (LOW R_FZ_DSP), (LOW R_FZ_STP)" on the second line in FIG. The value stored at that address is stored at that address with the value of the Q register as the upper 1 byte of the address and the value of the lower 1 byte of the address "R_FZ_DSP" as the lower 1 byte of the address.

Here, the total command size of the command group shown in FIG. 174(a) is the second line command "LDQ A, (LOW R_FZ_STP)" 2 bytes + the third line command "LDQ (LOW R_FZ_DSP), A" 2 bytes. = 4 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 3 cycles = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 6 cycles=6 cycles.

Therefore, as can be understood by comparing FIG. 174(a) and FIG. 174(b), the command group occupying two lines (second and third lines) in FIG. Without changing the command size and total execution cycle, it can be expressed in one line (second line) in FIG. .

Also, in the example of FIG. 174(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 174(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

FIG. 175 is an explanatory diagram for explaining an example of commands for implementing the CPUINIT module. Here, the special game progresses in one of the low-probability game state and the high-probability game state. The gaming machine 100 is provided with a display indicating that the game state is the high-probability game state, and when the game state is the high-probability game state, the display lights up. When the high-probability gaming state is not notified to the player when power is restored (so-called hiding), the display can be hidden. At this time, if the presence or absence of lighting of the display is determined based on the actual game state, the display will be turned on if the game state at the time of power failure recovery is a high probability game state. Therefore, a flag indicating that the player is in hiding is prepared from the time of restoration of power supply until the first big win game is started, and whether or not the indicator is lit is determined based on the flag.

The index "CPUINIT:" on the first line in FIG. 175(a) indicates the start address of the CPUINIT module. Then, the command "LDQ A, (LOW R_KAK_FLG)" on the second line in FIG. 1 byte, and the value (1 if high probability gaming state, 0 if not high probability gaming state) stored at that address (address of flag indicating whether or not high probability gaming state) to A register read out.

Then, according to the command "LDQ (LOW R_KAK_HOT), A" on the third line in FIG. 1 byte, and the value of the A register is stored at that address (the address of the flag indicating that it is latent).

Here, the command group of FIG. 175(a) can be changed as shown in FIG. 175(b). 175(a) will be omitted here, and only the different processing in FIG. 175(b) will be described.

The command "LDQ (LOW R_KAK_HOT), (LOW R_KAK_FLG)" on the second line in FIG. The value stored at the address is set to the lower 1 byte, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_KAK_HOT" is set to the lower 1 byte of the address and stored at that address.

Here, the total command size of the command group shown in FIG. 175(a) is the second line command "LDQ A, (LOW R_KAK_FLG)" 2 bytes + the third line command "LDQ (LOW R_KAK_HOT), A" 2 bytes. = 4 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 3 cycles = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 6 cycles=6 cycles.

Therefore, as can be understood by comparing FIG. 175(a) and FIG. 175(b), the command group occupying two lines (second to third lines) in FIG. 175(b) can be expressed in one line (second line), which makes it possible to reduce the number of commands themselves and the design load.

Also, in the example of FIG. 175(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 175(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

FIG. 176 is an explanatory diagram for explaining an example of commands for realizing the EXE_SET module. The EXE_SET module shown in FIG. 176 executes the execution flag setting process shown in step S2400-11 in FIG.

The index "EXE_SET:" on the first line in FIG. 176(a) indicates the head address of the EXE_SET module. Then, the command "LDQ A, (LOW AT_NXT)" on the second line in FIG. The value (value indicating the effect state of the next game) stored in the address (the address of the value indicating the effect state of the next game) is read to the A register.

Then, according to the command "LDQ (LOW AT_MOD), A" on the third line in FIG. 1 byte, and the value of the A register is stored at that address (the address of the value indicating the effect state of the game).

Here, the command group of FIG. 176(a) can be changed as shown in FIG. 176(b). 176(a) will be omitted here, and only the different processing in FIG. 176(b) will be described.

The command "LDQ (LOW AT_MOD), (LOW AT_NXT)" on the second line in FIG. The value stored at that address is stored at that address with the value of the Q register as the upper 1 byte of the address and the value of the lower 1 byte of the address "AT_MOD" as the lower 1 byte of the address.

Here, the total command size of the command group shown in FIG. 176(a) is the second line command "LDQ A, (LOW AT_NXT)" 2 bytes + the third line command "LDQ (LOW AT_MOD), A" 2 bytes. = 4 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 3 cycles = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 6 cycles=6 cycles.

Therefore, as can be understood by comparing FIG. 176(a) and FIG. 176(b), the command group that occupied two lines (second and third lines) in FIG. 176(b) can be expressed in one line (second line), which makes it possible to reduce the number of commands themselves and the design load.

Also, in the example of FIG. 176(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 176(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

<LDIN>
FIG. 177 is a flow chart showing specific processing of the HPT_GRP module. The HPT_GRP module executes the reach group determination process of step S612-7 in the special symbol variation number determination process (see FIG. 39). Numerical values of step S in this figure are used only in the explanation of this figure. Also, during the description of the HPT_GRP module, the first register is the HL register and the other registers are the BC or A registers.

In the reach group determination process, the address of the reach group determination random number determination table determined in advance according to the type of hold, the number of holds, the game state, etc. is stored in advance in the HL register.

As shown in FIG. 177, the main CPU 300a loads the comparison value stored at the address (table address) shown in the HL register into the BC register and adds 2 to the value of the HL register (S1). As will be described later in detail, the reach group determination random number determination table stores a set of comparison values of 2-byte length and group numbers of 1-byte length, and these sets are continuously stored in multiple order. . Therefore, here, by adding 2 to the value of the HL register after loading the comparison value, the HL register becomes an address value in which the group number stored next to the loaded comparison value is stored.

Thereafter, the main CPU 300a compares the comparison value loaded in the BC register with the reach group determination random number (random value) preloaded in the DE register (S2), and determines the reach stored in the address indicated in the HL register. Load the group number (S3).

After that, the main CPU 300a adds 1 to the value of the HL register (table address) (S4). Here, by adding 1 to the value of the HL register after loading the group number, the HL register becomes an address value in which the comparison value stored next to the loaded group number is stored.

Then, if the comparison value in step S2 is equal to or less than the reach group determination random number (random value) (YES in S5), the main CPU 300a returns the process to step S1, and the comparison value is the reach group determination random number. If not below (NO in S5), the HPT_GRP module is terminated (S6).

FIGS. 178(a) and 178(b) are explanatory diagrams for explaining an example of commands for realizing the HPT_GRP module. FIG. 178(c) is an explanatory diagram for explaining an example of the reach group determination random number determination table. The flowchart shown in FIG. 177 is implemented by, for example, the programs shown in FIGS. 178(a) and 178(b). First, after explaining the reach group determination random number determination table in FIG. 178(c), commands for realizing the HPT_GRP module shown in FIGS. 178(a) and (b) will be explained.

A table starting from the index “D_GRP_SEL — 00:” in FIG. 178(c) indicates the head address of any reach group determination random number determination table. The fixed value "8999" on the second line, the fixed value "9099" on the fourth line, and the fixed value "9299" on the sixth line are comparison values of 2-byte length. @D_MOD_SEL_00", the fixed value "@D_MOD_SEL_01" on the fifth line, and the fixed value "@D_MOD_SEL_02" on the seventh line are group numbers each having a 1-byte length. In the reach group determination random number determination table, a set of a 2-byte comparison value and a 1-byte group number corresponding to the comparison value are sequentially stored in order.

The index "HPT_GRP:" on the first line in FIG. 178(a) indicates the head address of the HPT_GRP module. Then, the 2-byte length value (comparison value) stored at the address indicated by the HL register is read (loaded) into the BC register by the command "LDIN BC, (HL)" on the second line in FIG. 178(a). ), and 2 is added to the value of the HL register. The command on the second line corresponds to step S1 in FIG. The HL register is pre-loaded with the address of the reach group determination random number determination table determined in advance.

Then, the command "CP BC, DE" on the third line in FIG. 178(a) compares the value stored in the BC register (comparison value) with the value stored in the DE register (reach group determination random number). do. Here, if the value stored in the BC register is less than or equal to the value stored in the DE register, the zero flag (if equal) or the carry flag (if less than) is set to 1. A reach group determination random number is stored in advance in the DE register. Such a command on the third line corresponds to step S2 in FIG.

After that, the 1-byte length value (group number) stored at the address indicated by the HL register is read to the A register by the command "LD A, (HL)" on the fourth line in FIG. 178(a). Such a command on the fourth line corresponds to step S3 in FIG. Then, 1 is added to the value of the HL register by the command "INC HL" on the fifth line in FIG. 178(a). The command on the fifth line corresponds to step S4 in FIG.

Subsequently, when the command "JLS HPT_GRP" on the 6th line in FIG. , and if the zero flag and the carry flag are not set to 1, the command "RET" on the 7th line in FIG. 178(a) terminates the HPT_GRP module. The commands on the 6th and 7th lines correspond to steps S5 and S6 in FIG. Then, when the HPT_GRP module ends, the group number corresponding to the range shown in FIG. 9 is stored in the A register.

Here, the command group of FIG. 178(a) can be changed as shown in FIG. 178(b). 178(a) will be omitted, and only the different processing in FIG. 178(b) will be described.

The 1-byte length value (group number) stored at the address indicated by the HL register is read to the A register by the command "LDIN A, (HL)" on the fourth line in FIG. 178(b), and the value of the HL register is incremented by 1. The commands on the fourth line correspond to steps S3 and S4 in FIG. Such a command has a command size of "1" and an execution cycle of "2".

Here, the total command size of the command group shown in FIG. Command "LD A, (HL)" 1 byte + Command "INC HL" 1 byte on 5th line + Command "JLS HPT_GRP" 3 bytes on 6th line + Command 'RET' 1 byte on 7th line = 10 bytes, total execution The cycle is 2nd row 4 cycles+3rd row 2 cycles+4th row 2 cycles+5th row 1 cycle+6th row 4(3) cycles+7th row 3 cycles=16(15) cycles. Note that the number of cycles in parentheses indicates the execution cycle when not moved by the command "JLS HPT_GRP".

On the other hand, the total command size of the command group shown in FIG. "LDIN A, (HL)" 1 byte + 5th line command "JLS HPT_GRP" 3 bytes + 6th line command "RET" 1 byte = 9 bytes, total execution cycle is 2nd line 4 cycles + 3rd line 2 Cycle + 4th row 2 cycles + 5th row 4 (3) cycles + 6th row 3 cycles = 15 (14) cycles. Note that the number of cycles in parentheses indicates the execution cycle when not moved by the command "JLS HPT_GRP".

Therefore, by replacing the command group of FIG. 178(a) with the command group of FIG. 178(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

178(a) and 178(b), the command group occupying two lines (4th and 5th lines) in FIG. 178(a) is 178(b) can be expressed in one line (fourth line), which makes it possible to reduce the number of commands themselves and the design load.

In the example of FIG. 178(b), when obtaining a desired 2-byte length value or 1-byte length value in a table in which a plurality of values with different byte lengths are alternately arranged, the value of the HL register is 2-addition and 1-addition can be executed with the same command "LDIN", and the design load can be reduced.

FIG. 179 is an explanatory diagram for explaining the E_ILGER module. The E_ILGER module shown in FIG. 179 executes the fraud monitoring process shown in step S3100-19 in FIG.

The index "E_ILGER:" on the first line in FIG. 179(a) indicates the start address of the E_ILGER module. The command "LD HL, _EX_ILTM" on the second line reads the address "EX_ILTM" for storing the illegal insertion monitoring timer to the HL register.

After that, the command "LD A, (HL)" on the third line in FIG. 179(a) reads the 1-byte length value (unauthorized insertion monitoring timer) stored at the address indicated by the HL register to the A register. Then, 1 is added to the value of the HL register by the command "INC HL" on the fourth line in FIG. 179(a). Subsequently, if the value of the A register is 0 (if the unauthorized input monitoring timer is 0) by the command "JT Z, A, E_ILGER01" on the fifth line of FIG. and move to the index "E_ILGER01:" on the 6th line, and if the value of the A register is not 0, the process moves to the next command after the current command.

Here, the command group of FIG. 179(a) can be changed as shown in FIG. 179(b). 179(a) will be omitted here, and only the different processing in FIG. 179(b) will be described.

By command "LDIN A, (HL)" on the 3rd line in FIG. Add 1 to the value of Such a command has a command size of "1" and an execution cycle of "2".

Here, the total command size of the command group shown in FIG. 179(a) is the command "LD HL, _EX_ILTM" 3 bytes on the 2nd line + the command "LD A, (HL)" 1 byte on the 3rd line + 4th line command "INC HL" 1 byte + 5th line command "JT Z, A, E_ILGER01" 2 bytes = 7 bytes. 3 (2) cycles = 9 (8) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the command "JT Z, A, E_ILGER01" does not move.

On the other hand, the total command size of the command group shown in FIG. The command "JT Z, A, E_ILGER01" 2 bytes=6 bytes, and the total execution cycle is 2nd line 3 cycles+3rd line 2 cycles+4th line 3(2) cycles=8(7) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the command "JT Z, A, E_ILGER01" does not move.

Therefore, by replacing the command group of FIG. 179(a) with the command group of FIG. 179(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

179(a) and 179(b), the command group occupying two lines (3rd to 4th lines) in FIG. 179(a) is 179(b) can be expressed in one line (the third line), which makes it possible to reduce the number of commands themselves and the design load.

FIG. 180 is an explanatory diagram for explaining the E_LEVOT module. The E_LEVOT module shown in FIG. 180 is a subroutine called in the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the test signal transmission process when the lever is depressed.

The index "E_LEVOT:" on the first line in FIG. 180(a) indicates the start address of the E_LEVOT module. The command "LD HL, T_EXM_STP" on the second line reads the address "T_EXM_STP" for storing the test stop information transmission table to the HL register. In this test stop information transmission table, values of six 1-byte test signals are continuously stored as one set, and a plurality of sets are continuously stored.

After that, the value of the A register is added to the value of the HL register by the command "ADDWB HL, A" on the third line in FIG. 180(a), and the value of the HL register is updated. A value obtained by multiplying the instruction information type by 6 is stored in the A register. Therefore, here, the value of the HL register indicates one set of head addresses corresponding to the instruction information type in the test stop information transmission table.

Then, the fixed value "6" is read to the B register by the command "LD B, 6" on the fourth line. The index "E_LEVOT01:" on the fifth line in FIG. 180(a) indicates the address of the index "E_LEVOT01".

The 1-byte length value (test signal value) stored at the address indicated by the HL register is read to the A register by the command "LD A, (HL)" on the sixth line in FIG. 180(a). 180(a), the command "OUT (@S2DT__), A" on the 7th line sets the value of the U register to the upper 1 byte of the address, and the RAM access protect register port (internal register I/O port). A fixed value "@S2DT__" indicating the lower 1 byte of the address is set as the lower 1 byte, and the value of the A register is output to that address.

The value of the HL register is incremented by 1 by the command "INC HL" on the eighth line in FIG. 180(a). Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ E_LEVOT01" on the ninth line of FIG. , if the decremented result is 0, the process is shifted to the command following the command.

Here, the command group of FIG. 180(a) can be changed as shown in FIG. 180(b). 180(a) will be omitted here, and only the different processing in FIG. 180(b) will be described.

By the command "LDIN A, (HL)" on the 6th line in FIG. Add 1 to the value of Such a command has a command size of "1" and an execution cycle of "2".

Here, the total command size of the command group shown in FIG. "LD B, 6" 2 bytes + 6th line command "LD A, (HL)" 1 byte + 7th line command "OUT (@S2DT__), A" 2 bytes + 8th line command "INC HL" 1 byte + 2 bytes of the command "DJNZ E_LEVOT01" on the 9th line = 12 bytes. Cycles+3 (2) cycles in the ninth row=15 (14) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the command "DJNZ E_LEVOT01" does not move.

On the other hand, the total command size of the command group shown in FIG. LD B, 6" 2 bytes + 6th line command 'LDIN A, (HL)' 1 byte + 7th line command 'OUT (@S2DT__), A' 2 bytes + 5th line command 'DJNZ E_LEVOT01' 2 bytes = 11 bytes, and the total execution cycle is: 2nd line 3 cycles + 3rd line 1 cycle + 4th line 2 cycles + 6th line 2 cycles + 7th line 3 cycles + 9th line 3 (2) cycles = 14 (13) cycles . Note that the number of cycles in parentheses indicates the execution cycle when the command "DJNZ E_LEVOT01" does not move.

Therefore, by replacing the command group of FIG. 180(a) with the command group of FIG. 180(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. In particular, in the example of FIG. 180(a), if the value of the B register in the command "DJNZ E_LEVOT01" is 2 or more, the difference in total execution cycles increases by the amount of the value multiplied by one cycle. The amount of reduction in the total execution cycle of b) is also large. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Also, as can be understood by comparing FIGS. 180(a) and 180(b), the command group occupying two lines (6th and 8th lines) in FIG. In 180(b), it can be expressed in one line (sixth line), and it is possible to reduce the number of commands themselves and the design load.

<LDQP>
FIG. 181 is a flow chart showing specific processing of the SBC_OUT module. The SBC_OUT module executes the subcommand transmission process (see FIG. 23) of step S100-65. Numerical values of step S in this figure are used only in the explanation of this figure.

Here, the subcommand is set in the transmission buffer in a plurality of processes in interrupt processing, and is transmitted in subcommand transmission processing. Here, the transmission buffer is, for example, a 96-byte ring buffer, subcommands are set in order in a plurality of processes, and in the subcommand transmission process, the subcommands that are set first are sequentially transmitted to the sub control board 330. FIFO.

As shown in FIG. 181, the main CPU 300a reads the value of the subcommand write pointer into the A register (S1), and compares the value of the subcommand write pointer and the value of the subcommand read pointer (S2). Here, if the value of the subcommand write pointer and the value of the subcommand read pointer are the same, that is, if there is no unsent subcommand, the zero flag is set to 1; , the zero flag is not set to 1.

If the zero flag is 1 (YES in S3), the main CPU 300a terminates the SBC_OUT module. Each lower byte is read out to the DE register (S4), and the value of the subcommand read pointer is incremented by 1 if it is less than the subcommand pointer upper limit value and cleared to zero if it is equal to or greater than the subcommand pointer upper limit value by count-up processing, which is a general-purpose module ( S5).

After that, the main CPU 300a reads the address of the subcommand buffer (transmission buffer) to the HL register (S6), executes the word data selection process (S7), and then reads the SCU1 data register for transmitting the subcommand. The command is output (S8), the subsequent command is read to the A register (S9), the subsequent command is output to the SCU1 data register (S10), and the SBC_OUT module is terminated (S11).

FIG. 182 is an explanatory diagram for explaining an example of commands for realizing the SBC_OUT module.

The index "SBC_OUT:" on the first line in FIG. 182(a) indicates the top address of the SBC_OUT module. Then, according to the command "LDQ A, (LOW R_SBC_WPT)" on the second line in FIG. 1 byte, and the value stored at that address (the value of the subcommand write pointer) is read to the A register. The command on the second line corresponds to step S1 in FIG.

The command "CPQ A, (LOW R_SBC_RPT)" on the third line of FIG. , and the value stored at that address (the value of the subcommand read pointer) is compared with the value of the A register (the value of the subcommand write pointer). Here, if the value stored at the same address matches the value of the A register, 1 is set in the zero flag. Such a command on the third line corresponds to step S2 in FIG.

If the zero flag is set to 1 by the command "RET Z" on the fourth line in FIG. 182(a), the SBC_OUT module is terminated. Such a command on the fourth line corresponds to step S3 in FIG.

By the command "LD DE,@LMT_CMD_BFP*256+LOW R_SBC_RPT" on the fifth line in FIG. "R_SBC_RPT", which indicates the lower byte of , is read into the E register. This fifth line command corresponds to step S4 in FIG.

The COUNTUP module, which is a general-purpose module, is read and executed by the command "RST COUNTUP" on the sixth line in FIG. 182(a). As a result, the value of the subcommand read pointer is incremented by 1 if it is less than the subcommand pointer upper limit value, and is cleared to zero if it is equal to or greater than the subcommand pointer upper limit value. The sixth line command corresponds to step S5 in FIG.

By the command "LD HL, R_SBC_SBF" on the 7th line in FIG. 182(a), "R_SBC_SBF" indicating the address of the subcommand buffer (transmission buffer) is read to the HL register. The command on the 7th line corresponds to step S6 in FIG. Here, "R_SBC_SBF" is 2-byte length data. If the upper 1 byte of the address of the subcommand buffer is "F0H", it can be read by the command "LDQ". Here, 2-byte length data is read without using the command "LDQ".

The WORDSEL module, which is a general-purpose module, is read by the command "RST WORDSEL" on the eighth line in FIG. The value of the lower byte (the value of the L register, ie the previous command) is read into the A register. The eighth line command corresponds to step S7 in FIG.

The command "OUT (@S1DT__), A" on the 9th line in FIG. 182(a) outputs the value of the A register (preceding command) to the address indicated by the fixed value "@S1DT__". The command on the ninth line corresponds to step S8 in FIG.

The value of the H register (subsequent command) is read to the A register by the command "LD A,H" on the 10th line of FIG. 182(a). Such a command on the tenth line corresponds to S9 in FIG.

The command "OUT (@S1DT__), A" on the 11th line in FIG. finish. The command on the 11th line corresponds to step S10 in FIG. 181, and the command on the 12th line corresponds to step S11 in FIG.

Here, the command group of FIG. 182(a) can be changed as shown in FIG. 182(b). Here, the case where the upper 1 byte of the sub-command buffer (transmission buffer) is "F1H" will be explained, and the explanation of the processing that is substantially the same as in FIG. Only the processing that is different will be described.

According to the command "LDQP HL, LOW R_SBC_SBF" on the 7th line in FIG. subcommand buffer address) is read into the HL register. The command on the 7th line corresponds to step S6 in FIG. Such a command has a command size of "3" and an execution cycle of "7 (5)".

Here, the total command size of the command group shown in FIG. 182(a) is the second line command "LDQ A, (LOW R_SBC_WPT)" 2 bytes + the third line command "CPQ A, (LOW R_SBC_RPT)" 3 bytes. + 4th line command "RET Z" 1 byte + 5th line command "LD DE, @LMT_CMD_BFP*256+LOW R_SBC_RPT" 2 bytes + 6th line command "RST COUNTUP" 1 byte + 7th line command "LD HL, R_SBC_SBF" 3 bytes + 8th line command "RST WORDSEL" 1 byte + 9th line command "OUT (@S1DT__), A" 2 bytes + 10th line command "LD A,H" 1 byte + 11th line command "OUT ( @S1DT__), A" 2 bytes + command "RET" 1 byte on 12th line = 19 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 4 cycles + 4th line 3 (1) cycles + 5th line 2 Cycle+6th row 4 cycles+7th row 3 cycles+8th row 4 cycles+9th row 3 cycles+10th row 1 cycle+11th row 3 cycles+12th row 3 cycles=32 (30) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RET Z" does not move to the routine one level above.

On the other hand, the total command size of the command group shown in FIG. 182(b) is the second line command "LDQ A, (LOW R_SBC_WPT)" 2 bytes + the third line command "CPQ A, (LOW R_SBC_RPT)" 3 bytes + 4 bytes. Line command "RET Z" 1 byte + Line 5 command "LD DE,@LMT_CMD_BFP*256+LOW R_SBC_RPT" 2 bytes + Line 6 command "RST COUNTUP" 1 byte + Line 7 command "LDQP HL, LOW R_SBC_SBF" 3 bytes + 8th line command "RST WORDSEL" 1 byte + 9th line command "OUT (@S1DT__), A" 2 bytes + 10th line command "LD A,H" 1 byte + 11th line command "OUT ( @S1DT__), A" 2 bytes + command "RET" 1 byte on 12th line = 19 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 4 cycles + 4th line 3 (1) cycles + 5th line 2 Cycle + 6th row 4 cycle + 7th row 5 cycle + 8th row 4 cycle + 9th row 3 cycle + 10th row 1 cycle + 11th row 3 cycle + 12th row 3 cycle = 34 (32) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RET Z" does not move to the routine one level above.

Therefore, by replacing the command group shown in FIG. 182(a) with the command group shown in FIG. byte is "F1H"), the design load can be reduced. In the special symbol storage area shift process shown in step S610-9 in FIG. 37, when reading the special game special symbol discrimination flag, the upper 1 byte of the address where the special game special symbol discrimination flag is stored is set to "F1H". , the command "LDQP" may be used. Furthermore, in the external information management process shown in step S400-29 in FIG. 26, when saving the combined bit data in the output port 2 buffer, the upper 1 byte of the output port 2 buffer is set to "F1H", and the command "LDQP" is executed. may be used. Furthermore, in the saving process at power failure in FIG. 25, when saving the backup validity determination value in the backup validity determination flag, the upper 1 byte of the address where the backup validity determination flag is stored is set to "F1H", and the command "LDQP" is executed. may be used.

<RCPQ>
FIG. 183 is an explanatory diagram for explaining an example of another command for realizing the SBC_OUT module. Note that FIG. 183(a) is the same as FIG. 182(a), so the description is omitted. Also, with regard to FIG. 183(b), the description of the processing that is substantially the same as that of FIG. 183(a) will be omitted, and only the processing that is different from FIG. 183(b) will be described.

The command "RCPQ Z, A, (LOW R_SBC_RPT)" on the third line in FIG. The value stored at that address (value of the subcommand read pointer) is compared with the value of the A register (value of the subcommand write pointer). If the zero flag is 1, the command "RET ” to terminate the SBC_OUT module. Such commands on the third line correspond to steps S2 to S4 in FIG. Such a command has a command size of "3" and an execution cycle of "7 (5)". The number of cycles in parentheses indicates the execution cycle when the command does not move to the routine one level above.

Here, the total command size of the command group shown in FIG. 183(b) is the second line command "LDQ A, (LOW R_SBC_WPT)" 2 bytes + the third line command "RCPQ Z, A, (LOW R_SBC_RPT)". 3 bytes + 4th line command "LD DE,@LMT_CMD_BFP*256+LOW R_SBC_RPT" 2nd byte + 5th line command "RST COUNTUP" 1 byte + 6th line command "LD HL, R_SBC_SBF" 3 bytes + 7th line command "RST WORDSEL" 1 byte + 8th line command "OUT (@S1DT__), A" 2 bytes + 9th line command "LD A, H" 1 byte + 10th line command "OUT (@S1DT__), A" 2 bytes + 11 1 byte of the command "RET" on the line = 18 bytes, and the total execution cycle is: 2nd line 2 cycles + 3rd line 7 (5) cycles + 4th line 2 cycles + 5th line 4 cycles + 6th line 3 cycles + 7th line 4th cycle+3rd cycle of 8th row+1st cycle of 9th row+3rd cycle of 10th row+3rd cycle of 11th row=32 (30) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RCPQ Z, A, (LOW R_SBC_RPT)" does not move to the routine one level above.

Therefore, by replacing the command group of FIG. 183(a) with the command group of FIG. 183(b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

183(a) and 183(b), the command group occupying two lines (3rd to 4th lines) in FIG. 183(a) is 183(b) can be expressed in one line (the third line), which makes it possible to reduce the number of commands themselves and the design load.

FIG. 184 is an explanatory diagram for explaining an example of commands for realizing the FZ_OPN module. The FZ_OPN module shown in FIG. 184 executes normal electric accessory winning opening control processing (see FIG. 57).

In the normal electric accessory winning opening control process, in the above step S850-5, the counter value of the normal electric accessory winning ball number counter has not reached the specified number, that is, the first variable start opening 120B is set to 1 It is determined whether or not the same number of game balls as the maximum number of winning prizes during the open/close control of the round have entered. As a result, if it is determined that the specified number has not been reached, the normal electric accessory winning opening control process is terminated, and if it is determined that the specified number has been reached, the process proceeds to step S850-7.

As this ordinary electric accessary prize opening control process, the index "FZ_OPN:" on the first line in FIG. 184(a) indicates the top address of the FZ_OPN module. Then, in step S850-5, the value of the Q register is set to the upper 1 byte of the address and the value of the lower 1 byte of the address "R_FDN_CNT" is set to the lower address by the command "LDQ A, (LOW R_FDN_CNT)" on the second line. 1 byte, and the value stored at that address (the counter value of the normal electric accessory winning ball number counter) is read to the A register. The command "CP A, @FDN_CNT" on the third line compares the value of the A register with a fixed value "@FDN_CNT" indicating a specified number, here 8. That is, if the value of the A register is less than 8, the carry flag is set to 1. Then, if the carry flag is 1 according to "RET C" on the fourth line, the FZ_OPN module is terminated. That is, if the counter value of the normal electric accessory winning ball number counter is less than 8, the FZ_OPN module is terminated. If the carry flag is not 1, the subsequent processing is executed.

Here, the command group of FIG. 184(a) can be changed as shown in FIG. 184(b). 184(a) will be omitted here, and only the different processing in FIG. 184(b) will be described.

The command "RCPQ C, (LOW R_FDN_CNT), @FDN_CNT" on the second line of FIG. The value (the counter value of the counter for the number of winning balls of normal electric accessories) stored at the address of the lower 1 byte is compared with the fixed value "@FDN_CNT", which indicates the specified number, here, 8, and the carry flag is set. If 1, terminate the FZ_OPN module to execute the command "RET". The command size of such command is "4" and the execution cycle is "8(6)". The number of cycles in parentheses indicates the execution cycle when the command does not move to the routine one level above.

Here, the total command size of the command group shown in FIG. 184(a) is the second line command "LDQ A, (LOW R_FDN_CNT)" 2 bytes + the third line command "CP A, @FDN_CNT" 3 bytes + 4 lines. 1 byte of the second command "RET C" = 6 bytes, and the total execution cycle is 2 cycles on the 2nd line + 4 cycles on the 3rd line + 3 (1) cycles on the 4th line = 9 (7) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RET C" does not move to the routine one level higher.

On the other hand, the total command size of the command group shown in FIG. 8(6) cycles=8(6) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RCPQ C, (LOW R_FDN_CNT), @FDN_CNT" does not move to the next higher routine.

Therefore, by replacing the command group of FIG. 184(a) with the command group of FIG. 184(b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

184(a) and 184(b), the command group occupying three lines (2nd to 4th lines) in FIG. 184(a) is 184(b) can be expressed in one line (second line), which makes it possible to reduce the number of commands themselves and the design load.

Also, in the example of FIG. 184(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 184(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

FIG. 185 is an explanatory diagram for explaining an example of commands for realizing the TD_OPN module. The TD_OPN module shown in FIG. 185 executes the big winning opening control process (see FIG. 47).

In the big winning hole opening control process, in the above step S720-5, the counter value of the big winning hole winning ball number counter has not reached the specified number, that is, the maximum possible winning number in one round is set in the big winning hole. It is determined whether or not the same number of game balls are entered. As a result, when it is determined that the specified number has not been reached, the big winning opening opening control process is terminated, and when it is determined that the specified number has been reached, the process proceeds to step S720-7.

As this special prize opening control process, the index "TD_OPN:" on the first line in FIG. 185(a) indicates the head address of the TD_OPN module. Then, in step S720-5, the value of the Q register is set to the upper 1 byte of the address and the value of the lower 1 byte of the address "R_TDN_FLG" is set to the lower address by the command "LDQ A, (LOW R_TDN_FLG)" on the second line. 1 byte, and the value (special electric accessory designation flag) stored at that address is read to the A register. It should be noted that the special electric accessory designation flag indicates which big winning opening is the object of the big winning opening opening control process.

The command "LD HL, D_TDC_MAX-1" on the 3rd line is a value obtained by subtracting 1 from the address of the special winning opening prescribed winning number data table (a table showing the prescribed number of the special electric accessory operating ram set table in FIG. 14) into the HL register.

The BYTESEL module, which is a general-purpose module, is read by the command "RST BYTESEL" on the fourth line in FIG. (prescribed number) is read into the A register.

The command "CPQ A, (LOW R_TDN_CNT)" on the fifth line in FIG. , and the value stored at that address (the counter value of the winning ball number counter for the big winning opening) is compared with the value of the A register, which is 10 here. That is, if the value stored at the same address is less than 10, the carry flag is not set and becomes 0. Then, if the carry flag is 0 by "RET NC" on the 6th line, the TD_OPN module is terminated. That is, if the counter value of the big winning hole winning ball number counter is less than 10, the TD_OPN module is terminated. If the carry flag is 1, the subsequent processing is executed.

Here, the command group of FIG. 185(a) can be changed as shown in FIG. 185(b). 185(a) will be omitted here, and only the different processing in FIG. 185(b) will be described.

The command "RCPQ NC, A, (LOW R_TDN_CNT)" on the fifth line in FIG. 1 byte, the value stored at that address (the counter value of the winning ball number counter for the big winning opening) is compared with the value of the A register (default value), here 10, and if the carry flag is 0 , exit the TD_OPN module to execute the command "RET". Such a command has a command size of "3" and an execution cycle of "7 (5)". The number of cycles in parentheses indicates the execution cycle when the command does not move to the routine one level above.

Here, the total command size of the command group shown in FIG. 185(a) is the second line command "LDQ A, (LOW R_TDN_FLG)" 2 bytes + the third line command "LD HL, D_TDC_MAX-1" 3 bytes + 4 bytes. Line 1 command "RST BYTESEL" 1 byte + Line 5 command "CPQ A, (LOW R_TDN_CNT)" 3 bytes + Line 4 command "RET NC" 1 byte = 10 bytes. Cycle + 3rd row 3 cycles + 4th row 3 cycles + 5th row 4 cycles + 4th row 3 (1) cycles = 15 (13) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RET NC" does not move to the routine one level higher.

On the other hand, the total command size of the command group shown in FIG. 185(b) is the second line command "LDQ A, (LOW R_TDN_FLG)" 2 bytes + the third line command "LD HL, D_TDC_MAX-1" 3 bytes + 4 lines. 1st command "RST BYTESEL" 1 byte + 5th line command "RCPQ NC, A, (LOW R_TDN_CNT)" 3 bytes = 9 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 3 cycles + 4th line 3 Cycles+5th row 7 (5) cycles=15 (13) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RCPQ NC, A, (LOW R_TDN_CNT)" does not move to the routine one level above.

Therefore, by replacing the command group of FIG. 185(a) with the command group of FIG. 185(b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

185(a) and 185(b), the command group occupying two lines (5th and 6th lines) in FIG. 185(b) can be expressed in one line (fifth line), which makes it possible to reduce the number of commands themselves and the design load.

<JCPQ>
FIG. 186 is an explanatory diagram for explaining an example of commands for realizing the HSY_PRC module. The HSY_PRC module shown in FIG. 186 executes firing position designation management processing (see step S400-27 in FIG. 26).

As this firing position designation management process, the index "HSY_PRC:" on the first line in FIG. 186(a) indicates the start address of the HSY_PRC module. The command "XOR A, A" on the second line computes the exclusive OR of the value of the A register and the value of the A register to initialize the A register.

Then, by the command "LDQ HL, LOW R_TDN_FLG" on the third line, the value of the Q register is read to the H register, and the value of the lower 1 byte of the address "R_TDN_FLG" is read to the L register.

By the command "JCP NZ, (HL), @TDK_AT2, HSY_PRC_10" on the 4th line, the value indicated in the HL register (special electric accessory designation flag) and the fixed value "@TDK_AT2" indicating the second big prize opening are compared, and if the zero flag is not set to 1, the process moves to the address indicated by the index "HSY_PRC_10" on the 7th line (processing is branched).

On the other hand, if the zero flag is set to 1, the value of the Q register is read to the H register and the value of the lower 1 byte of the address "R_ZUG_CHK_FIX" is read to the L register by the command "LDQ HL, LOW R_ZUG_CHK_FIX" on the fifth line. .

By the command "JCP NZ, (HL), @ZUG_SML1, HSY_PRC_20" on the 6th line, the value indicated in the HL register (special symbol determination flag) and the fixed value "@ZUG_SML1" indicating the small winning symbol 1 designation data, here Then, 07H is compared with 07H, and if 1 is not set in the zero flag, the address is moved to the address indicated by the index "HSY_PRC_20" on the 8th line (processing is branched).

Here, the command group of FIG. 186(a) can be changed as shown in FIG. 186(b). 186(a) will be omitted here, and only the different processing in FIG. 186(b) will be described.

The command "JCPQ NZ, (LOW R_TDN_FLG), @TDK_AT2, HSY_PRC_10" on the third line in FIG. The lower 1 byte of the address is compared with the value indicated by the address (special electric accessory designation flag) and the fixed value "@TDK_AT2" indicating the second big prize opening, and if 1 is not set in the zero flag, Move to the address indicated by the index "HSY_PRC_10" on the fifth line (branch the process).

The command "JCPQ NZ, (LOW R_ZUF_CHK_FIX, @ZUG_SML1, HSY_PRC_20" on the fourth line in FIG. , and compare the value (special symbol determination flag) indicated at the address with the fixed value "@TDK_AT2" indicating the second big winning opening, and the fixed value "@ ZUG_SML1", here, 07H, and if the zero flag is not set to 1, move to the address indicated by the index "HSY_PRC_20" on the 6th line (process is branched).

Here, the total command size of the command group shown in FIG. Command "JCP NZ, (HL), @TDK_AT2, HSY_PRC_10" 4 bytes + Command "LDQ HL, LOW R_ZUG_CHK_FIX" 2 bytes on line 5 + Command "JCP NZ, (HL), @ZUG_SML1, HSY_PRC_20" 4 bytes on line 6 = 13 bytes, and the total execution cycle is 2nd line 1 cycle + 3rd line 2 cycles + 4th line 6 (5) cycles + 5th line 2 cycles + 6th line 2 cycles 6 (5) = 17 (15) cycles . Note that the number of cycles in parentheses indicates the execution cycle when the command "JCP NZ, . . . " does not move.

On the other hand, the total command size of the command group shown in FIG. 186(b) is the command "XOR A, A" 1 byte on the second line + the command "JCPQ NZ, (LOW R_TDN_FLG), @TDK_AT2, HSY_PRC_10" on the third line. 4 bytes + 4th line command "JCPQ NZ, (LOW R_ZUG_CHK_FIX, @ZUG_SML1, HSY_PRC_20" 4 bytes = 9 bytes, and the total execution cycle is 2nd line 1 cycle + 3rd line 6 (5) cycles + 4th line 6 ( 5) = 13 (11) cycles The number of cycles in parentheses indicates the number of execution cycles when the command "JCP NZ, ..." does not move.

Therefore, by replacing the command group of FIG. 186(a) with the command group of FIG. 186(b), the total command size is reduced by 4 bytes, and the total execution cycle is also reduced by at least 4 cycles. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

186(a) and 186(b), the command group occupying 4 lines (3rd to 6th lines) in FIG. 186(a) is 186(b) can be expressed in two lines (third and fourth lines), which makes it possible to reduce the number of commands and the design load.

Also, in the example of FIG. 186(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. In the example of FIG. 186(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

FIG. 187 is an explanatory diagram for explaining an example of commands for realizing the FDN_CHK module. The FDN_CHK module shown in FIG. 187 executes normal electric accessory winning confirmation processing (see step S500-9 in FIG. 28).

As confirmation processing at the time of this ordinary electric accessory winning prize, the index "FDN_CHK:" in the first line of FIG. 187(a) indicates the top address of the FDN_CHK module.

Then, by the command "LDQ HL, (LOW R_FDN_EFF)" on the second line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FDN_EFF" is set to the lower 1 byte of the address, and the address (the value of the normal electric accessory closing valid timer) is read to the HL register.

The command "RET NTZ" on the third line terminates the FDN_CHK module if the zero flag is not 1. The reason why "NTZ" is used here is that the command "LDQ HL, (LOW R_FDN_EFF)" changes the second zero flag but does not change the first zero flag.

By the command "LDQ A, (LOW R_FUT_PHS)" on the fourth line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FUT_PHS" is set as the lower 1 byte of the address, and the address value (Normal game management phase) is read to the A register.

By the command "JCP NZ, A, @FD_OPN, FDN_CHK_10" on the fifth line, the value indicated in the A register (normal game management phase) and the fixed value "@FD_OPN" indicating the normal electric accessory winning opening control process, Here, 04H is compared with 04H, and if 1 is not set in the zero flag, the address is moved to the address indicated by the index "FDN_CHK_10" on the eighth line (processing is branched).

On the other hand, if the zero flag is 1, the command "INCQ (LOW R_FDN_CNT)" on the 6th line sets the value of the Q register to the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_FDN_CNT" to the address. The value stored at the address (the counter value of the winning ball number counter for normal electric accessories) is added by 1, the added value is stored at the address, and the command "RET" on the 7th line is used. , terminate the FDN_CHK module.

Here, the command group of FIG. 187(a) can be changed as shown in FIG. 187(b). 187(a) will be omitted here, and only the different processing in FIG. 187(b) will be described.

By the command "JCPQ NZ, (LOW R_FUT_PHS), @FD_OPN, FDN_CHK_10" on the 4th line of FIG. The lower 1 byte of the address is compared with the address value (ordinary game management phase) and a fixed value "@FD_OPN" indicating the normal electric accessary prize opening control process, here 04H, and 1 is set in the zero flag. If not, move to the address indicated by the index "FDN_CHK_10" on the 7th line (branch the process).

Here, the total command size of the command group shown in FIG. Command "LDQ A, (LOW R_FUT_PHS)" 2 bytes + 5th line command "JCP NZ, A, @FD_OPN, FDN_CHK_10" 3 bytes + 6th line command "INCQ (LOW R_FDN_CNT)" 2 bytes + 7th line command " RET" 1 byte = 11 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 3(1) cycle + 4th line 2 cycles + 5th line 4(3) cycles + 6th line 5 cycles + 7th line 3 cycles = 21 (18) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the command "RET NTZ", "JCP NZ, . . . " does not move.

On the other hand, the total command size of the command group shown in FIG. "JCPQ NZ, (LOW R_FUT_PHS), @FD_OPN, FDN_CHK_10" 4 bytes + 5th line command "INCQ (LOW R_FDN_CNT)" 2 bytes + 6th line command "RET" 1 byte = 10 bytes, and the total execution cycle is 2nd row 4 cycles+3rd row 3(1) cycles+4th row 6(5) cycles+5th row 5 cycles+6th row 3 cycles=19(16) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the command "RET NZ", "JCPQ NTZ, . . . " does not move.

Therefore, by replacing the command group of FIG. 187(a) with the command group of FIG. 187(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 2 cycles. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

187(a) and 187(b), the command group occupying two lines (4th and 5th lines) in FIG. 187(b) can be expressed in one line (fourth line), which makes it possible to reduce the number of commands and the design load.

Also, in the example of FIG. 187(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 187(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

FIG. 188 is an explanatory diagram for explaining an example of commands for realizing the FZ_STP module. The FZ_STP module shown in FIG. 188 executes normal symbol stop symbol display processing (see FIG. 54).

As this normal symbol stop symbol display process, the index "FZ_STP:" on the first line in FIG. 188(a) indicates the leading address of the FZ_STP module.

Then, if the second zero flag is not set to 1 by the command "RET NTZ" on the second line, the FZ_STP module is terminated.

By the command "LDQ A, (LOW R_FZ_ATA)" on the third line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FZ_ATA" is set as the lower 1 byte of the address, and the address value (Normal pattern hit flag) is read to the A register. In addition, the normal pattern hit flag becomes 01H when the hit is determined by the normal pattern lottery, and becomes 00H when the loss is determined.

By the command "JCP Z, A, @FZ_ATA, FZ_STP_10" on the 4th line, compare the value shown in the A register (normal pattern per flag) and the fixed value "@FZ_ATA" indicating the hit, here 01H, If the zero flag is set to 1, the process moves to the address indicated by the index "FZ_STP_10" on the eighth line (processing is branched).

On the other hand, if the zero flag is not set to 1, the command "CLRQ (LOW R_FUT_PHS)" on the fifth line sets the value of the Q register to the upper 1 byte of the address, and sets the value of the lower 1 byte of the address "R_FUT_PHS" to the address. The lower 1 byte is assigned, and 0 is substituted (cleared) for the value (normal game management phase) stored at that address.

By the command "CLRQ (LOW R_FZ_STP)" on the 6th line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FZ_STP" is set as the lower 1 byte of the address, and the 0 is assigned (cleared) to the value (normal symbol stop symbol number), and the FZ_STP module is terminated by the command "RET" on the 7th line.

Here, the command group of FIG. 188(a) can be changed as shown in FIG. 188(b). 188(a) will be omitted here, and only the different processing in FIG. 188(b) will be described.

The command "JCPQ Z, (LOW R_FZ_ATA), @FZ_ATA, FZ_STP_10" on the third line in FIG. The lower 1 byte of the address is compared with the value of the address (normal pattern per flag) and the fixed value "@FZ_ATA" indicating the hit, here 01H. Move to the address indicated by the index "FZ_STP_10" (branch the process).

Here, the total command size of the command group shown in FIG. Command "JCP Z, A, @FZ_ATA, FZ_STP_10" 3 bytes + 5th line command "CLRQ (LOW R_FUT_PHS)" 2 bytes + 6th line command "CLRQ (LOW R_FZ_STP)" 2 bytes + 7th line command "RET" 1 byte = 11 bytes, and the total execution cycle is: 2nd row 3 (1) cycle + 3rd row 2 cycle + 4th row 4 (3) cycle + 5th row 2 cycle + 6th row 2 cycle + 7th row 3 cycle = 16 (13) Cycle. The number of cycles in parentheses indicates the execution cycle when the commands "RET NTZ", "JCP Z, .

On the other hand, the total command size of the command group shown in FIG. 188(b) is the command "RET NTZ" 1 byte on the second line + the command "JCPQ Z, (LOW R_FZ_ATA), @FZ_ATA, FZ_STP_10" 4 bytes on the third line. + 4th line command "CLRQ (LOW R_FUT_PHS)" 2 bytes + 5th line command "CLRQ (LOW R_FZ_STP)" 2 bytes + 6th line command "RET" 1 byte = 10 bytes, total execution cycle is 2 lines 3rd row 3 (1) cycle + 3rd row 6 (5) cycle + 4th row 2 cycle + 5th row 2 cycle + 6th row 3 cycle = 16 (13) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the command "RET NTZ", "JCPQ Z, . . . " does not move.

Therefore, by replacing the command group of FIG. 188(a) with the command group of FIG. 188(b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

188(a) and 188(b), the command group occupying two lines (3rd to 4th lines) in FIG. 188(a) is 188(b) can be expressed in one line (the third line), which makes it possible to reduce the number of commands themselves and the design load.

Also, in the example of FIG. 188(b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 188(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

<random number generator>
FIG. 189 is a block diagram for explaining the configuration of random number generators 740-746. As described above, the main CPUs 300a and 500a are provided with a plurality of random number generators.

For example, as shown in FIG. 189, the main CPUs 300a and 500a have four channels of maximum value setting random number generator 740, which is a random number generator capable of setting the maximum value of 16 bits, and the maximum value of 16 bits is fixed at 65536. A maximum value fixed random number generator 742, which is a random number generator, has 4 channels. A maximum value setting random number generator 744, which is a random number generator capable of setting a maximum value of 8 bits, has 8 channels. 8 channels of fixed maximum random number generator 746 are provided. These random number generators 740 to 746 are hardware random number generators (hardware random number generators).

The maximum value setting random number generator 740 can set the random number update cycle to any one of 32 to 47 clocks, and the start value can be any of 0001h, a value based on the ID number, and a value that is changed at each system reset. can be set to The fixed maximum random number generator 742 has a random number update period of one clock and a start value that is changed at each system reset. Note that the system reset is to reset the state in terms of hardware, and is executed when a predetermined abnormality occurs when the power is turned on.

The maximum value setting random number generator 744 can set the random number update period to any one of 16 to 31 clocks, and the start value can be set to 01h, a value based on the ID number, or a value changed at each system reset. can be set to The fixed maximum random number generator 746 has a random number update period of one clock and a start value that is changed at each system reset. In the initial setting process of step S100-1, the start value is set and saved, and the random number update period of the maximum value setting random number generators 740 and 744 is set and saved.

In addition, these random number generators 740 to 746 have their start values updated each time the system is reset. Then, the maximum value setting random number generator 740 updates the random number (random number counter) once at any one of the 32nd to 47th clocks of the internal system clock. The maximum value setting random number generator 744 updates the random number (random number counter) once at any of the 16th to 31st clocks of the internal system clock by hardware. The maximum value fixed random number generators 742 and 746 update random numbers (random number counters) once per clock of the internal system clock by hardware. These random number generators 740 to 746 update random numbers according to a certain rule, and the random number sequence is automatically updated each time the random number sequence is cycled. When the software determines that the game ball has passed through the predetermined area, a random number (hardware random number count value) is acquired from the random number register.

In addition, the main CPUs 300a and 500a can also generate software random numbers by multiplying or dividing the random numbers obtained from the random number generators 740 to 746 by a predetermined number in the program (software random number generator). is. The software random number generation unit updates the random number while interrupt processing that occurs every 4 ms is not being executed. Specifically, the software random number generator compares the previous random number with the maximum value, sets the random number to 0 if the previous random number has reached the maximum value, and sets the previous random number to 0 if the previous random number has not reached the maximum value. In that case, 1 is added to the random number. Then, when it is determined that the game ball has passed through the predetermined area, a random number (software random number count value) is acquired.

Here, in the gaming machine 100, as random numbers, jackpot determination random numbers, winning pattern random numbers, reach group determination random numbers, reach mode determination random numbers, variation pattern random numbers, and winning determination random numbers are provided.

The jackpot decision random number is in the range of 0 to 65535, the winning pattern random number is in the range of 0 to 99, the reach group decision random number is in the range of 0 to 10006, the reach mode decision random number is in the range of 0 to 250, Variation pattern random numbers are in the range of 0-238, and hit determination random numbers are in the range of 0-99.

In addition, when providing a plurality of winning patterns of the normal design, it is necessary to provide a normal design random number, for example, in the range of 0-99. Furthermore, when providing a plurality of normal pattern fluctuation patterns (variation time), it is necessary to provide a normal pattern fluctuation pattern random number, for example, in the range of 0-99.

FIG. 190 is a diagram for explaining combinations of random number generators. For example, since it is necessary to generate a random number from 0 to 65535 for the jackpot determination random number, a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 65535 is used. Since it is necessary to generate a random number from 0 to 99 as the winning symbol random number, an 8-bit random number generated by a software random number generator with a maximum value of 99 is used.

Since it is necessary to generate a random number from 0 to 10006 as the reach group determination random number, a 16-bit random number generated by the maximum value setting random number generator 740 with the maximum value set to 10006 is used. Since it is necessary to generate a random number from 0 to 250 as the reach mode determination random number, an 8-bit random number generated by a software random number generator with a maximum value of 250 is used. Since it is necessary to generate a random number from 0 to 238 as the variation pattern random number, an 8-bit random number generated by a software random number generator with a maximum value of 238 is used.

Since it is necessary to generate a random number from 0 to 99 as the winning determination random number, an 8-bit random number generated by the maximum value setting random number generator 744 whose maximum value is set to 99 is used. Since it is necessary to generate a random number from 0 to 99 for the normal pattern random number, an 8-bit random number generated by a software random number generator with the maximum value set to 99 is used. Since it is necessary to generate random numbers from 0 to 99, the 8-bit random number generated by the software random number generator with the maximum value set to 99 is used for the normal pattern fluctuation pattern random number.

Here, when using the random number generated by the software random number generator, in step S100-61 in FIG. 23, step S400-17 in FIG. 26, and step S100-69 in FIG. It is necessary to perform processing to update the random number. Then, there is a possibility that the capacity of the control area for performing the game control process will be squeezed.

Therefore, as shown in FIGS. 190(b) and (c), for example, the jackpot determination random number is in the range of 0 to 65535, the winning pattern random number is in the range of 0 to 99, and the reach group determination random number is in the range of 0 to 10006. , the reach mode decision random number is in the range of 0 to 1000, the fluctuation pattern random number is in the range of 0 to 255, the hit decision random number is in the range of 0 to 65535, the general pattern random number is in the range of 0 to 99, and the general pattern The variation pattern random number is in the range of 0-255. The range of these random numbers is an example, and the random number with the maximum value of 65535, which is the maximum value of the maximum value fixed random number generator 742, and the maximum value of 255, which is the maximum value of the maximum value fixed random number generator 746. Any random number may be set as the random number.

Then, as shown in FIG. 190(b), a 16-bit random number generated by a maximum value setting random number generator 740 with a maximum value of 65535 is used as the jackpot decision random number. As the winning symbol determination random number, an 8-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 99 is used. The reach group determination random number uses a 16-bit random number generated by the maximum value set random number generator 740 with the maximum value set to 10,006. The reach mode decision random number uses a 16-bit random number generated by a maximum value setting random number generator with a maximum value of 1000. An 8-bit random number generated by a fixed maximum value random number generator 746 whose maximum value is fixed at 255 is used as the variation pattern random number.

A 16-bit random number generated by the maximum value setting random number generator 740 with the maximum value set to 65535 is used as the winning decision random number. The normal pattern random number uses an 8-bit random number generated by the maximum value setting random number generator 744 whose maximum value is set to 99. The normal pattern fluctuation pattern random number uses an 8-bit random number generated by the maximum value fixed random number generator 746 whose maximum value is fixed to 255.

Also, as shown in FIG. 190(c), the jackpot determination random number and the winning determination random number may be 16-bit random numbers generated by a fixed maximum value random number generator 742 whose maximum value is fixed to 65535. The maximum value setting random number generator 740 can appropriately set a start value, a random number update period, a maximum value of random numbers, etc., but the random number update period is slower than that of the maximum value fixed random number generator 742 . Therefore, for win/fail random numbers (jackpot decision random numbers and winning decision random numbers) that are directly linked to the player's profit, it is preferable to use the maximum value fixed random number generator 742, which has a fast random number update cycle and is difficult to read random numbers.

In this way, by using the random numbers generated by the random number generators 740 to 746 (hardware random number generators) as the plurality of random numbers used in the progress of the game, steps S100-61 in FIG. 23 and FIG. In step S400-17 of FIG. 23 and step S100-69 in FIG. 23, there is no need to determine the initial value of the random number or to update the random number. As a result, the capacity of the main ROM 300b of about 35 bytes can be reduced, and the capacity of the main RAM 300c of about 4 bytes can be reduced. Thus, it becomes possible to ensure the capacity of the control area for performing the game control process.

<Command “OR”>
FIG. 191 is a flow chart showing specific processing of the SMC_ROT module. Here, as an arbitrary process, a process of synthesizing a phase flag indicating the reel position with an index flag, which is part of the SMC_ROT module that executes the steady rotation process, will be described. Here, the index flag is a flag represented by a 1-byte value that is turned ON when an index signal is acquired after the reels 410a, 410b, and 410c reach a steady rotation speed. For example, bit 0 of the index flag becomes 1 when the index signal of the left reel 410a is acquired, bit 1 of the index flag becomes 1 when the index signal of the middle reel 410b is acquired, and bit 1 of the index flag becomes 1 when the index signal of the right reel 410c is acquired. Bit 2 becomes 1. By referring to the index flag, it is possible to confirm which of the reels 410a, 410b, 410c has acquired the index signal. The phase flag is a 1-byte flag that specifies the reels 410a, 410b, and 410c that are being processed. For example, bit 0 of the phase flag becomes 1 (00000001B) during processing of the left reel 410a, bit 1 of the phase flag becomes 1 (00000010B) during processing of the middle reel 410b, and bit 1 of the phase flag becomes 1 (00000010B) during processing of the right reel 410c. Bit 2 becomes 1 (00000100B). Numerical values of step S in this figure are used only in the explanation of this figure. Also, in the description of the SMC_ROT module, the first register is the C register, the second register is the HL register, and the register different from the first and second registers is the A register.

It is assumed that the value of the phase flag is already held in a predetermined register (for example, C register) at the stage of executing the SMC_ROT module. Then, the main CPU 500a executes arbitrary processing as shown in FIG. The main CPU 500a first sets the address of the index flag (variable) to be logically summed in the HL register (S1). Then, in order to synthesize the phase flag with the index flag, the main CPU 500a calculates the logical sum of the already set C register value (phase flag) and the 1-byte value stored at the address indicated by the HL register. Then, the value stored at the address indicated by the HL register is overwritten with the result of the logical sum in order to reflect it in the index flag (S2). Here, combining means that when any bit of the phase flag, which is a variable, is set (if it is 1), the same bit of the index flag is also set (set to 1). Therefore, since the phase flag is set for the reels 410a, 410b, and 410c being processed, the corresponding bit of the index flag is set by synthesis regardless of whether or not the index signal is acquired. Also, when all the index signals are acquired (when all the reels 410a, 410b, and 410c reach a steady rotational speed), all the bits corresponding to the respective reels of the index flags are set (00000111B) regardless of the phase flags. Become. Then, the SMC_ROT module ends by moving to the PRE_PLS module that executes the excitation pattern update preprocessing (S3). Thus, it is possible to synthesize the phase flag with the index flag.

FIG. 192 is an explanatory diagram for explaining an example of commands for realizing the SMC_ROT module. The flowchart shown in FIG. 191 is realized by the program shown in FIG. 192, for example.

The index "SMC_ROT:" on the first line in FIG. 192 indicates the head address of the SMC_ROT module. The command "LDQ HL, LOW_IDX_FND" on the second line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "_IDX_FND" to the L register. The command on the second line corresponds to step S1 in FIG.

The command "LD A, (HL)" on the third line in FIG. 192 causes the 1-byte value (index flag value) stored at the address indicated by the HL register to be read to the A register. The command "OR A, C" on the fourth line calculates the logical sum of the value of the A register and the value of the C register, and updates the A register with the calculation result. Then, the value of the A register is stored in the address indicated by the HL register by the command "LD (HL), A" on the fifth line. That is, the 1-byte value stored at the address indicated by the HL register is overwritten with the value of the A register, and the value of the index flag is updated. The commands on the 3rd to 5th lines correspond to step S2 in FIG.

The command "JP PRE_PLS" on the sixth line in FIG. 192 moves to the index "PRE_PLS:" indicating the start address of the PRE_PLS module. The sixth line command corresponds to step S3 in FIG.

Thus, the total command size of the commands of the SMC_ROT module shown in FIG. 192 is the command "LDQ HL, LOW_IDX_FND" on the second line 2 bytes + the command "LD A, (HL)" on the third line 1 byte + 4 lines 1st command "OR A, C" 1 byte + 5th line command "LD (HL), A" 1 byte + 6th line command "JP PRE_PLS" 3 bytes = 8 bytes. 2 cycles+3rd row 2 cycles+4th row 1 cycle+5th row 2 cycles+6th row 3 cycles=10 cycles. By providing the processing of lines 3 to 5 in the SMC_ROT module, it becomes possible to easily synthesize (logical sum) the index flag and the phase flag stored as variables.

FIG. 193 is an explanatory diagram for explaining another example of commands for realizing the SMC_ROT module. Here, the command group of the SMC_ROT module in FIG. 192 is replaced with the command group of the SMC_ROT module in FIG.

The index "SMC_ROT:" on the first line in FIG. 193 indicates the top address of the SMC_ROT module. The command "LDQ HL, LOW_IDX_FND" on the second line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "_IDX_FND" to the L register.

The command "OR (HL), C" on the third line in FIG. Store at the address indicated by the register. That is, the 1-byte value stored at the address indicated by the HL register is overwritten with the calculation result, and the value of the index flag is updated. Such a command on the third line corresponds to step S2 in FIG.

The command "JP PRE_PLS" on the fourth line in FIG. 193 moves to the index "PRE_PLS:" indicating the top address of the PRE_PLS module. The command on the fourth line corresponds to step S3 in FIG.

The total command size of the commands of the SMC_ROT module shown in FIG. JP PRE_PLS" 3 bytes=7 bytes, and the total execution cycle is 2nd line 2 cycles+3rd line 5 cycles+4th line 3 cycles=10 cycles. Therefore, compared with the case of FIG. 192, the total command size is reduced by 1 byte. With this SMC_ROT module, it is possible to further shorten commands and secure the capacity of the control area for performing game control processing.

Also, as can be understood by comparing FIGS. 192 and 193, the command group occupying 3 lines (3rd to 5th lines) in FIG. ), it is possible to reduce the number of commands and the design load.

Here, the command "OR (HL), C" for executing the logical sum was mentioned and explained, but the command "AND (HL), C" for executing the logical product and the command "AND (HL), C" for executing the exclusive logic Even the sum "XOR (HL), C" can be replaced in the same manner as the logical sum, and the total command size can be reduced by 1 byte. Also, the register that stores the address of the variable is not limited to the HL register, but may be the DE register. Furthermore, the register to be logically summed is not limited to the C register, and the A register, B register, D register, E register, H register, and L register can also be adopted.

Also, unlike the example in FIG. 192, the A register is not used here. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 192, if the A register has already been used, it was necessary to stack and save the value of the A register. In this way, it becomes possible to effectively use resources.

<Command “LDF”>
FIG. 194 is a flow chart showing specific processing of the INITIAL module. Here, as an arbitrary process, the built-in register area setting process, which is a part of the INITIAL module that executes the CPU initialization process shown in step S2000 in FIG. 82, will be described. Numerical values of step S in this figure are used only in the explanation of this figure. Also, in the description of the INITIAL module, the first register is the HL register.

The main CPU 500a executes arbitrary processing as shown in FIG. The main CPU 500a first sets the top address of the CPU built-in register setting data table (data table) in the HL register (S1). Then, the main CPU 500a sets the number of setting data (S2).

Subsequently, the main CPU 500a sets the address of the internal register accessible through the input/output unit and the set data in the C register and the A register, respectively (S3). Next, the value of the A register (setting data) is output to the built-in register indicated by the C register (S4). Subsequently, the main CPU 500a decrements (subtracts "1") the value of the B register (number of set data), and determines whether or not the result of the decrement is 0 (S5). Here, if the decremented result is not 0 (NO in S5), the processing from step S3 is repeated, and if the decremented result is 0 (YES in S5), the next processing is performed.

FIG. 195 is an explanatory diagram for explaining an example of commands for realizing the INITIAL module. Among them, FIG. 195(a) shows the command group of the INITIAL module, and FIG. 195(b) shows the arrangement of the 1-byte data group in the program data of the main ROM 500b. The flowchart shown in FIG. 194 is realized by the program shown in FIG. 195, for example.

The index "INITIAL:" on the first line in FIG. 195(a) indicates the start address of the INITIAL module. By the command "LD HL, T_CPU_REG" on the second line, the head address "T_CPU_REG" of the CPU built-in register setting data table is read to the HL register. The command on the second line corresponds to step S1 in FIG. The number of setting data stored in the address "@NUM_CPU_REG" is read out to the B register by the command "LD B, @NUM_CPU_REG" on the third line. Such a command on the third line corresponds to step S2 in FIG.

As can be understood by referring to the 22nd line in FIG. 195(b), the address "@NUM_CPU_REG" describes the command "EQU ($-T_CPU_REG)/2". Here, "$" is the address next to the final address of the 1-byte data group that is the transfer source, that is, the address "@NUM_CPU_REG" itself, and "T_CPU_REG" is the start address of the 1-byte data group that is the transfer source. Therefore, the value of $-T_CPU_REG (a 1-byte value indicating the number of data) is the total number of bytes of the 1-byte value, and dividing that value by 2, the number of combinations of addresses and values, gives the number of set data is derived. For example, in the example of FIG. 195(b), the number of setting data is 20/2=10.

The index "INITIAL01:" on the fourth line in FIG. 195(a) indicates the starting address of the repeated processing. By the command "LDIN AC, (HL)" on the fifth line, the value stored at the address indicated by the HL register is stored in the C register, and is stored at the address indicated by adding "1" to the HL register. The resulting value is stored in the A register. This fifth line command corresponds to step S3 in FIG. The command "OUT (C), A" on the sixth line outputs the value of the A register (set data) to the value indicated by the C register (internal register). The sixth line command corresponds to step S4 in FIG.

For example, if the HL register has the value of the address "T_CPU_REG", the 1-byte value "@PT0PR__" in the second line of FIG. 195(b) is stored in the C register, and the A value of "120" is stored in the A register. Then, it outputs the value of the A register, that is, the value of "120", to the value of the C register, that is, the address indicated by "@PT0PR__".

Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ INITIAL01" on the 7th line in FIG. , if the decremented result is 0, the process is shifted to the command following the command. Here, since the number of data is "10", the value of the B register becomes 0 when the processing from "INITIAL01" is repeated 10 times. Such a command on the seventh line corresponds to step S5 in FIG.

Thus, the total command size of the commands of the INITIAL module shown in FIG. 195(a) is the command "LD HL, T_CPU_REG" 3 bytes on the second line + the command "LD B, @NUM_CPU_REG" 2 bytes on the third line + 5 bytes. 2 bytes of the command "LDIN AC, (HL)" on the 6th line + 2 bytes of the command "OUT (C), A" on the 6th line + 2 bytes of the command "DJNZ INITIAL01" on the 7th line = 11 bytes, and the total execution cycle is 2nd row 3 cycles+3rd row 2 cycles+5th row 4 cycles+6th row 3 cycles+7th row 3 cycles (2 cycles)=15 cycles (14 cycles). Note that the number of cycles in parentheses indicates the execution cycle when the command "DJNZ INITIAL01" does not move. Here, since the number of setting data is 10, the commands on the 5th to 7th lines are repeated 10 times. Therefore, the actual total execution cycle is: 2nd line 3 cycles + 3rd line 2 cycles + (5th line 4 cycles + 6th line 3 cycles + 7th line 3 cycles) x 9 loops + (5th line 4 cycles + 6th line 3 cycles+7th row 2 cycles)=104 cycles. Setting data can be set in internal registers by such an INITIAL module.

FIG. 196 is an explanatory diagram for explaining another example of commands for realizing the INITIAL module. Here, the command group of the INITIAL module in FIG. 195(a) is replaced with the command group of the INITIAL module in FIG. The group is used as it is as FIG. 196(b).

The index "INITIAL:" on the first line in FIG. 196(a) indicates the head address of the INITIAL module. By the command "LDF HL, T_CPU_REG" on the second line, the head address "T_CPU_REG" of the CPU built-in register setting data table is read to the HL register. The command on the second line corresponds to step S1 in FIG.

Here, the command "LDF HL, mn" is a command for storing the value of "mn" in the HL register. Such a command has a command size of "2" and an execution cycle of "2". On the other hand, the generally used load command "LD HL, mn" is also a command to store the value of "mn" in the HL register, but the command size of this command is "3" and the execution cycle is "3". is. Therefore, by changing "LD" to "LDF" on the condition that mn is in the range of 1200H to 1DFFH on the memory map and that it is loaded into the HL register, the command size is reduced by 1 byte and executed. The cycle is also reduced by one cycle.

Thus, the value of mn in the command "LDF HL, mn" must be anywhere from 1200H to 1DFFH in the memory map. Therefore, in this embodiment, the program data is arranged in the range of 1200H to 1DFFH in the used area of the main ROM 500b, and the command "LDF HL, mn" is used only when reading data in this range. The assemble code of "LDF HL, 1200H" is expressed as 6A00H by adding 5800H to the target address "1200H". Therefore, the assemble code for "LDF HL, 1200H" to "LDF HL, 1DFFH" is 6A00H to 75FFH.

The number of setting data stored at the address "@NUM_CPU_REG" is read to the B register by the command "LD B, @NUM_CPU_REG" on the third line in FIG. 196(a). Such a command on the third line corresponds to step S2 in FIG.

The index "INITIAL01:" on the fourth line in FIG. 196(a) indicates the starting address of the repeated processing. By the command "LDIN AC, (HL)" on the fifth line, the value stored at the address indicated by the HL register is stored in the C register, and is stored at the address indicated by adding "1" to the HL register. The resulting value is stored in the A register. This fifth line command corresponds to step S3 in FIG. The command "OUT (C), A" on the sixth line outputs the value of the A register (set data) to the value indicated by the C register (internal register). The sixth line command corresponds to step S4 in FIG.

Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ INITIAL01" on the 7th line in FIG. , if the decremented result is 0, the process is shifted to the command following the command. Here, since the number of data is "10", the value of the B register becomes 0 when the processing from "INITIAL01" is repeated 10 times. Such a command on the seventh line corresponds to step S5 in FIG.

Thus, the total command size of the INITIAL module commands shown in FIG. 2 bytes of the command "LDIN AC, (HL)" on the line 6 + 2 bytes of the command "OUT (C), A" on the 6th line + 2 bytes of the command "DJNZ INITIAL01" on the 7th line = 10 bytes, and the total execution cycle is 2nd row 2 cycles+3rd row 2 cycles+5th row 4 cycles+6th row 3 cycles+7th row 3 cycles (2 cycles)=14 cycles (13 cycles). Note that the number of cycles in parentheses indicates the execution cycle when the command "DJNZ INITIAL01" does not move. Here, since the number of setting data is 10, the commands on the 5th to 7th lines are repeated 10 times. Therefore, the actual total execution cycle is: 2nd line 2 cycles + 3rd line 2 cycles + (5th line 4 cycles + 6th line 3 cycles + 7th line 3 cycles) x 9 loops + (5th line 4 cycles + 6th line 3 cycles+7th row 2 cycles)=103 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle compared to the case of FIG. 195(a). With such an INITIAL module, it is possible to further shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

In the above-described embodiment, the INITIAL module is used and the command "LD HL, T_CPU_REG" is replaced with the command "LDF HL, T_CPU_REG" in the process of setting the setting data in the internal register. , an example of reducing the processing load has been described. However, such commands are applicable not only to the INITIAL module but also to various modules.

For example, even in the DGEXTRN module that executes the display data conversion process, there is a command "LD HL, T_SEG_PTN", and like the INITIAL module, the start address "T_SEG_PTN" of the main display display pattern data table is read into the HL register. there is Also, the starting address "T_SEG_PTN" is included in the range of 1200H to 1DFFH. Therefore, even in the DGEXTRN module, by changing the command "LD HL, T_SEG_PTN" to the command "LDF HL, T_SEG_PTN", it is possible to further shorten the command and reduce the processing load.

Also in the GET_ARY module that executes the pattern array data acquisition process, there is a command "LD HL, T_FIG_LIN", and like the INITIAL module, the top address "T_FIG_LIN" of the pattern array offset table for each active line is read out to the HL register. ing. Also, the starting address "T_FIG_LIN" is included in the range of 1200H to 1DFFH. Therefore, even in the GET_ARY module, by changing the command "LD HL, T_FIG_LIN" to the command "LDF HL, T_FIG_LIN", it is possible to further shorten the command and reduce the processing load.

By keeping the transfer source address within the range of 1200H to 1DFFH in this way, most of the commands "LD HL, mn" can be replaced with the command "LDF HL, mn". By applying such replacement to all processes in this embodiment, it is possible to reduce the total command size by 80 to 90 bytes, for example.

Such a command "LDF" can be employed not only in the INITIAL module described above but also in various modules such as the RANKSET module. Moreover, it can be used not only in slot machines but also in pachinko machines, such as PWRFAIL modules and DYM_OUT modules.

FIG. 197 is an explanatory diagram for explaining the RANKSET module. The RANKSET module shown in step S2020 of FIG. 85 performs set value switching processing, that is, switches set values and updates set value data. Here, the data table setting process at the time of setting value switching in step S2020-5 in the RANKSET module will be described.

The index "RANKSET:" on the first line in FIG. 197(a) indicates the start address of the RANKSET module. By the command "LD HL, T_RNK_SET" on the second line, the start address "T_RNK_SET" of the data table at the time of setting value switching is read to the HL register. The command "RST TABLET" on the third line calls the TABLET module described with reference to FIG. 138 as a subroutine. Since such a TABLESET module has already been explained, its detailed explanation is omitted here. Here, two variables (_WIN_DAT, _EXT_REQ) in the set value switching time data table are set to predetermined values.

Here, if the command "LDF" is replaced, the command group of FIG. 197(a) can be changed as shown in FIG. 197(b). The index "RANKSET:" on the first line in FIG. 197(b) indicates the start address of the RANKSET module. By the command "LDF HL, T_RNK_SET" on the second line, the start address "T_RNK_SET" of the data table at the time of setting value switching is read to the HL register. The start address "T_RNK_SET" of the data table at the time of setting value switching is arranged in the range of 1200H to 1DFFH in the used area of the main ROM 500b. The command "RST TABLET" on the third line calls the TABLET module described with reference to FIG. 138 as a subroutine. Thus, two variables (_WIN_DAT, _EXT_REQ) in the set value switching time data table are set to predetermined values as in FIG. 197(a).

Here, the total command size of commands of the RANKSET module shown in FIG. The total execution cycle is 3 cycles on the 2nd line + 4 cycles on the 3rd line = 7 cycles. On the other hand, the total command size of the commands of the RANKSET module shown in FIG. The execution cycle is 2 cycles on the 2nd line + 4 cycles on the 3rd line = 6 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle compared to the case of FIG. 197(a). With such a RANKSET module, it is possible to further shorten the commands, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

FIG. 198 is an explanatory diagram for explaining the PWRFAIL module. The PWRFAIL module shown in step S300 of FIG. 25 performs saving processing when the power is turned off, that is, switches the setting value and updates the setting value data. Note that the output port clear processing in step S300-11 in the PWRFAIL module will be described here.

Assume that 00H is set in the A register in advance as the initial value of the output port. The index "PWRFAIL:" on the first line in FIG. 198(a) indicates the start address of the PWRFAIL module. The command "LD HL, D_OUT_PRT" on the second line causes the top address "D_OUT_PRT" of the output port address table to be read to the HL register. By the command "LD B, @PRT_CLR_LOP" on the third line, the output port initialization loop counter value (here, 13) stored at the address "@PRT_CLR_LOP" is read to the B register as the number of loops.

The index “PWRFAIL — 20:” on the fourth line in FIG. 198(a) indicates the start address of the repeated processing. The value (output port address) stored at the address indicated by the HL register is read to the C register by the command "LD C, (HL)" on the fifth line. The command "OUT (C), A" on the sixth line outputs the value of the A register (here, 00H) to the value indicated by the C register (internal register), and clears the output port.

Subsequently, the value of the HL register is incremented by one by the command "INC HL" on the 7th line in FIG. 198(a). The command "DJNZ PWRFAIL_20" on the eighth line decrements the value of the B register (subtracts "1"). , the process moves to the next command after the current command. Here, since the number of data is "13", the value of the B register becomes 0 when the processing from "PWRFAIL_20" is repeated 13 times. Thus the output port is cleared.

Here, by replacing with the command "LDF", the command group of FIG. 198(a) can be changed as shown in FIG. 198(b). It is also assumed here that 00H is set in the A register in advance as the initial value of the output port. The index "PWRFAIL:" on the first line in FIG. 198(b) indicates the start address of the PWRFAIL module. The command "LDF HL, D_OUT_PRT" on the second line causes the top address "D_OUT_PRT" of the output port address table to be read to the HL register. The top address "D_OUT_PRT" of the output port address table is arranged in the range of 1200H to 1DFFH in the used area of the main ROM 500b. By the command "LD B, @PRT_CLR_LOP" on the third line, the output port initialization loop counter value (here, 13) stored at the address "@PRT_CLR_LOP" is read to the B register as the loop count.

The index “PWRFAIL — 20:” on the 4th line in FIG. 198(b) indicates the starting address of the repeated processing. The value (output port address) stored at the address indicated by the HL register is read to the C register by the command "LD C, (HL)" on the fifth line. The command "OUT (C), A" on the sixth line outputs the value of the A register (here, 00H) to the value indicated by the C register (internal register), and clears the output port.

Subsequently, the value of the HL register is incremented by 1 by the command "INC HL" on the 7th line in FIG. 198(b). The command "DJNZ PWRFAIL_20" on the eighth line decrements the value of the B register (subtracts "1"). , the process moves to the next command after the current command. Here, since the number of data is "13", the value of the B register becomes 0 when the processing from "PWRFAIL_20" is repeated 13 times. Thus the output port is cleared.

Here, the total command size of commands of the PWRFAIL module shown in FIG. 1st command "LD C, (HL)" 1 byte + 6th line command "OUT (C), A" 2 bytes + 7th line command "INC HL" 1 byte + 8th line command "DJNZ PWRFAIL_20" 2 bytes = 11 bytes, and the total execution cycle is: 2nd line 3 cycles + 3rd line 2 cycles + 5th line 2 cycles + 6th line 3 cycles + 7th line 1 cycle + 8th line 3 cycles (2 cycles) = 14 cycles (13 cycles) ). Here, since the output port initialization loop counter value=13, the commands on the 5th to 8th lines are repeated 13 times. Therefore, the actual total execution cycle is: 2nd line 3 cycles + 3rd line 2 cycles + (5th line 2 cycles + 6th line 3 cycles + 7th line 1 cycle + 8th line 3 cycles) x 12 loops + (5th line 2 cycles+6th row 3 cycles+7th row 1 cycle+8th row 2 cycles)=121 cycles.

On the other hand, the total command size of the commands of the PWRFAIL module shown in FIG. command "LD C, (HL)" 1 byte + 6th line command "OUT (C), A" 2 bytes + 7th line command "INC HL" 1 byte + 8th line command "DJNZ PWRFAIL_20" 2 bytes = 10 bytes, and the total execution cycle is: 2nd line 2 cycles + 3rd line 2 cycles + 5th line 2 cycles + 6th line 3 cycles + 7th line 1 cycle + 8th line 3 cycles (2 cycles) = 13 cycles (12 cycles) becomes. Here, since the output port initialization loop counter value=13, the commands on the 5th to 8th lines are repeated 13 times. Therefore, the actual total execution cycle is: 2nd line 2 cycles + 3rd line 2 cycles + (5th line 2 cycles + 6th line 3 cycles + 7th line 1 cycle + 8th line 3 cycles) x 12 loops + (5th line 2 cycles+6th row 3 cycles+7th row 1 cycle+8th row 2 cycles)=120 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle compared to the case of FIG. 198(a). With such a PWRFAIL module, it is possible to further shorten commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

FIG. 199 is an explanatory diagram for explaining the DYM_OUT module. The DYM_OUT module shown in step S400-5 of FIG. 26 includes a first special symbol display device 160, a second special symbol display device 162, a first special symbol reservation display device 164, a second special symbol reservation display device 166, and a normal symbol. A dynamic port output process for controlling the lighting of the indicator 168, the normal symbol reservation indicator 170, the right hitting information indicator 172, and the performance display monitor 184 is executed.

The index "DYM_OUT:" on the first line in FIG. 199(a) indicates the head address of the DYM_OUT module. The command "LD HL, D_DYM_SEL" on the second line causes the top address "D_DYM_SEL" of the dynamic display selection table to be read to the HL register. The WORDSEL module described with reference to FIGS. 127 to 130 is called as a subroutine by the command "RST WORDSEL" on the third line. Since the WORDSEL module has already been described, a detailed description thereof will be omitted here. Thus, four 2-byte data in the dynamic display selection table are selected.

Here, if the command "LDF" is replaced, the command group of FIG. 199(a) can be changed as shown in FIG. 199(b). The index "DYM_OUT:" on the first line in FIG. 199(b) indicates the head address of the DYM_OUT module. The command "LDF HL, D_DYM_SEL" on the second line causes the top address "D_DYM_SEL" of the dynamic display selection table to be read to the HL register. The top address "D_DYM_SEL" of the dynamic display selection table is arranged in the range of 1200H to 1DFFH in the used area of the main ROM 500b. The WORDSEL module described with reference to FIGS. 127 to 130 is called as a subroutine by the command "RST WORDSEL" on the third line. Thus, four 2-byte data in the dynamic display selection table are selected.

Here, the total command size of commands of the DYM_OUT module shown in FIG. The total execution cycle is 3 cycles on the 2nd line + 4 cycles on the 3rd line = 7 cycles. On the other hand, the total command size of the commands of the DYM_OUT module shown in FIG. The execution cycle is 2 cycles on the 2nd line + 4 cycles on the 3rd line = 6 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle compared to the case of FIG. 199(a). Such a DYM_OUT module makes it possible to further shorten commands, reduce the processing load, and secure the capacity of the control area for game control processing.

<Command "SET">
FIG. 200 is a flow chart showing specific processing of the IPT_PD module. Here, as arbitrary processing, the CAL_MOD module for executing the state-specific module execution processing shown in step S3100-21 in FIG. The process of setting the external signal 4, which is part of the IPT_PD module that selectively transitions (every 5.96 msec) and performs the external signal output control process, will be described. Numerical values of step S in this figure are used only in the explanation of this figure. Also, in the description of the IPT_PD module, the predetermined register is the HL register.

The main CPU 500a executes arbitrary processing as shown in FIG. The main CPU 500a first performs subtraction processing of a counter related to the external signal output holding timer (S1). Then, the main CPU 500a sets the address of the output port 3 image in the HL register (S2). Subsequently, the main CPU 500a determines whether or not the security signal ON condition is satisfied by subtraction processing in step S1. A bit is raised (set to 1) (S3). Then, the IPT_PD module is terminated and the routine returns to the routine one step above (S4). Thus, the external signal 4 can be set.

FIG. 201 is an explanatory diagram for explaining an example of commands for realizing the IPT_PD module. The flowchart shown in FIG. 200 is realized by the program shown in FIG. 201, for example.

The index “IPT_PD:” on the first line in FIG. 201 indicates the start address of the IPT_PD module. The command "RST RAM_DEC" on the second line is a command to call a general-purpose module that decrements the variable by 1, and this command causes the counter related to the external signal output holding timer to be decremented. Here, at least the zero flag is updated by the command "RST RAM_DEC". The command on the second line corresponds to step S1 in FIG. By the command "LDQ HL, LOW_OUT_PT3" on the third line, the value of the Q register is read to the H register, and the value of the lower 1 byte of the address "_OUT_PT3" is read to the L register. The command "LDQ HL, LOW_OUT_PT3" does not change the zero flag. The command on the third line corresponds to step S2 in FIG.

By the command "JR Z, IPT_PD03" on the fourth line in FIG. 201, it is determined whether or not the subtraction result of the command "RST RAM_DEC" on the second line is zero. That is, if the security signal ON condition is not satisfied, the process moves to the index "IPT_PD03:" on the sixth line, and if not zero (if the zero flag is not set), the following processing is performed. The command "SET @EXT_SG4_POS, (HL)" on the fifth line is the output port 3 image, that is, the value (here, 2) defined by @EXT_SG4_POS in the value stored at the address indicated by the HL register. set the bit up. The index "IPT_PD03:" on the sixth line indicates the destination of the command "JR Z, IPT_PD03" on the fourth line. The commands on the 4th to 6th lines correspond to step S3 in FIG. Then, the command "RET" on line 7 in FIG. 201 returns to the routine one level above. The command on the 7th line corresponds to step S4 in FIG.

In this way, the total command size of the commands of the IPT_PD module shown in FIG. JR Z, IPT_PD03" 2 bytes + 5th line command "SET @EXT_SG4_POS, (HL)" 2 bytes + 7th line command "RET" 1 byte = 8 bytes, total execution cycle is command "JR Z, IPT_PD03" 4 cycles on the 2nd row + 2 cycles on the 3rd row + 2 cycles on the 4th row + 5 cycles on the 5th row + 3 cycles on the 7th row = 16 cycles. Row 4 cycles+3rd row 2 cycles+4th row 3 cycles+7th row 3 cycles=12 cycles. By providing the processing of the 4th to 6th lines in the IPT_PD module, bit manipulation of the output port 3 image can be performed according to the result of the subtraction.

FIG. 202 is an explanatory diagram for explaining another example of commands for realizing the IPT_PD module. Here, the command group of the IPT_PD module in FIG. 201 is replaced with the command group of the IPT_PD module in FIG.

The index "IPT_PD:" on the first line in FIG. 202 indicates the start address of the IPT_PD module. The command "RST RAM_DEC" on the second line is a command to call a general-purpose module that decrements the variable by 1, and this command causes the counter related to the external signal output holding timer to be decremented. Here, at least the zero flag is updated by the command "RST RAM_DEC". The command on the second line corresponds to step S1 in FIG. By the command "LDQ HL, LOW_OUT_PT3" on the third line, the value of the Q register is read to the H register, and the value of the lower 1 byte of the address "_OUT_PT3" is read to the L register. The command "LDQ HL, LOW_OUT_PT3" does not change the zero flag. The command on the third line corresponds to step S2 in FIG.

The command "SET NZ, @EXT_SG4_POS, (HL)" on the fourth line in FIG. If the signal ON condition is met, the bit of the value defined by @EXT_SG4_POS (here, 2) in the output port 3 image, ie, the value of the address indicated by the HL register, is raised. The command on the fourth line corresponds to step S3 in FIG. Then, the command "RET" on the fifth line in FIG. 202 returns to the routine one level above. This fifth line command corresponds to step S4 in FIG.

Here, the command "SET cc, b, (HL)" sets the b-th bit of the value (variable) of the address indicated by the HL register if the flag (zero flag or carry flag) corresponding to cc is true. is a command. Such a command has a command size of "2" and an execution cycle of "5" ("2"). The number of cycles in parentheses indicates the execution cycle when the flag is not true in the command "SET cc,b,(HL)".

In this way, the total command size of the commands of the IPT_PD module shown in FIG. SET NZ, @EXT_SG4_POS, (HL)" 2 bytes + 5th line command "RET" 1 byte = 6 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 2 cycles + 4th line 5 cycles (2 cycles )+5th row 3 cycles=14 cycles (11 cycles). Therefore, compared to the case of FIG. 201, the total command size is reduced by 2 bytes, and the total execution cycle is reduced by at least 1 cycle. With this IPT_PD module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Also, as can be understood by comparing FIGS. 201 and 202, the command group occupying three lines (fourth to sixth lines) in FIG. ), it is possible to reduce the number of commands and the design load.

Although the bit setting command "SET cc, b, (HL)" has been described here, the bit setting command "SET cc, b, r" can also be used. can. Here, the command "SET cc, b, r" is r (A register, B register, D register, E register, H register, L register) if the flag (zero flag or carry flag) corresponding to cc is true. ) is a command to set the b-th bit of the value. Such a command has a command size of "2" and an execution cycle of "2".

Such a command "SET" can be employed not only in the IPT_PD module described above but also in various modules such as the DYNMOUT module. Moreover, it can be used not only in slot machines but also in pachinko machines, for example, EXT_PRC modules.

FIG. 203 is an explanatory diagram for explaining the DYNMOUT module. In the DYNMOUT module shown in step S3100-7 of FIG. 98, the main CPU 500a outputs the set output image to the output port, the main credit display section 430, the main payout display section 432, the inserted number display, and the start display. , stop switches 420a, 420b, and 420c, the replay indicator, and the section indicator 460, dynamic port output processing (dynamic lighting control processing) is executed.

The index "DYNMOUT:" on the first line in FIG. 203(a) indicates the head address of the DYNMOUT module. By the command "RESQ @CHN_DSP_BIT, (LOW_WIN_DAT+1)" on the second line, the value of the Q register is set as the upper 1 byte of the address, and the value obtained by adding 1 to the lower 1 byte of the address "_WIN_DAT" is set as the lower 1 byte of the address. , the bit indicated by @CHN_DSP_BIT (here, bit 7) in the value stored at that address (main display data buffer 2) is set to 0 (reset). By the command "LDQ A, (LOW_OUT_PT2)" on the third line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_OUT_PT2" is set as the lower 1 byte of the address, and stored at that address. Reads the resulting value (output port 2 image) into the A register. According to the command "JAND Z, A, 00000011B, DYNMOUT02" on the 4th line, if the AND of the value of the A register and 00000011B is zero, move to the address "DYNMOUT02"; process. By the command "SETQ @CHN_DSP_BIT, (LOW_WIN_DAT+1)" on the fifth line, the value of the Q register is set as the upper 1 byte of the address, and the value obtained by adding 1 to the lower 1 byte of the address "_WIN_DAT" is set as the lower 1 byte of the address. , 1 is set in the bit (here, bit 7) indicated by @CHN_DSP_BIT of the value (main display unit data buffer 2) stored at that address. The index "DYNMOUT02:" on the sixth line indicates the destination of the command "JAND Z, A, 00000011B, DYNMOUT02" on the fourth line. Thus, bit 7 of the main display data buffer 2 can be set according to the value of the lower two bits of the output port 2 image.

Here, if the command "SET" is replaced, the command group of FIG. 203(a) can be changed as shown in FIG. 203(b). The index "DYNMOUT:" on the first line in FIG. 203(b) indicates the head address of the DYNMOUT module. By the command "LDQ HL, LOW _WIN_DAT+1" on the second line, the value of the Q register is read to the H register, and the value obtained by adding 1 to the value of the lower 1 byte of the address "_WIN_DAT" is read to the L register. The command "RES @CHN_DSP_BIT, (HL)" on the third line sets 0 (reset) to the bit indicated by @CHN_DSP_BIT (here, bit 7) in the value stored at the address indicated by the HL register. By the command "LDQ A, (LOW_OUT_PT2)" on the fourth line, the value of the Q register is set as the upper 1 byte of the address, the value of the lower 1 byte of the address "_OUT_PT2" is set as the lower 1 byte of the address, and stored at that address. Reads the resulting value (output port 2 image) into the A register. The command "AND A, 00000011B" on the fifth line performs a logical product operation of the value of the A register and 00000011B to mask the A register. If the command "SET NZ, @CHN_DSP_BIT, (HL)" on the sixth line indicates that the operation result of the command "AND A, 00000011B" on the fifth line is not zero (if the zero flag is not set), the HL register indicates 1 is set in the bit (here, bit 7) indicated by @CHN_DSP_BIT in the address value (main display unit data buffer 2). Thus, as in FIG. 203(a), bit 7 of the main display data buffer 2 can be set according to the value of the lower 2 bits of the output port 2 image.

Here, the total command size of commands of the DYNMOUT module shown in FIG. )” 2nd byte + 4th line command “JAND Z, A, 00000011B, DYNMOUT02” 3rd byte + 5th line command “SETQ @CHN_DSP_BIT, (LOW_WIN_DAT+1)” 3 bytes = 11 bytes, total execution cycle is output port 2nd row + 3rd row 3 cycles + 4th row 3 cycles + 5th row 6 cycles = 18 cycles, and the lower 2 bits of the output port 2 image are all 0. In this case, 2nd row 6 cycles+3rd row 3 cycles+4th row 4 cycles=13 cycles.

On the other hand, the total command size of the commands of the DYNMOUT module shown in FIG. 203(b) is the second line command "LDQ HL, LOW_WIN_DAT+1" 2 bytes + the third line command "RES @CHN_DSP_BIT, (HL)" 2 bytes. + 4th line command "LDQ A, (LOW_OUT_PT2)" 2 bytes + 5th line command "AND A, 00000011B" 2 bytes + 6th line command "SET NZ, @CHN_DSP_BIT, (HL)" 2 bytes = 10 bytes When the lower two bits of the output port 2 image are not 0, the total execution cycle is: 2nd row 2 cycles + 3rd row 5 cycles + 4th row 3 cycles + 5th row 2 cycles + 6th row 5 cycles = 17 cycles, If the lower 2 bits of the output port 2 image are all 0, then 2nd row + 3rd row 5 cycles + 4th row 3 cycles + 5th row 2 cycles + 6th row 2 cycles = 14 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte compared to the case of FIG. 203(a). With such a DYNMOUT module, it is possible to further shorten commands and secure the capacity of the control area for performing game control processing.

FIG. 204 is an explanatory diagram for explaining the EXT_PRC module. In the EXT_PRC module shown in step S400-29 of FIG. 26, the main CPU 500a performs external information management processing, that is, sets output data for external information to be output from the game information output terminal board 312 to the outside.

The index "EXT_PRC:" on the first line in FIG. 204(a) indicates the start address of the EXT_PRC module. By the command "LD BC, @D_SEC_LOP*256+0" on the second line, @D_SEC_LOP (here, 8), which is the number of RAMs to be checked (the number of loops), is set in the B register, and the initial value of the synthesized bit data is set in the C register. 0 is set. With the command "JR Z, EXT_PRC_15" on the third line, it is determined whether or not the AND of the target ram addresses calculated before executing the command is zero. ), move to the index "EXT_PRC_15:" on the fifth line, and if it is not zero (if the zero flag is not set), process the fourth line. The command "SET @EXT_SEC_POS, C" on the fourth line causes the bit of the value (here, bit 6) defined by @EXT_SEC_POS in the value of the C register (composite bit data) to be set. The index "EXT_PRC_15:" on the fifth line indicates the destination of the command "JR Z, EXT_PRC_15" on the third line. In this way, bit 6 of the synthesized bit data can be set according to the result of the AND operation of the target ram addresses.

Here, if the command "SET" is replaced, the command group of FIG. 204(a) can be changed as shown in FIG. 204(b). The index "EXT_PRC:" on the first line in FIG. 204(b) indicates the start address of the EXT_PRC module. By the command "LD BC, @D_SEC_LOP*256+0" on the second line, @D_SEC_LOP (here, 8), which is the number of RAMs to be checked (the number of loops), is set in the B register, and the initial value of the synthesized bit data is set in the C register. 0 is set. The command "SET NZ, @EXT_SEC_POS, C" on the third line determines whether or not the AND of the target ram addresses calculated before the command is executed is zero. If not set), set the bit of the value (here, bit 6) defined by @EXT_SEC_POS in the value of the C register (composite bit data). Thus, as in FIG. 204(a), it is possible to set bit 6 of the synthesized bit data according to the result of the AND operation of the target ram address.

Here, the total command size of the commands of the EXT_PRC module shown in FIG. 204(a) is the second line command "LD BC, @D_SEC_LOP*256+0" 2 bytes + the third line command "JR Z, EXT_PRC_15" 2 bytes. + 4th line command "SET @EXT_SEC_POS, C" 2 bytes = 6 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 2 cycles + 4th line 2 cycles = 6 cycles if the AND is not 0 , if the AND is 0, 2 cycles on the 2nd row+3 cycles on the 3rd row=5 cycles.

On the other hand, the total command size of the commands of the EXT_PRC module shown in FIG. 204(b) is the second line command "LD BC, @D_SEC_LOP*256+0" 2 bytes + the third line command "SET NZ, @EXT_SEC_POS, C". 2 bytes = 4 bytes, and if the AND is not 0, the total execution cycle is: 2nd row 2 cycles + 3rd row 5 cycles = 7 cycles, and if the AND is 0, 2nd row 2 cycles + 3 rows Second cycle = 4 cycles. Therefore, it can be understood that the total command size is reduced by 2 bytes compared to the case of FIG. 204(a). With such an EXT_PRC module, it becomes possible to further shorten the command and secure the capacity of the control area for performing the game control process.

<Command "JANDQ">
FIG. 205 is a flow chart showing specific processing of the STOPDCT module. Here, as an arbitrary process, the process S2500-23 for confirming the stop indicator, which is a part of the STOPDCT module for executing the process during rotation of the reel shown in step S2500 in FIG. 92, will be described. Numerical values of step S in this figure are used only in the explanation of this figure. Also, during the description of the STOPDCT module, the predetermined register is the HL register.

The main CPU 500a executes arbitrary processing as shown in FIG. The main CPU 500a first performs a process of extracting an operation target bit (S1). Through such processing, the operation target bit is set in the A register. Then, the main CPU 500a synthesizes the operation target bit of the A register and the rotating flag set in advance in the D register (S2). Subsequently, the main CPU 500a confirms the stop indicator by taking a logical AND with the value of the address indicating the stop indicator (S3). The process is repeated from the beginning of the module, and if the stop indicator is not lit in red (NO in S4), the next process is executed. Then, the STOPDCT module ends by moving to the STP_REL module that executes the rotation stop processing (S5). In this way, it becomes possible to carry out the pressing process according to the state of the stop indicator.

FIG. 206 is an explanatory diagram for explaining an example of a command for realizing the STOPDCT module. The flowchart shown in FIG. 205 is realized by the program shown in FIG. 206, for example.

The index "STOPDCT:" on the first line in FIG. 206 indicates the start address of the STOPDCT module. The command "CALLF SMPLBIT" on the second line is a command to call the SMPLBIT module that executes the operation target bit extraction process, and the bit corresponding to the stop switch that is the operation target (actually operated) by this command is set to A. Set in a register. The second line command corresponds to step S1 in FIG. By the command "AND A, D" on the 3rd line, the logical product of the A register in which the operation target bit is set and the D register in which the rotating flag is set in advance, and the result is stored in the A register. to hold. The command on the third line corresponds to step S2 in FIG.

The command "ANDQ A, (LOW_OUT_PT4)" on the fourth line in FIG. The value of the display) and the value of the A register are ANDed, and the result is held in the A register. The command on the fourth line corresponds to step S3 in FIG. The command "JR Z, STOPDCT" on the fifth line determines whether or not the operation result of the command "ANDQ A, (LOW_OUT_PT4)" on the fourth line is zero. ), move to the index "STOPDCT:" (second predetermined value) on the first line, and if not zero (if the zero flag is not set), perform the following processing. The command on the fifth line corresponds to step S4 in FIG.

Thus, the total command size of the commands of the STOPDCT module shown in FIG. A, (LOW_OUT_PT4)" 3 bytes + 5th line command "JR Z, STOPDCT" 2 bytes = 8 bytes. 3 cycles (2 cycles)=12 cycles (11 cycles). Note that the number of cycles in parentheses indicates the execution cycle when the command "JR Z, STOPDCT" does not move. By providing the processing of the fourth and fifth lines in the STOPDCT module, it becomes possible to perform the depression processing according to the state of the stop indicator.

FIG. 207 is an explanatory diagram for explaining another example of commands for realizing the STOPDCT module. Here, the command group of the STOPDCT module in FIG. 206 is replaced with the command group of the STOPDCT module in FIG.

The index "STOPDCT:" on the first line in FIG. 207 indicates the start address of the STOPDCT module. The command "CALLF SMPLBIT" on the second line is a command to call the SMPLBIT module that executes the operation target bit extraction process, and the bit corresponding to the stop switch that is the operation target is set in the A register by this command. The command on the second line corresponds to step S1 in FIG. By the command "AND A, D" on the 3rd line, the logical product of the A register in which the operation target bit is set and the D register in which the rotating flag is set in advance, and the result is stored in the A register. to hold. The command on the third line corresponds to step S2 in FIG.

The command "JANDQ Z, A, (LOW_OUT_PT4), STOPDCT" on the fourth line in FIG. The logical product of the value (stop indicator value) and the value of the A register is calculated, and it is determined whether or not the calculation result is zero. If it is zero (if the zero flag is set), the first line index "STOPDCT:" (second predetermined value), and if it is not zero (if the zero flag is not set), the next process is performed. The commands on the fourth line correspond to steps S3 and S4 in FIG.

Here, the command "JANDQ cc, A, (k), e" is a value (first predetermined value) in which the value of the Q register is the upper 1 byte and the value of the address indicated by k is the lower 1 byte, If the flag (zero flag or carry flag) corresponding to cc is true, move to the address indicated by e (second predetermined value), and move to the address indicated by e (second predetermined value). If the corresponding flag is not true, it is a command to move on to the next process. Such a command has a command size of "4" and an execution cycle of "6" ("5"). The number of cycles in parentheses indicates the execution cycle when the flag is not true in the command "JANDQ cc, A, (k), e".

The total command size of the commands of the STOPDCT module shown in FIG. (LOW_OUT_PT4), STOPDCT" 4 bytes=7 bytes, and the total execution cycle is 2nd line 4 cycles+3rd line 1 cycle+4th line 6 cycles (5 cycles)=11 cycles (10 cycles). The number of cycles in parentheses indicates the execution cycle when the command "JANDQ Z, A, (LOW_OUT_PT4), STOPDCT" does not move. Therefore, the total command size is reduced by 1 byte and the total execution cycle is reduced by at least 1 cycle compared to the case of FIG. With such a STOPDCT module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Also, as can be understood by comparing FIGS. 206 and 207, the command group occupying two lines (4th and 5th lines) in FIG. ), it is possible to reduce the number of commands and the design load.

<Command "CALLEX">
The E_SETTM module sets the input abnormality non-monitoring timer setting process, that is, sets the input abnormality non-monitoring timer in the ERRWAIT module that executes the error wait process shown in step S2200-11 of FIG. 89 and step S2800-39 of FIG. It is a module for The E_SETTM module is arranged in another area (2000H to 3FBFH) of the main ROM 500b.

The main CPU 500a reads out the program in the used area from the main ROM 500b, executes the read program, calls the E_SETTM module in another area as a subroutine in arbitrary processing, and executes the E_SETTM module. The E_SETTM module sets a power-on failure non-monitoring timer.

FIG. 208 is a flow chart showing specific processing of the E_SETTM module. Here, as arbitrary processing, in the ERRWAIT module that executes the error wait processing shown in step S2200-11 in FIG. 89 and step S2800-39 in FIG. explain. Numerical values of step S in this figure are used only in the explanation of this figure.

The main CPU 500a executes arbitrary processing as shown in FIG. 208(a). The main CPU 500a checks the blocker state, and if bit 3 (blocker solenoid output bit number) of the output port 4 image is not 0, calls the E_SETTM module in another area. Therefore, the main CPU 500a first disables the interrupt (S1), and calls the E_SETTM module in another area as a subroutine (S2).

As shown in FIG. 208(b), the main CPU 500a saves the general-purpose registers (A register, B register, C register, D register, E register, H register, L register, F register) in the E_SETTM module (S3). . Then, the main CPU 500a sets the input abnormality non-monitoring timer value as an initial value in the A register (S4), stores the value of the A register in the value indicated by the predetermined address (input abnormality non-monitoring timer), A closing abnormality non-monitoring timer is set (S5). When such processing is completed, the main CPU 500a restores the general-purpose register (S6), permits interrupts (S7), terminates the E_SETTM module, and returns to the routine one level above (S8).

Here, the E_SETTM module is designed to satisfy all of the above conditions (1) to (6) in order to properly divide roles between the usage area and another area while ensuring the fairness of the gaming machine. ing.

FIG. 209 is an explanatory diagram for explaining an example of commands for realizing the E_SETTM module. Of these, FIG. 209(a) shows a command group for arbitrary processing that calls the E_SETTM module, and FIG. 209(b) shows a command group for the E_SETTM module. The flowchart shown in FIG. 208 is realized by the program shown in FIG. 209, for example.

The interrupt is disabled by the command "DI" on the first line of FIG. 209(a). Such a command on the first line corresponds to step S1 in FIG. 208(a). The E_SETTM module is called as a subroutine by the command "CALL E_SETTM" on the second line. The command on the second line corresponds to step S2 in FIG. 208(a).

The index "E_SETTM:" on the first line in FIG. 209(b) indicates the head address of the E_SETTM module. The command "EX AF, AF'" on the second line replaces the value of the pair register AF with the value of the opposite register, that is, the pair register AF', and saves the value of the pair register AF. By the command "EXX" on the third line, the values of the pair registers BC, DE and HL are exchanged with the values of the pair registers BC', DE' and HL' which are back registers, and the values of the pair registers BC, DE and HL are changed to be evacuated. The commands on the second and third lines correspond to step S3 in FIG. 208(b).

The command "LD A, @MDL_WAT_TMR" on the fourth line in FIG. 6+1) is read into the A register. The command on the fourth line corresponds to step S4 in FIG. 208(b). By the command "LD (_EX_SLTM), A" on the fifth line, the value of the A register is stored in the variable "_EX_SLTM" as the input abnormality non-monitoring timer. The command on the fifth line corresponds to step S5 in FIG. 208(b). In this way, it is possible to set the closing abnormality non-monitoring timer value to the closing abnormality non-monitoring timer.

The command "EXX" on the 6th line in FIG. The values of DE and HL are returned. The command "EX AF, AF'" on the 7th line replaces the value of the pair register AF with the value of the opposite register, that is, the pair register AF', and restores the value of the pair register AF. The commands on the 6th and 7th lines correspond to step S6 in FIG. 208(b). The interrupt is permitted by the command "EI" on line 8 of FIG. 209(b). Here, even if the command "EI" is issued before returning from the subroutine, the interrupt is appropriately permitted. Therefore, by describing the command "EI" in the subroutine, it is possible to secure the capacity of the used area. The command on the eighth line corresponds to step S7 in FIG. 208(b). Then, the command "RET" on the ninth line returns to the routine one level above. The command on the ninth line corresponds to step S8 in FIG. 208(b). In this way, it becomes possible to set the closing abnormality non-monitoring timer in another area.

Thus, the total command size of the BLKSHUT module shown in FIG. 209A and the E_SETTM module shown in FIG. command "CALL E_SETTM" 3 bytes + 2nd line command "EX AF, AF'" 1 byte + 3rd line command "EXX" 1 byte + 4th line command "LD A, @MDL_WAT_TMR " 2nd byte + 5th line command "LD (_EX_SLTM), A" 4th byte + 6th line command "EXX" 1st byte + 7th line command "EX AF, AF'" 1st byte + 8th line command "EI" 1 byte + 1 byte of the command "RET" on the 9th line = 16 bytes. Cycle + 3rd row 1 cycle + 4th row 2 cycle + 5th row 4 cycle + 6th row 1 cycle + 7th row 1 cycle + 8th row 1 cycle + 9th row 3 cycle = 20 cycles. By providing such an E_SETTM module, the command "CALL E_SETTM" with a command size of 3 bytes can be used without setting the input abnormality non-monitoring timer in each module described above. It is possible to secure the capacity of the control area for performing control processing.

FIG. 210 is an explanatory diagram for explaining another example of commands for realizing the E_SETTM module. Here, the command group for arbitrary processing that calls the E_SETTM module in FIG. 209(a) is replaced with the command group for arbitrary processing that calls the E_SETTM module in FIG. 210(a), and the E_SETTM module command in FIG. group is replaced with the command group of the E_SETTM module in FIG. 210(b).

The E_SETTM module is called as a subroutine by the command "CALLEX E_SETTM" on the first line of FIG. 210(a). Such a command on the first line corresponds to step S2 in FIG. 208(a).

Here, the command "CALLEX mn" is a command for calling a subroutine having a start address indicated by a fixed value mn, like the command "CALL mn". However, the command "CALLEX mn" has multiple functions in addition to simply calling a subroutine like the command "CALL mn". For example, by executing this command, the non-maskable interrupt (NMI) and maskable interrupt (INT) are automatically disabled, and the register bank is switched from the first register bank 726 to the second register bank 728. Call a subroutine having a start address indicated by a fixed value mn. Therefore, there is no need for the command "DI" related to interrupt or the commands "EX AF, AF'" and "EXX" (or command "PUSH") related to saving. Therefore, the command "CALLEX E_SETTM" on the first line in FIG. 210(a) is executed not only in step S2 in FIG. 208(a), but also in step S1 in FIG. 208(a) and step S3 in FIG. handle. Such a command has a command size of "2" and an execution cycle of "4".

However, the command "CALLEX mn" has certain limitations. For example, if the call destination address is in the range of 2000H to 20FFH on the address map, the command size is "2" and the execution cycle is "4". is "4" and the execution cycle is "6". Therefore, in order to shorten the command, in this embodiment, the called address, for example, "E_SETTM" is arranged so as to be included within 2000H to 20FFH.

The index "E_SETTM:" on the first line in FIG. 210(b) indicates the start address of the E_SETTM module. By the command "LD A, @MDL_WAT_TMR" on the second line, the fixed value "@MDL_WAT_TMR", that is, (252/6+1) corresponding to 250.32 msec as the input abnormality non-monitoring timer value (initial value) is stored in the A register. read out. The command on the second line corresponds to step S4 in FIG. 208(b). The command "LD (_EX_SLTM), A" on the third line stores the value of the A register in the variable "_EX_SLTM" as the input abnormality non-monitoring timer. The command on the third line corresponds to step S5 in FIG. 208(b). In this way, it is possible to set the closing abnormality non-monitoring timer value to the closing abnormality non-monitoring timer.

The command "RETEX" on the fourth line in FIG. 210(b) returns to the routine one level above. The command on the fourth line corresponds to step S8 in FIG. 208(b). In this way, it becomes possible to set the closing abnormality non-monitoring timer in another area.

Here, the command "RETEX" is a command to return to the routine one level above, like the command "RET". However, the command "RETEX" is often used in pairs with the command "CALLEX mn", and has multiple functions in addition to simply returning from a subroutine like the command "RET". For example, executing this command automatically switches the register bank from the second register bank 728 to the first register bank 726, enables interrupts, and then returns to the routine one level above. Therefore, commands "EXX" and "EX AF, AF'" (or command "POP") related to return and command "EI" related to interrupt are not required. Therefore, the command "RETEX" on the fourth line of FIG. 210(b) corresponds not only to step S8 of FIG. 208(b) but also to steps S6 and S7 of FIG. 208(b). Such a command has a command size of "2" and an execution cycle of "5".

The total command size of the BLKSHUT module shown in FIG. 210(a) and the E_SETTM module shown in FIG. 2 bytes of the command "LD A, @MDL_WAT_TMR" on the second line + 4 bytes of the command "LD (_EX_SLTM), A" on the third line + 2 bytes of the command "RETEX" on the fourth line = 10 bytes, and the total execution cycle is , 4 cycles on the 1st line in FIG. 210(a)+2 cycles on the 2nd line in FIG. 210(b)+4 cycles on the 3rd line+5 cycles on the 4th line=15 cycles. Therefore, compared to the case of FIG. 209, the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by at least 5 cycles. With such an E_SETTM module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Also, as can be understood by comparing FIG. 209 and FIG. 210, in FIG. ) can be represented by two lines in FIG. , it is possible to reduce the design load.

Such a command "CALLEX" can be employed not only in the BLKSHUT module described above but also in various modules. In addition, it can be used not only in slot machines but also in pachinko machines, for example, DYM_OUT modules.

211 and 212 are explanatory diagrams for explaining the DYM_OUT module. The DYM_OUT module shown in step S400-5 of FIG. 26 includes a first special symbol display device 160, a second special symbol display device 162, a first special symbol reservation display device 164, a second special symbol reservation display device 166, and a normal symbol. A dynamic port output process for controlling the lighting of the indicator 168, the normal symbol reservation indicator 170, the right hitting information indicator 172, and the performance display monitor 184 is executed.

The interrupt is disabled by the command "DI" on the first line of FIG. 211(a). The E_DMOUT module is called as a subroutine by the command "CALL E_DMOUT" on the second line.

The index "E_DMOUT:" on the first line in FIG. 211(b) indicates the start address of the E_DMOUT module. The command "EX AF, AF'" on the second line replaces the value of the pair register AF with the value of the opposite register, that is, the pair register AF', and saves the value of the pair register AF. By the command "EXX" on the third line, the values of the pair registers BC, DE and HL are exchanged with the values of the pair registers BC', DE' and HL' which are back registers, and the values of the pair registers BC, DE and HL are changed. be evacuated. The address "R_ERW_IOB" of the identification segment output request buffer is set in the HL register by the command "LD HL, R_ERW_IOB" on the fourth line. A 1-byte value (common counter) stored at the address indicated by "R_COM_CNT" is read to the A register by the command "LD A, (R_COM_CNT)" on the fifth line. Here, the common counter is used to determine the common number for LED dynamic lighting control, and stores a value indicating the common number. By the command "LD A, (HL+A)" on the 6th line, the 1-byte value (display data) stored at the address indicated by the HL register plus the value of the A register (offset) is transferred to the A register. read out. The command "OUT (@OTC_PRT),A" on the 7th line sets the value of the U register to the upper 1 byte of the address and sets the fixed value " @OTC_PRT" is set as the lower 1 byte, and the value of the A register is output to that address. By the command "EXX" on the eighth line, the values of the pair registers BC, DE, HL and the values of the pair registers BC', DE', HL', which are back registers, are exchanged, and the values of the pair registers BC, DE, HL are changed. return. The command "EX AF, AF'" on the ninth line replaces the value of the pair register AF with the value of the pair register AF', which is a reverse register, and restores the value of the pair register AF. The command "EI" on line 10 enables interrupts. Here, even if the command "EI" is issued before returning from the subroutine, the interrupt is appropriately permitted. Therefore, by describing the command "EI" in the subroutine, it is possible to secure the capacity of the used area. Then, the command "RET" on the 11th line returns to the routine one level above. Thus, dynamic port output processing can be executed in another area.

Here, by replacing with the command "CALLEX", the command group in FIG. 211 can be changed as in FIG. The E_DMOUT module is called as a subroutine by the command "CALLEX E_DMOUT" on the first line of FIG. 212(a). Here, the called address, for example, "E_DMOUT" is arranged so as to be included within 2000H to 20FFH.

The index "E_DMOUT:" on the first line in FIG. 212(b) indicates the start address of the E_DMOUT module. The address "R_ERW_IOB" of the identification segment output request buffer is set in the HL register by the command "LD HL, R_ERW_IOB" on the second line. The 1-byte value (common counter) stored at the address indicated by "R_COM_CNT" is read to the A register by the command "LD A, (R_COM_CNT)" on the third line. By the command "LD A, (HL+A)" on the fourth line, the 1-byte value (display data) stored at the address obtained by adding (offset) the value of the A register to the address indicated by the HL register is transferred to the A register. read out. The command "OUT (@OTC_PRT),A" on the 5th line sets the value of the U register to the upper 1 byte of the address and sets the fixed value " @OTC_PRT" is set as the lower 1 byte, and the value of the A register is output to that address. The command "RETEX" on the 6th line returns to the routine one level above. In this way, dynamic port output processing can be executed in another area as in FIG.

Thus, the total command size of the DYM_OUT module shown in FIG. 211(a) and the E_DMOUT module shown in FIG. command "CALL E_DMOUT" 3 bytes + command "EX AF, AF'" on the second line in FIG. 3 bytes + 5th line command "LD A, (R_COM_CNT)" 3 bytes + 6th line command "LD A, (HL + A)" 3 bytes + 7th line command "OUT (@OTC_PRT), A" 2 bytes + 8 lines 1st command 'EXX' 1 byte + 9th line command 'EX AF, AF' 1 byte + 10th line command 'EI' 1 byte + 11th line command 'RET' 1 byte = 21 bytes, total execution 211(a) 1st line + 2nd line 5th cycle + 2nd line 1st cycle + 3rd line 1st cycle + 4th line 3rd cycle + 5th line 4th cycle + 6th line 4 Cycle + 7th row 3 cycle + 8th row 1 cycle + 9th row 1 cycle + 10th row 1 cycle + 11th row 3 cycle = 28 cycles.

On the other hand, the total command size of the DYM_OUT module shown in FIG. 212(a) and the E_DMOUT module shown in FIG. b) 2nd line command "LD HL, R_ERW_IOB" 3 bytes + 3rd line command "LD A, (R_COM_CNT)" 3 bytes + 4th line command "LD A, (HL+A)" 3 bytes + 5th line Command "OUT (@OTC_PRT), A" 2 bytes + 6th line command "RETEX" 2 bytes = 15 bytes, total execution cycle is 1st line 4 cycles in Fig. 212(a) + Fig. 212(b) 2nd row 3 cycles+3rd row 4 cycles+4th row 4 cycles+5th row 3 cycles+6th row 5 cycles=23 cycles. Therefore, compared with the case of FIG. 211, the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by 5 cycles. With such an E_DMOUT module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

By the way, as described with reference to FIGS. 208 to 210, the command "CALLEX mn" has a command size of "2" if the call destination address is in the range of 2000H to 20FFH on the address map. The execution cycle is "4", but in other ranges the command size is "4" and the execution cycle is "6". Therefore, it is desirable to arrange all call destination addresses in the range of 2000H to 20FFH. However, since the number of bytes that can be written is only 256 bytes in 2000H to 20FFH, the number of subroutines is limited if subroutines are written as they are in this range. For example, even if the E_SETTM module has a relatively small command size, the second line command "LD A, @MDL_WAT_TMR" 2 bytes + the third line command "LD (_EX_SLTM), A" 4 bytes The command "RETEX" on the +4th line occupies 2 bytes=8 bytes, so a large number of subroutines cannot be arranged.

Therefore, in this embodiment, substantially only the command "JP mn" relating to movement is arranged in the range of 2000H to 20FFH on the address map, and the body of the subroutine is arranged at the movement destination. Since the command size of the command "JP mn" is "3", by arranging the command "JP mn" in parallel in the range of 2000H to 20FFH on the address map, 256/3=86 modules can be called as subroutines. It becomes possible.

It is also possible to use the command "CALL mn" with a command size of "3" instead of the command "JP mn". , the number of subroutines is limited by the command "JP mn". Therefore, it is desirable to employ the command "JP mn". Specific processing of the E_SETTM module reflecting such contents will be described below.

FIG. 213 is a flow chart showing specific processing of the E_SETTM module. Here, as an arbitrary process, a part of the BLKSHUT module that executes the blocker blocking process will be described as in FIG. 208 . Numerical values of step S in this figure are used only in the explanation of this figure.

The main CPU 500a executes arbitrary processing as shown in FIG. 213(a). The main CPU 500a calls the RRE01 module as a subroutine in another area (S1).

Subsequently, as shown in FIG. 213(b), the main CPU 500a moves to the E_SETTM module without performing significant processing in the RRE01 module (S2). Thus, the RRE01 module is a module for moving to the E_SETTM module, and is arranged in the range of 2000H to 20FFH on the address map. In this way, a large number of subroutines can be arranged.

As shown in FIG. 213(c), the main CPU 500a sets the input abnormality non-monitoring timer value in the A register in the E_SETTM module (S3), and sets the A register value to a predetermined address (input abnormality non-monitoring timer). The data is stored in the indicated value, and a closing abnormality non-monitoring timer is set (S4). When such processing is completed, the main CPU 500a terminates the E_SETTM module and returns to the routine one level above (S5). Since the E_SETTM module is the destination of the RRE01 module, it is not restricted by the address map. Therefore, since it can be arranged arbitrarily in the range of 2100H to 3FBFH in the separate area, even if the total command size is large to some extent, it is allowed.

FIG. 214 is an explanatory diagram for explaining still another example of commands for realizing the E_SETTM module. Here, as shown in FIG. 214(b), an RRE01 module is newly provided for moving to the E_SETTM module.

The command "CALLEX PRE01" on the first line in FIG. 214(a) calls the RRE01 module instead of the E_SETTM module as a subroutine. Such a command on the first line corresponds to step S1 in FIG. 213(a). The command "CALLEX PRE01" also disables interrupts and saves general-purpose registers.

The index "PRE01:" on the first line in FIG. 214(b) indicates the head address of the PRE01 module. The command "JP E_SETTM" on the second line moves to the E_SETTM module body. Such a command corresponds to step S2 in FIG. 213(b).

When calling a plurality of subroutines through the command "CALLEX mn", an index indicating the calling address of the plurality of subroutines (for example, "PRE01:" and the command "JP mn" are consecutively placed in the range from 2000H to 20FFH). By doing so, the range from 2000H to 20FFH can be effectively used and a large number of subroutines can be arranged.

The index “E_SETTM:” on the first line in FIG. 214(c) indicates the head address of the E_SETTM module. By the command "LD A, @MDL_WAT_TMR" on the second line, the fixed value "@MDL_WAT_TMR", that is, (252/6+1) corresponding to 250.32 msec as the input abnormality non-monitoring timer value (initial value) is stored in the A register. read out. The command on the second line corresponds to step S3 in FIG. 213(c). By the command "LD (_EX_SLTM), A" on the third line, the value of the A register is stored in the variable "_EX_SLTM" as the input abnormality non-monitoring timer. The command on the third line corresponds to step S4 in FIG. 213(c). In this way, it is possible to set the closing abnormality non-monitoring timer value to the closing abnormality non-monitoring timer.

The command "RETEX" on the fourth line in FIG. 214(c) returns to the routine one level above. The command on the fourth line corresponds to step S5 in FIG. 213(c). In this way, it becomes possible to set the closing abnormality non-monitoring timer in another area. Note that the command "RETEX" also restores the general-purpose registers and enables interrupts.

In the example of FIG. 214, the total command size and the total execution cycle are increased by the command "JP E_SETTM" compared to the case of FIG. However, by moving to the subroutine main body via the command "JP E_SETTM", many subroutines can be arranged in the range of 2000H to 20FFH, expanding the limit on the number of subroutines, and furthermore, the command of the subroutine itself Since the size restriction is eased, as a result, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

In this way, even if only the command "JP mn" is placed in the range from 2000H to 20FFH, if the number of subroutines that can be placed is insufficient, that is, if there are 86 or more subroutines, the total command size of the module is small. is placed in the range of 2100H to 217FH (range of 128 bytes), and instead of command size "3" command "JP mn", command size "2" suitable for short distance movement "JR mn" may be used. By doing so, it becomes possible to arrange more commands "JR mn" in the range from 2000H to 20FFH.

<Command "ICPLMQA", "ICPLMQ">
The RAM_INC module is a module for RAM addition processing, that is, for incrementing a 1-byte variable in the main RAM 500c by 1 up to a predetermined number. Note that the RAM_INC module not only increments, but also sets a carry flag as a result of the increment. Also, the RAM_INC module can be used as a general-purpose module.

Such a RAM_INC module is called as a subroutine from multiple modules. For example, in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, it selectively shifts according to the game state and the effect state, and executes the present prognostic process (AT state=“3”). and the EXE_SET module for executing the execution flag setting process shown in step S2400-11 in FIG. , and the EXE_SET module for executing the execution flag setting process shown in step S2400-11 in FIG. ), and the EXE_SET module for executing the execution flag setting process shown in step S2400-11 in FIG. ”) is called from the BIT_LOT module or the like.

The main CPU 500a reads a program from the main ROM 500b, executes the read program, and increments a 1-byte value held in the main RAM 500c in arbitrary processing.

FIG. 215 is a flow chart showing specific processing of the RAM_INC module. Numerical values of step S in this figure are used only in the explanation of this figure. Also, in the description of the RAM_INC module, the predetermined register is the A register, the predetermined number is the upper limit value, and the specific address is the address to be incremented.

As shown in FIG. 215(a), the main CPU 500a sets an address to be incremented in the HL register in arbitrary processing (S1). Then, the main CPU 500a increments the 1-byte value stored at the address indicated by the HL register (S2), stores the incremented value at the address indicated by the HL address, and updates the value (S3). However, here, an upper limit (predetermined number) is set so that the result of incrementing does not exceed the upper limit.

216 and 217 are explanatory diagrams for explaining an example of commands for realizing the RAM_INC module. The flowchart shown in FIG. 215 is realized by the program shown in FIG. 216, for example.

The index “RAM_INC:” on the first line in FIG. 216 indicates the head address of the RAM_INC module. The command "LDQ HL, LOW_AT_SET" on the second line reads the value of the Q register to the H register, and reads the value of the lower 1 byte of the address "_AT_SET" to the L register. The command on the second line corresponds to step S1 in FIG. The command "LD A, (HL)" on the third line causes the 1-byte value (eg, 02H) stored at the address indicated by the HL register to be read to the A register, as shown in FIG. The command "INC A" on the fourth line in FIG. 216 causes the value of the A register to be incremented by 1 from 02H to 03H, for example, as shown in FIG. In addition, in order to provide versatility, instead of the command "LD A, (HL)" on the third line and the command "INC A" on the fourth line, the command "LD A, 1" and the command "ADD A, ( HL)" can also be used. In this case, the value to be incremented can be changed to a value other than 1 by changing the value of "1" stored in the A register.

The command "JCP C, A, 5, RAM_INC01" on the fifth line in FIG. 216 compares the value of the A register with the upper limit "5". ) and move to the address “RAM_INC01”. Thus, if the value of the A register is less than the upper limit value of 5, the next process can be omitted and the index "RAM_INC01" on the 7th row can be moved to. The command "LD A, 5" on the sixth line stores the upper limit value "5" in the A register. This is because when the value of the A register exceeds 5 by the command "INC A" on the 4th line, the value of the A register is forcibly overwritten to 5, so that the incremented result is 5 or less. be. Here, if the value of the A register before incrementing is 4, that is, if the value of the A register is incremented from 4 to 5, the value of the A register is already 5, so it must be updated to 5. However, adding processing to determine this increases the processing load. Therefore, giving priority to versatility, the value of the A register is forcibly updated to 5 in the same way as when 5 is exceeded. The commands on the 3rd to 6th lines correspond to step S2 in FIG.

The index “RAM_INC01” on the 7th line in FIG. 216 indicates the destination address of the command “JCP C, A, 5, RAM_INC01” on the 5th line. The command "LD (HL), A" on the eighth line stores the value of the A register (eg, 03H) at the address indicated by the HL register, as shown in FIG. The eighth line command corresponds to step S3 in FIG. In this way, it is possible to increment the 1-byte variable in the main RAM 500c by 1 up to a predetermined number and hold the incremented value in the A register (the value of the A register can be used in subsequent processing). Become.

Thus, the total command size of the commands of the RAM_INC module shown in FIG. 1st command "INC A" 1 byte + 5th line command "JCP C, A, 5, RAM_INC01" 3 bytes + 6th line command "LD A, 5" 2 bytes + 8th line command "LD (HL), A" 1 byte=10 bytes, and the total execution cycle is 2nd line 2 cycles+3rd line 2 cycles+4th line 1 cycle+5th line 4 cycles+6th line 2 cycles+8th line 2 cycles=13 cycles. By providing such a RAM_INC module, a 1-byte variable can be incremented uniformly and easily, so commands can be shortened and the capacity of the control area for game control processing can be secured.

FIG. 218 is an explanatory diagram for explaining another example of commands for implementing the RAM_INC module. Here, the command group of the RAM_INC module in FIG. 216 is replaced with the command group of the RAM_INC module in FIG.

The index “RAM_INC:” on the first line in FIG. 218 indicates the start address of the RAM_INC module. The command "ICPLMQA (LOW _AT_SET), 5" on the second line sets the value of the Q register to the upper 1 byte of the address, the value of the lower 1 byte of the address "_AT_SET" to the lower 1 byte of the address, and increments the address. The 1-byte value stored in the target address) is compared with the upper limit value "5". The byte value is incremented by 1 and stored in the A register, and the 1-byte value stored at the address to be incremented is updated. If the incremented value is 5 or more (if the carry flag is not set), the upper limit value "5" is stored in the A register, and the 1-byte value stored at the address to be incremented is set as the upper limit value. Update to "5". The commands on the second line correspond to steps S1 to S3 in FIG. In this way, it is possible to increment the 1-byte variable in the main RAM 500c by 1 up to a predetermined number and hold the incremented value in the A register (the value of the A register can be used in subsequent processing). Become.

Here, the command "ICPLMQA (k), n" sets the value of the Q register as the upper 1 byte of the address, the value k as the lower 1 byte of the address, the 1-byte value stored at the target address, and the upper limit value As a result, if it is less than n, the 1-byte value stored at the target address is incremented by 1, stored in the A register, and the 1-byte value stored at the target address is updated. , n or more, this command stores the upper limit value n in the A register and updates the 1-byte value stored in the target address to the upper limit value n. Such a command size is "4" and the execution cycle is "7".

The total command size of the commands of the RAM_INC module in FIG. 218 is the second line command "ICPLMQA (LOW_AT_SET), 5" 4 bytes=4 bytes, and the total execution cycle is the second line 7 cycles=7 cycles. Therefore, compared with the case of FIG. 216, the total command size is reduced by 6 bytes, and the total execution cycle is reduced by 6 cycles. With such a RAM_INC module, it is possible to further shorten commands, reduce processing load, and secure the capacity of the control area for performing game control processing.

Also, as can be understood by comparing FIG. 216 and FIG. 218, the command group occupying 7 lines (2nd to 8th lines) in FIG. It is possible to reduce the number of commands and reduce the design load.

FIG. 219 is an explanatory diagram for explaining still another example of commands for realizing the RAM_INC module. In the RAM_INC module described with reference to FIG. 218, an example was given in which the 1-byte variable in the main RAM 500c is incremented by 1 up to a predetermined number, and the value after the increment is held in the A register. However, depending on the processing, it may be sufficient to increment a 1-byte variable in the main RAM 500c by 1 up to a predetermined number without leaving the result in the A register. Here is an example of incrementing a 1-byte variable by 1 without updating the A register.

The index “RAM_INC:” on the first line in FIG. 219 indicates the start address of the RAM_INC module. The command "ICPLMQ (LOW _AT_SET), 5" on the second line sets the value of the Q register to the upper 1 byte of the address, the value of the lower 1 byte of the address "_AT_SET" to the lower 1 byte of the address, and increments the address. The 1-byte value stored in the address to be incremented is compared with the upper limit value "5". Update the byte value by incrementing it by 1. If the incremented value is 5 or more (if the carry flag is not set), the 1-byte value stored at the address to be incremented is updated to the upper limit value "5". The commands on the second line correspond to steps S1 to S3 in FIG. Thus, the 1-byte variable in the main RAM 500c can be incremented by 1 up to a predetermined number.

Here, the command "ICPLMQ (k), n" sets the value of the Q register as the upper 1 byte of the address, the value k as the lower 1 byte of the address, the 1-byte value stored at the target address, and the upper limit value As a result, if less than n, the 1-byte value stored at the target address is incremented by 1 and updated, and if n or more, the 1-byte value stored at the target address is the upper limit. It is a command to update to the value n. Such a command size is "4" and the execution cycle is "7".

The total command size of the commands of the RAM_INC module in FIG. 219 is the second line command "ICPLMQ (LOW_AT_SET), 5" 4 bytes=4 bytes, and the total execution cycle is the second line 7 cycles=7 cycles. Therefore, compared with the case of FIG. 216, the total command size is reduced by 6 bytes, and the total execution cycle is reduced by 6 cycles. With such a RAM_INC module, it is possible to further shorten commands, reduce processing load, and secure the capacity of the control area for performing game control processing.

Also, here, unlike the example in FIG. 216, the A register is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 216, if the A register was already used, it was necessary to stack and save the value of the A register. In this way, it becomes possible to effectively use resources.

Also, as can be understood by comparing FIG. 216 and FIG. 219, the command group occupying 7 lines (2nd to 8th lines) in FIG. It is possible to reduce the number of commands and reduce the design load.

<Command "LDINTQR">
The TABLESET module is a general-purpose module for table setting processing, that is, setting predetermined values (initial values) to variables in the main RAM 500c. Here, an example in which the TABLESET module is arranged at 0030H on the memory map will be described.

The main CPU 500a reads a program from the main ROM 500b, executes the read program, calls the TABLET module as a subroutine in arbitrary processing, and executes the TABLET module. The TABLESET module transfers a plurality of 1-byte values described in the program data of the main ROM 500b to an area holding a plurality of data handled as variables in the work area of the main RAM 500c. Thus, the values of multiple variables are set. Here, the number of data to be transferred is simply called the number of data.

FIG. 220 is a flow chart showing specific processing of the TABLESET module. Here, as arbitrary processing, error wait processing shown in step S2200-11 of FIG. 89 and step S2800-39 of FIG. will be described. Numerical values of step S in this figure are used only in the explanation of this figure. Also, in the description of the TABLESET module, the first register is the B register, the second register is the HL register, the register different from the first register and the second register is the A register, and the predetermined value is "1". be. It goes without saying that the predetermined value can be arbitrarily set.

As shown in FIG. 220(a), the main CPU 500a sets the start address of the 1-byte data group to be the transfer source in the HL register in arbitrary processing (S1). Then, the TABLESET module is called as a subroutine (S2).

As shown in FIG. 220(b), the main CPU 500a saves the BC register in the TABLESET module (S3) and prohibits interrupts (S4). Then, the main CPU 500a reads the 1-byte value stored at the address indicated by the HL register to the B register (S5). This 1-byte value indicates the number of data. Subsequently, the main CPU 500a adds "2" to the HL register to the address specified by the value stored in the address indicated by adding "1" to the HL register. 2 is added to the value of the HL register to set the next address to be transferred (S6). Subsequently, the main CPU 500a decrements the value of the B register (subtracts "1") and determines whether or not the result of the decrement is 0 (S7). Here, if the decremented result is not 0 (NO in S7), the processing from step S6 is repeated, and if the decremented result is 0 (YES in S7), an interrupt is permitted (S8), and the BC register (S9), terminates the TABLESET module, and returns to the routine one level above (S10).

221 and 222 are explanatory diagrams for explaining an example of commands for realizing the TABLESET module. Among them, FIG. 221(a) shows a command group for arbitrary processing to call the TBLSET module, FIG. 221(b) shows a command group for the TBLSET module, and FIG. 221(c) shows the program data of the main ROM 500b. 221(d) shows the arrangement of a 1-byte data group in the work area of the main RAM 500c. The flowchart shown in FIG. 220 is realized by the program shown in FIG. 221, for example.

The command "LD HL, T_ERR_RCV" on the first line in FIG. 221(a) sets the start address "T_ERR_RCV" of the 1-byte data group as the transfer source in the HL register. Such a command on the first line corresponds to step S1 in FIG. 220(a). Then, the command "RST TABLET" on the second line calls the TABLET module as a subroutine. The command on the second line corresponds to step S2 in FIG. 220(a).

The index "TABLSET:" on the first line in FIG. 221(b) indicates the start address of the TBLSET module. The value of the BC register is saved in the stack area by the command "PUSH BC" on the second line. The command on the second line corresponds to step S3 in FIG. 220(b). Interrupts are disabled by the command "DI" on the third line. The command on the third line corresponds to step S4 in FIG. 220(b).

The 1-byte value stored at the address indicated by the HL register is read to the B register by the command "LD B, (HL)" on the fourth line in FIG. 221(b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 221(a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" on the second line in FIG. 221(c) is read out to the B register as the number of data (transfer repetition number). Note that "T_ERR_RCV_" is the address next to the last address of the transfer source 1-byte data group, and T_ERR_RCV is the start address of the transfer source 1-byte data group. 1-byte value) is the total number of bytes of the 1-byte value, and the number of data is derived by dividing that value by 2, which is the number of combinations of addresses and values. In the example of FIG. 221(c), the number of data is 9/2=4. The command on the fourth line in FIG. 221(b) corresponds to step S5 in FIG. 220(b).

The index "TABLSET10:" on the fifth line in FIG. 221(b) indicates the start address of the repeated processing. Specified by the value stored at the address indicated by the HL register plus "1" by the command "INLD AC, (HL)" on the 6th line and the command "LDQ (C), A" on the 7th line. The value stored at the address indicated by the value obtained by adding "2" to the HL register is stored in the address to be transferred, and "2" is added to the value of the HL register to set the next transfer address. The commands on the 6th and 7th lines correspond to step S6 in FIG. 220(b).

For example, if the HL register has the value of the address "T_ERR_RCV", the lower 1-byte value of the 2-byte variable "_ERR_NUM" in the third line of FIG. A value of "0" in the third row is stored in the A register.

The command "LDQ (C), A" on the 7th line in FIG. , A is a command to store the value of the A register.

For example, the value of the C register, that is, the value of the lower 1 byte of "_ERR_NUM" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "0" is stored at that address.

Here, in FIGS. 221(c) and 221(d), the variable "_ERR_NUM" indicates an error number, the variable "_CRE_TMR" indicates a credit button detection timer, and the variable "_CRE_FLG" indicates a credit button detection flag. , and the variable “_SNS_OLD” indicates the previous medal passing sensor bit state. Note that the arrangement of variables shown in FIG. 221(d) does not have to be continuous as shown, and may be separated.

Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ TABLESET10" on the eighth line of FIG. , if the result of decrementing is 0, the process is shifted to the command following the current command. Here, since the number of data is "4", the value of the B register becomes 0 when the processing from "TABLSET10" is repeated four times. The eighth line command corresponds to step S7 in FIG. 220(b).

The interrupt is enabled by the command "EI" on the ninth line of FIG. 221(b). The command on the ninth line corresponds to step S8 in FIG. 220(b). The data saved in the stack area by the command "POP BC" on the 10th line is restored to the BC register. The command on the tenth line corresponds to step S9 in FIG. 220(b). Then, the command "RET" on the 11th line returns to the routine one level above. The command on the 11th line corresponds to step S10 in FIG. 220(b).

Thus, as shown in FIG. 222, a plurality of 1-byte values (55H, 77H, 66H, 22H) described in the program data of the main ROM 500b are converted to variables ("_ERR_NUM", "_CRE_TMR", "_CRE_FLG", "_SNS_OLD").

The TABLESET module is called as a subroutine from multiple modules. For example, the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 selectively shifts according to the game state and the effect state, and executes the present precursor process (AT state=“3”). and the EXE_SET module for executing the execution flag setting process shown in step S2400-11 in FIG. , and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ), and the EXE_SET module for executing the execution flag setting process shown in step S2400-11 in FIG. ”), and the EXE_SET module for executing the execution flag setting process shown in step S2400-11 in FIG. 7”), the RANKSET module for executing the set value switching process shown in step S2020 in FIG. 85, the FGSETUP module for executing the symbol code setting process shown in step S2400 in FIG. 91, and step S2900 in FIG. is called from the GAMESET module that executes the game transition process shown in , the JCGMSET module that executes the process during operation of the accessory shown in step S2900-3 of FIG. 96, and the like.

In this way, the total command size of the commands of the TABLESET module shown in FIG. B, (HL)" 1 byte + 6th line command "INLD AC, (HL)" 2 bytes + 7th line command "LDQ (C), A" 2 bytes + 8th line command "DJNZ TABLESET10" 2 bytes + 9 1 byte of the command "EI" on the 10th line + 1 byte of the command "POP BC" on the 10th line + 1 byte of the command "RET" on the 11th line = 12 bytes, and the total execution cycle is 3 cycles on the 2nd line + 1 cycle on the 3rd line. + 4th row 2 cycles + 6th row 4 cycles + 7th row 3 cycles + 8th row 3 cycles (or 2 cycles) + 9th row 1 cycle + 10th row 3 cycles + 11th row 3 cycles = 23 cycles (or 22 cycles) . The number of cycles in parentheses indicates the number of execution cycles when the command "DJNZ TABLESET10" does not move. By providing such a TABLESET module, it is possible to provide a command "RST TABLESET" with a command size of 1 byte without performing table setting processing in each of the modules described above. It becomes possible to secure the capacity of the control area for performing the processing.

FIG. 223 is an explanatory diagram for explaining another example of commands for realizing the TABLESET module. Here, the command group of the TBLSET module in FIG. 221(b) is replaced with the command group of the TBLSET module in FIG. 223(a) and 223(c). , is used as it is as FIG. 223(d). Here, as shown in FIGS. 223(a), 223(c), and 223(d), the processes substantially equivalent to those in FIGS. 221(a), 221(c), and 221(d) are The explanation is omitted, and only the different processing in FIG. 223(b) is explained.

The index "TABLSET:" on the first line in FIG. 223(b) indicates the top address of the TBLSET module. The value of the BC register is saved in the stack area by the command "PUSH BC" on the second line. The command on the second line corresponds to step S3 in FIG. 220(b). Interrupts are disabled by the command "DI" on the third line. The command on the third line corresponds to step S4 in FIG. 220(b).

A 1-byte value stored at the address indicated by the HL register is read to the B register by the command "LD B, (HL)" on the fourth line in FIG. 223(b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 223(a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV)/2" on the second line in FIG. 223(c) is read to the B register as the number of data (number of repetitions of transfer). In the example of FIG. 223(c), the number of data is four. The command on the fourth line in FIG. 223(b) corresponds to step S5 in FIG. 220(b).

The value of the HL register is incremented by one by the command "INC HL" on the fifth line in FIG. 223(b). The value stored at the address indicated by adding "1" to the address specified by the value stored at the address indicated by the HL register by the command "LDINTQR (HL)" on the sixth line. is transferred, "2" is added to the value of the HL register to set the next address to be transferred, the value of the B register is decremented (subtracted by "1"), and the processing continues until the decremented result becomes 0. Repeated. The commands on the fifth and sixth lines correspond to steps S6 and S7 in FIG. 220(b).

Here, the command "LDINTQR (HL)" uses the value of the Q register as the upper 1 byte of the address, the value stored at the address indicated by the HL register as the lower 1 byte of the address, and stores the value in the HL register at that address. Transfers the value stored in the address indicated by the value incremented by "1", adds "2" to the value of the HL register to update the value of the HL register, and decrements the value of the B register (subtracts "1"). ) and the value is repeatedly transferred until the decremented result becomes 0. Such a command has a command size of "2" and an execution cycle of "5".

For example, if the HL register has the value of the address "T_ERR_RCV", then the value of the Q register is the upper 1 byte of the address, and the lower 1 byte of "_ERR_NUM" in the third row of FIG. The value of "0" in the third row of FIG. 223(c) is transferred to the address, "2" is added to the value of the HL register, and the value of the B register is decremented ("1"). subtraction), and the transfer is repeated until the decremented result becomes 0, that is, four times.

Subsequently, the interrupt is permitted by the command "EI" on line 7 of FIG. 223(b). The command on the seventh line corresponds to step S8 in FIG. 220(b). The data saved in the stack area by the command "POP BC" on the eighth line is restored to the BC register. The eighth line command corresponds to step S9 in FIG. 220(b). Then, the command "RET" on the ninth line returns to the routine one level above. The command on the ninth line corresponds to step S10 in FIG. 220(b).

The total command size of the commands of the TABLESET module in FIG. 223(b) is the command "PUSH BC" 1 byte on the 2nd line + the command "DI" 1 byte on the 3rd line + the command "LD B, (HL)" on the 4th line. 1 byte + 5th line command "INC HL" 1 byte + 6th line command "LDINTQR (HL)" 2 bytes + 7th line command "EI" 1 byte + 8th line command "POP BC" 1 byte + 9th line command "RET" 1 byte = 9 bytes, and the total execution cycle is: 2nd line 3rd cycle + 3rd line 1st cycle + 4th line 2nd cycle + 5th line 1st cycle + 6th line 5th cycle + 7th line 1st cycle + 8th line 3 cycles+3 cycles of the 9th row=19 cycles. Therefore, compared with the case of FIG. 221(b), the total command size is reduced by 3 bytes, and the total execution cycle is also reduced by at least 4 cycles. In particular, in the example of FIG. 221(b), if the value of the B register in the command "DJNZ TABLESET10" is 2 or more, then 10 cycles (6th line 4 cycles + 7th line 3 cycles + 8th line 3 cycles) Since the total execution cycle increases by the amount multiplied by , the amount of reduction in the total execution cycle in FIG. 221(b) also increases. With such a TABLESET module, it is possible to further shorten commands, reduce the processing load, and secure the capacity of the control area for performing game control processing.

Also, unlike the example in FIG. 221, the A and C registers are not used here. Therefore, the value of the A register and the value of the C register are not unintentionally updated. Also, in the example of FIG. 221, if the A and C registers were already used, it was necessary to stack and save the values of the A and C registers. No stack processing is required. In this way, it becomes possible to effectively use resources.

221(b) and FIG. 223(b), the command group occupying four lines (5th to 8th lines) in FIG. H.223(b) can be expressed in two lines (5th and 6th lines), which makes it possible to reduce the number of commands and the design load.

<DECWMQ>
FIG. 224 is a flow chart showing specific processing of the IPT_PC module. The IPT_PC module executes time monitoring processing that is read once every four times in step S3100-21 of the timer interrupt processing (see FIG. 98). Numerical values of step S in this figure are used only in the explanation of this figure.

The time monitoring process is a process of subtracting one by one from the timers (for example, one-game timer, etc.) set in various steps of FIGS. 82 to 98 .

As shown in FIG. 224(a), the main CPU 500a reads the address where the timer is stored to the HL register (S1), executes the WORDDEC module shown in FIG. The value of the indicated address is subtracted by 1 (S3). Then, the command "RET" terminates the WORDDEC module and returns to the IPT_PC module (S4).

FIG. 225 is an explanatory diagram for explaining an example of commands for realizing the IPT_PC module. The flowchart shown in FIG. 224 is realized by the program shown in FIG. 225, for example. In addition, in FIG. 225, as an example, the processing for subtracting the timer between one game will be described.

The index "IPT_PC:" on the first line in FIG. 225(a) indicates the start address of the IPT_PC module. Then, by the command "LDQ HL, (LOW_GAM_TMR)" on the second line in FIG. 225(a), the value of the Q register is read to the H register, and the value of the lower 1 byte of the address "_GAM_TMR" is read to the L register. The command on the second line corresponds to step S1 in FIG. 224(a).

Then, the WORDDEC module shown in FIG. 225(b) is called by the command "CALLF WORDDEC" on the third line of FIG. 225(a). The command on the second line corresponds to step S2 in FIG. 224(a).

The index "WORDDEC:" on the first line in FIG. 225(b) indicates the start address of the WORDDEC module. Then, by the command "DCPWLD (HL), 0" on the second line in FIG. 225(b), the data is stored at the address indicated by the HL register (more precisely, the address indicated by the HL register and the next address). The 2-byte length value (timer between one game) is read, and 1 is subtracted (updated) from the read value. If the carry flag is set to 1 by the subtraction, that is, if the read value is 0 (predetermined value), then the address indicated in the HL register (more precisely, the address indicated in the HL register A fixed value "0 (specific value)" is stored in the indicated address and the next address). On the other hand, if the carry flag is not set to 1, that is, if the read value is 1 or more, the subtracted value is stored at the address indicated in the HL register (more precisely, the address indicated in the HL register). stored in the following address). The command on the second line corresponds to step S3 in FIG. 224(b).

Then, the command "RET" on the third line in FIG. 225(b) terminates the WORDDEC module and returns to the IPT_PC module. The command on the third line corresponds to step S4 in FIG. 224(b). In this way, it is possible to decrement by 1 each time the processing is performed until the 2-byte length value (timer between one game) stored at the address indicated by the HL register becomes zero.

Here, the command group of FIGS. 225(a) and 225(b) can be changed as shown in FIG. 225(c). 225(a) and 225(b) will be omitted, and only the different processing in FIG. 225(c) will be described.

The command "DECWMQ (LOW_GAM_TMR)" on the second line in FIG. The value stored at that address is read. Then, 1 is subtracted (decremented) from the read value, and if the carry flag is set to 1 by the subtraction, that is, if the read value is 0, a fixed value " 0” is stored. On the other hand, if the carry flag is not set to 1, that is, if the read value is 1 or more, the subtracted value is stored at that address.

Here, the total command size of the command group shown in FIGS. 225(a) and 225(b) is the command "LDQ A, (LOW_GAM_TMR)" on the second line of FIG. 225(a) 2 bytes+FIG. (a) 3rd line command "CALLF WORDDEC" 2 bytes + 2nd line command "DCPWLD (HL), 0" 4 bytes in Fig. 225(b) + 3rd line command " RET" 1 byte = 9 bytes, and the total execution cycle is: 2 cycles on the 2nd line in Fig. 225(a) + 4 cycles on the 3rd line in Fig. 225(a) + 9 cycles on the 2nd line in Fig. 225(b) + 3 cycles on the 3rd line in FIG. 225(b)=18 cycles.

On the other hand, the total command size of the command group shown in FIG. 225(c) is the command "DECWMQ (LOW_GAM_TMR)" on the second line, 3 bytes=3 bytes, and the total execution cycle is 8 cycles on the second line=8 cycles. becomes.

Therefore, by replacing the command group of FIGS. 225(a) and 225(b) with the command group of FIG. 225(c), the total command size is reduced by 6 bytes and the total execution cycle is also reduced by 10 cycles. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

225(a) and 225(c), the command group occupying two lines (2nd to 3rd lines) in FIG. H.225(c) can be expressed in one line (second line), which makes it possible to reduce the number of commands and the design load.

In addition, in the example of FIG. 225(c), the WORDDEC module can also be deleted, freeing up a valuable area for general-purpose modules and allowing other modules to be placed in that area. In this way, effective utilization of resources becomes possible.

<RIBIT>
FIG. 226 is a flow chart showing specific processing of the CMDPROC module. The CMDPROC module executes the subcommand transmission process (see step S3100-11 in FIG. 98). Numerical values of step S in this figure are used only in the explanation of this figure.

The main CPU 500a acquires the value of the interrupt wait monitor register, as shown in FIG. 226 (S1). Here, the interrupt waiting monitor register consists of 1 byte, and the power-off warning signal is input to the 6th bit. When the power supply voltage of the slot machine 400 falls below a predetermined value, a power-off notice signal is input, and the sixth bit of the interrupt wait monitor register becomes 1, otherwise it becomes 0.

The main CPU 500a refers to the 6th bit of the acquired interrupt wait monitor register to determine whether a power-off warning signal is input, that is, whether there is an external interrupt request (S2). If there is an external interrupt request (YES at S2), the CMDPROC module is terminated and the process returns to the routine one step above. It is transmitted to the sub control board 502 .

FIG. 227 is an explanatory diagram for explaining an example of commands for realizing the CMDPROC module. The flowchart shown in FIG. 226 is realized by the program shown in FIG. 227, for example.

The index "CMDPROC:" on the first line in FIG. 227(a) indicates the head address of the CMDPROC module. Then, the command "IN A, (@IRR____)" on the second line in FIG. 227(a) sets the value of the U register to the upper 1 byte of the address, and sets the fixed value indicating the lower 1 byte of the address of the interrupt wait monitor register. With "@IRR_____" as the lower 1 byte of the address, the value stored at that address is read into the A register. The command on the second line corresponds to step S1 in FIG.

Then, if the 6th bit of the value stored in the A register is not 0, that is, if it is 1, the command "RET ” to exit the CMDPROC module and return to the routine one level above. On the other hand, if the 6th bit of the value stored in the A register is 0, the process proceeds to the next command. Such a command on the third line corresponds to step S2 in FIG.

Here, the command group of FIG. 227(a) can be changed as shown in FIG. 227(b). 227(a) will be omitted here, and only the different processing in FIG. 227(b) will be described.

The command "RIBIT NZ, 6, (@IRR_____)" on the second line in FIG. 227(b) sets the value of the U register to the upper 1 byte of the address and a fixed value indicating the lower 1 byte of the address of the interrupt wait monitor register. If "@IRR_____" is the lower 1 byte of the address, and if the 6th bit of the value stored at that address is not 0, the CMDPROC module is terminated and the command "RET" is executed. Back to routine. On the other hand, if the 6th bit of the value stored at that address is 0, the process proceeds to the next command.

Here, the total command size of the command group shown in FIG. 227(a) is the command "IN A, (@IRR_____)" 2 bytes on the second line + the command "RBIT NZ, 6, A" 2 bytes on the third line. = 4 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 5 (3) cycles = 8 (6) cycles. Note that the number of cycles in parentheses indicates the execution cycle when the command "RBIT NZ, 6, A" does not move.

On the other hand, the total command size of the command group shown in FIG. (5) cycles=7(5) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RIBIT NZ, 6, (@IRR_____)" does not move.

Therefore, by replacing the command group of FIG. 227(a) with the command group of FIG. 227(b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 1 cycle. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Also, in the example of FIG. 227(b), the A register used in FIG. 227(a) is not used. Therefore, the value of the A register is not unintentionally updated. Also, in the example of FIG. 227(a), if the A register was already used, it was necessary to stack and save the value of the A register. unnecessary. In this way, it becomes possible to effectively use resources.

227(a) and 227(b), the command group occupying two lines (2nd to 3rd lines) in FIG. H.227(b) can be expressed in one line (second line), which makes it possible to reduce the number of commands and the design load.

<AND + OR>
FIG. 228 is a flow chart showing specific processing of the SET_PLS module. The SET_PLS module executes the excitation pattern update process read in the stepping motor control process (see step S3100-13 in FIG. 98). Numerical values of step S in this figure are used only in the explanation of this figure.

The main CPU 500a, as shown in FIG. 228, acquires the head address of the excitation pattern table storing the excitation pattern of the stepping motor 452 (S1). The main CPU 500a adds an offset value stored in advance in the A register to the obtained head address of the excitation pattern table, that is, offsets the address (S2).

Then, the main CPU 500a acquires the output image stored in the predetermined output port (S3), and masks the upper 4 bits of the acquired output image (S4). The output image obtained here has a 1-byte length, and the excitation pattern of the stepping motor 452 is indicated in the upper 4 bits. Therefore, here, the excitation pattern is cleared by masking the upper 4 bits of the output image.

Thereafter, the main CPU 500a synthesizes the excitation pattern by ORing the value indicated by the address offset in step S2 and the acquired output image (S5), and updates the synthesized excitation pattern as the output image. (S6), the SET_PLS module is finished, and the routine returns to the upper routine (S7).

FIG. 229 is an explanatory diagram for explaining an example of commands for realizing the SET_PLS module. The flowchart shown in FIG. 228 is realized by the program shown in FIG. 229, for example.

The index “SET_PLS:” on the first line in FIG. 229(a) indicates the start address of the SET_PLS module. Then, the address "T_PLS_PTN" of the excitation pattern table storing the excitation pattern of the stepping motor 452 is read to the HL register by the command "LD HL, T_PLS_PTN" on the second line of FIG. 229(a). Such a second line command corresponds to step S1 in FIG.

Then, the command "ADDWB HL, A" on the third line in FIG. 229(a) adds the value of the A register (offset value) to the value of the HL register to update the value of the HL register. Such a command on the third line corresponds to step S2 in FIG.

After that, the value (output image) stored at the address "IY+@OFS_OUT_PRT" of the output port is read to the A register by the command "LD A, (IY+@OFS_OUT_PRT)" on the fourth line in FIG. 229(a). Such a command on the fourth line corresponds to step S3 in FIG.

Subsequently, the command "AND A, 00001111B" on the fifth line in FIG. 229(a) computes the logical product of the value of the A register (output image) and the fixed value "00001111B" (first value). (The high-order 4 bits are masked), and the operation result is stored in the A register. This fifth line command corresponds to step S4 in FIG.

Then, the value of the A register (masked output image) and the value stored at the address shown in the HL register (excitation pattern , second value) is calculated, and the calculation result is stored in the A register. The sixth line command corresponds to step S5 in FIG.

After that, the value of the A register is stored at the address "IY+@OFS_OUT_PRT" of the output port by the command "LD (IY+@OFS_OUT_PRT), A" on the 7th line of FIG. 229(a). The command on the 7th line corresponds to step S6 in FIG. Then, the command "RET" on the eighth line in FIG. 229(a) terminates the SET_PLS module and returns to the routine one level above. The eighth line command corresponds to step S7 in FIG.

Here, the command group of FIG. 229(a) can be changed as shown in FIG. 229(b). 229(a) will be omitted here, and only the different processing in FIG. 229(b) will be described.

The CALADRS module shown in FIG. 229(c) is called by the command "RST CALADRS" on the third line in FIG. 229(b). The index "CALADRS:" on the first line in FIG. 229(c) indicates the start address of the CALADRS module. Then, the command "ADDWB HL, A" on the second line in FIG. 229(c) adds the value of the A register (offset value) to the value of the HL register, thereby updating the value of the HL register. Then, the 1-byte value stored at the address indicated by the HL register is read to the A register by the command "LD A, (HL)" on the third line. Then, the command "RET" on the fourth line in FIG. 229(c) terminates the CALADRS module and returns to the SET_PLS module.

After that, the value (output image) stored at the address "IY+@OFS_OUT_PRT" and the fixed value "00001111B" are logically combined with the command "AND (IY+@OFS_OUT_PRT), 00001111B" on the fourth line of FIG. 229(b). A product is calculated (the upper 4 bits are masked), and the calculation result is stored at the address "IY+@OFS_OUT_PRT".

Then, the value (masked output image) stored at the address "IY+@OFS_OUT_PRT" and the value of the A register ( excitation pattern) is calculated, and the calculation result is stored in the address "IY+@OFS_OUT_PRT".

Here, the total command size of the command group shown in FIG. "LD A, (IY+@OFS_OUT_PRT)" 3 bytes + 5th line command "AND A, 00001111B" 2 bytes + 6th line command "OR A, (HL)" 1 byte + 7th line command "LD (IY+@ OFS_OUT_PRT), A" 3 bytes + 8th line command "RET" 1 byte = 14 bytes. 2 cycles+4 cycles of the 7th row+3 cycles of the 8th row=19 cycles.

On the other hand, the total command size of the command group shown in FIG. IY+@OFS_OUT_PRT), 00001111B" 4 bytes + 5th line command "OR (IY+@OFS_OUT_PRT), A" 3 bytes + 6th line command "RET" 1 byte = 12 bytes. Cycle + 3rd row 4 cycles + 4th row 7 cycles + 5th row 6 cycles + 6th row 3 cycles = 23 cycles.

Therefore, by replacing the command group of FIG. 229(a) with the command group of FIG. 229(b), the total command size is reduced by 2 bytes. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process. Note that the CALADRS module, which is a general-purpose module, is read and executed by other modules, and is not newly added.

Also, as can be understood by comparing FIGS. 229(a) and 229(b), the command group in FIG. 229(b) can be reduced by two lines from the command group in FIG. It is possible to reduce the number of commands and lighten the design load.

<CPLBQ>
FIG. 230 is a flow chart showing specific processing of the OTM_ATK module. Numerical values of step S in this figure are used only in the explanation of this figure.

Here, as another example of the slot machine 400, a so-called chance zone effect state is provided. The chance zone performance state is a state in which it is easier to win an AT lottery than the normal performance state, and is shifted over a predetermined game. For example, the chance zone effect state is shifted over 8 games, and AT lottery is performed for each game. In another example of the slot machine 400, the result of the AT lottery in each game in the chance zone production state is stored in 1 bit (winning = 1, non-winning = 0), so that the results of all the AT lotteries are totaled. It is managed as 8-bit (1-byte length) correctness information.

The OTM_ATK module executes such a process of managing the result of the AT lottery. The OTM_ATK module is called and executed in the execution flag setting process shown in step S2400-11 in FIG. 91 only when the AT lottery is won in each game.

As shown in FIG. 230, the main CPU 500a acquires the number of games in the chance zone effect state (S1) and acquires the address of the number-of-games bit table (S2). Incidentally, in the number-of-games bit table, bit information corresponding to the first game to the eighth game in the chance zone effect state are successively arranged, as will be described in detail later. , the bit (1-bit information) corresponding to is 1 and the other bits are 0, which is 1-byte length data.

The main CPU 500a acquires bit information corresponding to the acquired number of games from the number-of-games bit table (S3), and acquires 1-byte win/loss information (1-byte information) indicating the result of the AT lottery (S4). ). Then, the main CPU 500a updates (combines) the win-or-fail information by ORing the acquired bit information and the win-win information (S5), and saves the updated win-win information (S6). The OTM_ATK module is terminated and the routine returns to the routine one level above (S7).

FIG. 231 is an explanatory diagram for explaining an example of commands for realizing the OTM_ATK module. The flowchart shown in FIG. 230 is realized by the program shown in FIG. 231, for example.

The index "OTM_ATK:" on the first line in FIG. 231(a) indicates the head address of the OTM_ATK module. Then, according to the command "LDQ A, (LOW_CZ_CNT)" on the second line of FIG. 1 byte, and the value (number of games played) stored at that address is read to the A register. This second line command corresponds to step S1 in FIG.

Then, the head address "T_XXX_XXX" of the number-of-games bit table shown in FIG. 231(b) is read to the HL register by the command "LD HL, T_XXX_XXX" on the third line of FIG. 231(a). Such a command on the third line corresponds to step S2 in FIG.

The index "T_XXX_XXX:" on the first line in FIG. 231(b) indicates the top address of the table "T_XXX_XXX". The value "00000001B" on the second line in FIG. 231(b) corresponds to the first game in the chance zone effect state, and only the 0 bit is 1 and the other bits are 0. Similarly, the values in the 3rd to 9th rows of FIG. Bit is 0.

The CALADRS module is called by the command "RST CALADRS" on the fourth line in FIG. 231(a). In the CALADRS module, the value of the A register (number of games played) is added to the value of the HL register, the value of the HL register is updated, and the value (number of games played) stored at the address indicated in the updated HL register is added. ) is read into the A register. The command on the fourth line corresponds to step S3 in FIG.

The command "LDQ B, (LOW_ATW_BIT)" on the fifth line of FIG. , and the value (validity information) stored at that address is read to the B register. This fifth line command corresponds to step S4 in FIG.

The command "OR A, B" on the 6th line in FIG. 231(a) computes the logical sum of the value of the A register (bit information corresponding to the number of games played) and the value of the B register (hit/fail information). Here, when the AT lottery is won in the game, the bit corresponding to the number of games is set to 1 in the win/fail information. The sixth line command corresponds to step S5 in FIG.

The command "LDQ (LOW_ATW_BIT), A" on the seventh line in FIG. , and the value of the A register (updated pass/fail information) is stored at that address. The command on the 7th line corresponds to step S6 in FIG.

Then, the command "RET" on the eighth line of FIG. 231(a) terminates the OTM_ATK module and returns to the routine one level above. The eighth line command corresponds to step S7 in FIG.

Here, the command group of FIG. 231(a) can be changed as shown in FIG. 231(c). 231(a) will be omitted here, and only the different processing in FIG. 231(c) will be described.

The command "CPLBQ A, (LOW_ATW_BIT)" on the third line in FIG. , and the bit corresponding to the value of the A register (the number of games played) of the value (win/fail information) stored at that address is inverted. Therefore, here, among the win/fail information, the bit corresponding to the game (the number of games) won in the AT lottery is inverted and becomes 1.

Here, the total command size of the command group shown in FIG. 231(a) is the command "LDQ A, (LOW_CZ_CNT)" on the second line 2 bytes + the command "LD HL, T_XXX_XXX" on the third line 3 bytes + 4 lines. 1st command "RST CALADRS" 1 byte + 5th line command "LDQ B, (LOW_ATW_BIT)" 3 bytes + 6th line command "OR A, B" 1 byte + 7th line command "LDQ (LOW_ATW_BIT), A" 2 bytes + 8th line command "RET" 1 byte = 13 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 3 cycles + 4th line 4 cycles + 5th line 4 cycles + 6th line 2 cycles + 7 3 cycles of row + 3 cycles of 8th row = 22 cycles.

On the other hand, the total command size of the command group shown in FIG. 231(c) is the second line command "LDQ A, (LOW_CZ_CNT)" 2 bytes + the third line command "CPLBQ A, (LOW _ATW_BIT)" 3 bytes. + 1 byte of the command "RET" on the 4th line = 6 bytes, and the total execution cycle is 3 cycles on the 2nd line + 6 cycles on the 3rd line + 3 cycles on the 4th line = 12 cycles.

Therefore, by replacing the command group of FIG. 231(a) with the command group of FIG. 231(c), the total command size is reduced by 7 bytes and the total execution cycle is also reduced by at least 10 cycles. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

231(a) and 231(c), the command group occupying 5 lines (3rd to 7th lines) in FIG. H.231(c) can be expressed in one line (the third line), which makes it possible to reduce the number of commands and the design load.

Further, by replacing with the command group of FIG. 231(c), the game number bit table becomes unnecessary, so that the data capacity for the game number bit table can be reduced.

<LDSB>
FIG. 232 is an explanatory diagram for explaining an example of commands for realizing the KRS_JDG module.

Here, as another example of the gaming machine 100, in a predetermined round game in the big win game, when the game ball enters the probability variable area (specific area) provided in the big win opening, the game state after the big win game Set to high probability game state. Then, when a predetermined number of games pass through the big winning opening in a predetermined round game in a big game in which a predetermined special pattern is determined, the probability variable area is opened and a game ball can enter the probability variable area. . Below, when 3 game balls enter the big winning opening in the first round game, and when 5 gaming balls enter the big winning opening in the 5th round game, the variable area is opened. An example will be given for explanation.

The KRS_JDG module executes processing for managing the release of such probability variable areas. It should be noted that the KRS_JDG module is called and executed in the big winning opening opening control process shown in FIG.

The index "KRS_JDG:" on the first line in FIG. 232(a) indicates the head address of the KRS_JDG module. Then, the command "LDQ A, (LOW R_ROU_CNT)" on the second line in FIG. 1 byte, and the value (the number of times of continuous operation of the special electric accessory, ie, the number of round games) stored in the address is read to the A register.

Then, the command "LD B, (HL)" on the third line in FIG. 232(a) reads the value of the address indicated by the value stored in the HL register to the B register. It should be noted that the address "D_KRS_JDG_2" of the probability variable area determination table shown in FIG. 232(b) is read in advance to the HL register.

The index "D_KRS_JDG_2:" on the first line in FIG. 232(b) indicates the start address of the table "D_KRS_JDG_2". The value "(@D_KRS_JDG_2-D_KRS_JDG2-1)/2" on the second line in FIG. It is a value obtained by dividing the value obtained by subtracting 1 by 2, and indicates the number of determination times (the number of round games in which the variable probability area is opened).

The value "@KRS_TGT_ROU_01" in the third row of FIG. 232(b) is a value (target round value, here, 1) indicating the first round game that opens the variable probability area, and 4 in FIG. 232(b). The row value "@KRS_JDG_01" is a value (open identification value, Here, it is 3). Similarly, the value "@KRS_TGT_ROU_03" in the fifth row of FIG. ), the value "@KRS_JDG_03" in the 6th row is a value (open The identification value, here 5).

Therefore, the determination count is read out to the B register by the command "LD B, (HL)" on the third line in FIG. 232(a).

The index "KRS_JDG_10:" on the fourth line in FIG. 232(a) indicates the address of the index "KRS_JDG_10". The value of the HL register is incremented by 1 by the command "INC HL" on the fifth line in FIG. 232(a). After that, the value of the A register and the value (target round value) stored at the address indicated by the value of the HL register are compared by the command "CP A, (HL)" on the sixth line of FIG. 232(a). If the value of the A register is the same as the value of the HL register, the zero flag is set to 1. If the value of the A register is different from the value of the HL register, the zero flag is not set to 0.

Subsequently, the value of the HL register is again incremented by 1 by the command "INC HL" on the seventh line in FIG. 232(a). After that, the value of the address indicated by the HL register (open identification value) is read to the C register by the command "LD C, (HL)" on the eighth line in FIG. 232(a).

Then, if the zero flag is set by the command "RET Z" on the ninth line of FIG. 232(a), the KRS_JDG module is ended and the module one level above is returned to.

If the zero flag is not set, the command "DJNZ KRS_JDG_10" on the 10th line in FIG. If the decremented result is 0 after moving to "KRS_JDG_10", the command "RET" on line 11 in FIG. 232(a) terminates the KRS_JDG module and returns to the upper module.

Here, in the gaming machine 100, the maximum number of round games is ten. Also, the number of balls entering the big winning hole for opening the probability variable area is set between 2 and 5 since the prescribed number for each round game is 10. That is, the target round value is a value of 10 or less and can be represented by 4 bits. Therefore, although the value "@KRS_TGT_ROU_01" and the value "@KRS_TGT_ROU_03" indicating the target round value are configured with a 1-byte length, they may actually be 4 bits.

Also, the open identification value is a value of 5 or less and can be represented by 3 bits. Therefore, although the value "@KRS_JDG_01" and the value "@KRS_JDG_03" indicating the release identification value are composed of 1-byte length, they may actually be 3 bits.

Therefore, an example in which two values, the target round value that can be represented by 4 bits and the open identification value that can be represented by 3 bits, are treated as one value (data) of 1-byte length will be described below.

FIG. 233 is an explanatory diagram for explaining another example of commands for realizing the KRS_JDG module. 232 will be omitted, and only the different processing in FIG. 233 will be described.

The value of the address shown in the HL register is read to the B register by the command "LD B, (HL)" on the third line in FIG. 233(a). It should be noted that the address "D_KRS_JDG_2" of the variable probability area determination table shown in FIG. 233(b) is read in advance to the HL register.

The value "@KRS_TGT_ROU_01*8+@KRS_JDG_01" in the third row of FIG. 233(b) is a value (target round value) indicating the first round game in which the high-order 5 bits open the probability variable area, and low-order 3 bits. is a value (open identification value) indicating how many game balls enter the big winning opening in the first round game to open the probability variable region to open the probability variable region. Similarly, the value "@KRS_TGT_ROU_03*8+@KRS_JDG_03" in the fourth row of FIG. The lower 3 bits is a value (opening identification value) indicating how many game balls enter the big winning opening in the second round game to open the probability variable area to open the probability variable area.

The command "LDSB 2, DE, (HL)" on the 6th line in FIG. The upper 5 bits of the value in the register are shifted 3 bits to the right and read out to the D register (other bits are set to 0). That is, the target round value and the release identification value are separated, the target round value is read to the D register, and the release identification value is read to the E register. Note that "2" in the command "LDSB 2, DE, (HL)" is a value indicating that 3 bits from 0 to 2 are read to the E register, and the higher bits ( 5 bits) is shifted and read out to the D register.

The command "CP A, D" on the 7th line in FIG. 233(a) compares the value of the A register and the value of the D register (target round value), and the value of the A register is the same as the value of the D register. If so, the zero flag is set and becomes 1, and if different from the target round value, the zero flag is not set and becomes 0.

Here, the total command size of the command group shown in FIG. 232(a) is the second line command "LDQ A, (LOW R_ROU_CNT)" 2 bytes + the third line command "LD B, (HL)" 1 byte. + 5th line command "INC HL" 1 byte + 6th line command "CP A, (HL)" 1 byte + 7th line command "INC HL" 1 byte + 8th line command "LD C, (HL)" 1 byte + 9th line command "RET Z" 1 byte + 10th line command "DJNZ KRS_JDG_10" 2 bytes + 11th line command "RET" 1 byte = 11 bytes, total execution cycle is 2nd line 3 cycles + 3 Row 2 cycle + 5th row 1 cycle + 6th row 2 cycle + 7th row 1 cycle + 8th row 1 cycle + 9th row 3 (1) cycle + 10th row 3 (2) cycle + 11th row 3 (1) cycle = 19 (14) Cycle. Also, the variable probability region determination table shown in FIG. 232(b) is 5 bytes. Note that the number of cycles in parentheses indicates the execution cycle when not moved by the command.

On the other hand, the total command size of the command group shown in FIG. 233(a) is the command "LDQ A, (LOW R_ROU_CNT)" on the second line 2 bytes + the command "LD B, (HL)" on the third line 1 byte + 5. Line command "INC HL" 1 byte + Line 6 command "LDSB 2, DE, (HL)" 2 bytes + Line 7 command "CP A, D" 1 byte + Line 8 command "RET Z" 1 Byte + 9th line command "DJNZ KRS_JDG_10" 2 bytes + 10th line command "RET" 1 byte = 11 bytes. 3rd cycle+7th row 1st cycle+8th row 3(1) cycle+9th row 3(2) cycle+10th row 3(1) cycle=19(14) cycles. Also, the variable probability region determination table shown in FIG. 233(b) is 3 bytes. Note that the number of cycles in parentheses indicates the execution cycle when not moved by the command.

Therefore, by replacing the command group of FIG. 232 (a) and the probability variable region determination table of FIG. 232 (b) with the command group of FIG. 233 (a) and the probability variable region determination table of FIG. 233 (b), the total size Reduced by 2 bytes. By such replacement, it is possible to shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Note that the command "LDSB" can be used to treat two values (information) of 8 bytes or less in total as one piece of data with a length of 1 byte, and can be applied to cases other than the above examples. can.

<Management of register bank and register group>
As described with reference to FIG. 101, register unit 716 of CPU core 700 is provided with two register banks (first register bank 726 and second register bank 728) that can be used exclusively by switching. Each of the first register bank 726 and the second register bank 728 is provided with two register groups (main register groups 726a and 728a and sub-register groups 726b and 728b) that can be accessed by switching exclusively. It includes 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY). Therefore, the register groups in which such a plurality of registers are common are two register banks (first register bank 726, second register bank 728) and two register groups (main register groups 726a, 728a, sub-register group 726b). , 728b) are present in four regions.

Such register groups are used exclusively between register banks and between register groups, respectively, and can store information independently, so that they are not affected by updates of registers in other areas. In other words, the main CPU 500a can update the contents of the registers of the currently targeted register bank and register group, but cannot access other non-targeted register banks and register groups.

In this way, by utilizing the fact that register groups are independent between register banks and between register groups, each register group can be classified according to its type (purpose, function, occasion, etc.). Consider adapting to each program. For example, in the memory space of this embodiment, as shown in the memory map of FIG. 102, the main ROM 500b and the main RAM 500c are allocated a used area and another area. As described above, the use area of the main ROM 500b stores programs and data for executing game control processing for controlling the progress of the game, and another area of the main ROM 500b stores data that does not affect the progress of the game. Instruction code and program data of the program that executes the process outside the game control are stored. As described above, the used area and the separate area are different in the content of the intended processing, so it is preferable to associate different register groups with each other.

Therefore, in this embodiment, the first register bank 726 corresponds to the register group used for executing the game control process in the use area, and the second register bank 728 corresponds to the register group used to execute the game control outside process in another area. Let In other words, the first register bank 726 is used as a group of registers used for execution of game control processing in the use area, and the second register bank 728 is used as a group of registers used for execution of non-game control processing in another area. . Then, the main CPU 500a refers to the program stored in 0000h to 1FFFh of the main ROM 500b, updates the register group of the first register bank 726, executes the game control process, and stores it in 2000h to 3FFFh of the main ROM 500b. By referring to the program being executed, the register bank is switched, the register group of the second register bank 728 is updated, and the processing outside the game control is executed. With such a configuration, independence and exclusivity between the used area and another area can be ensured in both the memory and the register.

Moreover, in this embodiment, the program executed in the game control process is divided into two. Here, for example, it is divided into main processing and timer interrupt processing. 22 to 25 (gaming machine 100) and 82 to 97 (slot machine 400). Timer interrupt processing (second processing) is, for example, shown in FIGS. 26 to 59 (gaming machine 100) and FIG. This is a process that is executed by temporarily interrupting the main process in response to a timer interrupt that occurs every predetermined time (eg, 4 ms, 1.49 ms). Although the main process has been described as the first process here, it is not limited to such a case, and any process for progressing the game can be applied. Also, here, as the second process, the timer interrupt process has been described, but it is not limited to such a case. etc.) can be applied as long as it is a process that is executed by a predetermined interrupt that occurs based on the establishment of the above.

In this embodiment, one of the two register groups 726a and 726b of the first register bank 726 corresponds to one of the main processing and timer interrupt processing, and the other of the main processing and timer interrupt processing corresponds to the second register group. The other of the two register groups 726a and 726b of one register bank 726 is made to correspond. In other words, one of the two register groups 726a and 726b of the first register bank 726 is used as a group of registers used for executing either main processing or timer interrupt processing, and two registers of the first register bank 726 are used. The other of the two register groups 726a and 726b is used as a register group used for executing the other of main processing and timer interrupt processing. An example in which the main register group 726a corresponds to the main process and the sub-register group 726b corresponds to the timer interrupt process will be described below in the first embodiment. 726b and the main register group 726a for timer interrupt processing will be described.

(First embodiment)
Here, an example in which the main register group 726a is associated with the main process and the sub-register group 726b is associated with the timer interrupt process will be described. Therefore, the main CPU 500a sequentially executes the main processing with reference to the main register group 726a. When a timer interrupt occurs, the main CPU 500a interrupts the main processing, temporarily switches from the main register group 726a to the sub-register group 726b, and switches to the sub-register group 726b. When the interrupt processing is executed and the timer interrupt processing ends, the sub-register group 726b is switched to the main register group 726a, and the main processing is restarted.

By the way, as described above, the Q register is used in this embodiment. The value written in the Q register is referenced as part of the address in any command. By using such a Q register, commands that refer to the Q register can be written, and the command size and the number of cycles can be reduced.

For example, if the command "LD A, (mn)" is written in the program for the load instruction "LD" for reading data from the memory space, the value stored at the 16-bit address mn can be read to the A register. Such a command has a command size of 3 bytes and a cycle count of 4 cycles. On the other hand, if the command "LDQ A, (n)" that refers to the Q register is written in the program, the value of the Q register will be the upper 1 byte of the address, the address n will be the lower 1 byte of the address, and the address n will be a 16-bit address. , the value stored at that address can be read into the A register. Such a command has a command size of 2 bytes and a cycle count of 3 cycles. Therefore, both the command size and the number of cycles can be reduced.

Such Q registers are managed for each register group as described above. That is, the Q register (first register) of the main register group (first register group) 726a and the Q' register (second register) of the sub-register group (second register group) 726b exist and are independent of each other. hold the value.

Also, when the power of the main CPU 500a including the register unit 716 is turned on, the Q register of the main register group 726a and the Q' register of the sub-register group 726b are set to initial values independently of each other. For example, when the power is turned on, the Q register of the main register group 726a stores the upper byte value of 1 (for example, F0h ), and the Q' register of the sub-register group 726b is set to the same "F0h" (first value) as the main RAM 500c, and the Q' register of the plurality of upper byte values (for example, F0h to F3) in the address of the storage area of the main RAM 500c. , 1 is set to "F1h", which is the same as the value of the upper byte of 1 (eg, F1h). This is based on the assumption that the memory areas to be referred to are divided between the processing using the main register group 726a and the processing using the sub-register group 726b.

However, in this embodiment, the main process using the main register group 726a and the timer interrupt process using the sub-register group 726b access variables associated with the same memory area. Therefore, if the Q register of the main register group 726a and the Q' register of the sub-register group 726b, which are referred to as the high-order bytes of the address, both hold the same value (for example, F0h), the command for adjusting the address is unnecessary, the command size can be reduced.

Therefore, in this embodiment, both the Q register of the main register group 726a and the Q' register of the sub-register group 726b are set to the same value (here, F0h). Note that the initial value of the Q register of the main register group 726a is F0h (first value), so there is no need to set another value. Therefore, here, only the Q' register of the sub-register group 726b is rewritten from F1h to F0h (second value). Note that the main CPU 500a needs to set a value in the Q' register before using a command that refers to the Q' register. Therefore, for example, it is conceivable to initialize the Q' register in the initialization processing of the main processing (for example, the CPU initialization processing in FIG. 82).

234 is a diagram depicting an example of a command for setting a value in the Q' register; FIG. Here, the main CPU 500a sets F0h in the Q' register in the initialization process of the main process. However, as described above, the main CPU 500a can update the contents of the Q register of the main register group 726a, which is the current target register group, but can access the Q' register of the sub-register group 726b, which is another register group. Can not do it. Therefore, as shown in FIG. 234, the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers (IX, IY) in sub-register group 726b. Switch to register (IX', IY'). Then, the command "LD Q, 0F0H" on the second line sets F0h in the Q' register, and the command "EX ALL" on the third line switches from the sub-register group 726b to the main register group 726a.

The total command size of the command example shown in FIG. 234 is: 1st line command "EX ALL" 2 bytes + 2nd line command "LD Q, 0F0H" 1 byte + 3rd line command "EX ALL" 2 bytes=5 Bytes, and the total execution cycle is 1st row 2 cycles + 2nd row 1 cycle + 3rd row 2 cycles = 5 cycles.

Here, an example in which the command "EX ALL" is used to switch between the Q register of the main register group 726a and the Q' register of the sub-register group 726b has been described. , for example, the command "EX Q, Q'" may be used. Since the command size of the command "EX Q, Q'" is 2 bytes and the cycle is 2 cycles, even if it is replaced with the command "EX ALL", the total command size and the total execution cycle will not change.

Command types that refer to such a Q' register are not limited to the command "LDQ" exemplified above, and there are many others, and they are repeatedly described in the program. Therefore, every time a command that refers to the Q' register is used, the effect of reducing the command size and the number of cycles can be obtained. As the frequency of use of commands that refer to the Q' register increases, the number of times the Q register is referenced also increases. Therefore, the value of the Q' register should be set reliably. Therefore, instead of setting the Q' register only once in the initialization processing of the main processing, or in addition, it is conceivable to repeatedly set the Q' register throughout the loop processing of the main processing. For example, the command group in FIG. 234 is executed in any one of FIGS. 88 to 97 (slot machine 400). By doing so, F0h can be set in the Q' register each time the loop processing of the main processing is executed. The value of the ' register can be reliably set to F0h, and the value of the Q' register can be stably maintained.

However, since the Q' register is used for timer interrupt processing, F0h is set in the Q' register before enabling the timer interrupt.

It is also conceivable to set the Q' register only once in the initialization processing of the main processing, or to repeatedly set the Q' register through timer interrupt processing instead of or in addition to repeatedly setting it in the loop processing of the main processing. be done. By doing this, every time a timer interrupt occurs, F0h can be set in the Q' register. can be reliably set to F0h, and the value of the Q' register can be maintained stably. An example of repeatedly setting the Q' register through timer interrupt processing will be described in detail below.

FIG. 235 is a diagram showing an example of commands for setting values in the Q' register. Here, first, normal timer interrupt processing will be described using FIG. 235(a) without referring to setting of the Q' register. Note that the main CPU 500a targets the main register group 726a until timer interrupt processing occurs (in the main processing). The index "TMR_IPT:" on the first line in FIG. 235(a) indicates the start address of the timer interrupt process. By the command "EX ALL" on the second line, from the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY) , 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers (IX', IY') in sub-register group 726b switch to Thus, the object becomes the sub-register group 726b. Then, after executing necessary processing in the timer interrupt processing, the sub-register group 726b is switched to the main register group 726a by the command "EX ALL" on the fifth line. Interrupts are enabled by the command "EI" on line 6. Here, even if the command "EI" is issued before returning from the subroutine to the main process, the interrupt is appropriately permitted. Then, the command "RETI" on the 7th line returns to the main processing.

The total command size of the commands shown in FIG. 235(a) is: 2 bytes of the command "EX ALL" on the 2nd line + 2 bytes of the command "EX ALL" on the 5th line + 1 byte of the command "EI" on the 6th line + 1 byte on the 7th line command "RETI" 2 bytes=7 bytes, and the total execution cycle is 2 cycles on the 2nd line+2 cycles on the 5th line+1 cycle on the 6th line+4 cycles on the 7th line=9 cycles.

Here, a command for setting the Q' register at any timing of the timer interrupt processing in FIG. 235(a) is described. When setting the Q' register in timer interrupt processing, only the command "LD Q, 0F0H" should be described after the command "EX ALL" as shown in FIG. 235(b). In the case of timer interrupt processing, the command "EX ALL" is executed again at the end of the processing (line 5) to switch to the main register group 726a.

Note that the position of the command "LD Q, 0F0H" must precede the command referring to the Q' register in the timer interrupt processing. Therefore, as shown in FIG. 235(b), it should be immediately after the command "EX ALL" on the second line. It is also possible to write a command other than a command referencing the Q' register after the command "EX ALL", and describe a command referencing the Q' register after describing the command "LD Q, 0F0H". .

The total command size of the commands shown in FIG. 235(b) is the command "EX ALL" 2 bytes on the 2nd line + the command "LD Q, 0F0H" 1 byte on the 3rd line + the command "EX ALL" 2 bytes on the 5th line. + 1 byte of the command "EI" on the 6th line + 2 bytes of the command "RETI" on the 7th line = 8 bytes. + 7th row 4 cycles = 10 cycles. As can be understood by comparing FIGS. 235(a) and 235(b), even if the setting of the Q' register is added, the total command size=1 byte and the total execution cycle=1 cycle increase.

As described with reference to FIG. 234, setting the Q' register in the initialization process of the main process requires a total command size of 5 bytes and a total execution cycle of 5 cycles. Likewise, when repeating through the loop processing of the main processing, total command size=5 bytes and total execution cycle=5 cycles are required. On the other hand, if the Q' register is set in the timer interrupt processing, the description of two commands "EX ALL" can be omitted, so the total command size=1 byte and the total execution cycle=1 cycle increase. Therefore, if the setting of the Q' register is executed only by the timer interrupt processing, at least the memory increase can be suppressed.

(Second embodiment)
Next, an example in which the sub-register group 726b is associated with main processing and the main register group 726a is associated with timer interrupt processing will be described. Therefore, the main CPU 500a first switches from the main register group 726a to the sub-register group 726b, executes main processing with reference to the sub-register group 726b, and interrupts the main processing when a timer interrupt occurs. The sub-register group 726b is switched to the main register group 726a to execute the timer interrupt processing, and when the timer interrupt processing ends, the main register group 726a is switched to the sub-register group 726b to restart the main processing.

Again, since the initial value of the Q register of the main register group 726a is F0h, there is no need to set another value, and only the Q' register of the sub-register group 726b is rewritten to F0h. Note that, as mentioned above, it must be set before any command that references the Q' register is used. Therefore, for example, it is conceivable to initialize the Q' register in the initialization processing of the main processing (for example, the CPU initialization processing in FIG. 82).

FIG. 236 is a diagram showing an example of a command for setting a value in the Q' register. Here, the main CPU 500a sets F0h in the Q' register in the initialization process of the main process. However, as described above, the main CPU 500a can update the contents of the Q register of the main register group 726a, which is the current target register group, but can access the Q' register of the sub-register group 726b, which is another register group. Can not do it. Therefore, as in FIG. 234, as in FIG. 236, the 8-bit registers (Q, A, F, B, C, D, E, H, L ) and 16-bit registers (IX, IY) to 8-bit registers (Q', A', F', B', C', D', E', H', L') in sub-register group 726b. and 16-bit registers (IX', IY').

Then, F0h is set in the Q' register by the command "LD Q, 0F0H" on the second line. After that, the sub-register group 726b is referred to and the main processing is performed.

The total command size of the commands shown in FIG. 236 is 2 bytes of the command "EX ALL" on the 1st line + 1 byte of the command "LD Q, 0F0H" on the 2nd line=3 bytes, and the total execution cycle is 2 bytes on the 1st line. Cycle+2nd row 1 cycle=3 cycles.

As described with reference to FIG. 234, after the main register group 726a is associated with the main process and the sub-register group 726b is associated with the timer interrupt process, the Q' register is set in the initialization process of the main process. , total command size=5 bytes and total execution cycle=5 cycles are required. Similarly, when setting the Q' register repeatedly through the loop processing of the main processing, the total command size=5 bytes and the total execution cycle=5 cycles are required. On the other hand, when the sub-register group 726b is associated with the main process, the main register group 726a is associated with the timer interrupt process, and the Q' register is set in the initialization process of the main process, one command "EX ALL" is executed. Since the description of minutes can be omitted, the increase in total command size=3 bytes and total execution cycle=3 cycles can be suppressed.

Also, as described above, the Q' register is used frequently, so the value of the Q' register should be set reliably. Therefore, instead of setting the Q' register only once in the initialization processing of the main processing, or in addition, it is conceivable to repeatedly set the Q' register throughout the loop processing of the main processing. For example, only the command "EX ALL" on the first line of the command group in FIG. , 88 to 97 (slot machine 400). By doing this, F0h can be set in the Q' register each time according to the loop processing of the main processing. The value of the ' register can be reliably set to F0h, and the value of the Q' register can be stably maintained.

However, since a command that refers to the Q' register is used in the main processing, F0h is set in the Q' register before using the command that refers to the Q' register.

It is also conceivable to set the Q' register only once in the initialization processing of the main processing, or to repeatedly set the Q' register through timer interrupt processing instead of or in addition to repeatedly setting it in the loop processing of the main processing. be done. By doing this, every time a timer interrupt occurs, F0h can be set in the Q' register. can be reliably set to F0h, and the value of the Q' register can be maintained stably.

FIG. 237 is a diagram showing an example of commands for setting values in the Q' register. Here, the Q' register is set in timer interrupt processing. Note that the main CPU 500a targets the sub-register group 726b until timer interrupt processing occurs (in the main processing). Specifically, the index "TMR_IPT:" on the first line in FIG. 237 indicates the start address of the timer interrupt process. F0h is set in the Q' register by the command "LD Q, 0F0H" on the second line. Then, in order to save the values of the registers used in the main process, the 8-bit registers (Q', A', F', B', C ', D', E', H', L') and 16-bit registers (IX', IY') to the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY). Thus, the object becomes the main register group 726a. Subsequently, after executing necessary processing in the timer interrupt processing, the main register group 726a is switched to the sub-register group 726b by the command "EX ALL" on the fifth line. Interrupts are enabled by the command "EI" on line 6. Here, even if the command "EI" is issued before returning from the subroutine to the main process, the interrupt is appropriately permitted. Then, the command "RETI" on the 7th line returns to the main processing.

The total command size of the commands shown in FIG. command "EI" 1 byte + command "RETI" 2 bytes on the 7th line = 8 bytes. 4 cycles=10 cycles.

The command "LD Q, 0F0H" must be placed before the command "EX ALL" is executed in the timer interrupt processing. Therefore, it should be immediately before the command "EX ALL" on the third line.

Here, the sub-register group 726b is associated with the main process, the main register group 726a is associated with the timer interrupt process, and the Q' register is set only once in the initialization process of the main process. or through timer interrupt processing. In either case, the command " EX ALL" can be omitted, so if the Q' register becomes the initial value F1h while keeping the total command size = 3 bytes and the total execution cycle = 3 cycles increase, Also, the value of the Q' register can be reliably set to F0h, and the value of the Q' register can be stably maintained.

<Switching register groups>
By the way, if a timer interrupt occurs during execution of the main process, the timer interrupt process continues to use the register regardless of what the value of the register is at the time of the interrupt. Therefore, when a timer interrupt occurs, it is necessary to separately hold the contents of the register at the interrupt timing. For example, in order to smoothly resume the main processing when returning to the main processing from the timer interrupt processing, the contents of the registers at the interrupt timing must be saved in the stack area of the main RAM 500c using a save command. However, the number of save commands increases according to the number of registers to be saved, and not only the command size but also the number of cycles increases.

In this embodiment, as described above, the 8-bit registers (Q, A, F, B, C, D, E, H, L) and 16-bit registers in the main register group 726a are activated by the command "EX ALL". (IX, IY) and 8-bit registers (Q', A', F', B', C', D', E', H', L') and 16-bit registers ( IX', IY'). With such a command, when switching between main processing and timer interrupt processing, the target register group can be saved at once, and other saved register groups can be restored at once. Such a command "EX ALL" has a command size of 2 bytes and requires only 2 cycles.

In addition, the first register bank 726 and the second register bank 728 are switched in register bank units including the main register group 726a and the sub-register group 726b by the command "CALLEX mn" and the command "RETEX". With such a command, the target register bank can be saved at once, and other saved register banks can be restored at once. If the address mn is limited to 2000h to 20FFh, the command size of the command "CALLEX mn" can be suppressed to 2 bytes, and the number of cycles required is only 4 cycles. The command "RETEX" has a command size of 2 bytes and requires only 5 cycles. Hereinafter, such a switching command will be described by applying it to the first embodiment and the second embodiment.

FIG. 238 is a diagram for explaining transition of register banks and register groups. As described above, in the example (first embodiment) in which the main register group 726a corresponds to the main process and the sub-register group 726b corresponds to the timer interrupt process, the main CPU 500a refers to the main register group 726a. The main processing is executed sequentially, and when a timer interrupt occurs, the main processing is interrupted, and the command "EX ALL" is used to temporarily switch from the main register group 726a to the sub-register group 726b (1), and the timer interrupt processing is executed. When the timer interrupt processing is completed, the sub-register group 726b is switched to the main register group 726a by the command "EX ALL" (2), and the main processing is restarted. In addition, the main CPU 500a switches from the first register bank 726 to the second register bank 728 by the command "CALLEX mn" at a predetermined timing in the game control process (3), executes the process outside the game control, and executes the game control process. When the outside process is completed, the second register bank 728 is switched to the first register bank 726 by the command "RETEX" (4), and the game control process is resumed.

In the example (second embodiment) in which the sub-register group 726b is associated with the main process and the main register group 726a is associated with the timer interrupt process, the main CPU 500a first executes the command "EX ALL" to set the main register Switch (1) from the group 726a to the group of sub-registers 726b, refer to the group of sub-registers 726b to execute the main processing, interrupt the main processing when a timer interrupt occurs, and temporarily execute the command "EX ALL". The sub-register group 726b is switched to the main register group 726a (2), timer interrupt processing is executed, and when the timer interrupt processing ends, the main register group 726a is switched to the sub-register group 726b by the command "EX ALL" ( 1) Resume the main process. In addition, the main CPU 500a switches from the first register bank 726 to the second register bank 728 by the command "CALLEX mn" at a predetermined timing in the game control process (3), executes the process outside the game control, and executes the game control process. When the outside process is completed, the second register bank 728 is switched to the first register bank 726 by the command "RETEX" (4), and the game control process is restarted.

Thus, with respect to the two register banks, the first register bank 726 corresponds to the used area, the second register bank 728 corresponds to another area, and the main register group 726a and sub-register group 726b of the first register bank 726 By making one of them correspond to main processing and the other to timer interrupt processing, the independence and exclusivity of each area can be ensured. In addition to these switching, by using a switching command to switch at least the entire register group integrally, it is possible to reduce the command size and the number of cycles while ensuring the independence and exclusivity of each area. . Here, as described with reference to FIG. 238, one of the main register group 726a and the sub-register group 726b of the first register bank 726 is associated with main processing, the other is associated with timer interrupt processing, and the second One or both of the main register group 728a and sub-register group 728b of the register bank 728 have been explained with an example corresponding to the game control outside process, for example, the main process, the timer interrupt process, the register corresponding to the game control outside process Banks and register groups can be set arbitrarily. For example, one of the main register group 728a and the sub-register group 728b of the second register bank 728 corresponds to main processing, the other corresponds to timer interrupt processing, and the main register group 726a and the sub-register group 726b of the first register bank 726 correspond to the main processing. One or both of the corresponding to the processing outside the game control, the main register group 726a of the first register bank 726 to correspond to the main processing, the main register group 728a of the second register bank 728 to correspond to the timer interrupt processing, One or both of the sub-register group 726b of the first register bank 726 and the sub-register group 728b of the second register bank 728 may be made to correspond to non-game control processing.

Next, a case where the main CPU 500a is powered off will be described. When the main CPU 500a is powered off while executing the main process, the main CPU 500a restores the register group of the register bank corresponding to the main process (the main register group 726a or the sub-register group 726b of the first register bank 726) to the command It saves to the stack area of the main RAM 500c through "PUSH" (for example, command "PUSH ALL") or the like, and then, for example, performs the save processing at power failure shown in FIG.

Here, the register group (main register group 726a or sub-register group 726b) corresponding to the main process is saved, but the saving of the register group corresponding to the timer interrupt process and the non-game control process is omitted. Necessary information is set in a group of registers corresponding to such timer interrupt processing after the timer interrupt processing is started. , when the timer interrupt processing ends, the contents of the register become unnecessary. Similarly, in the register group corresponding to the game control outside process, after the game control outside process is started, the necessary information is set, that is, without taking over the contents of the register from the game control process, outside the game control It is referenced only within the process, and when the process outside the game control ends, the contents of the register become unnecessary. Therefore, there is no problem even if the register group corresponding to the timer interrupt process and the process outside the game control is not saved.

In addition, when the power is turned off during timer interrupt processing or non-game control processing, not during main processing, processing is performed as follows. Timer interrupt processing has priority over interrupts due to power failure. That is, even if a power-off interrupt occurs during timer interrupt processing, the save processing at power-off is not executed immediately, and is executed only after the timer interrupt processing ends. In other words, the timer interrupt process is completed at the timing when the power-off save process starts. As described above, the timer interrupt processing is referenced only within the timer interrupt processing, and when the timer interrupt processing ends, the contents of the register become unnecessary. Therefore, even if the power is turned off during timer interrupt processing, there is no need to save the contents of the registers related to timer interrupt processing at the timing when the power-off save processing is started. Similarly, non-game control processing has priority over interrupts due to power off. That is, even if a power-off interrupt occurs during the game-control outside process, the power-off saving process is not immediately executed, and is executed only after the game-control outside process is completed. In other words, the timer interrupt process is completed at the timing when the power-off save process starts. It should be noted that, as described above, the process outside the game control is referred to only within the process outside the game control, and when the process outside the game control ends, the contents of the register become unnecessary. Therefore, even if the power is turned off during the process outside the game control, there is no need to save the contents of the register related to the process outside the game control at the timing when the save process at the time of power loss starts, so there is no problem.

Note that information in the register bank and the register group at the time of power-off is erased by power-off. When the power is restored after being turned off, the first register bank 726 and its main register group 726a, which are initial values, are set in the register bank and register group. Therefore, the processing that is executed first when the power is restored is the main processing, and the first register bank 726 and its main register group 726a correspond to the main processing. Thus, after the power is restored, the main processing is started. Here, since the first register bank 726 and its main register group 726a are saved when the power is turned off, the main processing can be performed stably and reliably.

In the embodiment described above, the first register group is the main register group, the first register is the Q register, the first value is F0h, the second register group is the sub-register group, and the second register is Q' Although the example has been described in which the registers are used and the second value is F0h, the present invention is not limited to such a case. F1h, the second register group is the main register group, the second register is the Q register, and the second value is F1h. In such a configuration, F1h is rewritten in the Q register of the main register group. Further, in the above-described embodiment, an example in which the first register bank is the first register bank 726 and the second register bank is the second register bank 728 has been described. The second register bank may be the second register bank 728 and the second register bank may be the first register bank 726 .

<Register access method>
By the way, in a conventional microprocessor, an address space (memory space) to which the main ROM 500b and the main RAM 500c are allocated, and an address space (I/O space) to which the input/output unit 704 (device corresponding to the input/output unit 704) is allocated. ) and were independently managed. Here, the memory space to which the main ROM 500b and the main RAM 500c are allocated may be called a memory map, and the I/O space to which the input/output unit 704 is allocated may be called an I/O map.

Conventional microprocessors have had to access memory space and I/O space using dedicated instructions. For example, when a conventional microprocessor uses instructions dedicated to the memory space of the main ROM 500b and main RAM 500c, access to the main ROM 500b and main RAM 500c becomes possible by enabling the memory request (MREQ) terminal. . Also, when a conventional microprocessor uses an instruction dedicated to the I/O space of the input/output unit 704, the input/output unit 704 can be accessed by enabling the I/O request (IORQ) terminal. becomes. Therefore, conventional microprocessors have had to change the instructions to be used depending on whether the object to be accessed is the main ROM 500 b or main RAM 500 c or the input/output unit 704 . Here, an access method provided for a conventional microprocessor to access the input/output unit 704 (device) is called an I/O mapped I/O method. The main CPU 500a can read information from the input/output unit 704 to the register and write information from the register to the input/output unit 704 by commands based on the I/O mapped I/O method.

However, as described above, in this embodiment, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 500b and the main RAM 500c, and the input/output unit 704 is assigned to FE00h to FFFFh of the memory space. Therefore, there is no concept of I/O space, and the main CPU 500a can access the input/output units 704 assigned to FE00h to FFFFh in the memory space by using instructions dedicated to the memory space. Here, an access system provided for the main CPU (processor) 500a to access the main ROM (storage means) 500b and the main RAM (storage means) 500c is called a memory mapped I/O system. The main CPU 500a can read information from the input/output unit 704 to the register and write information from the register to the input/output unit 704 by commands based on the memory-mapped I/O method.

Thus, in this embodiment, the main CPU 500a accesses the input/output unit 704 using the memory-mapped I/O method. On the other hand, from the viewpoint of general versatility, for example, the program of the conventional microprocessor can be used as it is, access by the I/O mapped I/O method is also possible in this embodiment. Therefore, in addition to the memory-mapped I/O method, the main CPU 500a can treat part of the memory space as an I/O space and access the input/output unit 704 by the I/O-mapped I/O method. . Although it was possible to access the input/output unit 704 by the memory-mapped I/O method even in a conventional microprocessor, it is possible to access the input/output unit 704 by using the I/O-mapped I/O method or by using the memory-mapped I/O method. If the memory-mapped I/O method is selected, the I/O-mapped I/O method cannot be used.

FIG. 239 is an explanatory diagram for explaining a usage mode of an access method. The memory-mapped I/O method has the advantage of being able to use a large number of commands (instructions) prepared for accessing the main ROM 500b and main RAM 500c, such as LD instructions and LDIR instructions. On the other hand, the memory-mapped I/O method has a drawback that the command size becomes larger than that of the I/O-mapped I/O method when simply reading from and writing to the input/output unit 704 . On the other hand, the I/O mapped I/O method has the advantage that the command size can be smaller than the memory mapped I/O method when simply reading from and writing to the input/output unit 704 . On the other hand, the I/O mapped I/O method has the drawback that only limited commands (instructions) prepared for accessing the input/output unit 704, such as IN instructions and OUT instructions, can be used.

In a program, since simple reading and writing of the input/output unit 704 are common, it is possible to reduce the command size by using the I/O mapped I/O method instead of the memory mapped I/O method. . For example, when reading a value stored at a predetermined address in the input/output unit 704 to the A register, using a memory-mapped I/O command "LD A, (mn)" (mn is a 2-byte integer) , the command size needs 3 bytes, but if you use the I/O mapped I/O method command "IN A, (g)" (g is a 1-byte integer), the command size only needs 2 bytes. . Therefore, the I/O mapped I/O method is normally used.

However, in some of the processes of the program, it is better to use memory-mapped I/O commands (instructions) than I/O-mapped I/O commands (instructions) to improve game control processing. It may be possible to reduce the capacity of the control area for performing Specifically, rather than accessing the same address of the input/output unit 704 allocated in the memory space with a command according to the I/O mapped I/O method such as an IN instruction or an OUT instruction, a memory mapped I/O method such as an LD instruction is used. The total command size may be smaller when accessing with a command based on the /O method. Therefore, here, an appropriate access method that reduces the total command size is used according to the content of the processing.

FIG. 240 is a flowchart for explaining an example of subcommand transmission processing, and FIG. 241 is a diagram showing an example of specific commands for realizing the subcommand transmission processing. Such subcommand transmission processing is executed in step S100-65 of FIG. 23 and step S3100-11 of FIG. 98 described above. In the subcommand transmission process, a command message (command) is transmitted to the sub control boards 330 and 502 through the transmission buffer (FIFO). Here, for convenience of explanation, an example in which the main CPU 500a executes the subcommand transmission process S3100-11 will be given, and the process related to subcommand accumulated data that is not related to this embodiment will be omitted. The numerical values of step S in the description of FIG. 240 are used only in the description of this figure.

Here, the messages 1, 2, 3, and 4 constituting the 4-byte command messages to be sent to the sub control board 502 are set in the D register, E register, B register, and C register, respectively. . However, depending on the command message to be sent, the messages 2 to 4 may be set after the fact. Further, when the electronic messages are not set for the electronic messages 3 and 4, predetermined values may be set for the electronic messages 3 and 4. FIG.

As shown in FIG. 240, first, the main CPU 500a saves the values of each register (S1), and determines whether messages 2 to 4 have already been set based on message 1 (S2). If telegrams 2 to 4 have been set (YES in S2), the main CPU 500a proceeds to step S6. S3), based on the message 1, it is determined whether or not the messages 3 and 4 have already been set (S4). If the messages 3 and 4 have been set (YES in S4), the main CPU 500a proceeds to step S6, and if not (NO in S4), sets a predetermined value to the messages 3 and 4 (S5 ).

Subsequently, the main CPU 500a sets the destination address (S6), sets telegram 2 as the augend (S7), and prohibits interrupts (S8). The main CPU 500a outputs the messages 1 to 4 (S9), calculates the checksums of the messages 1 to 4 (S10), and outputs the calculated checksums (S11). Finally, the main CPU 500a permits interrupts (S12), and restores the saved register values (S13).

Specifically, the index "CMDPROC" on the first line in FIG. 241 indicates the start address of the subcommand transmission process. The subcommand transmission process is called by the index "CMDPROC". The command "PUSH HL" on the second line saves the value of the HL register to the stack area, and the command "PUSH BC" on the third line saves the value of the BC register to the stack area. The commands on the second and third lines correspond to step S1 in FIG. 240 for saving the value of the register.

The value of the D register, that is, the value of telegram 1 is set in the A register by the command "LD A, D" on the fourth line in FIG. , A register is compared with the fixed value "B0H". As a result, if it is less than B0H (if the carry flag is set), the process moves to the index "CMDPROC01" on the 12th line. Thus, if the value of message 1 is less than B0H, the next process can be skipped and the process can be moved to the index "CMDPROC01" on the 12th line. The commands on the 4th and 5th lines correspond to step S2 in FIG. 240, in which if telegrams 2 to 4 have already been set, the process proceeds to step S6.

The command "LDQ A, (E)" on the 6th line in FIG. 241 sets the value of the Q register to the upper 1 byte of the address and the value of the E register to the lower 1 byte of the address, and stores them in the memory area indicated by the address. The 1-byte value (telegram 2) thus obtained is set in the A register, and the value of the A register, ie, telegram 2, is set in the E register by the command "LD E, A" on the seventh line. The commands on the 6th and 7th lines correspond to step S3 in FIG.

According to the command "JBIT Z, 3, D, CMDPROC01" on line 8 of FIG. Move to "CMDPROC01". Thus, if bit 3 of electronic message 1 is 0, the next process can be omitted and the process can move to the index "CMDPROC01" on the 12th line. The command on the eighth line corresponds to step S4 in FIG. 240, in which if telegrams 3 and 4 have already been set, the process proceeds to step S6.

The command "IN HL, (@CID_____)" on the 9th line in FIG. A 2-byte value stored in the memory area indicated by is input to the HL register. Specifically, the 1-byte value stored in the memory area indicated by the address is input to the L register, and the 1-byte value stored in the memory area indicated by the address plus 1 is transferred to the H register. is entered. The command "LD B, H" on the 10th line sets the value of the H register to the B register, and the command "LD C, L" on the 11th line sets the value of the L register to the C register. The commands on the 9th to 11th lines correspond to step S5 in FIG.

Subsequently, the value of the C register is set to the H register by the command "LD H, C" on the 13th line in FIG. Here, the C register used in the OUT instruction is released by transferring telegram 4 stored in the C register to the H register. The symbol "@S1DT____" itself is set in the C register by the command "LD C,@S1DT____" on the 14th line. The symbol "@S1DT____" indicates a transmission buffer (FIFO) of a transmission-only asynchronous serial communication circuit. The commands on the 13th and 14th lines correspond to step S6 in FIG. 240 for setting the destination address.

The command "LD A, E" on the 15th line in FIG. 241 sets the value of the E register (telegram 2) to the A register. This is because the value of the A register is used as the augend when calculating the checksum in step S10 of FIG. The command on the 15th line corresponds to step S7 in FIG. 240 for setting telegram 2 in the A register. Then, the interrupt is prohibited by the command "DI" on the 16th line. The command on the 16th line corresponds to step S8 in FIG.

The command "OUT (C), D" on line 17 in FIG. A value (telegram 1) is output. The command "OUT (C), A" on the 18th line sets the value of the U register to the upper 1 byte of the address, the value of the C register to the lower 1 byte, and stores the value of the A register (telegram 2) is output. The command "OUT (C), B" on the 19th line sets the value of the U register to the upper 1 byte of the address, the value of the C register to the lower 1 byte, and stores the value of the B register (data message) in the memory area indicated by the address. 3) is output. The command "OUT (C), H" on the 20th line sets the value of the U register to the upper 1 byte of the address, the value of the C register to the lower 1 byte, and stores the value of the H register (telegram 4) is output. Here, in the symbol "@S1DT____" itself (address value), data are stored in the order of the D register, A register (E register), B register, and H register (C register), that is, in the order of messages 1, 2, 3, and 4. is being output. The commands on the 17th to 20th lines correspond to step S9 in FIG. 240 for outputting messages 1 to 4.

The command "ADD A, D" on the 21st line in FIG. 241 adds the value of the D register (telegram 1) to the value of the A register (telegram 2), and the result is held in the A register. The command "ADD A, B" on the 22nd line adds the value of the B register (telegram 3) to the value of the A register (checksum value), and the result is held in the A register. The command "ADD A, H" on the 23rd line adds the value of the H register (telegram 4) to the value of the A register (checksum value), and the result is held in the A register. The commands on the 21st to 23rd lines correspond to step S10 in FIG.

The command "OUT (C), A" on the 24th line in FIG. A value (checksum value) is output. In this way, a command message of a total of 5 bytes consisting of the messages 1 to 4 and the checksum value is output to the transmission buffer. The command on the 24th line corresponds to step S11 in FIG. 240 for outputting the calculated checksum. Then, the interrupt is permitted by the command "EI" on the 25th line. The command on the 25th line corresponds to step S12 in FIG.

The data saved in the stack area is returned to the BC register by the command "POP BC" on the 26th line in FIG. Returned to register. The command on the 26th and 27th lines corresponds to step S13 in FIG. 240 for restoring the value of the register. Then, the command "RET" on the 28th line returns to the calling process.

In FIG. 241, the subcommand transmission processing in FIG. 240 is realized by the I/O mapped I/O method using the IN instruction and the OUT instruction. However, as described above, in some processes in a program, the command size may be smaller if the instructions of the memory-mapped I/O method are used. An example in which the memory-mapped I/O method is applied to some processing will be described below.

FIG. 242 is a diagram showing an example of another command for realizing subcommand transmission processing. 241, 4-byte telegrams 1, 2, 3, and 4 to be transmitted to the sub-control board 502 are set in the D, E, B, and C registers, respectively.

Comparing the command group in FIG. 241 with the command group in FIG. 242, the command group indicated by (1) corresponding to step S5 and the command group indicated by (2) corresponding to steps S6 to S11 are different. ing. Here, the difference in the total command size will be explained by focusing on the command group (1) and the command group (2) respectively.

Regarding the command group of (1), the 2-byte value stored in the memory area indicated by the symbol "@CID_____" is set in the BC register by the command "LD BC, (@CID_____)" on the 9th line in FIG. be. Specifically, the 1-byte value stored in the memory area indicated by the symbol "@CID_____" is input to the C register, and the 1-byte value stored in the memory area indicated by the symbol "@CID____"+1 is transferred to the B register. is entered. The command on the ninth line corresponds to step S5 in FIG.

In the example of FIG. 241, since the I/O mapped I/O system is used, the HL register can be selected as the setting destination of the value input by the IN instruction, but the BC register cannot be selected. In other words, the command "IN BC, (mn)" (where mn is a 2-byte integer) is not prepared as a command. Therefore, in the example of FIG. 241, the 2-byte value stored in the memory area indicated by the symbol "@CID____" must be temporarily held in the HL register and then transferred to the B and C registers. On the other hand, in the memory-mapped I/O method of FIG. 242, the 2-byte value stored in the memory area indicated by the symbol "@CID____" is directly set in the BC register by using the LD instruction. be able to.

Here, the total command size of the command group of (1) in FIG. 241 is the command "IN HL, (@CID_____)" 3 bytes on the 9th line + the command "LD B, H" 1 byte on the 10th line + 11th line command "LD C, L" 1 byte = 5 bytes, whereas the total command size of the command group (commands) in (1) of Fig. 242 is the command "LD BC, (@CID_____)" on the ninth line ” becomes 4 bytes. Therefore, it can be understood that the total command size can be reduced by 1 byte by changing the I/O mapped I/O method to the memory mapped I/O method.

Subsequently, for the command group (2), the 2-byte value of the symbol "@S2DT____" itself is set in the HL register by the command "LD HL,@S2DT____" on the 11th line in FIG. The symbol "@S2DT____" indicates an input buffer of a transmission-only asynchronous serial communication circuit. The command on the 11th line corresponds to step S6 in FIG. 240 for setting the destination address. In the example of FIG. 241, since the I/O mapped I/O system is used, the C register had to be released in order to use the OUT instruction. On the other hand, in the memory-mapped I/O method, the address of the transmission destination can be held in the HL register without the need to open the C register. Therefore, in the example of FIG. 242, the command "LD H, C" on line 13 of FIG. 241 can be deleted.

The command "LD A, E" on the 12th line in FIG. 242 sets the value of the E register (telegram 2) to the A register. The command on the 12th line corresponds to step S7 in FIG. 240 for setting telegram 2 in the A register. Then, the interrupt is prohibited by the command "DI" on the 13th line. The command on the 13th line corresponds to step S8 in FIG.

The command "LD (HL), D" on the 14th line in FIG. 242 stores the value of the D register (telegram 1) in the memory area indicated by the address of the HL register. The command "LD (HL), A" on the 15th line stores the value of the A register (telegram 2) in the memory area indicated by the address of the HL register. The command "LD (HL), B" on the 16th line stores the value of the B register (telegram 3) in the memory area indicated by the address of the HL register. The command "LD (HL), C" on the 17th line stores the value of the C register (telegram 4) in the memory area indicated by the address of the HL register. Here, data is stored in the symbol "@S1DT____" itself (address value) in the order of the D register, A register (E register), B register, and C register, that is, in the order of messages 1, 2, 3, and 4. As a result, data is output to the transmission buffer in order of messages 1, 2, 3, and 4. FIG. The commands on the 14th to 17th lines correspond to step S9 in FIG.

The command "ADD A, D" on the 18th line in FIG. 242 adds the value of the D register (telegram 1) to the value of the A register (telegram 2), and the result is held in the A register. The command "ADD A, B" on the 19th line adds the value of the B register (telegram 3) to the value of the A register (checksum value), and the result is held in the A register. The command "ADD A, C" on the 20th line adds the value of the C register (telegram 4) to the value of the A register (checksum value), and the result is held in the A register. The commands on the 18th to 20th lines correspond to step S10 in FIG.

The command "LD (HL), A" on the 21st line in FIG. 242 stores the value of the A register (checksum value) in the memory area indicated by the address of the HL register. In this way, a command message of a total of 5 bytes consisting of messages 1 to 4 and the checksum value is stored in the transmission buffer, and as a result, the command message is output to the transmission buffer. The command on the 21st line corresponds to step S11 in FIG. 240 for outputting the calculated checksum.

In the example of FIG. 241, the OUT instruction is used to output to the input/output unit 704 by the I/O mapped I/O method. On the other hand, in the memory mapped I/O method, the LD instruction can be used. Therefore, the command size can be reduced by holding the address of the transmission destination in the HL register instead of the C register and storing the value of each register in the memory area indicated by the address of the HL register with the LD instruction.

Here, the total command size of the command group of (2) in FIG. "LD A, E" 1 byte + 16th line command "DI" 1 byte + 17th line command "OUT (C), D" 2 bytes + 18th line command "OUT (C), A" 2 bytes + 19 lines 2nd command "OUT (C), B" 2 bytes + 20th line command "OUT (C), H" 2 bytes + 21st line command "ADD A, D" 1 byte + 22nd line command "ADD A, B" 1 byte + 23rd line command "ADD A, H" 1 byte + 24th line command "OUT (C), A" 2 bytes = 18 bytes, whereas the command group of (2) in Fig. 242 is the command "LD HL, @S2DT___" on the 11th line 3 bytes + the command "LD A, E" on the 12th line 1 byte + the command "DI" on the 13th line 1 byte + the command "LD (HL), D" 1 byte + 15th line command "LD (HL), A" 1 byte + 16th line command "LD (HL), B" 1 byte + 17th line command "LD (HL), C" " 1 byte + 18th line command "ADD A, D" 1 byte + 19th line command "ADD A, B" 1 byte + 20th line command "ADD A, C" 1 byte + 21st line command "LD ( HL), A" 1 byte=13 bytes.

Therefore, regarding the command group of (2), the total command size can be reduced by 5 bytes by changing the I/O mapped I/O method to the memory mapped I/O method. As can be understood by comparing the command group of (2) in FIG. 241 and the command group of (2) in FIG. 242, the total command size can be reduced by 1 byte each time the OUT instruction is replaced with the LD instruction.

As described above, in this embodiment, while accessing the input/output unit 704 by the I/O mapped I/O method, depending on the content of the processing, the memory mapped I/O method that reduces the total command size is used to access the input/output unit 704. 704 is accessed. In this way, by mixing the I/O mapped I/O method and the memory mapped I/O method in the same program and applying an access method that reduces the total command size depending on the content of the processing, the command It is possible to shorten and secure the capacity of the control area for performing the game control process.

<Usage example 1 of memory mapped I/O method>
As described above, the conventional microprocessor accesses the input/output unit 704 using the I/O mapped I/O method. In this case, the I/O space that can be assigned to the input/output unit 704 is limited to 256 bytes. In other words, in a conventional microprocessor, the input/output unit 704 can be specified by only one byte of address information.

FIG. 243 is a diagram showing part of a command group for implementing CPU initialization processing, and FIG. 244 is a diagram showing a table referred to in CPU initialization processing. Here, for convenience of explanation, the initialization processing (step S100-1 in FIG. 22 and step S2000-1 in FIG. 82) of the CPU initialization processing described above will be described. In the initial setting process, the input/output unit 704 is initialized by setting setting data in the input/output unit 704 (internal register). Here, an example in which the main CPU 500a executes the initial setting process S2000-1 will be given.

A command "LD HL, T_CPU_REG" on the first line in FIG. 243 sets the top address "T_CPU_REG" of the data group of the CPU built-in register setting data table, which is the read source, in the HL register. The symbol "@NUM_CPU_REG" itself is set in the B register by the command "LD B, @NUM_CPU_REG" on the second line.

As can be understood by referring to the 48th line of the CPU built-in register setting data table in FIG. 244, the symbol "@NUM_CPU_REG" describes the command "EQU ($-T_CPU_REG)/2". Here, "$" is the address next to the last address of the data group to be transferred, that is, the symbol "@NUM_CPU_REG" itself, and "T_CPU_REG" is the first address of the data group to be transferred. The value of T_CPU_REG (1-byte value indicating the number of data) is the total number of bytes of the 1-byte value. By dividing this value by 2, which is the number of combinations of addresses and values, the number of set data is derived. . For example, in the example of FIG. 244, the number of setting data is 30/2=15.

The index “INITIAL01” on the third line in FIG. 243 indicates the start address of the repeated processing. By the command "LDIN AC, (HL)" on the fourth line, the 1-byte value stored in the memory area indicated by the address of the HL register is stored in the C register, and the address of the value obtained by adding "1" to the HL register. A 1-byte value stored in the memory area indicated by is stored in the A register. The command "OUT (C), A" on the fifth line outputs the value (setting data) of the A register to the memory area (internal register) indicated by the address of the C register.

For example, if the HL register is the value of the address "T_CPU_REG", the 1-byte value "@PT0PR__" in the third line of FIG. is stored in the A register. Then, the value "160" of the A register is output to the memory area indicated by the symbol "@PT0PR__" of the C register.

Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ INITIAL01" on the sixth line in FIG. If the result of decrementing is 0, the process moves to the next command after the current command. Here, since the number of data is "15", the value of the B register becomes 0 when the processing from the index "INITIAL01" is repeated 15 times.

In this way, the total command size of the commands for the initial setting process shown in FIG. 2 bytes of the command "LDIN AC, (HL)" + 2 bytes of the command "OUT (C), A" of the fifth line + 2 bytes of the command "DJNZ INITIAL01" of the sixth line = 11 bytes.

As described above, in this embodiment, the address space of the input/output unit 704 is integrated with the address spaces of the main ROM 500b and the main RAM 500c. Therefore, the main CPU 500a accesses the input/output unit 704 through addresses FE00h to FFFFh in the memory space. In this case, the memory space to which the input/output unit 704 can be allocated is 512 bytes. By increasing the memory space in this way, the number of input/output units 704 to be allocated can also be increased. On the other hand, since the memory space becomes larger than 256 bytes, 2 bytes are required as an address for specifying the input/output unit 704 . For example, in the present embodiment, some input/output units 704 are allocated in advance to FE00h to FEFFh, which are 256-byte areas in the memory space, and other input/output units 704 are allocated to 256-byte areas in the memory space. It is assigned to FF00h to FFFFh. Therefore, the main CPU 500a must change the value of the U register between "FEH" and "FFH" every time it accesses the input/output unit 704 with a different high-order byte of the address. Here, another embodiment for implementing the initialization processing shown in FIG. 243 using the U register will be described.

FIG. 245 is a diagram showing another example of part of a command group for implementing CPU initialization processing, and FIG. 246 is a diagram showing another example of a table referred to in CPU initialization processing. be. Here, as in FIGS. 243 and 244, the main CPU 500a sets setting data in the input/output unit 704 (built-in register) by the I/O mapped I/O method for convenience of explanation.

The command "LDF HL, T_CPU_REG" on the first line in FIG. 245 sets the top address "T_CPU_REG" of the data group in the CPU built-in register setting data table in FIG. 246 to the HL register. The symbol "@NUM_CPU_RG1" itself is set in the B register by the command "LD B, @NUM_CPU_RG1" on the second line.

As can be understood by referring to the 42nd line of the CPU built-in register setting data table in FIG. 246, the symbol "@NUM_CPU_RG1" describes the command "EQU ($-T_CPU_REG)/2". Here, "$" is the symbol "@NUM_CPU_RG1" itself, and "T_CPU_REG" is the head address of the data group to be the transfer source, so the value of $-T_CPU_REG is the total number of bytes of the 1-byte value indicating the number of data. By dividing this value by 2, which is the number of combinations of addresses and values, the number of setting data is derived. For example, in the example of FIG. 246, the number of setting data is 26/2=13.

The command "LD U, 0FEH" on the third line in FIG. Here, two values "FEH" and "FFH" are prepared as high-order addresses of the addresses indicating the plurality of input/output units 704, and the main CPU 500a, depending on the input/output unit 704 to be accessed, each time , changes the value of the U register, which is the upper byte. The initial value of the U register is "FFH". Here, first, "FEH" is set in the U register ("FFH" is changed to "FEH"), and setting data is set for the input/output unit 704 whose upper address is "FEH".

The index “INITIAL01” on the fourth line in FIG. 245 indicates the start address of the repeated processing. By the command "LDIN AC, (HL)" on the fifth line, the value stored in the memory area indicated by the address of the HL register is stored in the C register, and "1" is added to the value of the HL register. The value stored in the memory area is stored in the A register. The command "OUT (C), A" on the sixth line outputs the value (setting data) of the A register to the memory area (internal register) indicated by the address of the C register.

For example, if the HL register is the value of the address "T_CPU_REG", the 1-byte value "@PT0PR__" (for example, "01H") in the third line of FIG. 246 is stored in the C register, and the A 1-byte value "160" is stored in the A register. Then, the value "160" of the A register is output to the memory area indicated by the symbol "@PT0PR__" of the C register.

The value of the B register is decremented (subtracted by "1") by the command "DJNZ INITIAL01" on line 7 of FIG. If the result is 0, the process moves to the next command after the command. Here, since the number of data is "13", the value of the B register becomes 0 when the processing from the index "INITIAL01" is repeated 13 times. In this way, setting of setting data for the thirteen input/output units 704 in the preceding stage of FIG. 246 is completed.

The command "LD U, 0FFH" on the eighth line in FIG. As described above, of the two values "FEH" and "FFH" as the address indicating the input/output unit 704, the setting data for the input/output unit 704 whose upper address is "FEH" has been completed. Here, "FFH" is set in the U register, and setting data is set for the input/output unit 704 whose upper address is "FFH". By setting "FFH" in the U register, the U register is returned to its initial value.

The command "LD B, @NUM_CPU_RG2" on the ninth line in FIG. 245 sets the symbol "@NUM_CPU_RG2" itself in the B register. As can be understood by referring to the 50th line of the CPU built-in register setting data table in FIG. 246, the symbol "@NUM_CPU_RG2" describes the command "EQU ($-T_CPU_REG)/2-@NUM_CPU_RG1". there is Here, "$" is the symbol "@NUM_CPU_RG2" itself, and "T_CPU_REG" is the top address of the 1-byte data group that is the transfer source. NUM_CPU_RG1" is 13, so in the example of FIG. 246, the number of setting data is 15-13=2.

The index “INITIAL02” on the 10th line in FIG. 245 indicates the starting address of the repeated processing. By the command "LDIN AC, (HL)" on the 11th line, the value stored in the memory area indicated by the address of the HL register is stored in the C register, and "1" is added to the value of the HL register. The value stored in the memory area is stored in the A register. The command "OUT (C), A" on the 12th line outputs the value (setting data) of the A register to the memory area (internal register) indicated by the address of the C register.

For example, if the HL register was the symbol "@NUM_CPU_RG1" itself, then the 1-byte value "@S1CM____" (e.g., "2CH") on line 44 of FIG. A 1-byte value "10000000B" is stored in the A register. Then, the value "10000000B" of the A register is output to the memory area indicated by the symbol "@S1CM___" of the C register.

Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ INITIAL02" on the 13th line of FIG. If the result of decrementing is 0, the process moves to the next command after the current command. Here, since the number of data is "2", the value of the B register becomes 0 when the processing from the index "INITIAL02" is repeated twice. In this way, the setting of the setting data for the second input/output unit 704 in the latter stage of FIG. 246 is completed.

In this way, the total command size of the commands for the initialization processing shown in FIG. command "LD U, 0FEH" 3 bytes + 5th line command "LDIN AC, (HL)" 2 bytes + 6th line command "OUT (C), A" 2 bytes + 7th line command "DJNZ INITIAL01" 2 Byte + 8th line command "LD U, 0FFH" 3 bytes + 9th line command "LD B, @NUM_CPU_RG2" 2 bytes + 11th line command "LDIN AC, (HL)" 2 bytes + 12th line command "OUT (C), A” 2 bytes+13th line command “DJNZ INITIAL02” 2 bytes=24 bytes.

Here, since the U register must be changed in order to access a plurality of input/output units 704, the total command size is correspondingly larger than in the example of FIG. However, as described above, in some processes in the program, the command size may be smaller if the instructions of the memory-mapped I/O method are used instead of the I/O-mapped I/O method. be. Therefore, an example in which the memory-mapped I/O method is applied to some processing will be described.

FIG. 247 is a diagram showing another example of part of a command group for implementing CPU initialization processing. Here, unlike FIGS. 243 and 245, the main CPU 500a sets setting data in the input/output unit 704 (built-in register) by the memory-mapped I/O method. Since the CPU built-in register setting data table shown in FIG. 246 can be used as it is for the CPU built-in register setting data table referred to in the CPU initialization process, it will be explained using FIG.

The command "LDF HL, T_CPU_REG" on the first line in FIG. is set to The symbol "@NUM_CPU_RG1" itself (the number to be transferred) is set in the B register (first register) by the command "LD B, @NUM_CPU_RG1" on the second line.

As can be understood by referring to the 42nd line of the CPU built-in register setting data table in FIG. 246, the symbol "@NUM_CPU_RG1" describes the command "EQU ($-T_CPU_REG)/2". Here, the value of $-T_CPU_REG is the total number of bytes of the 1-byte value indicating the number of data, and when this value is divided by 2, which is the number of combinations of addresses and values, the number of set data is 26/2=13. becomes.

The command "LD Q, HIGH @PTOPR__" on the third line in FIG. 247 sets the upper byte value ("FEH") of the symbol "@PTOPR__" in the Q register. Here, since the input/output unit 704 is accessed by the memory mapped I/O method, the upper byte of the input/output unit 704 is set in the QH register instead of the U register. As described above, two values "FEH" and "FFH" are prepared as addresses indicating the input/output unit 704, and the main CPU 500a changes the high-order byte according to the input/output unit 704 to be accessed each time. The value of the Q register is changed. The initial value of the Q register is "F0H" corresponding to the top address of the main RAM 500c. Here, first, "FEH" is set in the Q register (third register), and setting data is set for the input/output unit 704 whose upper address is "FEH".

The command "LDINTQR (HL)" on the fourth line in FIG. 247 sets the value of the Q register to the upper 1 byte of the transfer destination address, and the value stored in the memory area indicated by the address of the HL register to the lower order of the transfer destination address. The value stored in the memory area indicated by the address obtained by adding "1" to the value of the HL register as 1 byte is transferred to the memory area indicated by the transfer destination address, and the value of the HL register is changed to "2". is added to update the address to be transferred next, the value of the B register is decremented (subtracted by "1"), and the process is repeated until the decremented result becomes 0, that is, the set data 13 times. In this way, setting of setting data for the thirteen input/output units 704 in the preceding stage of FIG. 246 is completed. With such an LDINTQR instruction, processing is executed without using registers other than the B, HL, and Q registers, such as the A register.

The command "LD B, @NUM_CPU_RG2" on the fifth line in FIG. 247 sets the symbol "@NUM_CPU_RG2" itself (the number to be transferred) in the B register (first register). As can be understood by referring to the 50th line of the CPU built-in register setting data table in FIG. 246, the symbol "@NUM_CPU_RG2" describes the command "EQU ($-T_CPU_REG)/2-@NUM_CPU_RG1". there is Here, the value of $-T_CPU_REG (one-byte value indicating the number of data) is 30/2=15, and "@NUM_CPU_RG1" is 13, so in the example of FIG. 2.

The command “LD Q, HIGH @S2CMS__” on the sixth line in FIG. 247 sets the upper byte value (“FFH”) of the symbol “@S2CMS__” in the Q register (third register). In this case as well, since the input/output unit 704 is accessed by the memory-mapped I/O method, the upper byte of the input/output unit 704 is set in the QH register instead of the U register. As described above, of the two values "FEH" and "FFH" as the address indicating the input/output unit 704, setting of the setting data for the input/output unit 704 with the higher address "FEH" is completed. Therefore, here, "FFH" is set in the Q register, and setting data is set for the input/output unit 704 whose upper address is "FFH".

The command "LDINTQR (HL)" on the 7th line in FIG. The value stored in the memory area indicated by the address obtained by adding "1" to the value of the HL register, which is the lower 1 byte of the transfer destination address, is transferred to the memory area indicated by the transfer destination address. The address to be transferred next is updated by adding "2" to the value, the value of the B register is decremented (subtracted by "1"), and the decremented result becomes 0, that is, the setting data is set twice. The process is repeated. In this way, the setting of the setting data for the second input/output unit 704 in the latter stage of FIG. 246 is completed. With such an LDINTQR instruction, processing is executed without using registers other than the B, HL, and Q registers, such as the A register.

Then, the command "LD Q, HIGH @RAM_BGN_ADR" on the eighth line in FIG. 247 sets the upper byte value of the symbol "@RAM_BGN_ADR" in the Q register. Thus, the value of the Q register is restored to the initial value "F0H".

In this way, the total command size of the commands for the initial setting process shown in FIG. command "LD Q, HIGH @PTOPR__" 2 bytes + 4th line command "LDINTQR (HL)" 2 bytes + 5th line command "LD B, @NUM_CPU_RG2" 2 bytes + 6th line command "LD Q, HIGH @ S2CMS__” 2 bytes + 7th line command “LDINTQR (HL)” 2 bytes + command “LD Q, HIGH @RAM_BGN_ADR” 1 byte = 15 bytes.

Here, the I/O mapped I/O system in FIG. 245 is changed to the memory mapped I/O system as shown in FIG. 247, and accordingly the LDINTQR instruction can be used. 245 is 24 bytes, the total command size of the initialization processing command in FIG. 247 is 15 bytes, so that 9 bytes can be reduced. Thus, by using the LDINTQR instruction by the memory-mapped I/O method, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

<Usage example 2 of memory mapped I/O method>
FIG. 248 is an explanatory diagram showing addresses of output ports, and FIG. 249 is a diagram showing a part of a command group for realizing save processing at power-off. Here, for convenience of explanation, the output port clearing process (step S300-11 in FIG. 25 and step S3000-11 in FIG. 97) in the saving process S3000 at power failure will be described. In the output port clear processing, the output of the output port is cleared to 0. Here, an example in which the main CPU 500a executes the output port clearing process S3000-11 will be given.

In this embodiment, a total of 9 output ports, output ports 0 to 8, are prepared as the input/output unit 704 . The output ports 0 to 8 can continuously output discrete signals (binary values of Hi (high level) and Low (low level)) bit by bit. Note that the target of the output port clear processing is limited to a total of 6 output ports 0 to 4 and 7 among the output ports 0 to 8. FIG. Therefore, output ports 0 to 4 and 7 are cleared in the output port clear process.

Referring to FIG. 248, output port 4 is assigned to address "FFF0H" in the memory space, output port 3 is assigned to address "FFF1H", output port 2 is assigned to address "FFF2H", and address "FFF3H" is assigned. is assigned output port 1, address "FFF4H" is assigned output port 0, and address "FFF5H" is assigned output port 7.

The output port clear processing in FIG. 249 is processing that is performed only when "0" is set in the A register. It means that By the command "LD BC, 6*256+@OUT_PRT_7" on the first line in FIG. 249, 6, which is the number of output ports, is set in the B register, and the lower 1-byte address value indicating output port 7 is set in the C register. be. As shown in FIG. 248, the value of the lower 1 byte indicating output port 7 is "F5H". By the command "OUT (C), A" on the third line, the value of the U register (here, the initial value "FFH") is set to the upper 1 byte of the address, the value of the C register is set to the lower 1 byte, and the address The value of the A register (“0”) is output to the memory area indicated by .

The value stored at the address indicated by the C register is decremented by one by the command "DEC C" on the fourth line in FIG. The command "DJNZ PRFPROC02" on the fifth line decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, the index "PRFPROC02" on the second line is reached, If it is 0, the process moves to the next command after the command. Here, since the number of output ports is "6", the value of the B register becomes 0 when the processing from the index "PRFPROC02" is repeated six times.

In this way, the address of the input/output unit 704 is decremented in the order of "FFF5H"→"FFF4H"→"FFF3H"→"FFF2H"→"FFF1H"→"FFF0H". Each bit of the output port is set to 0 in the order of →output port 2 →output port 3 →output port 4.

In this way, the total command size of the commands for the output port clear processing shown in FIG. 2 bytes+4th line command "DEC C" 1 byte+5th line command "DJNZ PRFPROC02" 2 bytes=8 bytes.

As described above, in some processes in a program, the command size may be reduced by using instructions of the memory-mapped I/O method instead of the I/O-mapped I/O method. Therefore, an example in which the memory-mapped I/O method is applied to some processing will be described.

FIG. 250 is a diagram showing another example of part of the command group for realizing the saving process at power failure. Here, the main CPU 500a clears the output of the output port to 0 by the memory mapped I/O method.

The command "LD HL, @OUT_PRT_4" on the first line in FIG. 250 sets the 2-byte symbol "@OUT_PRT_4" itself (output port information) indicating output port 4 in the HL register (second register). As shown in FIG. 248, the 2-byte value indicating output port 4 is "FFF0H". The command "LD B, 6" on the second line sets 6, which is the number of output ports to be cleared (the number to be cleared), in the B register (first register).

The command "CLRIRS" on the third line in FIG. The address to be cleared is updated, the value of the B register is decremented (subtracted by "1"), and the process is repeated until the decremented result becomes 0, that is, six times, which is the number of output ports to be cleared. . With such a CLRIRS instruction, processing is executed without using registers other than the B and HL registers, such as the A register.

In this way, the address of the input/output unit 704 is incremented in the order of "FFF0H"→"FFF1H"→"FFF2H"→"FFF3H"→"FFF4H"→"FFF5H". The outputs of the output ports are set to 0 in the order of →output port 1 →output port 0 →output port 7.

In this way, the total command size of the commands for the output port clear processing shown in FIG. Second command "CLRIRS" 2 bytes=7 bytes.

Here, the I/O mapped I/O system in FIG. 249 is changed to the memory mapped I/O system as shown in FIG. 250, and the CLRIRS instruction can be used accordingly. Then, the total command size of the output port clear processing command in FIG. 249 is 8 bytes, whereas the total command size of the output port clear processing command in FIG. 250 is 7 bytes. Become. Thus, by using the CLRIRS instruction by the memory-mapped I/O method, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

In the example of FIG. 250, the use of the CLRIRS instruction eliminates the need to use the A register. Therefore, the value of the A register is not unintentionally updated. For example, if the A register has already been used, normally it would have been necessary to save the A register, but since the A register is not used here, there is no need to save it. In this way, it becomes possible to effectively use resources. In the example of FIG. 249, it is assumed that the value "0" is set in advance in the A register. Processing for setting "0" is also unnecessary. In this way, it becomes possible to further shorten the command and secure the capacity of the control area for performing the game control process.

Although the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such embodiments. It is obvious that a person skilled in the art can conceive of various modifications or modifications within the scope of the claims, and it should be understood that these also belong to the technical scope of the present invention. be done.

Further, in the above-described embodiment, the main control boards 300, 500 and the sub-control boards 330, 502 are arranged to share the function parts for progressing the game, but the function parts of the main control boards 300, 500 may be arranged on the sub-control boards 330 and 502, the functional units of the sub-control boards 330 and 502 may be arranged on the main control boards 300 and 500, and all the functional units may be integrated into one control board. can also be distributed.

Further, each processing performed by the main control boards 300, 500 and the sub-control boards 330, 502 described above does not necessarily have to be processed chronologically according to the order described in the flow chart, and may include parallel or subroutine processing. It's okay.

100 Gaming machines 300, 500 Main control boards 300a, 500a Main CPU
300b, 500b Main ROM
300c, 500c Main RAM
330, 502 Sub-control boards 330a, 502a Sub-CPU
330b, 502b Sub-ROM
330c, 502c, sub RAM
400 slot machine

Claims (5)

A game machine comprising a CPU, a ROM storing a program used by the CPU, and a RAM holding data, on a predetermined board used for progressing a game,
The CPU
reading the program from the ROM;
Based on said program,
call a subroutine,
In the subroutine,
comparing the value of the A register with the value stored in the RAM at the address indicated by the predetermined value;
returning from the subroutine depending on the result of the comparison;
multiplying the multiplicand, which changes based on the progress of the game, by the multiplier to obtain a ratio related to the game profit,
The multiplication is executed by adding up the results of multiplying the multiplicands separated in units of 1 byte by multipliers. A game machine comprising a CPU, a ROM storing a program used by the CPU, and a RAM holding data, on a predetermined board used for progressing a game,
The CPU
reading the program from the ROM;
Based on said program,
call a subroutine,
In the subroutine,
comparing the value of the A register with the value stored in the RAM at the address indicated by the predetermined value;
returning from the subroutine depending on the result of the comparison;
multiplying the multiplicand, which changes based on the progress of the game, by the multiplier to obtain a ratio related to the game profit,
The multiplication is performed by a 16-bit multiplier in which the multiplicand is set in the multiplicand setting register and the multiplier is set in the multiplier setting register, and the multiplication result is generated in the multiplication result register after a predetermined time. A game machine comprising a CPU, a ROM storing a program used by the CPU, and a RAM holding data, on a predetermined board used for progressing a game,
The CPU
reading the program from the ROM;
Based on said program,
call a subroutine,
In the subroutine,
comparing the value of the A register with the value stored in the RAM at the address indicated by the predetermined value;
returning from the subroutine depending on the result of the comparison;
Dividing the dividend, which changes based on the progress of the game, by the divisor to obtain a ratio relating to the game profit,
The division is performed by a 32-bit divider that generates the division result in the division result register after a predetermined time by setting the dividend in the dividend setting register and the divisor in the divisor setting register. A game machine comprising a CPU, a ROM storing a program used by the CPU, and a RAM holding data, on a predetermined board used for progressing a game,
The CPU
reading the program from the ROM;
Based on said program,
call a subroutine,
In the subroutine,
comparing the value of the A register with the value stored in the RAM at the address indicated by the predetermined value;
returning from the subroutine depending on the result of the comparison;
Multiplying the multiplier by the multiplicand that changes based on the progress of the game,
dividing the dividend by the divisor to obtain the ratio of the multiplicand to the divisor;
By setting the multiplicand in the multiplicand setting register and the multiplier in the multiplier setting register, the multiplication is executed by a 16-bit multiplier in which the multiplication result is generated in the multiplication result register after a predetermined time,
The maximum value of the multiplication result is 3 bytes or more,
The division is performed by a 32-bit divider that generates the division result in the division result register after a predetermined time by setting the dividend in the dividend setting register and the divisor in the divisor setting register. A game machine comprising a CPU, a ROM storing a program used by the CPU, and a RAM holding data, on a predetermined board used for progressing a game,
The CPU
reading the program from the ROM;
Based on said program,
call a subroutine,
In the subroutine,
comparing the value of the A register with the value stored in the RAM at the address indicated by the predetermined value;
returning from the subroutine depending on the result of the comparison;
Multiplying the multiplier by the multiplicand that changes based on the progress of the game,
dividing the dividend by the divisor to obtain the ratio of the multiplicand to the divisor;
The multiplication is performed by accumulating results obtained by multiplying each of the multiplicands separated in units of one byte by a multiplier,
The maximum value of the multiplication result is 4 bytes,
The division is performed by a 32-bit divider that generates the division result in the division result register after a predetermined time by setting the dividend in the dividend setting register and the divisor in the divisor setting register.

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