JP2022172851A - Switching power source circuit - Google Patents

Abstract

To perform a stable phase compensation while suppressing increase of the area of a circuit layout or the number of terminals.SOLUTION: A switching power source circuit supplies electric power from a power source circuit to a load so that a switching operation of a switching element makes a voltage applied to the load a predetermined value. The circuit includes an error amplifier, an oscillation circuit, a comparator, and a phase compensation circuit. The phase compensation circuit includes: a first resistor and a second capacitor for converting the output voltage of the error amplifier to a first current signal and a second current signal; a first current mirror circuit and a second current mirror circuit in which the first current signal and the second current signal are input, respectively; and a second resistor for receiving an output current of the first current mirror and an output current of the second current mirror and generating an output voltage for an input terminal of the comparator.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to switching power supply circuits.

2. Description of the Related Art A so-called switching power supply circuit that utilizes the switching operation of a switching element is known as a power supply circuit for stabilizing the voltage from a power supply to a predetermined value in order to stably operate a load to which power is supplied. (for example, Patent Document 1). This type of switching power supply circuit is used in the form of a composite power supply IC or the like. For example, in a vehicle, it is installed together with other circuits (amplifier, LDO (Low Drop-Out), etc.) to step down the power supply voltage of a 12V vehicle battery. It supplies power to various devices (microcomputers, etc.) that are loads mounted on the vehicle.

JP 2010-51127 A

Here, a switching power supply circuit according to background art will be described with reference to FIGS. 7 and 8. FIG. 7 and 8 are circuit diagrams showing switching power supply circuits 1A' and 1B' according to the reference technology together with peripheral configurations. 7 and 8 exemplify a voltage feedback type step-down switching power supply circuit, the left side of the broken line shows the internal circuit of an IC (integrated circuit), and the right side of the broken line shows the configuration of the external circuit of the IC. is shown.

A switching power supply circuit 1A' shown in FIG. 7 includes an error amplifier AMP1 and a comparator COMP1. The error amplifier AMP1 has a pair of input terminals, that is, an inverting input terminal 2 and a non-inverting input terminal 4, and a differential output terminal for extracting a differential output according to the potential difference between the inverting input terminal 2 and the non-inverting input terminal 4. 6. A feedback voltage (output detection voltage) obtained by dividing the output voltage Vout by feedback resistors RFB1 and RFB2 is input to the inverting input terminal 2, and a reference voltage VREF is input to the non-inverting input terminal 4. is output from the differential output terminal 6. The comparator COMP1 has a non-inverting input terminal 8 to which the output voltage from the differential output terminal 6 is input, and an inverting input to which a triangular wave (or sawtooth wave) voltage having a constant period generated by the oscillation circuit 7 is input. A voltage corresponding to the result of comparison between the two is output from an output terminal 12 . The output voltage of comparator COMP1 is input to gate drive circuit 14, and gate drive circuit 14 outputs a corresponding gate drive voltage to terminal GATE.

The output transistor MP1 is a P-channel MOS transistor (MOSFET), its source is connected to the power supply voltage VBAT, its drain is connected to the load resistor RL via the inductance L1, and its gate is It is connected to the terminal GATE. A gate drive voltage is input to the gate of the output transistor MP1 from the terminal GATE, and a switching operation is performed to connect or disconnect the source and the drain according to the gate drive voltage. to supply power at a predetermined output voltage VOUT.

The switching power supply circuit 1A' has a load resistor RL as a load, and a feedback circuit 15 including feedback resistors RFB1 and RFB2 is provided with a phase compensation capacitor CFB. More specifically, the phase compensation capacitor CFB is provided between the input side of the feedback circuit 15 and the node between the feedback resistors RFB1 and RFB2. Here, in order to reduce the number of parts in a composite power supply IC, it may be required to mount each element such as the feedback resistors RFB1 and RFB2 and the phase compensation capacitor CFB inside the IC. In this case, when the output voltage VOUT of the switching power supply circuit 1A' becomes relatively high, the voltage applied to the phase compensation capacitor CFB increases during operation, so a phase compensation capacitor CFB with a high withstand voltage is required. Depending on the semiconductor manufacturing process, it is not possible to manufacture such a high withstand voltage phase compensation capacitor CFB. If it is attempted, the area becomes large, so it is difficult to mount it in the IC.

Further, as shown in FIG. 8, the switching power supply circuit 1B' including a light emitting diode (LED) as a load also has the following problems.
The switching power supply circuit 1B' includes light-emitting diodes LED1 and LED2 as loads, unlike the switching power supply circuit 1A' described above. These light-emitting diodes LED1 and LED2 are provided in a feedback circuit like the switching power supply circuit 1A' in FIG. 15 cannot be provided with a phase compensation capacitor CFB. Therefore, in the switching power supply circuit 1B', a current detection resistor RSENSE is arranged between the source of the output transistor MP1 and the power supply voltage VBAT, and is provided between the source of the output transistor MP1 and the current detection resistor RSENSE. In some cases, a method of monitoring the source current of the output transistor MP1 and performing current mode control may be adopted by adding a SENSE terminal for detecting the potential of the node that is applied.

In a switching power supply circuit configured as a composite power supply IC, it is preferable to reduce the number of terminals as much as possible and assign them to pins of other circuits. As described above, additional SENSE terminals are required, resulting in an increase in the number of terminals. As for the external circuits of the IC, it is preferable to reduce the number of parts by limiting the specifications to the specifications rather than to increase the versatility. Resulting in. In addition, the provision of the current detection resistor RSENSE not a little increases power consumption during operation and also causes loss.

At least one embodiment of the present disclosure has been made in view of the above circumstances, and an object thereof is to provide a switching power supply circuit capable of performing stable phase compensation while suppressing an increase in the circuit layout area and the number of terminals. and

In order to solve the above problems, a switching power supply circuit according to one embodiment includes:
A switching power supply circuit capable of supplying power from the power supply circuit to a load such that the voltage applied to the load becomes a predetermined value by switching operation of a switching element,
A first capacitor is connected to the output terminal, and an error capable of outputting from the output terminal a signal based on the difference between the output detection voltage and the reference voltage that linearly or nonlinearly changes according to the voltage applied to the load. an amplifier;
an oscillation circuit capable of generating a triangular wave voltage having a constant period;
a comparator capable of controlling the switching operation of the switching element by comparing the output voltage of the error amplifier and the triangular wave voltage of the oscillation circuit;
a phase compensation circuit inserted between the output terminal of the error amplifier and the input terminal of the comparator;
with
The phase compensation circuit is
a first resistor for converting the output voltage of the error amplifier into a first current signal;
a second capacitor for converting the output voltage of the error amplifier into a second current signal;
a first current mirror circuit and a second current mirror circuit to which the first current signal and the second current signal are input, respectively;
a second resistor receiving the output currents of the first current mirror circuit and the second current mirror circuit and generating an output voltage for the input terminal of the comparator;
Prepare.

According to at least one embodiment of the present disclosure, it is possible to provide a switching power supply circuit capable of performing stable phase compensation while suppressing increases in circuit layout area and the number of terminals.

1 is a circuit diagram showing the configuration of a switching power supply circuit according to a first embodiment; FIG. 2 is a circuit diagram showing a configuration of a phase compensation circuit in FIG. 1; FIG. 8 is a circuit diagram showing a phase compensation circuit included in a switching power supply circuit according to a second embodiment; FIG. FIG. 3 is a diagram showing signal waveforms in the switching power supply circuit; FIG. 11 is a circuit diagram of a switching power supply circuit according to a third embodiment; 6 is a circuit diagram showing the phase compensation circuit of FIG. 5; FIG. 1 is a circuit diagram showing a switching power supply circuit according to a reference technique; FIG. 1 is a circuit diagram showing a switching power supply circuit according to a reference technique; FIG.

Several embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, the dimensions, materials, shapes, relative arrangements, etc. of the components described as the embodiment or shown in the drawings are not meant to limit the scope of the present disclosure, but are merely illustrative examples. do not have.

First, as a premise of the embodiment according to the present disclosure, basic phase compensation in the switching power supply circuit 1A' according to the reference technology described above will be described with reference to FIG. In the switching power supply circuit 1A', the resonance frequency _f0 in the output section 16 composed of the capacitor COUT and the inductance L1 is expressed as follows.

In the phase compensation, the zero generated by the first capacitor CEO and the resistor REO connected between the output terminal 6 (EOUT terminal) of the error amplifier AMP1 and the ground point, and the zero generated by the phase compensation capacitor CFB and the feedback resistor RFB1. By setting zero and near the resonance frequency f0 represented by equation (1), the phase delay occurring at the resonance frequency of the inductance L1 and the capacitor COUT is cancelled. The zero frequency f _Z1 generated by the first capacitor CEO and the resistor REO and the zero frequency f _Z2 generated by the feedback resistor RFB1 are expressed as follows.

(First embodiment)
Next, a switching power supply circuit 1A according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a circuit diagram showing the configuration of the switching power supply circuit 1A according to the first embodiment, and FIG. 2 is a circuit diagram showing the configuration of the phase compensation circuit 20A of FIG.

The switching power supply circuit 1A is a circuit for supplying power at a predetermined voltage to a load. Although FIG. 1 exemplifies the resistor RL as the load of the switching power supply circuit 1A, the load may include a light emitting diode LED as shown in the switching power supply circuit 1B' of FIG. The switching power supply circuit 1A includes a phase compensation circuit 20A having a function of performing phase compensation. The phase compensation circuit 20A is arranged so as to be inserted between the output terminal 6 of the error amplifier AMP1 and the non-inverting input terminal 8 of the comparator COMP1, and is adapted for loads including various elements including resistors and light emitting diodes. It can be applied to a switching power supply circuit that supplies power.

As shown in FIG. 2, the phase compensation circuit 20A includes a first resistor R1 for converting the output voltage of the error amplifier AMP1 into a first current signal CS1, and a first resistor R1 for converting the output voltage of the error amplifier AMP1 into a second current signal CS2. a first current mirror circuit CM1 and a second current mirror circuit CM2 to which the first current signal CS1 and the second current signal CS2 are respectively input; a first current mirror circuit CM1 and a second current mirror circuit CM1; and a second resistor R2 for receiving the output current of the mirror circuit CM2 and generating an output voltage for the comparator COMP1.

The phase compensation circuit 20A has a SIN terminal as an input terminal and a SOUT terminal as an output terminal. The SIN terminal is connected to transistors MN1 and MN2, which are N-channel MOS transistors (MOSFETs) for buffering the voltage input from the error amplifier AMP1 to the SIN terminal. More specifically, the transistor MN1 has its gate connected to the SIN terminal, its source connected to the second capacitor C2, and its drain connected to the second current mirror circuit CM2. The transistor MN2 has a gate connected to the SIN terminal, a source connected to the first resistor R1, and a drain connected to the first current mirror circuit CM1. A first resistor R1 is connected between the source of the transistor MN2 and the ground GND, and converts the output voltage from the error amplifier AMP1 into a first current signal CS1. A second capacitor C2 is connected between the source of the transistor MN1 and the ground GND, and converts the output voltage of the error amplifier AMP1 into a second current signal CS2.

The first current signal CS1 is folded back by a first current mirror circuit CM1 including transistors MP2 and MP3 which are P-channel MOS transistors (MOSFETs). The first current mirror circuit CM1 has transistors MP2 and MP3. More specifically, transistor MP2 has its gate and drain connected to the drain of transistor MN2 and its source connected to the source of transistor MP3. The transistor MP3 has a gate connected to the drain of the transistor MN2, a source connected to the source of the transistor MP2, and a drain connected to the SOUT terminal.

The second current signal CS2 is folded back by a second current mirror circuit CM2 including transistors MP4 and MP5 which are P-channel MOS transistors (MOSFETs). The second current mirror circuit CM2 has transistors MP4 and MP5. More specifically, transistor MP4 has its gate and drain connected to the drain of transistor MN1 and its source connected to the source of transistor MP5. The transistor MP5 has a gate connected to the drain of the transistor MN1, a source connected to the source of the transistor MP4, and a drain connected to the SOUT terminal.

A second resistor R2 is connected between the SOUT terminal and the ground point GND on the output sides of the first current mirror circuit CM1 and the second current mirror circuit CM2. Thus, the output terminal SOUT of the phase compensation circuit 20A is configured as a node where the second resistor R2 and the outputs of the current mirror circuits CM1 and CM2 are connected to each other, and is connected to the non-inverting input terminal 8 of the comparator COMP1.

ここでｖ_ｓｏ：ＳＯＵＴ端子における電圧（小信号）、ｖ_ｓｉ：ＳＩＮ端子における電圧（小信号）、ｍ：トランジスタＭＰ４及びＭＰ５のドレイン電流比である。 In the phase compensation circuit 20A having such a configuration, the output voltage of the error amplifier AMP1 is input from the SIN terminal to the gates of the transistors MN1 and MN2. The transistors MN1 and MN2 function as buffers for the voltage signal input from the SIN terminal, and apply the voltage lowered by the gate-source potential difference (Vgs) of the transistors MN1 and MN2 to the second capacitor C2 connected to their respective sources. and the first resistor R1. The drain currents of the transistors MN1 and MN2 (the first current signal CS1 and the second current signal CS2) are folded back by the first current mirror circuit CM1 and the second current mirror circuit CM2 and flow through the second resistor R2. The current source I1 is configured to apply a DC bias current to the second current mirror circuit CM2 including the transistors MP4 and MP5, and the transfer function of the phase compensation circuit 20A is expressed as follows.

where v _so is the voltage at the SOUT terminal (small signal), v _si is the voltage at the SIN terminal (small signal), and m is the drain current ratio of transistors MP4 and MP5.

The frequency _fz3 , which is zero in this embodiment, is obtained as follows from the above equation (4).

Here, m is the ratio between the input (drain current of transistor MP4) and the output (drain current of transistor MP5) of the second current mirror circuit CM2 by transistors MP4 and MP5, and is determined by the gate aspect ratio of transistors MP4 and MP5. parameter. Since the zero frequency _fz3 shown in Equation (5) depends on the value of m, it can be changed by adjusting the value of m. Therefore, even if the capacitance value of the second capacitor C2 included in the phase compensation circuit 20A is small, it is possible to generate zero at low frequencies by adjusting the value of m. This contributes to reducing the layout area of the entire switching power supply circuit by reducing the number of capacitors that require a large layout area.

As described above, according to the present embodiment, the phase compensation capacitor CFB with a high withstand voltage as in the conventional example is not required, and the second capacitor C2 of the phase compensation circuit 20A can be set to a small capacitance value. It is possible to configure the phase compensation circuit 20A capable of performing stable phase compensation without reducing the area and increasing the number of terminals. By including such a phase compensation circuit 20A, the switching power supply circuit 1A can effectively reduce the overall layout area.

Here, in the phase compensation circuit 20A shown in FIG. 2, a direct current is applied to the transistor MP4 on the input side of the second current mirror circuit CM2 by the current source I1 connected to the source of the transistor MN1. A voltage above the threshold is generated. This current does not cause any problem if it is smaller than the drain current of the transistor MN2. Increases proportionally with value. Therefore, if the value of m is set to a large value, the voltage of the SOUT terminal will not drop completely with respect to the triangular wave (or sawtooth wave) voltage to be compared by the comparator COMP1, and the comparator COMP1 will not be able to output a low on-duty signal. For example, the switching power supply circuit 1A may be difficult to operate stably. Such problems can be solved by a switching power supply circuit 1B according to a second embodiment described below.

(Second embodiment)
FIG. 3 is a circuit diagram showing a phase compensation circuit 20B included in the switching power supply circuit according to the second embodiment. The configuration of the switching power supply circuit according to the second embodiment, except for the phase compensation circuit 20B, is the same as that of the switching power supply circuit 1A according to the first embodiment described above, so detailed description thereof will be omitted here.

The phase compensation circuit 20B of the second embodiment further includes a third current mirror circuit CM3, unlike the phase compensation circuit 20A (see FIG. 2). The third current mirror circuit CM3 comprises transistors MN3, MN4 and MN5. More specifically, the transistor MN3 has its gate and drain connected to the second current source I2, and its source connected to the ground point GND. The transistor MN4 has its gate connected to the second current source I2, its source connected to the ground point GND, and its drain connected to the node provided between the source of the transistor MN1 and the second capacitor C2. be. The transistor MN5 has its gate connected to the gates of the transistors MN3 and MN4, its source connected to the ground point GND, and its drain connected to the SOUT terminal. Here, the ratio of the input (drain current of the transistor MN3) and the output (drain current of the transistor MN5) of the third current mirror circuit CM3 is the same as the drain current ratio of the transistors MP4 and MP5 of the second current mirror circuit CM2. set to

In this circuit configuration, the third current mirror circuit CM3 sinks a current m times as large as the current source I2 from the SOUT terminal through the transistor MN5, thereby canceling the aforementioned DC bias. As a result, even when the value of m is set large, the operation of the switching power supply circuit 1A can be stably maintained.

Here, in the phase compensation circuit 20A described above (similar to the phase compensation circuit 20B), the voltage at the SOUT terminal does not change until the voltage at the SIN terminal reaches the threshold voltage Vthn of the transistors MN1 and MN2. Therefore, when the switching power supply circuit is started, unless the voltage of the SIN terminal (EOUT terminal) increases from 0 V to the threshold voltage Vthn of the transistors MN1 and MN2, the first current mirror circuit CM1 and the second current mirror circuit CM2 do not operate. The output voltage of SOUT remains at 0 V, and after that, the voltage of the SIN terminal increases to the threshold voltage Vthn of the transistors MN1 and MN2, and finally the output voltage of the SOUT terminal increases. Therefore, it takes time for the output transistor MP1 to start the switching operation.

The triangular wave (or sawtooth wave) voltage input to the inverting input terminal 10 of the comparator COMP1 in FIG. have In particular, this triangular wave (or sawtooth wave) voltage always exceeds VOSCL because the output transistor MP1 does not turn ON when the voltage at the SOUT terminal becomes 0V. As a result, the voltage V _EOSW at which the voltage of the EOUT terminal rises from 0 V when the switching power supply circuit 1A is started in FIG. It is represented as follows.

As shown in FIG. 1, a first capacitor CEO for phase compensation is connected to the EOUT terminal. Therefore, when the switching power supply circuit 1A is started, it takes time for the error amplifier AMP1 to charge the first capacitor CEO until the voltage of the EOUT terminal rises from 0V and reaches the voltage _VEOSW , and the voltage of the VOUT terminal becomes regulated. There is a lag time before the value is reached. In order to shorten such a delay time, it is necessary to shorten the time required for the output transistor MP1 to start switching operation. Such problems can be preferably solved by a switching power supply circuit 1C according to a third embodiment described below.

(Third Embodiment)
FIG. 5 is a circuit diagram of a switching power supply circuit 1C according to the third embodiment, and FIG. 6 is a circuit diagram showing a phase compensation circuit 20C of FIG.

The switching power supply circuit 1C further includes a charging circuit 30 for charging the first capacitor CEO at startup. The charging circuit 30 comprises transistors MP6 and MP7. More specifically, the transistor MP6 has its gate connected to the CONT terminal, its source connected to the third current source I3, and its drain connected to the SIN terminal. The transistor MP7 has a gate connected to the CONT terminal, a source connected to the third current source I3, and a drain connected to the drain of the transistor MN1.

The output voltage of the latch circuit 24 is input to the charging circuit 30 from the CONT terminal. The output voltage of the latch circuit 24 is Low at startup, and the transistors MP6 and MP7 are turned on. At this time, the current source I3 applies the charging current Ic (see FIG. 5) from the SIN terminal to the first capacitor CEO via the transistor MP6.

The first capacitor CEO is gradually charged by the charging current Ic from the current source I3, and the voltage of the EOUT terminal increases with time. Then, when the SOUT terminal voltage reaches VOCSL, the output voltage of the comparator COMP1 switches from High to Low, and the switching operation of the output transistor MP1 starts. At this time, the voltage of the output terminal 12 of the comparator COMP1 is also input to the IN terminal of the latch circuit 24, and at the timing when the switching operation starts, the output of the OUT terminal of the latch circuit 24 is switched from Low to High, and after that, is in the High state. is retained. When the output voltage of the latch circuit 24 becomes High in this manner, the transistors MP6 and MP7 of the charging circuit 30 are turned off, and the charging of the first capacitor CEO ends.

Thus, in this embodiment, the first capacitor CEO is charged by the charging circuit 30 when the switching power supply circuit 1C is activated. Further, the charging circuit 30 determines completion of charging on the condition that the switching operation of the output transistor MP1 is detected, and terminates the charging operation of the first capacitor CEO. As a result, the time required for the output transistor MP1 to start the switching operation can be effectively shortened. After charging the first capacitor CEO by the charging circuit 30 is completed, the phase compensation circuit 20C performs phase compensation in the same manner as the phase compensation circuits 20A and 20B described above.

The charging circuit 30 of this embodiment is incorporated in the phase compensation circuit 20C, as shown in FIG. As a result, the charging circuit 30 can be mounted in the switching power supply circuit 1C in an efficient layout while suppressing complication of the circuit configuration of the switching power supply circuit 1C. Although FIG. 6 illustrates the case where the charging circuit 30 is built in the phase compensation circuit 20C, the charging circuit 30 may be installed in the switching power supply circuit 1C as a separate configuration from the phase compensation circuit 20C. For example, it may be incorporated in other configurations such as the error amplifier AMP1.

Here, in order to shorten the charging time of the first capacitor CEO by the charging circuit 30, the output current value of the current source I3 should be set large. The voltage applied to C2 also increases sharply. Then, the drain current of the transistor MP5 forming the second current mirror circuit CM2 temporarily increases, and the voltage of the SOUT terminal also increases, which may cause a so-called overshoot. Such an overshoot may cause the output of the error amplifier AMP1 to switch to High before the output voltage of the EOUT terminal rises sufficiently, and the transistor MP6 to switch to the OFF state, thereby terminating the charging of the EOUT terminal. be.

In order to solve such a problem, the phase compensation circuit 20C of this embodiment is designed so that the output current from the second current mirror circuit CM2 is cut off while the charging circuit 30 is charging the first capacitor CEO. configured to Specifically, the transistor MP7 deactivates the second current mirror circuit CM2 including the transistors MP4 and MP5 while charging the first capacitor CEO at start-up. At the same time, the transistor MN6, having its gate connected to the CONT terminal, stops the drain current of the transistor MN5 by turning off the transistor MN6 while charging the first capacitor CEO. This also prevents the charging current from the current source I3 from stopping while the first capacitor CEO is being charged.

As described above, according to each of the above embodiments, there is no need to perform phase compensation in the feedback circuit 15 (see FIG. 7). It is possible to realize a switching power supply circuit capable of performing phase compensation. Especially in the phase compensation circuit, since the current flowing through the second capacitor C2 can be increased by the second current mirror circuit CM2, the capacitance value of the second capacitor C2 can be small, and the layout area on the integrated circuit can be effectively reduced. can be reduced. Taking advantage of such characteristics, it is possible to provide a switching power supply circuit capable of performing stable phase compensation with a small number of terminals.

In addition, it is possible to appropriately replace the components in the above-described embodiments with well-known components without departing from the scope of the present disclosure, and the above-described embodiments may be combined as appropriate.

The contents described in each of the above embodiments are understood as follows, for example.

(1) A switching power supply circuit according to one aspect includes:
A switching power supply circuit (for example, the above-mentioned The switching power supply circuits 1A, 1B, 1C) of the embodiment,
A first capacitor (for example, the first capacitor CEO in the above embodiment) is connected to the output terminal, and the difference between the output detection voltage and the reference voltage, which varies linearly or nonlinearly according to the voltage applied to the load. an error amplifier (for example, the error amplifier AMP1 in the above embodiment) capable of outputting a signal based on from the output terminal;
an oscillation circuit capable of generating a triangular wave voltage having a constant period (for example, the oscillation circuit 7 of the above embodiment);
a comparator (for example, the comparator COMP1 of the above embodiment) capable of controlling the switching operation of the switching element by comparing the output voltage of the error amplifier and the triangular wave voltage of the oscillation circuit;
a phase compensation circuit (for example, the phase compensation circuits 20A, 20B, and 20C of the above embodiments) inserted between the output terminal of the error amplifier and the input terminal of the comparator;
with
The phase compensation circuit is
a first resistor (for example, the first resistor R1 in the above embodiment) for converting the output voltage of the error amplifier into a first current signal;
a second capacitor (for example, the second capacitor C2 in the above embodiment) for converting the output voltage of the error amplifier into a second current signal;
A first current mirror circuit (for example, the first current mirror circuit CM1 in the above embodiment) and a second current mirror circuit (for example, the second current mirror in the above embodiment) to which the first current signal and the second current signal are input, respectively circuit CM2); and
a second resistor (for example, the second resistor R2 in the above embodiment) for receiving the output currents of the first current mirror circuit and the second current mirror circuit and generating an output voltage for the input terminal of the comparator; ,
Prepare.

According to the above aspect (1), it is possible to reduce the layout area of the second capacitor for phase compensation and configure a phase compensation circuit capable of performing stable phase compensation without increasing the number of terminals.

(2) In another aspect, in the aspect of (1) above,
The phase compensation circuit further includes a current source (for example, the current source I3 in the above embodiment) capable of supplying a current for canceling the DC component from the output current of the second current mirror circuit.

According to the aspect (2) above, even when the gate aspect ratio of the transistor included in the second current mirror circuit is set large, the switching operation can be stably ensured in the switching power supply circuit.

(3) In another aspect, in the above aspect (1) or (2),
A charging circuit (for example, the charging circuit 30 of the above embodiment) is further provided for charging the first capacitor at startup.

According to the aspect (3) above, by charging the first capacitor with the charging circuit when the switching power supply circuit is activated, the time required for the output transistor to start switching operation can be effectively shortened.

(4) In another aspect, in the aspect of (3) above,
When the switching operation is detected, the charging operation of the first capacitor by the charging circuit is terminated.

According to the above aspect (4), by ending the charging operation of the first capacitor when the switching operation of the output transistor is started, the switching operation of the output transistor can be performed quickly while suppressing wasteful power consumption. can start at

(5) In another aspect, in the above (3) or (4) aspect,
The charging circuit is built in the phase compensation circuit.

According to the above aspect (5), it is possible to mount the charging circuit in the switching power supply circuit in an efficient layout while suppressing complication of the circuit configuration of the switching power supply circuit.

(6) In another aspect, in the aspect of (5) above,
The second current mirror circuit is configured such that output current from the second current mirror circuit is interrupted while the first capacitor is being charged by the charging circuit.

According to the aspect (6) above, even when the charging current is set large in order to shorten the charging time of the first capacitor by the charging circuit, the output voltage of the phase compensation circuit is prevented from overshooting. can be effectively prevented.

1 switching power supply circuit 7 oscillation circuit 10 phase compensation circuit 14 gate drive circuit 15 feedback circuit 16 output section 24 latch circuit 30 charging circuit AMP1 error amplifier COMP1 comparator CEO first capacitor C2 second capacitor CM1 first current mirror circuit CM2 second current mirror circuit CM3 third current mirror circuit I1, I2, I3 current source

Claims (6)

A switching power supply circuit capable of supplying power from the power supply circuit to a load such that the voltage applied to the load becomes a predetermined value by switching operation of a switching element,
A first capacitor is connected to the output terminal, and an error capable of outputting from the output terminal a signal based on the difference between the output detection voltage and the reference voltage that linearly or nonlinearly changes according to the voltage applied to the load. an amplifier;
an oscillation circuit capable of generating a triangular wave voltage having a constant period;
a comparator capable of controlling the switching operation of the switching element by comparing the output voltage of the error amplifier and the triangular wave voltage of the oscillation circuit;
a phase compensation circuit inserted between the output terminal of the error amplifier and the input terminal of the comparator;
with
The phase compensation circuit is
a first resistor for converting the output voltage of the error amplifier into a first current signal;
a second capacitor for converting the output voltage of the error amplifier into a second current signal;
a first current mirror circuit and a second current mirror circuit to which the first current signal and the second current signal are input, respectively;
a second resistor receiving the output currents of the first current mirror circuit and the second current mirror circuit and generating an output voltage for the input terminal of the comparator;
A switching power supply circuit. 2. The switching power supply circuit according to claim 1, wherein said phase compensation circuit further comprises a current source capable of supplying a current for canceling a DC component from the output current of said second current mirror circuit. 3. The switching power supply circuit according to claim 1, further comprising a charging circuit for charging said first capacitor at startup. 4. The switching power supply circuit according to claim 3, wherein the charging operation of said first capacitor by said charging circuit is terminated when said switching operation is detected. 5. The switching power supply circuit according to claim 3, wherein said charging circuit is incorporated in said phase compensation circuit. 6. The switching of claim 5, wherein said second current mirror circuit is configured such that output current from said second current mirror circuit is blocked while said first capacitor is being charged by said charging circuit. power circuit.

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