JP2022171076A - Transimpedance amplifier circuit - Google Patents

Abstract

To provide a transimpedance amplifier circuit that prevents fluctuations of an AGC band due to amplitude setting.SOLUTION: A transimpedance amplifier circuit comprises: an amplifier circuit that amplifies an input current signal and converts it into a voltage signal according to a gain set according to a control signal; and a gain control circuit that generates the control signal according to the amplitude of the voltage signal. The gain control circuit includes a detection circuit that generates an amplitude detection signal according to the amplitude of the voltage signal, a setting circuit that generates an amplitude reference signal according to a reference voltage, a voltage control current source circuit that generates a differential current signal based on a differential voltage in which the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal is corrected according to an output amplitude setting signal, and a variable capacitance circuit that is connected with output of the voltage control current source circuit, has a capacitance value set according to the output amplitude setting signal, and is charged and discharged according to the differential current signal. The gain control circuit generates the control signal according to a charging voltage of the variable capacitance circuit.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to transimpedance amplifier circuits.

2. Description of the Related Art In an optical transmission system, a wavelength division multiplexing system is known in which optical signals obtained by multiplexing a plurality of optical signals having different wavelengths are transmitted and received using two optical fibers. A coherent reception system is also known as a technique for efficiently receiving multiplexed optical signals. For example, in an optical receiver that receives one of a plurality of optical signals (single optical signal), an amplifier circuit that amplifies a current signal converted from the single optical signal includes a transimpedance amplifier and a gain of the transimpedance amplifier. and an AGC (Auto Gain Control) circuit for variably controlling the amplitude of the amplified signal. This type of amplifier circuit has a wide input dynamic range and is capable of outputting a linear output signal due to the variable gain function of the AGC circuit.

WO2015/004828 JP 2015-220567 A JP 2015-084474 A JP 2011-217226 A

For example, when a setting signal for setting the amplitude of an output signal output from an amplifier circuit is supplied to the AGC circuit, the loop gain and AGC band of the AGC circuit may fluctuate according to the set amplitude. Here, the AGC band is obtained as a frequency when the gain of the loop gain characteristic of the AGC loop is "1" (0 dB in decibels).

Accordingly, an object of the present disclosure is to provide a transimpedance amplifier circuit that suppresses fluctuations in the AGC band due to amplitude setting.

A transimpedance amplifier circuit of the present disclosure includes an amplifier circuit that amplifies an input current signal according to a gain set by a control signal and converts it into a voltage signal, and a gain that generates the control signal according to the amplitude of the voltage signal. a control circuit, wherein the gain control circuit includes a detection circuit that generates an amplitude detection signal according to the amplitude of the voltage signal; a setting circuit that generates an amplitude reference signal according to a reference voltage; a voltage controlled current source circuit for generating a differential current signal based on a differential voltage in which the difference between the voltage and the voltage of the amplitude reference signal is corrected according to the output amplitude setting signal; and connected to the output of the voltage controlled current source circuit. and a variable capacitance circuit which has a capacitance value set according to the output amplitude setting signal and is charged and discharged by the differential current signal, wherein the gain control circuit is controlled by the charging voltage of the variable capacitance circuit. The control signal is generated in response.

According to the present disclosure, it is possible to provide a transimpedance amplifier circuit that suppresses fluctuations in the AGC band due to amplitude setting.

FIG. 1 is a block diagram showing an example of a configuration of a transimpedance amplifier circuit according to a first embodiment; FIG. FIG. 2 is a circuit diagram showing an example of the AGC control circuit of FIG. FIG. 3 is an explanatory diagram showing an example of capacitance value setting by the thermocode generator in FIG. 4 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal in the AGC control circuit of FIG. 2. FIG. FIG. 5 is a characteristic diagram showing the characteristic shown in FIG. 4 as an AGC band with respect to the output amplitude. FIG. 6 is a circuit diagram showing another configuration example of the AGC control circuit mounted on the transimpedance amplifier circuit of FIG. 7 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal in the AGC control circuit of FIG. 6. FIG. FIG. 8 is a characteristic diagram showing the characteristic shown in FIG. 7 as an AGC band with respect to the output amplitude. FIG. 9 is a characteristic diagram showing the relationship between the output amplitude of the transimpedance amplifier circuit and the amplitude detection signal when the feedback function of the AGC control circuit of FIG. 2 or 6 is disabled.

[Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure are listed and described.

[1] A transimpedance amplifier circuit according to an aspect of the present disclosure includes an amplifier circuit that amplifies an input current signal according to a gain set by a control signal and converts it into a voltage signal, and according to the amplitude of the voltage signal, a gain control circuit that generates the control signal, wherein the gain control circuit includes a detection circuit that generates an amplitude detection signal according to the amplitude of the voltage signal; and a setting circuit that generates an amplitude reference signal according to the reference voltage. a voltage controlled current source circuit for generating a differential current signal based on the differential voltage obtained by correcting the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal according to the output amplitude setting signal; a variable capacitance circuit that is connected to the output of the current source circuit, has a capacitance value set according to the output amplitude setting signal, and is charged and discharged by the differential current signal; The control signal is generated according to the charging voltage of the variable capacitance circuit.

In this transimpedance amplifier circuit, the AGC band can be made constant regardless of the magnitude of the amplitude of the set voltage signal. That is, it is possible to provide the transimpedance amplifier circuit 100 that suppresses fluctuations in the AGC band due to amplitude setting.

[2] In [1] above, the gain control circuit includes a switch control section that generates a switch control signal according to the output amplitude setting signal, and the variable capacitance circuit is switched on and off according to the switch control signal. a plurality of capacitive elements connected to the output of the voltage-controlled current source circuit via respective switches, and the switch controller controls the voltage-controlled current source circuit as the amplitude indicated by the output amplitude setting signal increases. The switch control signal may be generated to increase the number of the capacitive elements connected to the output of. As a result, the charge accumulated in the output node of the voltage-controlled current source circuit can be changed according to the set amplitude, and the fluctuation of the AGC band due to the amplitude setting can be compensated.

[3] In [2] above, when the digital value of the output amplitude setting signal increases by one, the switch control unit turns on only one of the switches for connecting/disconnecting the plurality of capacitive elements, which is in an off state. The switch control signal may be generated to enable the state. As a result, a capacitance value corresponding to the output amplitude setting signal can be set to the output of the voltage controlled current source circuit by a simple means.

[4] In any one of [1] to [3] above, the gain control circuit further includes a current generator that generates an offset current corresponding to the value indicated by the output amplitude setting signal, and the amplitude detection signal. and a differential amplifier circuit that differentially amplifies the amplitude setting signal and adds a voltage corresponding to the offset current to the voltage obtained by amplifying the amplitude detection signal. Thereby, the offset voltage corresponding to the amplitude indicated by the output amplitude setting signal can be reflected in the output of the differential amplifier circuit, and the amplitude of the voltage signal can be set to the amplitude indicated by the output amplitude setting signal.

[Details of the embodiment of the present disclosure]
A specific example of the transimpedance amplifier circuit of the present disclosure will be described below with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference numerals, and descriptions thereof may be omitted. Further, the symbols of the input terminal, output terminal and each node are also used as symbols indicating signals, voltages or currents.

[First Embodiment]
[Circuit configuration of transimpedance amplifier circuit]
FIG. 1 is a block diagram showing an example of a configuration of a transimpedance amplifier circuit according to a first embodiment; FIG. The transimpedance amplifier circuit 100 shown in FIG. 1 has a TIA (TransImpedance Amplifier) 10, a VGA (Variable Gain Amplifier) 20, a BUF (buffer) 30, a CML (Current Mode Logic) 40, and an AGC control circuit 50.

For example, the transimpedance amplifier circuit 100 is used in a coherent optical receiver that receives optical signals, and receives differential current signals converted from single-wavelength optical signals by photodiodes at input terminals InP and InN. The transimpedance amplifier circuit 100 amplifies the received current signal and outputs it as a differential voltage signal from output terminals OutP and OutN. The voltage signals output from the output terminals OutP and OutN are output to a signal processing circuit such as a DSP (Digital Signal Processor), for example.

The TIA 10 converts differential input current signals received at the input terminals InP and InN into voltage signals and outputs the voltage signals to the VGA 20 . For example, the gain of TIA 10 changes according to control signal CNTL 1 received from AGC control circuit 50 . Since the gain of the TIA 10 converts current into voltage, the unit is expressed as impedance, for example, 1000Ω. The TIA 10 has, for example, an INV (INVerting amplifier) 11 and resistance elements R11 and R12. For example, INV11 is an example of an inverting amplifier circuit that amplifies a differential signal.

INV 11, for example, inverts and amplifies the differential voltage signal input between the non-inverting input terminal and the inverting input terminal, and outputs the inverted and amplified differential voltage signal from the inverting output terminal and the non-inverting output terminal. do. The resistance element R11 is connected, for example, between the non-inverting input terminal of INV11 and the inverting output terminal of INV11. The resistive element R12 is connected, for example, between the inverting input terminal of INV11 and the non-inverting output terminal of INV11. The gain of the TIA 10 changes according to the control signal CNTL1. The TIA 10 may be changed by using variable resistance elements as the resistance elements R11 and R12 and changing the resistance values of the resistance elements R11 and R12 according to the control signal CNTL1.

VGA 20 amplifies the differential voltage signal received from TIA 10 and outputs it to BUF 30 . For example, the gain of VGA 20 changes according to control signals CNTL2, CNTL3 and CNTL4 received from AGC control circuit 50. FIG. For example, the VGA 20 performs non-inverting amplification, but may perform inverting amplification to invert the logic of the differential voltage signal to be output. By the way, the differential voltage signal is composed of a positive phase signal (positive phase component) and a negative phase signal (negative phase component). The positive-phase signal and the negative-phase signal are 180 degrees out of phase with each other and form a pair of complementary signals.

For example, when the voltage of the positive phase signal increases, the voltage of the negative phase signal decreases, and when the voltage of the positive phase signal decreases, the voltage of the negative phase signal increases. Further, when the positive phase signal reaches the peak value, the negative phase signal reaches the bottom value, and when the positive phase signal reaches the bottom value, the negative phase signal reaches the peak value. The positive phase signal and negative phase signal preferably have the same amplitude and the same average value (DC component). The logic of the differential voltage signal can be inverted by interchanging the pair of positive-phase signal and negative-phase signal. Therefore, in a circuit that amplifies a differential voltage signal, switching between non-inverting amplification and inverting amplification can be easily performed by changing the connection between the positive-phase signal wiring and the negative-phase signal wiring. The VGA 20 may be included in the TIA 10 to amplify differential voltage signals output from the TIA 10 .

BUF 30 outputs voltage signals IP and IN obtained by amplifying differential voltage signals received from VGA 20 to AGC control circuit 50 and CML 40 . The CML 40 outputs voltage signals obtained by amplifying the voltage signals IP and IN to output terminals OutP and OutN. The voltage signals IP, IN and the voltage signals output to the output terminals OutP, OutN are all differential voltage signals (hereinafter referred to as differential voltage signals). For example, the voltage signal IP is a positive phase signal of the differential voltage signal, and the voltage signal IN is a negative phase signal of the differential voltage signal. For example, if the voltage gain of the VGA 20 is sufficiently large and the driving capability is also sufficiently large, the BUF 30 may be omitted and the VGA 20 may supply the differential voltage signals IP and IN.

AGC control circuit 50 outputs control signals CNTL1-CNTL4 that adjust the gains of TIA 10 and VGA 20 in order to set the amplitude of differential voltage signals IP, IN received from BUF 30 to the amplitude indicated by output amplitude setting signal OA. Generate. AGC control circuit 50 is an example of a gain control circuit. An example of AGC control circuit 50 is shown in FIG. The amplitudes of the differential voltage signals IP and IN are controlled by the AGC control circuit 50. For example, when the CML 40 performs linear amplification with a constant gain, the amplitudes of the differential voltage signals IP and IN are controlled to be constant. By doing so, the amplitude of the differential voltage signal output from the output terminals OutP and OutN can be kept constant.

[Circuit Configuration of AGC Control Circuit]
FIG. 2 is a circuit diagram showing an example of the AGC control circuit 50 of FIG. AGC control circuit 50 has bipolar transistors Q1P and Q1N that receive differential voltage signals IP and IN output from BUF 30 in FIG. For example, the bipolar transistor Q1P receives the positive phase signal IP of the differential voltage signals IP and IN, and the bipolar transistor Q1N receives the negative phase signal IN of the differential voltage signals IP and IN. The AGC control circuit 50 also has a current source I51 and a resistive element R51 connected to the emitters of the bipolar transistors Q1P and Q1N, and a capacitive element C51 connected to the resistive element R51. Bipolar transistors Q1P and Q1N have the same electrical characteristics, for example, within the allowable range of manufacturing variations.

In the following, bipolar transistors are also simply referred to as transistors. Transistors Q1P and Q1N, current source I51, resistive element R51 and capacitive element C51 function as a detection circuit that detects the amplitude of voltage signals IP and IN. Amplitude detection signal PH set to a voltage corresponding to the amplitude detected by the detection circuit is output to the gate of p-channel MOS transistor M1P of the differential amplifier circuit. The resistance element R51 and the capacitance element C51 form a low-pass filter, and the amplitude detection signal PH is averaged and output from the connection node between the resistance element R51 and the capacitance element C51. For example, when the amplitudes of the differential voltage signals IP and IN are constant, the amplitude detection signal PH becomes a DC signal having a voltage value corresponding to the magnitude of the amplitude. In the following, p-channel MOS transistors are also simply referred to as transistors.

AGC control circuit 50 also has a bipolar transistor Q2 receiving reference voltage Vref, current source I52 and resistance element R52 connected to the emitter of transistor Q2, and capacitance element C52. Transistor Q2, current source I52, resistive element R52, and capacitive element C52 have the same circuit configuration as a detection circuit for detecting the amplitude of voltage signals IP and IN, and for example, detect the electrical characteristics and size of each circuit element. The same is true within the allowable range of electrical characteristics and size of each circuit element of the circuit and manufacturing variations.

For example, the reference voltage Vref is set to the center voltage of the amplitudes of the differential voltage signals IP and IN. The center voltage of the amplitude of the differential voltage signals IP, IN is equal to the temporal average value (DC component) of each voltage signal. The reference voltage Vref may be an average value obtained by applying the voltage signals IP and IN output from the BUF 30 in FIG. For example, a voltage signal IP is applied to one end of a series resistance circuit composed of two resistors, a voltage signal IN is applied to the other end of the series resistance circuit, and the voltage at the midpoint where the two resistors are connected is used as the reference voltage Vref. may

Transistor Q2, current source I52, resistance element R52, and capacitance element C52 function as a setting circuit that converts the level of reference voltage Vref and generates the level-converted voltage as amplitude reference signal AH. Amplitude reference signal AH is output to the gate of p-channel MOS transistor M1N of the differential amplifier circuit. Resistance element R52 and capacitance element C52 form a low-pass filter, and level-converted reference voltage Vref is stabilized and output from a connection node between resistance element R52 and capacitance element C52. For example, the amplitude reference signal AH becomes a DC signal having a voltage value corresponding to the reference voltage Vref. Thus, the amplitude detection signal PH and the amplitude reference signal AH are each output as a DC signal to the differential amplifier circuit. For example, transistors Q1P, Q1N, Q2 are heterojunction bipolar transistors.

The differential amplifier circuit has, for example, transistors M1P and M1N, a current source I53 connected to the sources of the transistors M1P and M1N, and resistive elements R53, R54, R55 and R56. Resistance elements R53 and R54 are connected in series between the drain of transistor M1P and ground line GND. Resistance elements R55 and R56 are connected in series between the drain of transistor M1N and ground line GND. For example, the resistance values of the resistance elements R53 and R55 are the same within the allowable range of manufacturing variations, and the resistance values of the resistance elements R54 and R56 are the same within the allowable range of manufacturing variations. be. The transistors M1P and M1N have the same electrical characteristics, for example, within the allowable range of manufacturing variations.

A connection node between the resistance elements R53 and R54 receives an offset current Ioffset from a DAC (Digital-to-Analog Converter) 52 . As a result, an offset voltage corresponding to the product of the offset current Ioffset and the resistance value of the resistance element R54 is added to the drain voltage of the transistor M1P based on the ground potential.

DAC 52 generates offset current Ioffset corresponding to the digital value indicated by output amplitude setting signal OA. For example, the current value of the offset current Ioffset increases as the digital value of the output amplitude setting signal OA increases. The output amplitude setting signal OA is provided from outside the transimpedance amplifier circuit 100, for example. The DAC 52 is an example of a current generator that generates an offset current Ioffset according to the digital value indicated by the output amplitude setting signal OA.

For example, the digital value of the output amplitude setting signal OA is set to a small value when the set amplitude is small, and is set to a large value when the set amplitude is large. Although FIG. 2 shows an example in which the digital value A of the output amplitude setting signal OA is two digits in binary (A[1:0]), the digital value A may be one or more digits in binary.

For example, when the set amplitude is relatively small, the DAC 52 receives the output amplitude setting signal OA with a relatively small value and outputs a relatively small offset current Ioffset. When the set amplitude is relatively large, the DAC 52 receives a relatively large output amplitude setting signal OA and outputs a relatively large offset current Ioffset. The DAC 52 is, for example, a current DAC (IDAC) that outputs current.

The differential amplifier circuit outputs differential voltage signals VIN and VIP generated according to the voltage of the amplitude detection signal PH, the voltage of the amplitude reference signal AH, and the offset current Ioffset from the drains of the transistors M1P and M1N. do. The differential amplifier circuit and DAC 52 are an example of a differential voltage generation circuit that generates a differential signal by correcting the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal according to the output amplitude setting signal OA. For the correction according to the output amplitude setting signal OA, for example, as described above, an offset voltage corresponding to the product of the offset current Ioffset and the resistance value of the resistance element R54 is added to one voltage of the generated differential signal. is done.

The differential voltage signals VIP and VIN are supplied to differential inputs of an OTA (Operational Transconductance Amplifier) 51 . By supplying the differential voltage signals VIP and VIN to the OTA 51, the SN (Signal to Noise) ratio can be improved compared to the case where the amplitude detection signal PH and the amplitude reference signal AH are directly supplied to the OTA 51. The accuracy of functions can be improved. By adding the offset voltage due to the offset current Ioffset to one of the differential voltage signals VIP and VIN (negative phase signal) VIN, the voltage value of the voltage signal VIP and the voltage value of the voltage signal VIN are equal to each other. When equal, the amplitudes of the differential voltage signals IP, IN can be set equal to the amplitude value set by the output amplitude setting signal OA.

The OTA 51 outputs a differential current signal from its output node according to the differential voltage signals VIN and VIP. The OTA 51 is an example of a voltage controlled current source circuit. For example, the OTA 51 outputs a current (differential current signal) corresponding to the difference voltage between the voltage of the voltage signal VIP and the voltage of the voltage signal VIN. For example, the larger the voltage value of the voltage signal VIP than the voltage signal VIN, the smaller the differential current signal, and the smaller the voltage value of the voltage signal VIP than the voltage value of the voltage signal VIN, the larger the differential current signal. For example, when the voltage value of voltage signal VIP is the same as the voltage value of voltage signal VIN, the differential current signal is zero. The output node of the OTA 51 is connected to the capacitive element C2,1, and is connected to the capacitive elements C2,2, . The n capacitive elements C2,1, C2,2, . . . , C2,n will be referred to as capacitive element C2 in the following description.

The OTA 51 functions as an integration circuit together with the capacitive element C2 connected to the output of the OTA 51, and generates a voltage at the output node according to the differential current signal output from the OTA 51 and the capacitance value of the capacitive element C2. The time constant due to the output impedance of the OTA 51 and the capacitive element C2 forms the main pole of the gain characteristic of the AGC loop. In the following, the symbols C2,1, C2,2, etc. are also used as the capacitance values of the capacitive elements C2,1, C2,2, respectively. The AGC loop in the first embodiment includes a TIA 10 that changes the gain according to the control signal CNTL1, a VGA 20 that changes the gain according to the control signals CNTL2-CNTL4, a BUF 30, differential voltage signals IP, IN is input to generate control signals CNTL1-CNTL4.

The switching (on/off) of each switch SW is controlled by the thermocode generator 53 . The thermo-code generator 53 generates an output signal X[2:0], which is a thermo-code, according to the digital value A[1:0] of the output amplitude setting signal OA, as illustrated in the truth table in the drawing. Output. Thereby, the number of capacitive elements C2 connected to the output node of the OTA 51 can be increased by one each time the logical value of the output amplitude setting signal OA increases. Therefore, the capacitance value of the output node of OTA 51 can be easily set according to the logical value of output amplitude setting signal OA.

More specifically, when the number of binary digits of the digital value A is m (m is an integer of 2 or more), the number of output signals X corresponding to the digital value A [m-1:0] is 2 ^m -1 becomes. In the thermocode, the number of switches SW to be turned on increases by one as the digital value A increases by one. Therefore, when the digital value A increases or decreases by 1, only one switch SW is turned on/off accordingly, and the capacitance value of the capacitance element C2 is monotonically controlled without being affected by the timing of the output signal X. can be increased or decreased to For example, when controlling two switches SW at the same time without using a thermocode, specifically, one switch SW is turned from an off state to an on state and the other switch SW is turned from an on state to an off state. In this case, there is a possibility that the monotonous change of the charged voltage of the capacitive element C2 cannot be guaranteed due to the timing deviation of the respective output signals X. FIG. As a result, the control signals CNTL1-CNTL4 may not be generated properly.

The multiple switches SW and the multiple capacitive elements C2 are an example of a variable capacitance circuit that is charged and discharged by the differential current signal. The output signal X[2:0] is an example of a switch control signal that controls the switch SW. It is an example of a control unit.

The capacitive element C2 is set so as to compensate for fluctuations in the AGC band due to the amplitude setting indicated by the output amplitude setting signal OA. Therefore, as shown in FIG. 4, which will be described later, the AGC band of the AGC control circuit 50 can be made constant regardless of the setting of the output amplitude setting signal OA.

A gain control section 54 is connected to the output of the OTA 51 . Gain control unit 54 generates control signals CNTL1-CNTL4 for controlling the gains of TIA 10 and VGA 20 according to the charging voltage of capacitive element C2 connected to the output node of OTA 51. FIG.

For example, gain control section 54 generates control signals CNTL1-CNTL4 that increase the gains of TIA 10 and VGA 20 when the voltage of the output node of OTA 51 is relatively low. Gain control unit 54 generates control signals CNTL1-CNTL4 that reduce the gains of TIA 10 and VGA 20 when the voltage of the output node of OTA 51 is relatively high.

When amplitude detection signal PH and amplitude reference signal AH are constant, the voltage value of voltage signal VIN decreases as offset current Ioffset decreases, and the voltage value of voltage signal VIN increases as offset current Ioffset increases. The transimpedance amplifier circuit 100 operates so that the difference between the voltage value of the voltage signal VIP input to the OTA 51 and the voltage value of the voltage signal VIN becomes "0" due to the negative feedback of the AGC loop described above, and the offset current It operates to cancel the offset voltage due to Ioffset. As a result, it is possible to configure the AGC control circuit 50 capable of setting the amplitude by the digital value of the output amplitude setting signal OA.

[Capacitance value setting example]
FIG. 3 is an explanatory diagram showing a setting example of the capacitance value of the capacitive element C2 by the thermocode generator 53 of FIG. For example, as shown in FIG. 6, which will be described later, when a capacitive element C2 having a fixed capacitance value is connected to the output node of the OTA 51, the output amplitude of the differential voltage signal output from the output terminals OutP and OutN and the AGC band are The relationship is illustrated by FIG. Assume that the AGC band values of the four points in FIG. 8 are F1, F2, F3, and F4, respectively, and that F1 to F4 are adjusted to a constant band Ftarget regardless of the amplitude setting. For example, the band Ftarget is 300 kHz. In the following, the circuit of FIG. 6 will be referred to as the pre-compensation circuit and the circuit of FIG. 2 will be referred to as the post-compensation circuit.

If the parasitic capacitance of the output node of the OTA 51 is Cp (eg, 5 pF) and the capacitance value of the capacitive element C2 in FIG. 6 before compensation is C2F (eg, 12 pF), the capacitance value in the circuit before compensation is constant. (Cp+C2F). Here, the parasitic capacitance Cp is the output capacitance of the output node of the OTA 51, the input capacitance of the input to which the charging voltage of the capacitive element C2 of the gain control section 54 is input, the capacitance of the wiring connecting the OTA 51 and the gain control section 54, and the like. is the sum of The parasitic capacitance Cp is a fixed value determined according to the embodiment.

The AGC band becomes higher as the set output amplitude is larger, as shown in FIG. Therefore, in order to keep the AGC band constant, it is necessary to lower the AGC band by increasing the capacitance value of the capacitive element C2 as the set amplitude increases. The capacitance value of the capacitive element C2 and the AGC band are inversely proportional, and the parasitic capacitance Cp does not change before and after compensation. Therefore, the capacitance value Cn (n is a positive integer) after compensation for each output amplitude setting can be obtained by equation (1).

Cn=(C2F+Cp)・Fn/Ftarget−Cp (1)
In equation (1), Cn=C2F when the value of the AGC band Fn is equal to the constant band Ftarget. Also, when the value of the AGC band Fn is greater than the constant band Ftarget, Cn is greater than C2F, and when the value of the AGC band Fn is less than the constant band Ftarget, Cn is less than C2F.

FIG. 3 shows Cn calculated using equation (1). The four points in FIG. 3 respectively correspond to the four points in FIG. As shown below, the capacitance value Cn after compensation is obtained by adding the capacitance value C2,n to the capacitance value C(n-1) of the previous amplitude setting when n is greater than 2.

C2,1=C1
C2,2=C2-C2,1=C2-C1
C2,3=C3-(C2,1+C2,2)=C3-C2
...
C2,n=Cn-(C2,1+...+C2,(n-1))=Cn-C(n-1)

[Loop gain of the first embodiment]
FIG. 4 is a characteristic diagram showing an example of the loop gain of the AGC loop according to the amplitude setting by the output amplitude setting signal OA in the AGC control circuit 50 of FIG. FIG. 4 shows the characteristics of the AGC loop gain when the optical input signal power is constant (eg, -15 dBm).

The numbers at the end of the symbols OA_GC30, OA_GC120, OA_GC210, and OA_GC300 shown in FIG. It is supplied to the section 53 .

As described above, the AGC band can be determined as the frequency at which the gain is "1" (0 dB in decibels) in the loop gain characteristics of the AGC loop. For example, a suitable range for the AGC band is 100 kHz to 1 MHz. In this embodiment, the AGC band can be set to about 300 kHz regardless of the amplitude setting by changing the capacitance value of the capacitive element C2 connected to the output node of the OTA 51 according to the amplitude setting. 300 kHz is located near the center of the proper range of the AGC band, and desired communication performance can be secured even when the optical input signal power fluctuates.

FIG. 5 is a characteristic diagram showing the characteristic shown in FIG. 4 as an AGC band with respect to the output amplitude. As shown in FIG. 5, the AGC band can be kept substantially constant regardless of the amplitude set by the output amplitude setting signal OA.

As described above, in this embodiment, by changing the capacitance value of the capacitive element C2 connected to the output node of the OTA 51 according to the amplitude setting, the AGC band is made constant regardless of the magnitude of the set output amplitude. be able to. That is, it is possible to provide the transimpedance amplifier circuit 100 that suppresses fluctuations in the AGC band due to amplitude setting. As a result, sufficient communication performance can be ensured even when the optical input signal power fluctuates.

By connecting the capacitive element C2 to the output node of the OTA 51 via the switch SW that is switched on/off according to the output amplitude setting signal OA, the stored charge can be changed according to the set amplitude. This makes it possible to compensate for fluctuations in the AGC band due to amplitude setting. By generating the output signal X[2:0] indicating the thermocode corresponding to the output amplitude setting signal OA, the output signal X[2:0] is stable without being affected by the on/off timing of the output signal X[2:0]. , a capacitance value corresponding to the output amplitude setting signal OA can be set to the output of the OTA 51 .

By supplying the offset current Ioffset to the connection node of the resistance elements R53 and R54 of the differential amplifier circuit, the offset voltage corresponding to the amplitude indicated by the output amplitude setting signal OA can be reflected in the output of the differential amplifier circuit. . As a result, the amplitude of the differential voltage signals IP and IN can be set to the amplitude indicated by the output amplitude setting signal OA.

[Circuit configuration of another AGC control circuit]
FIG. 6 is a circuit diagram showing another configuration example of the AGC control circuit mounted in the transimpedance amplifier circuit 100 of FIG. Elements similar to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted. An AGC control circuit 50A shown in FIG. 6 is mounted in the transimpedance amplifier circuit 100 shown in FIG. 1 instead of the AGC control circuit 50 shown in FIG.

The AGC control circuit 50A eliminates the thermocode generator 53 and the switch SW from the AGC control circuit 50 of FIG. 2, and has a capacitive element C2 instead of the capacitive elements C2,1 to C2,n. Other configurations of the AGC control circuit 50A are the same as those of the AGC control circuit 50 of FIG. The AGC control circuit 50A operates in the same manner as the AGC control circuit 50 of FIG. 2 except that the capacitance value is not adjusted by the output amplitude setting signal OA.

[Loop gain of other AGC control circuits]
FIG. 7 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal OA in the AGC control circuit 50A of FIG. FIG. 7 corresponds to FIG. 4 and shows the characteristics of the AGC loop gain when the optical input signal power is kept constant (eg, -15 dBm).

If the capacitance value is not adjusted by the output amplitude setting signal OA, the AGC band fluctuates according to the set output amplitude. In FIG. 7, the AGC band varies from about 180 kHz to about 1 MHz, and the margin for the appropriate range of 100 kHz to 1 MHz is small. Therefore, if the optical input signal power fluctuates, there is a risk that desired communication performance cannot be ensured.

FIG. 8 is a characteristic diagram showing the characteristic shown in FIG. 7 as an AGC band with respect to the output amplitude. In FIG. 8, the AGC band fluctuates according to the amplitude set by the output amplitude setting signal OA.

[Characteristics when the feedback function is disabled]
FIG. 9 shows the output amplitude of the transimpedance amplifier circuit 100 when the negative feedback by the AGC control circuit of FIG. 2 or 6 is disabled, and the difference voltage PH-AH between the amplitude detection signal PH and the amplitude reference signal AH. It is a characteristic diagram showing a relationship. As shown in FIG. 9, when the negative feedback is disabled, the difference voltage PH-AH increases in a nonlinear and arcuate manner as the set amplitude increases. In the setting circuit of the AGC control circuit 50, when the reference voltage Vref is set to the average value of the differential voltage signals IP and IN, the differential voltage PH-AH is equal to the amplitude of the differential voltage signals IP and IN (peak to peak value). half).

By the way, the change in the AGC band shown in FIG. 8 occurs because the gain of the AGC loop fluctuates depending on the amplitude setting, and is mainly due to two causes. First, since the TIA 10 and VGA 20 are included in the AGC loop, the AGC loop gain fluctuates due to fluctuations in the gains of the TIA 10 and VGA 20 due to AGC control. The second reason is that the transistors Q1P and Q1N (for example, HBT) in FIGS. 2 and 6 have diode characteristics between the base and the emitter and thus have nonlinear characteristics with respect to the input. For example, the nonlinear relationship between the difference voltage PH-AH in FIG. 9 and the actual output amplitude is due to the nonlinear characteristics of the transistors Q1P and Q1N.

Although the embodiments and the like of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and the like. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These also naturally belong to the technical scope of the present disclosure.

10 TIAs
20 VGA
30 BUF
40 CML
50, 50A AGC control circuit 51 OTA
52 DACs
53 thermocode generation unit 54 gain control unit 100 transimpedance amplifier circuit AH amplitude reference signal C2 capacitive elements C51, C52 capacitive elements CNTL1-CNTL4 control signals I51, I52, I53 current sources InN, InP input terminals IN, IP voltage signal M1N, M1P Transistor OA Output amplitude setting signal OutN, OutP Output terminal PH Amplitude detection signal Q1N, Q1P Transistor Q2 Transistor R11, R12 Resistance element R51, R52, R53, R54, R55, R56 Resistance element SW Switch VIN, VIP Voltage signal Vref Reference voltage

Claims (4)

an amplifier circuit that amplifies an input current signal according to a gain set by a control signal and converts it into a voltage signal;
a gain control circuit that generates the control signal according to the amplitude of the voltage signal;
with
The gain control circuit is
a detection circuit that generates an amplitude detection signal according to the amplitude of the voltage signal;
a setting circuit that generates an amplitude reference signal in response to the reference voltage;
a voltage controlled current source circuit for generating a differential current signal based on a differential voltage obtained by correcting a difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal according to an output amplitude setting signal;
a variable capacitance circuit connected to the output of the voltage controlled current source circuit, having a capacitance value set according to the output amplitude setting signal, and charged and discharged by the differential current signal;
with
The gain control circuit generates the control signal according to the charging voltage of the variable capacitance circuit.
Transimpedance amplifier circuit. The gain control circuit is
A switch control unit that generates a switch control signal according to the output amplitude setting signal,
The variable capacitance circuit has a plurality of capacitive elements connected to the output of the voltage controlled current source circuit via switches that are switched on and off according to the switch control signal,
2. The switch control unit according to claim 1, wherein the switch control unit generates the switch control signal that increases the number of the capacitive elements connected to the output of the voltage controlled current source circuit as the amplitude indicated by the output amplitude setting signal increases. Transimpedance amplifier circuit. The switch control section controls the switch control signal such that, when the digital value of the output amplitude setting signal increases by one, only one of the switches for connecting and disconnecting the plurality of capacitive elements is turned on. 3. The transimpedance amplifier circuit of claim 2, wherein the transimpedance amplifier circuit generates The gain control circuit is
a current generator that generates an offset current corresponding to a value indicated by the output amplitude setting signal;
a differential amplifier circuit that differentially amplifies the amplitude detection signal and the amplitude reference signal and adds a voltage corresponding to the offset current to a voltage obtained by amplifying the amplitude detection signal;
comprising
4. A transimpedance amplifier circuit according to any one of claims 1 to 3.

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