JP2022170153A - multilayer wiring board - Google Patents

Abstract

To provide a multilayer wiring board which is excellent in insulation reliability.SOLUTION: A multilayer wiring board 12 has two or more layers 126 laminated with each other, wherein each of the two or more layers 126 includes: an insulating resin layer 1263 that has a first surface S1 and a second surface S2 as a back face of the first surface S1 and is provided with a groove part opened in the first surface S1; a conductor layer 1262 including a wiring part 1262W embedded with the groove part in the insulating resin layer 1263; a first metal-containing layer 1261a which does not cover the side face of the wiring part 1262W and covers the surface on the first surface S1 side of the wiring part 1262W; and a second metal-containing layer 1261b which includes a part interposed between the first metal-containing layer 1261a and the wiring part 1262W and a part covering side face of the wiring part 1262W, and is made of a metal material different from a material of the first metal-containing layer 1261a.SELECTED DRAWING: Figure 2

Description

The present invention relates to a multilayer wiring board.

In recent years, as semiconductor devices have become faster and more highly integrated, wiring substrates for flip chip-ball grid arrays on which semiconductor chips are mounted, ie, FC-BGA substrates, are also equipped with semiconductor chips. There is a demand for a narrower pitch of the connecting terminals used for bonding between the substrates and a finer wiring in the substrate. On the other hand, the connection between the FC-BGA substrate and the mother board is required to use connection terminals arranged at substantially the same pitch as in the past. Based on these demands, a technique of providing a multi-layer wiring board including fine wiring, also called an interposer, between the FC-BGA board and the semiconductor chip has been adopted.

One of them is silicon interposer technology. This silicon interposer technology manufactures an interposer by forming a multi-layered wiring structure in which each layer includes fine wiring on a silicon wafer using a semiconductor circuit manufacturing technology.

Also, a technique has been developed in which the multilayer wiring structure described above is not formed on a silicon wafer but directly built into an FC-BGA substrate. According to this technique, the multi-layered wiring structure is formed by chemical mechanical polishing (CMP) or the like in the manufacture of an FC-BGA substrate whose core layer is made of, for example, a glass epoxy substrate. This is disclosed in US Pat.

Further, an interposer is formed on a support such as a glass substrate, the interposer is bonded to the FC-BGA substrate, and then the support is peeled off from the interposer, thereby forming the above multilayer wiring structure on the FC-BGA substrate. There is also a method (hereinafter referred to as a transfer method) provided above. This is disclosed in Patent Document 2.

JP 2014-225671 A WO2018/047861

An object of the present invention is to provide a multilayer wiring board having excellent insulation reliability.

According to one aspect of the present invention, an insulating resin layer comprising two or more layers laminated to each other, each of the two or more layers having a first surface and a second surface that is the back surface thereof, an insulating resin layer provided with a groove portion opened on the first surface; a conductor layer including a wiring portion in which the groove portion of the insulating resin layer is embedded; and the wiring portion without covering the side surface of the wiring portion. a first metal-containing layer covering the surface of the first surface side of, a portion interposed between the first metal-containing layer and the wiring portion, and a portion covering the side surface of the wiring portion, A multilayer wiring board including a second metal-containing layer made of a metal material different from the material of the first metal-containing layer is provided.

According to still another aspect of the present invention, there is provided the multilayer wiring board according to the above aspect, wherein the insulating resin layers of each two adjacent layers of the two or more layers are in contact with each other.

According to still another aspect of the present invention, the insulating resin layer is integrally formed in the thickness direction, and the insulating resin layer has a first recess opening on the first surface and an opening on the second surface. A second recess communicating with one or more of the first recesses is further provided, and the conductor layer includes a land portion embedded in the first recess of the insulating resin layer and a land portion at the position of the land portion. a via portion protruding from the surface, the via portion filling a concave portion of another insulating resin layer adjacent to the first surface side, and the first metal-containing layer covering the side surface of the land portion. A multilayer wiring board according to any one of the above aspects is provided, in which the surface of the land portion on the first surface side and the side surface of the via portion are further covered.

Here, the fact that the insulating resin layer is "integrally formed in the thickness direction" means that the insulating resin layer does not have an interface intersecting the thickness direction. It means that it has a single layer structure. Even when a plurality of mutually laminated insulating layers are made of the same material, their interfaces can be confirmed by observing the cross section with an electron microscope such as a scanning electron microscope.

According to still another aspect of the present invention, there is provided the multilayer wiring board according to any one of the above aspects, wherein the insulating resin layer is made of a non-photosensitive resin.

According to still another aspect of the present invention, there is provided the multilayer wiring board according to any of the above aspects, wherein the first metal-containing layer contains titanium and the second metal-containing layer contains copper.

According to still another aspect of the present invention, the multilayer wiring board according to any one of the above aspects, wherein the portion of the second metal-containing layer covering the side surface of the wiring portion has an arithmetic mean roughness Ra of 10 nm or less. is provided.

According to still another aspect of the present invention, a first wiring board and a second wiring board bonded to the first wiring board are provided, and the first wiring board and the second wiring board have a bonding structure interposed therebetween. A composite wiring board is provided which is electrically connected to each other via electrodes, and wherein the second wiring board is a multilayer wiring board according to any of the above aspects.

According to still another aspect of the present invention, there is provided the composite wiring board according to the above aspect, wherein the first wiring board is a flip-chip ball grid array wiring board and the second wiring board is an interposer.

According to still another aspect of the present invention, a package includes a composite wiring board according to any one of the above aspects, and a functional device mounted on a surface of the second wiring board opposite to the first wiring board. A device is provided.

Here, the "functional device" is a device that operates by being supplied with at least one of electric power and electric signals, a device that outputs at least one of electric power and electric signals in response to an external stimulus, or a device that outputs at least one of electric power and electric signals. It is a device that operates when supplied with at least one of them and outputs at least one of electric power and electrical signals in response to stimulation from the outside. A functional device is in the form of a chip, for example, a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. A functional device can include, for example, one or more of a large scale integrated circuit (LSI), a memory, an imaging device, a light emitting device, and MEMS (Micro Electro Mechanical Systems). MEMS are, for example, one or more of pressure sensors, acceleration sensors, gyro sensors, tilt sensors, microphones, and acoustic sensors. According to one example, the functional device is a semiconductor chip including an LSI.

According to yet another aspect of the present invention, the method includes forming two or more stacked layers, wherein forming each of the two or more layers includes forming a recess in an insulating resin layer; forming a dummy layer having a groove and at least one through-hole communicating with the recess; forming a metal-containing layer; forming, on the first metal-containing layer, a second metal-containing layer made of a metal material different from that of the first metal-containing layer; and forming the recess on the dummy layer. forming a conductor layer so as to fill the groove and the through hole; and polishing the conductor layer so that a portion positioned outside the recess, the groove, or the through hole is removed, obtaining a via portion, a land portion, and a wiring portion, respectively, of the conductor layer, the portion in which the recess is embedded, the portion in which the through hole is embedded, and the portion in which the groove is embedded; removing the layer, removing the exposed portion of the first metal-containing layer, and providing an insulating resin layer covering the conductor layer and filling a gap between the land portion and the wiring portion. A method for manufacturing a multilayer wiring board is provided.

According to still another aspect of the present invention, there is provided the method of manufacturing a multilayer wiring board according to the above aspect, wherein the dummy layer is made of a photosensitive resin.

According to still another aspect of the present invention, there is provided a method of manufacturing a multilayer wiring board according to any one of the above aspects, wherein the insulating resin layer is made of a non-photosensitive resin.

According to the present invention, a multilayer wiring board having excellent insulation reliability is provided.

1 is a schematic cross-sectional view of a packaged device according to an embodiment of the invention; FIG. FIG. 2 is a cross-sectional view schematically showing a multilayer wiring board included in the packaged device shown in FIG. 1; FIG. 3 is an enlarged sectional view showing a part of the multilayer wiring board shown in FIG. 2; FIG. 4 is a cross-sectional view showing an enlarged part of a multilayer wiring board according to another embodiment of the present invention; 1 is a cross-sectional view schematically showing one step in a method for manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. FIG. 4 is a cross-sectional view schematically showing another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the method of manufacturing a multilayer wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing one step of a method of manufacturing a packaged device according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing another step of the method of manufacturing a packaged device according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step of the method of manufacturing a packaged device according to one embodiment of the present invention; FIG. 2 is a cross-sectional view schematically showing a multilayer wiring board according to a comparative example; FIG. 31 is an enlarged sectional view showing a part of the multilayer wiring board shown in FIG. 30;

Embodiments of the present invention will be described below with reference to the drawings. The embodiments described below embody any of the above aspects more specifically. The embodiments shown below are examples embodying the technical idea of the present invention. It is not limited. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

In the drawings referred to in the following description, the same reference numerals are given to components having the same or similar functions. Here, the drawings are schematic, and the relationship between the dimension in the thickness direction and the direction perpendicular to the thickness direction, that is, the dimension in the in-plane direction, the relationship between the dimensions in the thickness direction of a plurality of layers, etc. , may differ from reality. Therefore, specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationships of two or more components may differ between the drawings. It should also be noted that in some drawings the same structure is shown upside down from other drawings.

In the present disclosure, the “upper surface” and the “lower surface” refer to the two main surfaces of the plate-shaped member or the layer included therein, that is, the surface perpendicular to the thickness direction and having the largest area and the back surface thereof. , respectively denote the surface shown above and the surface shown below in the drawing. In addition, "side surface" means a surface that is perpendicular to or inclined with respect to the main surface.

Also, in this disclosure, the description "AA on top of BB" is used regardless of the direction of gravity. The condition identified by the statement "AA on BB" encompasses the condition where AA is in contact with BB. Reference to "AA over BB" does not exclude the interposition of one or more other components between AA and BB.

<Structure>
FIG. 1 is a schematic cross-sectional view of a packaged device according to one embodiment of the present invention.

A packaged device 1 shown in FIG. 1 includes a composite wiring board 10, a functional device 20, a sealing resin layer 30, and a bonding electrode 40. As shown in FIG.

The functional device 20 is, for example, a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. Here, as an example, functional device 20 is assumed to be a semiconductor chip. That is, here the packaged device 1 is a semiconductor package.

Packaged device 1 includes a plurality of functional devices 20 . Packaged device 1 may include only one functional device 20 .

The functional device 20 is bonded to the composite wiring board 10 via bonding electrodes 40 . Here, the functional device 20 is bonded to the composite wiring board 10 by flip chip bonding. One or more of functional devices 20 may be bonded to composite wiring board 10 by other bonding methods such as wire bonding.

The bonding electrodes 40 are arranged with a narrow pitch between the functional device 20 and the composite wiring board 10 . The joint electrode 40 is made of solder, for example. When bonding the functional device 20 to the composite wiring board 10 by wire bonding, for example, gold wires can be used to electrically connect the functional device 20 and the composite wiring board.

The sealing resin layer 30 includes a portion interposed between the functional device 20 and the composite wiring board 10 and a portion at least partially covering the side surfaces of the functional device 20 . The sealing resin layer 30 fixes the functional device 20 to the composite wiring board 10 .

The composite wiring board 10 includes an FC-BGA board 11, a multilayer wiring board 12, a sealing resin layer 13, and bonding electrodes .

The FC-BGA board 11 is an example of a first wiring board. The FC-BGA substrate 11 is bonded to, for example, a mother board (not shown).

The FC-BGA substrate 11 includes a core layer 111 , an insulating layer 112 , a conductor layer 113 , an insulating layer 114 and a joining conductor 115 .

Core layer 111 is an insulating layer. The core layer 111 is, for example, a fiber-reinforced substrate made of woven fabric or non-woven fabric impregnated with a thermosetting insulating resin. As woven or non-woven fabrics, for example glass fibres, carbon fibres, or aramid fibres, can be used. For example, an epoxy resin can be used as the insulating resin.

The core layer 111 is provided with through holes. A portion of the conductor layer 113 covers the side wall of the through hole. Here, part of the conductor layer 113 covers the sidewalls of the through holes provided in the core layer 111 so as to form through holes with conductor sidewalls. These through-holes whose side walls are made of a conductor may be filled with an insulator.

The rest of the conductor layer 113 and the insulating layer 112 form a multilayer wiring structure on both main surfaces of the core layer 111 . Each multilayer wiring structure includes conductor layers 113 and insulating layers 112 that are alternately laminated.

Each insulating layer 112 included in the multilayer wiring structure is, for example, an insulating resin layer. Through holes are provided in the insulating layer 112 .

The conductor layer 113 is made of a metal such as copper or an alloy. The conductor layer 113 may have a single layer structure or a multilayer structure.

Each conductor layer 113 included in the multilayer wiring structure includes a wiring portion and a land portion. The conductor layer 113 facing the core layer 111 with the insulating layer 112 therebetween further includes a via portion covering the side wall of the through hole provided in the insulating layer 112 .

An insulating layer 114 is provided on the multilayer wiring structure. The insulating layer 114 is, for example, an insulating resin layer such as a solder resist. The insulating layer 114 is provided with through-holes communicating with the conductor layer 113 located on the outermost surface of the multilayer wiring structure.

The bonding conductor 115 is a metal bump provided on the exposed portion of the conductor layer 113 at the position of the through hole of the insulating layer 114 . Note that the joining conductor is also called a joining terminal. The joining conductor 115 is made of solder, for example.

The multilayer wiring board 12 is a second wiring board. The multilayer wiring board 12 is bonded to the functional device 20 via the bonding electrodes 40 and bonded to the FC-BGA substrate 11 via the bonding electrodes 14 . That is, the multilayer wiring board 12 is an interposer that mediates bonding between the functional device 20 and the FC-BGA board 11 . The thickness of the multilayer wiring board 12 is, for example, within the range of 10 μm or more and 300 μm or less. The multilayer wiring board 12 will be detailed later.

The junction electrodes 14 are arranged between the multilayer wiring board 12 and the functional device 20 . The pitch of the bonding electrodes 14 is wider than the pitch of the bonding electrodes 40 and narrower than the pitch of the bonding conductors 115 located on the bottom surface of the FC-BGA substrate 11 . The joint electrode 14 is made of solder, for example.

The sealing resin layer 13 includes a portion interposed between the FC-BGA substrate 11 and the multilayer wiring substrate 12 . Note that the sealing resin layer is also called an underfill layer. The sealing resin layer 13 fixes the second wiring board 12 to the FC-BGA board 11 .

The multilayer wiring board 12 will be described in more detail with reference to FIGS. 2 and 3. FIG.
FIG. 2 is a cross-sectional view schematically showing a multilayer wiring board 12 included in the packaged device 1 shown in FIG. FIG. 3 is a cross-sectional view showing an enlarged part of the multilayer wiring board 12 shown in FIG.

2 and 3, the multilayer wiring board 12 shown in FIGS. It includes layer 127 b , conductor layer 129 , insulating resin layer 130 and surface treatment layer 131 .

Two or more layers 126 are laminated together. Here, two layers 126 are laminated. The number of layers 126 may be three or more.

Each of these layers 126 includes an insulating resin layer 1263, a conductor layer 1262, a first metal containing layer 1261a and a second metal containing layer 1261b.

The insulating resin layer 1263 is, for example, integrally formed in the thickness direction. Insulating resin layer 1263 is preferably made of insulating resin containing no filler.

As shown in FIGS. 2 and 3, the insulating resin layer 1263 has a first surface S1 and a second surface S2 which is the back surface thereof. The insulating resin layer 1263 is provided with a plurality of first recesses R1, a plurality of grooves G, and a plurality of second recesses R2.

The first recess R1 is open on the first surface S1. The first concave portion R1 is a land concave portion embedded with a land portion 1262L, which will be described later.

The first recesses R1 have the same depth. The depth of first recess R1 is smaller than the thickness of insulating resin layer 1263 .

One or more of the first recesses R1 communicate with one of the grooves G. One or more of the first recesses R1 communicate with the second recesses R2 of the insulating resin layer 1263 in which the first recesses R1 are provided.

The first recess R1 has an opening, side walls and a bottom surface. The bottom surface of the first recess R1 is a plane perpendicular to the thickness direction. According to one example, the first recess R1 has a circular bottom surface, and the bottom surface of the first recess R1 communicating with the second recess R2 is circularly open.

The first recess R1 here has a shape in which the dimension in the direction perpendicular to the thickness direction gradually increases from the opening toward the bottom. That is, the first recess R1 here has a reverse tapered cross section perpendicular to the thickness direction. According to one example, the first recess R1 has a truncated cone shape. The first recess R1 may have a rectangular cross section parallel to the thickness direction. That is, the first recess R1 may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction.

The groove G is open on the first surface S1. The groove portion G is embedded with a wiring portion 1262W, which will be described later. The depth of the groove G is equal to the depth of the first recess R1.

The groove portion G has an opening, side walls and a bottom surface. The bottom surface of the groove G is a plane perpendicular to the thickness direction.

The groove portion G has a shape in which the width gradually widens from the opening toward the bottom surface. That is, the groove G here has a reverse tapered cross section perpendicular to the length direction. The groove G may have a rectangular cross section perpendicular to the length direction.

The second recess R2 is open on the second surface S2. The second recess R2 is a via recess filled with a via portion 1262V, which will be described later.

The second recess R2 communicates with one or more of the first recesses R1. Specifically, each of the second recesses R2 communicates with one of the first recesses R1.

The second recess R2 has an opening and side walls. The second recess R2 communicates with the first recess R1 at its bottom position. The orthogonal projection of the second recess R2 onto a plane perpendicular to the thickness direction is surrounded by the outline of the orthogonal projection of the bottom surface of the first recess R1 communicating with this second recess R2 onto the plane.

The second recess R2 has a shape in which the dimension in the direction perpendicular to the thickness direction gradually increases from the opening toward the bottom. That is, the second recess R2 has a reverse tapered cross section perpendicular to the thickness direction. According to one example, the second recess R2 has a truncated cone shape. The second recess R2 may have a rectangular cross section parallel to the thickness direction. That is, the second recess R2 may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction.
The first recessed portion R1, the groove portion G, and the second recessed portion R2 will be described later in more detail.

The conductor layer 1262 includes a land portion 1262L and a wiring portion 1262W in which the first concave portion R1 and the groove portion G of the insulating resin layer 1263 are respectively embedded, and a via portion 1262V protruding from the first surface S1 at the position of the land portion 1262L. there is In each conductor layer 1262, each via portion 1262V is formed integrally with one land portion 1262L included in that conductor layer 1262. FIG. The via portion 1262V of each conductor layer 1262 is adjacent to the insulating resin layer 1263 in which the first concave portion R1 and the groove portion G are respectively embedded by the land portion 1262L and the wiring portion 1262W of the conductor layer 1262 on the first surface S1 side. is embedded in the second recess R2 of the insulating resin layer.

The conductor layer 1262 is made of a metal such as copper or an alloy. The conductor layer 1262 may have a single layer structure or a multilayer structure. According to one example, conductor layer 1262 is comprised of copper.

As shown in FIGS. 2 and 3, the first metal-containing layer 1261a covers the surface of the wiring portion 1262W on the first surface S1 side without covering the side surface of the wiring portion 1262W. In addition, the first metal-containing layer 1261a covers the surface of the land portion 1262L on the first surface S1 side without covering the side surface of the land portion 1262L. Also, the first metal-containing layer 1261a covers the side and bottom surfaces of the via portion 1262V in FIG.

The first metal-containing layer 1261a is an adhesion layer or seed that improves the adhesion of the second metal-containing layer 1261b to the dummy layer 125 and the insulating resin layer 124, which will be described later, and makes it difficult for the second metal-containing layer 1261b to peel off. It is an adhesion layer. Also, the first metal-containing layer 1261 a is a barrier layer that makes it difficult for metal to diffuse from the conductor layer 1262 to the insulating resin layer 1263 . According to one example, the first metal-containing layer 1261a is a titanium-containing layer, such as a titanium oxide layer.

Second metal-containing layer 1261b includes a portion interposed between first metal-containing layer 1261a and wiring portion 1262W and a portion covering the side surface of wiring portion 1262W. Second metal-containing layer 1261b further includes a portion interposed between first metal-containing layer 1261a and land portion 1262L and a portion covering the side surface of land portion 1262L. Second metal-containing layer 1261b includes a portion interposed between first metal-containing layer 1261a and via portion 1262V. The second metal-containing layer 1261b is a seed layer that plays a role as a power supply layer in film formation of the conductor layer 1262 by electroplating.

The second metal-containing layer 1261b is made of a metal material different from the material of the first metal-containing layer 1261a. The second metal-containing layer 1261 b may be made of the same material as the conductor layer 1262 . Alternatively, the second metal-containing layer 1261b may be made of a metal material that has a lower ionization tendency than the material of the conductor layer 1262 . The second metal-containing layer 1261b includes, for example, copper. When second metal-containing layer 1261b contains copper, delamination is less likely to occur between insulating resin layer 1263 and second metal-containing layer 1261b. Even when two layers laminated to each other are made of the same material, the interface between the layers can be confirmed by observing a cross section parallel to the lamination direction with, for example, a scanning electron microscope.

A portion of the second metal-containing layer 1261b covering the side surface of the wiring portion 1262W preferably has an arithmetic average roughness Ra of 10 nm or less. When the arithmetic mean roughness Ra of the portion is 10 nm or less, high transmission characteristics can be achieved because electrons travel a short distance through the surface of the portion.
Arithmetic mean roughness Ra is obtained by a method conforming to JIS B 0601:2013.

The insulating resin layer 124 is provided on one main surface of the multilayer wiring structure composed of the layer 126, as shown in FIG. The material of the insulating resin layer 124 may be the same as or different from the material of the insulating resin layer 1263 .

Insulating resin layer 124 is provided with through holes at positions of via portions 1262V of insulating resin layer 1263 included in layer 126 adjacent thereto. The through hole of insulating resin layer 124 is filled with via portion 1262V of insulating resin layer 1263 included in layer 126 adjacent thereto.

The through-holes of the insulating resin layer 124 are recesses opened on the layer 126 side. Here, it has a shape in which the dimension in the direction perpendicular to the thickness direction gradually increases from the bottom to the top. That is, here, the recess of the insulating resin layer 124 has a reverse tapered cross section perpendicular to the thickness direction. According to one example, these through-holes have a frusto-conical shape. These through holes may have a rectangular cross section parallel to the thickness direction. That is, these through-holes may have a prismatic or cylindrical shape whose height direction is parallel to the thickness direction.

The insulating resin layer 123 is provided on the insulating resin layer 124 . The material of the insulating resin layer 123 may be the same as or different from the material of the insulating resin layers 124 and 1263 . Through holes are provided in the insulating resin layer 123 at the positions of the through holes of the insulating resin layer 124 .

The conductor layer 122 fills the through holes of the insulating resin layer 123 . The conductor layer 122 is an electrode for joining the multilayer wiring board 12 and the functional device 20 . The conductor layer 122 is made of copper, for example.

The conductor layer 129 fills the second recess R2 of the insulating resin layer 1263 included in the layer 126 positioned above, and also fills the second surface S2 of the insulating resin layer 1263 with the opening of the second recess R2 and its surroundings. covering the area. The conductor layer 129 is made of a metal such as copper or an alloy.

The adhesion layer 127a covers the portion covering the inner surface of the second recess R2 of the insulating resin layer 1263 included in the layer 126 located above and the opening of the second recess R2 on the second surface S2 of the insulating resin layer 1263. and a portion covering the area around the The adhesion layer 127a is a layer that improves the adhesion of the seed layer 127b to the insulating resin layer 1263 and makes it difficult for the seed layer 127b to peel off.

The seed layer 127b is provided on the adhesion layer 127a. The seed layer 127b plays a role as a power supply layer in film formation of the conductor layer 129 by electroplating.

The insulating resin layer 130 is provided on the insulating resin layer 1263 and the conductor layer 129 included in the upper layer 126 . Through holes are provided in the insulating resin layer 130 at the positions of the conductor layers 129 .

The surface treatment layer 131 is provided on the portion of the conductor layer 129 exposed in the through hole of the insulating resin layer 130 . The surface treatment layer 131 is provided to prevent oxidation of the surface of the conductor layer 129 and improve wettability with solder.

As shown in FIG. 2, adjacent two of the two or more layers 126 are in contact with, for example, the insulating resin layers 1263 .

The length t1 in FIG. 3 is the distance between the first surface S1 of one of the two adjacent layers 126 and the bottom surface of the groove G included in the other layer 126 . Length t2 is the depth of groove G in layer 126 . The length t3 is the distance between the bottom surface of the groove portion G included in the layer 126 and the second surface S2 of this layer 126 . The length t4 is the width of the bottom surface of the groove G that the layer 126 includes. The length t5 is the distance between the bottom surfaces of grooves G adjacent to each other in the width direction.

FIG. 4 is a cross-sectional view showing an enlarged part of a multilayer wiring board 12 according to another embodiment of the present invention. A multilayer wiring board 12 according to this embodiment is the same as the multilayer wiring board 12 described above, except that the width D1 shown in FIG. 4 is smaller than the width D2 shown in FIG. The width D1 is the width of the portion of the first metal-containing layer 1261a that covers the surface of the wiring portion 1262W on the first surface S1 side. In other words, the width D1 is the width of the first metal-containing layer 1261a in a direction perpendicular to the length direction of the wiring portion 1262W and perpendicular to the thickness direction of the wiring portion 1262W. Width D2 is the width of a region of the surface of second metal-containing layer 1261b facing a plane including first surface S1.

When the width D1 is smaller than the width D2, the contact area between the insulating resin layer 1263 and the second metal containing layer 1261b is large, so that delamination is less likely to occur between the insulating resin layer 1263 and the second metal containing layer 1261b.

<Manufacturing method>
The multilayer wiring board 12 included in this packaged device 1 can be manufactured, for example, by the following method.

5 to 26 are cross-sectional views schematically showing a method of manufacturing a multilayer wiring board according to one embodiment of the present invention.

In this method, first, as shown in FIG. 5, a release layer 3 is formed on one surface of a support 2 .

Since the release layer 3 may be irradiated with light through the support 2, it is advantageous for the support 2 to have translucency. As the support 2, for example, a glass plate can be used. A rectangular glass plate is suitable for upsizing. Also, the glass plate can achieve excellent flatness and high rigidity. Therefore, the glass plate as the support 2 is suitable for forming fine patterns thereon.

In addition, since the glass plate has a small coefficient of thermal expansion (CTE) and is not easily distorted, it is excellent in ensuring pattern arrangement accuracy and flatness. When a glass plate is used as the support 2, the thickness of the glass plate is desirably thick from the viewpoint of suppressing the occurrence of warping in the manufacturing process, for example 0.5 mm or more, preferably 1.2 mm or more.

The CTE of the glass plate is preferably 3 ppm or more and 16 ppm or less, and more preferably about 10 ppm from the viewpoint of matching with the CTE of the FC-BGA substrate 11 and the functional device 20 .

As the glass, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, or the like is used.

On the other hand, if the support 2 is not required to have light transmittance when the support 2 is peeled off, such as using a resin that foams with heat for the release layer 3, the support 2 may be made of a material that causes less distortion, such as metal. or ceramics can be used.

In the following, as an example, it is assumed that the material of the release layer 3 is a resin that can be separated by absorbing ultraviolet light (UV light), and the support 2 is a glass plate.

The release layer 3 may be, for example, a resin that can be peeled by generating heat or changing properties by absorbing light such as UV light, or may be a resin that is foamed by heat and becomes peelable. Materials for the release layer 3 include, for example, organic resins such as epoxy resins, polyimide resins, polyurethane resins, silicone resins, polyester resins, oxetane resins, maleimide resins, and acrylic resins, amorphous silicon, gallium nitride, and metal oxides. It can be selected from inorganic layers such as monolayers. The release layer 3 may further contain additives such as a photodegradation accelerator, a light absorber, a sensitizer, and a filler.

The release layer 3 may have a single layer structure or a multilayer structure. Further, for example, a protective layer may be provided on the release layer 3 for the purpose of protecting the multilayer wiring structure formed on the support 2, and the adhesiveness between the support 2 and the release layer 3 may be improved. Additional enhancing layers may be provided. Further, a laser light reflecting layer or a metal layer may be further provided between the peeling layer 3 and the multilayer wiring structure.

When a resin that can be peeled off by light such as UV light, for example, laser light, is used as the material of the peeling layer 3 , if the support 2 is translucent, the peeling layer 3 can be formed through the support 2 . light may be applied.

Next, an adhesion layer 4a and a seed layer 4b are formed in a vacuum as shown in FIG. The adhesion layer 4a is a layer that improves the adhesion of the seed layer 4b to the peeling layer 3 and prevents the peeling of the seed layer 4b in subsequent steps. Also, the seed layer 4 b serves as a power supply layer in electroplating for forming the conductor layer 122 .

The adhesion layer 4a and the seed layer 4b can be formed by, for example, a sputtering method or a vapor deposition method. Materials for the adhesion layer 4a and the seed layer 4b include, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO ( Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), ZnO, PZT ₍ lead zirconate titanate), TiN, _Cu3N4 , Cu alloy, or a combination of these can be used. Here, as an example, in consideration of electrical characteristics, ease of manufacture, and cost, a titanium layer and a copper layer are used for the adhesion layer 4a and the seed layer 4b, respectively, and they are formed by a sputtering method. and

The total thickness of the adhesion layer 4a and seed layer 4b is preferably 1 μm or less. Here, as an example, a titanium layer with a thickness of 50 nm is formed as the adhesion layer 4a, and a copper layer with a thickness of 300 nm is formed as the seed layer 4b.

Next, as shown in FIG. 7, a resist layer 121 is formed on the seed layer 4b. The resist layer 121 is made of a photosensitive resin. As the photosensitive resin, for example, photosensitive polyimide resin, photosensitive benzocyclobutene resin, photosensitive epoxy resin, or modified products thereof can be used. The photosensitive resin may be liquid or film-like.

When a liquid photosensitive resin is used as the material of the resist layer 121, the resist layer 121 is formed by, for example, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, and gravure offset. It can be formed on the seed layer 4b by any one of printing, spin coating, and doctor coating. When a film resist is used as the resist layer 121, the resist layer 121 can be provided on the seed layer 4b by any method such as lamination, vacuum lamination, or vacuum pressing.

Next, through holes are formed in the resist layer 121 by photolithography. The shape of the through holes in plan view is set according to the pitch and shape of the bonding electrodes of the functional device 20 . Here, as an example, it is assumed that the through holes have circular openings with a diameter of 25 μm and a pitch of 55 μm. Here, planar viewing refers to observing an object in the thickness direction, that is, observing an orthogonal projection of the object onto a plane perpendicular to the thickness direction.

The thickness of the resist layer 121 is set according to the thickness of the conductor layer 122 to be formed next. Here, as an example, the thickness of the resist layer 121 is set to 8 μm.

After forming these through-holes, plasma treatment may be performed for the purpose of removing residues during development.

Next, as shown in FIG. 8, a conductor layer 122 is formed on the seed layer 4b by electroplating. The conductor layer 122 constitutes an electrode for bonding with the functional device 20 . Electrolytic plating for forming the conductor layer 122 includes, for example, electrolytic nickel plating, electrolytic copper plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, and the like. Among these, electrolytic copper plating is desirable because it is simple and inexpensive and can achieve good electrical conductivity.

The conductor layer 122 serves as an electrode for bonding with the functional device 20 as described above. Therefore, the thickness of the conductor layer 122 is desirably 1 μm or more from the viewpoint of solder joint, and desirably 30 μm or less from the viewpoint of productivity.

Next, as shown in FIG. 9, the resist layer 121 is removed. The resist layer 121 is removed by, for example, a dry etching method, or dissolved or peeled off by immersion in an alkaline solution or solvent.

Next, as shown in FIG. 10, an insulating resin layer 123 is formed so as to embed the conductor layer 122 . The material of the insulating resin layer 123 may be a photosensitive resin or a non-photosensitive resin. The material of the insulating resin layer 123 may be the same as or different from the material of the insulating resin layers 124, 130 and 1263, which will be described later.

Next, as shown in FIG. 11, the upper surface of the conductor layer 122 is exposed by physical polishing or physical polishing and chemical mechanical polishing (CMP). The structure obtained in this way can also be obtained by a damascene method.

Next, as shown in FIG. 12, an insulating resin layer 124 having a through hole at the position of the conductor layer 122 is provided on the conductor layer 122 and the insulating resin layer 123 . The through-hole of the insulating resin layer 124 is the second concave portion R2 opened on the second surface of the insulating resin layer 124, which is the upper surface of the insulating resin layer 124 in this case. The second recessed portion R2 may be formed to have a rectangular cross section, but is preferably formed to have a forward tapered shape. The forward tapered shape facilitates formation of the first metal-containing layer 1261a and the second metal-containing layer 1261b without causing a discontinuity in the second recess R2.

The insulating resin layer 124 is made of, for example, a photosensitive resin. As this photosensitive resin, for example, the same material as described above for the resist layer 121 can be used. Also, the insulating resin layer 124 having through holes can be formed, for example, by the same method as described above for the resist layer 121 .

Alternatively, the insulating resin layer 124 is made of a non-photosensitive resin. As the non-photosensitive resin, for example, polyimide resin, benzocyclobutene resin, epoxy resin, or modified products thereof can be used. Non-photosensitive resins such as polyimide can achieve high heat resistance in addition to being excellent in insulating properties and mechanical properties. Inorganic particles such as silica, alumina, and zirconia may be added as a filler to the non-photosensitive resin. Here, as an example, a non-photosensitive polyimide resin is used as the non-photosensitive resin.

The non-photosensitive resin may be liquid or film-like.

When a liquid non-photosensitive resin is used, the insulating resin layer 124 is formed by, for example, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating.

When a film-like non-photosensitive resin is provided as the insulating resin layer 124, lamination, vacuum lamination, vacuum press, or the like can be applied.

Here, as an example, a photosensitive epoxy resin is applied onto the conductor layer 122 and the insulating resin layer 123 by spin coating. A photosensitive epoxy resin can be cured at a relatively low temperature, and shrinkage due to curing is small, which is advantageous for subsequent fine pattern formation. Also, here, as an example, the insulating resin layer 124 is formed to have a thickness of 2 μm.

In addition, after forming the insulating resin layer 124, in order to planarize the surface, it may be subjected to physical polishing, or may be subjected to physical polishing and polishing such as CMP. When a non-photosensitive resin is used as the material of the insulating resin layer 124, the through holes can be formed by, for example, laser light irradiation.

Next, as shown in FIG. 13, a dummy layer 125 is formed on the insulating resin layer 124 and the conductor layer 122. The dummy layer 125 has a groove G' and at least one through hole R1' communicating with the second recess R2. The groove G' and the through hole R1' of the dummy layer 125 correspond to the groove portion G and the first concave portion R1 of the insulating resin layer 1263, respectively.

The dummy layer 125 is made of photosensitive resin. As this photosensitive resin, for example, the same material as described above for the resist layer 121 can be used. Also, the dummy layer 125 having the groove G' and the through hole R1' can be formed by the same method as described above for the resist layer 121, for example.

Through hole R<b>1 ′ of dummy layer 125 is formed so that the opening diameter at the upper surface thereof is larger than the opening diameter at the upper surface of the through hole of insulating resin layer 124 . Also, the through hole R1' is formed in a forward tapered shape. The groove G' is also formed so that the cross section perpendicular to the length direction has a forward tapered shape.

The groove G' and the through-hole R1' may be formed so as to have a rectangular cross-section, but if they are formed in a forward tapered shape, the groove G' and the through-hole R1' do not have a discontinuous portion. , it becomes easier to form the first metal-containing layer 1261a and the second metal-containing layer 1261b.

Next, in a vacuum, as shown in FIG. 14, the upper surface of the dummy layer 125, the inner surface of the second recess R2, the inner surface of the groove G′, and the inner surface of the through hole R1′ are coated with a first metal-containing layer. Form layer 1261a. Subsequently, a second metal-containing layer 1261b made of a metal material different from that of the first metal-containing layer 1261a is formed on the first metal-containing layer 1261a.

The first metal-containing layer 1261a and the second metal-containing layer 1261b are a seed adhesion layer (or adhesion layer) and a seed layer, respectively. The first metal-containing layer 1261a and the second metal-containing layer 1261b can use the same materials as described above for the adhesion layer 4a and the seed layer 4b, respectively. Also, the first metal-containing layer 1261a and the second metal-containing layer 1261b can be formed by methods similar to those described above for the adhesion layer 4a and the seed layer 4b, respectively.

The material of the second metal-containing layer 1261b is preferably the same material as the conductor layer 1262 or a metal material with a lower ionization tendency than the material of the conductor layer 1262. When the material of the second metal-containing layer 1261 b has a lower ionization tendency than the material of the conductor layer 1262 , the second metal-containing layer 1261 b tends to prevent diffusion of metal from the conductor layer 1262 to the insulating resin layer 1263 .

The sum of the thickness of the first metal-containing layer 1261a and the thickness of the second metal-containing layer 1261b is preferably 1 μm or less. In this case, it is preferable as a power supply layer for electroplating.

The thickness of the first metal-containing layer 1261a is preferably in the range of 10 nm to 100 nm, more preferably in the range of 30 nm to 80 nm.

The thickness of the second metal-containing layer 1261b is preferably in the range of 40 nm to 400 nm, more preferably in the range of 100 nm to 350 nm.

Here, as an example, in consideration of electrical characteristics, ease of manufacture, and cost, furthermore, the adhesion between the insulating resin layer 1263 and the second metal-containing layer 1261b is improved, and the material of the conductor layer 1262 is selected. For example, a layer containing titanium is employed as the first metal-containing layer 1261a to prevent diffusion of copper. In addition, a layer containing copper is adopted as the second metal-containing layer 1261b in consideration of electrical properties, ease of manufacture, and cost. The first metal-containing layer 1261a and the second metal-containing layer 1261b are sequentially formed by sputtering. The thickness of the first metal-containing layer 1261a is 50 nm, and the thickness of the second metal-containing layer 1261b is 300 nm.

As the material of the first metal-containing layer 1261a, a material other than titanium may be applied as long as it has a function of preventing diffusion of the material of the second metal-containing layer 1261b, for example, copper. Also, between the first metal-containing layer 1261a and the second metal-containing layer 1261b, a layer made of a metal material different from the material of the first metal-containing layer 1261a and the material of the second metal-containing layer 1261b may be provided. .

Next, as shown in FIG. 15, a conductor layer 1262' is formed on the second metal-containing layer 1261b. The conductor layer 1262' is formed so as to fill the second recess R2, the groove G', and the through hole R1'. Conductive layer 1262' can use the same materials as described above for conductive layer 122. FIG. Also, the conductor layer 1262 ′ can be formed by a method similar to that described above for the conductor layer 122 . Here, as an example, the conductor layer 1262 is assumed to be a copper layer formed by electrolytic plating.

Next, as shown in FIG. 16, the conductor layer 1262', the first metal-containing layer 1261a, and the second metal-containing layer 1261b are subjected to physical polishing and polishing such as CMP to remove the conductor layer 1262' and the first metal-containing layer 1262'. A portion of the layer 1261a and the second metal-containing layer 1261b located outside the second recess R2, the groove G', or the through hole R1' is removed. In addition, along with this polishing, the portion near the upper surface of the dummy layer 125 may also be removed.

Of the conductor layer 1262' shown in FIG. 15, the conductor layer 1262 shown in FIG. 16 is the portion left after the above polishing.
As described above, of the conductor layer 1262, the portion in which the second recess R2 is embedded, the portion in which the through hole R1′ is embedded, and the portion in which the groove G′ is embedded are formed into via portions 1262V, land portions 1262L and Obtained as wiring portion 1262W.

Next, as shown in FIG. 17, the dummy layer 125 is removed. The dummy layer 125 can be removed by dry etching or immersion in an alkaline solution or solvent.

Next, as shown in FIG. 18, exposed portions of the first metal-containing layer 1261a in the structure shown in FIG. 17 are removed with an etchant. By removing the exposed portion of the first metal-containing layer 1261a, the second metal-containing layer 1261b covering the side surface of the land portion 1262L and the side surface of the wiring portion 1262W is exposed.

As the etchant, a chemical solution that selectively etches the first metal-containing layer 1261a with respect to the second metal-containing layer 1261b is used. This etching maintains the smoothness of the portion of the second metal-containing layer 1261b that covers the side surfaces of the wiring portion 1262W and the land portion 1262L.

For example, after this etching, the portion of the second metal-containing layer 1261b that covers the side surfaces of the wiring portion 1262W and the land portion 1262L has an arithmetic mean roughness Ra of 10 nm or less.

Note that the width D1 described with reference to FIG. 4 may be smaller than the width D2. When the width D1 and the width D2 are approximately the same and the adhesion between the insulating resin layer 1263 and the second metal-containing layer 1261b is insufficient, the width D1 is made smaller than the width D2 so that the insulating resin The contact area between layer 1263 and second metal-containing layer 1261b can be increased. This can improve the adhesion between the insulating resin layer 1263 and the second metal-containing layer 1261b.

In order to improve adhesion between the wiring portion 1262W, the first metal-containing layer 1261a and the second metal-containing layer 1261b, and the insulating resin layer 1263, after removing the exposed portion of the first metal-containing layer 1261a, the wiring is Part 1262W, first metal-containing layer 1261a and second metal-containing layer 1261b may be treated with a silane coupling agent.

Next, as shown in FIG. 19, an insulating resin layer 1263 covering the conductor layer 1262 and filling the gap between the land portion 1262L and the wiring portion 1262W is provided. A through hole is formed in the insulating resin layer 1263 as the second recess R2. In addition, of the insulating resin layer 1263, the lower surface and the upper surface of the insulating resin layer 1263 are the first surface S1 and the second surface S2, respectively. Further, the recessed portion of the insulating resin layer 1263 filled with the land portion 1262L is the above-described first recessed portion R1. The recessed portion of the insulating resin layer 1263 filled with the wiring portion 1262W is the groove portion G described above.

The insulating resin layer 1263 is made of photosensitive resin or non-photosensitive resin. As this photosensitive resin or non-photosensitive resin, for example, materials similar to those described above for the resist layer 121 and the insulating resin layer 124 can be used. Also, the insulating resin layer 1263 having the first concave portion R1, the second concave portion R2 and the groove portion G can be formed by the same method as described above for the resist layer 121 and the insulating resin layer 124, for example.

The thickness of the insulating resin layer 1263 is, for example, within the range of 1.5 μm to 2 μm. Here, as an example, the insulating resin layer 1263 is formed with a thickness of 2 μm.

As described above, the layer 126 including the first metal-containing layer 1261a, the second metal-containing layer 1261b, the conductor layer 1262, and the insulating resin layer 1263 is obtained.

The sequence of steps described with reference to FIGS. 13-19 is then repeated. As a result, the multilayer wiring structure shown in FIG. 20 is obtained. That is, a multilayer wiring structure including two layers 126 is obtained. By repeating the above sequence two or more times, the number of layers 126 included in the multilayer wiring structure can be increased to three or more.

Next, as shown in FIG. 21, an adhesion layer 127a covering the upper surface of the insulating resin layer 1263 included in the upper layer 126 and the inner surface of the second recess R2 is formed. Subsequently, a seed layer 127b made of a metal material different from the material of the adhesion layer 127a is formed on the adhesion layer 127a. The seed layer 127b is preferably made of the same material as the conductor layer 129 or made of a metal material with a lower ionization tendency compared to the material of the conductor layer 129 .

For the adhesion layer 127a and the seed layer 127b, materials similar to those described above for the adhesion layer 4a and the seed layer 4b can be used, respectively. Further, the adhesion layer 127a and the seed layer 127b can be formed by the same method as described above for the adhesion layer 4a and the seed layer 4b, respectively.

Next, a resist layer 128 having through holes is formed on the seed layer 127b. Each of the through-holes in resist layer 128 communicates with second recess R2 provided in insulating resin layer 1263 included in upper layer 126 .

The resist layer 128 is made of photosensitive resin. Resist layer 128 can use the same materials as described above for resist layer 121 . Also, the resist layer 128 can be formed by the same method as described above for the resist layer 121 .

Next, as shown in FIG. 22, a conductor layer 129 is formed on the seed layer 127b. Conductor layer 129 can use the same materials as those described above for conductor layer 122 . Conductor layer 129 can be formed by a method similar to that described above for conductor layer 122 .

Next, as shown in FIG. 23, the resist layer 128 is removed. Resist layer 128 can be removed by a method similar to that described above for resist layer 121 .

Next, as shown in FIG. 24, exposed portions of the adhesion layer 127a and the seed layer 127b are removed. The adhesion layer 127a and the seed layer 127b can be removed, for example, by immersion in a chemical solution. As the chemical solution, for example, a chemical solution containing hydrogen peroxide can be used.

Next, as shown in FIG. 25, the insulating resin layer 130 is formed on the insulating resin layer 1263 and the conductor layer 129 . The insulating resin layer 130 has through holes at the positions of the conductor layers 129 . The insulating resin layer 130 can be formed, for example, by providing a solder resist on the insulating resin layer 1263 and the conductor layer 129 and exposing and developing it. An insulating layer obtained from a solder resist is also called a solder resist layer.

As a material of the solder resist, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used. Here, as an example, a photosensitive epoxy resin containing a filler is used as the solder resist.

Next, as shown in FIG. 26, a surface treatment layer 131 is provided on the conductor layer 129 . The surface treatment layer 131 is provided for the purpose of preventing oxidation of the surface of the conductor layer 129 and improving wettability with solder. Here, as an example, an electroless Ni/Pd/Au plating layer is formed as the surface treatment layer 131 .

As the surface treatment layer 131, an OSP (Organic Solderability Preservative) film, that is, a surface treatment layer using a water-soluble preflux may be formed. Alternatively, as the surface treatment layer 131, an electroless tin plated layer or an electroless Ni/Au plated layer may be formed.

Next, a bonding conductor 132 is formed on the surface treatment layer 131 . The bonding conductors 132 are, for example, metal bumps such as solder bumps. The joining conductor 132 can be formed by, for example, placing a solder material such as a solder ball on the surface treatment layer 131, melting it, and then cooling it to fix it to the surface treatment layer 131.

As described above, the multilayer wiring board 12 supported by the support 2, that is, the multilayer wiring board with support is obtained.

Using the support-attached multilayer wiring board thus obtained, the packaged device 1 shown in FIG. 1 can be manufactured, for example, by the following method.

FIG. 27 is a cross-sectional view schematically showing a step in a method of manufacturing a packaged device according to one embodiment of the invention. FIG. 28 is a cross-sectional view schematically showing another step in the method of manufacturing a packaged device according to one embodiment of the invention. FIG. 29 is a cross-sectional view schematically showing still another step in the method of manufacturing a packaged device according to one embodiment of the invention.

First, as shown in FIG. 27, the multilayer wiring board 12 supported by the support 2 and the FC-BGA board 11 are joined. Then, those joints are sealed with a sealing resin layer 13 .

As a material for the sealing resin layer 13, for example, a mixture of resin and filler can be used. As the resin, for example, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins can be used. As fillers, for example, one or more of silica, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide can be used. The sealing resin layer 13 can be formed, for example, by filling a space between the FC-BGA substrate 11 and the multilayer wiring substrate 12 with a liquid material.

As described above, the composite wiring board 10 including the FC-BGA board 11 and the multilayer wiring board 12 is obtained. At this point, the support 2 is still provided on the multilayer wiring board 12 .

Next, as shown in FIG. 28, the release layer 3 is irradiated with a laser beam 50 from the support 2 side, and the support 2 and the composite wiring board 10 are separated from each other as shown in FIG. As described above, the material of the release layer 3 is a resin that can be peeled off by absorbing ultraviolet light (UV light). is. If the release layer 3 remains on the composite wiring board 10, it is removed by etching, for example. Further, the adhesion layer 4a and the seed layer 4b are also removed by etching, for example.

After that, the functional device 20 shown in FIG. 1 is bonded to the composite wiring board 10 .
Prior to bonding the functional device 20, an electroless Ni/Pd/Au plating layer, an OSP film, an electroless tin plating layer, And a surface treatment layer such as an electroless Ni/Au plating layer may be provided.

Then, those joints are sealed with a sealing resin layer 30 .
As the material of the sealing resin layer 30, for example, the materials exemplified as the materials of the sealing resin layer 13 can be used. The encapsulating resin layer 30 can be formed, for example, by the same method as described above for the encapsulating resin layer 13 .
As described above, the packaged device 1 shown in FIG. 1 is completed.

In the above method, the functional device 20 is bonded to the multilayer wiring board 12 after the multilayer wiring board 12 is bonded to the FC-BGA substrate 11 . Alternatively, the multilayer wiring board 12 may be bonded to the FC-BGA board 11 after the functional device 20 is bonded to the multilayer wiring board 12 .

<effect>
Interposers obtained by silicon interposer technology, so-called silicon interposers, are manufactured using silicon wafers and facilities for semiconductor front-end processes. Silicon wafers are limited in shape and size, and the number of interposers that can be manufactured from one wafer is not necessarily large. And the manufacturing equipment is also expensive. Therefore, silicon interposers are expensive. Moreover, since a silicon wafer is a semiconductor, the use of a silicon interposer also poses a problem of deterioration in transmission characteristics.

A silicon wafer is not required for manufacturing the multilayer wiring board 12 described above. Also, in the multilayer wiring board 12, most of the insulating layers can be made of insulating resin layers. Therefore, the above-described multilayer wiring board 12 can be manufactured using inexpensive materials and equipment, enabling cost reduction and achieving excellent transmission characteristics.

The method of directly forming a multi-layered wiring structure including a conductor layer having a fine wiring pattern on an FC-BGA substrate causes little deterioration in transmission characteristics seen in silicon interposers. However, in this method, there are problems with the manufacturing yield of the FC-BGA substrate itself, and there is a high degree of difficulty in forming a multilayer wiring structure including a conductor layer having a fine wiring pattern on a core layer such as a glass epoxy substrate. Therefore, there is a problem that the manufacturing yield is low as a whole. Furthermore, it is difficult to achieve high symmetry with respect to the plane that bisects the thickness of the FC-BGA substrate. Therefore, such FC-BGA substrates tend to warp or distort when heated.

In manufacturing the composite wiring board 10 and the packaged device 1 described above, the multilayer wiring board 12 is manufactured separately from the FC-BGA board 11, and these are bonded together. A multilayer wiring structure including a conductor layer 1262 having a fine wiring pattern is not built into the FC-BGA board 11, but built into the multilayer wiring board 12. FIG. Therefore, the above composite wiring board 10 and packaged device 1 can be manufactured with a high yield.

Further, in manufacturing the composite wiring board 10, the multilayer wiring structure including the conductor layer 1262 having a fine wiring pattern is formed on the support 2 rather than on a core layer such as a glass epoxy board. Since a substrate having excellent smoothness can be used as the support 2, a fine pattern or the like to be formed thereon can be formed with high shape accuracy. For this reason as well, the composite wiring board 10 and the packaged device 1 can be manufactured with a high yield.

In addition, in the composite wiring board 10 and the packaged device 1 described above, it is easy to achieve high symmetry with respect to the plane that bisects the thickness of the FC-BGA board 11. In the substrate 12, too, it is easy to achieve a high degree of symmetry with respect to the plane that bisects its thickness. Therefore, the above-described composite wiring board 10 and packaged device 1 are less likely to warp or distort during heating.

Moreover, there is a semi-additive method as a method for forming fine wiring. In the semi-additive method, first, an underlayer is prepared, and a first metal-containing layer and a second metal-containing layer are formed on the underlayer. Next, a resist layer is formed in a pattern on the second metal-containing layer, and a conductor layer including a wiring part is formed on the second metal-containing layer by electrolytic copper plating. The resist is then removed, followed by further removal of the unwanted first metal-containing layer and second metal-containing layer. Specifically, after removing the resist, the portions of the first metal-containing layer and the second metal-containing layer that are not covered with the conductor layer are removed by etching. After that, the underlying layer and the conductor layer are covered with an insulating resin layer. In this manner, fine wiring and the like are formed on the underlying layer.

According to this method, the surface of the conductor layer is also etched when the unnecessary layers are etched. As a result, the surface of the conductor layer becomes rough. In this case, the arithmetic mean roughness Ra of the surface of the conductor layer is about 100 nm. When the surface of the conductor layer is rough as described above, particularly when the surface of the wiring portion is rough, electrons travel a long distance through the surface, and high transmission characteristics cannot be achieved.

On the other hand, according to the method for manufacturing the multilayer wiring board 12 described above, the side surface of the wiring portion 1262W is covered with the second metal-containing layer 1261b. Moreover, according to the above-described method, the upper surface of the wiring portion and the portion of the second metal-containing layer 1261b covering the side surface of the wiring portion 1262W are hardly etched. Therefore, the upper surface of the wiring portion 1262W and the surface of the portion of the second metal-containing layer 1261b are smooth. When the upper surface of the wiring part 1262W and the surface of the above-mentioned portion are smooth, the movement distance of electrons passing through the upper surface of the wiring part 1262W and the surface of the above-mentioned portion of the second metal-containing layer 1261b is small, so that high transmission characteristics can be achieved. is possible.

Further, in the method of manufacturing the multilayer wiring board 12 described above, if the step described with reference to FIG. It is in contact with the containing layer 1261a. For example, when a titanium layer and a copper layer are used as the first metal-containing layer 1261a and the second metal-containing layer 1261b, respectively, delamination may occur between the insulating resin layer 1263 and the titanium layer.

In contrast, according to the method for manufacturing the multilayer wiring board 12 described above, the insulating resin layer 1263 is in contact with the second metal-containing layer 1261b. When a titanium layer and a copper layer are used as the first metal-containing layer 1261a and the second metal-containing layer 1261b, respectively, delamination is less likely to occur between the insulating resin layer 1263 and the copper layer.

Further, in the multilayer wiring board 12 described above, as shown in FIGS. 2 to 4, the first metal-containing layer 1261a covers the surface of the wiring portion 1262W on the first surface S1 side. Therefore, in the two adjacent layers 126, diffusion of metal from the wiring portion 1262W included in one layer 126 to the insulating resin layer 1263 included in the other layer 126 is unlikely to occur. Therefore, the multilayer wiring board 12 described above can achieve excellent insulation reliability.

Further, in the multilayer wiring board 12 described above, as shown in FIGS. 2 to 4, the first metal-containing layer 1261a does not cover the side surface of the wiring portion 1262W, and the surface of the wiring portion 1262W on the side of the first surface S1 is formed. is covered. Therefore, for example, when a material having a lower conductivity than the material of the wiring portion 1262W is used as the material of the first metal-containing layer 1261a, the multilayer wiring board 12 described above further covers the side surface of the wiring portion 1262W. A lower wiring resistivity than a multilayer wiring board with one metal-containing layer 1261a can be achieved.

Next, the effects of using the above-described multilayer wiring board 12 and its manufacturing method will be described.

(Example)
The multilayer wiring board 12 described with reference to FIGS. 2 and 3 was manufactured by the method described with reference to FIGS. The lengths t1 and t3 of the multilayer wiring board 12 were set to 5 μm, and the lengths t2, t4 and t5 were set to 2 μm. Moreover, the wiring length was set to 2 mm.

(Comparative example)
FIG. 30 is a cross-sectional view schematically showing a multilayer wiring board 12'. FIG. 31 is a cross-sectional view showing an enlarged part of the multilayer wiring board 12' shown in FIG.

A multilayer wiring board 12' shown in FIGS. 30 and 31 is the same as the multilayer wiring board 12 according to the embodiment except for the following points.

That is, multilayer wiring board 12 ′ includes layer 126 ′ instead of layer 126 . Each layer 126' includes an insulating resin layer 1263, a first metal-containing layer 1261a', a second metal-containing layer 1261b', and a conductor layer 1262'. Since the conventional semi-additive method is used to form the first metal-containing layer 1261a', the second metal-containing layer 1261b', and the conductor layer 1262', the side surface of the wiring part 1262W' is formed by the second metal-containing layer 1261b'. not covered. Moreover, the cross section of the wiring portion 1262W has a substantially rectangular shape. Except for these points, the multilayer wiring board 12' according to the comparative example is the same as the multilayer wiring board 12 according to the embodiment.

In FIG. 31, the length t1′ is the distance between the first surface S1 of one of the two adjacent layers 126′ and the bottom surface of the groove included in the other layer 126′. be. Length t2' is the depth of the trench in layer 126'. The length t3' is the shortest distance between the bottom surface of the trench included in the layer 126' and the second surface S2 of this layer 126'. Length t4' is the width of the bottom of the trench that layer 126' contains. The length t5' is the distance between the bottom surfaces of adjacent grooves in the width direction of the grooves.

The lengths t1' and t3' of the multilayer wiring board 12' were set to 5 .mu.m, and the lengths t2', t4' and t5' were set to 2 .mu.m. Moreover, the wiring length was set to 2 mm.

(Confirmation of actions and effects)
The multilayer wiring board 12 according to the example and the multilayer wiring board 12' according to the comparative example were evaluated as follows.

(Evaluation method)
S-parameters were measured using a microwave network analyzer measurement system. Transmission characteristics (S21) were measured as S parameters.

(Evaluation results)
The multilayer wiring board 12 according to the example had S21 of −1.3 dB at 10 GHz. On the other hand, the multilayer wiring board 12' according to the comparative example had S21 of -2 dB at 10 GHz. Thus, the multilayer wiring board 12 according to the example exhibited high electrical properties.

DESCRIPTION OF SYMBOLS 1... Packaged device, 2... Support body, 3... Release layer, 4a... Adhesion layer, 4b... Seed layer, 10... Composite wiring board, 11... FC-BGA board, 12... Multilayer wiring board, 12'... Multilayer wiring Substrate 13 Sealing resin layer 14 Joining electrode 20 Functional device 30 Sealing resin layer 40 Joining electrode 50 Laser light 111 Core layer 112 Insulating layer 113 Conductor layer , 114... Insulating layer 115... Joining conductor 121... Resist layer 122... Conductor layer 123... Insulating resin layer 124... Insulating resin layer 125... Dummy layer 126... Layer 126'... Layer 1261a... First metal-containing layer 1261a′ First metal-containing layer 1261b Second metal-containing layer 1261b′ Second metal-containing layer 1262 Conductor layer 1262′ Conductor layer 1262L Land portion 1262L′ Land portion 1262V Via portion 1262V' Via portion 1262W Wiring portion 1262W' Wiring portion 1263 Insulating resin layer 127a Adhesion layer 127b Seed layer 128 Resist layer 129 Conductor Layer 130...Insulating resin layer 131...Surface treatment layer 132...Joining conductor G...Groove part G'...Groove part R1...First concave part R1'...Through hole R2...Second concave part S1...First surface, S2 . . . second surface;

Claims (12)

comprising two or more layers laminated together, each of said two or more layers comprising:
an insulating resin layer having a first surface and a second surface that is the back surface thereof, the insulating resin layer being provided with a groove portion opened on the first surface;
a conductor layer including a wiring portion embedded in the groove portion of the insulating resin layer;
a first metal-containing layer covering the surface of the wiring portion on the first surface side without covering the side surface of the wiring portion;
A second metal comprising a portion interposed between the first metal-containing layer and the wiring section and a portion covering the side surface of the wiring section, and made of a metal material different from the material of the first metal-containing layer. A multilayer wiring board including a containing layer. 2. The multilayer wiring board according to claim 1, wherein each two adjacent layers of the two or more layers are in contact with the insulating resin layers. The insulating resin layer is integrally formed in the thickness direction,
The insulating resin layer is further provided with a first recess opening on the first surface and a second recess opening on the second surface and communicating with one or more of the first recesses,
The conductor layer further includes a land portion embedded in the first concave portion of the insulating resin layer and a via portion protruding from the first surface at the position of the land portion,
the via portion fills a concave portion of another insulating resin layer adjacent to the first surface side;
3. The first metal-containing layer according to claim 1, wherein the first metal-containing layer does not cover the side surface of the land portion, but further covers the surface of the land portion on the first surface side and the side surface of the via portion. A multilayer wiring board as described. 4. The multilayer wiring board according to claim 1, wherein said insulating resin layer is made of a non-photosensitive resin. 5. The multilayer wiring board according to claim 1, wherein said first metal-containing layer contains titanium, and said second metal-containing layer contains copper. 6. The multilayer wiring board according to claim 1, wherein said portion of said second metal-containing layer covering the side surface of said wiring portion has an arithmetic mean roughness Ra of 10 nm or less. A first wiring board and a second wiring board joined to the first wiring board, wherein the first and second wiring boards are electrically connected to each other via a joining electrode interposed therebetween. A composite wiring board, wherein the second wiring board is the multilayer wiring board according to any one of claims 1 to 6. 8. The composite wiring board according to claim 7, wherein the first wiring board is a flip-chip ball grid array wiring board, and the second wiring board is an interposer. The composite wiring board according to claim 7 or 8;
and a functional device mounted on a surface of the second wiring substrate opposite to the first wiring substrate. forming two or more layers that are laminated, wherein forming each of said two or more layers comprises:
forming a recess in the insulating resin layer;
forming a dummy layer having a groove and at least one through hole communicating with the recess on the insulating resin layer;
forming a first metal-containing layer covering the upper surface of the dummy layer and the inner surfaces of the recess, the groove, and the through hole;
forming a second metal-containing layer made of a different metal material from the first metal-containing layer on the first metal-containing layer;
forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole;
polishing the conductor layer so as to remove portions positioned outside the recesses, the grooves, or the through holes; and obtaining the portions in which the grooves are embedded as a via portion, a land portion, and a wiring portion, respectively;
then removing the dummy layer;
removing exposed portions of the first metal-containing layer;
A method of manufacturing a multilayer wiring board, comprising: providing an insulating resin layer that covers the conductor layer and fills a gap between the land portion and the wiring portion. 11. The method of manufacturing a multilayer wiring board according to claim 10, wherein the dummy layer is made of a photosensitive resin. 12. The method of manufacturing a multilayer wiring board according to claim 10, wherein the insulating resin layer is made of a non-photosensitive resin.

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