JP2023083003A - wiring board - Google Patents

Abstract

To provide a wiring board which is less likely to be cracked by heat application.SOLUTION: A wiring board 12 comprises: a first insulating layer 1241 which has a first surface and a second surface that is a rear face thereof, and which is provided with a first through-hole R1 extending from the first surface to the second surface; a second insulating layer 1242 which is provided on the second surface, and which is provided with a second through-hole R2 communicating with the first through-hole R1, and a groove G; and a conductor layer including a via part 1244V which embeds the first through-hole R1, a land part 1244L which embeds the second through-hole R2, and a wiring part 1244W which embeds the groove G. In a region located between the land part 1244L and the wiring part 1244W, which is part of a boundary surface between the first insulating layer 1241 and the second insulating layer 1242, a position adjacent to the land part 1244L and a position away from the land part 1244L have different heights.SELECTED DRAWING: Figure 2

Description

The present invention relates to wiring boards.

In recent years, as semiconductor devices have become faster and more highly integrated, wiring substrates for flip chip-ball grid arrays on which semiconductor chips are mounted, ie, FC-BGA substrates, are also equipped with semiconductor chips. There is a demand for a narrower pitch of the connecting terminals used for bonding between the substrates and a finer wiring in the substrate. On the other hand, the connection between the FC-BGA substrate and the mother board is required to use connection terminals arranged at substantially the same pitch as in the past. Based on these demands, a technique of providing a multi-layer wiring board including fine wiring, also called an interposer, between the FC-BGA board and the semiconductor chip has been adopted.

One of them is silicon interposer technology. This silicon interposer technology manufactures an interposer by forming a multi-layered wiring structure in which each layer includes fine wiring on a silicon wafer using a semiconductor circuit manufacturing technology.

Also, a technique has been developed in which the multilayer wiring structure described above is not formed on a silicon wafer but directly built into an FC-BGA substrate. According to this technique, the multi-layered wiring structure is formed by chemical mechanical polishing (CMP) or the like in the manufacture of an FC-BGA substrate whose core layer is made of, for example, a glass epoxy substrate. This is disclosed in US Pat.

Further, an interposer is formed on a support such as a glass substrate, the interposer is bonded to the FC-BGA substrate, and then the support is peeled off from the interposer, thereby forming the above multilayer wiring structure on the FC-BGA substrate. There is also a method (hereinafter referred to as a transfer method) provided above. This is disclosed in Patent Document 2.

Wiring included in the multilayer wiring structure can be fabricated by a semi-additive method. Such a method is disclosed in US Pat.

JP 2014-225671 A WO2018/047861 JP 2018-22894 A

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring board that is less likely to crack due to heating.

According to one aspect of the present invention, the first insulating layer has a first surface and a second surface that is the back surface thereof, and is provided with a first through hole extending from the first surface to the second surface. a first insulating layer, a second insulating layer provided on the second surface, the second insulating layer provided with a second through hole communicating with the first through hole, and a groove portion; a conductor layer including a via portion in which the first through hole is embedded, a land portion in which the second through hole is embedded, and a wiring portion in which the groove portion is embedded; A wiring board is provided in which a region positioned between the land portion and the wiring portion in the interface with the layer has different heights between a position adjacent to the land portion and a position spaced apart from the land portion.

According to still another aspect of the present invention, there is provided the wiring board according to the above aspect, wherein the position adjacent to the land is farther from the first surface than the position spaced apart from the land. be done.

According to still another aspect of the present invention, according to any one of the above aspects, the first insulating layer is further provided with a recess opening at the second surface, and the groove is open at the bottom surface of the recess. A wiring board is provided.

According to still another aspect of the present invention, the ratio D/T between the depth D of the recess and the thickness T of the first insulating layer at the location adjacent to the land is between 0.5 and 0.99. A wiring substrate according to any of the above aspects is provided.

According to still another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein a plurality of the wiring portions are present in one recess.

According to still another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the concave portion has a forward tapered shape.

According to still another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the wiring portion has a constant thickness in its length direction.

According to still another aspect of the present invention, it further includes an insulating resin layer that fills the first insulating layer side portion of the groove, and the wiring portion fills a portion of the groove that is not filled with the insulating resin layer. A wiring board according to any of the above aspects is provided.

According to still another aspect of the present invention, the wiring board according to any of the above aspects further includes a first metal-containing layer covering the side and bottom surfaces of the conductor layer, wherein the first metal-containing layer contains titanium. provided.

According to still another aspect of the present invention, a metal layer is interposed between the first metal-containing layer and the conductor layer and is made of the same material as the conductor layer or has a lower ionization tendency than the material of the conductor layer. A wiring board according to the above aspect is provided, further comprising a second metal-containing layer made of a metallic material, wherein the second metal-containing layer is made of copper.

According to still another aspect of the present invention, an insulating layer and a conductor layer embedded in the insulating layer and including a wiring portion, a land portion and a via portion are provided, and the thickness T1 of the wiring portion is equal to that of the land portion. A wiring substrate having a thickness greater than T2 is provided.

According to still another aspect of the present invention, there is provided the wiring board according to the above aspect, wherein a ratio T1/T2 between the thickness T1 of the wiring portion and the thickness T2 of the land portion is larger than 1 and smaller than 2.

According to still another aspect of the present invention, a first wiring board and a second wiring board bonded to the first wiring board are provided, and the first wiring board and the second wiring board have a bonding structure interposed therebetween. A composite wiring board is provided which is electrically connected to each other via electrodes, and wherein the second wiring board is a wiring board according to any of the above aspects.

According to still another aspect of the present invention, there is provided the composite wiring board according to the above aspect, wherein the first wiring board is a flip-chip ball grid array wiring board, and the second wiring board is an interposer.

According to still another aspect of the present invention, a package including a wiring board according to any one of the above aspects and a functional device mounted on a surface of the second wiring board opposite to the first wiring board. A device is provided.

Here, the "functional device" is a device that operates by being supplied with at least one of electric power and electric signals, a device that outputs at least one of electric power and electric signals in response to an external stimulus, or a device that outputs at least one of electric power and electric signals. It is a device that operates when supplied with at least one of them and outputs at least one of electric power and electrical signals in response to stimulation from the outside. A functional device is in the form of a chip, for example, a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. A functional device can include, for example, one or more of a large scale integrated circuit (LSI), a memory, an imaging device, a light emitting device, and MEMS (Micro Electro Mechanical Systems). MEMS are, for example, one or more of pressure sensors, acceleration sensors, gyro sensors, tilt sensors, microphones, and acoustic sensors. According to one example, the functional device is a semiconductor chip including an LSI.

According to still another aspect of the present invention, a first insulating layer having a first through hole and a recess is formed on a release layer provided on a support; forming a second insulating layer having a second through hole communicating with the first through hole and at least one groove; forming the first through hole and the second through hole on the second insulating layer; and forming a conductor layer so as to fill the trench.

According to still another aspect of the present invention, there is provided the wiring board manufacturing method according to the above aspect, wherein the concave portion has a forward tapered shape.

According to still another aspect of the present invention, there is provided the wiring substrate manufacturing method according to any one of the above aspects, wherein the support is made of glass.

According to still another aspect of the present invention, there is provided the wiring board manufacturing method according to any one of the above aspects, wherein both the first and second insulating layers are made of a photosensitive resin.

According to the present invention, there is provided a wiring substrate that is less likely to crack due to heating.

1 is a schematic cross-sectional view of a packaged device according to an embodiment of the invention; FIG. FIG. 2 is a schematic cross-sectional view of a wiring substrate included in the packaged device shown in FIG. 1; FIG. 3 is a cross-sectional view schematically showing a part of the wiring board shown in FIG. 2; FIG. 4 is a cross-sectional view schematically showing one step in the method of manufacturing a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 15 is a top view schematically showing an example of the structure obtained in the process of FIG. 14; FIG. 4 is a cross-sectional view schematically showing a step in a wiring board manufacturing method according to another embodiment of the present invention; FIG. 5 is a cross-sectional view schematically showing a step in a wiring board manufacturing method according to still another embodiment of the present invention; FIG. 5 is a cross-sectional view schematically showing a step in a wiring board manufacturing method according to still another embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing one step of a method of manufacturing a packaged device according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing another step of the method of manufacturing a packaged device according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step of the method of manufacturing a packaged device according to one embodiment of the present invention; Sectional drawing which shows roughly the wiring board which concerns on a comparative example.

Embodiments of the present invention will be described below with reference to the drawings. The embodiments described below embody any of the above aspects more specifically. The embodiments shown below are examples embodying the technical idea of the present invention. It is not limited. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

In the drawings referred to in the following description, the same reference numerals are given to components having the same or similar functions. Here, the drawings are schematic, and the relationship between the dimension in the thickness direction and the direction perpendicular to the thickness direction, that is, the dimension in the in-plane direction, the relationship between the dimensions in the thickness direction of a plurality of layers, etc. , may differ from reality. Therefore, specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationships of two or more components may differ between the drawings. It should also be noted that in some drawings the same structure is shown upside down from other drawings.

In the present disclosure, the “upper surface” and the “lower surface” refer to the two main surfaces of the plate-shaped member or the layer included therein, that is, the surface perpendicular to the thickness direction and having the largest area and the back surface thereof. , respectively denote the surface shown above and the surface shown below in the drawing. In addition, "side surface" means a surface that is perpendicular to or inclined with respect to the main surface.

Also, in this disclosure, the description "AA on top of BB" is used regardless of the direction of gravity. The condition identified by the statement "AA on BB" encompasses the condition where AA is in contact with BB. Reference to "AA over BB" does not exclude the interposition of one or more other components between AA and BB.

<Structure>
FIG. 1 is a schematic cross-sectional view of a packaged device according to one embodiment of the present invention.

A packaged device 1 shown in FIG. 1 includes a composite wiring board 10, a functional device 20, a sealing resin layer 30, and a bonding electrode 40. As shown in FIG.

The functional device 20 is, for example, a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. Here, as an example, functional device 20 is assumed to be a semiconductor chip. That is, here the packaged device 1 is a semiconductor package.

Packaged device 1 includes a plurality of functional devices 20 . Packaged device 1 may include only one functional device 20 .

The functional device 20 is bonded to the composite wiring board 10 via bonding electrodes 40 . Here, the functional device 20 is bonded to the composite wiring board 10 by flip chip bonding. One or more of functional devices 20 may be bonded to composite wiring board 10 by other bonding methods such as wire bonding.

The bonding electrodes 40 are arranged with a narrow pitch between the functional device 20 and the composite wiring board 10 . The joint electrode 40 is made of solder, for example. When bonding the functional device 20 to the composite wiring board 10 by wire bonding, for example, gold wires can be used to electrically connect the functional device 20 and the composite wiring board.

The sealing resin layer 30 includes a portion interposed between the functional device 20 and the composite wiring board 10 and a portion at least partially covering the side surfaces of the functional device 20 . The sealing resin layer 30 fixes the functional device 20 to the composite wiring board 10 .

The composite wiring board 10 includes an FC-BGA board 11, a wiring board 12, a sealing resin layer 13, and bonding electrodes .

The FC-BGA board 11 is an example of a first wiring board. The FC-BGA substrate 11 is bonded to, for example, a mother board (not shown).

The FC-BGA substrate 11 includes a core layer 111 , an insulating layer 112 , a conductor layer 113 , an insulating layer 114 and a joining conductor 115 .

Core layer 111 is an insulating layer. The core layer 111 is, for example, a fiber-reinforced substrate made of woven fabric or non-woven fabric impregnated with a thermosetting insulating resin. As woven or non-woven fabrics, for example glass fibres, carbon fibres, or aramid fibres, can be used. For example, an epoxy resin can be used as the insulating resin.

The core layer 111 is provided with through holes. A portion of the conductor layer 113 covers the side wall of the through hole. Here, part of the conductor layer 113 covers the sidewalls of the through holes provided in the core layer 111 so as to form through holes with conductor sidewalls. These through-holes whose side walls are made of a conductor may be filled with an insulator.

The rest of the conductor layer 113 and the insulating layer 112 form a multilayer wiring structure on both main surfaces of the core layer 111 . Each multilayer wiring structure includes conductor layers 113 and insulating layers 112 that are alternately laminated.

Each insulating layer 112 included in the multilayer wiring structure is, for example, an insulating resin layer. Through holes are provided in the insulating layer 112 .

The conductor layer 113 is made of a metal such as copper or an alloy. The conductor layer 113 may have a single layer structure or a multilayer structure.

Each conductor layer 113 included in the multilayer wiring structure includes a wiring portion and a land portion. The conductor layer 113 facing the core layer 111 with the insulating layer 112 therebetween further includes a via portion covering the side wall of the through hole provided in the insulating layer 112 .

An insulating layer 114 is provided on the multilayer wiring structure. The insulating layer 114 is, for example, an insulating resin layer such as a solder resist. The insulating layer 114 is provided with through-holes communicating with the conductor layer 113 located on the outermost surface of the multilayer wiring structure.

The bonding conductor 115 is a metal bump provided on the exposed portion of the conductor layer 113 at the position of the through hole of the insulating layer 114 . Note that the joining conductor is also called a joining terminal. The joining conductor 115 is made of solder, for example.

The wiring board 12 is a second wiring board. The wiring substrate 12 is bonded to the functional device 20 via the bonding electrodes 40 and bonded to the FC-BGA substrate 11 via the bonding electrodes 14 . That is, the wiring board 12 is an interposer that mediates bonding between the functional device 20 and the FC-BGA board 11 . The thickness of the wiring board 12 is, for example, within a range of 10 μm or more and 300 μm or less. The wiring board 12 will be detailed later.

The junction electrodes 14 are arranged between the wiring board 12 and the functional device 20 . The pitch of the bonding electrodes 14 is wider than the pitch of the bonding electrodes 40 and narrower than the pitch of the bonding conductors 115 located on the bottom surface of the FC-BGA substrate 11 . The joint electrode 14 is made of solder, for example.

The sealing resin layer 13 includes a portion interposed between the FC-BGA substrate 11 and the wiring substrate 12 . Note that the sealing resin layer is also called an underfill layer. The sealing resin layer 13 fixes the second wiring board 12 to the FC-BGA board 11 .

The wiring board 12 will be described in more detail with reference to FIG.
FIG. 2 is a cross-sectional view schematically showing wiring substrate 12 included in packaged device 1 shown in FIG. 3 is a cross-sectional view schematically showing a portion of the wiring board shown in FIG. 2. FIG.

2 and 3, the wiring substrate 12 shown in FIG. It includes layer 125 b , conductor layer 127 , insulating resin layer 128 and surface treatment layer 129 .

Here, two layers 124 are laminated. The number of layers 124 may be three or more.

Each of these layers 124 includes a first insulating layer 1241 , a second insulating layer 1242 , a first metal-containing layer 1243 a, a second metal-containing layer 1243 b and a conductor layer 1244 .

First insulating layer 1241 is preferably made of an insulating resin that does not contain filler.

The first insulating layer 1241, as shown in FIGS. 2 and 3, has a first surface S1 and a second surface S2 which is the rear surface thereof. A plurality of first through holes R1 and recesses C are provided in the first insulating layer 1241 .

The first through hole R1 extends from the first surface S1 to the second surface S2. The first through hole R1 is a via hole filled with a via portion 1244V, which will be described later.

The first through holes R1 have the same depth. Here, the first through hole R1 has a shape in which the dimension in the direction perpendicular to the thickness direction gradually decreases from the opening on the upper surface side toward the opening on the lower surface side. According to one example, the first through hole R1 has a truncated cone shape. The first through hole R1 may have a rectangular cross section parallel to the thickness direction. That is, the first through hole R1 may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction.

The recess C has an opening, side walls and a bottom surface. The recess C is open on the second surface S2. The bottom surface of the recess C is a plane perpendicular to the thickness direction. The recess C here has a shape in which the dimension in the direction perpendicular to the length direction gradually decreases from the opening toward the bottom. That is, the concave portion C here has a forward tapered cross section perpendicular to the length direction.

The second insulating layer 1242 is provided on the second surface S<b>2 of the first insulating layer 1241 . A plurality of second through holes R2 and a plurality of grooves G are provided in the second insulating layer 1242 . Second insulating layer 1242 is preferably made of an insulating resin that does not contain filler.

Here, the groove portion G extends from the top surface to the bottom surface of the second insulating layer 1242 . Here, the bottom surface of the groove portion G is the top surface of the first insulating layer 1241 . That is, the groove G is open at the bottom surface of the recess C. As shown in FIG. The groove G has a shape in which the dimension in the direction perpendicular to the thickness direction gradually decreases from the opening on the upper surface side toward the opening on the lower surface side. According to one example, the groove G has a frusto-conical shape. The groove G may have a rectangular cross section parallel to the thickness direction. The groove portion G is embedded with a wiring portion 1244W, which will be described later. Here, the depth of the groove portion G is greater than the depth of the second through hole R2.

One or more of the second through holes R2 communicate with one of the grooves G. One or more of the second through holes R2 communicate with the first through holes R1. The second through-hole R2 is a land concave portion embedded with a land portion 1244L, which will be described later.

The second through holes R2 have the same depth. Here, the second through hole R2 extends from the upper surface to the lower surface of the second insulating layer 1242. As shown in FIG. The second through hole R2 here has a shape in which the dimension in the direction perpendicular to the thickness direction gradually decreases from the opening on the upper surface side toward the opening on the lower surface side. According to one example, the second through hole R2 has a truncated cone shape. The second through hole R2 may have a rectangular cross section parallel to the thickness direction. That is, the second through hole R2 may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction.
The orthogonal projection of the first through hole R1 onto a plane perpendicular to the thickness direction is surrounded by the outline of the orthogonal projection onto the plane beyond the lower opening of the second through hole R2 communicating with the first through hole R1. ing.

Note that the first through hole R1, the first through hole R2, the groove portion G, and the recess portion C will be described in more detail later.

The conductor layer 1244 includes a via portion 1244V in which the first through hole R1, the second through hole R2 and the groove portion G are respectively embedded, a land portion 1244L, and a wiring portion 1244W. In each conductor layer 1244, each via portion 1244V is formed integrally with one of the land portions 1244L included in that conductor layer 1244. FIG. The thickness of the wiring portion 1244W included in one layer 124 is, for example, constant in its length direction.

The conductor layer 1244 is made of metal or alloy such as copper. According to one example, conductor layer 1244 comprises copper.

2 and 3, the first metal-containing layer 1243a is interposed between the conductor layer 1244 and the first insulating layer 1241 and between the conductor layer 1244 and the second insulating layer 1242. and a portion covering the surface of the conductor layer 1244 on the side of the first surface S1. That is, the first metal-containing layer 1243a is provided on the sidewalls and bottom surfaces of the via portion 1244V, the land portion 1244L and the wiring portion 1244W.

The first metal-containing layer 1243a is an adhesion layer that improves the adhesion of the second metal-containing layer 1243b to the first insulating layer 1241 and the second insulating layer 1242 and makes it difficult for the second metal-containing layer 1243b to peel off. This is the seed adhesion layer. The first metal-containing layer 1243a is a barrier layer that makes diffusion of metal from the conductor layer 1244 to the first insulating layer 1241 and the second insulating layer 1242 difficult. According to one example, the first metal-containing layer 1243a is a titanium-containing layer, such as a titanium oxide layer.

The second metal-containing layer 1243b is provided on the first metal-containing layer 1243a. That is, the second metal-containing layer 1243b is interposed between the first metal-containing layer 1243a and the conductor layer 1244. FIG. The second metal-containing layer 1243b is a seed layer that plays a role as a power feeding layer in film formation of the conductor layer 1244 by electroplating.

The second metal-containing layer 1243b is made of a metal material different from the material of the first metal-containing layer 1243a. The second metal-containing layer 1243b may be made of the same material as the conductor layer 1244. FIG. Alternatively, the second metal-containing layer 1243b may be made of a metal material that has a lower ionization tendency than the material of the conductor layer 1244 . Second metal-containing layer 1243b includes, for example, copper. When the second metal-containing layer 1243b contains copper, delamination is less likely to occur between the first insulating layer 1241 and the second metal-containing layer 1243b and between the second insulating layer 1242 and the second metal-containing layer 1243b. Even when the first insulating layer 1241 and the second insulating layer 1242 are made of the same material, the interface between the layers can be confirmed by observing a cross section parallel to the stacking direction with a scanning electron microscope, for example. be able to.

The insulating resin layer 121 is provided on one main surface of the multilayer wiring structure composed of the layer 124, as shown in FIG. The material of the insulating resin layer 121 may be the same as or different from the material of the first insulating layer 1241 .

The insulating resin layer 121 is provided with a through hole at the position of the via portion 1244V included in the layer 124 adjacent thereto. The through holes of the insulating resin layer 121 are filled with the conductor layer 123 .

The through holes of the insulating resin layer 121 extend from the upper surface of the insulating resin layer 121 to the lower surface of the insulating resin layer 121 . Here, it has a shape in which the dimension in the direction perpendicular to the thickness direction gradually decreases from the opening on the upper surface side toward the opening on the lower surface side. According to one example, this through hole has a truncated cone shape. The through hole may have a rectangular cross section parallel to the thickness direction. That is, the through hole may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction.

The conductor layer 123 fills the through holes of the insulating resin layer 121 . It is an electrode for joining the wiring board 12 and the functional device 20 . The conductor layer 123 is made of copper, for example.

The conductor layer 127 is provided at the land portion 1244L included in the layer 124 positioned above. The conductor layer 127 is made of a metal such as copper or an alloy.

The adhesion layer 122 a is interposed between the conductor layer 123 and the insulating resin layer 121 . The adhesion layer 122a is a layer that improves the adhesion of the seed layer 122b to the insulating resin layer 121 and makes it difficult for the seed layer 122b to peel off.

The seed layer 122 b is interposed between the adhesion layer 122 a and the conductor layer 123 . The seed layer 122b plays a role as a power supply layer in film formation of the conductor layer 123 by electroplating.

The adhesion layer 125a is interposed between the land portion 1244L included in the layer 124 located above and the conductor layer 127. As shown in FIG. The adhesion layer 125a is a layer that improves the adhesion of the seed layer 125b to the second insulating layer 1242 and makes it difficult for the seed layer 125b to peel off.

The seed layer 125b is provided on the adhesion layer 125a. The seed layer 125b plays a role as a power supply layer in film formation of the conductor layer 127 by electroplating.

The insulating resin layer 128 is provided on the layer 124 and the conductor layer 127 positioned above. Through holes are provided in the insulating resin layer 128 at the positions of the conductor layers 127 .

The surface treatment layer 129 is provided on the portion of the conductor layer 127 exposed in the through hole of the insulating resin layer 128 . The surface treatment layer 129 is provided to prevent oxidation of the surface of the conductor layer 127 and improve wettability with solder.

As shown in FIG. 2, two adjacent layers 124 are in contact with, for example, a first insulating layer 1241 on one side and a second insulating layer 1242 on the other side.
Further, as shown in FIG. 2, in a region located between the land portion 1244L and the wiring portion 1244W in the interface between the first insulating layer 1241 and the second insulating layer 1242, the position adjacent to the land portion 1244L is The distance from the first surface S1 is greater than the position away from the land portion 1244L, for example, the position of the bottom surface of the recess C.

A thickness T1 in FIG. 3 is the thickness of the wiring portion 1244W. The thickness T2 is the thickness of the land portion 1244L. Thickness T3 is the thickness of via portion 1244V.

As shown in FIG. 3, thickness T1, thickness T2, and thickness T3 satisfy inequality T2+T3>T1 and also satisfy inequality T1>T2 or inequality T3<T1. As shown in FIG. 3, the wiring board 12 includes an insulating layer and a conductor layer embedded in the insulating layer and including a wiring portion, a land portion and a via portion. greater than the thickness T2.

The thickness T1 of the wiring portion 1244W is preferably within the range of 0.5 μm to 30 μm, more preferably within the range of 0.7 μm to 20 μm.

The thickness T2 of the land portion 1244L is preferably in the range of 0.5 μm to 15 μm, more preferably in the range of 1 μm to 10 μm.

A thickness T3 of the via portion 1244V is preferably in the range of 0.5 μm to 15 μm, more preferably in the range of 1 μm to 10 μm.

A ratio T1/T2 between the thickness T1 of the wiring portion 1244W and the thickness T2 of the land portion 1244L is preferably larger than 0.4 and smaller than 2, and preferably larger than 1 and smaller than 2. If this ratio is too large, short circuits are likely to occur between two adjacent layers 124 . If this ratio is too small, it tends to be difficult to achieve high transmission characteristics.
At least one of the adhesion layer 122a, the first metal-containing layer 1243a, and the adhesion layer 125a may be omitted.

<Manufacturing method>
The wiring board 12 included in this packaged device 1 can be manufactured, for example, by the following method.

4 to 20 are cross-sectional views schematically showing a method of manufacturing a multilayer wiring board according to one embodiment of the present invention.

In this method, first, a release layer 3 is formed on one surface of a support 2, as shown in FIG.

Since the release layer 3 may be irradiated with light through the support 2, it is advantageous for the support 2 to have translucency. As the support 2, for example, a glass plate can be used. A rectangular glass plate is suitable for upsizing. Also, the glass plate can achieve excellent flatness and high rigidity. Therefore, the glass plate as the support 2 is suitable for forming fine patterns thereon.

In addition, since the glass plate has a small coefficient of thermal expansion (CTE) and is not easily distorted, it is excellent in ensuring pattern arrangement accuracy and flatness. When a glass plate is used as the support 2, the thickness of the glass plate is desirably thick from the viewpoint of suppressing the occurrence of warping in the manufacturing process, for example 0.5 mm or more, preferably 1.2 mm or more.

The CTE of the glass plate is preferably 3 ppm or more and 16 ppm or less, and more preferably about 10 ppm from the viewpoint of matching with the CTE of the FC-BGA substrate 11 and the functional device 20 .

As the glass, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, or the like is used.

On the other hand, if the support 2 is not required to have light transmittance when the support 2 is peeled off, such as using a resin that foams with heat for the release layer 3, the support 2 may be made of a material that causes less distortion, such as metal. or ceramics can be used.

In the following, as an example, it is assumed that the material of the release layer 3 is a resin that can be separated by absorbing ultraviolet light (UV light), and the support 2 is a glass plate.

The release layer 3 may be, for example, a resin that can be peeled by generating heat or changing properties by absorbing light such as UV light, or may be a resin that is foamed by heat and becomes peelable. Materials for the release layer 3 include, for example, organic resins such as epoxy resins, polyimide resins, polyurethane resins, silicone resins, polyester resins, oxetane resins, maleimide resins, and acrylic resins, amorphous silicon, gallium nitride, and metal oxides. It can be selected from inorganic layers such as monolayers. The release layer 3 may further contain additives such as a photodegradation accelerator, a light absorber, a sensitizer, and a filler.

The release layer 3 may have a single layer structure or a multilayer structure. Further, for example, a protective layer may be provided on the release layer 3 for the purpose of protecting the multilayer wiring structure formed on the support 2, and the adhesion between the support 2 and the release layer 3 may be improved. Additional enhancing layers may be provided. Further, a laser light reflecting layer or a metal layer may be further provided between the peeling layer 3 and the multilayer wiring structure.

When a resin that can be peeled off by light such as UV light, for example, laser light, is used as the material of the peeling layer 3 , if the support 2 is translucent, the peeling layer 3 can be formed through the support 2 . light may be applied.

Next, an insulating resin layer 121 is formed on the release layer 3, and then through holes are formed in the insulating resin layer 121 by photolithography.

The insulating resin layer 121 is made of, for example, a photosensitive resin. As the photosensitive resin, for example, photosensitive polyimide resin, photosensitive benzocyclobutene resin, photosensitive epoxy resin, or modified products thereof can be used. The photosensitive resin may be liquid or film-like.

When a liquid photosensitive resin is used as the material of the insulating resin layer 121, the insulating resin layer 121 is formed by, for example, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, It can be formed on the seed layer 122b by any of gravure offset printing, spin coating, and doctor coating. When a film resist is used as the insulating resin layer 121, the insulating resin layer 121 can be provided on the release layer 3 by any method such as lamination, vacuum lamination, or vacuum pressing.
Note that the insulating resin layer 121 may be made of a non-photosensitive resin. When a non-photosensitive resin is used as the material of the insulating resin layer 121, the through holes can be formed by, for example, laser light irradiation.

Here, as an example, a photosensitive epoxy resin is applied onto the release layer 3 by spin coating. A photosensitive epoxy resin can be cured at a relatively low temperature, and shrinkage due to curing is small, which is advantageous for subsequent fine pattern formation.

The planar view shape of the through holes is set according to the pitch and shape of the bonding electrodes of the functional device 20 . The thickness of the insulating resin layer 121 is set according to the thickness of the conductor layer 123 to be formed next.
After forming the through holes, plasma treatment may be performed for the purpose of removing residues during development.

Next, as shown in FIG. 5, an adhesion layer 122a and a seed layer 122b are formed on the insulating resin layer 121 and on the portion of the release layer 3 not covered with the insulating resin layer 121. Next, as shown in FIG. The adhesion layer 122a is a layer that improves the adhesion of the seed layer 122b to the peeling layer 3 and prevents the peeling of the seed layer 122b in subsequent steps. Also, the seed layer 122b plays a role as a power feeding layer in electroplating for forming the conductor layer 122. As shown in FIG.

The adhesion layer 122a and the seed layer 122b can be formed by sputtering or vapor deposition, for example. Materials for the adhesion layer 122a and the seed layer 122b include, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO ( Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum-doped Zinc _Oxide ), ZnO, PZT (lead zirconate titanate), TiN, _Cu3N4 , Cu alloy, or a combination of these can be used. Here, as an example, in consideration of electrical characteristics, ease of manufacture, and cost, a titanium layer and a copper layer are used for the adhesion layer 122a and the seed layer 122b, respectively, and they are formed by a sputtering method. and When a titanium layer and a copper layer are used for the adhesion layer 122a and the seed layer 122b, respectively, the adhesion between the conductor layer 123 and the insulating resin layer 121 is particularly excellent.

The total thickness of the adhesion layer 122a and the seed layer 122b is preferably 1 μm or less. Here, as an example, a titanium layer with a thickness of 50 nm is formed as the adhesion layer 122a, and a copper layer with a thickness of 300 nm is formed as the seed layer 122b.

Next, as shown in FIG. 6, a conductor layer 123 is formed on the seed layer 122b by electroplating. The conductor layer 123 constitutes, for example, an electrode for bonding with the functional device 20 . Examples of electrolytic plating for forming the conductor layer 123 include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, and the like. Among these, electrolytic copper plating is desirable because it is simple and inexpensive and can achieve good electrical conductivity.

The conductor layer 123 serves as an electrode for bonding with the functional device 20 as described above. Therefore, the thickness of the conductor layer 123 is desirably 1 μm or more from the viewpoint of solder joint, and desirably 30 μm or less from the viewpoint of productivity.

Next, as shown in FIG. 7, the upper surface of the conductor layer 123 is exposed by physical polishing or physical polishing and chemical mechanical polishing (CMP). The structure obtained in this way can also be obtained by a damascene method.

Next, as shown in FIG. 8, a first insulating layer 1241 is provided on the conductor layer 123 and the insulating resin layer 121 .

The first insulating layer 1241 is made of, for example, photosensitive resin. As this photosensitive resin, for example, the same material as described above for the insulating resin layer 121 can be used. The first insulating layer 1241 can be formed, for example, by a method similar to that described above for the insulating resin layer 121 .

Next, as shown in FIG. 9, the first insulating layer 1241 is provided with the first through hole R1 and the concave portion C. Then, as shown in FIG. The first through hole R<b>1 is provided at the position of the conductor layer 123 . The recess C is open on the upper surface of the first insulating layer 1241 .

The first through hole R1 may be formed so that the cross section perpendicular to the thickness direction of the first insulating layer 1241 has a rectangular shape. It is preferable to form the shape so as to gradually decrease from the opening toward the opening on the lower surface side. Forming in this manner facilitates the formation of the first metal-containing layer 1243a and the second metal-containing layer 1243b without causing a discontinuous portion in the first through hole R1.

α shown in FIG. 9 is the angle formed by the bottom surface of the recess C and the side wall of the recess C. As shown in FIG. The angle α preferably satisfies the inequality 0°<α<90°. That is, the concave portion C preferably has a forward tapered cross section perpendicular to the length direction. When the concave portion C has a forward tapered shape, when the wiring substrate 12 and the FC-BGA substrate 11 are joined, cracks are less likely to occur at the position where the side wall and the bottom surface of the concave portion C are in contact with each other.

The depth D of the recess C is preferably in the range of 0.25 μm to 29.75 μm, more preferably in the range of 0.75 μm to 19.75 μm.

The thickness of the first insulating layer 1241, that is, the thickness T of the first insulating layer 1241 at the position adjacent to the land portion 1244L is preferably in the range of 0.5 μm to 15 μm, more preferably in the range of 1 μm to 10 μm. is more preferable.

A ratio D/T between the depth D and the thickness T is preferably in the range of 0.5 to 0.99, more preferably in the range of 0.75 to 0.98. more preferred.

The first through hole R1 and the recess C can be formed by photolithography, for example. For example, when a positive photoresist is used, the first through hole R1 and the concave portion C are formed by making the exposure amount when forming the concave portion C smaller than the exposure amount when forming the first through hole R1. can be formed by

Next, as shown in FIG. 10, a second insulating layer 1242 is provided on the first insulating layer 1241 . The second insulating layer 1242 is made of, for example, photosensitive resin. As the photosensitive resin, for example, materials similar to those described above for the insulating resin layer 121 can be used. The second insulating layer 1242 can be formed, for example, by a method similar to that described above for the insulating resin layer 121 .

Next, as shown in FIG. 11, the second insulating layer 1242 is provided with a second through hole R2, one or more of which communicates with the first through hole R1, and a groove portion G. Next, as shown in FIG.

The second through hole R2 is formed to have a larger opening diameter at its upper surface than the opening diameter of the first through hole R1 of the first insulating layer 1241 at its upper surface. Here, the groove G is provided so as to open at the bottom surface of the recess C. As shown in FIG.

The second through hole R2 may be formed so that the cross section perpendicular to the thickness direction of the second insulating layer 1242 has a rectangular shape. It is preferable to form the shape so as to gradually decrease from the opening toward the opening on the lower surface side. The groove G is also preferably formed so that the dimension in the direction perpendicular to the thickness direction gradually decreases from the opening on the upper surface side toward the opening on the lower surface side. In this case, it becomes easy to form the first metal-containing layer 1243a and the second metal-containing layer 1243b without causing discontinuous portions in the groove G and the second through hole R2.

Next, as shown in FIG. 12, a first metal-containing layer covering the upper surface of the first insulating layer 1241, the inner surface of the first through hole R1, the inner surface of the groove portion G, and the inner surface of the second through hole R2 1243a. Subsequently, a second metal-containing layer 1243b made of a metal material different from that of the first metal-containing layer 1243a is formed on the first metal-containing layer 1243a.

The first metal-containing layer 1243a and the second metal-containing layer 1243b are a seed adhesion layer (or adhesion layer) and a seed layer, respectively. The first metal-containing layer 1243a and the second metal-containing layer 1243b can use the same materials as described above for the adhesion layer 122a and the seed layer 122b, respectively. Also, the first metal-containing layer 1243a and the second metal-containing layer 1243b can be formed by methods similar to those described above for the adhesion layer 122a and the seed layer 122b, respectively.

The material of the second metal-containing layer 1243b is preferably the same material as the conductor layer 1244, or a metal material with a lower ionization tendency than the material of the conductor layer 1244. When the material of the second metal-containing layer 1243b has a lower ionization tendency than the material of the conductor layer 1244, the second metal-containing layer 1243b prevents metal from diffusing from the conductor layer 1244 to the first insulating layer 1241 and the second insulating layer 1242. easy to prevent.

The sum of the thickness of the first metal-containing layer 1243a and the thickness of the second metal-containing layer 1243b is preferably 1 μm or less. In this case, it is preferable as a power supply layer for electroplating.

The thickness of the first metal-containing layer 1243a is preferably in the range of 10 nm to 100 nm, more preferably in the range of 30 nm to 80 nm.

The thickness of the second metal-containing layer 1243b is preferably in the range of 40 nm to 400 nm, more preferably in the range of 100 nm to 350 nm.

Here, as an example, in consideration of electrical characteristics, ease of manufacture, and cost, furthermore, the adhesion between the first and second insulating layers and the second metal-containing layer 1243b is improved, and the conductor layer A layer containing titanium is employed as the first metal-containing layer 1243a to prevent diffusion of the material of 1244, eg, copper. In addition, a layer containing copper is adopted as the second metal-containing layer 1243b in consideration of electrical characteristics, ease of manufacture, and cost. The first metal-containing layer 1243a and the second metal-containing layer 1243b are sequentially formed by sputtering.

As the material for the first metal-containing layer 1243a, a material for the second metal-containing layer 1243b, for example, a material other than titanium may be applied as long as it has a copper diffusion preventing function. Also, between the first metal-containing layer 1243a and the second metal-containing layer 1243b, a layer made of a metal material different from the material of the first metal-containing layer 1243a and the material of the second metal-containing layer 1243b may be provided. .

Next, as shown in FIG. 13, a conductor layer 1244' is formed on the second metal-containing layer 1243b. The conductor layer 1244' is formed so as to fill the first through hole R1, the second through hole R2, and the groove portion G. As shown in FIG. Conductive layer 1244' can use the same materials as described above for conductive layer 123. FIG. Also, the conductor layer 1244 ′ can be formed by a method similar to that described above for the conductor layer 123 . Here, as an example, the conductor layer 1244' is assumed to be a copper layer formed by electrolytic plating.

Next, as shown in FIG. 14, the conductor layer 1244′, the first metal-containing layer 1243a, and the second metal-containing layer 1243b are subjected to physical polishing and polishing such as CMP to obtain the conductor layer 1244′ and the first metal-containing layer 1244′. A portion of the layer 1243a and the second metal-containing layer 1243b located outside the first through hole R1, the second through hole R2, or the groove portion G is removed. In addition, along with this polishing, the portion near the upper surface of the second insulating layer 1242 may also be removed. Of the conductor layer 1244' shown in FIG. 13, the conductor layer 1244 shown in FIG. 14 is the portion left after the above polishing.
As described above, of the conductor layer 1244, the portion in which the first through hole R1 is embedded, the portion in which the second through hole R2 is embedded, and the portion in which the groove portion G is embedded are formed into via portions 1244V and land portions 1244L, respectively. and a wiring portion 1244W.

The sequence of steps described with reference to FIGS. 8-14 is then repeated. As a result, the multilayer wiring structure shown in FIG. 15 is obtained. That is, a multilayer wiring structure including two layers 124 is obtained. By repeating the above sequence two or more times, the number of layers 124 included in the multilayer wiring structure can be increased to three or more.

Next, as shown in FIG. 16, an adhesion layer 125a is formed on the upper surface of the upper layer 124. Next, as shown in FIG. Subsequently, a seed layer 125b made of a metal material different from the material of the adhesion layer 125a is formed on the adhesion layer 125a. The seed layer 125b is preferably made of the same material as the conductor layer 127 or made of a metal material having a lower ionization tendency than the material of the conductor layer 127. FIG.

For the adhesion layer 125a and the seed layer 125b, materials similar to those described above for the adhesion layer 122a and the seed layer 122b, respectively, can be used. Further, the adhesion layer 125a and the seed layer 125b can be formed by the same method as described above for the adhesion layer 122a and the seed layer 122b, respectively. Here, as an example, a titanium layer with a thickness of 50 nm is formed as the adhesion layer 125a, and a copper layer with a thickness of 300 nm is formed as the seed layer 125b.

Next, as shown in FIG. 17, a resist layer 126 having through holes is formed on the seed layer 125b.

The resist layer 126 is made of, for example, a photosensitive resin. The resist layer 126 can be made of the same materials as those described above for the insulating resin layer 121 . Also, the resist layer 126 can be formed by the same method as described above for the insulating resin layer 121 .

Next, as shown in FIG. 18, a conductor layer 127 is formed on the seed layer 125b. Conductor layer 127 can use the same materials as those described above for conductor layer 123 . Conductor layer 127 can be formed by a method similar to that described above for conductor layer 123 . Like the conductor layer 123, the conductor layer 127 is desirably an electrolytic copper plating layer.

Next, as shown in FIG. 19, the resist layer 126 is removed. The resist layer 126 is removed by, for example, a dry etching method, or dissolved or peeled off by immersion in an alkaline solution or solvent.

Next, the exposed portions of the adhesion layer 125a and the seed layer 125b are removed. The adhesion layer 125a and the seed layer 125b can be removed, for example, by immersion in a chemical solution. As the chemical solution, for example, a chemical solution containing hydrogen peroxide can be used.

Next, as shown in FIG. 20, an insulating resin layer 128 is formed on the second insulating layer 1242 and the conductor layer 127. Next, as shown in FIG. The insulating resin layer 128 has through holes at the positions of the conductor layers 127 . The insulating resin layer 128 can be formed, for example, by providing a solder resist on the second insulating layer 1242 and the conductor layer 127 and exposing and developing it. An insulating layer obtained from a solder resist is also called a solder resist layer.

As a material for the solder resist, for example, an insulating resin containing a filler, such as an epoxy resin or an acrylic resin, can be used.

Next, a surface treatment layer 129 is provided on the conductor layer 127 . The surface treatment layer 129 is provided for the purpose of preventing oxidation of the surface of the conductor layer 127 and improving wettability with solder. Here, as an example, an electroless Ni/Pd/Au plating layer is formed as the surface treatment layer 129 .

As the surface treatment layer 129, an OSP (Organic Solderability Preservative) film, that is, a surface treatment layer using a water-soluble preflux may be formed. Alternatively, as the surface treatment layer 129, an electroless tin plated layer or an electroless Ni/Au plated layer may be formed.

Next, a bonding conductor 130 is formed on the surface treatment layer 129 . The bonding conductors 130 are, for example, metal bumps such as solder bumps. The joining conductor 130 can be formed, for example, by placing a solder material such as a solder ball on the surface treatment layer 129 , melting them, and then cooling and fixing them to the surface treatment layer 129 . Solder material is not particularly limited.

As described above, the wiring board 12 supported by the support 2, that is, the wiring board with support is obtained.

21 is a top view schematically showing an example of the structure obtained by the process of FIG. 14. FIG. The wiring portion 1244W and the land portion 1244L shown in FIG. 21 are not electrically connected to each other. A dashed line PC shown in FIG. 21 indicates the contour of the bottom surface of one recess C. As shown in FIG. As shown in FIG. 21, a plurality of wiring portions 1244W are present in one recess C. As shown in FIG.

As shown in FIG. 22, in the wiring substrate 12 described above, the first insulating layer 1241 adjacent to the insulating resin layer 121 is composed of an inorganic insulating layer 1241a in a portion adjacent to the insulating resin layer 121, and the other insulating layer 1241a. A portion may be made of the organic insulating layer 1241b. In addition, as shown in FIG. 22, in the two layers 124 laminated to each other, the first insulating layer 1241 included in the upper layer 124 has an inorganic insulating layer 1241a in the portion adjacent to the lower layer 124, The other portion may consist of the organic insulating layer 1241b. The material of the organic insulating layer 1241b is, for example, the same material as described above for the insulating resin layer 121 .

Since the inorganic insulating layer 1241a has a high Young's modulus, it is difficult to bend. Therefore, in the wiring board 12 provided with the inorganic insulating layer 1241a, for example, when the wiring board 12 and the FC-BGA board 11 are joined together, warping of the wiring board 12 is suppressed, and cracks due to warping are less likely to occur. In addition, as shown in FIG. 22, the inorganic insulating layer 1241a included in the upper layer 124 improves interlayer insulation reliability between the wiring portion 1244W included in the upper layer 124 and the wiring portion 1244W included in the lower layer 124. can be made

The inorganic insulating layer 1241a is formed by plasma CVD (Chemical Vapor Deposition), for example. The inorganic insulating layer 1241a is made of an insulator such as silicon oxide or silicon nitride.

The first insulating layer 1241 including the inorganic insulating layer 1241a and the organic insulating layer 1241b can be formed, for example, by the following method.

First, an inorganic insulating layer 1241a is provided on the upper surface of the structure shown in FIG. Next, an organic insulating layer 1241b having first through holes R1 and recesses C is formed on the inorganic insulating layer 1241a by a method similar to that described with reference to FIGS. Next, the exposed inorganic insulating layer 1241a is removed by dry etching or the like.
Thus, a first insulating layer 1241 including an inorganic insulating layer 1241a and an organic insulating layer 1241b is obtained.

Further, in the method for manufacturing the wiring board 12 described above, the concave portion C is provided in the first insulating layer 1241, but instead of providing the concave portion C, a convex portion may be provided at the position of the concave portion C. However, in this case, the thickness of the wiring portion 1244W is reduced.

Further, in the method of manufacturing the wiring board 12 described above, an insulating resin layer that fills the lower portion of the groove portion G may be further provided. By providing such an insulating resin layer, the thickness of the wiring portion 1244W can be adjusted. For example, when both ends in the length direction of the concave portion C are separated from the land portion 1244L, by providing the insulating resin layer in the concave portion C, the thickness of the wiring portion 1244W is reduced between the inside and the outside of the concave portion C. can be made equal. Further, when such an insulating resin layer is provided, the wiring portion 1244W fills the portion of the groove portion G that is not filled with this insulating resin layer.

In the method for manufacturing the wiring board 12 described above, the adhesion layer 125a and the seed layer 125b are formed after the insulating resin layer 121 having the through holes is formed on the separation layer 3. After forming the layer 125a and the seed layer 125b, the insulating resin layer 121 having through holes may be provided.

A wiring board with a support can also be obtained, for example, by the following method. A method of manufacturing a wiring board according to another embodiment of the present invention will be described below.

First, a structure similar to that described with reference to FIG. 14 is obtained except that a resist layer as a dummy layer is included instead of the second insulating layer 1242 . The dummy layer is then removed from the resulting structure, as shown in FIG.

Next, the exposed surface of the first insulating layer 1241 is covered so as to fill the gap between the land portion 1244L and the wiring portion 1244W, and the second insulating layer 1242 is formed so as to fill the upper surfaces of the land portion 1244L and the wiring portion 1244W. do. The second insulating layer 1242 is formed using, for example, a non-photosensitive resin. Next, a through hole is formed in the second insulating layer 1242 at the position of the land. After that, a wiring board with support is obtained by the same method as the method described with reference to FIGS. 15 to 20 .
The method for manufacturing a wiring board according to another embodiment of the present invention has been described above.

A method of manufacturing a wiring board according to still another embodiment of the present invention will be described below.
First, the structure shown in FIG. 9 is prepared.
Next, a first metal-containing layer 1243a is formed on the upper surface of the first insulating layer 1241 and the inner surface of the first through hole R1. Subsequently, a second metal-containing layer 1243b is formed on the first metal-containing layer 1243a.

Next, a resist layer is formed as a dummy layer on the second metal-containing layer 1243b, having a groove portion G' and at least one second through-hole R2' communicating with the first through-hole R1. The second through hole R2' and the groove portion G' correspond to the second through hole R2 and the groove portion G, respectively. Here, as an example, each of the groove G' and the second through hole R2' is formed in a rectangular shape.

Next, a conductor layer 1244 is formed on the exposed second metal-containing layer 1243b.

Next, as shown in FIG. 24, the resist layer is removed from the resulting structure, after which the exposed first metal-containing layer 1243a and second metal-containing layer 1243b are also removed.

Next, the exposed surface of the first insulating layer 1241 is covered so as to fill the gap between the land portion 1244L and the wiring portion 1244W, and the second insulating layer 1242 is formed so as to fill the upper surfaces of the land portion 1244L and the wiring portion 1244W. do. The second insulating layer 1242 is formed using, for example, a non-photosensitive resin. Next, a through hole is formed in the second insulating layer 1242 at the position of the land. After that, a wiring board with support is obtained by the same method as the method described with reference to FIGS. 15 to 20 .
The method for manufacturing a wiring board according to still another embodiment of the present invention has been described above.

Using the wiring board with a support obtained by the method described above, the packaged device 1 shown in FIG. 1 can be manufactured, for example, by the following method.

FIG. 25 is a cross-sectional view schematically showing a step in a method of manufacturing a packaged device according to one embodiment of the invention. FIG. 26 is a cross-sectional view schematically showing another step in the method of manufacturing a packaged device according to one embodiment of the invention. FIG. 27 is a cross-sectional view schematically showing still another step in the method of manufacturing a packaged device according to one embodiment of the invention.

First, as shown in FIG. 25, the wiring board 12 supported by the supporting body 2 and the FC-BGA board 11 are joined. Then, those joints are sealed with a sealing resin layer 13 .

As the material of the sealing resin layer 13, for example, a mixture of resin and filler can be used. As the resin, for example, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins can be used. As fillers, for example, one or more of silica, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide can be used. The sealing resin layer 13 can be formed, for example, by filling a space between the FC-BGA substrate 11 and the wiring substrate 12 with a liquid material.

As described above, the composite wiring board 10 including the FC-BGA board 11 and the wiring board 12 is obtained. At this point, the support 2 is still provided on the wiring board 12 .

Next, as shown in FIG. 26, the release layer 3 is irradiated with a laser beam 50 from the support 2 side, and the support 2 and the composite wiring board 10 are separated from each other as shown in FIG. As described above, the material of the release layer 3 is a resin that can be peeled off by absorbing ultraviolet light (UV light). is. If the release layer 3 remains on the composite wiring board 10, it is removed by etching, for example.

After that, the functional device 20 shown in FIG. 1 is bonded to the composite wiring board 10 .
Prior to bonding the functional device 20, an electroless Ni/Pd/Au plating layer, an OSP film, an electroless tin plating layer, And a surface treatment layer such as an electroless Ni/Au plating layer may be provided.

Then, those joints are sealed with a sealing resin layer 30 .
As the material of the sealing resin layer 30, for example, the materials exemplified as the materials of the sealing resin layer 13 can be used. The encapsulating resin layer 30 can be formed, for example, by the same method as described above for the encapsulating resin layer 13 .
As described above, the packaged device 1 shown in FIG. 1 is completed.

In the above method, the functional device 20 is joined to the wiring board 12 after the wiring board 12 is joined to the FC-BGA board 11 . Alternatively, the wiring substrate 12 may be bonded to the FC-BGA substrate 11 after the functional device 20 is bonded to the wiring substrate 12 .

<effect>
Interposers obtained by silicon interposer technology, so-called silicon interposers, are manufactured using silicon wafers and facilities for semiconductor front-end processes. Silicon wafers are limited in shape and size, and the number of interposers that can be manufactured from one wafer is not necessarily large. And the manufacturing equipment is also expensive. Therefore, silicon interposers are expensive. Moreover, since a silicon wafer is a semiconductor, the use of a silicon interposer also poses a problem of deterioration in transmission characteristics.

The method of directly forming a multi-layered wiring structure including a conductor layer having a fine wiring pattern on an FC-BGA substrate causes little deterioration in transmission characteristics seen in silicon interposers. However, this method has problems with the manufacturing yield of the FC-BGA substrate itself, and it is highly difficult to form a multilayer wiring structure including a conductor layer having a fine wiring pattern on a core layer such as a glass epoxy substrate. Therefore, there is a problem that the manufacturing yield is low as a whole. Furthermore, it is difficult to achieve high symmetry with respect to the plane that bisects the thickness of the FC-BGA substrate. Therefore, such FC-BGA substrates tend to warp or distort when heated.

On the other hand, a wiring board containing a fine wiring pattern including a conductor layer and a photosensitive resin layer is formed on a support, and the support on which the wiring board is formed is mounted on the FC-BGA wiring board. In that case, I had the following problem: The above photosensitive resin layer does not contain filler. On the other hand, the underfill layer provided between the wiring board and the FC-BGA wiring board and the solder resist layer included in the wiring board contain fillers. Therefore, the photosensitive resin layer tends to have a lower elastic modulus and a larger CTE than the underfill layer and the solder resist layer. Therefore, when the wiring board provided on the support and the FC-BGA wiring board are joined by heating, the photosensitive resin layer deforms more than the underfill layer and the solder resist layer. Along with this deformation, elongation and warpage of the wiring board, peeling of the conductor layer due to stress generated in the wiring board, and cracks originating from the peeled portion may occur.

FIG. 28 is a cross-sectional view schematically showing a wiring board 12' according to a comparative example. A wiring board 12' shown in FIG. 28 is the same as the wiring board 12 shown in FIG. 20, except that the concave portion C described above is not provided. That is, in the wiring substrate 12', the area located between the land portion 1244L and the wiring portion 1244W in the interface between the first insulating layer 1241 and the second insulating layer 1242 is the same as the position adjacent to the land portion 1244L and the land portion. The height is the same at a position away from 1244L. Therefore, when the wiring board 12' and the FC-BGA wiring board are joined by heating, the stress due to the deformation such as warping of the wiring board 12' concentrates in the area surrounded by the broken line PR shown in FIG. Cracks are likely to occur.

On the other hand, in the wiring substrate 12 described above, as shown in FIG. 20, the region located between the land portion 1244L and the wiring portion 1244W in the interface between the first insulating layer 1241 and the second insulating layer 1242 is The height is different between the position adjacent to the land portion 1244L and the position spaced apart from the land portion 1244L. Specifically, the wiring board 12 described above has a recess C. As shown in FIG. In this way, when a step is provided at the interface between the first insulating layer 1241 and the second insulating layer 1242 so as to partition the land portion 1244L and the wiring portion 1244W, the thickness direction of the wiring substrate 12 is perpendicular to the thickness direction. The shearing force applied to the wiring board 12 is distributed in a direction inclined with respect to the thickness direction of the wiring board 12 and a direction perpendicular thereto. Therefore, when the wiring board 12 and the FC-BGA wiring board are joined by heating, the stress applied to the contact between the land portion 1244L and the first insulating layer 1241 is dispersed as described above. Cracks originating from the interface with the first insulating layer 1241 are less likely to occur.

In the wiring substrate 12' shown in FIG. 28, the thickness T1 of the wiring portion 1244W and the thickness T2 of the land portion 1244L are equal. When the wiring pattern is miniaturized in such a wiring substrate 12', the wiring resistance tends to increase because the surface area per length of the wiring pattern becomes very small.

On the other hand, in the wiring board 12 described above, the thickness T1 of the wiring portion 1244W is larger than the thickness T2 of the land portion 1244L, as described with reference to FIG. That is, the thickness T1 of the wiring portion 1244W on the wiring substrate 12 is greater than the thickness T1 of the wiring portion 1244W on the wiring substrate 12'. Therefore, the above-described wiring board 12 has lower wiring resistance and higher transmission characteristics than the wiring board 12'.

In addition, the wiring board 12 described above has a thicker wiring portion 1244W than the wiring board 12', so the amount of insulating resin contained in one layer 124 is small. Therefore, the wiring board 12 is less thermally expanded and less deformed than the wiring board 12'. Therefore, when the wiring board provided on the support and the wiring board for FC-BGA are joined by heating, cracks are less likely to occur.

Note that the above-described effect that cracks are less likely to occur and the above-described effect that wiring resistance is small and high transmission characteristics are obtained by adopting a configuration in which the thickness T1 of the wiring portion 1244W is larger than the thickness T2 of the land portion 1244L. If so, it works even if the stepped structure described above is not employed.
In addition, the effect of having a low wiring resistance and high transmission characteristics as described above can be obtained by adopting the structure in which the thickness T1 of the wiring portion 1244W is larger than the thickness T2 of the land portion 1244L if the stepped structure described above is employed. It plays even if it is not adopted.

DESCRIPTION OF SYMBOLS 1... Packaged device, 2... Support body, 3... Release layer, 10... Composite wiring board, 11... FC-BGA board, 12... Wiring board, 12'... Wiring board, 13... Sealing resin layer, 14... Joining Electrode 20 Functional device 30 Sealing resin layer 40 Joining electrode 50 Laser light 111 Core layer 112 Insulating layer 113 Conductor layer 114 Insulating layer 115 Joining conductor DESCRIPTION OF SYMBOLS 121... Insulating resin layer, 122... Conductor layer, 122a... Adhesion layer, 122b... Seed layer, 123... Conductor layer, 124... Layer, 125a... Adhesion layer, 125b... Seed layer, 126... Resist layer, 127... Conductor layer, DESCRIPTION OF SYMBOLS 128... Insulating resin layer 129... Surface treatment layer 130... Conductor for joining 1241... First insulating layer 1241a... Inorganic insulating layer 1241b... Organic insulating layer 1242... Second insulating layer 1243a... First metal containing Layer, 1243b... second metal-containing layer, 1244... conductor layer, 1244'... conductor layer, 1244L... land portion, 1244V... via portion, 1244W... wiring portion.

Claims (19)

a first insulating layer having a first surface and a second surface that is the back surface thereof, the first insulating layer having a first through hole extending from the first surface to the second surface;
a second insulating layer provided on the second surface, the second insulating layer having a second through hole communicating with the first through hole and a groove portion;
a conductor layer including a via portion in which the first through-hole is embedded, a land portion in which the second through-hole is embedded, and a wiring portion in which the groove is embedded;
In the interface between the first insulating layer and the second insulating layer, a region positioned between the land portion and the wiring portion has a height adjacent to the land portion and a position spaced apart from the land portion. Wiring boards with different sizes. 2. The wiring board according to claim 1, wherein said position adjacent to said land has a greater distance from said first surface than said position spaced apart from said land. 3. The wiring board according to claim 1, wherein the first insulating layer is further provided with a recess opening at the second surface, and the groove is open at the bottom surface of the recess. 4. The method according to claim 3, wherein a ratio D/T of the depth D of the recess and the thickness T of the first insulating layer adjacent to the land is in the range of 0.5 to 0.99. wiring board. 5. The wiring substrate according to claim 3, wherein a plurality of said wiring portions are present in one said recess. 6. The wiring board according to claim 3, wherein the recess has a forward tapered shape. The wiring board according to any one of claims 1 to 6, wherein the wiring portion has a constant thickness in its length direction. 8. The insulating resin layer according to any one of claims 1 to 7, further comprising an insulating resin layer filling a portion of the groove on the side of the first insulating layer, wherein the wiring portion fills a portion of the groove that is not filled with the insulating resin layer. The wiring board according to item 1. 9. The wiring board according to claim 1, further comprising a first metal-containing layer covering the side and bottom surfaces of said conductor layer, said first metal-containing layer containing titanium. a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a lower ionization tendency than the material of the conductor layer; 10. The wiring board of claim 9, further comprising: said second metal-containing layer comprising copper. A wiring board comprising an insulating layer and a conductor layer embedded in the insulating layer and including a wiring portion, a land portion and a via portion, wherein a thickness T1 of the wiring portion is greater than a thickness T2 of the land portion. 12. The wiring board according to claim 11, wherein a ratio T1/T2 between the thickness T1 of the wiring portion and the thickness T2 of the land portion is larger than 1 and smaller than 2. A first wiring board and a second wiring board joined to the first wiring board, wherein the first and second wiring boards are electrically connected to each other via a joining electrode interposed therebetween. A composite wiring board, wherein the second wiring board is the wiring board according to any one of claims 1 to 12. 14. The composite wiring board according to claim 13, wherein the first wiring board is a flip-chip ball grid array wiring board, and the second wiring board is an interposer. The composite wiring board according to claim 13 or 14;
and a functional device mounted on a surface of the first wiring substrate opposite to the second wiring substrate. forming a first insulating layer having a first through hole and a recess on a release layer provided on a support;
forming a second insulating layer having a second through hole communicating with the first through hole and at least one groove on the first insulating layer;
and forming a conductor layer on the second insulating layer so as to fill the first through hole, the second through hole, and the trench. 17. The method of manufacturing a wiring board according to claim 16, wherein the recess has a forward tapered shape. 18. The method of manufacturing a wiring board according to claim 16, wherein the support is made of glass. 19. The method of manufacturing a wiring board according to claim 16, wherein both the first and second insulating layers are made of a photosensitive resin.

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