JP2022167527A - Memory access device and memory access method and memory access program - Google Patents

Abstract

To provide a memory access device, a method, and a program that suppress writing of unnecessary data other than input data into a memory in a burst access for the memory.SOLUTION: A memory access device 100 includes: coding means 110 that generates segment data containing a continuous section of a plurality of input data after splitting or linking the plurality of input data inputted from outside in an entry sequence, generates head position data representing the head position of each of the plurality of input data in the segment data, and generates a segment containing the segment data and the head position data; memory control means 120 that writes the generated segment into the memory in one or more segment units along with reading out a segment from the memory in one or more segment units; and decoding means 130 that reconfigures the plurality of input data inputted from outside based on the segment read out from the memory and outputs the reconfigured data to outside.SELECTED DRAWING: Figure 1

Description

The present invention relates to techniques for accessing (writing and reading) data in memory.

In order to speed up memory access, memory may be accessed by burst processing (hereinafter referred to as "burst access"). The length of data accessed at one time in burst access is defined as a predetermined length (referred to as "segment length"). On the other hand, the data length of data to be written (input data) differs for each data.

An example of technology for speeding up access to memory is disclosed in Patent Document 1. In the memory access control circuit of Patent Document 1, a data transfer request to a synchronous memory from a data processing device is divided into a plurality of data transfer requests according to the amount of data to be burst-transferred at one time. Here, in each divided data transfer request, data transferred at one time is limited to data in a single memory bank. The divided data transfer requests are assembled into data transfer requests in which data transfer requests for each memory bank are combined one by one, and output as a plurality of new data transfer requests. As a result of the above configuration, in the memory access control circuit of Patent Document 1, the data processor efficiently accesses continuous data stored in a plurality of memory banks.

However, even if the technique of Patent Document 1 is used to read data from the memory, it is not possible to solve the problem that the proportion of desired data in each segment on the memory is low.

FIG. 9 is a schematic diagram for explaining the burst access technique referred to in the present invention. In this burst access technique, as shown in FIG. 9, the portion where the input data is less than the segment length (the hatched portion in the middle of FIG. 9) is also written to the memory. As a result, there is a memory area in which useless data other than the input data is written, and the efficiency of memory utilization decreases. In addition, since the data read from the memory includes unnecessary data other than the input data, the data to be output (output data) is unnecessary data other than the input data (hatched portion in the lower part of FIG. 9). including.

JP 2006-268801 A

As described above in the burst access technique referred to in the present invention, when the data length of input data increases or decreases with respect to the segment length in burst access, useless data other than input data may be written or read from memory. There is As a result, there is a problem that the proportion of input data in memory (memory utilization efficiency) decreases, the access speed decreases, and the proportion of useless data other than input data included in output data is high.

SUMMARY OF THE INVENTION It is an object of the present invention, which has been made in view of the above problems, to suppress writing of useless data other than input data to a memory during burst access to the memory.

In one aspect of the present invention, a memory access device divides or concatenates a plurality of input data input from the outside in order of input, and then generates segment data including continuous portions of the plurality of input data, and divides the segment data into segment data. Encoding means for generating head position data representing the head position of each piece of input data, generating a segment containing the segment data and the head position data, and writing the generated segment to a memory in units of one or more segments, memory control means for reading out segments from the memory in units of one or more segments; reconfiguring a plurality of externally input data based on the segments read out from the memory; and decoding means for outputting the input data to the outside.

In one aspect of the present invention, a memory access method divides or concatenates a plurality of input data input from the outside in order of input, and then generates segment data including continuous portions of the plurality of input data, Encoding processing for generating head position data representing the head position of each piece of input data, generating segments containing segment data and head position data, and writing the generated segments to memory in units of one or more segments, A memory control process for reading segments from the memory in units of one or more segments, a plurality of input data input from the outside are reconfigured based on the segments read from the memory, and a plurality of reconfigured external input data and a decoding process for outputting the input data to the outside.

In one aspect of the present invention, a memory access program divides or concatenates a plurality of input data input from the outside in order of input, generates segment data containing continuous portions of the plurality of input data, Encoding processing for generating head position data representing the head position of each piece of input data, generating segments containing segment data and head position data, and writing the generated segments to memory in units of one or more segments, A memory control process for reading segments from the memory in units of one or more segments, a plurality of input data input from the outside are reconfigured based on the segments read from the memory, and a plurality of reconfigured external input data It causes the computer to execute decoding processing for outputting the input data to the outside.

According to the present invention, it is possible to suppress writing of useless data other than input data to the memory in burst access to the memory.

1 is a block diagram showing an example of configuration of a memory access device according to a first embodiment of the present invention; FIG. It is a figure which shows an example of the segment structure in 1st Embodiment of this invention. FIG. 4 is a schematic diagram for explaining the operation of the memory access device according to the first embodiment of the present invention; It is a block diagram showing an example of the configuration of a memory access device according to a second embodiment of the present invention. It is a figure which shows an example of the segment structure in 2nd Embodiment of this invention. FIG. 10 is a schematic diagram for explaining the operation of the memory access device according to the second embodiment of the present invention; FIG. 11 is a schematic diagram for explaining the operation of the memory access device in the modified example of the second embodiment of the present invention; 1 is a block diagram showing an example of a hardware configuration that can implement a memory access device according to each embodiment of the present invention; FIG. FIG. 3 is a schematic diagram for explaining a burst access technique referred to in the present invention;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in all the drawings, the same reference numerals are given to the same constituent elements, and the description thereof will be omitted as appropriate.
(First embodiment)
A first embodiment of the present invention, which is the basis of each embodiment of the present invention, will be described.

A configuration in this embodiment will be described.

FIG. 1 is a block diagram showing an example configuration of a memory access device according to the first embodiment of the present invention. As shown in FIG. 1, the memory access device 100 of this embodiment includes an encoding section 110, a memory control section 120, and a decoding section .

The encoding unit 110 divides or concatenates a plurality of pieces of input data input from the outside in order of input to generate segments. Here, the segment includes segment data and head position data. Segment data includes a continuous portion of a plurality of pieces of input data after being divided or concatenated in order of input. The head position data is data representing the head position of each piece of input data among a plurality of pieces of input data, and is data representing the position of the head position of each piece of input data within the segment data.

The memory control unit 120 writes the generated segments to the memory 200 in units of one or more segments, and reads the segments from the memory 200 in units of one or more segments. The memory 200 writes and reads data in units of one or more segments during burst access.

The decoding unit 130 reconstructs a plurality of input data input from the outside based on the segments read from the memory 200, and outputs the reconstructed plurality of input data input from the outside to the outside. Here, to reconstruct the input data means to separate each of the plurality of input data input from the outside based on the segments read from the memory 200 and output them to the outside.

FIG. 2 is a diagram showing an example of segment configuration in the first embodiment of the present invention. A segment includes a segment header portion and a segment data portion.

The segment data part is set to have a fixed length (for example, (segment length-2n) octets; referred to as "segment data length") and stores segment data. Segment data is obtained by dividing or concatenating (combining) all or part of one or more pieces of input data into fixed segment data lengths in the order of input. If the input data or the input data remaining after the input data is divided into segment data (referred to as "preceding input data") is less than the segment data length, the preceding input data is replaced with the next input data ("subsequent data"). input data”) are concatenated into segment data. As such, a segment may include all or part of multiple input data within the segment data.

In this embodiment, the input data and segment standards are defined so that the lower limit of the input data length is 1/n (n is an integer of 2 or more) of the segment data length or more (this A non-restrictive variant will be described later in the second embodiment). Thus, in this embodiment, one segment may contain up to n entire pieces of input data or up to n+1 pieces of input data. That is, the segment data portion can include all or part of one or more and n+1 or less input data.

The segment header part has a fixed length (for example, 2n octets; called "segment header length") and stores the segment header. A segment header contains n head position data. The i-th head position data (indicated by HPi in FIG. 2) (where i is an integer that satisfies 1≦i≦n) indicates the i-th head position among the head positions of each input data stored in the segment data section. This is the data to hold. The start position represents the position in the segment data portion. In the following, a case where the start position is represented by the distance (the number of octets) from the first octet of the segment data portion will be described as an example, but the representation of the start position in this embodiment is not limited to this.

Operations in this embodiment will be described.

FIG. 3 is a schematic diagram explaining the operation of the memory access device according to the first embodiment of the present invention. In FIG. 3, the case where n is 3 will be described as an example (see the second embodiment for the operation when n is 2). In FIG. 3, "A", "B", "C", "D", and "E" represent each input data, and subscripted alphabetic characters represent divided data obtained by dividing each input data indicated by alphabetic characters. where "EOF" represents a signal indicating the end of input data, and "*" represents arbitrary padding data. Also in FIG. 3, the values "0", "X", "Y", "Z", "W", and "V" represent positions in the segment data portion, and the invalid value "-" represents an invalid position. (no position specified), and the special value "/" indicates the end of the input data. Here, the invalid value and the special value are predetermined values that are not normally used as the value of the head position data, such as 0xffff (hexadecimal notation) and 0xfffe (hexadecimal notation). As shown in FIG. 3, the encoding unit 110 holds the i-th head position in the i-th head position data when the i-th head position of the input data is included in the segment data portion.

For example, first, since the input data A is longer than the segment data portion, the encoding unit 110 causes the segment data portion to hold the divided data A1 (the first segment from the left in FIG. 3). Then, the encoding unit 110 causes the first head position data to hold the first head position 0 of the input data A in the segment data portion. The encoding unit 110 holds invalid values in the other head position data.

Next, the encoding unit 110 causes the segment data portion to hold the divided data A2 in the segment in which the input data A is being divided (the second segment from the left in FIG. 3). Since the segment data part does not include the beginning of the input data, the encoding unit 110 causes all the beginning position data to hold an invalid value.

Subsequently, since the remaining input data A (A3) is shorter than the segment data portion, the encoding section 110 causes the segment data portion to hold the divided data A3 (the third segment from the left in FIG. 3). Then, the encoding unit 110 waits for the subsequent input data B, concatenates the divided data B1 of the subsequent input data B to the preceding input data A3, and stores them in the segment data portion. Here, the encoding unit 110 causes the first starting position data of the input data B to hold the first starting position X in the segment data part, and causes the other starting position data to hold an invalid value.

Subsequently, since the remaining input data B (B2) is shorter than the segment data portion, the encoding section 110 causes the segment data portion to hold the divided data B2 (the fourth segment from the left in FIG. 3). Then, the encoding unit 110 waits for the subsequent input data C, D, and E, and concatenates the subsequent input data C and D and the divided data E1 of the subsequent input data E to the divided data B2 of the preceding input data B. Stored in the segment data part. Here, in the segment data portion, the encoding unit 110 causes the first leading position Y of the input data C to be held in the first leading position data, and the second leading position Z of the input data D to be held in the second leading position data. Position data holds the third leading position W of the input data E in the third leading position data.

Subsequently, since the remaining input data E (E2) is shorter than the segment data portion, the encoding section 110 causes the segment data portion to hold the divided data E2 (the fifth segment from the left in FIG. 3). Then, the encoding unit 110 waits for the end of the input data, connects the padding data “*” to the divided data E2 of the preceding input data E, and stores them in the segment data section. Here, the encoding unit 110 causes the first head position V of "EOF" to be held in the first head position data in the segment data part, and a special value "/" indicating that the position V is the end of the input data. ” is held in the second start position data, and the process ends.

In this way, the encoding unit 110 divides or concatenates input data to generate segments, and outputs the generated segments to the memory control unit 120 .

The memory control unit 120 sequentially writes the segments input from the encoding unit 110 to the memory 200 in units of one or more segments.

The memory control unit 120 sequentially reads segments in units of one or more segments from the memory 200 and outputs the read segments to the decoding unit 130 .

The decoding unit 130 reads the segment written in the memory 200 via the memory control unit 120 . Then, the decoding unit 130 reconstructs the input data based on the read segment start position data, and outputs the reconstructed input data to the outside as output data. Here, one segment can include up to n entire pieces of input data or up to n+1 pieces of input data. That is, one segment can include the leading positions of up to n pieces of input data. The start position data of each segment holds the i-th start position of the input data in that segment. That is, the start position of all input data is held by some start position data of any segment. Therefore, the decoding unit 130 can reconstruct the input data based on the read segment head position data.

Even if the head position of the subsequent input data necessary for reconstructing certain input data has not been acquired at a certain time, the decoding unit 130 reads the subsequent segment to read the head position indicating the head position of the subsequent input data. Can get location data.

The decoding unit 130 sequentially outputs the reconstructed input data to the outside as output data.

For example, first, the decoding unit 130 inputs the first segment (the first segment from the left in FIG. 3). The first segment holds the value "0" in the first head position data, and holds invalid values in the second and third head position data. Therefore, the decoding unit 130 determines that the divided data A1 of the first input data A is stored in the first segment from the beginning.

Next, decoding section 130 inputs a second segment (the second segment from the left in FIG. 3). The second segment holds invalid values for all leading position data. Therefore, the decoding unit 130 determines that the divided data A2 of the first input data A is continuously stored in the second segment.

Subsequently, decoding section 130 inputs the third segment (the third segment from the left in FIG. 3). The third segment holds the value "X" in the first head position data and invalid values in the second and third head position data. Therefore, the decoding unit 130 determines that the divided data A3 of the first input data A is stored immediately before the position "X" of the third segment. Then, the decoding unit 130 determines that the divided data B1 of the second input data B is stored after the position "X" of the third segment. Since the input data A has been reconstructed, the decoding unit 130 outputs the reconstructed input data A to the outside as output data.

Subsequently, decoding section 130 inputs the fourth segment (the fourth segment from the left in FIG. 3). The fourth segment holds the value "Y" in the first head position data, the value "Z" in the second head position data, and the value "W" in the third head position data. ” is held. Therefore, the decoding unit 130 stores the divided data B2 of the second input data B immediately before the position "Y" in the fourth segment, and decodes the data from the position "Y" to the position "Z" immediately before the position "Z". It is determined that the third input data C is stored up to and the fourth input data D is stored from the position "Z" to just before the position "W". Then, the decoding unit 130 determines that the divided data E1 of the fifth input data E is stored after the position "W" of the fourth segment. Since the input data B, C, and D have been reconstructed, the decoding unit 130 outputs the reconstructed input data B, C, and D to the outside as output data.

Subsequently, decoding section 130 inputs the fifth segment (the fifth segment from the left in FIG. 3). The fifth segment holds the value "V" in the first head position data and the special value "/" in the second head position data. Therefore, the decoding unit 130 determines that the divided data E2 of the fifth input data E is stored immediately before the position "V" of the fifth segment. Then, the decoding unit 130 determines that the position "V" of the fifth segment is the end of the input data. Since the input data E has been reconstructed, the decoding unit 130 outputs the reconstructed input data E to the outside as output data, and terminates the process.

In this way, the decoding unit 130 reads out the segment written in the memory 200 via the memory control unit 120, reconstructs the input data based on the head position data of the read segment, and reconstructs the input data. is output to the outside as output data.

As described above, the operation in the present embodiment has been described by taking the case where n is 3 as an example. However, n in this embodiment is not limited to 3, and it is clear that n may be 2 or n may be 4 or more.

As described above, in this embodiment, a segment includes a segment header portion and a segment data portion. The input data and segment standards are defined so that the lower limit of the input data length is 1/n or more of the segment data length. Therefore, the segment data part can include all or part of one or more and n+1 or less input data. The segment header portion includes n head position data. The i-th start position data holds the i-th start position among the start positions of each input data stored in the segment data portion. The memory access device 100 of this embodiment includes an encoding section 110, a memory control section 120, and a decoding section . The encoding unit 110 divides or concatenates input data to generate segments, and outputs the generated segments to the memory control unit 120 . The memory control unit 120 writes the segments input from the encoding unit 110 to the memory 200 in units of one or more segments. The memory control unit 120 reads data from the memory 200 in units of one or more segments, and outputs the read segments to the decoding unit 130 . Decoding section 130 receives a segment from memory control section 120, reconstructs the input data based on the start position data of the input segment, and outputs the reconstructed input data to the outside as output data. Here, the i-th start position data of each segment holds the i-th start position of the input data in that segment. That is, the start positions of all input data are held by any start position data of any segment. In other words, the decoding unit 130 can reconstruct the input data based on the read segment head position data.

Therefore, the memory access device 100 of the present embodiment has the effect of being able to suppress writing of useless data other than input data to the memory during burst access to the memory.

As a result, in the memory access device 100 of this embodiment, the memory utilization efficiency is improved, the access speed is improved, and the ratio of output data containing useless data other than input data is reduced.

In the above description, the case where the input data and segment standards are defined such that the lower limit of the data length of each input data is 1/n or more of the data length of the segment data. However, in this embodiment, the relationship between the lower limit value of the input data length and the segment data length may not be defined. Alternatively, in the present embodiment, the lower limit of the data length of each input data is 1/n or more of the data length of the segment data, but the segment may include head position data less than n in number. In these cases, input data includes content data (content included in each input data) and content data length (data length of content data). Such a modified example of this embodiment will be described later in the second embodiment.
(Second embodiment)
A second embodiment of the present invention based on the first embodiment of the present invention will be described. In this embodiment, the input data and segment standards are defined such that the lower limit of the input data length is equal to or greater than half the segment data length.

A configuration in this embodiment will be described.

FIG. 4 is a block diagram showing an example configuration of a memory access device according to the second embodiment of the present invention. As shown in FIG. 4, the memory access device 105 of this embodiment includes an encoder 115, a memory controller 125, and a decoder 135. FIG.

The encoding unit 115 designates the start address of the write destination in the memory 200, inputs input data from the outside, generates segments according to the data length of the input data, and controls the generated segments in the memory. Output to the unit 125 .

The memory control unit 125 designates the start address of the write destination on the memory 200, and then converts the segments input from the encoding unit 115 into one or more segments in units of one or more continuous segments starting from the start address of the write destination on the memory 200. Write to area. In addition, the memory control unit 125 designates the head address of the read source on the memory 200, and then reads data in units of one or more segments from a continuous area starting from the head address of the read source on the memory 200, and reads the data. The resulting segment is output to decoding section 135 .

The decoding unit 135 designates the top address of the read source in the memory 200, reads the segment written in the memory 200 via the memory control unit 125, reconstructs the input data from the read segment, Output the reconfigured input data to the outside as output data.

FIG. 5 is a diagram showing an example of segment configuration in the second embodiment of the present invention. A segment includes a segment header portion and a segment data portion.

The segment data part is set to have a fixed length (eg, (segment length-4) octets; segment data length) and stores segment data. Segment data is obtained by dividing or concatenating (combining) all or part of one or more pieces of input data into fixed segment data lengths in the order of input. If the input data or the input data remaining after the input data is divided into segment data (preceding input data) is less than the segment data length, the next input data (subsequent input data) is concatenated with the preceding input data. segment data. As such, a segment may include all or part of multiple input data within the segment data.

In this embodiment, the input data and segment standards are defined so that the lower limit of the input data length is 1/2 or more of the segment data length (a modification of this embodiment without this limitation). Examples are given below). Thus, in this embodiment, one segment may include up to two entire pieces of input data or up to three portions of input data. That is, the segment data portion can include all or part of one or more and three or less pieces of input data.

The segment header part has a fixed length (eg, 4 octets; segment header length) and stores the segment header. The segment header includes FHP (First Header Point; an example of head position data) and LHP (Last Header Point; an example of head position data). FHP is data that holds the first start position among the start positions of each input data stored in the segment data portion. LHP is data that holds the last leading position among the leading positions of each input data stored in the segment data portion. The start position represents the position in the segment data portion. In the following, a case where the start position is represented by the distance (the number of octets) from the first octet of the segment data portion will be described as an example, but the representation of the start position in this embodiment is not limited to this.

Operations in this embodiment will be described.

FIG. 6 is a schematic diagram explaining the operation of the memory access device according to the second embodiment of the present invention. In FIG. 6, "A", "B", "C", and "D" represent each input data, subscripted alphabetic characters represent divided data obtained by dividing each input data indicated by the alphabetic characters, and "EOF ” represents a signal indicating the end of input data, and “*” represents arbitrary padding data. Also, in FIG. 6, the values "0", "X", "Y", "Z", and "V" represent positions in the segment data portion, and the invalid value "-" represents an invalid position (position specified). and the special value "/" indicates the end of the input data. Here, the invalid value and special value are predetermined values that are not normally used as FHP and LHP values, such as 0xffff (hexadecimal notation) and 0xfffe (hexadecimal notation). As shown in FIG. 6, when the segment data part includes the head position of the input data, the encoding unit 115 holds the first head position in FHP and the last head position in LHP.

For example, first, since the input data A is longer than the segment data portion, the encoding unit 115 causes the segment data portion to hold the divided data A1 (the first segment from the left in FIG. 6). Then, the encoding unit 115 causes both the FHP and the LHP to hold the first and last leading position 0 of the input data A in the segment data portion.

Next, the encoding unit 115 causes the segment data portion to hold the divided data A2 in the segment in which the input data A is being divided (the second segment from the left in FIG. 6). Since the beginning of the input data is not included in the segment data portion, the encoding unit 115 causes both FHP and LHP to hold invalid values.

Subsequently, since the remaining input data A (A3) is shorter than the segment data portion, the encoding unit 115 causes the segment data portion to hold the divided data A3 (the third segment from the left in FIG. 6). Then, the encoding unit 115 waits for the succeeding input data B, connects the divided data B1 of the succeeding input data B to the preceding input data A3, and stores them in the segment data portion. Here, the encoding unit 115 causes the FHP to hold the first head position X of the input data B in the segment data portion, and the LHP to hold the last head position X of the input data B. FIG.

Subsequently, since the remaining input data B (B2) is shorter than the segment data portion, the encoding unit 115 causes the segment data portion to hold the divided data B2 (the fourth segment from the left in FIG. 6). Then, the encoding unit 115 waits for the subsequent input data C and D, connects the divided data D1 of the subsequent input data C and the subsequent input data D to the divided data B2 of the preceding input data B, and stores them in the segment data portion. Here, the encoding unit 115 causes the FHP to hold the first head position Y of the input data C and the LHP to hold the last head position Z of the input data D in the segment data portion.

Subsequently, since the remaining input data D (D2) is shorter than the segment data portion, the encoding unit 115 causes the segment data portion to hold the divided data D2 (the fifth segment from the left in FIG. 6). Then, the encoding unit 115 waits for the end of the input data, attaches the padding data “*” to the divided data D2 of the preceding input data D, and stores them in the segment data portion. Here, the encoding unit 115 causes the FHP to hold the first leading position Y of “EOF” in the segment data part, and holds a special value “/” indicating that the position Y is the end of the input data in the LHP. and terminate the process.

In this way, the encoding unit 115 divides or concatenates input data to generate segments, and outputs the generated segments to the memory control unit 125 .

The memory control unit 125 sequentially writes the segments input from the encoding unit 115 to the memory 200 in units of one or more segments.

The memory control unit 125 sequentially reads segments in units of one or more segments from the memory 200 and outputs the read segments to the decoding unit 135 .

The decoding unit 135 reads the segment written in the memory 200 via the memory control unit 125 . Then, the decoding unit 135 reconstructs the input data based on the FHP and LHP of the read segment, and outputs the reconstructed input data to the outside as output data. Here, one segment can include up to two entire pieces of input data or up to three pieces of input data. That is, one segment can include the top positions of up to two pieces of input data. The FHP and LHP of each segment hold the first and last leading positions of the input data in that segment, respectively. That is, the head positions of all input data are held by the FHP or LHP of any segment. Therefore, the decoding unit 135 can reconstruct the input data based on the FHP and LHP of the read segment.

Even if the head position of the subsequent input data required for reconstructing certain input data has not been acquired at a certain time, the decoding unit 135 reads the subsequent segment to read the FHP that indicates the head position of the subsequent input data. Or you can get LHP.

The decoding unit 135 sequentially outputs the reconstructed input data to the outside as output data.

For example, first, the decoding unit 135 inputs the first segment (the first segment from the left in FIG. 6). The first segment holds the value "0" for FHP and LHP. Therefore, the decoding unit 135 determines that the divided data A1 of the first input data A is stored in the first segment from the beginning.

Next, the decoding unit 135 inputs the second segment (the second segment from the left in FIG. 6). The second segment holds invalid values for FHP and LHP. Therefore, the decoding unit 135 determines that the divided data A2 of the first input data A is continuously stored in the second segment.

Subsequently, the decoding unit 135 inputs the third segment (the third segment from the left in FIG. 6). The third segment holds the value "X" for FHP and LHP. Therefore, the decoding unit 135 stores the divided data A3 of the first input data A immediately before the position "X" of the third segment, and stores the second input data after the position "X". It is determined that the divided data B1 of B is stored. Since the input data A has been reconstructed, the decoding unit 135 outputs the reconstructed input data A to the outside as output data.

Subsequently, the decoding unit 135 inputs the fourth segment (the fourth segment from the left in FIG. 6). The fourth segment holds the value "Y" in FHP and the value "Z" in LHP. Therefore, the decoding unit 135 stores the divided data B2 of the second input data B immediately before the position "Y" in the fourth segment, and decodes the data from the position "Y" to the position "Z" immediately before the position "Z". It is determined that the third input data C is stored by . Then, the decoding unit 135 determines that the divided data D1 of the fourth input data D is stored after the position "Z" of the fourth segment. Since the input data B and C have been reconstructed, the decoding unit 135 outputs the reconstructed input data B and C to the outside as output data.

Subsequently, the decoding unit 135 inputs the fifth segment (the fifth segment from the left in FIG. 6). The fifth segment holds the value "V" in FHP and the special value "/" in LHP. Therefore, the decoding unit 135 determines that the divided data D2 of the fourth input data D is stored immediately before the position "V" of the fifth segment, and the position "V" is the end of the input data. I judge. Since the input data D has been reconstructed, the decoding unit 135 outputs the reconstructed input data D to the outside as output data, and terminates the process.

In this way, the decoding unit 135 reads the segment written in the memory 200 via the memory control unit 125, reconstructs the input data based on the FHP and LHP of the read segment, and reconstructs the input data. is output to the outside as output data.

As described above, in this embodiment, a segment includes a segment header portion and a segment data portion. The standards for input data and segments are defined such that the lower limit of the input data length is 1/2 or more of the segment data length. Therefore, the segment data portion can include all or part of one or more but no more than three pieces of input data. The segment header part includes FHP and LHP. The FHP holds the first start position among the start positions of each input data stored in the segment data portion. The LHP holds the last leading position among the leading positions of each input data stored in the segment data portion. The memory access device 105 of this embodiment includes an encoder 115 , a memory controller 125 and a decoder 135 . The encoding unit 115 divides or concatenates input data to generate segments, and outputs the generated segments to the memory control unit 125 . The memory control unit 125 writes the segments input from the encoding unit 115 to the memory 200 in units of one or more segments. The memory control unit 125 reads data in units of one or more segments from the memory 200 and outputs the read segments to the decoding unit 135 . The decoding unit 135 receives a segment from the memory control unit 125, reconstructs the input data based on the FHP and LHP of the input segment, and outputs the reconstructed input data to the outside as output data. Here, the FHP and LHP of each segment respectively hold the first head position and last head position of the input data in that segment. That is, the head position of all input data is held by the FHP or LHP of any segment. That is, the decoding unit 135 can reconstruct the input data based on the FHP and LHP of the read segment.

Therefore, the memory access device 105 of this embodiment has the effect of being able to suppress writing of useless data other than input data to the memory during burst access to the memory.

As a result, in the memory access device 105 of this embodiment, the memory utilization efficiency is improved, the access speed is improved, and the ratio of output data containing useless data other than input data is reduced.
(Modification)
A modification of this embodiment will be described. In this modified example, the segment standards are as described above in this embodiment. On the other hand, the relationship between the lower limit of the input data length and the segment data length is not specified. However, the input data includes content data representing content included in each input data, and content data length representing the data length of the content data.

The configuration in this modified example is as described above in this embodiment.

FIG. 7 is a schematic diagram for explaining the operation of the memory access device in the modified example of the second embodiment of the present invention. As shown in FIG. 7, in the operation example of this modified example, the input data D is shorter than the operation example shown in FIG. 6, and the input data E follows the input data D. In this modification, each piece of input data includes content data length and content data. However, in FIG. 7, only the internal structures of the input data C and D are illustrated, and the internal structures of the other input data are omitted. In the following, differences between the operation example shown in FIG. 7 and the operation example shown in FIG. 6 described above will be described.

The operation of the encoding unit 115 for the first to third segments from the left in FIG. 7 is the same as the operation example shown in FIG. 6 described above.

Subsequently, since the remaining input data B (B2) is shorter than the segment data portion, the encoding unit 115 causes the segment data portion to hold the divided data B2 (the fourth segment from the left in FIG. 7). Then, the encoding unit 115 waits for the subsequent input data C, D, and E, and concatenates the subsequent input data C and D and the divided data E1 of the subsequent input data E to the divided data B2 of the preceding input data B. Stored in the segment data part. Here, the encoding unit 115 causes the FHP to hold the first head position Y of the input data C and the LHP to hold the last head position W of the input data E in the segment data portion.

Subsequently, since the remaining input data E (E2) is shorter than the segment data portion, the encoding unit 115 causes the segment data portion to hold the divided data E2 (the fifth segment from the left in FIG. 7). Since the beginning of the input data is not included in the segment data portion, the encoding unit 115 causes both FHP and LHP to hold invalid values.

The operation of the decoding unit 135 for the first to third segments from the left in FIG. 7 is the same as the operation example shown in FIG. 6 described above.

Subsequently, the decoding unit 135 inputs the fourth segment (the fourth segment from the left in FIG. 7). The fourth segment holds the value "Y" in FHP and the value "W" in LHP. Therefore, the decoding unit 135 stores the divided data B2 of the second input data B immediately before the position “Y” of the fourth segment, and decodes the data from the position “Y” to the position “W” immediately before the position “W”. It is determined that the third and fourth input data (C+D) are stored by . Then, the decoding unit 135 determines that the divided data E1 of the fifth input data E is stored after the position "W" of the fourth segment. Since the input data B and (C+D) have been reconstructed, the decoding unit 135 outputs the reconstructed input data B and (C+D) to the outside as output data. Here, the fourth segment does not hold the leading position Z of the fourth input data D. Therefore, the decoding unit 135 cannot separate the third and fourth input data (C+D) into the third input data C and the fourth input data D.

Subsequently, the decoding unit 135 inputs the fifth segment (the fifth segment from the left in FIG. 7). The fifth segment holds invalid values for FHP and LHP. Therefore, the decoding unit 135 determines that the divided data E2 of the fifth input data E is continuously stored in the fifth segment.

As described above, the decoding unit 135 cannot separate the 3rd and 4th input data (C+D) into the 3rd input data C and the 4th input data D. However, the 3rd and 4th input data (C+D) is the concatenation of the 3rd input data C and the 4th input data D. Each of the input data C and D includes a content data length and content data. Therefore, if the structure of the output data is known, the device or program to which the output data of the memory access device 105 is input converts the third and fourth input data (C+D) to the third input data based on the content data length. Data C and fourth input data D can be separated and processed separately.

Therefore, the memory access device 105 of this modified example has the effect of being able to suppress writing of useless data other than input data to the memory during burst access to the memory. However, the memory access device 105 of this modification requires an external device or program for complete reconstruction of the input data. The memory access device 105 of this modification may include such an external device or program.

It is clear that this modification can be applied not only to the second embodiment but also to the first embodiment.

FIG. 8 is a block diagram showing an example of a hardware configuration that can implement a memory access device according to each embodiment of the present invention.

The memory access device 901 includes a storage device 902 , a CPU (Central Processing Unit) 903 , a keyboard 904 , a monitor 905 and an I/O (Input/Output) device 908 , which are connected by an internal bus 906 . ing. The storage device 902 stores operation programs of the CPU 903 of the encoding units 110, 115, memory control units 120, 125, decoding units 130, 135, etc. (hereinafter referred to as "encoding units, etc."). A CPU 903 controls the entire memory access device 901, executes an operation program stored in a storage device 902, and executes a program such as an encoding unit and transmits/receives data by an I/O device 908. FIG. The internal configuration of the memory access device 901 described above is an example. The memory access device 901 may have a configuration in which a keyboard 904 and a monitor 905 are connected as required.

The memory access device 901 in each of the above-described embodiments of the present invention may be realized by a dedicated device, but the I/O device 908 does not need a computer (information processing device). In this case, the computer reads the software program stored in the storage device 902 to the CPU 903 and executes the read software program in the CPU 903 . In the case of each of the above-described embodiments, it is sufficient that the software program includes a description capable of realizing the function of each part of the memory access device shown in FIGS. However, it is assumed that each of these units includes appropriate hardware. In such a case, such a software program (computer program) can be regarded as constituting the present invention. Furthermore, a computer-readable storage medium storing such a software program can also be regarded as constituting the present invention.

As above, the present invention has been exemplified by each of the above-described embodiments and modifications thereof. However, the technical scope of the present invention is not limited to the scope described in each of the above-described embodiments and modifications thereof. It is obvious to those skilled in the art that various modifications or improvements can be made to such embodiments. In such cases, new embodiments with such changes or improvements may also be included in the technical scope of the present invention. And this is clear from the matters described in the claims.

INDUSTRIAL APPLICABILITY The present invention can be used for storage devices that hold large amounts of data such as audio, moving images, or measurement data.

100, 105 memory access device 110, 115 encoder 120, 125 memory controller 130, 135 decoder 200 memory

Claims (6)

After dividing or concatenating multiple input data input from the outside in the order of input,
generating segment data that includes contiguous portions of the plurality of input data;
generating head position data representing the head position of each of the plurality of input data in the segment data;
encoding means for generating a segment including the segment data and the head position data;
writing the generated segments to memory in units of one or more segments;
memory control means for reading the segments from the memory in units of one or more segments;
decoding means for reconstructing the plurality of input data inputted from the outside based on the segments read out from the memory and outputting the reconstructed plurality of input data inputted from the outside to the outside; memory access device. The specifications of each of the input data and the segments are determined such that the lower limit of the data length of each of the input data is 1/n (n is an integer equal to or greater than 2) of the data length of the segment data. cage,
2. The memory access device according to claim 1, wherein said segment includes n pieces of head position data. Each of the input data
content data representing content included in each of the input data;
2. The memory access device according to claim 1, further comprising a content data length representing the data length of said content data. The specifications of each of the input data and the segments are determined such that the lower limit of the data length of each of the input data is 1/n (n is an integer equal to or greater than 2) of the data length of the segment data. cage,
4. The memory access device according to claim 3, wherein said segment includes the head position data whose number is smaller than n. After dividing or concatenating multiple input data input from the outside in the order of input,
generating segment data that includes contiguous portions of the plurality of input data;
generating head position data representing the head position of each of the plurality of input data in the segment data;
an encoding process for generating a segment including the segment data and the head position data;
writing the generated segments to memory in units of one or more segments;
a memory control process of reading the segments from the memory in units of one or more segments;
a decoding process of reconstructing the plurality of input data input from the outside based on the segments read from the memory, and outputting the reconstructed plurality of input data input from the outside to the outside. memory access method. After dividing or concatenating multiple input data input from the outside in the order of input,
generating segment data that includes contiguous portions of the plurality of input data;
generating head position data representing the head position of each of the plurality of input data in the segment data;
an encoding process for generating a segment including the segment data and the head position data;
writing the generated segments to memory in units of one or more segments;
a memory control process of reading the segments from the memory in units of one or more segments;
a decoding process of reconstructing the plurality of input data input from the outside based on the segments read from the memory and outputting the reconstructed plurality of input data input from the outside to the outside; memory access program to run.

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