JP2022166640A5 - - Google Patents
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- JP2022166640A5 JP2022166640A5 JP2021071990A JP2021071990A JP2022166640A5 JP 2022166640 A5 JP2022166640 A5 JP 2022166640A5 JP 2021071990 A JP2021071990 A JP 2021071990A JP 2021071990 A JP2021071990 A JP 2021071990A JP 2022166640 A5 JP2022166640 A5 JP 2022166640A5
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- circuit board
- copper foil
- heat sink
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 63
- 239000011889 copper foil Substances 0.000 claims description 51
- 238000007747 plating Methods 0.000 claims description 46
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 36
- 229910052709 silver Inorganic materials 0.000 claims description 34
- 239000004332 silver Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 32
- 238000004519 manufacturing process Methods 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000002245 particle Substances 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 239000000919 ceramic Substances 0.000 claims description 10
- 238000005304 joining Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 238000006073 displacement reaction Methods 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000005245 sintering Methods 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 238000005476 soldering Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 239000000843 powder Substances 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 2
- 239000011230 binding agent Substances 0.000 claims description 2
- 239000011888 foil Substances 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims 2
- 239000002344 surface layer Substances 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Description
本発明の第１３の態様は、半導体チップ搭載用の回路基板の製造方法であって、窒化ケイ素セラミックス基板の２つの主面のそれぞれに活性金属ペーストを塗布してペースト膜を形成する塗布工程と、両方の前記ペースト膜に第１の銅箔を重畳させ、かつ、少なくとも一方の前記第１の銅箔に、前記第１の銅箔の銅粒子よりも平均粒径が小さい第２の銅箔を重畳させて積層体を得る積層工程と、前記積層体を真空中または不活性ガス中で加熱しながら所定の面圧プロファイルに従って前記積層体を加圧することにより前記第１の銅箔を前記窒化ケイ素セラミックス基板に接合するとともに前記第２の銅箔を前記第１の銅箔に接合する、加熱加圧工程と、を備えることを特徴とする。 A thirteenth aspect of the present invention is a method for manufacturing a circuit board for mounting a semiconductor chip , which includes a coating step of applying an active metal paste to each of two main surfaces of a silicon nitride ceramic substrate to form a paste film. , a first copper foil is superimposed on both of the paste films, and a second copper foil having an average grain size smaller than the copper particles of the first copper foil is provided on at least one of the first copper foils. and nitriding the first copper foil by applying pressure to the laminate according to a predetermined surface pressure profile while heating the laminate in vacuum or in an inert gas. It is characterized by comprising a heating and pressing step of joining the second copper foil to the first copper foil while joining the silicon ceramic substrate .
本発明の第１４の態様は、第１３の態様に係る回路基板の製造方法であって、前記積層工程においては、両方の前記第１の銅箔に前記第２の銅箔を重畳させる、ことを特徴とする。 A fourteenth aspect of the present invention is the method for manufacturing a circuit board according to the thirteenth aspect , wherein in the laminating step, the second copper foil is superimposed on both the first copper foils. It is characterized by
本発明の第１５の態様は、第１１ないし第１４の態様のいずれかに係る回路基板の製造方法であって、前記活性金属ペーストが、チタン及びジルコニウムからなる群より選択される少なくとも１種の金属である活性金属の粉末と、銀粉末とを、金属粉末として少なくとも含み、かつ、有機成分としてバインダ及び溶剤を含む、ことを特徴とする。 A fifteenth aspect of the present invention is the method for manufacturing a circuit board according to any one of the eleventh to fourteenth aspects, wherein the active metal paste is at least one selected from the group consisting of titanium and zirconium. It is characterized in that it contains at least active metal powder and silver powder as metal powder, and also contains a binder and a solvent as organic components .
本発明の第１６の態様は、半導体モジュールの製造方法であって、第１ないし第５の態様のいずれかに係る回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、を備え、前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記電解銅箔に対して前記放熱板をはんだにて接合する、ことを特徴とする。 A sixteenth aspect of the present invention is a method for manufacturing a semiconductor module, which includes a plating step of forming a silver plating film by displacement silver plating on the circuit board according to any one of the first to fifth aspects; A chip mounting step of mounting a semiconductor chip by silver sintering on the main surface of the circuit board opposite to the main surface to which the heat sink is bonded, and one of the circuit boards that has undergone the plating step. a heat sink bonding step of bonding the heat sink plate with solder to the main surface of It is characterized by joining with solder.
本発明の第１７の態様は、半導体モジュールの製造方法であって、第６ないし第１０の態様のいずれかに係る回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、を備え、前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記銅箔の前記第２の部分に対して前記放熱板をはんだにて接合する、ことを特徴とする。 A seventeenth aspect of the present invention is a method for manufacturing a semiconductor module, comprising a plating step of forming a silver plating film by displacement silver plating on the circuit board according to any one of the sixth to tenth aspects; A chip mounting step of mounting a semiconductor chip by silver sintering on the main surface of the circuit board opposite to the main surface to which the heat sink is bonded, and one of the circuit boards that has undergone the plating step. a heat sink bonding step of bonding the heat sink to the main surface of the copper foil with solder, and in the heat sink bonding step, the second portion of the copper foil on which the silver plating film is formed is The heat dissipation plate is bonded to the heat sink by soldering.
本発明の第１８の態様は、半導体モジュールの製造方法であって、第１１または第１２の態様に係る製造方法にて製造された回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、を備え、前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記電解銅箔に対して前記放熱板をはんだにて接合する、ことを特徴とする。
本発明の第１９の態様は、半導体モジュールの製造方法であって、第１３または第１４の態様に係る製造方法にて製造された回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、を備え、前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記第２の銅箔に対して前記放熱板をはんだにて接合する、ことを特徴とする。
An 18th aspect of the present invention is a method for manufacturing a semiconductor module, in which a silver plating film is formed by displacement silver plating on a circuit board manufactured by the manufacturing method according to the 11th or 12th aspect. a chip mounting step of mounting a semiconductor chip by silver sintering on the main surface of the circuit board opposite to the main surface to which the heat dissipation plate is bonded after the plating step; and the plating step. a heat sink bonding step of bonding the heat sink plate to one main surface of the circuit board through solder, and in the heat sink bonding step, the electrolytic copper on which the silver plating film is formed is provided. It is characterized in that the heat sink is joined to the foil by soldering.
A nineteenth aspect of the present invention is a method for manufacturing a semiconductor module, which includes a plating step of forming a silver plating film by displacement silver plating on a circuit board manufactured by the manufacturing method according to the thirteenth or fourteenth aspect. and a chip mounting step of mounting a semiconductor chip by silver sintering on the main surface of the circuit board opposite to the main surface to which the heat sink is bonded, which has undergone the plating step, and the circuit board which has undergone the plating step. a heat sink bonding step of bonding the heat sink to one main surface of the substrate by soldering, and in the heat sink bonding step, the second copper foil on which the silver plating film is formed is The heat dissipation plate is joined to the heat sink by soldering.
本発明の第１ないし第１９の態様によれば、置換銀めっきにより銀めっき膜を設けたうえで回路基板の一方主面に半導体チップを搭載し、他方主面には放熱板をはんだ接合することによって、半導体モジュールを得る場合において、回路基板との銀焼結結合の接合信頼性については従来と同等に確保しつつ、回路基板と放熱板との接合信頼性について、従来よりも向上させることができる。
According to the first to nineteenth aspects of the present invention, a silver plating film is provided by displacement silver plating, a semiconductor chip is mounted on one main surface of the circuit board, and a heat sink is soldered to the other main surface. By doing so, when obtaining a semiconductor module, it is possible to improve the bonding reliability between the circuit board and the heat sink while ensuring the same reliability of the silver sintered bond with the circuit board as before. I can do it.
Claims (19)
窒化ケイ素セラミックス基板の２つの主面のそれぞれに圧延銅箔が接合されてなり、
少なくとも一方の前記圧延銅箔に電解銅箔が重畳されてなる、
ことを特徴とする、回路基板。 A circuit board for mounting a semiconductor chip,
Rolled copper foil is bonded to each of the two main surfaces of a silicon nitride ceramic substrate,
Electrolytic copper foil is superimposed on at least one of the rolled copper foils,
A circuit board characterized by:
前記圧延銅箔を構成する銅粒子の平均粒径が１００μｍ～１０００μｍであり、
前記電解銅箔を構成する銅粒子の平均粒径が１００μｍ未満である、
ことを特徴とする、回路基板。 The circuit board according to claim 1,
The average particle size of the copper particles constituting the rolled copper foil is 100 μm to 1000 μm,
The average particle size of the copper particles constituting the electrolytic copper foil is less than 100 μm,
A circuit board characterized by:
前記圧延銅箔の厚みが３００μｍ～２５００μｍであり、
前記電解銅箔の厚みが５μｍ～５０μｍである、
ことを特徴とする、回路基板。 The circuit board according to claim 1 or 2,
The thickness of the rolled copper foil is 300 μm to 2500 μm,
The thickness of the electrolytic copper foil is 5 μm to 50 μm,
A circuit board characterized by:
両方の前記圧延銅箔に前記電解銅箔が重畳されてなる、
ことを特徴とする、回路基板。 The circuit board according to any one of claims 1 to 3,
The electrolytic copper foil is superimposed on both of the rolled copper foils,
A circuit board characterized by:
一方の前記圧延銅箔にのみ前記電解銅箔が重畳されてなる、
ことを特徴とする、回路基板。 The circuit board according to any one of claims 1 to 3,
The electrolytic copper foil is superimposed on only one of the rolled copper foils,
A circuit board characterized by:
窒化ケイ素セラミックス基板の２つの主面のそれぞれに銅箔が接合されてなり、
少なくとも一方の前記銅箔が、
前記窒化ケイ素セラミックス基板との接合部分である第１の部分と、
当該銅箔の表層部分である第２の部分と、
を備え、
前記第１の部分の銅粒子よりも前記第２の部分の銅粒子の方が平均粒径が小さい、
ことを特徴とする、回路基板。 A circuit board for mounting a semiconductor chip,
Copper foil is bonded to each of the two main surfaces of a silicon nitride ceramic substrate,
At least one of the copper foils is
a first portion that is a joint portion with the silicon nitride ceramic substrate;
a second portion that is a surface layer portion of the copper foil;
Equipped with
The copper particles in the second part have a smaller average particle size than the copper particles in the first part.
A circuit board characterized by:
前記第１の部分の銅粒子の平均粒径が１００μｍ～１０００μｍであり、
前記第２の部分の銅粒子の平均粒径が１００μｍ未満である、
ことを特徴とする、回路基板。 The circuit board according to claim 6,
The average particle size of the copper particles in the first portion is 100 μm to 1000 μm,
the average particle size of the copper particles in the second portion is less than 100 μm;
A circuit board characterized by:
前記第１の部分の厚みが３００μｍ～２５００μｍであり、
前記第２の部分の厚みが５μｍ～５０μｍである、
ことを特徴とする、回路基板。 The circuit board according to claim 6 or 7,
The thickness of the first portion is 300 μm to 2500 μm,
The thickness of the second portion is 5 μm to 50 μm,
A circuit board characterized by:
前記２つの主面の両方に接合されてなる前記銅箔がともに、前記第１の部分と前記第２の部分とを備える、
ことを特徴とする、回路基板。 The circuit board according to any one of claims 6 to 8,
Both of the copper foils bonded to both of the two main surfaces include the first portion and the second portion,
A circuit board characterized by:
前記２つの主面の一方に接合されてなる前記銅箔のみが、前記第１の部分と前記第２の部分とを備え、
前記２つの主面の他方に接合されてなる前記銅箔を構成する銅粒子の平均粒径が、前記第２の部分を構成する銅粒子の平均粒径よりも大きく、前記第１の部分の銅粒子の平均粒径の取り得る範囲と同じ範囲内の値である、
ことを特徴とする、回路基板。 The circuit board according to any one of claims 6 to 8,
Only the copper foil bonded to one of the two main surfaces includes the first portion and the second portion,
The average grain size of the copper particles constituting the copper foil bonded to the other of the two main surfaces is larger than the average grain size of the copper particles constituting the second portion, and A value within the same range as the average particle size of copper particles,
A circuit board characterized by:
窒化ケイ素セラミックス基板の２つの主面のそれぞれに活性金属ペーストを塗布してペースト膜を形成する塗布工程と、
両方の前記ペースト膜に圧延銅箔を重畳させ、かつ、少なくとも一方の前記圧延銅箔に電解銅箔を重畳させて積層体を得る積層工程と、
前記積層体を真空中または不活性ガス中で加熱しながら所定の面圧プロファイルに従って前記積層体を加圧することにより前記圧延銅箔を前記窒化ケイ素セラミックス基板に接合するとともに前記電解銅箔を前記圧延銅箔に接合する、加熱加圧工程と、
を備えることを特徴とする、回路基板の製造方法。 A method for manufacturing a circuit board for mounting a semiconductor chip, the method comprising:
a coating step of coating each of the two main surfaces of the silicon nitride ceramic substrate with an active metal paste to form a paste film;
a laminating step of superimposing rolled copper foil on both of the paste films and superimposing electrolytic copper foil on at least one of the rolled copper foils to obtain a laminate;
The rolled copper foil is bonded to the silicon nitride ceramic substrate by pressing the laminate according to a predetermined surface pressure profile while heating the laminate in a vacuum or in an inert gas, and the electrolytic copper foil is bonded to the rolled copper foil. A heating and pressing process for bonding to copper foil,
A method for manufacturing a circuit board, comprising:
前記積層工程においては、両方の前記圧延銅箔に前記電解銅箔を重畳させる、
ことを特徴とする、回路基板の製造方法。 The method for manufacturing a circuit board according to claim 11,
In the laminating step, the electrolytic copper foil is superimposed on both of the rolled copper foils,
A method for manufacturing a circuit board, characterized by:
窒化ケイ素セラミックス基板の２つの主面のそれぞれに活性金属ペーストを塗布してペースト膜を形成する塗布工程と、a coating step of coating active metal paste on each of the two main surfaces of the silicon nitride ceramic substrate to form a paste film;
両方の前記ペースト膜に第１の銅箔を重畳させ、かつ、少なくとも一方の前記第１の銅箔に、前記第１の銅箔の銅粒子よりも平均粒径が小さい第２の銅箔を重畳させて積層体を得る積層工程と、A first copper foil is superimposed on both of the paste films, and a second copper foil having an average grain size smaller than the copper particles of the first copper foil is placed on at least one of the first copper foils. a lamination step of obtaining a laminate by overlapping;
前記積層体を真空中または不活性ガス中で加熱しながら所定の面圧プロファイルに従って前記積層体を加圧することにより前記第１の銅箔を前記窒化ケイ素セラミックス基板に接合するとともに前記第２の銅箔を前記第１の銅箔に接合する、加熱加圧工程と、By applying pressure to the laminate according to a predetermined surface pressure profile while heating the laminate in vacuum or in an inert gas, the first copper foil is bonded to the silicon nitride ceramic substrate, and the second copper foil is bonded to the silicon nitride ceramic substrate. a heating and pressing step of joining the foil to the first copper foil;
を備えることを特徴とする、回路基板の製造方法。A method for manufacturing a circuit board, comprising:
前記積層工程においては、両方の前記第１の銅箔に前記第２の銅箔を重畳させる、In the lamination step, the second copper foil is superimposed on both the first copper foils,
ことを特徴とする、回路基板の製造方法。A method for manufacturing a circuit board, characterized by:
前記活性金属ペーストが、チタン及びジルコニウムからなる群より選択される少なくとも１種の金属である活性金属の粉末と、銀粉末とを、金属粉末として少なくとも含み、かつ、有機成分としてバインダ及び溶剤を含む、
ことを特徴とする、回路基板の製造方法。 A method for manufacturing a circuit board according to any one of claims 11 to 14,
The active metal paste contains at least an active metal powder that is at least one metal selected from the group consisting of titanium and zirconium, and silver powder as metal powder, and also contains a binder and a solvent as organic components. ,
A method for manufacturing a circuit board, characterized by:
請求項１ないし請求項５のいずれかに記載の回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、
前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、
前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、
を備え、
前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記電解銅箔に対して前記放熱板をはんだにて接合する、
ことを特徴とする、半導体モジュールの製造方法。 A method for manufacturing a semiconductor module, the method comprising:
A plating step of forming a silver plating film on the circuit board according to any one of claims 1 to 5 by displacement silver plating,
a chip mounting step of mounting a semiconductor chip by silver sintering on the main surface of the circuit board that has undergone the plating step, which is opposite to the main surface to which the heat sink is bonded;
a heat sink joining step of joining the heat sink with solder to one main surface of the circuit board that has undergone the plating step;
Equipped with
In the heat sink bonding step, the heat sink is bonded to the electrolytic copper foil on which the silver plating film is formed by soldering.
A method for manufacturing a semiconductor module, characterized in that:
請求項６ないし請求項１０のいずれかに記載の回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、
前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、
前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、
を備え、
前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記銅箔の前記第２の部分に対して前記放熱板をはんだにて接合する、
ことを特徴とする、半導体モジュールの製造方法。 A method for manufacturing a semiconductor module, the method comprising:
A plating step of forming a silver plating film on the circuit board according to any one of claims 6 to 10 by displacement silver plating,
a chip mounting step of mounting a semiconductor chip by silver sintering on the main surface of the circuit board that has undergone the plating step, which is opposite to the main surface to which the heat sink is bonded;
a heat sink joining step of joining the heat sink with solder to one main surface of the circuit board that has undergone the plating step;
Equipped with
In the heat sink bonding step, the heat sink is bonded to the second portion of the copper foil on which the silver plating film is formed by soldering.
A method for manufacturing a semiconductor module, characterized in that:
請求項１１または請求項１２に記載の製造方法にて製造された回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、
前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、
前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、
を備え、
前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記電解銅箔に対して前記放熱板をはんだにて接合する、
ことを特徴とする、半導体モジュールの製造方法。 A method for manufacturing a semiconductor module, the method comprising:
A plating step of forming a silver plating film by displacement silver plating on a circuit board manufactured by the manufacturing method according to claim 11 or 12 ;
a chip mounting step of mounting a semiconductor chip by silver sintering on the main surface of the circuit board that has undergone the plating step, which is opposite to the main surface to which the heat sink is bonded;
a heat sink joining step of joining the heat sink with solder to one main surface of the circuit board that has undergone the plating step;
Equipped with
In the heat sink bonding step, the heat sink is bonded to the electrolytic copper foil on which the silver plating film is formed by soldering.
A method for manufacturing a semiconductor module, characterized in that:
請求項１３または請求項１４に記載の製造方法にて製造された回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、A plating step of forming a silver plating film by displacement silver plating on the circuit board manufactured by the manufacturing method according to claim 13 or 14,
前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、a chip mounting step of mounting a semiconductor chip by silver sintering on the main surface of the circuit board that has undergone the plating step, which is opposite to the main surface to which the heat sink is bonded;
前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、a heat sink bonding step of bonding the heat sink with solder to one main surface of the circuit board that has undergone the plating step;
を備え、Equipped with
前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記第２の銅箔に対して前記放熱板をはんだにて接合する、In the heat sink bonding step, the heat sink is bonded to the second copper foil on which the silver plating film is formed by soldering.
ことを特徴とする、半導体モジュールの製造方法。A method for manufacturing a semiconductor module, characterized in that:
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| JP2021071990A JP2022166640A (en) | 2021-04-21 | 2021-04-21 | Circuit board, method for manufacturing circuit board, and method for manufacturing semiconductor module |
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|---|---|---|---|
| JP2021071990A JP2022166640A (en) | 2021-04-21 | 2021-04-21 | Circuit board, method for manufacturing circuit board, and method for manufacturing semiconductor module |
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| JP2022166640A JP2022166640A (en) | 2022-11-02 |
| JP2022166640A5 true JP2022166640A5 (en) | 2023-12-19 |
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| JP2021071990A Pending JP2022166640A (en) | 2021-04-21 | 2021-04-21 | Circuit board, method for manufacturing circuit board, and method for manufacturing semiconductor module |
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