JP2022163423A - Multilayer ceramic capacitor - Google Patents

Abstract

To provide a multilayer ceramic capacitor having an external electrode on the side surface of a laminated body, capable of enlarging an effective area, which is an overlapping area of internal electrode layers in the lamination direction, and increasing capacity.SOLUTION: A multilayer ceramic capacitor according to the present invention includes a laminated body in which a plurality of dielectric layers are laminated, a first internal electrode layers led out to both end surfaces of the laminated body, and a second internal electrode layer that is not led out to both end surfaces and both side surfaces of the laminated body. The laminated body includes an inner layer portion in which a plurality of internal electrode layers face each other, a main surface side outer layer portion located on both main surface sides, a side surface side outer layer portion located on both side surfaces, and an end surface side outer layer portion located on both end surface sides. A connection conductor to be connected to the second internal electrode layer is arranged on both side outer layer portions. First and second external electrodes are connected to the first internal electrode layer, and third and fourth external electrodes are connected to the second internal electrode layer via the connection conductor.SELECTED DRAWING: Figure 9

Description

The present invention relates to multilayer ceramic capacitors.

Conventionally, there has been known an electronic component including a multilayer body in which internal electrodes and dielectric layers are alternately laminated, and external electrodes electrically connected to the internal electrodes and formed on the surface of the multilayer body. .

As one of such electronic components, Patent Literature 1 describes a laminated ceramic capacitor having external electrodes provided on both end surfaces of a laminate and external terminals provided on both side surfaces. In this laminated ceramic capacitor, signal internal electrodes drawn out from both end surfaces of the laminate and grounding internal electrodes drawn out from both side surfaces of the laminate are alternately laminated via dielectric layers. External electrodes electrically connected to the signal internal electrodes are provided on both end surfaces of the laminate, and grounding external terminals electrically connected to the grounding internal electrodes are provided on both side surfaces of the laminate. It is

JP 2016-86118 A

However, in the multilayer ceramic capacitor described in Patent Document 1, the grounding internal electrodes have portions drawn out to both side surfaces of the laminate, so that the signal internal electrodes and the grounding internal electrodes overlap in the stacking direction. There is a problem that the effective area becomes smaller and the capacitance becomes smaller accordingly.

SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a multilayer ceramic capacitor having external electrodes on the side surfaces of a multilayer body, in which the effective region, which is the region where the internal electrode layers overlap in the stacking direction, is enlarged to increase the capacitance. An object of the present invention is to provide a multilayer ceramic capacitor capable of

A multilayer ceramic capacitor according to the present invention has a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and has a first main surface and a second main surface facing each other in the lamination direction. , a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction, and a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction and the length direction. a first external electrode arranged on the first end surface; a second external electrode arranged on the second end surface; and a second external electrode arranged on the first side surface. A multilayer ceramic capacitor having three external electrodes and a fourth external electrode arranged on a second side surface, wherein the laminate includes an internal layer portion in which a plurality of internal electrode layers face each other; a first side surface formed of a plurality of dielectric layers positioned between the first side surface, the outermost surface of the inner layer portion on the first side surface side, and an extension line of the outermost surface; and a plurality of dielectric layers located on the second side surface side and between the outermost surface of the inner layer portion on the second side surface and the second side surface side and the extension line of the outermost surface. a plurality of outer layer portions located on the first end surface side and between the first end surface, the outermost surface of the inner layer portion on the first end surface side, and an extension line of the outermost surface a first end surface side outer layer portion formed from a dielectric layer of , an outermost surface of the inner layer portion located on the second end surface side and on the second end surface and the second end surface side, and an extension line of the outermost surface and a second end surface side outer layer portion formed from a plurality of dielectric layers positioned between the plurality of internal electrode layers disposed on the plurality of dielectric layers, the first end surface and the second a first internal electrode layer drawn out to two end faces; and a second internal electrode layer that is not drawn out to either the end surface or the second end surface, and the second internal electrode layer is provided on the first side outer layer portion and the second side side outer layer portion. and the second internal electrode layer is connected to the third external electrode and the fourth external electrode through the connection conductor.

A multilayer ceramic capacitor according to the present invention has a first external electrode layer disposed on a first end surface of a multilayer body, a second external electrode layer disposed on a second end surface, and a first side surface. A third external electrode is arranged on the upper surface, and a fourth external electrode is arranged on the second side surface. Therefore, in such a multilayer ceramic capacitor, the effective region, which is the region where the internal electrode layers overlap in the height direction, can be expanded, and as a result, the effective volume can be improved to increase the capacity. .

According to the present invention, there is provided a multilayer ceramic capacitor having external electrodes on the side surfaces of the multilayer body, wherein the effective region, which is the region in which the internal electrode layers overlap in the stacking direction, can be expanded to increase the capacitance. A capacitor can be provided.

The above object, other objects, features and advantages of the present invention will become more apparent from the following description of the mode for carrying out the invention with reference to the drawings.

1 is an external perspective view showing an example of a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) according to an embodiment of the present invention; FIG. 1 is a top view showing an example of a multilayer ceramic capacitor (three-terminal multilayer ceramic capacitor) according to an embodiment of the present invention; FIG. Figure 3 is a cross-sectional view along line III-III of Figure 2; 3 is a cross-sectional view taken along line IV-IV of FIG. 2; FIG. 3 is a cross-sectional view taken along line VV of FIG. 2; FIG. FIG. 3 is a cross-sectional view taken along line VI-VI of FIG. 2; 6 is a cross-sectional view showing a modification of the side external electrode layer shown in FIG. 5; FIG. FIG. 4 is a cross-sectional view along line VIII-VIII of FIG. 3; 4 is a cross-sectional view taken along line IX-IX of FIG. 3; FIG. 1 is an exploded perspective view of a laminate that constitutes a laminated ceramic capacitor according to an embodiment of the present invention; FIG. 1 is a perspective view of a dielectric sheet having patterns of first internal electrode layers formed thereon, which is prepared in the process of manufacturing a multilayer ceramic capacitor according to the present invention; FIG. FIG. 4 is a perspective view of a dielectric sheet having patterns of second internal electrode layers formed thereon, which is prepared in the manufacturing process of the multilayer ceramic capacitor according to the present invention; 1 is a perspective view of a laminated block for inner layers manufactured in a manufacturing process of a multilayer ceramic capacitor according to the present invention; FIG. (a) to (e) are explanatory diagrams of a manufacturing process of the side outer layer block. FIG. 4 is a diagram showing a state in which strip-shaped blocks for a first side outer layer portion and a second side outer layer portion are crimped to inner layer strip-shaped blocks; 1 is an external perspective view of a multilayer chip manufactured in a manufacturing process of a multilayer ceramic capacitor according to the present invention; FIG.

1. Laminated Ceramic Capacitor A laminated ceramic capacitor according to an embodiment of the present invention will be described. The laminated ceramic capacitor according to this embodiment is a three-terminal laminated ceramic capacitor.

FIG. 1 is an external perspective view showing an example of a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) according to an embodiment of the present invention. FIG. 2 is a top view showing an example of a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) according to an embodiment of the present invention. 3 is a cross-sectional view along line III-III of FIG. 2; FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 2. FIG. 5 is a cross-sectional view taken along line VV of FIG. 2. FIG. FIG. 6 is a cross-sectional view taken along line VI--VI of FIG. FIG. 7 is a cross-sectional view showing a modification of the side external electrode layer shown in FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. 3. FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. 3. FIG. FIG. 10 is an exploded perspective view of a laminate constituting a laminated ceramic capacitor according to an embodiment of the invention.

As shown in FIG. 1, the laminated ceramic capacitor 10 includes, for example, a rectangular parallelepiped laminate 12 and external electrodes 30 .

(A) Laminate The laminate 12 has a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 16 laminated on the dielectric layers 14 . The dielectric layers 14 and the internal electrode layers 16 are laminated in the height direction x.
Moreover, the laminate 12 has, as the plurality of internal electrode layers 16, a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b.

The laminate 12 has a first main surface 12a and a second main surface 12b facing in the height direction x, and a first side surface 12c and a second side surface facing in the width direction y orthogonal to the height direction x. 12d, and a first end face 12e and a second end face 12f facing each other in a length direction z orthogonal to the height direction x and width direction y. The laminate 12 has rounded corners and ridges. A corner portion is a portion where three adjacent surfaces of the laminate intersect, and a ridge portion is a portion where two adjacent surfaces of the laminate intersect. In addition, unevenness or the like is formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. may have been

The dimensions of the laminate 12 are not particularly limited.

The laminate 12 has an inner layer portion 18, and a first main surface side outer layer portion 20a and a second main surface side outer layer portion 20b that are arranged to sandwich the inner layer portion 18 in the height direction x.

The inner layer section 18 includes multiple dielectric layers 14 and multiple internal electrode layers 16 . The inner layer portion 18 includes from the internal electrode layer 16 closest to the first main surface 12a to the internal electrode layer 16 closest to the second main surface 12b in the height direction x. In the inner layer portion 18 , a plurality of internal electrode layers 16 are arranged facing each other with the dielectric layers 14 interposed therebetween. The inner layer portion 18 is a portion that generates capacitance and substantially functions as a capacitor.

The first main surface side outer layer portion 20a is located on the first main surface 12a side. The first main surface side outer layer portion 20a is an assembly of a plurality of dielectric layers 14 positioned between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a.
The second main surface side outer layer portion 20b is located on the second main surface 12b side. The second main surface side outer layer portion 20b is an assembly of a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.
The dielectric layer 14 used in the first main surface side outer layer portion 20 a and the second main surface side outer layer portion 20 b may be the same as the dielectric layer 14 used in the inner layer portion 18 .

The dimension in the height direction x of the first principal surface side outer layer portion 20a and the second principal surface side outer layer portion 20b is preferably 10 μm or more and 50 μm or less.

Note that the laminate 12 is formed from a plurality of dielectric layers 14 located on the side of the first side surface 12c and located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the side of the first side surface 12c. It has a first side outer layer portion 22a that is attached.
Similarly, the laminated body 12 is formed from the plurality of dielectric layers 14 located on the second side surface 12d side and located between the second side surface 12d and the outermost surface of the inner layer portion 18 on the second side surface 12d side. It has a second side outer layer portion 22b formed thereon.

The dimension in the width direction y of the first side outer layer portion 22a and the second side outer layer portion 22b is preferably 5 μm or more and 30 μm or less. As a result, the effective area of the multilayer ceramic capacitor 10 can be increased, which has the effect of improving the acquired capacitance.

The dimensions in the width direction y of the first side outer layer portion 22a and the second side outer layer portion 22b are the same as those of the first side outer layer portion 22a and the second side outer layer portion 22b along the height direction x. means the average value calculated based on the measured values at multiple locations measured at multiple locations.

Here, the method for measuring the dimension in the width direction y of the first side outer layer portion 22a and the second side outer layer portion 22b is as follows.
That is, first, the WT section including the width direction y and the height direction x of the multilayer ceramic capacitor 10 is exposed. Next, either the end portion in the width direction y of the first internal electrode layer 16a and the second internal electrode layer 16b in the WT cross section or the two side outer layer portions located on both outer sides in the width direction y An image is taken with an optical microscope so that one of the first side outer layer portion 22a or the second side outer layer portion 22b is placed in the same field of view. The imaging locations are three locations in the height direction x: the upper portion, the central portion, and the lower portion. In the upper, central and lower portions, the first internal electrode layers 16a and the second internal electrode layers 16b have widths from the ends in the width direction y toward the first side surface 12c or the second side surface 12d. A plurality of line segments parallel to the direction y are drawn and the length of each line segment is measured. About the length of the line segment thus measured, the average value of each of the upper portion, the middle portion, and the lower portion is calculated. By further averaging the respective average values, the dimension in the width direction y of the first side outer layer portion 22a and the second side outer layer portion 22b is obtained.

The connection conductors 17 connected to the second internal electrode layers 16b are disposed on the first side-side outer layer portion 22a and the second side-side outer layer portion 22b. It is connected to the third external electrode 30c and the fourth external electrode 30d via. Details of the connection conductor 17 will be described later.

The first side outer layer portion 22a and the second side outer layer portion 22b are, for example, a laminate chip that becomes the inner layer portion 18, the main surface side outer layer portions 20a and 20b, and the end surface side outer layer portions 24a and 24b after firing. After manufacturing, ceramic green sheets are attached to both sides of the laminate chip and fired. It should be noted that a ceramic slurry that becomes a ceramic green sheet may be applied to both sides.

Further, the laminate 12 is located on the first end face side 12e side, and from the plurality of dielectric layers 14 located between the first end face 12e and the outermost surface of the inner layer portion 18 on the first end face 12e side. It has a first end surface side outer layer portion 24a formed thereon.
Similarly, the laminated body 12 is located on the side of the second end face 12f, and from the plurality of dielectric layers 14 located between the second end face 12f and the outermost surface of the inner layer portion 18 on the side of the second end face 12f. It has a second end face side outer layer portion 24b formed thereon.

The dimension in the length direction z of the first end surface side outer layer portion 24a and the second end surface side outer layer portion 24b is preferably 10 μm or more and 70 μm or less. As a result, intrusion of moisture from the outside can be suppressed, and insulation can be ensured. Also, an effective area can be secured in order to satisfy a predetermined capacitance.

The composition of the dielectric layer 14 positioned in the inner layer portion 18 differs from the composition of the first side outer layer portion 22a and the second side outer layer portion 22b, and the composition of the dielectric layer 14 positioned in the inner layer portion 18, The compositions of the first end surface side outer layer portion 24a and the second end surface side outer layer portion 24b are the same. As a result, the composition of the side outer layer portion can be changed to make it more dense, so that the penetration of moisture from the outside can be suppressed, and a higher quality chip can be produced.

Specifically, the composition of the dielectric layer 14 located in the inner layer portion 18 uses a dielectric ceramic whose main component is BaTiO ₃ . Moreover, you may use what added the subcomponents, such as a Mn compound and a Ni compound, to these main components.

A dielectric ceramic containing BaTiO ₃ as a main component is used for the composition of the first side outer layer portion 22a and the second side outer layer portion 22b. Further, in addition to the above-described main components, subcomponents of Mg compounds are added to the first side outer layer portion 22a and the second side outer layer portion 22b. Here, the composition of the dielectric layer 14 located in the inner layer portion 18 and the first The compositions of the side outer layer portion 22a and the second side outer layer portion 22b are different. As with the inner layer portion 18, subcomponents such as Mn compounds and Ni compounds may be further added to the first side outer layer portion 22a and the second side outer layer portion 22b.

A dielectric ceramic containing BaTiO ₃ as a main component is used for the composition of the first end surface side outer layer portion 24a and the second end surface side outer layer portion 24b. Moreover, you may use what added the subcomponents, such as a Mn compound and a Ni compound, to these main components.

Here, the method for measuring the composition of the dielectric layer 14 located in the inner layer portion 18 and the composition of the first side outer layer portion 22a and the second side outer layer portion 22b is as follows.
That is, the laminated ceramic capacitor 10 is made into a state in which the inside can be observed by forming a cross section by, for example, breaking or polishing. Then, composition analysis is performed on the cross section using a wavelength dispersive X-ray spectrometer (WDX) or a transmission electron microscope (TEM) to determine the inner layer portion 18, the first side outer layer portion 22a, and the second outer layer portion 22a. can analyze the composition of the side surface side outer layer portion 22b. Also, the first end face side outer layer portion 24a and the second end face side outer layer portion 24b can be analyzed by the same method.

The thickness of the dielectric layer 14 after firing is preferably 0.3 μm or more and 4.0 μm or less.
The number of laminated dielectric layers 14 is preferably 20 or more and 1000 or less. The number of dielectric layers 14 is the number of dielectric layers 14 of the inner layer portion 18 and the number of dielectric layers 14 of the first outer layer portion 20a and the second outer layer portion 20b. is the total number of

In addition, as shown in FIG. 7, a plurality of first side outer layer portions 22a and second side outer layer portions 22b may be provided in the width direction y. Specifically, the first side outer layer portion 22a includes an outer first side outer layer portion 22a ₁ and an inner first side outer layer portion 22a ₂ , and the second side outer layer portion 22b includes an outer first side outer layer portion 22a 1 and an inner first side outer layer portion 22a 2 . A second side outer layer portion 22b ₁ and an inner second side outer layer portion 22b ₂ may be provided.

The first outer layer portion 22a ₁ is located on the first side surface 12c side of the laminate 12, and the second outer layer portion 22b ₁ is located on the second side surface 12d side of the laminate 12. do.
The inner first side outer layer portion 22a ₂ is located on the inner layer portion 18 side, i.e., inside the outer first side outer layer portion 22a ₁ in the width direction y, and is positioned closer to the inner second side outer layer portion 22b ₂ . is located on the inner layer portion 18 side, that is, on the inner side in the width direction y of the outer second side outer layer portion 22b ₁ .

It should be noted that the fact that the plurality of first side outer layer portions 22a and second side outer layer portions 22b are provided means that the outer first side outer layer portion 22a ₁ and the inner first side outer layer portion 22a ₂ are provided. and the difference in sinterability between the outer second side outer layer portion 22b ₁ and the inner second side outer layer portion 22b ₂ . Boundaries can be checked. That is, between the outer first side outer layer portion 22a ₁ and the inner first side outer layer portion 22a ₂ and between the outer second side outer layer portion 22b ₁ and the inner second side outer layer portion 22b ₂ There is a boundary between

In this modification, the first side outer layer portion 22a and the second side outer layer portion 22b are made of a dielectric ceramic material having a perovskite structure composed mainly of BaTiO ₃ , for example. there is These main components contain Si as an additive.

The outer first side outer layer portion 22a ₁ and the outer second side outer layer portion 22b ₁ have a higher Si content than the inner first side outer layer portion 22a ₂ and the inner second side outer layer portion 22b ₂ . A high content is preferred. That is, in the outer first side outer layer portion 22a ₁ and the outer _second side outer layer portion 22b ₁ , the molar ratio of Si to Ti is It is higher than the molar ratio of Si to Ti in the outer layer portion 22b ₂ . For example, the molar ratio of Si to Ti in the outer first side outer layer portion 22a ₁ and the outer second side outer layer portion 22b ₁ is 3.5 or more and 6.0 or less, and the inner first side outer layer portion The molar ratio of Si to Ti in 22a ₂ and inner second side outer layer portion 22b ₂ is 0.02 or more and 3.5 or less. Each molar ratio can be measured by WDX analysis or TEM.

Since Si acts as a sintering aid, the first outer layer portion 22a ₁ and the second outer layer portion 22b ₁ obtained by firing during manufacturing of the multilayer ceramic capacitor 10 are formed from the inner first side surface. It has a denser structure than the side outer layer portion 22a ₂ and the inner second side outer layer portion 22b ₂ . Thereby, the strength of the first side outer layer portion 22a and the second side outer layer portion 22b can be improved. As a result, the first side outer layer portion 22a and the second side outer layer portion 22b are less likely to be cracked or chipped, and moisture can be prevented from entering the interior.

(B) Internal Electrode Layers The laminate 12 has, as the internal electrode layers 16, a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b.
That is, the plurality of internal electrode layers 16 are arranged on the plurality of dielectric layers 14, the first internal electrode layers 16a drawn out to the first end face 12e and the second end face 12f, and the plurality of dielectric layers 14 12a and 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. and second internal electrode layers 16b.

As shown in FIG. 8, the first internal electrode layer 16a is formed in a substantially rectangular shape, and has notches 26 on both sides in the width direction y at the central portion in the length direction z. That is, the first internal electrode layer 16a has a dimension in the width direction y smaller than the dimension in the width direction y of the dielectric layer 14 by the notch portion 26 .
The first internal electrode layer 16a extends to the first end surface 12e and the second end surface 12f of the laminate 12 in the length direction z. The first internal electrode layer 16a extends in the width direction y to a position in contact with the first side outer layer portion 22a and the second side outer layer portion 22b except for the notch portion 26 .
Further, a first connection conductor 17a, which will be described later, is arranged in the first side outer layer portion 22a so as to face the notch portion 26. As shown in FIG.

The second internal electrode layer 16b has a shape that does not come into contact with the first end surface 12e and the second end surface 12f on which the external electrodes 30 are arranged. That is, as shown in FIG. 9, the second internal electrode layer 16b extends in the width direction y to a position where it contacts the first side outer layer portion 22a and the second side outer layer portion 22b. In addition, one end of the second internal electrode layer 16b does not extend to the first end face 12e of the laminate 12 in the length direction z, and the other end extends to the second end face 12e of the laminate 12. It does not extend to the end face 12f. Therefore, when the size of the dielectric layer 14 is used as a reference, one end of the second internal electrode layer 16b in the length direction z is located inside the first end face 12e by a predetermined distance in the length direction z. The other end of the second internal electrode layer 16b in the length direction z is located inside the second end surface 12f by a predetermined distance in the length direction z.
The second internal electrode layer 16b is provided on the first side surface 12c and the second side surface 12d of the laminate 12 via a second connection conductor 17b, which will be described later. is connected to the external electrode 30d. In other words, the second internal electrode layer 16b does not have a lead portion that protrudes in the width direction y and is connected to the third external electrode 30c and the fourth external electrode 30d.
The maximum dimension in the width direction y of the second internal electrode layers 16b is substantially the same as the maximum dimension in the width direction y of the first internal electrode layers 16a.

The first internal electrode layers 16a and the second internal electrode layers 16b contain Ni, for example. In addition to Ni, the first internal electrode layers 16a and the second internal electrode layers 16b may contain metals such as Cu, Ag, Pd, Ag—Pd alloy, and Au.
The first internal electrode layers 16a and the second internal electrode layers 16b may contain the same dielectric material as the dielectric ceramic contained in the dielectric layers 14 as a common material.

The number of stacked internal electrode layers 16 including the first internal electrode layers 16a and the second internal electrode layers 16b is, for example, 20 or more and 1000 or less.
The thicknesses of the first internal electrode layers 16a and the second internal electrode layers 16b are preferably, for example, 0.1 μm or more and 0.8 μm or less.

The first internal electrode layers 16a and the second internal electrode layers 16b contain Si and Ti. The molar ratio of Si to Ti contained in the second internal electrode layers 16b having uniform dimensions in the width direction y is higher at the edges in the width direction y than at the center portion in the width direction y of the second internal electrode layers 16b. part is larger. That is, Si is segregated at the ends in the width direction y of the second internal electrode layers 16b. Similarly, Si is segregated also at the ends in the width direction y of the first internal electrode layers 16a.
The respective amounts of Ti and Si contained in the first internal electrode layers 16a and the second internal electrode layers 16b are, for example, after polishing the multilayer ceramic capacitor 10 to expose the second internal electrode layers 16b. , can be determined using a wavelength dispersive X-ray analyzer (WDX).

(C) Connection Conductor The connection conductor 17 is arranged inside the first side outer layer portion 22a and the second side outer layer portion 22b.
The connection conductor 17 includes a first connection conductor 17a arranged in a layer at the same height position as the first internal electrode layer 16a, and a second connection conductor 17a arranged in a layer at the same height position as the second internal electrode layer 16b. 2 connecting conductors 17b.

The first connection conductor 17a is arranged at a position facing the notch 26 of the first internal electrode layer 16a with a predetermined gap therebetween, and is not electrically connected to the first internal electrode layer 16a. The first connection conductor 17a is exposed from the first side surface 12c and the second side surface 12d of the laminate 12, and the exposed portions are covered with the third external electrode 30c and the fourth external electrode 30d. . Also, the first connection conductor 17a is arranged on the dielectric layer 14 in a portion that will become the first side outer layer portion 22a and the second side outer layer portion 22b.

The second connection conductor 17b is arranged to electrically connect the second internal electrode layer 16b and the third external electrode 30c and the second internal electrode layer 16b and the fourth external electrode 30d. . In addition, the second connection conductor 17b is arranged on the dielectric layer 14 in a portion that becomes the first side outer layer portion 22a and the second side outer layer portion 22b.
As a result, a path extending to the internal electrode layer 16 and the external electrode 30 can be formed at the same time as the formation of the lateral side outer layer portion in the width direction y. The outer layer can be formed uniformly and thinned, increasing the effective area and improving the acquisition capacity.

For the connection conductor 17, for example, Ni, Pd, Ag, Cu, Sn, Ag--Pd alloy, or the like can be used.
The connection conductor 17 is preferably made of the same metal as the metal forming the first internal electrode layer 16a and the second internal electrode layer 16b. As a result, they are sintered at the same time as firing, and in particular, the connections between the second internal electrode layers 16b and the connection conductors 17 can be maintained, so that desired characteristics can be obtained.

The length in the length direction z of the connection conductor 17 is preferably the same as the length in the length direction z of the second internal electrode layer 16b, but may be arranged with a different length.
The thickness of the connection conductor 17 in the height direction x is preferably the same as the thickness of the second internal electrode layer 16b in the height direction x, but they may be arranged with different thicknesses.

(D) External Electrodes External electrodes 30 are arranged on the first end surface 12e side, the second end surface 12f side, and the first side surface 12c side and the second side surface 12d side of the laminate 12 . The external electrode 30 has a first external electrode 30a, a second external electrode 30b, a third external electrode 30c and a fourth external electrode 30d.

A first external electrode 30a is arranged on the first end surface 12e of the laminate 12 . The first external electrode 30a extends from the first end surface 12e of the laminate 12 to extend from one of each of the first main surface 12a, the second main surface 12b, the first side surface 12c and the second side surface 12d. placed so as to cover the Also, the first external electrode 30 a is electrically connected to the first internal electrode layer 16 a exposed at the first end surface 12 e of the laminate 12 . Note that the first external electrode 30a may be arranged only on the first end surface 12e of the laminate 12 .

A second external electrode 30b is arranged on the second end surface 12f of the laminate 12 . The second external electrode 30b extends from the second end surface 12f of the laminate 12 to extend from one of each of the first main surface 12a, the second main surface 12b, the first side surface 12c and the second side surface 12d. placed so as to cover the Also, the second external electrode 30b is electrically connected to the first internal electrode layer 16a exposed at the second end face 12f of the laminate 12. As shown in FIG. Note that the second external electrode 30b may be arranged only on the second end surface 12f of the laminate 12 .

A third external electrode 30c is arranged on the first side surface 12c of the laminate 12 . The third external electrode 30c is arranged to extend from the first side surface 12c and partially cover the first main surface 12a and the second main surface 12b. The third external electrode 30c is electrically connected via a second connection conductor 17b connected to the second internal electrode layer 16b exposed on the first side surface 12c of the laminate 12. As shown in FIG. Note that the third external electrode 30c may be arranged only on the first side surface 12c of the laminate 12 .

A fourth external electrode 30d is arranged on the second side surface 12d of the laminate 12 . The fourth external electrode 30d is arranged to extend from the second side surface 12d and partially cover the first main surface 12a and the second main surface 12b. The fourth external electrode 30d is electrically connected via a second connection conductor 17b connected to the second internal electrode layer 16b exposed on the second side surface 12d of the laminate 12 . Note that the fourth external electrode 30d may be arranged only on the second side surface 12d of the laminate 12 .

The external electrode 30 preferably includes a base electrode layer 32 arranged on the surface of the laminate 12 and a plated layer 34 arranged so as to cover the base electrode layer 32 .

The underlying electrode layer 32 has a first underlying electrode layer 32a, a second underlying electrode layer 32b, a third underlying electrode layer 32c, and a fourth underlying electrode layer 32d.

The first base electrode layer 32a is arranged on the surface of the first end surface 12e of the laminate 12 and extends from the first end surface 12e to form the first main surface 12a, the second main surface 12b, and the first main surface 12b. It is formed to cover part of each of the side surface 12c and the second side surface 12d.
The second base electrode layer 32b is arranged on the surface of the second end surface 12f of the laminate 12 and extends from the second end surface 12f to form the first principal surface 12a, the second principal surface 12b, and the first principal surface 12b. It is formed to cover part of each of the side surface 12c and the second side surface 12d.
The first base electrode layer 32a may be arranged only on the surface of the first end surface 12e of the laminate 12, and the second base electrode layer 32b may be arranged on the surface of the second end surface 12f of the laminate 12. It may be placed only on the surface.

The third base electrode layer 32c is arranged on the surface of the first side surface 12c of the laminate 12 and extends from the first side surface 12c to one of each of the first main surface 12a and the second main surface 12b. It is formed so as to cover the part.
The fourth base electrode layer 32d is arranged on the surface of the second side surface 12d of the laminate 12 and extends from the second side surface 12d to one of the first main surface 12a and the second main surface 12b. It is formed so as to cover the part.
The third base electrode layer 32c may be arranged only on the surface of the first side surface 12c of the laminate 12, and the fourth base electrode layer 32d may be arranged on the surface of the second side surface 12d of the laminate 12. It may be placed only on the surface.

The underlying electrode layer 32 includes at least one selected from a baking layer, a conductive resin layer, a thin film layer, and the like.
Hereinafter, each configuration in the case where the underlying electrode layer 32 is the baked layer, the conductive resin layer, and the thin film layer will be described.

(For baked layer)
The baking layer contains a glass component and a metal component. The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li and the like. The metal component of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag—Pd alloy, Au, and the like. The baking layer may be multiple layers. The baking layer is obtained by applying a conductive paste containing a glass component and a metal component to the laminate 12 and baking the paste. The baking layer may be obtained by simultaneously firing the laminated chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminated chip, and the laminated chip having the internal electrode layer 16 and the dielectric layer 14 is fired. After obtaining the laminated body 12, the laminated body 12 may be coated with a conductive paste and baked. In addition, when the laminated chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminated chip are simultaneously fired, the baking layer contains a dielectric material instead of the glass component. It is preferable to form a baked layer by baking the product.

The thickness in the direction connecting the first end surface 12e and the second end surface 12f at the center in the height direction x of the first base electrode layer 32a located on the first end surface 12e is about 3 μm or more and 70 μm or less. preferable.
The thickness in the direction connecting the first end face 12e and the second end face 12f at the center in the height direction x of the second base electrode layer 32b located on the second end face 12f is about 3 μm or more and 70 μm or less. is preferred.

The thickness in the direction connecting the first side surface 12c and the second side surface 12d at the center in the height direction x of the third base electrode layer 32c located on the first side surface 12c is about 3 μm or more and 70 μm or less. preferable.
The thickness in the direction connecting the first side surface 12c and the second side surface 12d at the center in the height direction x of the fourth base electrode layer 32d located on the second side surface 12d is about 3 μm or more and 70 μm or less. is preferred.

Extending from the first end surface 12e onto a portion of the first major surface 12a and a portion of the second major surface 12b and a portion of the first side surface 12c and a portion of the second side surface 12d When the base electrode layer 32 is provided, the length of the first base electrode layer 32a located on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d is The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the central portion in the direction z is preferably, for example, about 3 μm or more and 40 μm or less.
Also, extending from the second end surface 12f, a portion of the first main surface 12a and a portion of the second main surface 12b, a portion of the first side surface 12c and a portion of the second side surface 12d When the base electrode layer 32 is provided thereon, it is the second base electrode layer 32b located on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d. The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the central portion in the length direction z is preferably, for example, about 3 μm or more and 40 μm or less.

When the base electrode layer 32 is provided on part of the first main surface 12a and part of the second main surface 12b by extending from the first side surface 12c, the first main surface 12a and the second main surface 12b The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the central portion in the width direction y of the third base electrode layer 32c located on the main surface 12b of is, for example, 3 μm. It is preferable that the thickness is about 40 μm or more.
Further, when the base electrode layer 32 is provided on part of the first main surface 12a and part of the second main surface 12b by extending from the second side surface 12d, the first main surface 12a and the second main surface 12b The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the central portion in the width direction y of the fourth base electrode layer 32d located on the second main surface 12b is, for example, , 3 μm or more and 40 μm or less.

(In case of conductive resin layer)
The conductive resin layer may be multiple layers.
The conductive resin layer may be arranged on the baking layer so as to cover the baking layer, or may be arranged directly on the laminate 12 .
The conductive resin layer contains thermosetting resin and metal.
The conductive resin layer may completely cover the underlying electrode layer 32 or may partially cover the underlying electrode layer 32 .
Since the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plated film or a baked product of a conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical impact or impact due to thermal cycles, the conductive resin layer functions as a buffer layer to prevent the multilayer ceramic capacitor 10 from cracking. can be done.

Ag, Cu, Ni, Sn, Bi, or an alloy containing them can be used as the metal contained in the conductive resin layer.
Also, metal powder whose surface is coated with Ag can be used. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason why Ag conductive metal powder is used as the conductive metal is that Ag has the lowest specific resistance among metals and is therefore suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. be. Also, it is possible to make the metal of the base material inexpensive while maintaining the above characteristics of Ag.

Furthermore, as the metal contained in the conductive resin layer, Cu and Ni subjected to anti-oxidation treatment can also be used.
As the metal contained in the conductive resin layer, metal powder obtained by coating the surface of metal powder with Sn, Ni, or Cu can also be used. When using a metal powder coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.
The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.
The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, an electric path is formed inside the conductive resin layer by the conductive fillers coming into contact with each other.

The metal contained in the conductive resin layer may have a spherical shape or a flat shape, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, and the like.
The resin contained in the conductive resin layer is preferably contained at 25 vol % or more and 65 vol % or less with respect to the volume of the entire conductive resin.

Moreover, it is preferable that the conductive resin layer contains a curing agent together with the thermosetting resin. As a curing agent, when using an epoxy resin as a base resin, as a curing agent for the epoxy resin, various known compounds such as phenol, amine, acid anhydride, imidazole, active ester, and amide imide are used. can do.

The thickness of the conductive resin layer positioned at the center in the height direction x of the laminate 12 positioned on the first end face 12e and the second end face 12f is preferably, for example, about 10 μm to 150 μm.
Moreover, the thickness of the conductive resin layer positioned at the center in the height direction x of the laminate 12 positioned on the first side surface 12c and the second side surface 12d is preferably, for example, about 10 μm or more and 150 μm or less.

(For thin film layers)
When a thin film layer is provided as the base electrode layer 32, the thin film layer is a layer of 1 μm or less formed by a thin film forming method such as a sputtering method or a vapor deposition method and having metal particles deposited thereon.

The plating layer 34 includes a first plating layer 34a, a second plating layer 34b, a third plating layer 34c and a fourth plating layer 34d.
As the first plating layer 34a, the second plating layer 34b, the third plating layer 34c, and the fourth plating layer 34d, for example, Cu, Ni, Sn, Ag, Pd, Ag—Pd alloy, Au, etc. At least one selected.

The first plating layer 34a is arranged to cover the first base electrode layer 32a.
The second plating layer 34b is arranged to cover the second base electrode layer 32b.
The third plating layer 34c is arranged to cover the third base electrode layer 32c.
The fourth plating layer 34d is arranged to cover the fourth base electrode layer 32d.

The plating layer 34 may be formed of multiple layers. In this case, the plating layer 34 preferably has a two-layer structure of a lower plating layer formed on the underlying electrode layer 32 by Ni plating and an upper plating layer formed on the lower plating layer by Sn plating.
That is, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer.
The second plating layer 34b has a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.
The third plating layer 34c has a third lower plating layer and a second upper plating layer located on the surface of the third lower plating layer.
The fourth plating layer 34d has a fourth lower plating layer and a second upper plating layer located on the surface of the fourth lower plating layer.

The Ni-plated lower layer plating layer is used to prevent the base electrode layer 32 from being corroded by solder when mounting the multilayer ceramic capacitor 10 on a mounting board or the like, and the Sn-plated upper layer plating layer is used to prevent the multilayer ceramic capacitor 10 from being eroded. It is used to improve the wettability of solder when the capacitor 10 is mounted on a mounting board or the like so as to facilitate mounting.
The thickness of each plating layer is preferably 2.0 μm or more and 15.0 μm or less.

Alternatively, the external electrode 30 may be formed only by the plating layer without providing the base electrode layer 32 .
Hereinafter, although not shown, a structure in which a plated layer is provided without providing the base electrode layer 32 will be described.

Any or each of the first external electrode 30 a to the fourth external electrode 30 d may not be provided with the base electrode layer 32 and the plated layer may be directly formed on the surface of the laminate 12 . That is, the laminated ceramic capacitor 10 may have a structure including plated layers electrically connected to the first internal electrode layers 16a and the second internal electrode layers 16b. In such a case, the plating layer may be formed after disposing a catalyst on the surface of the laminate 12 as a pretreatment.

When the plated layer is formed directly on the laminate 12 without providing the base electrode layer 32, the thickness of the base electrode layer 32 is reduced to reduce the height, that is, to reduce the thickness of the laminate 12. That is, since the thickness can be converted to the thickness of the inner layer portion 18, the degree of freedom in designing the thin chip can be improved.

The plating layer preferably includes a lower layer plating electrode formed on the surface of the laminate 12 and an upper layer plating electrode formed on the surface of the lower layer plating electrode. Each of the lower layer plating electrode and the upper layer plating electrode preferably contains at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi or Zn, or an alloy containing such metal.
Further, the lower plated electrode is preferably formed using Ni, which has solder barrier properties, and the upper plated electrode is preferably formed using Sn or Au, which has good solder wettability.

Further, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, the lower plated electrodes are preferably formed using Cu, which has good bonding properties with Ni. . The upper layer plated electrode may be formed as required, and each of the first external electrode 30a to the fourth external electrode 30d may be composed of only the lower layer plated electrode. The plating layer may have the upper layer plating electrode as the outermost layer, or another plating electrode may be formed on the surface of the upper layer plating electrode.

Here, when the external electrode 30 is formed only by the plating layer without providing the base electrode layer 32, the thickness of each plating layer arranged without providing the base electrode layer 32 should be 1 μm or more and 15 μm or less. is preferred.

Furthermore, the plated layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99% by volume or more.

The dimension in the length direction z of the multilayer ceramic capacitor 10 including the multilayer body 12 and the first external electrodes 30a to 40d is defined as L dimension. The dimension in the height direction x of the multilayer ceramic capacitor 10 including the electrode 30d is defined as the dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the laminate 12 and the first external electrode 30a to the fourth external electrode 30d is defined as T. W dimension.
The dimensions of the multilayer ceramic capacitor 10 are not particularly limited, but the L dimension in the length direction z is 1.0 mm or more and 3.2 mm or less, the W dimension in the width direction y is 0.5 mm or more and 2.5 mm or less, and the height direction x The T dimension of is 0.3 mm or more and 2.5 mm or less. The dimensions of the laminated ceramic capacitor 10 can be measured with a microscope.

In the multilayer ceramic capacitor 10 shown in FIG. 1, the first external electrode layer 30a is arranged on the first end surface 12e of the laminate 12, and the second external electrode layer 30b is arranged on the second end surface 12f. In addition, the third external electrode 30c is arranged on the first side surface 12c, and the fourth external electrode 30d is arranged on the second side surface 12d. Since the internal electrode layers 16 can be arranged in a desired size in y, in the multilayer ceramic capacitor 10, the effective area, which is the area where the internal electrode layers 16 overlap in the height direction x, can be expanded. As a result, it is possible to increase the capacity by improving the effective volume.

2. Method for Manufacturing Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor according to the present invention will be described.

(A) Manufacturing process of strip-shaped blocks for inner layers First, dielectric sheets for dielectric layers and conductive paste for internal electrode layers are prepared. The conductive paste for dielectric sheets and internal electrode layers contains a binder and a solvent. Binders and solvents may be those known in the art.

A sheet having a composition as described below is prepared as a dielectric sheet for the dielectric layer.

The dielectric layer 14 located in the inner layer portion 18 is made of dielectric ceramic whose main component is BaTiO ₃ . Moreover, you may use what added the subcomponents, such as a Mn compound and a Ni compound, to these main components.

A dielectric ceramic containing BaTiO ₃ as a main component is used for the composition of the first side outer layer portion 22a and the second side outer layer portion 22b, which will be described later. Further, in addition to the above-described main components, subcomponents of Mg compounds are added to the first side outer layer portion 22a and the second side outer layer portion 22b. Here, the composition of the dielectric layer 14 located in the inner layer portion 18 and the first The compositions of the side outer layer portion 22a and the second side outer layer portion 22b are different. As with the inner layer portion 18, subcomponents such as Mn compounds and Ni compounds may be added to the first side outer layer portion and the second side outer layer portion.

A dielectric ceramic containing BaTiO ₃ as a main component is used for the composition of the first end surface side outer layer portion 24a and the second end surface side outer layer portion 24b. Moreover, you may use what added the subcomponents, such as a Mn compound and a Ni compound, to these main components.

By using a sheet having the composition as described above as the dielectric sheet for the dielectric layer, the composition of the dielectric layer 14 located in the inner layer portion 18 and the composition of the first side outer layer portion 22a and the second side layer portion 22a can be adjusted. The composition of the outer layer portion 22b is different, and the composition of the dielectric layer 14 located in the inner layer portion 18 and the composition of the first end surface side outer layer portion 24a and the composition of the second end surface side outer layer portion 24b are the same. can.

Subsequently, as shown in FIGS. 11 and 12, a conductive paste for internal electrode layers is printed in a predetermined pattern on dielectric sheet 40 for dielectric layers by, for example, screen printing or gravure printing. be. As a result, a dielectric sheet 44a having a first internal electrode layer pattern 42a formed thereon as shown in FIG. 11 is prepared, and a dielectric sheet 44a having a second internal electrode layer pattern 42b formed thereon as shown in FIG. A body sheet 44b is provided.

Next, as shown in FIG. 13, a predetermined number of dielectric sheets 40 for dielectric layers on which patterns of internal electrode layers are not printed are stacked to form a second main surface on the side of the second main surface. A portion to be the side outer layer portion 20b is formed. After that, a dielectric sheet 44a having a first internal electrode layer pattern formed thereon and a dielectric sheet having a second internal electrode layer pattern formed thereon are formed on the portion that will become the second main surface side outer layer portion 20b. 44b are alternately laminated to form a portion that will become the inner layer portion 18, and furthermore, on this portion that will become the inner layer portion 18, a dielectric layer for a dielectric layer on which the pattern of the internal electrode layer is not printed. By stacking a predetermined number of sheets 40, a portion to be the first main surface side outer layer portion 20a on the first main surface side is formed. Thereby, a laminated sheet is produced.

Subsequently, the laminated sheet is pressed in the lamination direction by a means such as a hydrostatic press to produce a laminated block 46 for the inner layer.

Next, as shown in FIG. 13, an inner layer laminate block 46 including a dielectric sheet 40 printed with an internal electrode layer pattern can serve as a side surface on which the internal electrode layer 16 portion of the laminate 12 is exposed. The inner layer strip-shaped block 48 is produced by cutting along the cutting line 100 in the length direction z into strips of the dimension in the width direction y of one laminate 12 so as to follow the surface.

(B) Manufacturing process of strip-shaped block for side outer layer Next, a method for manufacturing the first side outer layer and the second side outer layer will be described.

First, as shown in FIG. 14(a), a plurality of dielectric sheets 50 for manufacturing the side outer layer portions corresponding to the portions to be the first side outer layer portion and the second side outer layer portion are prepared. be prepared.

Next, as shown in FIG. 14(b), a conductive paste to be the connecting conductor 17 is applied to the prepared dielectric sheet 50 by, for example, screen printing or gravure printing so as to form a predetermined connecting conductor. A plurality of dielectric sheets 54 are prepared on which patterns 52 for connection conductors are printed and patterns for connection conductors are formed.

After that, a predetermined number of dielectric sheets 40 for dielectric layers on which patterns of internal electrode layers are not printed are laminated to form a second main surface side outer layer portion 20b on the side of the second main surface 12a. is formed. After that, a plurality of dielectric sheets 54 having patterns for connection conductors formed thereon are laminated to form portions to be the first side outer layer portion 22a and the second side outer layer portion 22b. A predetermined number of dielectric sheets 40 for dielectric layers on which patterns of internal electrode layers are not printed are laminated on the portions to be the first side outer layer portion 22a and the second side outer layer portion 22b. As a result, a portion to be the first main surface side outer layer portion 20a on the first main surface 12a side is formed. Thereby, as shown in FIG. 14(c), laminated sheets for the first side outer layer portion and the second side outer layer portion are produced.

Subsequently, as shown in FIG. 14(d), the laminated sheets for the first side outer layer portion and the second side outer layer portion are pressed in the lamination direction by a means such as hydrostatic pressing to obtain a second Laminated blocks 56 for one side outer layer and a second side outer layer are fabricated.

Finally, the prepared laminated block 56 for the first side outer layer and the second side outer layer is set to the thickness of the first side outer layer and the second side outer layer in the width direction y. Cut into strips along the cutting line 102 in the length direction z at equal intervals so as to have the dimensions, and as shown in FIG. A strip-shaped block 58 for is produced. At this time, the cutting is performed in a direction perpendicular to the longitudinal direction of the printed connection conductor. In other words, it is cut in a direction straddling a plurality of band-shaped connection conductors.

(C) Manufacturing Process of Laminated Chip One internal electrode layer exposed surface of the inner layer strip-shaped block 48 produced in the strip-shaped block manufacturing process is pasted together. At this time, one internal electrode layer exposed surface of the strip-shaped inner layer block 48 and the connection conductors of the strip-shaped block 58 for the first side outer layer and the second side outer layer are aligned. They are aligned and laminated for connection and then crimped.

Subsequently, one side surface of another strip-shaped block 58 for the first side outer layer portion and the second side outer layer portion manufactured in the manufacturing process of the strip-shaped block for the side outer layer, and the strip-shaped block for the inner layer 2, and the other internal electrode layer exposed surface of the inner layer strip-shaped block 48 manufactured in the manufacturing process of 1 is pasted together. At this time, one internal electrode layer exposed surface of the strip-shaped inner layer block 48 and the connection conductors of the strip-shaped block 58 for the first side outer layer and the second side outer layer are aligned. They are aligned and laminated for connection and then crimped.

Next, as shown in FIG. 15, an assembly 60 after completion of pasting of the strip-shaped blocks 58 for the side outer layer portion is cut in the width direction z at a predetermined pitch along the surface that can be the end surface of the laminate. By cutting along the line 104 , the laminated chip 62 is obtained by separating into individual chips.

The corners and ridges of the laminated chip 62 may be rounded by barrel polishing or the like.

Then, the laminated chip 62 cut out is fired to produce the laminated body 12 as shown in FIG. Although the firing temperature depends on the materials of the dielectric layers 14 and the internal electrode layers 16, it is preferably 900° C. or higher and 1400° C. or lower.

(D) Step of forming external electrodes (underlying electrode layer)
Subsequently, the third base electrode layer 32c of the third external electrode 30c is formed on the first side surface 12c of the laminated body 12 obtained by firing, and the third base electrode layer 32c is formed on the second side surface 12d of the laminated body 12 by firing. A fourth base electrode layer 32d of four external electrodes 30d is formed.
When a baked layer is formed as the base electrode layer 32 , a conductive paste containing a glass component and a metal component is applied and then baked to form a baked layer as the base electrode layer 32 . The temperature of the baking treatment at this time is preferably 700° C. or higher and 900° C. or lower.

Here, various methods can be used as a method for forming the baking layer. For example, a method of applying a conductive paste by extruding it through a slit can be used. In the case of this construction method, by increasing the extruding amount of the conductive paste, not only the first side surface 12c and the second side surface 12d but also a part of the first main surface 12a and the second main surface 12b are exposed. The base electrode layer 32 can be formed up to a part of the .
It can also be formed using a roller transfer method. In the case of the roller transfer method, the underlying electrode layer 32 is formed not only on the first side surface 12c and the second side surface 12d but also on part of the first main surface 12a and part of the second main surface 12b. At this time, by increasing the pressing pressure during roller transfer, it is possible to form the underlying electrode 32 on a portion of the first principal surface 12a and a portion of the second principal surface 12b.

Next, the first base electrode layer 32a of the first external electrode 30a is formed on the first end face 12e of the laminated body 12 obtained by firing, and the second base electrode layer 32a is formed on the second end face 12f of the laminated body 12. A second underlying electrode layer 32b of the second external electrode 30b is formed.
As in the case of forming the base electrode layers 32 of the third external electrode 30c and the fourth external electrode 30d, when forming the baked layer as the base electrode layer 32, a conductive paste containing a glass component and a metal component is used. is applied, and then a baking process is performed to form a baked layer as the base electrode layer 32 . The temperature of the baking treatment at this time is preferably 700° C. or higher and 900° C. or lower.

Also, as a method for forming the baked layer as the base electrode layer 32 of the first external electrode 30a and the second external electrode 30b, a dipping method can be used. As a result, not only the first end surface 12e and the second end surface 12f, but also a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and the second surface are formed. It can be formed so as to extend to a part of the side surface 12d.

Regarding the baking treatment, the third base electrode layer 32c of the third external electrode 30c, the fourth base electrode layer 32d of the fourth external electrode 30d, and the first base electrode layer of the first external electrode 30a 32a and the second base electrode layer 32b of the second external electrode 30b may be baked at the same time, or the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32c of the fourth external electrode 30d may be baked. The electrode layer 32d and the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b may be baked separately.

(Conductive resin layer)
When forming the base electrode layer 32 with a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer alone may be directly formed on the laminate 12 without forming the baking layer.

As a method for forming the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied on the baking layer or the laminate 12, and heat-treated at a temperature of 250° C. or more and 550° C. or less to remove the resin. is thermally cured to form a conductive resin layer. The atmosphere during the heat treatment at this time is preferably an N ₂ atmosphere. Moreover, in order to prevent scattering of the resin and oxidation of various metal components, it is preferable to suppress the oxygen concentration to 100 ppm or less.

As for the method of applying the conductive resin paste, for example, the method of applying the conductive resin paste by pushing it out from a slit or the roller transfer method can be used in the same manner as the method of forming the base electrode layer 32 with a baked layer. can be done.

(thin film layer)
Further, when the base electrode layer 32 is formed of a thin film layer, the base electrode layer can be formed by a thin film forming method such as sputtering or vapor deposition by performing masking or the like and where the external electrode 30 is desired to be formed. The base electrode layer formed of a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

(Plating electrode)
A plating electrode may be provided on the portion where the internal electrode layer 16 and the connection conductor 17 are exposed from the laminate 12 without providing the base electrode layer 32 . In that case, it can be formed by the following method.

The first end surface 12e and the second end surface 12f of the laminate 12 are plated to form lower layer plated electrodes on the exposed portions of the internal electrode layers 16. As shown in FIG. Similarly, the first side surface 12 c and the second side surface 12 d of the laminate 12 are plated to form lower-layer plated electrodes on the exposed portions of the connection conductors 17 . Either electroplating or electroless plating can be used for plating, but electroless plating requires pretreatment with a catalyst or the like in order to increase the rate of plating deposition, which complicates the process. There is a disadvantage. Therefore, it is usually preferable to adopt electrolytic plating. As the plating method, barrel plating is preferably used. Also, if necessary, an upper layer plating electrode may be formed in the same manner on the surface of the lower layer plating electrode.

Subsequently, a plating layer 34 is formed on the surface of the base electrode layer 32, the surface of the conductive resin layer or the surface of the lower layer plating electrode, and the surface of the upper layer plating electrode, if necessary.
More specifically, in the present embodiment, a Ni plated layer is formed as a lower plated layer and a Sn plated layer is formed as an upper plated layer on the underlying electrode layer 32 which is a baked layer. The Ni plating layer and the Sn plating layer are sequentially formed by, for example, barrel plating. Either electroplating or electroless plating may be employed for the plating treatment. However, electroless plating requires pretreatment with a catalyst or the like in order to improve the deposition rate of the plating, which has the disadvantage of complicating the process. Therefore, it is usually preferable to adopt electrolytic plating.

As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

As described above, the embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.
That is, without departing from the scope of the technical idea and purpose of the present invention, various modifications can be made to the embodiments described above in terms of mechanism, shape, material, quantity, position, arrangement, etc. and they are included in the present invention.

REFERENCE SIGNS LIST 10 multilayer ceramic capacitor 12 laminate 12a first main surface 12b second main surface 12c first side surface 12d second side surface 12e first end surface 12f second end surface 14 dielectric layer 16 internal electrode layer 16a first first surface internal electrode layer 16b second internal electrode layer 17 connection conductor 17a first connection conductor 17b second connection conductor 18 inner layer portion 20a first main surface side outer layer portion 20b second main surface side outer layer portion 22a first side surface side outer layer portion 22b second side surface side outer layer portion 24a first end surface side outer layer portion 24b second end surface side outer layer portion 30 external electrode 30a first external electrode 30b second external electrode 30c third external electrode 30d fourth external electrode 32 ground electrode layer 32a first ground electrode layer 32b second ground electrode layer 32c third ground electrode layer 32d fourth ground electrode layer 34 plating layer 34a first plating layer 34b second second plated layer 34c third plated layer 34d fourth plated layer 40 dielectric sheet for dielectric layer 42a pattern for first internal electrode layer 42b pattern for second internal electrode layer 44a first internal electrode Dielectric sheet formed with layer pattern 44b Dielectric sheet formed with pattern for second internal electrode layer 46 Laminated block for inner layer 48 Strip-shaped block for inner layer 50 Dielectric sheet for side outer layer 52 Pattern for connection conductor 54 Dielectric sheet on which pattern for connection conductor is formed 56 Laminated block for side outer layer 58 Strip-shaped block for side outer layer 60 Assembly 62 Laminated chip x height direction y width direction z length direction

Claims (5)

having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface facing each other in the lamination direction and perpendicular to the lamination direction A laminate having first and second end faces facing each other in the length direction, and first side faces and second side faces facing each other in the width direction orthogonal to the lamination direction and the length direction,
a first external electrode disposed on the first end surface;
a second external electrode disposed on the second end surface;
a third external electrode disposed on the first side;
a fourth external electrode disposed on the second side;
A multilayer ceramic capacitor having
The laminate is
an internal layer portion where the plurality of internal electrode layers face each other;
Formed from the plurality of dielectric layers located on the first side surface and between the first side surface, the outermost surface of the inner layer portion on the first side surface, and an extension line of the outermost surface a first side outer layer portion to be
Formed from the plurality of dielectric layers located on the second side surface and between the second side surface, the outermost surface of the inner layer portion on the second side surface side, and an extension line of the outermost surface a second side outer layer portion to be
Formed from the plurality of dielectric layers positioned on the first end face side and positioned between the first end face, the outermost surface of the inner layer portion on the first end face side, and an extension line of the outermost surface a first end face side outer layer portion to be
Formed from the plurality of dielectric layers positioned on the second end face side and positioned between the second end face, the outermost surface of the inner layer portion on the second end face side, and an extension line of the outermost surface a second end face side outer layer portion to be
has
The plurality of internal electrode layers are arranged on the plurality of dielectric layers, and a first internal electrode layer is drawn out to the first end surface and the second end surface;
any of the first main surface and the second main surface, the first side surface, the second side surface, the first end surface, and the second end surface disposed on the plurality of dielectric layers; and a second internal electrode layer that is not drawn out to
A connection conductor connected to the second internal electrode layer is disposed on the first side outer layer portion and the second side outer layer portion, and the second internal electrode layer is connected via the connection conductor. A multilayer ceramic capacitor connected to the third external electrode and the fourth external electrode. The composition of the dielectric layer located in the inner layer portion is different from the composition of the first side outer layer portion and the second side outer layer portion,
2. The multilayer ceramic capacitor according to claim 1, wherein said dielectric layer located in said inner layer portion has the same composition as said first end face side outer layer portion and said second end face side outer layer portion. 3. The multilayer ceramic capacitor according to claim 1, wherein said connecting conductor is made of the same metal as the metal forming said first internal electrode layer and said second internal electrode layer. 4. The multilayer ceramic capacitor according to claim 1, wherein said first side outer layer portion and said second side outer layer portion each have a thickness of 5 [mu]m or more and 30 [mu]m or less. 5. The multilayer ceramic capacitor according to claim 1, wherein said first end surface side outer layer portion and said second end surface side outer layer portion each have a thickness of 10 [mu]m or more and 70 [mu]m or less.

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