JP2022159793A - Semiconductor test device and semiconductor device manufacturing method - Google Patents

Abstract

To provide a technique capable of suppressing variations in on-resistance within the surface of a semiconductor substrate.SOLUTION: A semiconductor test device 100 includes a plurality of rollers 1 which are arranged in the Y-axis direction at intervals and rotate so as to slide a semiconductor wafer 50 as an object to be measured in the Y-axis direction with the semiconductor wafer 50 placed thereon, a lower contact jig 2 arranged between the plurality of rollers 1 and electrically connected to the semiconductor wafer 50 by contacting a partial region on the back surface of the semiconductor wafer 50, and an upper contact jig 3 arranged on the plurality of rollers 1 and having a probe 12 electrically connected to the semiconductor wafer 50 by coming into contact with the surface of the semiconductor wafer 50.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a semiconductor test apparatus and a method of manufacturing a semiconductor device.

Conventionally, as a method for measuring the electrical characteristics of a plurality of semiconductor elements formed on a semiconductor substrate, the semiconductor substrate is placed on the upper surface of a stage, and the semiconductor substrate is attached to the stage using a vacuum chuck. There is a method of pressing a probe against the surface of a semiconductor element formed on a semiconductor substrate (see, for example, Patent Document 1).

JP 2016-157804 A

In the conventional technique, the stage is in contact with the entire back surface of the semiconductor substrate in order to cause the entire back surface of the semiconductor substrate to adhere to the stage while the semiconductor substrate is placed on the upper surface of the stage. Wiring for supplying current to the semiconductor element is connected to the side of the stage. The element has a longer path for current flowing on the upper surface of the stage than the semiconductor element located at a short distance. Since the in-plane on-resistance of the semiconductor substrate is proportional to the length of the path of the current flowing on the upper surface of the stage, there is a problem that the in-plane on-resistance of the semiconductor substrate varies depending on the position of the semiconductor element.

Accordingly, an object of the present disclosure is to provide a technique capable of suppressing variations in on-resistance within the surface of a semiconductor substrate.

A semiconductor test apparatus according to the present disclosure is arranged in a first direction with an interval therebetween, and rotates so as to slide the object to be measured in the first direction with the object to be measured placed thereon. a plurality of rollers, and a lower contact jig disposed between the plurality of rollers and electrically connected to the object to be measured by contacting a partial region on the back surface of the object to be measured; An upper contact jig is provided above the plurality of rollers and has probes electrically connected to the object to be measured by contacting the surface of the object to be measured.

According to the present disclosure, the area of the lower contact jig that contacts the back surface of the object to be measured is smaller than the area of the conventional stage. Shorten. As a result, it is possible to suppress variations in on-resistance within the plane of the semiconductor substrate.

1 is a perspective view schematically showing the configuration of a semiconductor test device according to Embodiment 1; FIG. FIG. 11 is a perspective view schematically showing the configuration of a semiconductor test device according to a modification of the first embodiment; 4 is a flow chart showing procedures of a method for measuring a semiconductor element included in a method for manufacturing a semiconductor device using the semiconductor testing apparatus according to the first embodiment; FIG. 4 is an explanatory diagram for explaining operations of an upper contact jig and a lower contact jig provided in the semiconductor test device according to the first embodiment; FIG. 11 is a perspective view schematically showing the configuration of a semiconductor test device according to Embodiment 2; FIG. 11 is a perspective view schematically showing the configuration of a semiconductor test device according to a modification of the second embodiment; FIG. 11 is an explanatory diagram for explaining operations of an upper contact jig and a lower contact jig provided in the semiconductor test device according to the second embodiment; FIG. 10 is a diagram schematically showing the configuration of an upper contact jig included in the semiconductor test device according to the third embodiment;

<Embodiment 1>
<Overall composition>
Embodiments will be described below with reference to the drawings. FIG. 1 is a perspective view schematically showing the configuration of a semiconductor test device 100 according to an embodiment.

In FIG. 1, the X, Y and Z directions are orthogonal to each other. The X, Y and Z directions shown in the following figures are also orthogonal to each other. Hereinafter, the direction including the X direction and the direction opposite to the X direction (−X direction) is also referred to as the “X-axis direction”. Also, hereinafter, the direction including the Y direction and the direction opposite to the Y direction (−Y direction) is also referred to as the “Y-axis direction”. Also, hereinafter, the direction including the Z direction and the direction opposite to the Z direction (−Z direction) is also referred to as the “Z-axis direction”.

As shown in FIG. 1, a semiconductor testing apparatus 100 is an apparatus for measuring semiconductor chips performed in a manufacturing process of a semiconductor device. and a tool 3.

The plurality of rollers 1 are arranged in the Y-axis direction (first direction) at intervals, and slide the semiconductor wafer 50 as an object to be measured in the Y-axis direction with the semiconductor wafer 50 placed thereon. Rotate. The plurality of rollers 1 are formed of a member having conductivity so as to extend in the X-axis direction, and both ends of the plurality of rollers 1 are supported by, for example, two supports (not shown) extending in the Y-axis direction. It is rotatably supported. Since the plurality of rollers 1 are made of an electrically conductive member, it is possible to confirm which roller 1 the semiconductor wafer 50 is on by an electrical continuity check.

The lower contact jig 2 is arranged between the plurality of rollers 1 and formed of a conductive member so as to extend in the X-axis direction. Wiring (not shown) for supplying a current from a measuring section (not shown) of the semiconductor test apparatus 100 to the semiconductor wafer 50 is connected to the side of the lower contact jig 2 . is in contact with a part of the back surface of the semiconductor wafer 50, the semiconductor wafer 50 and the lower contact jig 2 are electrically connected.

Specifically, the length of the lower contact jig 2 in the X-axis direction is longer than the length of the plurality of rollers 1 in the X-axis direction, that is, longer than the diameter of the semiconductor wafer 50 . Therefore, the upper surface of the lower contact jig 2 can simultaneously contact the back surface of the semiconductor wafer 50 from one end portion to the other end portion in the X-axis direction (second direction). Also, the width of the lower contact jig 2 in the Y-axis direction is larger than the width of one semiconductor chip (not shown) among the plurality of semiconductor chips formed on the semiconductor wafer 50 . As a result, the lower contact jig 2 can simultaneously contact the area corresponding to one row of semiconductor chips in the X-axis direction on the back surface of the semiconductor wafer 50 . Here, the semiconductor wafer corresponds to the semiconductor substrate, and the semiconductor chip corresponds to the semiconductor element.

As described above, the area of the lower contact jig 2 that contacts the back surface of the semiconductor wafer 50 is smaller than the area of the conventional stage. Shorten.

Also, the lower contact jig 2 is connected to a first moving mechanism (not shown). The first moving mechanism has a first height position where the lower contact jig 2 contacts the back surface of the semiconductor wafer 50 and a second height position located below the first height position (-Z direction). The lower contact jig 2 is moved between the upper and lower positions.

The upper contact jig 3 is arranged above the plurality of rollers 1 (in the Z direction) and has a probe 12 made of a member having conductivity. The probes 12 and the semiconductor wafer 50 are electrically connected by contacting the surface of the semiconductor wafer 50 with the probes 12 .

The upper contact jig 3 is connected to a second moving mechanism (not shown). The second moving mechanism has a third height position where the upper contact jig 3 contacts the surface of the semiconductor wafer 50 and a fourth height position above the third height position (in the Z direction). position, and move the upper contact jig 3 in the X-axis direction.

The semiconductor test apparatus 100 also includes a camera (not shown) for aligning the semiconductor wafer 50 . After the semiconductor wafer 50 is conveyed on the plurality of rollers 1, the camera recognizes the pattern formed on the semiconductor wafer 50, thereby confirming the position of the semiconductor wafer 50 in the X-axis direction and the Y-axis direction.

A plurality of sets of the lower contact jig 2 and the upper contact jig 3 may be provided. FIG. 2 is a perspective view schematically showing the configuration of a semiconductor test apparatus 100A according to Modification 1 of the embodiment.

As shown in FIG. 2, the semiconductor test apparatus 100A differs from the semiconductor test apparatus 100 in that two sets of the lower contact jig 2 and the upper contact jig 3 are provided. Three or more sets of the lower contact jig 2 and the upper contact jig 3 may be provided. This enables the semiconductor test apparatus 100A to measure a plurality of semiconductor wafers 50 simultaneously.

<Measurement procedure>
Next, a procedure of a method of measuring a semiconductor chip included in a method of manufacturing a semiconductor device will be described with reference to FIGS. 3 and 4. FIG. FIG. 3 is a flow chart showing a procedure of a method of measuring a semiconductor chip included in a method of manufacturing a semiconductor device using the semiconductor test apparatus 100. As shown in FIG. 4A to 4C are explanatory diagrams for explaining the operations of the upper contact jig 3 and the lower contact jig 2 provided in the semiconductor test apparatus 100. FIG.

The method for measuring a semiconductor chip when using the semiconductor test apparatus 100A is the same procedure as when using the semiconductor test apparatus 100, so here, the measurement of the semiconductor chip when using the semiconductor test apparatus 100 is performed. I will explain the method.

As shown in FIG. 3, after a plurality of semiconductor chips are formed on the surface of the semiconductor wafer 50 (step S1), as shown in FIG. step S2).

Next, it is recognized that the probes 12 are at the fourth height position where they do not contact the surface of the semiconductor wafer 50 (step S3). Here, in step S3, a camera for aligning the semiconductor wafer 50 is used to recognize the height position of the probe 12. FIG.

Next, by recognizing the pattern formed on the semiconductor wafer 50 by the camera, the position of the semiconductor wafer 50 in the X-axis direction and the Y-axis direction is confirmed, that is, the alignment of the semiconductor wafer 50 is performed (step S4). ).

Next, the semiconductor wafer 50 is slid in the Y-axis direction by rotating the plurality of rollers 1 so that the semiconductor chip to be measured is positioned on the lower contact jig 2 . When the semiconductor chip to be measured is positioned on the lower contact jig 2, the rollers 1 stop rotating. Here, a semiconductor chip positioned at one end in the Y-axis direction and one end in the X-axis direction of the semiconductor wafer 50 is to be measured.

Next, as shown in FIG. 4B, after confirming that the lower contact jig 2 has moved up to the first height position (moved in the Z direction) and made contact with the back surface of the semiconductor wafer 50, The upper contact jig 3 descends (moves in the -Z direction) so that the probes 12 move to the third height position where they come into contact with the surface of the semiconductor chip (step S5). Next, measurement of the electrical characteristics of the semiconductor chip is started (step S6).

When the measurement of the electrical characteristics of the semiconductor chip is finished, as shown in FIG. It moves to the position where the adjacent semiconductor chip in the X-axis direction is formed with respect to the chip. Then, the upper contact jig 3 is lowered (moved in the -Z direction) so that the probes 12 move to the third height position (step S5), and measurement of the electrical characteristics of the semiconductor chip is started (step S6).

When the measurement of the electrical characteristics of the semiconductor chip located at the other end of the semiconductor wafer 50 in the X-axis direction is completed, the plurality of rollers 1 are rotated to move the semiconductor wafer 50 to the adjacent row in the Y-axis direction and the X-axis direction. A semiconductor chip located at one end of the direction is the object of measurement, and the electrical characteristics of all the semiconductor chips formed on the semiconductor wafer 50 are measured by repeating the above procedure.

When the electrical characteristics of all semiconductor chips have been measured, the upper contact jig 3 rises (moves in the Z direction) so that the probes 12 move to the fourth height position, and the lower contact jig 2 It descends (moves in the -Z direction) to the second height position.

<effect>
As described above, in the first embodiment, the semiconductor test apparatuses 100 and 100A are arranged in the Y-axis direction with a space therebetween, and the semiconductor wafer 50 as the object to be measured is mounted thereon. and a plurality of rollers 1 rotating so as to slide in the Y-axis direction; and probes 12 arranged above (in the Z direction) the plurality of rollers 1 and electrically connected to the semiconductor wafer 50 by coming into contact with the surface of the semiconductor wafer 50. and an upper contact jig 3.

Therefore, since the area of the lower contact jig 2 in contact with the back surface of the semiconductor wafer 50 is smaller than the area of the conventional stage, the path of current flowing through the upper surface of the lower contact jig 2 is shorter than in the conventional stage. . As a result, variations in on-resistance within the surface of the semiconductor wafer 50 can be suppressed.

Further, the partial region on the back surface of the semiconductor wafer 50 is a region extending from one end to the other end in the X-axis direction that intersects the Y-axis direction on the back surface of the semiconductor wafer 50 .

Therefore, since the lower contact jig 2 is in contact with a region extending from one end to the other end in the X-axis direction that intersects the Y-axis direction on the back surface of the semiconductor wafer 50, when the probes 12 come into contact with the semiconductor chip, the semiconductor chip is A pressing force applied to the wafer 50 can be received in the above region. As a result, it is possible to suppress the occurrence of cracks in the semiconductor wafer 50 when the probes 12 come into contact with the semiconductor chip.

In addition, since the semiconductor test apparatus 100A includes a plurality of sets of the lower contact jig 2 and the upper contact jig 3, it is possible to simultaneously measure a plurality of semiconductor wafers 50, thereby reducing the takt time required for measuring the semiconductor chips. As a result, the tact time required for manufacturing semiconductor devices can be improved.

<Embodiment 2>
<Overall composition>
Next, a semiconductor test device 100B according to Embodiment 2 will be described. FIG. 5 is a perspective view schematically showing the configuration of a semiconductor test device 100B according to the second embodiment. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

As shown in FIG. 5, in the second embodiment, a lower contact jig 2A is provided instead of the lower contact jig 2 in the configuration of the first embodiment.

The lower contact jig 2A is arranged between the plurality of rollers 1 and is composed of a cubic body portion 2a formed of a conductive member and a conductive member extending in the X-axis direction. and a rail 2b.

The body portion 2a is inserted through the rail 2b so as to be movable in the X-axis direction along the rail 2b. The length of the rail 2 b in the X-axis direction is longer than the length of the plurality of rollers 1 in the X-axis direction, that is, longer than the diameter of the semiconductor wafer 50 . Therefore, the body portion 2a can move at least from one end portion to the other end portion of the back surface of the semiconductor wafer 50 in the X-axis direction.

Wiring (not shown) for supplying current from a measuring unit (not shown) of the semiconductor test apparatus 100B to the semiconductor wafer 50 is connected to the side of the rail 2b. The semiconductor wafer 50 and the lower contact jig 2A are electrically connected by contacting the top surface with a part of the back surface of the semiconductor wafer 50 .

The size of the upper surface of the body portion 2 a is slightly larger than the size of one semiconductor chip (not shown) among the plurality of semiconductor chips formed on the semiconductor wafer 50 . Therefore, the upper surface of the body portion 2a can come into contact with a region corresponding to one semiconductor chip on the back surface of the semiconductor wafer 50. As shown in FIG. Thereby, even when the thickness of the semiconductor wafer 50 is not uniform, the lower contact jig 2A and the semiconductor wafer 50 can be brought into contact with each other.

Further, the main body portion 2a and the rails 2b are connected to a first moving mechanism (not shown). The first moving mechanism moves the body portion 2a in the X-axis direction along the rails 2b. Further, the first moving mechanism has a first height position where the body portion 2a contacts the back surface of the semiconductor wafer 50, and a second height position located below the first height position (-Z direction). The rail 2b is moved together with the body portion 2a between the positions.

A plurality of sets of the lower contact jig 2A and the upper contact jig 3 may be provided. FIG. 6 is a perspective view schematically showing the configuration of a semiconductor test device 100C according to a modification of the second embodiment.

As shown in FIG. 6, the semiconductor test apparatus 100C differs from the semiconductor test apparatus 100B in that two sets of lower contact jigs 2A and upper contact jigs 3 are provided. Three or more sets of the lower contact jig 2A and the upper contact jig 3 may be provided. This enables the semiconductor test apparatus 100C to simultaneously measure a plurality of semiconductor wafers 50. FIG.

<Measurement procedure>
Next, with reference to FIGS. 3 and 7, the procedure of the method of measuring a semiconductor chip included in the method of manufacturing a semiconductor device will be described only in points different from the case of the first embodiment. 7A to 7C are explanatory diagrams for explaining operations of the upper contact jig 3 and the lower contact jig 2A provided in the semiconductor test apparatus 100B according to the second embodiment.

The semiconductor chip measurement method using the semiconductor test apparatus 100C is the same procedure as the semiconductor test apparatus 100B, so here, the semiconductor chip measurement using the semiconductor test apparatus 100B I will explain the method.

After the processing from step S1 to step S4 shown in FIG. 3 is performed, as shown in FIG. 7A, the plurality of rollers 1 are rotated so that the semiconductor chip to be measured is positioned on the main body 2a. By doing so, the semiconductor wafer 50 is slid in the Y-axis direction. When the semiconductor chip to be measured is positioned on the body portion 2a, the rollers 1 stop rotating. Here, since the body portion 2a is positioned at one end in the X-axis direction, the semiconductor chip positioned at one end in the Y-axis direction and one end in the X-axis direction of the semiconductor wafer 50 is the object of measurement.

Next, as shown in FIG. 7B, the rail 2b is lifted (moved in the Z direction) together with the main body 2a, and after confirming that the upper surface of the main body 2a is in contact with the back surface of the semiconductor wafer 50, The upper contact jig is lowered (moved in the -Z direction) so that the probes 12 move to the third height position where they come into contact with the surface of the semiconductor chip (step S5). Next, measurement of the electrical characteristics of the semiconductor chip is started (step S6).

When the measurement of the electrical characteristics of the semiconductor chip is completed, as shown in FIG. It moves to the position where the adjacent semiconductor chip in the X-axis direction is formed with respect to the chip. On the other hand, the rail 2b is lowered to the second height position (moved in the -Z direction) together with the main body 2a, and the main body 2a forms a semiconductor chip adjacent in the X-axis direction to the semiconductor chip for which measurement has been completed. position. Then, the upper contact jig 3 is lowered (moved in the -Z direction) so that the probes 12 move to the third height position (step S5), and measurement of the electrical characteristics of the semiconductor chip is started (step S6).

When the measurement of the electrical characteristics of the semiconductor chip located at the other end of the semiconductor wafer 50 in the X-axis direction is completed, the plurality of rollers 1 are rotated to move the semiconductor wafer 50 to the adjacent row in the Y-axis direction and the X-axis direction. A semiconductor chip located at one end of the direction is the object of measurement, and the electrical characteristics of all the semiconductor chips formed on the semiconductor wafer 50 are measured by repeating the above procedure.

When the electrical characteristics of all semiconductor chips have been measured, the upper contact jig 3 is raised (in the Z direction) so that the probes 12 move to the fourth height position, as shown in FIG. 7(c). ), and the rail 2b descends (moves in the -Z direction) to the second height position together with the main body 2a.

<effect>
As described above, in the semiconductor test apparatuses 100B and 100C according to the second embodiment, the object to be measured is a semiconductor wafer on which a plurality of semiconductor chips are formed, and the partial region on the back surface of the object to be measured is It is a region corresponding to one semiconductor chip on the back surface of the semiconductor wafer.

Therefore, even if the thickness of the semiconductor wafer 50 is not uniform, the lower contact jig 2A and the semiconductor wafer 50 can be brought into contact with each other.

The semiconductor test apparatuses 100B and 100C also have a first height position where the lower contact jig 2A contacts the back surface of the semiconductor wafer 50, and a second height position located below the first height position (-Z direction). 2 and a moving mechanism for moving the main body portion 2a of the lower contact jig 2A in the X-axis direction intersecting the Y-axis direction.

Therefore, the regions corresponding to the semiconductor chips to be measured on the back surface of the semiconductor wafer 50 can be brought into contact with the body portion 2a of the lower contact jig 2A one by one. As a result, variations in on-resistance within the surface of the semiconductor wafer 50 can be suppressed.

In addition, since the semiconductor test apparatus 100C includes a plurality of sets of the lower contact jig 2A and the upper contact jig 3, it is possible to simultaneously measure a plurality of semiconductor wafers 50, thereby reducing the takt time required for measuring the semiconductor chips. As a result, the tact time required for manufacturing semiconductor devices can be improved.

<Embodiment 3>
<Overall composition>
Next, a semiconductor test apparatus according to Embodiment 3 will be described. FIG. 8 is a diagram schematically showing the configuration of an upper contact jig 3A provided in the semiconductor test device according to the third embodiment. In addition, in Embodiment 3, the same components as those described in Embodiments 1 and 2 are denoted by the same reference numerals, and descriptions thereof are omitted.

As shown in FIG. 8, in the third embodiment, an upper contact jig 3A is provided instead of the upper contact jig 3 in the configurations of the first and second embodiments. For example, in the case where the semiconductor device is a power device, there is concern about discharge because measurement is performed by applying 0 V to the front surface of the semiconductor chip and a high voltage (several kV) to the rear surface. If the distance from the electrode end on the surface of the semiconductor chip to the center of the dicing line of the semiconductor wafer 50 can be sufficiently long, there is no need to pressurize the periphery of the probe 12 to suppress discharge. A semiconductor chip made of a silicon carbide semiconductor or the like requires pressurization because the distance from the electrode end to the center of the dicing line of the semiconductor wafer 50 is short. In the third embodiment, pressure is applied around the probe 12 of the upper contact jig 3A for the purpose of suppressing discharge.

The upper contact jig 3A includes probes 12, a probe card 10, an annular pressure wall 11, and an air tube 13. As shown in FIG.

The probe card 10 is arranged above the semiconductor wafer 50 (in the Z direction). The probe card 10 is connected to a second moving mechanism (not shown). The probe card 10 is movable in the X-axis direction by a second moving mechanism.

The pressure wall 11 is provided so as to extend from the lower surface of the probe card 10 downward (-Z direction) toward the roller 1 (see FIG. 1). One end of the probe 12 is attached to the lower surface of the probe card 10, and the other end (tip on the roller 1 side) of the probe 12 protrudes from the pressure wall 11 through a hole (not shown) formed in the pressure wall 11. ing.

One end of the air tube 13 is connected to the upper surface of the probe card 10, and the other end of the air tube 13 is connected to an air supply source (not shown). The air tube 13 pressurizes the space by supplying air to the space surrounded by the pressurizing wall 11 . The upper contact jig 3A is provided with an electropneumatic regulator (not shown). The flow rate of air supplied to the space surrounded by the pressurizing wall 11 is controlled by adjusting the opening and closing of the valve of the electro-pneumatic regulator so that the set pressure is achieved by the electro-pneumatic regulator.

The area of the inner circumference of the air tube 13 connected to the probe card 10 is defined as the inlet area, and the inner circumference of the pressure wall 11 is measured from the tip of the probe 12 on the roller 1 side to the end of the pressure wall 11 on the roller 1 side. The inlet area and the outlet area are designed so that the outlet area is smaller than the inlet area when the outlet area is the value obtained by multiplying the length of .

The reason for this is that air stays in the space surrounded by the pressurizing wall 11, so that the space surrounded by the pressurizing wall 11, that is, the periphery of the probe 12 is sufficiently pressurized, but the exit area is If the area is larger than the inlet area, air does not stay in the space surrounded by the pressurizing wall 11, so the periphery of the probe 12 is not sufficiently pressurized. On the other hand, when the outlet area is smaller than the inlet area, the air stays in the space surrounded by the pressurizing wall 11, so the periphery of the probe 12 is sufficiently pressurized.

<Measurement procedure>
Next, with reference to FIG. 3, only points different from the first embodiment will be described with respect to the procedure of the semiconductor chip measurement method included in the semiconductor device manufacturing method.

After the processing up to recognition of the height position of the probe 12 in steps S1 to S3 shown in FIG. The height position and the height position of the end of the pressure wall 11 on the side of the roller 1 are detected, and the exit area is calculated by the control unit provided in the semiconductor test device, and the exit area is smaller than the pre-calculated entrance area. It is determined whether or not After the processing from step S4 to step S5 is performed, in step S6, if the outlet area is smaller than the inlet area, air is supplied from the air tube 13 to the space surrounded by the pressurizing wall 11. The space is pressurized to the set pressure. Then, the measurement of the electrical characteristics of the semiconductor chip is started.

On the other hand, when the outlet area is larger than the inlet area, the measurement of the electrical characteristics of the semiconductor chip is started without supplying air.

<effect>
As described above, in the semiconductor test apparatus according to the third embodiment, the upper contact jig 3A includes the probe card 10 having the probes 12 attached to the lower surface, and the probe card 10 extending downward (-Z direction) from the lower surface of the probe card 10. Air is supplied to an annular pressurizing wall 11 provided so as to be present and projecting the tip of the probe 12 downward (−Z direction), and a space connected to the upper surface of the probe card 10 and surrounded by the pressurizing wall 11. and an air tube 13 that pressurizes the space by supplying the probe 12 to the inner periphery of the pressurizing wall 11. Assuming that the outlet area is the value obtained by multiplying the length from the lower (-Z direction) tip to the lower (-Z direction) end of the pressure wall 11, the pressure wall 11 The space enclosed by is pressurized.

Therefore, discharge can be suppressed when the applied voltage during measurement is high, so high voltage application measurement of a semiconductor chip made of a silicon carbide semiconductor or the like with a short termination region becomes possible.

In addition, it is possible to freely combine each embodiment, and to modify or omit each embodiment as appropriate.

1 roller, 2, 2A lower contact jig, 3, 3A upper contact jig, 10 probe card, 11 pressure wall, 12 probe, 13 air tube, 50 semiconductor wafer, 100, 100A, 100B, 100C semiconductor test device.

Claims (8)

a plurality of rollers arranged in a first direction at intervals and rotating so as to slide the object to be measured in the first direction with the object to be measured placed thereon;
a lower contact jig disposed between the plurality of rollers and electrically connected to the object to be measured by contacting a part of the back surface of the object to be measured;
an upper contact jig disposed above the plurality of rollers and having a probe electrically connected to the object to be measured by coming into contact with the surface of the object to be measured;
Semiconductor test equipment with 2. The partial area on the back surface of the object to be measured is an area extending from one end to the other end in a second direction intersecting the first direction on the back surface of the object to be measured. The semiconductor test device according to . The object to be measured is a semiconductor substrate on which a plurality of semiconductor elements are formed,
2. The semiconductor test apparatus according to claim 1, wherein said partial region on the back surface of said device under test is a region corresponding to one said semiconductor element on the back surface of said semiconductor substrate. The lower contact jig is positioned between a first height position where the lower contact jig contacts the back surface of the semiconductor substrate and a second height position positioned below the first height position. 4. The semiconductor test apparatus according to claim 3, further comprising a moving mechanism for moving the lower contact jig in a second direction intersecting with the first direction. 5. The semiconductor testing apparatus according to claim 1, comprising a plurality of sets of said lower contact jig and said upper contact jig. The upper contact jig includes a probe card having the probes attached to its lower surface, and an annular shape extending from the lower surface of the probe card to the roller side and projecting the tip of the probe on the roller side. a pressurizing wall, and an air tube connected to the top surface of the probe card and supplying air to a space surrounded by the pressurizing wall to pressurize the space;
The area of the inner periphery of the air tube connected to the probe card is defined as the inlet area, and the inner periphery of the pressure wall is measured from the tip of the probe on the roller side to the end of the pressure wall on the roller side. 6. The space surrounded by the pressurizing wall is pressurized when the outlet area is smaller than the inlet area when the outlet area is multiplied by the length of 1. A semiconductor test device according to claim 1. A method for manufacturing a semiconductor device using the semiconductor test apparatus according to claim 3,
(a) placing the semiconductor substrate on a plurality of the rollers;
(b) recognizing the height position of the probe;
(c) rotating the plurality of rollers to slide the semiconductor substrate in the first direction to bring the back surface of the semiconductor substrate into contact with the lower contact jig;
(d) lowering the upper contact jig to measure the electrical characteristics of the semiconductor element while the probe is in contact with the surface of the semiconductor substrate;
A method of manufacturing a semiconductor device, comprising: The upper contact jig includes a probe card having the probes attached to its lower surface, and an annular shape extending from the lower surface of the probe card to the roller side and projecting the tip of the probe on the roller side. a pressurizing wall, and an air tube connected to the top surface of the probe card and supplying air to a space surrounded by the pressurizing wall to pressurize the space;
(e) between the step (b) and the step (c), after recognizing the height position of the end of the pressure wall on the roller side, the connection portion of the air tube with the probe card; The inlet area, which is the area of the inner circumference, and the outlet area, which is the value obtained by multiplying the inner circumference of the pressure wall by the length from the tip of the probe on the roller side to the end of the pressure wall on the roller side. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of: calculating and pressurizing said space surrounded by said pressurizing wall when said exit area is smaller than said entrance area.

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