JP2022136080A - Flexible wiring for low temperature application - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flexible wiring for low temperature application such as a quantum processor that uses a superconducting qubit.

SOLUTION: A device such as a flexible wiring includes an elongated flexible substrate, a plurality of conductive traces arranged in an array on the first side of the elongated flexible substrate, and an electromagnetic shielding layer on the second side of the elongated flexible substrate, and the second side is on the opposite side of the first side, and the elongated flexible substrate includes a folding area between a first conductive trace and a second conductive trace such that the electromagnetic shielding layer provides electromagnetic shielding between the first conductive trace and the second conductive trace.

SELECTED DRAWING: Figure 2

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present disclosure relates to flexible wiring for cryogenic applications, such as quantum processors using superconducting qubits.

Quantum computing is a relatively new computing method that exploits quantum effects such as ground state superposition and entanglement to perform certain computations more efficiently than conventional digital computers. In contrast to digital computers, which store and manipulate information in the form of bits (eg, "1" or "0"), quantum computing systems can use qubits to manipulate information. A qubit can refer to a quantum device that allows the superposition of multiple states (e.g., data in both the '0' and '1' states) and/or the superposition of data in multiple states itself. can. According to conventional terminology, the superposition of '0' and '1' states in a quantum system can be expressed as, for example, α|0>+β|1>. The '0' and '1' states of a digital computer are analogous to the |0> and |1> ground states of a qubit, respectively. The value |α| ² represents the probability that the qubit is in the |0> state, and the value |β| ² represents the probability that the qubit is in the |1> ground state.

In general, in some aspects, the subject matter of the present disclosure is an elongated flexible substrate, a plurality of conductive traces arranged in an array on a first side of the elongated flexible substrate, and a conductive trace on a second side of the elongated flexible substrate. an electromagnetic shielding layer, the second side opposite the first side, the elongated flexible substrate having the electromagnetic shielding layer interposed between the first conductive trace and the first conductive trace; A folded region is included between the first conductive trace and the second conductive trace to provide electromagnetic shielding between the two conductive traces.

Device implementations may include one or more of the following features. For example, in some implementations the folded region includes a raised band on the flexible substrate, the length of the elongated raised band extending parallel to the length of the first conductive trace and the second conductive trace. .

In some implementations, the flexible trace includes a first elongated groove in the folded region, the length of the first elongated groove being the length of the first conductive trace and the length of the second conductive trace. parallel.

The first elongated groove may extend to either the first side or the second side of the elongated flexible substrate. The flexible trace can include a second elongated groove in the folded region, the length of the second elongated groove being parallel to the length of the first conductive trace and the length of the second conductive trace, the first The elongated groove is on the first side of the substrate and the second elongated groove is on the second side of the substrate. The first elongated groove may extend into the electromagnetic shielding layer. The first elongated groove may extend into the elongated flexible substrate.

In some implementations, at least one conductive trace of the plurality of conductive traces includes a double layer, the double layer having a superconductor layer and a metal layer on the superconductor layer. The superconductor layer may contain niobium or NbTi. A metal layer may comprise copper or a copper alloy.

In some implementations, the electromagnetic shielding layer comprises a double layer, the double layer including a superconductor layer and a metal layer on the superconductor layer. The superconductor layer may contain niobium or NbTi. The metal layer may contain copper or a copper alloy.

In some implementations, the electromagnetic shielding layer includes a plurality of microstrips having lengths oriented orthogonal to the lengths of the plurality of conductive traces.

In general, in some other aspects, the presently disclosed subject matter includes a first elongated flexible layer, a second elongated flexible layer joined to the first elongated flexible layer, a first elongated flexible layer and a second elongated flexible layer. a plurality of conductive traces disposed at a bond interface between two elongated flexible layers; a first electromagnetic shielding layer on a major surface of the first elongated flexible layer; A device such as a flexible wiring comprising a second electromagnetic shielding layer on a major surface of the layer and a via extending through the first elongated flexible layer, the via comprising a superconductor via contact. can be

Flexible wiring implementations may include one or more of the following features. For example, in some implementations the via includes an adhesive layer and the superconductor via contact is formed on the adhesive layer.

In some implementations, the via extends from the first electromagnetic shielding layer to at least one conductive trace of the plurality of conductive traces, the superconductor via contact connecting the first electromagnetic shielding layer and the at least one connected to two conductive traces.

In some implementations, the via extends from the first electromagnetic shielding layer to the second electromagnetic shielding layer, and the superconductor via contact connects to the first electromagnetic shielding layer and the at least one conductive trace. be.

In general, in another aspect, the presently disclosed subject matter includes a first elongate flexible substrate, a first plurality of conductive traces arranged in an array on a first side of the first elongate flexible substrate, a first a first electromagnetic shielding layer on a second side of one elongated flexible substrate, the second side of the first elongated flexible substrate opposite the first side of the first elongated flexible substrate; A first flexible trace comprising a first electromagnetic shielding layer, a second elongated flexible substrate, and a second plurality of electrically conductive wires arranged in an array on a first side of the second elongated flexible substrate. a trace and a second electromagnetic shielding layer on a second side of the second elongated flexible substrate, the second side of the second elongated flexible substrate opposite the first side of the second elongated flexible substrate a second flexible trace comprising a second electromagnetic shielding layer on the side, the first flexible trace being coupled to the second flexible trace through a butt joint.

Device implementations may include one or more of the following features. For example, in some implementations, a butt joint is a wire connecting a first conductive trace from a first plurality of conductive traces to a first conductive trace from a second plurality of conductive traces. Including bond.

In some implementations, the butt joint comprises a solder bridge connecting a first conductive trace from the first plurality of conductive traces to a first conductive trace from the second plurality of conductive traces. include.

In some implementations, the device includes a metal block affixed to and in thermal contact with the first electromagnetic shielding layer and the second electromagnetic shielding layer.

In general, in another aspect, the presently disclosed subject matter includes a first elongated flexible substrate, a first plurality of conductive traces disposed at a bonding interface within the first elongated flexible substrate, and a first elongated flexible substrate. a first flexible trace comprising a first electromagnetic shielding layer on the first major surface of the substrate and a second electromagnetic shielding layer on the second major surface of the first elongated flexible substrate; two elongated flexible substrates, a second plurality of conductive traces disposed at a bonding interface within the second elongated flexible substrate, and a third electromagnetic shield on the first major surface of the second elongated flexible substrate. and a fourth electromagnetic shielding layer on the second major surface of the second elongated flexible substrate, the first flexible wiring through a butt joint. It is electrically connected to the second flexible wiring.

Device implementations may include one or more of the following features. For example, in some implementations, the first elongated flexible substrate includes a first cavity through which a first conductive trace of the first plurality of conductive traces is exposed, and the second elongated flexible substrate includes: , a second cavity through which a first conductive trace of a second plurality of conductive traces is exposed. The butt joint may include a wirebond connecting an exposed first conductive trace of the first plurality of conductive traces to an exposed first conductive trace of the second plurality of conductive traces.

In some implementations, the butt joint is solder connecting an exposed first conductive trace of the first plurality of conductive traces to an exposed first conductive trace of the second plurality of conductive traces. May include bridges.

In some implementations, the device further includes a first metal block secured to and in thermal contact with the first electromagnetic shielding layer and the third electromagnetic shielding layer. The device may further include a second metal block secured to and in thermal contact with the second electromagnetic shielding layer and the fourth electromagnetic shielding layer.

In general, in another aspect, the presently disclosed subject matter is a cryostat including a first stage configured to be maintained within a first temperature range; a quantum information processing system within the first stage; flexible wiring within one stage and coupled to a quantum information processing system, the flexible wiring arranged in an array on a first side of the elongated flexible substrate and the elongated flexible substrate; and an electromagnetic shielding layer on a second side of an elongated flexible substrate, the second side opposite the first side and the elongated The flexible substrate is positioned between the first conductive trace and the second conductive trace such that the electromagnetic shielding layer provides electromagnetic shielding between the first conductive trace and the second conductive trace. Including folding areas.

In general, in another aspect, the presently disclosed subject matter is a cryostat including a first stage configured to be maintained within a first temperature range; a quantum information processing system within the first stage; flexible wiring within one stage and coupled to a quantum information processing system, the flexible wiring comprising a first elongated flexible layer and a second elongated flexible layer joined to the first elongated flexible layer; two elongated flexible layers; a plurality of conductive traces disposed at the bond interface between the first elongated flexible layer and the second elongated flexible layer; a second electromagnetic shielding layer on a major surface of the second elongated flexible layer; and a via extending through the first elongated flexible layer, the via comprising a superconductor via contact. including.

Particular implementations of the subject matter described herein can realize one or more of the following advantages. For example, in some implementations, folded regions of flexible wiring provide electromagnetic shielding between signal traces. Shielding can reduce crosstalk without the need to form via holes in the substrate. In some implementations, when vias are provided in the substrate, the vias may be filled with a superconducting material (eg, niobium) that allows for improved signal integrity and reduced crosstalk. Furthermore, materials that are superconducting do not exhibit DC resistance, so the via metal does not lead to resistive heating. In some implementations, flexible wiring greatly increases the number and density of wires that can be connected to devices (e.g., quantum information processing systems, etc.) contained within a cryostat compared to devices using coaxial cables. becomes possible. Furthermore, by using flexible wiring instead of coaxial cables, the space required by coaxial cables can be freed up for purposes other than providing electrical connections. In some implementations, the flexible wiring utilizes materials such as copper, copper alloys (e.g., brass), or superconductors (e.g., NbTi) that provide relatively low thermal conductivity and therefore low heat load. do. Moreover, in some implementations, manufacturing costs associated with flexible wiring may be lower per wire than devices that rely on coaxial cables. In some implementations, flexible wires may be joined to other flexible wires using butt joints instead of coaxial cable connectors. Multiple connections can be established by using butt joints instead of coaxial cable connectors. Also, the use of butt joints may free up space within the cryostat that would otherwise be used by the coaxial cable connector. Moreover, in some implementations, butt bonding provides a lower cost manufacturing technique than soldering circuit boards, especially when a large number of connections need to be made.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, drawings, and claims.

1 is a schematic diagram illustrating an example of a cooling system for cooling a quantum information processing system; FIG. It is a schematic diagram showing an example of flexible wiring. It is a schematic diagram showing an example of flexible wiring. It is a schematic diagram showing an example of flexible wiring. It is a schematic diagram showing an example of flexible wiring. FIG. 4 is a schematic diagram showing an example of a modified butt joint bond for flexible wiring; FIG. 4 is a schematic diagram showing an example of a modified butt joint bond for flexible wiring; 7B is a side view of the flexible trace shown in FIG. 7A; FIG.

Quantum computing requires coherent processing of quantum information stored in a quantum computer's qubits. Superconducting quantum computing is a promising implementation of solid-state quantum computing technology in which quantum information processing systems are formed in part from superconducting materials. In order to operate quantum information processing systems employing solid-state quantum computing technologies such as superconducting qubits, the systems are maintained at very low temperatures, for example tens of mK. Extreme cooling of the system helps keep the superconducting material below its critical temperature and avoids unwanted state transitions. To maintain such low temperatures, quantum information processing systems may be operated within cryostats, such as dilution refrigerators. In some implementations, the limited cooling capacity of such cryostats can be reduced to higher temperatures where much greater cooling capacity is available and dissipative circuits are less likely to perturb qubits in quantum information processing systems. It requires that the control signal be generated in an environment of Control signals may be transmitted to the quantum information processing system using shielded, impedance-controlled, GHz-capable transmission lines, such as coaxial cables.

The number of quantum bits used in quantum information processing systems is expected to increase significantly (eg, tens of thousands, hundreds of thousands, millions or more) in the near future. As the number of qubits increases, so does the number of transmission lines (e.g., control and data lines) required to drive the qubits and to read the output from the operations performed by the quantum information processing system. may increase.

The present disclosure is directed to wiring for cryogenic applications, such as superconducting quantum information processing systems, and in certain implementations the wiring provides significant transmission line density while maintaining low crosstalk and low heat load between transmission lines. can be increased to Additionally, the devices and methods disclosed herein may provide a low-cost alternative to bulky transmission lines such as coaxial cables in certain implementations.

FIG. 1 is a schematic diagram illustrating an example cooling system 100 for cooling a quantum information processing system. Exemplary cooling system 100 includes cryostat 102 in which quantum information processing system 110 may be included. Cryostat 102 cools the ambient environment surrounding quantum information processing system 110 to a temperature suitable for performing operations in system 110 . For example, in implementations in which quantum information processing system 110 includes a quantum processor with superconducting qubits, cryostat 102 cools the ambient environment surrounding the quantum processor to a temperature below the superconducting material's critical temperature, e.g., about 20 mK. , or cooled to about 10 mK. Examples of superconducting materials that can be used in superconducting quantum information processing systems include Al (Tc=1.2K), In (Tc=3.4K), and Nb (Tc=9.3K). The cryostat 102 may be cooled using liquid or gaseous cryogens such as helium and nitrogen, or may be cooled with a closed cycle cryocooler using helium gas. In some cases, the circuit elements of quantum information processing system 110 operate at microwave frequencies (eg, frequencies in the range of about 300 MHz to about 100 GHz, such as between about 300 MHz and 10 GHz). Accordingly, cryostat 102 may include external and internal electromagnetic shielding to block interference with quantum information processing system 110 .

In some implementations, the cryostat includes multiple thermally isolated stages (eg, different stages of a dilution refrigerator) across large temperature differentials. For example, exemplary cryostat 102 includes multiple stages 101 , 103 , and 105 . A first stage 101 may be maintained at a first temperature range T1, a second stage 103 may be maintained at a second temperature range T2 below the first temperature T1, and a third stage 105 may be maintained at a second temperature range T2. A third temperature range T3 below temperature T2 may be maintained. For example, the third temperature range T3 may be below the critical temperature Tc of superconducting materials used in the quantum information processing system 110, eg, T2≈10-20 mK. In contrast, second stage 103 may be maintained at a higher temperature than third stage 105 . For example, the second stage 103 may be maintained within a temperature range T2 of less than 3K and greater than 20mK. First stage 101 may be maintained within a higher temperature range than second stage 103 . For example, the first stage 101 may be maintained within a temperature range T1 of less than 300K and greater than 3K. Although only three stages are shown in the example of FIG. 1, the cryostat can include additional stages at different temperature levels. For example, in some cases the cryostat may include fourth and fifth stages maintained within a fourth temperature range T4 and a fifth temperature range T5, respectively. Each temperature step in a cryostat is typically several centimeters in length from one temperature step to the next, for example.

Each stage within cryostat 102 may be separated by boundaries 104 , 106 . Boundaries 104, 106 may include a heat sink maintained at a constant temperature. The cryostat 102 stage is operated in a vacuum environment. For example, first stage 101, second stage 103, and third stage 105 can be operated under a vacuum base pressure of about 1×10 ⁻⁷ Torr or less. Quantum information processing system 110 may include a substrate (eg, a dielectric substrate such as silicon or sapphire) on which quantum information processing devices such as qubits are formed. The qubits may be combinable with each other such that the qubits perform useful computations during operation of system 110 . In addition to qubits, quantum information processing system 110 may include other components, such as measurement readout devices, coupler devices for coupling qubits, control devices for driving and tuning qubits, and the like. Quantum information processing system 110 may be placed and/or secured to sample mount 112 within third stage 105 .

Quantum information processing system 110 may be coupled to control electronics 150 located outside cryostat 102 to control quantum information processing system 110 and read data therefrom. In the example shown in FIG. 1, the control electronics 150 are coupled to the quantum information processing system 110 within the cryostat 102 using flexible wires 114,116. Signals generated by control electronics 150 or quantum information processing system 110 are transmitted via flexible wires 114 , 116 . Flexible traces 114, 116 include, for example, a plurality of conductive wires on or within an elongated flexible substrate. Flexible wiring 114, 116 may include electromagnetic shielding to protect the wires from signal interference. Additionally, wires in traces 114, 116 may be impedance matched to quantum information processing system 110 and control electronics 150 to reduce signal reflections from loads.

Each flexible trace 114, 116 may include multiple individual wires. The individual wires may extend along the length (long dimension) of the flexible traces 114, 116 and may be arranged in an array (e.g., the wires extend parallel along the length of the flexible traces 114, 116). can be used). The total number of wires in or on the flexible trace may vary. For example, each flexible trace 114, 116 may include 10 or more wires, 20 or more wires, 30 or more wires, 50 or more wires, 100 or more wires, or 200 or more wires. Similarly, other numbers of wires may be used within each flexible trace 114,116. Each flexible wire may be coupled to another flexible wire such that data and control signals may be transmitted from one flexible wire to another flexible wire. For example, flexible trace 114 may be coupled to flexible trace 116 . In some implementations, the first set of at least two flexible wires are respectively coupled to the second set of at least two flexible wires. For example, a first set of 5, 10, 15, 20 or more flexible wires may be coupled to a second set of 5, 10, 15, 20 or more flexible wires, respectively. Other numbers of flexible wires can be coupled together. In the first and/or second sets, the flexible wires within the set may be directly stacked on top of each other, or the individual flexible wires within the stack may be separated from each other using spacers (eg, 2-10 mm spacers). may An advantage of forming multiple wires within a flexible wire and/or using multiple flexible wires is that, in some implementations, the flexible wire has a smaller footprint and higher wire density, which may contribute to quantum information processing. It allows the total number of connections between the system and the control electronics to be significantly increased compared to devices that rely on coaxial cables. In some implementations, short portions of the flexible wires 114, 116 are anchored at the boundaries 104, 106 or elsewhere within the cryostat 102 to heat sink the flexible wires 114, 116. FIG. For example, wire 116 may be secured to a heat sink that is held at a temperature of 3K at boundary 104 . Similarly, line 114 may be secured to a heat sink held at a temperature of 20 mK at boundary 106 . In contrast, the distance between the boundaries of traces 114, 116 is much longer than the clamping length to reduce thermal energy flow.

FIG. 2 is a schematic diagram illustrating an example of flexible wiring that may be used for cryogenic applications, including, for example, coupling to a quantum information processing system within a cryostat, such as cryostat 102 . A top plan view of flexible trace 200 and a cross-sectional view of flexible trace 200 along line AA are shown in FIG. As shown in plan view, flexible trace 200 includes an elongated flexible substrate 202 . Flexible trace 200 also includes a plurality of conductive traces 204 disposed on a major surface (eg, top or upper side) of elongated flexible substrate 202 . Each conductive trace 204 corresponds to an individual wire, and multiple traces 204 may be arranged in an array. For example, the conductive traces 204 may be arranged in parallel such that their long dimension (eg, their length) extends along the long dimension (length) of the elongated flexible substrate 202 . The spacing between adjacent traces 204 may be the same for each pair of adjacent traces 204 .

Elongated flexible substrate 202 may be formed from a flexible plastic ribbon, such as a polyimide ribbon. Examples of materials that can be used for the elongated flexible substrate 202 include, for example, poly(4,4'-oxydiphenylene-pyromellitimide) (also known as Kapton®). The thickness of elongated flexible substrate 202 can be, for example, between about 10 μm and about 500 μm, including thicknesses such as about 20 μm, 50 μm, 75 μm, and 100 μm, among others. The width of the elongate flexible substrate 202 can be, for example, between about 1 mm and about 30 mm, including widths such as 10 mm, 15 mm, and 20 mm, among others. The length of elongated flexible substrate 202 may be at least as long as necessary to provide coupling between devices, systems, and/or other wiring.

Conductive traces 204 comprise a thin film material that can be patterned on elongated flexible substrate 202 . Conductive traces 204 may include, for example, a single layer of material or two layers of material. Materials that may be used to form conductive traces 204 may include superconducting materials and/or non-superconducting metals. Examples of materials that may be used to form conductive traces 204 include, for example, copper, copper alloys (cupronickel, brass, bronze), aluminum, indium, NbTi, NbTi alloys, and/or niobium. In some cases, it may be advantageous to use copper alloys with low thermal conductivity, as the thermal conductivity of copper may be too high, otherwise the heat transport may be higher. . This helps reduce the lower thermal power load so that the cryostat maintains the low temperatures necessary for operation of the quantum information processing system 110 . In the case of two-layer traces, traces 204 have a first layer formed over and in contact with elongated flexible substrate 202 and a second layer formed over and in contact with the first layer. can include layers of A first layer of a two-layer trace may comprise a superconducting material such as niobium, for example, and a second layer of the two-layer trace may comprise a non-superconducting material such as copper or a copper alloy, for example. To improve adhesion of metals or superconductors to the surface of substrate 202, for example, in the case of polyimide substrates, substrate 202 may be ion milled. Alternatively, the first layer of the dual layer trace may comprise a non-superconducting material such as copper and the second layer of the dual layer trace may comprise a superconducting material such as niobium or aluminum. In some implementations, the material used to form the conductive traces may depend on where the flexible traces are used in the cryostat. For example, in the lowest temperature regime, such as between 3 K and 10 mK (eg, where quantum information processing systems may be deployed), flexible interconnects may be formed using materials with low loss tangents and low heat transport. In such cases, the conductive traces may be formed from a superconductor such as niobium. In the high temperature regions of the cryostat, such as temperatures above 3 K (e.g., where the wiring transitions from low temperature to room temperature), flexible wiring may be formed of materials that are not superconducting but have lower heat transport, such as copper alloys. However, high temperature superconductors (eg Nb) can also be used. Additionally, in some implementations, the materials forming the traces may be selected for their role in providing solder connections. For example, copper may be used in areas where wire bonds or other solder bonds are required.

The length of conductive traces 204 may be as long as the length of elongated flexible substrate 202 . The width of each conductive trace 204 can be, for example, between about 1 μm and about 250 μm, including widths such as 5 μm, 10 μm, 20 μm, 30 μm, 50 μm, or 100 μm, among others. In some implementations, the width of the conductive trace is selected to provide a predetermined impedance, such as an impedance of 50 ohms, or an impedance of 75 ohms, to reduce signal reflections from the load. . The thickness of each conductive trace 204 can be, for example, between about 10 μm and about 100 μm, including thicknesses of 50 nm, 100 nm, 250 nm, 500 nm, 750 nm, 1 μm, 5 μm, 10 μm, 20 μm, 50 μm, among others. For two layers of conductive traces, the thickness of each layer may be the same or different. For example, in some implementations, the first layer is 2 μm thick while the second layer is 5 μm thick. Alternatively, in some cases, the thickness of the first layer is 20 μm while the thickness of the second layer is 5 μm. Conductive traces 204 may be separated by a constant or variable pitch. For example, in some implementations, the pitch between adjacent conductive traces 204 is between about 1 μm and about 1 mm, including pitches such as 5 μm, 10 μm, 50 μm, 100 μm, 250 μm, 500 μm, or 750 μm, among others. . Conductive traces 204 may be formed on elongate flexible substrate 202 using integrated chip (IC) manufacturing techniques such as deposition (eg, sputtering and deposition), etching, and/or lift-off techniques.

As shown in cross-sectional view AA of FIG. 2, the flexible trace 200 includes a conductive layer 208 on a second major surface/bottom surface of an elongated flexible substrate 202, the second major surface being the first major surface. / is the opposite side of the top surface. Conductive layer 208 may be an electromagnetic shielding layer for shielding conductive traces 204 from crosstalk. Flexible substrate 202 includes folded regions 206 to allow electromagnetic shielding layer 208 to provide shielding between traces 204 . Folded regions 206 include regions of flexible substrate 202 where substrate 202 is folded such that elongated raised bands are provided. The elongated raised bands of folded regions 206 can have lengths that extend between and along conductive traces 204 . For example, elongated raised bands of folded regions 206 may extend parallel to conductive traces 204 within spaces between adjacent conductive traces 204 . A raised band may be formed by folding a flexible substrate over itself in a manner similar to pleats. In some implementations, the peaks or vertices of the raised bands extend above the top surface of the conductive traces 204 (eg, the surface of the traces 204 facing away from the substrate 202). With the substrate 202 folded in this manner, the electromagnetic shielding layer 208 in the folded regions 206 creates elongated arcs that act as walls extending between adjacent traces 204 . The arc span of each folded region 206 is indicated by two parallel dashed lines in the plan view of FIG. Additionally, the peaks or vertices of the elongated arcs within folded region 206 may extend above the top surface of conductive trace 204 . As a result, the electromagnetic shielding layer 208 within the folded regions 206 provides an electromagnetic barrier between adjacent traces to shield crosstalk between the traces. As shown in the cross-sectional view of FIG. 2, the folded regions 206 appear as raised fins, giving the flexible trace an accordion-like shape. The folded region 206 shown in FIG. 2 includes portions of the first major surface of the flexible substrate where the conductive traces 204 are not formed. In other implementations, folded region 206 may include a portion of the first major surface of substrate 202 on which conductive traces 204 are formed. An advantage of introducing folded regions 206 is that shielding between traces is provided without providing external shielding for wires or forming shielding within substrate 202, as may be required in stripline designs. This is what we can offer. In some implementations, the folded regions 206 reduce crosstalk between adjacent conductive traces by 20 to 20% compared to flexible wiring having conductive traces formed on the first major surface without the folded regions. 60 dB or more reduction.

In order to hold the folded regions in place so that the substrate does not return to its initial flat state, the substrate and/or the electromagnetic shielding layer 208 are used to introduce mechanical stresses that help retain the folded shape. can be fixed. FIG. 3 is a schematic diagram illustrating an example of a flexible trace 250 that includes grooved regions for introducing mechanical stress to hold the folded regions in place. Similar to trace 200, flexible trace 250 includes an elongated flexible substrate 202, conductive traces 204 on a first major surface of substrate 202, and electromagnetic shielding layer 208 on a second major surface of substrate 202. . Various parameters regarding materials and dimensions described herein with respect to interconnect 200 may also apply to interconnect 250 . The difference between wire 250 (shown in plan and cross-section along line AA in FIG. 3) and wire 200 in FIG. It is shown flat. When the substrate 202 is folded to provide the folded regions, the grooves can provide mechanical stress to hold the folded regions in place.

In some implementations, a groove, such as groove 210 , is formed in the first major surface of substrate 202 . The length of groove 210 extends parallel to the length of one or more adjacent conductive traces 204 (eg, along the X direction in FIG. 3). Trench 210 may have a variety of different depths into substrate 202 . For example, groove depths can range from about 1 μm to about 500 μm, such as 10 μm, 20 μm, 50 μm, 70 μm, 100 μm, 200 μm, 250 μm, 300 μm, or 400 μm, among other depths. Groove 210 can have a variety of different widths. For example, groove widths can range from about 10 μm to about 1 mm, such as 20 μm, 50 μm, 100 μm, 250 μm, 500 μm, or 750 μm, among other widths. The grooves 210 may extend the entire length of the elongated flexible substrate 202, or may extend to a length less than the length of the elongated flexible substrate. In the example of FIG. 3, each groove 210 is shown as a single continuation extending between adjacent conductive traces 204 . In other implementations, multiple separate individual grooves may be formed between conductive traces 204, whether arranged in a single line or a series of lines (eg, a two-dimensional array).

In some implementations, grooves, such as grooves 212 , are formed in the second major surface of substrate 202 . The same variations in groove depth, width length, and placement described herein with respect to groove 210 may be applied to groove 212 . An electromagnetic shielding layer 208 may cover the grooves formed in the second major surface of the flexible substrate 202 . As shown in cross-sectional view along line AA in FIG. 3, grooves 212 may be disposed between adjacent conductive traces 204, eg, along the Y-axis. In some implementations, grooves 212 are formed in electromagnetic shielding layer 208 instead of the second major surface of substrate 202, as shown in FIG. That is, the electromagnetic shielding layer 208 may be patterned (eg, through photolithography and etching or a lift-off process) such that openings are formed only in the electromagnetic shielding layer and not in the substrate 202 . The depth of the groove may completely penetrate the electromagnetic shielding layer 208 or partially penetrate the electromagnetic shielding layer 208 . In some implementations, the grooves extend through electromagnetic shielding layer 208 to the second major surface of flexible substrate 202, as indicated by grooves 214 delimited by dashed lines in the cross-sectional view of FIG.

The grooves are formed in flexible substrate 202 using photoprocessing techniques (e.g., spin coating resist on substrate 202, exposing and developing a pattern in the resist, and etching the exposed areas of substrate 202 to form the grooves). can be formed. In other implementations, the grooves may be formed by user laser machining (eg, polyimide laser drilling techniques).

In some implementations, the folded region of the flexible trace may be held in place by placing the electromagnetic shielding layer in multiple strips extending across the second major surface of the elongated flexible substrate. Strips may be used in place of or in addition to the grooves described herein. For example, it is a schematic diagram showing an example of a flexible wiring 300 . Specifically, FIG. 4 includes a plan view of the second major surface of flexible wiring substrate 302 on which electromagnetic shielding layer 308 is formed, and a cross-sectional view through substrate 302 at line AA. In the plan view of FIG. 4, the locations, boundaries and placement of conductive traces 304 formed on the first major surface of substrate 302 are indicated using dashed lines. The flexible wiring 300 is shown in a flat state, ie, no folded regions have yet been formed.

As shown in FIG. 4, the electromagnetic shielding layer 308 is arranged in a plurality of separate strips having lengths extending along the Y direction. When substrate 302 is folded to provide a folded area, shield layer strips 308 may provide mechanical stress to hold the folded area in place. As further shown in the plan view of FIG. 4, the length of strips 308 extends along a direction (Y-direction) perpendicular to the direction in which the lengths of conductive traces 304 extend (X-direction). An advantage of using separate strips to form the electromagnetic shielding layer 308 is that the overall heat transfer can be lower due to the low thermal conductivity material used to provide the shielding layer.

Alternatively, in some implementations, the strip may be formed in addition to the ground layer rather than as a ground layer. For example, a ground plane layer, such as layer 208, can be provided on the second major surface of the elongated flexible substrate to provide a ground plane, and multiple strips, such as strip 308, to provide mechanical stability. can be formed on the surface of the ground plane layer. For example, the ground plane layer may be formed from niobium, while the strips formed on the surface of the ground plane layer may be formed from copper. The dimensions described herein with respect to layer 208 may also apply to the ground plane layer. Similarly, the dimensions and spacings described herein with respect to strips 308 may also apply to strips formed in the ground plane layer.

In some implementations, the number of wires contained within a flexible trace can be increased by stacking the flexible traces. For example, any of flexible traces 200, 250, or 300 can be stacked together to provide a laminated flexible trace. In some cases, the flexible traces may be stacked together using adhesive-based or adhesive-free laminate bonding techniques (eg, application of heat and/or pressure to bond polyimide layers). In certain implementations, it may be advantageous to use adhesive-free polyimide bonding to eliminate adhesives that can outgas in a vacuum environment. In addition, adhesiveless laminates may have a CTE that closely matches that of copper, thus reducing temperature significantly when cooled to extremely low temperatures such as those used in cryostats. reduces stress between the board and the shield/trace caused by dynamic changes. In some cases, laminated flexible traces can be formed using a polymeric encapsulant that is sprayed or painted onto the initial elongated polymeric substrate containing the conductive trace/shield layers. For example, in some cases flexible traces such as traces 200, 250, 300 are sprayed or painted with an epoxy encapsulant (e.g., Stycast 2850FT) and then cured to provide an additional layer of polymer, on top of which is further conductive. A flexible material can be deposited and patterned.

In contrast to the flexible wiring shown in FIGS. 2-4, in some implementations the flexible wiring may be formed as a stripline. FIG. 5 is a schematic diagram illustrating an example of a flexible trace 500 formed in a stripline configuration. Flexible trace 500 includes signal traces 506 disposed between a first elongated flexible substrate portion 502 and a second elongated flexible substrate portion 504 . Signal traces 506 may include conductive thin film materials for transmitting control and/or data signals. A top surface (e.g., a first major surface) of first elongated flexible substrate portion 502 can include a first conductive layer 508, while a bottom surface (e.g., a second major surface) of second elongated flexible substrate portion 504 major surface) may include a second conductive layer 510 . First conductive layer 508, second conductive layer 510, and signal traces 506 may comprise, for example, thin film materials such as metal or superconductor thin films. For example, the metal or superconductor thin film may include thin film layers of copper, copper alloys, aluminum, niobium, or indium. Although only a single signal trace 506 is shown in FIG. 5, multiple signal traces 506 may be provided between the first elongated flexible substrate portion 502 and the second elongated flexible substrate portion 504 (eg, as shown in FIG. 5). 5 pages in and out). For example, such signal traces 506 can be aligned in parallel in a manner similar to the conductive traces 204 shown in FIG.

In some cases, first conductive layer 508 , second conductive layer 510 , and/or signal traces 506 may comprise a bilayer film as described herein with respect to flexible trace 200 . For example, as shown in FIG. 5, the second conductive layer 510 has a first thin film layer 518 formed on and/or in contact with the bottom surface of the second elongated flexible substrate portion 504. It can include layer membranes. The bilayer membrane can further include a second membrane layer 516 formed over and in contact with the first membrane layer 518 . A bilayer membrane can also be formed on the top surface of the first elongated flexible substrate portion 502 . In some implementations, a portion of second layer 516 is removed to reveal underlying first layer 518 .

The length of signal trace 506 may be the same length as the length of elongated flexible substrate portions 502,504. The width of each signal trace 506 can be, for example, between about 1 μm and about 250 μm, including widths such as 5 μm, 10 μm, 20 μm, 30 μm, 50 μm, or 100 μm, among others. The thickness of each signal trace 506 can be, for example, between about 10 μm and about 100 μm, including thicknesses of 50 nm, 100 nm, 250 nm, 500 nm, 750 nm, 1 μm, 5 μm, 10 μm, 20 μm, 50 μm, among others. For two layers of conductive traces, the thickness of each layer may be the same or different. For example, in some implementations, the first layer is 2 μm thick while the second layer is 5 μm thick. Alternatively, in some cases, the thickness of the first layer is 20 μm while the thickness of the second layer is 5 μm. Conductive traces 204 may be separated by a constant or variable pitch. For example, in some implementations, the pitch between adjacent signal traces 506 is between about 1 μm and about 1 mm, including pitches such as 5 μm, 10 μm, 50 μm, 100 μm, 250 μm, 500 μm, or 750 μm, among others. Signal traces 506 may be formed on elongate flexible substrate portion 502 or 504 using integrated chip (IC) manufacturing techniques such as deposition (eg, sputtering and deposition), etching, and/or lift-off techniques.

Each of the first elongated flexible substrate portion 502 and the second elongated flexible substrate portion 504 are made from a flexible plastic ribbon such as, for example, a polyimide ribbon (eg, poly(4,4′-oxydiphenylene-pyromellitimide)). can be formed. A first elongated flexible substrate portion 502 can be joined to a second elongated flexible substrate portion 504 . The thickness of substrate portions 502 and 504 can be, for example, between about 10 μm and about 500 μm, including thicknesses such as about 20 μm, 50 μm, 75 μm, and 100 μm, among others. The width of the elongated flexible substrate 502 can be, for example, between about 1 mm and about 30 mm, including widths such as 10 mm, 15 mm, and 20 mm, among others. The length of elongated flexible substrate portions 502 and 504 may be at least as long as necessary to provide coupling between devices, systems, and/or other wiring.

First conductive layer 508 and second conductive layer 510 may each correspond to an electromagnetic shielding layer that shields signal trace 506 from external signal noise. In some implementations, flexible traces 500 are combined with one or more flexible traces 500 to provide a stacked flexible trace with an increased number of signal lines for transmitting control and/or data signals. Stackable. As described herein, flexible traces may be stacked together using adhesive-based or adhesive-free laminate bonding techniques. In some cases, laminated flexible traces can be formed using a polymeric encapsulant that is sprayed or painted onto the initial elongated polymeric substrate containing the conductive trace/shield layers. For example, in some cases, a flexible trace such as trace 500 is sprayed or painted with an epoxy encapsulant material (eg, Stycast 2850FT) and then cured to provide an additional polymer layer upon which further conductive material is deposited. can be patterned.

In some implementations, flexible trace 500 includes one or more vias 512 that extend through first elongated flexible substrate portion 502 . Via 512 may include a conductive material (via contact 514 ) formed within via 512 . Via contacts 514 may comprise superconducting and/or non-superconducting metals such as, for example, copper, aluminum, niobium, indium, or copper alloys. In some cases, via contact 514 is formed on the sidewalls of via 512 but does not completely fill via 512 . In other cases, via contact 514 completely fills via 512 such that there is no continuous opening extending through via 512 . In some implementations, via contact 514 includes an adhesion layer formed to help adhere via contact 514 to the sides of via 512 . For example, the adhesion layer may include a copper or niobium film (eg, between about 1 nm and about 1 micron thick defined for the via sidewalls). In some implementations, the via contact 514 material formed on the adhesion layer is a copper or niobium film (eg, between about 500 nm and about 20 microns thick defined for the via sidewalls). can contain.

The adhesion layer, for example, uses electroless plating of adhesion layer material (e.g., Cu) to establish a thin first adhesion layer and then establishes a second adhesion layer on the first adhesion layer. can be formed by performing electroplating of a glue layer material (eg, Cu) to The remaining material (eg, Al, Cu, or Nb) of via contact 514 may then also be formed on the adhesion layer using, for example, electroplating. For example, aluminum can be plated (eg, electroplated) onto the adhesion layer. Other plating techniques may also be used to plate via contacts 514 . For example, solvent-based plating can be used to form niobium via contacts.

In some implementations, via 512 extends from first conductive layer 508 to signal trace 506 such that via contact 514 connects first conductive layer 508 to signal trace 506 . In some implementations, via 512 extends from first conductive layer 508 to second conductive layer 510 such that via contact 514 connects first conductive layer 508 to second conductive layer 510 . extends to In some implementations, via 512 extends from second conductive layer 510 to signal trace 506 such that via contact 514 connects second conductive layer 510 to signal trace 506 . Vias 512 may be formed using laser drilling techniques.

In some implementations, flexible trace 500 has areas where signal traces 506 are exposed so that electrical connections, such as wire bonds or bump bonds, can be made to the signal traces. Exposing signal traces 506 includes removing a portion of first elongated flexible substrate portion 502 and/or removing a portion of second elongated flexible substrate portion 504 covering signal traces 506 . obtain. In some cases, the length of first elongated flexible substrate portion 502 and/or second elongated flexible substrate portion 504 is long enough to cover the entire signal trace 506 such that a portion of signal trace 506 is exposed. It's not.

An example technique for connecting flexible wires to each other, to a quantum information processing system, and/or to circuit components is to use coaxial connectors, such as SMA connectors. However, coaxial connections can be bulky and thus occupy much of the limited available space within the cryostat. In addition, the bulkiness of coaxial connectors can also make it difficult to connect high density flexible wiring to the contacts. An alternative to coaxial connectors is the use of modified butt joint bonds that employ wire bonding between flexible wire contacts. FIG. 6 is a schematic diagram showing an example of a modified butt joint bond employing wire bonding. Specifically, FIG. 6 shows a cross-sectional view of a first flexible wire 602 coupled to a second flexible wire 604 using a modified butt joint bond. Each of first flexible trace 602 and second flexible trace 604 may have the same configuration as flexible trace 200 shown in FIG. For example, the flexible wiring 602 includes an elongated flexible substrate 606, a plurality of conductive traces 608 (one trace 608 is shown in FIG. 6) disposed on a major surface of the elongated flexible substrate 606, and an elongated flexible substrate 606. may include a conductive layer 610 on the second major surface of the . Similarly, flexible wiring 604 includes an elongated flexible substrate 612, a plurality of conductive traces 614 (one trace 614 is shown in FIG. 6) disposed on a major surface of elongated flexible substrate 612, and an elongated flexible substrate. A conductive layer 616 on the second major surface of 612 may be included. 2, each conductive trace 608, 614 corresponds to an individual wire, and multiple traces can be arranged in an array (e.g., in the Y direction into and out of the page in FIG. 6). Along). Additionally, conductive layers 610 and 616 can be electromagnetic shielding layers for shielding conductive traces 608, 614, respectively, from crosstalk. Although both flexible traces 602 and 604 are shown flat in FIG. can be provided.

A first flexible trace 602 is arranged with an edge 601 facing an edge 603 of a second flexible trace 604 . Edge 601 may be separated from edge 603 by a relatively short distance 622 and may touch each other. For example, distance 622 can be between about 25 microns and about several millimeters, such as 100 μm or 250 μm, among other distances. Wirebonds 618 are provided that may be used to electrically connect traces 608 of first flexible wire 602 to traces 614 of second flexible wire 604 .

In some implementations, solder bridges may be used instead of wire bonds to electrically connect traces 608 of first flexible wire 602 to traces 614 of second flexible wire 604 . Distance 622 should be kept as small as possible to allow solder bridges to form. The wire bonds 618 or solder used to form the solder bridges may be formed from superconducting or non-superconducting materials.

Both the edge 601 of the first flexible trace 602 and the edge 603 of the second flexible trace 604 can be cut using laser machining to provide more precise and relatively smooth edges. Edges 601 and 603 can then be placed closer together to shorten the bridge length of the solder bridge, which improves the integrity of the connection and facilitates the bonding process.

In some implementations, a joint between the first flexible trace 602 and the second flexible trace 604 provides an electrical connection between the first flexible trace 602 and the second flexible trace 604. to the metal block to provide mechanical connection to the first flexible wire 602 and the second flexible wire 604, and/or to maintain the wires at the temperature of the cryostat stage in which they are placed. fixed. For example, as shown in FIG. 6, a metal block 620 may be affixed to and in thermal contact with the electromagnetic shielding layers 610,616. In some implementations, metal block 620 is fixed in place relative to flexible wires 602 and 604 . Alternatively or additionally, metal block 620 is secured to shield layers 610, 616 through an adhesive such as solder. Metal block 620 may be formed from a material suitable for providing sufficient heat transfer within the cryostat, such as copper. In some implementations, shield layers 610, 616 double as ground planes and metal block 620 provides a common ground.

FIG. 6 shows a modified butt joint for flexible wiring with the configuration provided shown in FIG. In some implementations, modified butt joints may also be used with flexible wiring having the configuration shown in FIG. For example, Figure 7A is a schematic diagram showing a cross section of a first flexible wire 702 coupled to a second flexible wire 704 using a modified butt joint. Each of first flexible trace 702 and second flexible trace 704 has the same stripline configuration as flexible trace 500 shown in FIG. For example, flexible trace 702 includes a first elongated flexible substrate portion 706 , a second elongated flexible substrate portion 708 , signal traces 714 disposed between portions 706 and 708 , and a first elongated flexible substrate portion 706 on the top surface of substrate portion 706 . It may include one conductive layer 710 and a second conductive layer 712 on the bottom surface of substrate portion 708 . Similarly, flexible traces 704 include a first elongated flexible substrate portion 716 , a second elongated flexible substrate portion 718 , signal traces 724 disposed between portions 716 and 718 , and an upper surface of substrate portion 716 . It may include a first conductive layer 720 and a second conductive layer 722 on the bottom surface of substrate portion 718 . 5, each signal trace 714, 724 corresponds to an individual wire, and multiple traces can be arranged in an array (e.g., along the Y direction into and out of the page in FIG. 7A). hand). Additionally, the conductive layers 710, 712, 720, 722 can be electromagnetic shielding layers to shield the signal traces 714, 724 from crosstalk.

A first flexible trace 702 is arranged with an edge 701 facing an edge 703 of a second flexible trace 704 . Edge 701 may be a relatively short distance from edge 703 and may touch each other. For example, edge 701 may be separated from edge 703 by a distance between about 25 microns and about a few millimeters, such as 100 μm or 250 μm, among other distances. Wirebonds 730 are provided that may be used to electrically connect traces 714 of first flexible wire 702 to traces 724 of second flexible wire 704 . In some implementations, solder bridges may be used instead of wire bonds to connect traces 714 of first flexible wire 702 to traces 724 of second flexible wire 704 . The distance between the first edge 701 and the second edge 703 should be kept as small as possible to allow solder bridges to form. Both the edge 701 of the first flexible trace 702 and the edge 703 of the second flexible trace 704 can be cut using laser machining to provide more precise and relatively smooth edges. Edges 701 and 703 can then be placed closer together to shorten the bridge length of the solder bridge, which improves the integrity of the connection and facilitates the bonding process. The solder used to form wire bonds 730 or solder bridges may be formed from superconducting or non-superconducting materials.

In some implementations, first flexible trace 702 may include region 726 where substrate portion 706 is removed or does not expose portions of signal traces 714 . Similarly, second flexible trace 704 may include area 728 where substrate portion 716 is removed or does not expose a portion of signal trace 724 . By exposing the signal traces in regions 726, 728, the signal traces 726, 728 can be accessed for forming wire bonds or solder bridge bonds. FIG. 7B is a schematic diagram showing a side view of edge 703 and region 728 of second flexible trace 704 of FIG. 7A. As shown in FIG. 7B, only a portion of substrate portion 716 directly above signal traces needs to be removed or absent to form regions 728 and expose signal traces 724 . Substrate portions 716 to the left and right of region 728 may be left in place to bond to substrate portion 718 and provide support surfaces for conductive layer 720 . In some implementations, regions 726 , 728 include solder that forms an electrical connection between first flexible trace 702 and second flexible trace 704 .

In some implementations, a joint between the first flexible trace 702 and the second flexible trace 704 provides an electrical connection between the first flexible trace 702 and the second flexible trace 704. and/or to provide a mechanical connection between the first flexible wire 702 and the second flexible wire 704 to maintain the wire at the temperature of the cryostat stage in which it is placed. Fixed to the block and in thermal contact. For example, a metal block 732 can be placed against the electromagnetic shielding layers 712, 722, as shown in FIG. 7A. In some implementations, metal block 732 is fixed in place relative to flexible wires 702 and 704 . Alternatively or additionally, metal block 732 is secured to shield layers 712, 722 through an adhesive such as solder. Alternatively or additionally, additional metal blocks are secured to and in thermal contact with the shield layers 710,720. Additional metal blocks may also be secured to the shield layers 710, 720 through adhesives such as solder. The metal block may be formed from a material suitable for providing sufficient heat transfer within the cryostat, such as copper. In some implementations, the shield layers 712, 722 double as ground planes and the metal block 732 provides a common ground. Similarly, shield layers 710, 720 may double as ground planes with additional metal blocks providing a common ground.

In some implementations, the joint between the first flexible trace and the second flexible trace is at one temperature stage of the cryostat held at the first temperature and at a second temperature stage different from the first stage. A boundary within the cryostat separating a second temperature stage of the cryostat held at two temperatures may be provided. For example, the joint may anneal a first flexible trace, such as first flexible trace 602 or 702 in a temperature stage (e.g., stage 103 in FIG. 1) held at a temperature below 3K, but above 3K but above room temperature. It may connect to a second flexible wire, such as second flexible wire 604 or 704 in a temperature stage (eg, stage 101 in FIG. 1) held at a lower temperature. In some implementations, the flexible wiring in transitions between different temperature stages within the cryostat, or transitioning from a vacuum environment to another vacuum or non-vacuum environment, is combined with a flexible wiring and a clamping device (e.g., a metal such as a copper ring). It can be sealed at the transition using epoxy glue fixed to the ring).

Various techniques may be used to manufacture flexible wiring, as disclosed herein. For example, in some implementations, flexible wiring may be constructed by providing a large substrate (eg, a flexible plastic substrate such as polyimide) on which metal and/or superconducting films are formed. Substrates can include, for example, large sheets, such as 12 inches by 14 inches, greater than 8 inches on a side. The substrate may be placed in a vacuum chamber to deposit the metal/superconducting film. Prior to depositing the film, the substrate surface may be cleaned, for example by performing an ion cleaning (eg Ar ion cleaning). If a bilayer film is to be formed on a substrate, a first layer of material is blanket deposited on the substrate. The first layer may include, for example, a superconductor film such as niobium deposited using sputtering. Alternatively, the first layer may comprise a non-superconducting film such as copper. The first layer may be deposited to have a thickness of up to about 5 microns. For example, the first layer may be deposited to have a thickness of 100 nm, 250 nm, 500 nm, 750 nm, 1 μm, or 2 μm, among other thicknesses. A second layer is then blanket deposited (eg, sputtered or electrolessly plated) over the first layer. The second layer may comprise a non-superconducting film such as copper or a superconducting film such as niobium or aluminum. The second layer can be deposited to have a thickness of up to about 20 μm. For example, the second layer can be deposited to have a thickness of 100 nm, 250 nm, 500 nm, 750 nm, or 1 μm. In some cases, the first deposited portion of the second layer serves as a base layer for subsequent electroplating steps. For example, a thin 100 nm film of copper can be deposited after a thicker layer of copper is electroplated. In some implementations, films are deposited on both the top and bottom sides of the substrate. The deposited film can then be patterned (eg, using an etching or lift-off process) to form a desired circuit pattern. In some cases, for a two-layer film, the same pattern is transferred to both the first layer and the second layer during the patterning step. In other cases, the patterning step forms a different pattern in the first layer and then in the second layer. In some implementations, via holes are formed in the substrate using a laser etching process. The via hole may then be filled with a via contact material (eg, copper and/or superconducting material) to form a via contact. Once patterned, the substrate sheet can be divided into individual flexible traces. Dividing the substrate sheet may require performing laser cutting on the substrate sheet or using a blade to mechanically cut the substrate sheet. In some implementations, dividing the substrate sheet results in the final flexible traces. Alternatively, in some implementations, to form a laminated flexible wiring (eg, a stack of multiple flexible wiring 200), to form a stripline configuration (eg, flexible wiring 500), or to form a laminated stripline flexible wiring Separated substrate sheets may be stacked together to form the wiring. Stacking the divided substrate sheets may involve introducing an adhesive between the cured substrates so that the laminated substrates are bonded together. Alternatively, the split substrate sheets can be joined together using adhesiveless bonding techniques. After obtaining the laminated flexible trace, further processing may be performed as desired. For example, additional via contacts may be formed in one or more of the laminate substrates to provide connections to conductive traces on the laminate flexible wiring.

In some implementations, flexible wiring may be constructed using an extrusion and roll process. For example, a first elongated sheet of superconducting or non-superconducting material (eg, a 0.25 inch thick sheet of niobium, aluminum, or copper) may be provided. Optionally, a second elongated sheet of superconducting or non-superconducting material (eg, a 0.25 inch thick sheet of niobium, aluminum, or copper) may be provided on top of the first elongated sheet. If only a single sheet is provided, the single sheet of material is passed through an extruder which thins the sheet (eg, to a thickness of between about 20 microns and about 10 mm). If two layers are provided, the first and second elongated sheets may be pressed together under vacuum and/or heat and passed through an extruder to thin the bilayer sheet (e.g., about 20 thickness between microns to about 10 mm), the materials in the two-layer sheets adhere to each other. The thinned monolayer or bilayer sheet can then be laminated with a polyimide substrate. In some implementations, thinned monolayer or bilayer sheets are laminated to both sides of the polyimide substrate. As described herein, superconducting and/or non-superconducting films on polyimide substrates can be patterned (eg, using an etching process) to form a desired circuit pattern. In some cases, for a two-layer film, the same pattern is transferred to both the first layer and the second layer during the patterning step. In other cases, the patterning step forms a different pattern in the first layer and then in the second layer. In some implementations, via holes are formed in the substrate using a laser etching process. The via hole may then be filled with a via contact material (eg, copper and/or superconducting material) to form a via contact. Once patterned, the substrate sheet containing the patterned membrane can be divided into individual flexible traces. Dividing the substrate sheet may require performing laser cutting on the substrate sheet or using a blade to mechanically cut the substrate sheet. In some implementations, dividing the substrate sheet results in the final flexible traces. Alternatively, in some implementations, to form a laminated flexible wiring (eg, a stack of multiple flexible wiring 200), to form a stripline configuration (eg, flexible wiring 500), or to form a laminated stripline flexible wiring Separated substrate sheets may be stacked together to form the wiring. Stacking the divided substrate sheets may involve introducing an adhesive between the cured substrates so that the laminated substrates are bonded together. Alternatively, the split substrate sheets can be joined together using adhesiveless bonding techniques. After obtaining the laminated flexible trace, further processing may be performed as desired. For example, additional via contacts may be formed in one or more of the laminate substrates to provide connections to conductive traces on the laminate flexible wiring.

Implementations of the quantum subject matter and quantum operations described herein are quantum information processing techniques, including suitable quantum circuits, or more generally, the structures disclosed herein and their structural equivalents. It can be implemented in a quantum computing system, also called a system, or in one or more combinations thereof. The terms "quantum computing system" and "quantum information processing system" may include, but are not limited to, quantum computers, quantum cryptographic systems, topology quantum computers, or quantum simulators.

The terms quantum information and quantum data refer to information or data carried by, held in, or stored in a quantum system, the smallest system of interest being the qubit, e.g., defining a unit of quantum information. It is a system that The term "qubit" is understood to encompass any quantum system that can be properly approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, eg, with two or more levels. By way of example, such systems may include atomic, electronic, photon, ion, or superconducting qubits. In some implementations, the calculated ground state is identified with the ground and first excited states, but it is understood that other setups are possible in which the calculated state is identified with higher-level excited states. Quantum memory is a device capable of storing quantum data for long periods of time with high fidelity and efficiency, e.g. at the photomatter interface where light is used for transmission, or quantum data such as superposition or quantum coherence. It is understood to be such as for storing and storing features.

Quantum circuitry (also called quantum computing circuitry) includes circuitry for performing quantum processing operations. That is, quantum circuit elements are configured to exploit quantum mechanical phenomena such as superposition and entanglement to perform operations on data in a non-deterministic manner. Certain quantum circuit elements, such as qubits, can be configured to represent and operate on information in multiple states simultaneously. Examples of superconducting quantum circuit devices include, among others, quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUID) and other circuit elements.

In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements can be configured to collectively execute computer program instructions by performing basic arithmetic, logic, and/or input/output operations on data, where data is Represented in analog or digital form. In some implementations, classical circuit elements can be used to send data to and/or receive data from quantum circuit elements over electrical or electromagnetic connections. Examples of classical circuit elements include CMOS circuits, fast single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and circuit elements based on ERSFQ devices, which are based on RSFQ without bias resistors. Energy efficient version.

Fabrication of quantum and classical circuit elements described herein may involve deposition of one or more materials such as superconductors, dielectrics, and/or metals. Depending on the materials selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. can be done. The process for manufacturing circuit elements described herein may involve removing one or more materials from the device during manufacture. Depending on the material to be removed, removal processes can include, for example, wet etching techniques, dry etching techniques, or lift-off processes. The materials forming the circuit elements described herein can be patterned using known lithographic techniques (eg, photolithography or electron beam lithography).

During operation of a quantum computing system that employs superconducting quantum circuit elements and/or superconducting classical circuit elements, such as the circuit elements described herein, the superconducting circuit elements demonstrate that the superconducting material exhibits superconducting properties. is cooled in the cryostat to a temperature that allows A superconducting (or superconducting) material can be understood as a material that exhibits superconducting properties below the superconducting critical temperature. Examples of superconducting materials are aluminum (superconducting critical temperature of about 1.2 Kelvin), indium (superconducting critical temperature of about 3.4 Kelvin), NbTi (superconducting critical temperature of about 10 Kelvin), and niobium ( superconducting critical temperature of about 9.3 Kelvin). Accordingly, superconducting structures, such as superconducting traces and superconducting ground planes, are formed from materials that exhibit superconducting properties below the superconducting critical temperature.

Although this specification contains many specific implementation details, these should not be construed as limitations on the scope that may be claimed, but as a description of features that may be unique to the particular implementation. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Further, while functions may be described above as functioning in a particular combination, and may initially be claimed as such, in some cases one or more functions from the claimed combination are omitted from the combination. , and a claimed combination may cover subcombinations or variations of subcombinations.

Similarly, although acts have been drawn in a particular order in the figures, this does not mean that such acts are performed in the specific order or order shown, or at all, to achieve a desired result. It should not be understood as requiring the actions described to be performed. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. Multitasking and parallel processing can be advantageous in certain situations. Furthermore, the separation of various components in the implementations described above should not be understood as requiring such separation in all implementations.

A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.

100 cooling system 102 cryostat 101 first stage 103 second stage 104 boundary 105 third stage 106 boundary 110 quantum information processing system 112 sample mount 114 flexible wiring 116 flexible wiring 150 control electronics 200 flexible wiring 202 elongate flexible substrate 204 conductive trace 206 folded region 208 conductive layer 208 electromagnetic shielding layer 210 groove 212 groove 214 groove 250 flexible wiring 300 flexible wiring 302 flexible wiring substrate 304 conductive trace 308 electromagnetic shielding layer 308 shielding layer strip 500 flexible wiring 502 first elongated strip flexible substrate portion 504 second elongate flexible substrate portion 506 signal trace 508 first conductive layer 510 second conductive layer 512 via 514 via contact 516 second membrane layer 518 first membrane layer 601 edge 602 first flexible trace 603 edge 604 second flexible trace 606 elongated flexible substrate 608 conductive trace 610 conductive layer 610 electromagnetic shielding layer 612 elongated flexible substrate 614 conductive trace 616 conductive layer 616 electromagnetic shielding layer 618 wire bond 620 metal block 622 distance 701 edge 702 first flexible trace 703 edge 704 second flexible trace 706 first elongate flexible substrate portion 708 second elongate flexible substrate portion 710 shield layer 710 first conductive layer 712 shield layer 712 second Conductive Layer 712 Electromagnetic Shielding Layer 714 Signal Trace 716 First Elongated Flexible Substrate Portion 718 Second Elongated Flexible Substrate Portion 720 First Conductive Layer 720 Shielding Layer 722 Second Conductive Layer 722 Shielding Layer 722 Electromagnetic Shielding Layer 724 signal trace 726 area 728 area 730 wire bond 732 metal block

Claims (30)

an elongated flexible substrate;
a plurality of conductive traces arranged in an array on a first side of the elongated flexible substrate;
an electromagnetic shielding layer on a second side of the elongated flexible substrate, the second side opposite the first side;
The elongated flexible substrate extends between the first conductive trace and the second conductive trace such that the electromagnetic shielding layer provides electromagnetic shielding between the first conductive trace and the second conductive trace. A flexible trace with folded regions between traces. 2. The folded region of claim 1, wherein the folded region comprises a raised band on the flexible substrate, the length of the elongated raised band extending parallel to the length of the first conductive trace and the second conductive trace. Flexible wiring described in . 3. The folded region comprises a first elongated groove, the length of the first elongated groove being parallel to the length of the first conductive trace and the length of the second conductive trace. 1. Flexible wiring according to 1. 4. The flexible trace of claim 3, wherein said first elongated groove extends to said first side or said second side of said elongated flexible substrate. comprising a second elongated groove in the folding region;
a length of said second elongated groove is parallel to said length of said first conductive trace and said length of said second conductive trace;
4. The flexible trace of claim 3, wherein said first elongated groove is on said first side of said substrate and said second elongated groove is on said second side of said substrate. 4. The flexible wiring of Claim 3, wherein said first elongated groove extends into said electromagnetic shielding layer. 7. The flexible trace of Claim 6, wherein said first elongated groove extends into said elongated flexible substrate. 2. The method of claim 1, wherein at least one conductive trace of said plurality of conductive traces comprises a double layer, said double layer having a superconductor layer and a metal layer over said superconductor layer. flexible wiring. 9. The flexible wiring of claim 8, wherein said superconductor layer comprises niobium or NbTi. 9. The flexible wiring of Claim 8, wherein said metal layer comprises copper or a copper alloy. 2. The flexible wiring of claim 1, wherein said electromagnetic shielding layer comprises a double layer, said double layer comprising a superconductor layer and a metal layer on said superconductor layer. 12. The flexible wiring of claim 11, wherein said superconductor layer comprises niobium. 12. The flexible wiring of Claim 11, wherein said metal layer comprises copper or a copper alloy. 2. The flexible wiring of claim 1, wherein said electromagnetic shielding layer comprises a plurality of microstrips having lengths oriented perpendicular to the lengths of said plurality of conductive traces. a first elongate flexible layer;
a second elongated flexible layer joined to the first elongated flexible layer;
a plurality of conductive traces disposed at a bond interface between the first elongated flexible layer and the second elongated flexible layer;
a first electromagnetic shielding layer on a major surface of the first elongated flexible layer;
a second electromagnetic shielding layer on a major surface of the second elongated flexible layer;
a via extending through the first elongated flexible layer, the via including a superconductor via contact. 16. The flexible wiring of Claim 15, wherein said vias comprise an adhesive layer, and wherein said superconductor via contacts are formed on said adhesive layer. The via extends from the first electromagnetic shielding layer to at least one conductive trace of the plurality of conductive traces, and the superconductor via contact contacts the first electromagnetic shielding layer and the at least one conductive trace. 16. The flexible trace of claim 15, connected to a conductive trace. The via extends from the first electromagnetic shielding layer to the second electromagnetic shielding layer, and the superconductor via contact connects to the first electromagnetic shielding layer and the at least one conductive trace. 16. The flexible wiring according to claim 15. a first elongated flexible substrate; a first plurality of conductive traces arranged in an array on a first side of said first elongated flexible substrate; a first electromagnetic shielding layer, wherein the second side of the first elongated flexible substrate is opposite the first side of the first elongated flexible substrate; and a first flexible trace comprising
a second elongated flexible substrate; a second plurality of conductive traces arranged in an array on a first side of said second elongated flexible substrate; a second electromagnetic shielding layer, wherein the second side of the second elongated flexible substrate is opposite the first side of the second elongated flexible substrate; and a second flexible trace comprising:
A device, wherein the first flexible trace is coupled to the second flexible trace through a butt joint. 4. The butt joint comprises a wirebond connecting a first conductive trace from the first plurality of conductive traces to a first conductive trace from the second plurality of conductive traces. 20. The device according to 19. 3. The butt joint comprises a solder bridge connecting a first conductive trace from the first plurality of conductive traces to a first conductive trace from the second plurality of conductive traces. 20. The device according to 19. 20. The device of Claim 19, further comprising a metal block fixed in thermal contact with said first electromagnetic shielding layer and said second electromagnetic shielding layer. a first elongated flexible substrate; a first plurality of conductive traces disposed at a bond interface within said first elongated flexible substrate; and a second electromagnetic shielding layer on a second major surface of the first elongated flexible substrate;
a second elongated flexible substrate; a second plurality of conductive traces disposed at a bonding interface within said second elongated flexible substrate; and a fourth electromagnetic shielding layer on the second major surface of the second elongate flexible substrate, the device comprising:
A device, wherein the first flexible trace is electrically connected to the second flexible trace through a butt joint. The first elongated flexible substrate comprises a first cavity through which a first conductive trace of the first plurality of conductive traces is exposed, and the second elongated flexible substrate comprises a second plurality of conductive traces. 24. The device of claim 23, comprising a second cavity through which the first conductive trace of the conductive trace of is exposed. the butt bond forming a wirebond connecting the exposed first conductive trace of the first plurality of conductive traces to the exposed first conductive trace of the second plurality of conductive traces; 25. The device of claim 24, comprising: the butt joint forming a solder bridge connecting the exposed first conductive trace of the first plurality of conductive traces to the exposed first conductive trace of the second plurality of conductive traces; 25. The device of claim 24, comprising: 25. The device of Claim 24, further comprising a first metal block fixed to and in thermal contact with said first electromagnetic shielding layer and said third electromagnetic shielding layer. 28. The device of Claim 27, further comprising a second metal block fixed to and in thermal contact with said second electromagnetic shielding layer and said fourth electromagnetic shielding layer. a cryostat comprising a first stage configured to be maintained within a first temperature range;
a quantum information processing system in said first stage;
a flexible wire in the first stage and coupled to the quantum information processing system, the flexible wire comprising:
an elongated flexible substrate;
a plurality of conductive traces arranged in an array on a first side of the elongated flexible substrate;
an electromagnetic shielding layer on a second side of said elongated flexible substrate, said second side opposite said first side;
The elongated flexible substrate extends between the first conductive trace and the second conductive trace such that the electromagnetic shielding layer provides electromagnetic shielding between the first conductive trace and the second conductive trace. A system comprising folding regions between traces. a cryostat comprising a first stage configured to be maintained within a first temperature range;
a quantum information processing system in said first stage;
a flexible wire in the first stage and coupled to the quantum information processing system, the flexible wire comprising:
a first elongate flexible layer;
a second elongated flexible layer joined to the first elongated flexible layer;
a plurality of conductive traces disposed at a bond interface between the first elongated flexible layer and the second elongated flexible layer;
a first electromagnetic shielding layer on a major surface of the first elongated flexible layer;
a second electromagnetic shielding layer on a major surface of the second elongated flexible layer;
a via extending through the first elongated flexible layer, the via including a superconductor via contact.

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