JP2022130335A - Semiconductor processing system using in situ electrical bias - Google Patents

Abstract

To provide a semiconductor processing system using in situ electrical bias.SOLUTION: A system for processing a semiconductor wafer includes a processing chamber, a heat source, a substrate holder configured to expose the semiconductor wafer to the heat source, a first electrode configured to be removably coupled to a first main surface on the semiconductor wafer, and a second electrode coupled to the substrate holder. The first electrode and the second electrode together are configured to apply an electric field to the semiconductor wafer.SELECTED DRAWING: Figure 7A

Description

(Cross reference to related applications)
This application is a continuation-in-part of U.S. Nonprovisional Patent Application No. 16/841,342, filed April 6, 2020, which application is incorporated herein by reference.

(Technical field)
The present invention relates generally to semiconductor processing systems and methods, and in particular embodiments to semiconductor processing systems using in-situ electrical bias.

In general, semiconductor integrated circuits (ICs) are manufactured by sequentially depositing layers of materials (e.g., dielectrics, metals, semiconductors, etc.) on a semiconductor substrate and patterning the layers using photolithography and etching to form circuit components. (eg, transistors and capacitors) and interconnect elements (eg, lines, contacts, and vias). Its minimum feature size is being regularly shrunk with innovations such as immersion lithography and multi-patterning, reducing cost by increasing packing density. A smaller component footprint can be enhanced by increasing component power per unit area. For example, the drive current of a transistor or the stored charge density of a capacitor per unit width can be improved by using a thinner gate dielectric or a thinner capacitor dielectric, respectively.

However, the benefits of miniaturization come at some cost, which may have to be addressed in process complexity, circuit speed, and standby power consumption. The scaling trend toward narrower line widths and reduced spacing between conductors and electrodes has performance tradeoffs. Some of these tradeoffs can be mitigated by using new materials. For example, ruthenium and cobalt (instead of tungsten and copper) and fluorosilicate glasses and carbon-doped oxides have been shown to increase IR degradation and RC delay in interconnect systems due to higher line and via resistances and increased interline capacitance. can be mitigated by using metals such as low-k intermetal dielectrics (IMDs). Reducing the source-drain spacing of transistors and making gate dielectrics or capacitor dielectrics thinner can increase standby leakage. This problem can be alleviated by using high-k or ferroelectric dielectric materials.

Incorporating new materials requires further innovation to better exploit the advantages offered by their use in ICs.

According to an embodiment of the present invention, a system is provided for processing a semiconductor wafer, the system comprising a processing chamber, a heat source, a substrate holder configured to expose the semiconductor wafer to the heat source, and a semiconductor wafer. a first electrode configured to be removably coupled to the first major surface and a second electrode coupled to the substrate holder, the first electrode and the second electrode together , configured to apply an electric field to the semiconductor wafer.

According to an embodiment of the present invention, a system is provided for processing semiconductor wafers, the system includes a processing chamber, a heat source, a substrate holder configured to expose a plurality of semiconductor wafers to the heat source, and a plurality of a first bus including a first plurality of electrodes for contacting a first side of each of the semiconductor wafers of the semiconductor wafer; a second plurality of electrodes for contacting a second side of each of the plurality of semiconductor wafers; and a second bus including electrodes, the first bus and the second bus being together configured to apply an electric field to each of the plurality of semiconductor wafers.

According to embodiments of the present invention, a rapid thermal processing (RTP) system for processing semiconductor wafers is provided, the system comprising an RTP chamber, a substrate holder configured to support a substrate, and a substrate supported by the substrate holder. and a first electrode configured to be removably coupled to the first side of the substrate and coupled to the first potential node. and a first electrode and a second electrode configured to be removably coupled to an opposite second side of the substrate, the second electrode being coupled to a second potential node; and an electrode, the first electrode and the second electrode together being configured to apply an electric field through the substrate.

For a more detailed understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings below.
FIG. 4 illustrates a cross-sectional view of a processing chamber of an electric field annealer, in accordance with embodiments of the present invention; FIG. 4 shows a cross-sectional view of a processing chamber of an electric field annealer, according to an alternative embodiment of the present invention; FIG. 4 shows a perspective view of a load rail for an electric field annealer, in accordance with embodiments of the present invention. Figure 3 is an enlarged perspective view of a detail of the perspective view shown in Figure 2; FIG. 4 shows a perspective view of a load rail for an electric field annealer, in accordance with embodiments of the present invention. Figure 3 is an enlarged perspective view of a detail of the perspective view shown in Figure 2; Figure 3 is an enlarged perspective view from a different orientation of the detail of the perspective view shown in Figure 2; FIG. 4 illustrates a cross-sectional view of various semiconductor wafers positioned within a processing chamber of an electric field annealer, in accordance with embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of various semiconductor wafers positioned within a processing chamber of an electric field annealer, in accordance with embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of various semiconductor wafers positioned within a processing chamber of an electric field annealer, in accordance with embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of an electric field anneal configuration comprising a single wafer electric field anneal processing chamber using conductive heat transfer from a heat source, in accordance with embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of an electric field anneal configuration comprising a single wafer electric field anneal processing chamber using conductive heat transfer from a heat source, in accordance with embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of an electric field anneal configuration comprising a single wafer electric field anneal processing chamber using radiative heat transfer from a heat source, in accordance with embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of an electric field anneal configuration comprising a single wafer electric field anneal processing chamber using radiative heat transfer from a heat source, in accordance with embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of an electric field anneal configuration comprising a single wafer electric field anneal processing chamber using radiative heat transfer from a heat source, in accordance with embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of an electric field anneal configuration comprising a single wafer electric field anneal processing chamber using radiative heat transfer from a heat source, in accordance with embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of an electric field anneal configuration comprising a single wafer electric field anneal processing chamber using convective heat transfer from a heat source, in accordance with embodiments of the present invention. FIG. 2 illustrates a cross-sectional view of an electric field anneal configuration comprising a multi-wafer electric field anneal processing chamber, in accordance with an embodiment of the present invention. FIG. 2 illustrates a cross-sectional view of an electric field anneal configuration comprising a multi-wafer electric field anneal processing chamber, in accordance with an embodiment of the present invention. FIG. 2 illustrates a cross-sectional view of an electric field anneal configuration comprising a multi-wafer electric field anneal processing chamber, in accordance with an embodiment of the present invention. FIG. 3 illustrates a cross-sectional view of a cluster tool with an electric field annealing module, according to embodiments of the invention. FIG. 3 illustrates a cross-sectional view of a cluster tool with an electric field annealing module, according to embodiments of the invention. FIG. 3 illustrates a cross-sectional view of a cluster tool with an electric field annealing module, according to embodiments of the invention. FIG. 3 illustrates a cross-sectional view of a cluster tool with an electric field annealing module, according to embodiments of the invention.

The present disclosure describes an apparatus and method for processing a semiconductor wafer while an electrical bias voltage is applied across two conductive layers of the wafer during processing. The bias is applied through an electrode in direct electrical contact with the wafer and connected to a power supply located outside the processing chamber. In this document, the annealing process performed simultaneously with an electrical bias is referred to as electric field anneal, and the processing equipment used to perform electric field anneal is referred to as electric field annealer. A processing chamber may be referred to as an electric field annealing chamber. In an exemplary embodiment, an electrical bias is used to subject the dielectric film in the wafer to a DC electric field (electric field) of desired magnitude during a post-deposition anneal (PDA) process step.

Some manufacturing process flows, including the fabrication of ferroelectric dielectric-based electronic components such as metal oxide semiconductor field effect transistors (MOSFETs) and/or capacitors, use electric field PDAs, as described below. can be advantageous. Process steps used to form the ferroelectric layer include ferroelectric oxides, such as doped hafnium oxide, or doped hafnium zirconate, or perovskite oxides such as barium strontium titanate, or Depositing Bismuth may be included. A number of dopants such as La, Al, Si, Sr, Gd, Y have been shown to improve ferroelectric behavior by distorting the crystal structure. However, in the case of _HfO2 , _HfAlOx , or _HfZrOx , multiple phases are possible. In these materials, post-deposition annealing (PDA) conditions play an important role in introducing the desired non-centrosymmetric orthorhombic phase with ferroelectric behavior. A PDA step called ferroelectric annealing (FEA) can transform the deposited hafnium oxide layer into a stable or metastable polycrystalline ferroelectric hafnium oxide layer. The fabrication flow of ICs containing electronic components using hafnium oxide-based ferroelectric dielectrics typically includes an electrical cycling step, referred to herein as wake-up cycling, to obtain stable ferroelectric properties. included. In embodiments of the present disclosure, ferroelectric MOSFETs (FE-FETs) and ferroelectric capacitors can be constructed using ferroelectric dielectrics, including, for example, hafnium oxide, where crystallization During FEA, the dielectric is exposed to the applied DC electric field described above using apparatus and methods described in more detail below. The electric field FEA technique used in exemplary embodiments can provide the advantage of shortening and, in some embodiments, can eliminate wake-up cycling. Wake-up effects are described in more detail below. It is believed that the electric field FEA techniques described using various embodiments of the present disclosure can provide similar benefits when using materials other than hafnium oxide-based materials to form ferroelectric layers. be understood.

A dielectric material can be polarized by an electric field (E). The electric polarization vector (P) in response to the electric field is generally a function of the electric field E and is approximately linear and symmetric for centrosymmetric dielectrics. A centrosymmetric dielectric is nonferroelectric (ie, P=0 at E=0). However, some non-centrosymmetric dielectrics are ferroelectric, ie exhibit spontaneous or remnant polarization, P=P _R ≠0 at E=0, called remnant polarization (P _R ). In order to force P to zero in a ferroelectric dielectric, it is necessary to apply a forcing electric field ( _Ec ) of opposite polarity. The P versus E curve of ferroelectrics is nonlinear and has a nearly symmetrical hysteresis loop. As known to those skilled in the art, some ferroelectric films, such as hafnium oxide-based ferroelectric thin films, exhibit wake-up effects and were fabricated using conventional processing (no field annealing). ^The pristine film exhibits a stable, wider hysteresis loop ⁽ more P _R ) has a pinched hysteresis curve (small P _R ). Normally, all ferroelectric components that make up the original dielectric film with unstable P _R need to be stabilized by wake-up cycling in order for the respective circuit to function as designed. be. Accordingly, the innovative electric field annealing techniques described in this disclosure may provide significant advantages by reducing the number of wake-up cycles and, in some embodiments, eliminating the wake-up cycling step. can be recognized.

The presence of hysteresis in the P vs. E characteristic allows ferroelectric capacitors to be used as non-volatile memory (NVM) elements. For example, forcing a ferroelectric capacitor into either the top or bottom branch of a P vs. E hysteresis loop with a high positive or negative bias voltage corresponding to the corresponding state of high positive or negative polarization, respectively. can store a binary logic state of either '1' or '0'. After the bias is removed (E=0), some of the polarization is remnant polarization +PR or _−P , depending on whether the ferroelectric capacitor was forced into the upper or lower branch of the P vs. E hysteresis loop. Retained as _R. Since the maximum displacement current (corresponding to the maximum slope of P versus E) in each branch of the hysteresis curve occurs with opposite polarity, for example, by sensing the capacitor current in response to a voltage ramp of a given polarity, Stored information can be retrieved. As can be seen from the data storage and retrieval mechanisms described above, due to the criticality of stable and high PR, the wake-up cycling step usually involves hafnium oxide-based ferroelectric _NVMs formed without the above electric field FEA. Executed during manufacture of the IC. However, use of the electric field annealer and electric field FEA described in this disclosure reduces the number of wake-up cycles and, in some embodiments, eliminates the wake-up cycling step from the fabrication flow, thus reducing the oxidation It can provide the advantage of reducing the cost of hafnium-based ferroelectric NVM.

Ferroelectrics can be used in forming the gate dielectric stack of FE-FETs. If the remnant polarization of the gate dielectric stack is sufficiently high, the transistor, like a ferroelectric capacitor, will retain its state once programmed, turning it on or off even after the programming voltage is removed. can be left Such FE-FETs can also be used to store digital information in NVM cells. As described above in the context of hafnium oxide-based ferroelectric capacitor NVMs, the manufacturing cost of hafnium oxide-based ferroelectric FE-FET NVMs can be reduced by using an innovative electric field annealer and electric field FEA.

FE-FETs can offer several advantages over conventional (ie, non-ferroelectric) MOSFETs when used in digital logic or analog circuits. Gate dielectric stacks of FE-FETs used in digital logic and/or analog circuits include ferroelectric and non-ferroelectric thin films. When used in circuits, e.g., as digital switches, the ferroelectric portion of the gate dielectric stack provides dynamic capacitance, which under certain bias sweep conditions (e.g., sweep speed or frequency). Below, changes in the polarization of the ferroelectric can lead to voltage snapback. This snapback can result in a higher FE-FET I _ON /I _OFF ratio below the desired steeper threshold. In this context, FE-FETs are commonly referred to as negative capacitance field effect transistors (NCFETs). Here it is more precisely referred to as a steep slope strong field effect transistor (SSFEFET). However, the ferroelectric properties (eg, P _R ) and film thickness of the gate dielectric stack may need to be adjusted appropriately to achieve the IV and CV curves of the transistor without hysteresis. As known to those skilled in the art, IV and CV curves without hysteresis suggest stable transistor operation, but the presence of hysteresis can lead to circuit instability and unintended electrical oscillations. There is Considering circuit stability, it will be appreciated that P _R must remain stable and within the design window for the SSFEFET to provide the expected circuit benefits without destabilizing the circuit. Thus, a SSFEFET fabrication flow that does not include electric field FEA can incorporate a wake-up cycling step, while using the inventive electric field annealing techniques described in this disclosure reduces wake-up cycles. Thus, achieving stable ferroelectric properties, in some embodiments without a wake-up cycle, can provide cost savings advantages.

In this disclosure, first, the electric field annealing technique is illustrated in FIG. 1A along with the alternative embodiment of FIG. 1B. It is explained using a figure. The electric field annealer is further described with reference to various perspective views of the electric field annealer load rail shown in FIGS. For electrical connections during electric field FEA of gate dielectric layers of FE-FET/SSFEFET and/or MOS ferroelectric capacitors, planar bulk complementary MOS (CMOS) and silicon-on-insulator (CMOS) are shown in FIGS. 6A and 6B, respectively. SOI) A description will be given with reference to a cross-sectional view of a CMOS semiconductor wafer. In addition to MOS capacitors, capacitor components within ICs, commonly referred to as MIM capacitors, can be formed using metal layers for both the top and bottom electrodes of the capacitor. In this disclosure, abbreviations distinguish between nonferroelectric and ferroelectric insulators, nonferroelectric insulator being abbreviated as I and ferroelectric insulator being abbreviated as F. The electrical connections made to the electrodes of the MFM capacitor during electric field FEA are described with reference to the cross-sectional view shown in FIG. 6C.

As described with reference to FIGS. 1A and 1B, electric field annealing is performed in a single wafer processing chamber (eg, processing chamber 225) or a multiple wafer (or batch) processing chamber (eg, processing chamber 226). can be Semiconductor wafer 50 is heated to a desired temperature using a thermal processing system (e.g., thermal processing systems 235 and 236) that includes a heat source, a temperature sensor, and a temperature controller that regulates the power supplied to the heat source. maintained at Electric field annealers are used in ovens with slow temperature rises and stabilization times on the order of minutes, or in rapid ovens where semiconductor wafers are rapidly heated to high temperatures, often within seconds or milliseconds, and sometimes microseconds. It may consist of a heat source suitable for thermal processing (RTP). RTP technology can reduce processing time and offers many advantages over electric field annealers configured for single wafer processing. However, electric field annealers configured in either single or multiple wafer processing chambers may be configured for RTP. Various electric field annealer embodiments may be configured in various thermal processing systems with various heat sources oriented in various ways relative to the semiconductor wafer, as further described below.

As also described with reference to FIGS. 1A and 1B, semiconductor wafer 50 is electrically biased during electric field annealing in a single wafer or multiple wafer processing chamber. Electrical biasing causes the electrodes of the semiconductor wafer 50 and the conductive portions of the processing chambers (e.g., processing chambers 225 and 226) to be connected to an electrical source outside the chamber, such as a DC power supply 130, a voltmeter 150, and a reference potential called ground. It can be provided and monitored by electrically coupling the component. In various embodiments, the electric field annealer can be configured with different electrical connections, as further described below.

7A-7B, 8A-8D, and 9 illustrate various configurations of electric field annealers configured for single wafer processing. 10A-10C show configurations of electric field annealers suitable for batch processing.

In various embodiments, the thermal processing system uses conductive, radiative, or convective heat transfer mechanisms, or a combination of these mechanisms, to achieve the desired temperature of the semiconductor wafer during electric field annealing. Figures 7A-7B illustrate an embodiment using conductive heat transfer from a hotplate heat source. Embodiments configured to use radiant heat transfer from various types of heat sources are shown in FIGS. 8A-8D and convective heating is described with reference to FIG.

In various embodiments, various configurations are possible for applying the electric field and making electrical connections for monitoring the potential on the semiconductor wafer. 10A-10C are configured for batch processing with different electrical connection schemes for electrically coupling the semiconductor wafer 50 and various conductive portions of the processing chamber to the DC power supply 130, voltmeter 150, and ground. 3 shows three exemplary embodiments.

An electric field anneal processing chamber may be a stand-alone processing chamber, a processing chamber configured to perform electric field anneal in conjunction with several other processes (e.g., deposition) performed either simultaneously or sequentially, or other chambers. It may be an electric field anneal chamber in a cluster configuration of a semiconductor processing system comprising: Some examples of semiconductor processing systems that include clusters of processing modules, called cluster tools, are described with reference to FIGS. 11A-11D.

Stacks of various combinations of material layers can be formed for use in ferroelectric electronic devices (eg, transistors and capacitors). The stack may include ferroelectric layers in addition to non-ferroelectric dielectric layers, metal layers, and semiconductors. Examples include the following stacks (listing layers from top to bottom): metal-ferroelectric-metal (MFM), metal-ferroelectric-insulator-metal (MFIM), metal-ferroelectric Body-Insulator-Semiconductor (MFIS), Metal-Ferroelectric-Metal-Semiconductor (MFMS), Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS), Semiconductor-Ferroelectric-Semiconductor (SFS), and semiconductor-ferroelectric-insulator-semiconductor (SFIS). In this disclosure, exemplary stacks can be MFIS (eg, in FEFET/SSFEFET transistors) or MFM (eg, in capacitors with top and bottom metal electrodes).

FIG. 1A schematically shows a cross-sectional view of a semiconductor wafer 50 placed on a substrate holder 10 inside an electric field annealing process chamber 225, which is an annealer equipped to perform electric field annealing. Processing chamber 225 includes a thermal processing system 235 designed to thermally process wafers disposed within processing chamber 225 . In various embodiments, the thermal processing system 235 controls heating and cooling elements by using lamps, resistive elements, and others placed at various locations inside or outside the processing chamber 225 to A temperature controller is provided to maintain the desired temperature of the semiconductor wafer 50 within the processing chamber 225 . Some thermal processing systems used in embodiments of electric field annealing chambers are described further below.

Semiconductor wafer 50 comprises a substrate 20 , a MOS dielectric layer 30 formed over substrate 20 , and a conductive top electrode layer 40 formed over MOS dielectric layer 30 .

As shown schematically in FIG. 1A, the first field annealer electrode is in physical and electrical contact with the conductive top electrode layer 40 . The first field annealer electrode may comprise a conductive material that is immune to high temperature processing. In one embodiment, the first field annealer electrode may comprise tungsten. The first electric field annealer electrode is connected to a first terminal of a DC power supply 130 using a suitable conductor (e.g., tungsten) primary wiring 110 that can be heated to high temperatures during annealing without damage. An electrode 211 (eg, a tungsten ribbon) is provided. The ribbon shape of the primary electrode 211 provides a spring-like action that prevents slippage and helps maintain good physical contact with the surface of the semiconductor wafer 50 as it is heated during the annealing process. . The electrical potential of the conductive top electrode layer 40 is applied by the monitoring line 112 (similar to the primary line 110) to another monitoring electrode 212, e.g., another tungsten ribbon, placed in contact with the conductive top electrode layer 40. It can optionally be monitored using a connected voltmeter 150 . The two electrodes are electrically shorted together by a conductive top electrode layer 40 . Primary electrode 211 and monitoring electrode 212 may collectively be referred to as first field annealer electrode 210 . Primary wiring 110 and monitoring wiring 112 may collectively be referred to as two wirings 115 .

In the exemplary embodiment shown in FIG. 1A, the surface of substrate holder 10 that is in physical contact with the backside of semiconductor wafer 50 is used as the second electric field annealer electrode. The surface of the substrate holder 10 is coated with a suitable electrically conductive material, such as a silicon-based, carbon-based, silicon and carbon composite-based, or metal nitride-based coating to provide suitable electrical conductivity for use as an electrode at annealing temperatures. surface can be obtained. The backside, and the portion of the semiconductor wafer 50 adjacent to the backside, which may be a conductive material such as n-type or p-type doped silicon or germanium, is in electrical contact with the surface of the substrate holder 10 . good too. In some embodiments, a backside etch can be used to expose a conductive surface on the backside in order to establish electrical contact between the backside of the semiconductor wafer 50 and the surface of the substrate holder 10 .

As shown schematically in FIG. 1A, the front surface of the substrate holder 10, and thus the back surface of the semiconductor wafer 50, can be connected to a reference potential called ground, indicated as GND in FIG. 1A. A ground connection may be established using secondary wiring 113 similar to primary wiring 110 . In this embodiment, secondary wiring 113 is electrically connected to the ground wiring that connects the conductive portion of the main structure of the device to system ground. A second terminal of DC power supply 130 is also connected to ground (GND) for applying a bias voltage across semiconductor wafer 50 . As understood by those skilled in the art and further described below, the voltage drop across the two terminals of the DC power supply achieves an electric field in the MOS dielectric layer 30 having the desired polarity and field strength within the desired range. can be adjusted to In various embodiments, DC power supply 130 may be configured to provide a suitable voltage, such as 1V-100V, and in one embodiment 3V-10V.

The bias applied during annealing can be a fixed voltage or a time-varying voltage, the magnitude and waveform of which can vary widely depending on the material, layer thickness, annealing conditions, and specific device application. Please note that The above DC bias voltages are for illustration only and should not be construed as limiting. Time-varying voltage waveforms may include pulsed DC, alternating pulses, sine waves, sawtooth waves, and the like. It is further noted that the bias applied can be referenced to a common ground potential, some other fixed reference potential, a controlled variable reference potential, a time varying potential, or a floating node potential.

Although the embodiment of FIG. 1A shows a single semiconductor wafer 50 inside processing chamber 225, it will be appreciated that multiple wafers, including dummy wafers, may be placed within an appropriately designed processing chamber. . The electric field annealer electrodes and electrical connections of FIG. 1A are shown configured for single wafer processing. However, the configuration of the electric field annealer may be modified to anneal batches of semiconductor wafers. An exemplary embodiment suitable for batch processing is shown in FIG. 1B.

In FIG. 1B, a plurality of semiconductor wafers 50 are stacked horizontally on a slotted substrate holder 14 comprising an insulator (eg, a ceramic insulator) that is immune to high temperature processing. The insulating material prevents the substrate holder 14 from creating an electrical short between the conductive top and back sides of the semiconductor wafer 50 . The stacked wafers are shown loaded inside the processing chamber 226 of the electric field annealer. Located inside the processing chamber 226 are two conductive buses, a first conductive bus 108 and a second conductive bus 109, secured above and below the slotted substrate holder 14, respectively. . The temperature inside processing chamber 226 may be controlled by thermal processing system 236 .

The conductive top surface of each wafer is shown electrically connected to the first conductive bus 108 by a primary electrode 215 similar to primary electrode 211 of FIG. 1A. As shown in FIG. 1B, connections between the first conductive busses 108 and the primary electrodes 215 can be established using connecting wires that pass through openings in the slotted substrate holder 14 . In this embodiment, the first electric field annealer electrode includes primary electrode 215 and first conductive bus 108 . The first field annealer electrode is connected to a DC power supply 130 using primary wiring 110, similar to FIG. 1A. The conductive backside of each wafer can be connected to the second conductive bus 109 using secondary electrodes 216 and connecting wires (similar to the topside). In this embodiment, the second field annealer electrodes, including secondary electrode 216 and second conductive bus 109 are connected to GND using secondary trace 114 . The potential on the top surface of the wafer can be monitored by connecting the first conductive bus 108 to a voltmeter 150 using a monitor wire 112, as shown in FIG. 1B.

The electric field annealer described above with reference to FIG. 1B is suitable for batch processing wafers arranged in horizontal stacks. The design of processing chamber 226 may be modified to provide a similar electric field annealer, and semiconductor wafers 50 may be stacked vertically instead of horizontally.

Various configurations are possible for making electrical connections that bias a semiconductor wafer in a processing chamber during electric field anneals. Several embodiments illustrating some of these possibilities are further described below.

FIG. 2 shows a perspective view of an electric field annealer load rail 100, in accordance with an embodiment of the present invention. The load rail 100 can be used to introduce the wafer into the processing chamber 225 of the electric field annealer. The wafer is first loaded into the slot of the substrate holder attached to the load rail stage (Fig. 2). Electrodes are then positioned to make proper electrical contact to the/each wafer. A load rail stage is then used to position the wafer in the substrate holder into the heating zone of the oven.

In FIG. 2, two wires 115 (similar to primary wire 110 and monitor wire 112 in FIG. 1A) are shown leading to region B1 (indicated by the dashed circle in FIG. 2). Region B1 includes a first field annealer electrode 210 comprising two tungsten ribbons in contact with conductive top electrode layer 40 of semiconductor wafer 50 . As noted above, the ribbon shape helps maintain good physical contact with the semiconductor wafer 50 during the annealing process. A first field annealer electrode 210 is attached to a portion of two traces 115 that are exposed metal (eg, exposed tungsten). Other portions of the two wires 115 are electrically isolated from other conductive portions of the device by an insulating material, such as insulating ceramic beads. The insulated portion of the two traces 115 is called the insulated conductive trace 310 . FIG. 3 shows an insulated conductive trace 310 (eg, insulated using ceramic beads) in an enlarged perspective view of region D1 indicated by the dashed circle in FIG.

As noted above, the first of the two wires 115 passes through a power feedthrough 120 (shown in FIG. 2) to apply an electric field to a dielectric layer, such as the MOS dielectric layer 30 of the semiconductor wafer 50. It may be connected to a DC power supply 130 used to provide power. As shown schematically in FIG. 2, the other of the two wires 115 (similar to the monitor wire 112 of FIG. 1A) is for monitoring the potential of the conductive top electrode layer 40 of the semiconductor wafer 50. , may be connected to the first electric field annealer electrode 210 at one end and to the voltmeter 150 at the opposite end. Conductive portions of the main structure of the device, including the substrate holder (eg, substrate holder 10 of FIG. 1A) in contact with the backside of semiconductor wafer 50, are connected to ground GND by ground trace 140. FIG. The substrate holder for semiconductor wafer 50 is further described below with reference to FIG. 5A, which shows an enlarged perspective view of area B1 (indicated by the dashed circle in FIG. 2).

A perspective view of the loadrail 100 from a different angle, indicated by arrow C in FIG. 2, is shown in FIG. FIG. 4 shows the conductors of the two wires 115 exposed by removing the ceramic beads from the two respective insulated conductive wires 310 passing through the two respective openings. Two wires 115 connect to two tungsten ribbons of the first field annealer electrode 210 that are in contact with the top surface of the semiconductor wafer 50 . These two wires 115 in FIG. 4 are the same wires shown in FIG. 2 extending from the first field annealer electrode 210 to the DC power supply 130 and the voltmeter 150 respectively. In the perspective view of FIG. 4, the first electric field annealer electrode 210 is located in region C1 (indicated by the dashed circle). In the perspective view of FIG. 2, the first electric field annealer electrode 210 is placed in region B1.

Regions B1 of FIG. 2 and C1 of FIG. 4 are shown in greater detail in the enlarged perspective views shown in FIGS. 5A and 5B, respectively. The perspective view of FIG. 5A more clearly shows the connection between one of the two wires 115 and the first field annealer electrode 210. FIG. The angle at which the perspective view of FIG. 5B is shown provides a clearer view of the tungsten ribbons of first field annealer electrode 210 in physical contact with conductive top electrode layer 40 of semiconductor wafer 50 . Semiconductor wafer 50 in FIGS. 5A and 5B is shown supported from below by support plate 230 . Support plate 230 is part of the slotted substrate holder shown in FIGS. 2 and 3 and can also be an exemplary embodiment of substrate holder 10 of FIG. 1A. The surface of support plate 230 may be metallic, including, for example, stainless steel, and may be in physical and electrical contact with the conductive backside of semiconductor wafer 50 . In one embodiment, support plate 230 may be in the form of a ring. The ring shape supports the outer diameter of the wafer but exposes most of the backside to the heat source. Support plate 230 may include a conductive material connected to ground GND.

FIG. 5A shows some optional buffer wafers 240 that help achieve a more uniform temperature profile across the surface of semiconductor wafer 50 during annealing. Optional buffer wafer 240 is not shown in FIGS. 4 and 5B for clarity. As shown in FIG. 5B, an insulating ceramic tab 250 is formed between the semiconductor wafer 50 and the support to reduce the possibility of inadvertently creating an undesirable electrical short between the semiconductor wafer 50 and the conductive surface of the electric field annealer. It can be arranged along a carrier rail near the edge of plate 230 .

The DC bias voltage to which the DC power supply 130 can be set during the electric field PDA generally depends not only on the thickness t _OX of the target dielectric layer (eg, the MOS dielectric layer 30 of FIG. 1A) on which the electric field PDA is performed, but also on It also depends on the properties of the other layers, such as the material used in the conductive top electrode layer 40, and the materials, thicknesses, and properties of the layers below the target dielectric layer, as explained below. In some embodiments, the DC bias voltage of DC power supply 130 may be controlled to remain constant during field anneal.

6A and 6B show cross-sectional views of semiconductor wafer 50 during the electric field annealing step of planar bulk CMOS and planar SOI CMOS flows, respectively. The electric field anneal step in the exemplary embodiment shown in FIGS. 6A and 6B is an electric field ferroelectric anneal, FEA, performed after the conductive top electrode layer 40 is formed over the MOS dielectric layer 30. . Conductive top electrode layer 40 can be used as the gate electrode of a FE-FET/SSFEFET or a ferroelectric MOS capacitor, and can include one or more conductive materials such as TiN, TaN, W, metal alloys, and the like.

6A and 6B, fabricating ferroelectric components (eg, FE-FET/SSFEFETs and ferroelectric MOS capacitors) using MOS dielectric layer 30 using gate-first process integration. can be done. However, those skilled in the art will appreciate that the innovative aspects of these embodiments are applicable to each ferroelectric component fabricated using gate-last (or replacement-gate) process integration methods. be understood.

In the exemplary embodiment shown in FIGS. 6A and 6B, MOS dielectric layer 30 comprises a doped amorphous hafnium oxide film and an interfacial dielectric film (e.g. oxide) adjacent to the surface of the semiconductor (e.g. silicon). silicon). The thickness t _OX of MOS dielectric layer 30 depends on the application and can vary from about 1 nm to about 100 nm. The annealing temperature can be adjusted so that the amorphous hafnium oxide crystallizes during annealing to form a polycrystalline hafnium oxide film. For example, electric field FEA can be performed at temperatures from about 200° C. to about 1200° C., eg, in an inert gas environment at low pressure. Temperatures below 200° C. may be insufficient to crystallize the amorphous layer, and temperatures above 1200° C. may change the properties of other layers formed during earlier processing steps. _The orthorhombic phase of hafnium oxide is ferroelectric, but the orthorhombic phase is unstable in pure HfO2, so pure amorphous HfO2 naturally exhibits _single crystal or cubic phase grains. can be converted to However, as known to those skilled in the art, the orthorhombic phase of _HfO2 can be stabilized by certain dopant atoms such as zirconium, silicon, or lanthanum atoms. Therefore, as the amorphous hafnium oxide film doped in the MOS dielectric layer 30 crystallizes, an orthorhombic phase of HfO ₂ forms and is stabilized by dopants within the metastable orthorhombic phase, which is ferroelectric. obtain. The electric field strength during electric field FEA can be adjusted from 1 MV/cm to about 100 MV/cm. An electric field that is too low may not provide sufficient benefit in reducing/eliminating wakeup cycling, while an electric field that is too high damages and/or reduces the lifetime of the MOS dielectric layer 30. may be allowed to do so. As will be further described below, the respective DC bias voltage settings of DC power supply 130 to provide the desired range of electric fields in MOS dielectric layer 30 are dependent on whether the process flow is for bulk CMOS or SOI CMOS fabrication. depends on what.

6A-6C, the layers of semiconductor wafer 50 upon which the layers specific for ferroelectric components are formed are collectively referred to as substrate 20. FIG. Thus, for a planar FE-FET/SSFEFET or ferroelectric MOS capacitor, shown in FIGS. 6A and 6B, substrate 20 includes all layers formed prior to forming MOS dielectric layer 30. FIG. For the MFM ferroelectric capacitor shown in FIG. 6C, substrate 20 includes all layers formed prior to forming MFM conductive bottom electrode layer 45 .

In the case of a planar FE-FET/SSFEFET or a ferroelectric MOS capacitor, the substrate 20 comprises a first semiconductor region 21 of a first conductivity type (eg p-type), a second conductivity type (eg n-type). ) and isolation regions called shallow trench isolation (STI) regions 25 that serve to electrically isolate adjacent electronic components. The electronic components can be in either of two semiconductor regions (first semiconductor region 21 and second semiconductor region 22). As known to those skilled in the art, the conductive top electrode layer 40 over the first semiconductor region 21 and the second semiconductor region 22 may comprise the same material formed by the same process or may be formed by separate processes. may include different materials formed by When using separate processes, various masking steps can be used to mask and expose the appropriate areas.

As shown in FIG. 6A, in bulk CMOS, a first semiconductor region 21 of a first conductivity type extends all the way to the backside of a semiconductor wafer 50 and a second semiconductor region 22 of a second conductivity type extends all the way to the backside of the semiconductor wafer 50. , extends to a depth to form a pn junction with the first semiconductor region 21 . A pn junction is commonly referred to as an n-well to p-well junction. In SOI CMOS, the first semiconductor region 21, the second semiconductor region 22, and the STI region 25 are an insulating region called a buried oxide (BOX) layer 15 comprising, for example, silicon oxide, as shown in FIG. 6B. terminated below by A semiconductor wafer having a BOX layer 15 can be manufactured using several methods, such as a separation by oxygen implantation (SIMOX) process, a wafer bonding process, e.g. Smart Cut technology, as known to those skilled in the art. . Doped semiconductor region 12 under BOX layer 15 extends all the way to the backside of semiconductor wafer 50 .

As described above with reference to FIGS. 1A and 2, the backside of the semiconductor wafer 50 and the second terminal of the DC power supply 130 are connected to ground GND, and the first terminal of the DC power supply is connected to the primary wiring 110. is used to connect to the primary electrode 211 of the first electric field annealer electrode. (For simplicity, monitoring electrode 212 and monitoring wiring 112 are not shown in FIGS. 6A-6C.) Primary electrode 211 shown in FIGS. and in physical and electrical contact with the conductive top electrode layer 40, similar to the detailed perspective view of FIG. 5B. Thus, the entire DC bias voltage supplied by DC power supply 130 is applied across conductive top electrode layer 40 and the backside of semiconductor wafer 50 .

Referring again to FIG. 6A, in bulk CMOS, the potential on the semiconductor side of MOS dielectric layer 30 is approximately the same as the potential on the backside of semiconductor wafer 50 in first semiconductor region 21 . Therefore, the voltage drop across MOS dielectric layer 30 is due to the DC bias voltage supplied by DC power supply 130 and the work function difference between first semiconductor region 21 and conductive top electrode layer 40 above this region. It is determined. However, in the second semiconductor region 22, the voltage drop across the n-well/p-well junction determines the voltage drop across the MOS dielectric layer 30 in determining the potential on the semiconductor side of the MOS dielectric layer 30. should be included when Therefore, it is advantageous to minimize the voltage drop across the n-well to p-well junction by selecting the polarity of the DC bias voltage supplied by DC power supply 130 such that the pn junction is forward biased. could be. In one embodiment, the DC bias voltage setting of DC power supply 130 during electric field FEA may be between about 3V and about 10V for a t _OX value of about 10 nm for MOS dielectric layer 30 . The DC bias voltage can vary greatly with materials, layer thicknesses, and annealing conditions. The above values are for illustration only and should not be construed as limiting.

Referring to FIG. 6B, in SOI CMOS, a significant portion of the DC bias voltage supplied by DC power supply 130 depends on the thickness ratio and dielectric constant ratio of MOS dielectric layer 30 and BOX layer 15 to BOX It can descend over layer 15 . Therefore, the DC bias voltage used for electric field FEA in SOI CMOS process flows may need to be increased relative to corresponding values in bulk CMOS process flows.

More advanced CMOS ICs may use a three-dimensional MOS structure, called a FinFET structure, in which a gate and gate dielectric generally wrap around three sides of a thin, long semiconductor fin protruding from a semiconductor substrate. I'm in. The electrical connections to the FE-FET/SSFEFET and MOS ferroelectric capacitor during electric field FEA described with reference to the planar MOS structure shown in FIGS. can be adapted to perform field FEA of

FIG. 6C shows an electric field FEA step performed in a process flow involving the fabrication of MFM ferroelectric capacitors. The MFM ferroelectric capacitor structure in FIG. 6C comprises a doped hafnium oxide based ferroelectric dielectric layer 35 sandwiched between a conductive top electrode layer 40 and a conductive bottom electrode layer 45 . Primary electrode 211 , shown in contact with conductive top electrode layer 40 , is connected to a first terminal of DC power supply 130 (not shown) using primary wiring 110 . As with the semiconductor wafer 50 of FIGS. 6A and 6B, the backside of the semiconductor wafer 50 and the second terminal of the DC power supply 130 are connected to GND. However, as will be explained below, the excessively high cumulative thickness of the dielectric layers within substrate 20 effectively prevents conductive bottom electrode layer 45 from being electrically disconnected from the backside GND connection of semiconductor wafer 50 of FIG. 6C. If isolated, these connections alone may not be sufficient to produce a sufficiently high electric field in the ferroelectric dielectric layer 35 of the MFM capacitor.

The MFM capacitor layers, including the conductive bottom electrode layer 45, are generally formed during the Back End of Line (BEOL) of the IC manufacturing flow. Since the substrate 20 of FIG. 6C comprises all layers formed below the conductive bottom electrode layer 45, a relatively thick interlevel dielectric (ILD) layer and metal physically located over the conductive semiconductor. It may include inter-dielectric (IMD) layers, as well as gate layers of MOSFETs. Therefore, unless the conductive bottom electrode layer 45 is connected to the conductive semiconductor and the gate layer of the MOSFET by vias and contacts in the intermediate stages of fabrication shown in FIG. The electrical coupling between the electrode layer 45 may be too weak to generate a sufficiently high electric field in the ferroelectric dielectric layer 35 of the MFM capacitor. In such embodiments, the substrate holder that is in electrical contact with the backside of the semiconductor wafer 50, such as the substrate holder 10 of FIG. 1A or the support plate 230 of FIG. 5A, is not an effective second electric field annealer electrode. Sometimes. In such cases, additional processing can be used to create an effective second field annealer electrode connection, as described below with reference to FIG. 6C.

In IC designs where the conductive bottom electrode layer 45 is electrically isolated from the backside of the semiconductor wafer 50 at intermediate stages in the process flow where electric field FEA is desired, a masking step may be used, as shown in FIG. The ferroelectric dielectric layer 35 and the conductive top electrode layer 40 of the MFM capacitor can be patterned to expose a portion of the conductive bottom electrode layer 45 . The exposed area of conductive bottom electrode layer 45 may be, for example, in the shape of a ring along the edge of semiconductor wafer 50 . An additional secondary electrode 214 (similar in construction to the electrode of the first field annealer electrode 210 shown in the cross-sectional view of FIG. 1A and the detailed perspective views of FIGS. 5A and 5B) It can be placed in physical and electrical contact with the exposed portions of electrode layer 45 . Secondary electrode 214, which is a direct electrical connection to conductive bottom electrode layer 45, can be effectively a second field annealer electrode connection. As shown in FIG. 6C, additional secondary electrodes 214 may be connected to GND using secondary traces 114 (similar to primary traces 110). The overall DC bias voltage is therefore dropped across the ferroelectric dielectric layer 35 of the MFM capacitor. In one embodiment, the DC bias voltage setting for the DC power supply 130 during electric field FEA may be from about 3V to about 10V for a t _OX value of about 10 nm for the ferroelectric dielectric layer 35 of the MFM capacitor. In another embodiment, the DC bias voltage setting can be from about 0.5V to about 3V.

Although the description of the electric field anneal embodiments refers to applying a DC voltage to the semiconductor wafer 50, in various embodiments the applied bias voltage is pulsed, cycled, or alternated during annealing. may be made In some embodiments, the DC bias voltage can be set to a fixed or variable potential other than GND to provide the desired bias voltage across the ferroelectric dielectric layer. For example, not all the electrodes generating the electric field may be connected to ground potential, or one of the electrodes may be connected to a floating potential node.

Various methods may exist for configuring the electric field anneal to perform the electric field anneal described above. Various embodiments of electric field annealer configurations are described with reference to FIGS. 7A-7B, 8A-8D, 9, and 10A-10C.

7A and 7B illustrate an electric field annealer configuration that heats semiconductor wafer 50 using conductive heat transfer. Conductive heat transfer is accomplished using a heated body in direct contact with semiconductor wafer 50 . Methods of conductive heat transfer that may be utilized include hotplates as the heat source, such as ceramic hotplates, metal hotplates, and the like.

A semiconductor wafer 50 including a substrate 20, a MOS dielectric layer 30 formed over the substrate 20, and a conductive top electrode layer 40 formed over the MOS dielectric layer 30 was described above with reference to FIG. 1A. Like the configuration, it is located within the processing chamber 225 . In Figures 7A and 7B, a semiconductor wafer 50 is placed on a hotplate heat source that is also part of the substrate holder. DC power supply 130 and voltmeter 150 are connected to conductive top electrode layer 40 using primary electrode 211 and monitoring electrode 212, similar to the connections shown in FIG. 1A above.

In the electric field annealer configuration 701 shown in FIG. 7A, a semiconductor wafer 50 is placed on a hotplate 710 . The front surface of hot plate 710 is in physical contact with the back surface of semiconductor wafer 50 . The surface comprises a material that is a good electrical and thermal conductor, for example a coating comprising a metal or a metal-based compound such as titanium nitride, or a carbon-based coating.

In contrast, FIG. 7B shows a configuration 702 in which the electric field annealer may consist of a hotplate 720 with an electrically insulating but thermally conductive surface. Electrically and thermally conductive materials (e.g. metals such as stainless steel, or elements such as tungsten, copper, aluminum, silver, zinc, magnesium, nickel, titanium, tin, or alloys containing these elements, called ground plates) ) may be placed over the surface of the hot plate 720 and the semiconductor wafer 50 may be placed over the conductive plate 730 . The material of the conductive plate 730 can be selected to be thermally stable during the annealing process while not introducing contaminants into the process chamber. The surface of hotplate 720 may comprise a ceramic such as aluminum nitride, alumina, silicon nitride, or silicon carbide.

As shown in FIGS. 7A and 7B, in both configurations 701 and 702, the backside of semiconductor wafer 50 is electrically connected to a common ground (designated GND) using conductive traces. obtain. In some embodiments, conductive portions of chamber walls 227 may also be electrically coupled to a common ground.

In the configurations 701 and 702 shown in FIGS. 7A and 7B, the electric field annealer adjusts the temperature of the semiconductor wafer 50 via heat conduction between the backside of the semiconductor wafer 50 and the respective hotplate 710 or 720. can be done. Hotplates 710 and 720 are comprised of a thermal energy source represented schematically by heater 740 . In various embodiments, heater 740 may include a resistive or inductive heater or fluid flowing through a heat exchanger. Configurations that use conductive heat transfer from a hotplate, such as exemplary configurations 701 and 702, are generally used for relatively long anneals at moderate temperatures, such as 200° C.-600° C., in various embodiments. .

8A-8D illustrate electric field annealer configurations that use radiative heat transfer to transfer energy from a heat source to semiconductor wafer 50. FIG. Heat sources available for radiant heat transfer methods include insulated resistance wire heaters, heat plates containing ceramic coated resistors, broad spectrum infrared (IR) and ultraviolet (UV) lamp heaters, and monochromatic light emitting in the visible and UV ranges. Laser. The radiant heat source can be located at various locations inside or outside the processing chamber 225 away from the semiconductor wafer 50 . In some embodiments, semiconductor wafer 50 may be moved through a beam of radiation emitted from a heat source using a scanner.

Configurations 801, 802, and 803 (shown in FIGS. 8A, 8B, and 8C, respectively) use multiple heat sources to heat semiconductor wafer 50 from above and below using radiant heat transfer. Configuration 804 (shown in FIG. 8D) uses laser system 850 to provide laser beam 852 to heat semiconductor wafer 50 from its top surface. In configuration 804, semiconductor wafer 50 is scanned through laser beam 852 to expose the entire surface.

Exemplary embodiments of electric field annealer configurations 801 , 802 , 803 , and 804 have heat sources at locations inside processing chamber 225 . However, it will be appreciated that in some other embodiments the heat source may be located outside of the processing chamber 225 or attached to the chamber wall 227 .

In electric field annealer configurations 801 , 802 , 803 , and 804 , semiconductor wafer 50 may be placed on raised wafer support 810 that provides support along the perimeter of semiconductor wafer 50 . The raised wafer support 810 leaves most of the top and bottom surfaces of the semiconductor wafer 50 exposed to radiation emitted from heat sources located above and below the semiconductor wafer 50 .

Additionally, wafer support 810 can be used to make electrical contact to the backside of semiconductor wafer 50 . The backside of semiconductor wafer 50 can be electrically coupled to a common ground by providing a ground connection to wafer support 810, as shown in FIGS. 8A-8D. Good electrical contact is achieved, for example, by using a wafer support 810 that includes a metal or metal coating. Optional ground connections to chamber wall 227 and electrical coupling between semiconductor wafer 50 and DC power supply 130 and voltmeter 150 in configurations 801, 802, 803, and 804 are shown in FIGS. 7A and 7B. It can be similar to that described.

The heat sources positioned above and below semiconductor wafer 50 in electric field annealer configurations 801 (FIG. 8A) and 802 (FIG. 8B) comprise resistive heating elements. Configurations using resistive heating elements, such as exemplary configurations 801 and 802, generally have longer thermal time constants and can be used for moderate annealing temperatures, eg, 200°C-1000°C.

A resistive heating element 820 used in configuration 801 (FIG. 8A) includes mineral insulated (MI) cable 822 and cable support 824 . MI cables are semi-rigid, electrically resistive heating cables that contain electrically conductive wiring resistive elements that are electrically insulated using thermally conductive minerals (eg, magnesium oxide). Minerals can provide safe electrical insulation even at high annealing temperatures.

In the electric field annealer configuration 802 (FIG. 8B), the resistive heating element 830 comprises a graphite resistor coated with pyrolytic boron nitride (PBN) to achieve high temperature capability and extended heater life. High purity PBN coatings can provide electrical insulation, thermal stability, thermal shock resistance, and chemical inertness to graphite components.

FIG. 8C shows configuration 803 in which lamp heaters 840 are used to irradiate the top and bottom surfaces of semiconductor wafer 50 to heat it to the annealing temperature. Radiation can heat the entire semiconductor wafer 50 and provide sufficient power to rapidly heat the semiconductor wafer 50 to very high annealing temperatures (eg, 800° C.-1200° C.), thus configuration 803 is suitable for RTP. Lamp heater 840 may include an IR or UV lamp that emits radiation in a broad spectrum, often extending into the visible range. IR lamps can emit near-infrared light at very high power densities that can provide rapid temperature increases (eg, 200° C. per second). In some embodiments, an IR lamp is used for rapid thermal annealing (RTA) with annealing times from about 1 millisecond to about 10 seconds. RTP with even shorter annealing times requiring faster ramp rates (e.g., 10 ³ °C/sec to 10 ⁶ °C/sec), called flash lamp anneal (FLA), can be used, for example, in the UV to visible range. This can be achieved using a bank of flash xenon arc lamps with smooth emission curves.

In further embodiments, lamp heater 840 may comprise a microwave power source such as a microwave lamp.

In the exemplary configurations 801, 802, and 803 shown in FIGS. 8A-8C, the semiconductor wafer 50 is illuminated from both top and bottom surfaces, although in other embodiments the semiconductor wafer 50 is illuminated from either the top or bottom surface. can be irradiated from either

FIG. 8D shows an exemplary configuration 804 in which the energy or heat source is a laser in laser system 850 and energy is radiatively transferred to semiconductor wafer 50 by laser beam 852 . Laser beam 852 is focused to intersect a small area of the surface of semiconductor wafer 50 . Thus, very high power densities leading to local temperature spikes of about 10 ⁷ ° C./s to about 10 ⁹ ° C./s can be obtained using laser heating, a technique called laser spike annealing (LSA).

As noted above, annealing of the entire semiconductor wafer 50 may need to be accomplished using a scanner. In various embodiments, the scanning device may move the laser beam 852, or the semiconductor wafer 50 (having moving parts in the wafer support 810), or both, within the processing chamber 225. The movement can be a linear scan in a plane parallel to the top major surface of the semiconductor wafer 50 or a rotational scan. In the cross-sectional view of FIG. 8D, laser beam 852 is incident normal to the top major surface of semiconductor wafer 50 . However, in some embodiments, laser beam 852 may be incident at a high oblique angle, thereby allowing it to intersect the major top surface as a line extending over the entire extent of semiconductor wafer 50 . This can help reduce scan time by reducing the number of scan directions by one.

FIG. 9 shows an exemplary electric field annealer configuration 900 that heats the semiconductor wafer 50 using convective heat transfer. Convective heat transfer is accomplished using a heated medium to process chamber 225 to transfer heat from a heat source to semiconductor wafer 50 . Methods of convective heat transfer that may be utilized include directly or indirectly heated gas.

As shown in FIG. 9, the processing chamber 225 consists of a gas inlet pipe 910 and a gas outlet pipe 920 . Gases, typically inert gases (eg, nitrogen and argon), can be flowed over the semiconductor wafer 50 using a gas flow system including pumps and various gas sources. Gases flow into processing chamber 225 through gas inlet pipe 910 and are removed from processing chamber 225 through gas outlet pipe 920 . In the example shown in FIG. 9, a heater coil 930 is wrapped around the gas inlet pipe 910 and configured to heat the incoming gas. The heater coil 930 can be coupled to a temperature controller to adjust the temperature of the incoming gas to a desired value by adjusting the power supplied to the heater coil 930 . In configuration 900 , heater coil 930 is the heat source and heated incoming gas transfers thermal energy from heater coil 930 to semiconductor wafer 50 as the heated gas flows over the surface of semiconductor wafer 50 .

10A-10C illustrate first, second, and third configurations 1001, 1002, and 1003, each having multiple wafer processing chambers 1026 (similar to processing chambers 226 described above with reference to FIG. 1B). are shown respectively. A batch of semiconductor wafers 50 inside the processing chamber 1026 are in a vertical stack held by a wafer support structure, as shown in the exemplary embodiment in FIGS. 10A-10C. The processing chamber 1026 may be shaped like a tube having, for example, a quartz chamber wall 1020 and a base 1024 that includes, for example, a metal base that supports a semiconductor wafer support structure. The baseplate incorporates electrical feedthroughs to allow transmission of electrical connections to the wafer contacts 1018 and 1016 through the baseplate, while the baseplate is isolated from the bias source of the applied electric field (e.g., DC power supply 130). Remains electrically isolated. As shown in FIGS. 10A-10C, several heat sources 1010 can be used at various locations to uniformly heat the stack of semiconductor wafers 50 to a desired temperature. The wafer support structure may include refractory material. Refractory materials can include insulators such as quartz (eg, wafer support 1022), or conductive materials or coatings, such as stainless steel or carbon-based coatings (eg, wafer support 1028). In the wafer processing chamber 1026 of FIGS. 10B and 10C, a conductive wafer support 1028 is used because the wafer support structure itself is utilized as an electrical contact to the backside of the semiconductor wafer 50. FIG. As shown in FIGS. 10B and 10C, the conductive support 1028 is connected to GND via an electrical feedthrough that can be isolated from the base 1024. FIG.

In various embodiments, various configurations may be used to electrically couple the DC power supply 130 and ground to the stack of semiconductor wafers 50 . In some embodiments, such as the first and second configurations 1001 (FIG. 10A) and 1002 (FIG. 10B), a voltmeter 150 is used to monitor the potential at the semiconductor wafer 50 using monitoring electrodes (FIG. 1A). monitoring electrodes 212, etc.) are not present. In some other embodiments, such as third configuration 1003 (FIG. 10C), voltmeter 150 is electrically coupled to monitoring electrode 1044 that contacts semiconductor wafer 50 undergoing electric field annealing.

As shown schematically by the small circles in FIGS. 10A-10C, insulated wiring from electrical components outside of the processing chamber 1026 is routed using appropriately insulated connectors located on the base 1024. It can be electrically coupled to a conductor inside the processing chamber 1026 .

FIG. 10A shows electrical coupling in a first configuration 1001. FIG. DC power supply 130 in first configuration 1001 uses first conductive bus 1016 (similar to first conductive bus 108 in FIG. 1B) to connect primary electrode 1040 (primary electrode 215 in FIG. 1B). ) are electrically coupled to A common ground (shown as GND) is connected to the secondary electrode 1042 (similar to the second conductive bus 109 in FIG. 1B) using a second conductive bus 1018 (similar to the second conductive bus 109 in FIG. 1B). (similar to secondary electrode 216 in FIG. 1B). The primary electrode is in contact with part of the top surface of the semiconductor wafer 50 and the secondary electrode is in contact with part of the back surface of the semiconductor wafer 50 .

FIG. 10B shows the electrical coupling in the second configuration 1002. FIG. DC power source 130 in second configuration 1002 is electrically coupled to primary electrode 1040 using first conductive bus 1016, similar to the respective connections in first configuration 1001. FIG. However, instead of having a separate second conductive bus, one of the wafer supports (e.g., wafer support 1028) is used as a conductive bus to couple ground to the backside of semiconductor wafer 50. can do. Accordingly, in the second configuration 1002 (FIG. 10B), the wafer support 1028 includes a conductive refractory material or coating. As shown in FIG. 10B, a common ground (designated GND) is electrically coupled to wafer support 1028 which is in contact with the backside of semiconductor wafer 50 .

FIG. 10C shows a third configuration 1003. FIG. In a third configuration 1003, each top surface of semiconductor wafer 50 is in contact with two electrodes, primary electrode 1040 and monitoring electrode 1044 (similar to primary electrode 211 and monitoring electrode 212 in FIG. 1A). Primary electrode 1040 is electrically coupled to DC power supply 130 via first conductive bus 1016 and monitoring electrode 1044 is electrically coupled to voltmeter 150 via second conductive bus 1018 . there is As shown in FIG. 10C, the common ground of the third configuration 1003, like the ground connection (10B) of the second configuration 1002, is connected to the semiconductor wafer 50 through the wafer support 1028, which includes a conductive material or coating. is electrically coupled to the backside of the

Electrical connections (e.g., using field annealer electrodes 210, such as primary electrode 211 and monitoring electrode 212) to the backside and topside of semiconductor wafer 50 are made to incorporate in situ electrical measurements that can be used for process control. , provides the additional advantage of constructing the various embodiments of the electric field annealer described above. For example, the electrical connection may be part of a measurement probe of a process control system configured to measure current-voltage curves through layers of semiconductor wafer 50 during electric field anneal. In an exemplary embodiment where the electric field anneal is, for example, FEA performed to transform a deposited hafnium oxide dielectric layer into a stable or metastable polycrystalline ferroelectric hafnium oxide layer, lamp current-voltage A curve can be correlated with the formation of a ferroelectric orthorhombic phase in the dielectric layer. For example, a current-voltage curve can be used to detect the point at which the membrane remanent polarization (P _R ) intensity saturates, similar to a self-limiting process. A process control system can use such in-situ diagnostics with forward control or "virtual instrumentation" to achieve desired optimum film properties.

As noted above, the electric field anneal can be performed in a stand-alone processing chamber, a processing chamber configured to perform the electric field anneal in conjunction with some other process (e.g., deposition), either performed simultaneously or sequentially, or It can be performed in an electric field anneal chamber within a cluster configuration of a semiconductor processing system with other chambers.

The electric field anneal processing chamber has been described as a stand-alone chamber for various embodiments of electric field anneal configurations. However, semiconductor processing systems may be configured to use a single processing chamber for multiple processing technologies. For example, in some embodiments, additional gas lines, sensors, radio frequency (RF) sources, RF antennas, DC bias sources, sputter targets, etc. are added to extend the configuration of the electric field annealing chamber and extend its capabilities. Additional processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and plasma treatment (eg, plasma pre-clean) can be performed.

A stand-alone electric field anneal processing chamber or a processing chamber with extended capabilities may be included in a cluster configuration of several semiconductor processing chambers. 11A-11C show schematic diagrams of three cluster tools 1101, 1102, and 1103 with modules configured to perform electric field annealing. Additionally, the cluster tool may contain several other modules. For example, plasma etch processing chamber 1150 , plasma preclean processing chamber 1116 , and PVD processing chamber 1118 are shown included in cluster tools 1101 , 1102 , and 1103 .

Generally, a semiconductor wafer (eg, semiconductor wafer 50) is transferred to a cluster tool (eg, cluster tools 1101, 1102, and 1103) by an Equipment Front End Module (EFEM) 1130, shown schematically in FIGS. 11A-11C. and queued in the loading compartment to be loaded. Semiconductor wafers may then be transferred to another module for processing by a number of wafer transfer modules 1120 .

FIG. 11A shows a schematic diagram of a cluster tool 1101 with two electric field annealing process chambers with extended capabilities. In one embodiment, processing chamber 1110 may be configured to perform a PVD process and electric field anneal, and processing chamber 1114 may be configured to perform a plasma pre-clean process and electric field anneal. Also included in cluster tool 1101 are plasma etch processing chamber 1150 , plasma preclean processing chamber 1116 , and PVD processing chamber 1118 , as described above.

FIG. 11B shows a schematic diagram of a cluster tool 1102 containing one electric field annealing processing chamber 1140, and a cluster tool 1103 (shown in FIG. 11C) comprising two processing chambers 1140 that exclusively perform electric field annealing. Prepare.

FIG. 11D shows a portion of cluster tool 1102 where both electric field anneal processing chamber 1140 and PVD processing chamber 1118 can be accessed by wafer transfer module 1120 . Processing chamber 1140 can be similar to processing chamber 225 of configuration 802 (see FIG. 8B). Semiconductor wafers may be transferred from one module to another by the wafer transfer robot of wafer transfer module 1120, as indicated by the double arrows in FIG. 11D. In another part of the cluster tool, a wafer transfer module 1120 can transfer semiconductor wafers 50 between different pairs of processing chambers.

Exemplary embodiments of the invention are summarized here. Other embodiments can be appreciated from the entire specification and claims filed herein.

Example 1. A system for processing a semiconductor wafer, comprising a processing chamber, a heat source, a substrate holder configured to expose the semiconductor wafer to the heat source, and removably coupled to a first major surface of the semiconductor wafer. and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field to the semiconductor wafer. system.

Example 2. The system of Example 1, wherein the heat source is a hotplate positioned under the backside of the semiconductor wafer.

Example 3. A hot plate includes a substrate having an outer surface including an electrically insulating layer, the electrically insulating layer being covered by a conductive plate such that the conductive plate is electrically coupled to the backside of the semiconductor wafer. 3. The system of example 1 or 2, configured.

Example 4. The system of any one of Examples 1-3, wherein the hotplate is an electrically conductive material and is configured to be electrically coupled to the backside of the semiconductor wafer.

Example 5. The system of any one of Examples 1-4, wherein the heat source comprises a plurality of heat sources configured to radiantly heat the semiconductor wafer.

Example 6. The system of any one of Examples 1-5, wherein the heat source is positioned outside the processing chamber and configured to heat the semiconductor wafer by radiant heat transfer.

Example 7. The system of any one of Examples 1-6, wherein the heat source is positioned inside the processing chamber and configured to heat the semiconductor wafer by radiant heat transfer.

Example 8. The system of any one of Examples 1-7, wherein the heat source comprises a resistive heat source.

Example 9. The system of any one of Examples 1-8, wherein the heat source comprises a mineral insulated (MI) cable, a ceramic coated resistor, or a pyrolytic boron nitride (PBN) coated graphite resistor.

Example 10. The system of any one of Examples 1-9, wherein the heat source comprises an infrared (IR) lamp, an ultraviolet (UV) lamp, or a flash arc lamp.

Example 11. an electric field configured to be applied by maintaining a fixed voltage across the first electrode and the second electrode or by maintaining a time-varying voltage across the first electrode and the second electrode; 11. The system of any one of Examples 1-10, wherein the varying voltage comprises a pulse voltage or a sinusoidal voltage.

Example 12. 12. The system of any one of Examples 1-11, wherein the first electrode or the second electrode is coupled to a floating potential node.

Example 13. further comprising a scanner, the heat source being a laser beam source, the laser beam configured to heat a portion of the major surface of the semiconductor wafer intersecting the laser beam, the scanner being configured to heat the portion of the major surface intersecting the laser beam; 13. The system of any one of Examples 1-12, configured to move a portion to expose all major surfaces to the laser beam.

Example 14. 14. The system of any one of Examples 1-13, further comprising a fluid inlet and a fluid outlet positioned within the processing chamber and a heater coil configured to heat fluid entering the processing chamber.

Example 15. 15. The system of any one of Examples 1-14, further comprising a cluster of modules including an equipment front-end module, a wafer transfer module, and a processing module, wherein the processing chamber is part of the processing module.

Example 16. A system for processing semiconductor wafers, comprising a processing chamber, a heat source, a substrate holder configured to expose a semiconductor wafer to the heat source, and for contacting a first side of each of a plurality of semiconductor wafers. and a second bus including a second plurality of electrodes for contacting a second side of each of the plurality of semiconductor wafers; and the second bus are together configured to apply an electric field to each of the plurality of semiconductor wafers.

Example 17. 17. The system of Example 16, wherein the substrate holder is configured to vertically stack a plurality of semiconductor wafers within the processing chamber.

Example 18. wherein the first bus and the second bus are configured to simultaneously apply an electric field to each of the plurality of semiconductor wafers, and the substrate holder is configured to simultaneously expose the plurality of semiconductor wafers to the heat source; 18. The system according to 16 or 17.

Example 19. 19. The system of any one of Examples 16-18, wherein the substrate holder comprises a quartz wafer support.

Example 20. 20. The system of any one of Examples 16-19, wherein the substrate holder comprises a conductive wafer support, and wherein the conductive wafer support comprises a second bus.

Example 21. a third bus including a third plurality of electrodes, the third plurality of electrodes configured to removably contact the first side of each of the plurality of semiconductor wafers; is coupled to the voltage monitor.

Example 22. 22. The system of any one of Examples 16-21, further comprising a cluster of modules including an equipment front end module, a wafer transfer module, and a processing module, wherein the processing chamber is part of the processing module.

Example 23. A rapid thermal processing (RTP) system for processing semiconductor wafers, comprising an RTP chamber, a substrate holder configured to support a substrate, and an electromagnetic configured to heat the substrate supported by the substrate holder. an energy source; and a first electrode configured to be removably coupled to a first side of the substrate, the first electrode being coupled to a first potential node; a second electrode configured to be removably coupled to the second side, the second electrode coupled to the second potential node; The electrodes of the system are configured together to apply an electric field through the substrate.

Example 24. 24. The system of Example 23, wherein the substrate holder is configured to support a single one of a plurality of semiconductor wafers processed in the system.

Example 25. a first bus including a first plurality of electrodes and coupled to a first potential node, the first plurality of electrodes including the first electrode; a second bus including a plurality of electrodes and coupled to the second potential node, wherein the second plurality of electrodes includes the second electrode; is further configured to support a plurality of semiconductor wafers including substrates, the electromagnetic energy source is configured to heat the plurality of semiconductor wafers simultaneously, and the first plurality of electrodes are configured to support a plurality of semiconductor wafers; configured to contact a first side of each of the semiconductor wafers, the second plurality of electrodes configured to contact a second side of each of the plurality of semiconductor wafers; 25. The system of example 23 or 24, wherein the bus of and the second bus together are configured to apply an electric field to each of the plurality of semiconductor wafers.

Example 26. The system of any one of Examples 23-25, wherein the electromagnetic energy source is a flash lamp, laser, IR lamp, UV lamp, or microwave lamp.

Although the invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications and combinations of those exemplary embodiments, as well as other embodiments of the invention, will become apparent to persons skilled in the art upon reference to the specification. It is therefore intended that the appended claims cover any such modifications or embodiments.

10 substrate holder 14 slotted substrate holder 20 substrate 30 MOS dielectric layer 40 conductive top electrode layer 50 semiconductor wafer 100 load rail 108 first conductive bus 109 second conductive bus 110 primary wiring 112 monitoring wiring 113, 114 Secondary wire 115 Two wires 115
120 power feedthrough 130 DC power supply 140 ground wiring 150 voltmeter 210 first field annealer electrode 211 primary electrode 212 monitoring electrode 214 additional secondary electrode 216 secondary electrodes 225, 226 processing chambers 235, 236 thermal treatment system 310 isolated conductive wiring

Claims (22)

A system for processing semiconductor wafers, comprising:
a processing chamber;
a heat source;
a substrate holder configured to expose a semiconductor wafer to the heat source;
a first electrode configured to be removably coupled to a first major surface of a semiconductor wafer;
a second electrode coupled to the substrate holder, wherein the first electrode and the second electrode together are configured to apply an electric field to the semiconductor wafer;
system. A control system comprising a measurement probe configured to measure a current-voltage curve through a layer of the semiconductor wafer when the electric field is applied, the control system comprising a controller for controlling the electric field. 3. The system of claim 1, further comprising a system. 2. The system of claim 1, wherein the heat source is a hotplate positioned under the backside of the semiconductor wafer. the hotplate comprises a substrate having an outer surface comprising an electrically insulating layer;
4. The system of claim 3, wherein the electrically insulating layer is covered by a conductive plate, the conductive plate configured to be electrically coupled to the backside of the semiconductor wafer. 4. The system of claim 3, wherein the hotplate is of electrically conductive material and configured to be electrically coupled to the backside of the semiconductor wafer. 3. The system of Claim 1, wherein the heat source comprises a plurality of heat sources configured to radiantly heat the semiconductor wafer. 2. The system of claim 1, wherein the heat source is located outside the processing chamber and configured to heat the semiconductor wafer by radiant heat transfer. 2. The system of claim 1, wherein the heat source is positioned inside the processing chamber and configured to heat the semiconductor wafer by radiant heat transfer. 3. The system of Claim 1, wherein the heat source comprises a resistive heat source. 10. The system of claim 9, wherein the heat source comprises a mineral insulated (MI) cable, a ceramic coated resistor, or a pyrolytic boron nitride (PBN) coated graphite resistor. 2. The system of claim 1, wherein the heat source comprises an infrared (IR) lamp, an ultraviolet (UV) lamp, or a flash arc lamp. The electric field is
applied by maintaining a fixed voltage across the first electrode and the second electrode or by maintaining a time-varying voltage across the first electrode and the second electrode , the time-varying voltage comprises a pulse voltage or a sinusoidal voltage;
The system of claim 1. 2. The system of claim 1, wherein said first electrode or said second electrode is coupled to a floating potential node. further equipped with a scanner,
wherein the heat source is a laser beam source, the laser beam configured to heat a portion of the major surface of the semiconductor wafer that intersects the laser beam;
the scanner is configured to move the portion of the major surface intersecting the laser beam to expose all of the major surface to the laser beam;
The system of claim 1. a fluid inlet and a fluid outlet positioned within the processing chamber;
a heater coil configured to heat fluid entering the processing chamber;
The system of claim 1. 3. The system of claim 1, further comprising a cluster of modules comprising an equipment front-end module, a wafer transfer module, and a processing module, the processing chamber being part of the processing module. A system for processing semiconductor wafers, comprising:
a processing chamber;
a heat source;
a substrate holder configured to expose a plurality of semiconductor wafers to the heat source;
a first bus comprising a first plurality of electrodes for contacting a first side of each of the plurality of semiconductor wafers;
a second bus comprising a second plurality of electrodes for contacting a second side of each of the plurality of semiconductor wafers;
wherein the first bus and the second bus are together configured to apply an electric field to each of the plurality of semiconductor wafers;
system. 18. The system of Claim 17, wherein the substrate holder is configured to vertically stack the plurality of semiconductor wafers within the processing chamber. The first bus and the second bus are configured to simultaneously apply an electric field to each of the plurality of semiconductor wafers, and the substrate holder simultaneously exposes the plurality of semiconductor wafers to the heat source. 18. The system of claim 17, configured to: 18. The system of Claim 17, wherein the substrate holder comprises a quartz wafer support. 18. The system of claim 17, wherein said substrate holder comprises a conductive wafer support, said conductive wafer support comprising said second bus. a third bus comprising a third plurality of electrodes, said third plurality of electrodes configured to removably contact said first side of each of said plurality of semiconductor wafers; 18. The system of Claim 17, further comprising a third bus, wherein said third bus is coupled to a voltage monitor.

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