TW202242968A - Semiconductor processing systems with in-situ electrical bias - Google Patents

Abstract

A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of the semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.

Description

Semiconductor processing system with in situ electrical biasing

The present invention generally relates to semiconductor processing systems and methods, and in particular embodiments, to semiconductor processing systems with in-situ electrical biasing. [Cross-Reference to Common Application]

This application refers to US Nonprovisional Patent Application No. 16/841,342 (filed April 6, 2020), which is hereby incorporated by reference.

In general, semiconductor integrated circuits (ICs) are fabricated by sequentially depositing layers of materials (such as dielectrics, metals, semiconductors, etc.) Layers are patterned to form circuit components (such as transistors and capacitors) and connecting elements (such as lines, contacts, and vias). The minimum feature size is periodically reduced with innovations such as immersion lithography and multiple patterning to reduce cost by increasing packing density. Miniaturization of device footprint can be enhanced by increasing the output per unit area of the device. For example, transistor drive current per unit width or capacitor stored charge density can be increased by using thinner gate dielectrics or thinner capacitor dielectrics, respectively.

However, the benefits of miniaturization come with several costs in process complexity, circuit speed, and standby power consumption, which may need to be addressed. There is a performance trade-off in the scaling trend towards narrower line widths and reduced space between conductors and electrodes. Some of these tradeoffs may be mitigated through the use of new materials. For example, in interconnected systems, increased IR drop and RC delay due to higher resistance of lines and vias and increased capacitance between lines can be achieved by using materials such as ruthenium and cobalt (replacing tungsten and copper) ) metals, and low-k intermetal dielectrics (IMDs) such as fluorosilicate glasses and carbon-doped oxides. Reduced source-to-drain spacing and thinner gate or capacitor dielectrics in transistors can increase standby leakage. This problem may be alleviated by using a high-k dielectric or a ferroelectric dielectric material.

The incorporation of new materials requires further innovations to better exploit the advantages offered by their use in ICs.

According to an embodiment of the present invention, a system for processing a semiconductor wafer, wherein the system includes a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; an electrode configured to be detachably coupled to the first major surface of the semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode co-located on the semiconductor wafer An electric field is applied in the circle.

According to an embodiment of the present invention, a system for processing semiconductor wafers, wherein the system includes a processing chamber; a heat source; a substrate holder configured to expose a plurality of semiconductor wafers to the heat source; A bus bar, including a first plurality of electrodes for contacting a first side of each of the plurality of semiconductor wafers; and a second bus bar, including a first electrode for contacting a second side of each of the plurality of semiconductor wafers Two plural electrodes, the first bus bar and the second bus bar are jointly arranged to apply an electric field in each of the plurality of semiconductor wafers.

In accordance with an embodiment of the present invention, a rapid thermal processing (RTP) system for processing semiconductor wafers, wherein the system includes an RTP chamber; a substrate holder configured to support a substrate; an electromagnetic energy source configured to heat a substrate the substrate supported by the substrate holder; a first electrode configured to be detachably coupled to the first side of the substrate, the first electrode coupled to a first potential node; and a second electrode configured to be detachably coupled to the On an opposite second side of the substrate, the second electrode is coupled to a second potential node, the first electrode being co-located with the second electrode to apply an electric field across the substrate. 【Simplified illustration】

For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings in which:

1A is a cross-sectional view illustrating a processing chamber of an electric field annealer according to an embodiment of the present invention;

1B is a cross-sectional view of a processing chamber of an electric field annealer according to an alternate embodiment of the present invention;

2 is a perspective view illustrating a loading rail of an electric field annealer according to an embodiment of the present invention;

Figure 3 is an enlarged perspective view of a detail of the perspective view shown in Figure 2;

4 is a perspective view illustrating a loading rail of an electric field annealer according to an embodiment of the present invention;

Figure 5A is an enlarged perspective view of a detail of the perspective view depicted in Figure 2;

Figure 5B is an enlarged perspective view in different directions of a detail of the perspective view depicted in Figure 2;

6A-6C are cross-sectional views of various semiconductor wafers placed in a processing chamber of an electric field annealer, according to one embodiment of the present invention;

7A-7B are cross-sectional views of an electric field annealer configuration, including a single wafer electric field anneal processing chamber using conductive heat transfer from a heating source, in accordance with one embodiment of the present invention;

8A-8D are cross-sectional views illustrating an EFA configuration including a single wafer EFA processing chamber using radiant heat transfer from a heating source, in accordance with one embodiment of the present invention;

9 is a cross-sectional view illustrating an electric field annealer configuration including a single wafer electric field anneal processing chamber using convective heat transfer from a heating source in accordance with one embodiment of the present invention;

10A-10C are cross-sectional views illustrating an electric field annealer configuration, including a plurality of wafer electric field annealing chambers, according to an embodiment of the present invention;

11A-11D are cross-sectional views of a cluster tool, including an electric field annealing module, according to one embodiment of the present invention.

This disclosure describes apparatus and methods for processing semiconductor wafers while applying an electrical bias voltage across two conductor layers of the wafer during processing. The bias voltage is applied via electrodes in direct electrical contact with the wafer and connected to a power supply external to the processing chamber. In this specification, the annealing process performed simultaneously with the electrical bias is called E-field annealing, and the processing equipment used to implement the E-field annealing is called an E-field annealer. The processing chamber may be referred to as an E-field annealing chamber. In an exemplary embodiment, the electrical bias is used to subject the dielectric film in the wafer to a DC electric field (E-field) of a desired magnitude during a post-deposition anneal (PDA) processing step.

In several manufacturing process flows including the manufacture of ferroelectric dielectric basic electronic components such as metal oxide semiconductor field effect transistors (MOSFETs) and/or capacitors, as explained below, it may be advantageous to use an E-field PDA. Processing steps to form a ferroelectric layer may include depositing a ferroelectric oxide, such as doped hafnium oxide, or doped hafnium zirconate, or a perovskite oxide such as barium strontium titanate, or bismuth metal oxide thing. Many dopants, such as La, Al, Si, Sr, Gd, and Y, have been shown to improve ferroelectric properties by distorting the crystal structure. However, in the case of _HfO2 , _HfAlOx or _HfZrOx , there may be a plurality of crystal phases. Among these materials, the post-deposition annealing (PDA) conditions play an important role in inducing the ideal noncentrosymmetric orthorhombic phase with ferroelectric properties. This PDA step, known as ferroelectric annealing (FEA), potentially converts the deposited hafnium oxide layer into a stable or metastable polycrystalline ferroelectric hafnium oxide layer. The fabrication process of ICs containing electronic components using hafnium oxide-based ferroelectric dielectrics typically includes an electrical cycling step (referred to herein as a wake-up cycle) to obtain stable ferroelectric properties. In embodiments of the present disclosure, ferroelectric MOSFETs (FE-FETs) and ferroelectric capacitors may be fabricated using, for example, ferroelectric dielectrics, including, for example, hafnium oxide, wherein during crystallization of the FEA, the dielectric The mass is subjected to the DC E field mentioned above applied using the apparatus and methods described in further detail below. The E-field FEA technique used in example embodiments may offer the advantage of shortening and (in some embodiments) eliminating the wake-up cycle. The wake-up effect is described in further detail below. It should be appreciated that the E-field FEA technique described using various embodiments of the present disclosure may provide similar benefits for forming ferroelectric layers using materials other than the hafnium oxide base material.

The dielectric material may be polarized with an electric field (E). The electrical polarization vector (P) responsive to the E field is generally a function of the electric field E, which is approximately linear and symmetric for centrosymmetric dielectrics. Centrosymmetric dielectrics are non-ferroelectric (ie, at E = 0, P = 0). However, several non-centrosymmetric dielectrics are ferroelectric, that is, they exhibit spontaneous or remnant polarization; at E = 0, P = _{PR ≠ 0, called remanent polarization (P R )} . _A coercive electric field (EC ) of opposite polarity must be applied to force P to zero in the ferroelectric dielectric. The ferroelectric P versus E curve is nonlinear and has a substantially symmetrical hysteresis loop. As is known to those of ordinary skill in the art, some ferroelectric films such as hafnium oxide based ferroelectric films exhibit a wake-up effect where the original film produced using conventional processes (without E-field annealing) has a shrinkage The hysteresis curve (small P _R ), after it cycles through relatively high forward (positive) and reverse (negative) E fields multiple times (for example, about 10 ² cycles to about 10 ⁵ cycles), the The hysteresis curve opens up into a stable, wider hysteresis loop (larger P _R ). In general, each of the ferroelectric components including the original dielectric film with unstable P _R must be stabilized by wake-up cycling in order for the corresponding circuit to function as designed. Thus, it can be confirmed that the innovative E-field annealing technique described in this disclosure provides significant advantages by reducing the number of wake-up cycles and, in some embodiments, eliminating the wake-up cycle step.

In its P-to-E nature, the presence of hysteresis allows a ferroelectric capacitor to be used as a non-volatile memory (NVM) element. For example, it is possible by forcing the ferroelectric capacitor into the upper or lower branch of its P-to-E hysteresis loop with a high positive or negative bias voltage respectively, placing it in a correspondingly high positive or negative polarization state , to store the binary logic state of "1" or "0". After the bias is removed (E = 0), a portion of the polarization is retained as remanent polarization, depending on which of the ferroelectric capacitor is forced into the upper or lower branch of its P versus E hysteresis loop, +P _R or –P _R . Since the maximum displacement current (corresponding to the maximum slope of P versus E) in each branch of the hysteresis curve will occur at opposite polarities, it can be obtained by, for example, a capacitor responding to a voltage ramp of a given polarity The current is sensed to retrieve the stored information. As understood from the data storage and retrieval mechanism explained above, because of the importance of stability and high _PR , a wake-up cycle step is usually implemented in the manufacture of ICs that include devices that are not mentioned above. Hafnium oxide-based ferroelectric NVM formed in the case of E-field FEA. However, use of the E-field annealer and E-field FEA described in this disclosure can provide reduced hafnium oxide by reducing the number of wake-up cycles and, in some embodiments, eliminating the wake-up cycle step from the fabrication flow. Advantages of basic ferroelectric NVM cost.

Ferroelectricity may be used to form the gate dielectric stack of FE-FETs. If the remanent polarization of the gate dielectric stack is high enough, similar to the ferroelectric capacitor, the transistor, once programmed, can retain its function even after the programming voltage is removed. state and maintain "on" or "off". Such FE-FETs can also be used to store digital information in NVM cells. As explained above in the context of the hafnium oxide based ferroelectric capacitor NVM, the manufacturing cost of the hafnium oxide based ferroelectric FE-FET NVM can be reduced by using the innovative E-field annealer and E-field FEA.

When used in digital logic or analog circuits, FE-FETs may offer several advantages over conventional (ie, non-ferroelectric) MOSFETs. The gate dielectric stacks of FE-FETs used in digital logic and/or analog circuits include ferroelectric and non-ferroelectric thin films. When used in a circuit, such as a digital switch, the ferroelectric portion of the gate dielectric stack provides a dynamic capacitance that under specified bias sweep conditions (e.g., scan rate or frequency), may result in a voltage snap-back due to the switching of the ferroelectric polarization. This snapback may result in a desirable steeper subthreshold and higher I _ON /I _OFF ratio for the FE-FET. In this context, the FE-FET is generally referred to as a negative capacitance field effect transistor (NCFET). Here, it is more correct to say that it is a steep-slope ferroelectric field-effect transistor (SSFEFET). However, the ferroelectric properties (eg, P _R ) and film thickness in the gate dielectric stack may have to be properly tuned to achieve the IV and CV curves of the hysteresis-free crystal. As known by those skilled in the art, hysteresis-free IV and CV curves imply stable transistor operation, while the presence of hysteresis may lead to circuit instability and unexpected electrical oscillations. It should be appreciated that due to circuit stability considerations, P _R must remain stable and within a design window in order for the SSFEFET to provide the desired circuit benefits without destabilizing the circuit. Therefore, SSFEFET fabrication flows that do not include E-field FEA may include a wake-up cycle step, and the use of the innovative E-field annealing technique described in this disclosure can be improved by reducing the wake-up cycle and in some embodiments without wake-up Stable ferroelectric properties are achieved with cycling, offering the advantage of reduced cost.

In this disclosure, first, the E-field annealing technique is described using a schematic cross-sectional view of a processing chamber of an E-field annealer during an E-field anneal (e.g., E-field FEA) processing step, as shown in FIG. 1A and An alternative embodiment is shown in Figure 1B. The field E annealer is further described with reference to various perspective views of the loading rail of the field E annealer shown in FIGS. 2-5 . The electrical connection during E-field FEA of the gate dielectric layer of FE-FET/SSFEFET and/or MOS ferroelectric capacitor is referred to planar bulk complementary MOS ( CMOS) and silicon-on-insulator (SOI) CMOS semiconductor wafers are described in cross-sectional view. In addition to MOS capacitors, capacitor components in ICs, commonly referred to as MIM capacitors, can be formed using metal layers for both the top and bottom electrodes of the capacitor. In this disclosure, abbreviations are used to distinguish between non-ferroelectric and ferroelectric insulating layers; non-ferroelectric insulating layers are abbreviated as I, and ferroelectric insulating layers are abbreviated as F. The electrical connections made to the electrodes of the MFM capacitor during E-field FEA are described with reference to the cross-sectional view shown in FIG. 6C.

As described with reference to FIGS. 1A and 1B , the E-field anneal may be in a single wafer processing chamber (e.g., processing chamber 225) or in a multi-wafer (or batch) processing chamber (e.g., processing chamber 226). ) is executed. Semiconductor wafer 50 is heated to and maintained at a desired temperature using a thermal processing system (e.g., thermal processing systems 235 and 236) that includes a heating source, a temperature sensor, and a temperature that regulates power delivered to the heating source controller. The E field annealer can be equipped with an oven with a slow temperature rise and a stabilization time of about a few minutes, or with a heating source suitable for rapid thermal processing (rapid thermal processing, RTP), in which the semiconductor wafer is usually processed within a few seconds or a few minutes. Rapidly heated to a high temperature within milliseconds, and in some embodiments, within microseconds. RTP technology reduces processing time and offers many benefits to E-field annealers set up for single wafer processing. However, E-field annealers with single or multiple wafer processing chambers can be configured for RTP. Various different E-field annealer embodiments may be provided with various different thermal processing systems comprising various different heating sources oriented in many different ways relative to the semiconductor wafer, as further described below.

As also described with reference to FIGS. 1A and 1B , during E-field annealing in a single-wafer or multi-wafer processing chamber, the semiconductor wafer 50 is electrically biased. The electrodes of the semiconductor wafer 50 and conductive portions of the processing chamber (e.g., processing chambers 225 and 226) may be electrically coupled to electrical components outside the processing chamber (e.g., DC power supply 130, voltmeter 150, and Reference potential, which is referred to as ground) provides and monitors the electrical bias. In various embodiments, the E-field annealer can be configured with different electrical connections, as further described below.

7A-7B, 8A-8D, and 9 illustrate various configurations of E-field annealers configured for single wafer processing. Figures 10A-10C illustrate the configuration of an E-field annealer suitable for batch processing.

In various embodiments, the thermal processing system uses conductive, radiative, or convective heat transfer mechanisms, or combinations thereof, to achieve the desired temperature of the semiconductor wafer during the E-field anneal. 7A-7B illustrate an embodiment using conductive heat transfer from a hot plate heating source. 8A-8D illustrate embodiments configured to use radiative heat transfer from various types of heating sources, and convective heating is described with reference to FIG. 9 .

In various embodiments, various configurations may be electrically connected to apply the E-field and monitor the potential on the semiconductor wafer. 10A-10C illustrate three exemplary embodiments configured for batch processing with different electrical connections to electrically couple various conductive portions of the semiconductor wafer 50 and processing chamber to DC. Power supply 130, voltmeter 150, and ground.

The E-field anneal processing chamber may be a stand-alone processing chamber, a processing chamber configured to perform an E-field anneal and several other processes (e.g., deposition) performed simultaneously or sequentially, or within a semiconductor processing system having other chambers E-field annealing chamber in cluster configuration. Several examples of semiconductor processing systems that include clusters of processing modules called cluster tools are described with reference to FIGS. 11A-11D .

Stacks of various combinations of material layers may be formed for use in ferroelectric electronic devices such as transistors and capacitors. The stack may include ferroelectric layers, as well as non-ferroelectric dielectric layers, metal layers, and semiconductors. Examples include, but are not limited to, the following stacks (stacks are listed from top to bottom): metal-ferroelectric-metal (MFM), metal-ferroelectric-insulator-metal (MFIM), metal-iron Electro-Insulator-Semiconductor (MFIS), Metal-Ferroelectric-Metal-Semiconductor (MFMS), Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS), Semiconductor-Ferroelectric-Semiconductor (SFS), and Semiconductor-Ferroelectric - Insulator-Semiconductor (SFIS). In this disclosure, exemplary stacks may be MFIS (eg, in FEFET/SSFEFET transistors) or MFM (eg, in capacitors with top and bottom metal electrodes).

FIG. 1A schematically illustrates a cross-sectional view of a semiconductor wafer 50 placed on a substrate holder 10 within a processing chamber 225 of an E-field annealer equipped to perform an E-field anneal. Annealer. The processing chamber 225 includes a thermal processing system 235 designed to thermally treat wafers placed within the processing chamber 225 . In various embodiments, the thermal processing system 235 includes temperature controllers that control the heating and cooling elements by using lamps, resistive elements, and various locations within or outside of the processing chamber 225 Other elements are used to maintain the semiconductor wafer 50 in the processing chamber 225 at an ideal temperature. Some thermal processing systems used in embodiments of the processing chamber of the E-field annealer are described further below.

The semiconductor wafer 50 includes a substrate 20 , a MOS dielectric layer 30 formed on the substrate 20 , and a conductive top electrode layer 40 formed on the MOS dielectric layer 30 .

As schematically depicted in FIG. 1A , the first E field annealer electrode is in physical and electrical contact with the conductive top electrode layer 40 . The first E field annealer electrode may comprise a conductive material that is not affected by high temperature processing. In one embodiment, the first E field annealer electrode may comprise tungsten. The first E-field annealer electrode comprises a main electrode 211 (e.g., a tungsten ribbon) connected to a first terminal of the DC power supply 130 using a main wire 110 of a suitable conductor (e.g., tungsten), which is suitable Conductors may be heated to high temperatures during annealing without damage. The ribbon-shaped main electrode 211 provides a spring-like behavior during the annealing process to help avoid slippage and maintain good physical contact with the surface of the semiconductor wafer 50 as it is heated. The potential of the conductive top electrode layer 40 may optionally be monitored using a voltmeter 150 connected by a monitoring lead 112 (similar to the main lead 110) to another monitor electrode 212, for example, placed in contact with the conductive top electrode Layer 40 contacts another tungsten ribbon. The two electrodes are electrically shorted together by the conductive top electrode layer 40 . The main electrode 211 and the monitoring electrode 212 may collectively be referred to as a first E-field annealer electrode 210 . The main conductor 110 and the monitoring conductor 112 may collectively be referred to as a dual conductor 115 .

In the exemplary embodiment depicted in FIG. 1A , the surface of the substrate holder 10 physically connected to the backside of the semiconductor wafer 50 is used as the second E-field annealer electrode. The surface of the substrate holder 10 may be coated with a suitable conductive material, such as a silicon base, a carbon base, a silicon and carbon composite base, or a metal nitride base coating, to obtain a coating suitable for use as an electrode at the annealing temperature. conductor surface. The backside of semiconductor wafer 50 and a portion adjacent to the backside may be a conductive material, such as n-type or p-doped silicon or germanium, and may be in electrical contact with the surface of substrate holder 10 . In some embodiments, backside etching may be utilized to expose the conductor surface at the backside to establish an electrical contact between the backside of semiconductor wafer 50 and the surface of substrate holder 10 .

As shown schematically in FIG. 1A , the surface of the substrate holder 10 , and thus also the backside of the semiconductor wafer 50 , can be connected to a reference potential, referred to as ground, and at It is represented by GND in Fig. 1A. This ground connection can be established using a secondary wire 113 similar to the primary wire 110 . In this embodiment, the secondary conductor 113 is electrically connected to a ground conductor that connects the conductor portion of the primary structure of the device to system ground. The second terminal of the DC power supply 130 is also connected to ground (GND) to apply a bias voltage on the semiconductor wafer 50 . As understood by those of ordinary skill in the art and explained further below, the voltage drop between the two terminals of the DC power supply may be adjusted to achieve a desired polarity in the MOS dielectric layer 30 and in the desired The E field of the E field strength within the range. In various embodiments, the DC power supply 130 may be configured to supply a suitable voltage, such as between 1 V and 100 V, and in one embodiment between 3 V and 10 V.

It should be noted that the bias voltage applied during annealing may be a fixed voltage or a time-varying voltage, and that the amplitude and waveform may vary widely depending on the material, layer thickness, annealing conditions, and specific device application. The above DC bias voltages are for illustration only and should not be construed as limiting. Time-varying voltage waveforms may include pulsed DC, alternating pulses, sinusoidal, sawtooth, and the like. It should be further noted that the applied bias voltage may be referenced to a common ground potential, some other fixed reference potential, a controlled variable reference potential, a time-varying potential, or a floating node potential.

Although the embodiment in FIG. 1A depicts a single semiconductor wafer 50 within the processing chamber 225, it should be understood that a plurality of wafers, including baffle wafers, may be placed within a suitably designed processing chamber. round. The E field annealer electrodes and electrical connections shown in FIG. 1A are configured for single wafer processing. However, the E field annealer configuration may be changed to anneal a batch of semiconductor wafers. An exemplary embodiment suitable for batch processing is depicted in FIG. 1B .

In FIG. 1B, a plurality of semiconductor wafers 50 are stacked horizontally on a slotted substrate holder 14 that includes an insulating layer (eg, a ceramic insulating layer) that is not affected by high temperature processing. . The insulating material prevents the substrate holder 14 from electrically shorting between the conductive top and back surfaces of the semiconductor wafer 50 . The stacked wafers are shown loaded within a processing chamber 226 of the E-field annealer. Located within the processing chamber 226 are two conductive bus bars: a first conductive bus bar 108 and a second conductive bus bar 109 , fixed above and below the slotted substrate holder 14 , respectively. The temperature within the processing chamber 226 can be controlled by a thermal processing system 236 .

The conductive top surface of each wafer is shown electrically connected to first conductive bus-bar 108 by main electrode 215 similar to main electrode 211 in FIG. 1A . As shown in FIG. 1B , the connection between the first conductive bus bar 108 and the main electrode 215 can be established using connecting wires through openings in the slotted substrate holder 14 . In this embodiment, the first E field annealer electrode includes the main electrode 215 and the first conductive bus bar 108 . The first E field annealer electrode is connected to a DC power supply 130 using the same main wire 110 as in FIG. 1A. The conductive backside of each wafer can be connected to the second conductive busbar 109 using secondary electrodes 216 and connecting wires (similar to the topside). In this embodiment, the second E field annealer electrode including the secondary electrode 216 and the second conductive bus bar 109 is connected to GND using the secondary wire 114 . As shown in FIG. 1B , the potential of the top surfaces of the wafers can be monitored by connecting the first conductive bus 108 to a voltmeter 150 using a monitoring wire 112 .

The E-field annealer described above with reference to FIG. 1B is suitable for batch processing horizontally stacked wafers. The design of the processing chamber 226 may be modified to provide a similar E-field annealer, where the semiconductor wafers 50 may be stacked vertically rather than horizontally.

Various configurations are possible for making electrical connections to bias the semiconductor wafer in the processing chamber during the E-field anneal. A few examples depicting some of these possibilities are described further below.

FIG. 2 shows a perspective view of a loading rail 100 of an E-field annealer according to an embodiment of the present invention. The load rail 100 may be used to introduce the wafer into the processing chamber 225 of an E-field annealer. The wafers are first loaded into the slots of the substrate holders mounted on the load rail stage (Figure 2). The electrodes are then positioned to make appropriate electrical connections to the/each wafer. Next, the load rail table is used to place the wafers in the substrate holder into the heated zone of an oven.

In FIG. 2 , dual conductors 115 (similar to main conductor 110 and monitor conductor 112 of FIG. 1A ) are shown leading to a region B1 (marked by a dotted circle in FIG. 2 ). Region B1 includes a first E-field annealer electrode 210 comprising ditungsten ribbons contacting the conductive top electrode layer 40 of the semiconductor wafer 50 . As mentioned above, the ribbon shape helps maintain a good physical connection to the semiconductor wafer 50 during the annealing process. A first E-field annealer electrode 210 is attached to the exposed metal (eg, exposed tungsten) portion of the twin wire 115 . The rest of the twin wires 115 are electrically insulated from other conductors of the device by insulating material (eg, insulating ceramic beads). The insulated portion of the twin wire 115 is referred to as an insulated conductive wire 310 . FIG. 3 shows an insulated wire 310 (eg, using ceramic beads for insulation) in an enlarged perspective view of a region D1 , which is marked by a dotted circle in FIG. 2 .

The first of the twin conductors 115 passes through a power feedthrough 120 (shown in FIG. 2 ) and may be connected to a DC power supply 130 which, as described above, is used to pass through a dielectric layer such as , an E-field is provided in the MOS-dielectric layer 30) of the semiconductor wafer 50. As shown schematically in FIG. 2 , the other wire of the dual wire 115 (similar to the monitor wire 112 of FIG. 1A ) can be connected at one end to the first E-field annealer electrode 210 and the opposite end can be connected to a voltmeter 150, to monitor the potential of the conductive top electrode layer 40 of the semiconductor wafer 50 . The conductive portion of the main structure of the device, including a substrate holder (e.g., substrate holder 10 in FIG. . The substrate holder for semiconductor wafer 50 is further described below with reference to FIG. 5A , which shows an enlarged perspective view of area B1 (marked by a dashed circle in FIG. 2 ).

In FIG. 4 is shown a perspective view of the loading rail 100 from a different angle, which is marked with an arrow C in FIG. 2 . FIG. 4 shows the conductors of the twin wires 115 exposed by removing the ceramic beads from corresponding two insulated wires 310 passing through two corresponding openings. The double wire 115 is connected to the ditungsten ribbon of the first E-field annealer electrode 210 which is in contact with the top surface of the semiconductor wafer 50 . These dual wires 115 in FIG. 4 are the same wires as shown in FIG. 2 extending from the first E-field annealer electrode 210 to the DC power supply 130 and the voltmeter 150 respectively. In the perspective view of FIG. 4 , the first E-field annealer electrode 210 is located in a region C1 (marked with a dotted circle). In the perspective view of FIG. 2, the first E-field annealer electrode 210 is located in the region B1.

The area B1 of FIG. 2 and the area C1 of FIG. 4 are shown in more detail in the enlarged perspective views shown in FIGS. 5A and 5B , respectively. The perspective view in FIG. 5A more clearly shows the connection between one of the twin wires 115 and the first E field annealer electrode 210 . A clearer view of the tungsten ribbons of the first E field annealer electrode 210 in physical contact with the conductive top electrode layer 40 of the semiconductor wafer 50 is provided from the perspective shown in the perspective view in FIG. 5B . The semiconductor wafer 50 in FIGS. 5A and 5B is shown supported from the bottom by a support plate 230 . The support plate 230 is part of the slotted substrate holder shown in FIGS. 2 and 3 and may also be an exemplary embodiment of the substrate holder 10 of FIG. 1A . The surface of support plate 230 may be metallic, including, for example, stainless steel, and may be in physical and electrical contact with the conductive backside of semiconductor wafer 50 . The support plate 230 may be in the form of a ring in one embodiment. The ring shape supports the outer diameter of the wafer but exposes most of the backside surface to the heat source. The support plate 230 may include a conductive material connected to ground GND.

FIG. 5A shows several optional buffer wafers 240 that help achieve a more uniform temperature distribution over the surface of the semiconductor wafer 50 during annealing. For clarity, optional buffer wafer 240 is not shown in FIGS. 4 and 5B . As shown in FIG. 5B , insulating ceramic sheet 250 may be placed along the carrier rails near the edges of semiconductor wafer 50 and support plate 230 to minimize the gap between semiconductor wafer 50 and the conductive surface of the E-field annealer. Possibility of accidentally creating an undesirable electrical short circuit.

During the E-field PDA, the DC bias voltage settable by the DC power supply 130 generally does not only depend on the thickness t _ox of the target dielectric layer to implement the E-field PDA (for example, the MOS in FIG. 1A dielectric layer 30), also depends on the properties of other layers, such as the material used in the conductive top electrode layer 40, and, as described below, the materials of these layers below the target dielectric layer, thickness, and properties. In several embodiments, the DC bias voltage of the DC power supply 130 may be controlled to remain constant during the E-field anneal.

6A and 6B are cross-sectional views of the semiconductor wafer 50 in the E-field annealing step of the planar bulk CMOS process and the planar SOI CMOS process, respectively. In the exemplary embodiment depicted in FIGS. 6A and 6B , the E-field anneal step is an E-field ferroelectric anneal ( FEA). The conductive top electrode layer 40 can be used as the gate electrode of a FE-FET/SSFEFET or a ferroelectric MOS capacitor, and can comprise one or more conductive materials such as TiN, TaN, W, metal alloys, and the like.

In FIGS. 6A and 6B , a gate-first process integration method can be used to fabricate ferroelectric devices (eg, FE-FET/SSFEFET, and ferroelectric MOS capacitors) using MOS dielectric layer 30 . However, those skilled in the art will appreciate that the innovative concepts of these embodiments can be applied to corresponding ferroelectric devices produced using gate-last (or replacement gate) process integration methods.

In the exemplary embodiment shown in FIGS. 6A and 6B , the MOS dielectric layer 30 includes a doped amorphous hafnium oxide film, and an interface dielectric film adjacent to the surface of the semiconductor (eg, silicon). (such as silicon oxide). The thickness t _ox of the MOS dielectric layer 30 depends on the application and may vary from about 1 nm to about 100 nm. The annealing temperature can be adjusted so that during the annealing, the amorphous hafnium oxide will crystallize to form a polycrystalline hafnium oxide film. For example, the E-field FEA may be performed at a temperature of about 200°C to about 1200°C, eg, in a low pressure inert gas environment. Temperatures below 200°C may not be suitable for crystallizing the amorphous layer, while temperatures above 1200°C may alter the properties of other layers formed during earlier processing steps. The orthorhombic phase of hafnium oxide is ferroelectric, but pure amorphous _HfO2 may naturally convert to monoclinic or cubic grains, because the orthorhombic phase of pure _HfO2 is unstable of. However, as known to those skilled in the art, the orthorhombic phase of HfO ₂ can be stabilized by specific doping atoms such as zirconium, silicon, or lanthanum atoms. Therefore, when the doped amorphous hafnium oxide film in the MOS dielectric layer 30 is crystallized, the orthorhombic phase of HfO ₂ is formed, and can be obtained by the metastable orthorhombic phase (which is ferroelectric) ) in the dopant to be stabilized. The electric field strength during this E-field FEA may be adjusted to be between 1 MV/cm and about 100 MV/cm. While an E-field that is too low may not provide sufficient benefit in reducing/eliminating wake-up cycles, an E-field that is too high may cause damage to and/or degrade the lifetime of the MOS dielectric layer 30 . As explained further below, the corresponding DC bias voltage setting of the DC power supply 130 (to provide an E-field within the desired range in the MOS dielectric layer 30) depends on the manufacturing process being used for the block The manufacture of bulk CMOS or the manufacture of SOI CMOS.

In FIGS. 6A-6C , the layers of the semiconductor wafer 50 on which the specific layers of the ferroelectric component are formed are collectively referred to as the substrate 20 . Therefore, for a planar FE-FET/SSFEFET or a ferroelectric MOS capacitor, as shown in FIGS. 6A and 6B , the substrate 20 includes all layers formed before the MOS dielectric layer 30 is formed. For an MFM ferroelectric capacitor, as shown in FIG. 6C , the substrate 20 includes all the film layers formed before the formation of the MFM conductive bottom electrode layer 45 .

For a planar FE-FET/SSFEFET or a ferroelectric MOS capacitor, the substrate 20 includes a first semiconductor region 21 of a first conductivity type (for example, p -type), a second semiconductor region 21 of a second conductivity type (for example, n -type). Two semiconductor regions 22, and an insulating region, which is called a shallow trench isolation (STI) region 25, are used to electrically isolate adjacent electronic components. The electronic component may be in any two semiconductor regions (the first semiconductor region 21 and the second semiconductor region 22). As known to those skilled in the art, the conductive top electrode layer 40 over the first semiconductor region 21 and the second semiconductor region 22 may comprise the same material formed by the same process, or comprise the same material formed by a significantly different process. formed of different materials. When using significantly different processes, a variety of different masking steps can be used to mask and expose appropriate areas.

As shown in FIG. 6A, in bulk CMOS, the first semiconductor region 21 of the first conductivity type extends all the way to the backside of the semiconductor wafer 50, while the second semiconductor region 22 of the second conductivity type extends to a depth to form a p - n junction with the first semiconductor region 21 . The p - n junction is often referred to as an n-well-to-p-well junction. As shown in FIG. 6B, in SOI CMOS, the first semiconductor region 21, the second semiconductor region 22, and the STI region 25 are surrounded by an insulating region called a buried oxide (BOX) layer 15 underneath. To terminate, the BOX layer 15 comprises, for example, silicon oxide. As known to those skilled in the art, the semiconductor wafer with the BOX layer 15 may be manufactured using several methods, such as the isolation implantation of oxygen (SIMOX) process, wafer bonding process (such as smart dicing technology), and so on. A doped semiconductor region 12 under the BOX layer 15 extends all the way to the backside of the semiconductor wafer 50 .

As described above with reference to FIGS. 1A and 2 , the backside of the semiconductor wafer 50 and the second terminal of the DC power supply 130 are connected to the ground GND, and the first terminal of the DC power supply is connected to the ground GND using the main wire 110 . The main electrode 211 of the first E field annealer electrode. (For simplicity, monitor electrode 212 and monitor wire 112 are not shown in FIGS. 6A-6C.) As shown in FIGS. 6A and 6B, main electrode 211 is in physical and electrical contact with conductive top electrode layer 40, similar to The cross-sectional view in FIG. 1A and the detailed perspective view in FIGS. 5A and 5B. Thus, the total DC bias voltage supplied by the DC power supply 130 is applied across the conductive top electrode layer 40 and the bottom surface of the semiconductor wafer 50 .

Referring again to FIG. 6A , in bulk CMOS, in the first semiconductor region 21 , the semiconductor side of the MOS dielectric layer 30 has approximately the same potential as the backside of the semiconductor wafer 50 . Thus, the voltage drop across the MOS dielectric layer 30 is a function of the DC bias voltage provided by the DC power supply 130 and the work function between the first semiconductor region 21 and the conductive top electrode layer 40 above this region. The difference is decided. However, in the second semiconductor region 22, the voltage drop across the n-well to p-well junction must be included in the determination of the potential on the semiconductor side of the MOS dielectric layer 30, thereby determining the voltage across the MOS dielectric layer 30. Voltage drop. Thus, by selecting the polarity of the DC bias voltage (supplied by DC power supply 130) such that the pn junction is forward biased to minimize the voltage drop across the n-well to p-well junction, can be beneficial. In one embodiment, the DC bias voltage setting of the DC power supply 130 during the E-field FEA may be about 3V to about _{10V for the MOS dielectric layer 30 with a tox} value of about 10 nm. DC bias can vary widely depending on material, layer thickness, and annealing conditions. The numerical values mentioned above are for illustrative purposes only and should not be construed as limiting.

Referring to FIG. 6B, in SOI CMOS, depending on the ratio of the thickness of the MOS dielectric layer 30 and the BOX layer 15 and the ratio of the dielectric constant, a considerable part of the DC bias voltage supplied by the DC power supply part 130 May drop across BOX level 15. Therefore, the DC bias voltage for E-field FEA in SOI CMOS process flow may have to be increased relative to the corresponding value in bulk CMOS process flow.

Relatively advanced CMOS ICs may use a three-dimensional MOS structure known as a FinFET structure, where typically the gate and gate dielectric wrap around three sides of a thin, long semiconductor fin protruding from a semiconductor substrate. During the E-field FEA described by referring to the planar MOS structure shown in Figures 6A and 6B, the electrical connections to the FE-FET/SSFEFET and MOS ferroelectric capacitors may be adapted by those skilled in the art To implement the E-field FEA corresponding to the FinFET structure.

FIG. 6C illustrates the E-field FEA step performed in a process flow involving the fabrication of MFM ferroelectric capacitors. The MFM ferroelectric capacitor structure in FIG. 6C includes a hafnium oxide based ferroelectric dielectric layer 35 sandwiched between a conductive top electrode layer 40 and a conductive bottom electrode layer 45 . The main electrode 211, shown in contact with the conductive top electrode layer 40, uses the main wire 110 to connect to a first terminal of the DC power supply 130 (not shown). The backside of the semiconductor wafer 50 and the second terminal of the DC power supply 130 are connected to GND, like the semiconductor wafer 50 in FIGS. 6A and 6B . However, as explained below, if the conductive bottom electrode layer 45 becomes effectively electrically isolated from the backside GND of the semiconductor wafer 50 in FIG. 6C by an excessively high cumulative thickness of the dielectric layer in the substrate 20 connections, these connections alone may not be sufficient to generate a suitably high E-field in the ferroelectric dielectric layer 35 of the MFM capacitor.

The MFM capacitor layers, including conductive bottom electrode layer 45, are typically formed during the back end of the line (BEOL) of the IC manufacturing process. Since the substrate 20 in FIG. 6C includes all layers formed below the conductive bottom electrode layer 45, the substrate 20 may include a relatively thick interlayer dielectric physically above the conductive semiconductor and gate layers of the MOSFET. (ILD) layer and intermetal dielectric (IMD) layer. Therefore, unless the conductive bottom electrode layer 45 is connected by vias and contacts to the conductive semiconductor layer and gate layer of the MOSFET shown in FIG. The electrical coupling between the backside and the conductive bottom electrode layer 45 may be too weak to generate a suitably high E-field in the ferroelectric dielectric layer 35 of the MFM capacitor. In such embodiments, a substrate holder in electrical contact with the backside of semiconductor wafer 50, such as substrate holder 10 in FIG. 1A or support plate 230 in FIG. 5A, may not be an effective first embodiment. Two E field annealer electrodes. In such instances, additional processing may be used to create an effective second E field annealer electrode connection, as described below with reference to FIG. 6C.

In IC design, at an intermediate stage of the fabrication process requiring E-field FEA, where the conductive bottom electrode layer 45 is electrically decoupled from the backside of the semiconductor wafer 50, as shown in FIG. 6C, A masking step may be used to pattern the ferroelectric dielectric layer 35 and conductive top electrode layer 40 of the MFM capacitor to expose a portion of the conductive bottom electrode layer 45 . For example, the exposed area of the conductive bottom electrode layer 45 may be in the shape of a ring along the edge of the semiconductor wafer 50 . An additional secondary electrode 214 (an electrode similar in structure to the first E-field annealer electrode 210 shown in the cross-sectional view of FIG. 1A and the detailed perspective views of FIGS. 5A and 5B ) may be placed in contact with the conductive bottom electrode The exposed portions of layer 45 make physical and electrical contact. The secondary electrode 214, serving as a direct electrical connection to the conductive bottom electrode layer 45, may be effectively a second E field annealer electrode connection. As shown in FIG. 6C , an additional secondary electrode 214 can be connected to GND using a secondary wire 114 (similar to the primary wire 110 ). Thus, the entire DC bias voltage drops across the ferroelectric dielectric layer 35 of the MFM capacitor. In one embodiment, the DC _bias voltage setting of the DC power supply 130 may be about 3 V to About 10V. In another embodiment, the DC bias voltage setting may be from about 0.5V to about 3V.

Although, in the description of the embodiment of the E-field annealer, we refer to the application of a DC voltage to the semiconductor wafer 50, in various embodiments, the bias voltage applied during the anneal may be pulsed, cyclic Alternately. In several embodiments, the DC bias voltage may be set relative to a fixed or variable potential other than GND to provide a desired bias voltage across the ferroelectric dielectric layer. For example, all electrodes generating an electric field may not be connected to ground potential, or one of the electrodes may be connected to a floating potential node.

There may be various ways to arrange the E-field annealer to perform the E-field annealing described above. Various embodiments of E field annealer configurations are described with reference to Figures 7A-7B, 8A-8D, 9 and 10A-10C.

7A and 7B illustrate an E-field annealer configuration for heating a semiconductor wafer 50 using conductive heat transfer. Conductive heat transfer is achieved using a heating body placed in direct contact with the semiconductor wafer 50 . The method of conductive heat transfer may use a heating plate included as a heating source, for example, a ceramic heating plate, a metal heating plate, or the like.

A semiconductor wafer 50 includes a substrate 20, a MOS dielectric layer 30 formed on the substrate 20, and a conductive top electrode layer 40 formed on the MOS dielectric layer 30, and the semiconductor wafer 50 is placed in a processing chamber 225 , similar to the configuration described above with reference to FIG. 1A . In FIGS. 7A and 7B, a semiconductor wafer 50 is disposed on a hot plate heat source that is also part of the substrate holder. DC power supply 130 and voltmeter 150 are connected to conductive top electrode layer 40 using main electrode 211 and monitor electrode 212, similar to that shown above in FIG. 1A.

In the E-field annealer configuration 701 shown in FIG. 7A , the semiconductor wafer 50 is disposed on a heating plate 710 . The surface of the heating plate 710 is in physical contact with the backside of the semiconductor wafer 50 . The surface comprises a material that is a good electrical and thermal conductor, eg, a coating comprising a metal or metal-based compound, such as titanium nitride, or a carbon base coating.

In contrast, FIG. 7B shows a configuration 702 in which an E-field annealer can be configured with a heating plate 720 having an electrically insulating but thermally conductive surface. The conductive plate 730 (referred to as the ground plate) comprises an electrically and thermally conductive material (e.g., a metal such as stainless steel, or an element such as tungsten, copper, aluminum, silver, zinc, magnesium, nickel, titanium, tin, or alloys containing such elements), It may be placed on the surface of the heating plate 720 with the semiconductor wafer 50 placed on the conductive plate 730 . The conductive plate 730 material can be selected to be thermally stable during the anneal process while not introducing contaminants into the process chamber. The surface of the heating plate 720 may include ceramics, such as aluminum nitride, aluminum oxide, silicon nitride or silicon carbide.

As shown in FIGS. 7A and 7B , in both configurations 701 and 702 , the backside of the semiconductor wafer 50 may be electrically connected to a common ground (denoted GND) using conductive lines. In some embodiments, conductive portions of the chamber wall 227 may also be electrically coupled to the common ground.

In the configurations 701 and 702 shown in FIGS. 7A and 7B , the E-field annealer can adjust the temperature of the semiconductor wafer 50 by heat conduction between the backside of the semiconductor wafer 50 and the corresponding heating plate 710 or 720. . Heating plates 710 and 720 are provided with a source of thermal energy, schematically depicted by heater 740 . In various embodiments, heater 740 may comprise a resistive or induction heater or a fluid flow through a heat exchanger. In various embodiments, configurations using conductive heat transfer from a heating plate, such as the exemplary configurations 701 and 702, are typically used for relatively long anneals at moderate temperatures, such as 200°C to 600°C.

8A-8D illustrate an E-field annealer configuration that uses radiative heat transfer to transfer energy from a heating source to a semiconductor wafer 50 . Heating sources that can be used in the radiative heat transfer method are insulated resistive wire heaters, heating plates containing ceramic coated resistors, broad-spectrum infrared (IR) and ultraviolet (UV) lamp heaters, and monochromatic emitters in the visible and UV ranges light laser. The radiant heating source may be placed at various locations inside or outside of the processing chamber 225 remotely from the semiconductor wafer 50 . In several embodiments, a scanner may be used to move the semiconductor wafer 50 past the radiation beam emanating from the heating source.

Configurations 801, 802, and 803 (shown in FIGS. 8A, 8B, and 8C, respectively) utilize radiant heat transfer to heat semiconductor wafer 50 from above and below using multiple heating sources. Configuration 804 (shown in FIG. 8D ) uses a laser system 850 providing a laser beam 852 to heat semiconductor wafer 50 from its top side. In configuration 804, semiconductor wafer 50 is scanned by laser beam 852 to expose the entire surface.

Exemplary embodiments of E-field annealer configurations 801 , 802 , 803 , and 804 have a heating source at a location inside processing chamber 225 . However, it should be understood that in several other embodiments, the heating source may be located outside of the processing chamber 225 or attached to the chamber wall 227 .

In E-field annealer configurations 801 , 802 , 803 , and 804 , semiconductor wafer 50 may be placed on raised wafer support 810 , which provides support along the perimeter of semiconductor wafer 50 . The raised wafer support 810 exposes a substantial portion of the top and bottom surfaces of the semiconductor wafer 50 to radiation emitted from heating sources disposed above and below the semiconductor wafer 50 .

In addition, the wafer support 810 can be used to electrically contact the backside of the semiconductor wafer 50 . The backside of semiconductor wafer 50 may be electrically coupled to a common ground by providing a ground connection to wafer support 810, as shown in FIGS. 8A-8D. A good electrical connection can be achieved by using, for example, a wafer support 810 comprising metal or a metal coating. In configurations 801, 802, 803, and 804, the optional ground connection to the chamber wall 227 and the electrical coupling between the semiconductor wafer 50 and the DC power supply 130 and voltmeter 150 may be similar to those described with reference to FIGS. 7A and 7B. Narrator.

The heating sources above and below semiconductor wafer 50 in E-field annealer configurations 801 (FIG. 8A) and 802 (FIG. 8B) comprise resistive heating elements. Configurations using resistive heating elements, such as the example configurations 801 and 802, typically have longer thermal time constants and may use moderate annealing temperatures, such as 200°C to 1000°C.

A resistive heating element 820 used in configuration 801 ( FIG. 8A ) includes a mineral insulated (MI) cable 822 and a cable support 824 . MI cables are semi-rigid resistive heating cables comprising conductive filament resistive elements electrically insulated using thermally conductive minerals such as magnesium oxide. Minerals provide safe electrical insulation even at high annealing temperatures.

In the E-field annealer configuration 802 (FIG. 8B), the resistive heating element 830 comprises a pyrolytic boron nitride (PBN) coated graphite resistor for high temperature capability and extended heater life. High-purity PBN coatings provide electrical insulation, thermal stability, thermal shock resistance, and chemical inertness to graphite components.

FIG. 8C illustrates configuration 803 in which lamp heaters 840 are used to illuminate the top and bottom surfaces of semiconductor wafer 50 to heat them to the annealing temperature. This radiation heats the entire semiconductor wafer 50 and may provide sufficient energy to rapidly heat the semiconductor wafer 50 to very high annealing temperatures (eg, 800°C to 1200°C); thus configuration 803 is suitable for RTP. Lamp heater 840 may comprise an IR lamp or a UV lamp that emits broad spectrum radiation, typically extending into the visible range. IR lamps emit near-infrared light with a very high power density, capable of providing a rapid temperature rise (for example, 200 °C per second). In several embodiments, IR lamps are used for rapid thermal annealing (RTA) with an anneal time of about 1 millisecond to about 10 seconds. RTP with shorter annealing times and requiring faster ramp rates (e.g. 10 ³ °C/s to 10 ⁶ °C/s), called flash lamp annealing (FLA), can be used e.g. The emission curve is achieved by an array of flash xenon arc lamps.

In a further embodiment, lamp heater 840 may comprise a microwave power source, such as a microwave lamp.

Although the exemplary configurations 801, 802, and 803, shown in FIGS. 8A-8C, semiconductor wafer 50 is illuminated from both the top and bottom, in other embodiments, semiconductor wafer 50 may be illuminated from the top or the bottom.

FIG. 8D depicts an exemplary configuration 804 in which the energy or heat source is a laser in a laser system 850 , and the energy is delivered to the semiconductor wafer 50 by radiation of the laser beam 852 . Laser beam 852 is focused to intersect a small area of the surface of semiconductor wafer 50 . Therefore, very high power densities can be achieved using laser heating techniques, which result in localized temperature peaks of about 10 ⁷ °C/s to about 10 ⁹ °C/s, a technique known as laser spike anneal (laser spike anneal, LSA).

As mentioned above, annealing the entire semiconductor wafer 50 may have to be accomplished through the use of a scanner. In various embodiments, the scanning device may move the laser beam 852 or the semiconductor wafer 50 (with moving parts in the wafer support 810 ) or both within the processing chamber 225 . The movement may be a linear scan or a rotational scan in a plane parallel to the major top surface of the semiconductor wafer 50 . In the cross-sectional view of FIG. 8D , laser beam 852 is incident perpendicular to the main top surface of semiconductor wafer 50 . However, in some embodiments, the laser beam 852 may be incident at a high oblique angle so as to intersect the major top surface as a line extending across the entire extent of the semiconductor wafer 50 . This can help reduce scan time by reducing the number of scan directions by one.

FIG. 9 illustrates an exemplary E-field annealer configuration 900 for heating a semiconductor wafer 50 using convective heat transfer. Convective heat transfer is accomplished by using a heating medium to process chamber 225 to transfer heat from a heating source to semiconductor wafer 50 . Convective heat transfer methods that can be used are directly or indirectly heated gas and others.

As shown in FIG. 9 , the processing chamber 225 is configured with a gas inlet tube 910 and a gas outlet tube 920 . A gas flow system including pumps and various gas sources may be used to flow gases (typically inert gases such as nitrogen and argon) over semiconductor wafer 50 . Gas flows into the processing chamber 225 through the gas inlet tube 910 and is removed from the processing chamber 225 through the gas outlet tube 920 . In the example depicted in Figure 9, a heating coil 930 is wrapped around the gas inlet tube 910 and configured to heat the incoming gas. The heater coil 930 can be coupled to a temperature controller to adjust the temperature of the incoming gas to a desired value by adjusting the power supplied to the heater coil 930 . In configuration 900 , heater coil 930 is the heat source and the heated inlet gas transfers thermal energy from heater coil 930 to semiconductor wafer 50 as it flows over the surface of semiconductor wafer 50 .

Figures 10A-10C depict first, second, and third configurations 1001, 1002, and 1003, respectively, each having a multi-wafer processing chamber 1026 (similar to processing chamber 226 described above with reference to Figure IB). As shown in the exemplary embodiment of FIGS. 10A-10C , inside a processing chamber 1026 , a batch of semiconductor wafers 50 are in a vertical stack held by a wafer support structure. The processing chamber 1026 may be shaped as a tube having, for example, quartz chamber walls 1020 and a pedestal 1024 comprising, for example, a metal pedestal supporting a semiconductor wafer support structure. The base plate incorporates electrical feedthroughs to allow electrical connections to be passed through the base plate to the wafer contacts 1018 and 1016, while the base plate maintains a bias source (eg, DC power supply 130) for the applied E-field electrical insulation. As shown in FIGS. 10A-10C , several heating sources 1010 may be used at various locations to uniformly heat the stack of semiconductor wafers 50 to a desired temperature. The wafer support structure may include a refractory material. The refractory material may comprise an insulator such as quartz (eg, wafer support 1022 ) or a conductive material or coating, such as stainless steel or a carbon base coating (eg, wafer support 1028 ). The conductive wafer support 1028 is used because the wafer support structure itself serves as the electrical contact to the backside of the semiconductor wafer 50 within the wafer processing chamber in FIGS. 10B and 10C . As shown in FIGS. 10B and 10C , the conductive wafer support 1028 is connected to GND by an electrical feedthrough that may be insulated from the pedestal 1024 .

In various embodiments, a number of configurations may be used to electrically couple the DC power supply 130 and ground to the stack of semiconductor wafers 50 . In several embodiments, eg, first and second configurations 1001 ( FIG. 10A ) and 1002 ( FIG. 10B ) do not have monitoring electrodes (eg, monitoring electrode 212 in FIG. 1A ) to monitor the potential at semiconductor wafer 50 using voltmeter 150 . In several other embodiments, such as third configuration 1003 ( FIG. 10C ), voltmeter 150 is electrically coupled to monitor electrode 1044 that contacts semiconductor wafer 50 undergoing E-field annealing.

As indicated schematically by the small circles in FIGS. 10A-10C , insulated wires from electrical components outside the processing chamber 1026 can be electrically coupled to electrical components inside the processing chamber 1026 using appropriate insulated connectors located on the base 1024. conductor.

FIG. 10A illustrates electrical coupling in a first configuration 1001 . DC power supply 130 in first configuration 1001 is electrically coupled to main electrode 1040 (similar to main electrode 1040 in FIG. 1B ) using first conductive bus bar 1016 (similar to first conductive bus bar 108 in FIG. 1B ). 215). The common ground (denoted GND) is electrically coupled to the secondary electrode 1042 (similar to the secondary electrode 216 in FIG. 1B ) using the second conductive bus bar 1018 (similar to the second conductive bus bar 109 in FIG. 1B ). The primary electrode is in contact with a portion of the top surface of the semiconductor wafer 50 and the secondary electrode is in contact with a portion of the backside of the semiconductor wafer 50 .

FIG. 10B illustrates the electrical coupling in the second configuration 1002 . In the second configuration 1002 , the DC power supply 130 is coupled to the main electrode 1040 using the first conductive busbar 1016 , similar to the corresponding connection in the first configuration 1001 . However, instead of having a separate second conductive bus bar, one of the wafer supports (eg, wafer support 1028 ) may be used as a conductive bus bar to couple ground to the backside of semiconductor wafer 50 . Thus, in the second configuration 1002 (FIG. 10B), the wafer support 1028 includes a conductive refractory material or coating. As shown in FIG. 10B , the common ground (represented as GND) is electrically coupled to the wafer support 1028 which is in contact with the backside of the semiconductor wafer 50 .

FIG. 10C shows a third configuration 1003 . In the third configuration 1003, the top surface of each of the semiconductor wafers 50 is in contact with two electrodes: main electrode 1040 and monitor electrode 1044 (similar to main electrode 211 and monitor electrode 212 in FIG. 1A). The main electrode 1040 is electrically coupled to the DC power supply 130 by the first conductive bus bar 1016 and the monitor electrode 1044 is electrically coupled to the voltmeter 150 by the second communication bus bar 1018 . As shown in FIG. 10C , the common ground of the third configuration 1003 is electrically coupled to the backside of the semiconductor wafer 50 by a wafer support 1028 comprising a conductive material or coating, similar to that in the second configuration 1002 ( FIG. 10B ). ground connection.

Electrical connections (made using E-field annealer electrodes 210, e.g., main electrode 211 and monitor electrode 212) to the back and top surfaces of semiconductor wafer 50 provide additional advantages for various embodiments of E-field annealer configurations, As described above to incorporate in situ electrical measurements that can be used for process control. For example, the electrical connection may be part of a measurement probe of a process control system configured to measure a current-voltage curve through a layer of the semiconductor wafer 50 during an E-field anneal. In an exemplary embodiment, where E-field annealing is a FEA performed to convert, for example, a deposited hafnium oxide dielectric layer into a stable or metastable polycrystalline ferroelectric hafnium oxide layer, the ramped current-voltage curve may Associated with the formation of a ferroelectric orthorhombic phase in the dielectric layer. For example, the current-voltage curve can be used to detect the point in the film where the remanent polarization (P _R ) intensity saturates, similar to a self-limiting process. The process control system can use such in situ diagnostics with forward control or "virtual metrology" to achieve the desired optimum film properties.

As previously mentioned, E-field annealing may be performed in a separate processing chamber, a processing chamber configured to perform E-field annealing and other processes (such as deposition) simultaneously or sequentially, or in a semiconductor processing system with other chambers E-field annealing chamber in a cluster configuration.

The E-field anneal processing chamber has been described as a separate chamber for various embodiments of E-field annealer configurations. However, a semiconductor processing system may be configured to perform multiple processing techniques using a single processing chamber. For example, in several embodiments, additional gas lines, sensors, radio frequency (RF) sources, RF antennas, DC bias sources, sputtering targets, etc. can be added to expand the configuration of the E-field annealing chamber to expand It functions to perform additional processes such as chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and plasma treatment (eg, plasma pre-clean).

Standalone E-field annealing processing chambers or processing chambers with extended functionality may be included in a cluster configuration of several semiconductor processing chambers. 11A-11C show schematic diagrams of three cluster tools 1101, 1102, and 1103, including modules configured to perform E-field annealing. Additionally, the cluster tool may contain several other modules. For example, plasma etch process chamber 1150 , plasma pre-clean process chamber 1116 , and PVD process chamber 1118 are shown included in cluster tools 1101 , 1102 , and 1103 .

In general, semiconductor wafers (e.g., semiconductor wafer 50) are queued in a load bay to be transferred through equipment front-end module (EFEM) 1130 and loaded into cluster tools (e.g., cluster tools 1101, 1102, and 1103), at It is schematically depicted in Figures 11A-11C. The semiconductor wafers may then be transferred to another module for processing by number of wafer transfer modules 1120 .

FIG. 11A shows a schematic diagram of a cluster tool 1101 including two E-field annealing chambers with extended functionality. In one embodiment, the processing chamber 1110 may be configured to perform PVD processing and E-field annealing, and the processing chamber 1114 may be configured to perform plasma pre-cleaning processing and E-field annealing. Plasma etch processing chamber 1150 , plasma pre-clean processing chamber 1116 , and PVD processing chamber 1118 are also included in cluster tool 1101 as described above.

11B is a schematic diagram of the cluster tool 1102 including an E-field annealing processing chamber 1140, and the cluster tool 1103 (shown in FIG. 11C ) includes two processing chambers 1140 dedicated to performing E-field annealing.

FIG. 11D shows a portion of cluster tool 1102 where both the E-field anneal processing chamber 1140 and the PVD processing chamber 1118 are accessible by wafer transfer module 1120 . The processing chamber 1140 may be similar to the processing chamber 225 in configuration 802 (see FIG. 8B ). Semiconductor wafers can be transferred from one module to another by the wafer transfer robot of the wafer transfer module 1120, as indicated by the double arrows in FIG. 11D. In another portion of the cluster tool, the wafer transfer module 1120 may transfer semiconductor wafers 50 between different pairs of process chambers.

Exemplary embodiments of the invention are summarized here. Other embodiments are also contemplated by this specification as a whole and by the scope of claims filed here. Example 1. A system for processing a semiconductor wafer, wherein the system includes a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to for detachably coupling to the first major surface of the semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode being co-located to apply an electric field in the semiconductor wafer . Example 2. The system of Example 1, wherein the heating source is a heating plate placed under the backside of the semiconductor wafer. Example 3. The system of either of Examples 1 or 2, wherein the heating plate comprises a substrate having an outer surface comprising an electrically insulating layer, and wherein the electrically insulating layer is covered by a conductive plate, the electrically conductive plate is configured to be electrically coupled to the backside of the semiconductor wafer. Example 4. The system of any of Examples 1-3, wherein the heating plate is a conductive material, the heating plate configured to be electrically coupled to the backside of the semiconductor wafer. Example 5. The system of any of Examples 1-4, wherein the heating source comprises a plurality of heating sources configured to radiatively heat the semiconductor wafer. Example 6. The system of any of Examples 1-5, wherein the heating source is disposed outside the processing chamber and configured to heat the semiconductor wafer via radiant heat transfer. Example 7. The system of any of Examples 1-6, wherein the heating source is disposed inside the processing chamber and configured to heat the semiconductor wafer via radiant heat transfer. Example 8. The system of any of Examples 1-7, wherein the heating source comprises a resistive heating source. Example 9. The system of one of Examples 1-8, wherein the heating source comprises a mineral insulated (MI) cable, a resistor coated with ceramic, or a graphite coated with pyrolytic boron nitride (PBN) Resistor. Example 10. The system of any of Examples 1-9, wherein the heating source comprises an infrared (IR) lamp, an ultraviolet (UV) lamp, or a flash arc lamp. Example 11. The system of one of Examples 1 to 10, wherein the electric field is configured to be applied by maintaining a constant voltage across the first electrode and the second electrode, or maintaining a constant voltage across the first electrode and the second electrode A time-varying voltage is applied to the two electrodes, wherein the time-varying voltage includes a pulse voltage or a sinusoidal voltage. Example 12. The system of one of Examples 1-11, wherein the first electrode or the second first electrode is coupled to a floating potential node. Example 13. The system of any one of Examples 1 to 12, further comprising a scanner, wherein the heating source is a source of a laser beam configured to heat the semiconductor crystal intersected by the laser beam A portion of a major surface of a circle, and wherein the scanner is arranged to move the portion of the major surface that intersects the laser beam to expose the entirety of the major surface to the laser beam. Example 14. The system of any one of Examples 1 to 13, further comprising a fluid inlet and a fluid outlet disposed in the processing chamber; and a heating coil configured to heat a fluid flowing into the processing chamber . Example 15. The system of any one of Examples 1 to 14, further comprising: a cluster of modules including a front end module, a wafer transfer module, and a processing module, the processing chamber being part of the processing module. Example 16. A system for processing semiconductor wafers, wherein the system comprises a processing chamber; a heat source; a substrate holder configured to expose a plurality of semiconductor wafers to the heat source; a first bus bar comprising a first plurality of electrodes for contacting a first side of each of the plurality of semiconductor wafers; and a second bus bar including a second plurality of electrodes for contacting a second side of each of the plurality of semiconductor wafers, the The first bus bar and the second bus bar are jointly arranged to apply an electric field in each of the plurality of semiconductor wafers. Example 17. The system of Example 16, wherein the substrate holder is configured to vertically stack the plurality of semiconductor wafers in the processing chamber. Example 18. The system of one of Examples 16 or 17, wherein the first bus bar and the second bus bar are configured to simultaneously apply an electric field in each of the plurality of semiconductor wafers, and wherein the substrate holder A system is configured to simultaneously expose the plurality of semiconductor wafers to the heating source. Example 19. The system of one of Examples 16-18, wherein the substrate holder comprises a quartz wafer support. Example 20. The system of one of Examples 16 to 19, wherein the substrate holder includes a conductive wafer support, and wherein the conductive wafer support includes the second busbar. Example 21. The system of any one of Examples 16 to 20, further comprising a third busbar including a third plurality of electrodes configured to removably contact the first of the plurality of semiconductor wafers. On the side, the third bus bar is coupled to a voltage monitor. Example 22. The system of any of Examples 16-21, further comprising: a cluster of modules including a front end module, a wafer transfer module, and a processing module, the processing chamber being part of the processing module . Example 23. A rapid thermal processing (RTP) system for processing semiconductor wafers, wherein the system comprises an RTP chamber; a substrate holder configured to support a substrate; an electromagnetic energy source configured to heat the substrate held by the substrate holder The substrate supported; a first electrode configured to be detachably coupled to a first side of the substrate, the first electrode coupled to a first potential node; and a second electrode configured to be detachably coupled to an opposite second side of the substrate side, the second electrode is coupled to a second potential node, and the first electrode and the second electrode are co-disposed to apply an electric field through the substrate. Example 24. The system of Example 23, wherein the substrate holder is configured to support a single one of the plurality of semiconductor wafers to be processed in the system. Example 25. The system of either of Examples 23 or 24, further comprising: a first bus bar comprising a first plurality of electrodes and coupled to the first potential node, the first plurality of electrodes comprising the first electrode; and a second a bus bar comprising a second plurality of electrodes comprising the second electrode and coupled to the second potential node, wherein the substrate holder is further configured to support a plurality of semiconductor wafers comprising the substrate , wherein the electromagnetic energy source is positioned to simultaneously heat the plurality of semiconductor wafers, wherein the first plurality of electrodes is positioned to contact a first side of each of the plurality of semiconductor wafers and the second plurality of electrodes is positioned to contact the On the second side of each of the plurality of semiconductor wafers, the first bus bar and the second bus bar are co-located to apply the electric field in each of the plurality of semiconductor wafers.

Example 26. The system of any of Examples 23-25, wherein the source of electromagnetic energy is a flash lamp, a laser, an IR lamp, a UV lamp, or a microwave lamp.

While this invention has been described by reference to illustrative examples, this Methods section is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those of ordinary skill in the art upon reference to the present Methods section. Accordingly, the accompanying claims are intended to cover any such modifications or embodiments.

10: Substrate holder 12: Doped semiconductor region 14: Substrate holder 15: Buried oxide (BOX) layer 20: Substrate 21: The first semiconductor region 22: Second semiconductor region 25: STI area 30:MOS dielectric layer 35: ferroelectric dielectric layer 40: Conductive top electrode layer 45: Conductive bottom electrode layer 50: Semiconductor wafer 100: Loading guide rail 108: the first conduction bus bar 109: Second conductive bus bar 110: Main wire 112: monitoring wire 113: Secondary wire 114: Secondary wire 115: double wire 120: Power feedthrough 130: DC power supply part 140: Ground wire 150: Voltmeter 210: The first E field annealer electrode 211: Main electrode 212: Monitoring electrode 214: Secondary electrode 215: Main electrode 216: Secondary electrode 225: processing chamber 226: processing chamber 227: chamber wall 230: support plate 235: Heat treatment system 236: Heat treatment system 240: buffer wafer 250: insulating ceramic sheet 310: insulated wire 701: Configuration 702: Configuration 710: heating plate 720: heating plate 730: conductive plate 740: heater 801:E field annealer configuration 802:E field annealer configuration 803:E field annealer configuration 804:E field annealer configuration 810: wafer support 820: resistance heating element 822: mineral insulated cable 824: Cable support 830: resistance heating element 840: lamp heater 850:Laser system 852:Laser beam 900:E field annealer configuration 910: Gas inlet pipe 920: Gas outlet pipe 930: heating coil 1001: first configuration 1002: second configuration 1003: The third configuration 1010: heating source 1016: wafer contact 1018: wafer contact 1020: Quartz chamber wall 1022: Wafer support 1024: base 1026: Multi-wafer processing chamber 1028: Wafer support 1040: Main electrode 1042: Secondary electrode 1044: Monitoring electrode 1101: Cluster tools 1102: Cluster tools 1103: Cluster tools 1110: processing chamber 1114: processing chamber 1116: Plasma pre-cleaning process chamber 1118:PVD processing chamber 1120: Wafer transfer module 1130: Equipment front-end module 1140:E field annealing chamber 1150: Plasma etching processing chamber

20: Substrate

30:MOS dielectric layer

40: Conductive top electrode layer

50: Semiconductor wafer

130: DC power supply part

150: Voltmeter

211: Main electrode

212: Monitoring electrode

225: processing chamber

227: chamber wall

701: Configuration

710: heating plate

740: heater

Claims (22)

A system for processing semiconductor wafers, the system comprising: a processing chamber; a heating source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to the first major surface of the semiconductor wafer; and A second electrode coupled to the substrate holder, the first electrode and the second electrode are co-located to apply an electric field in the semiconductor wafer. The system of claim 1, further comprising a control system comprising measuring probes arranged to measure a current-voltage curve passing through a layer of the semiconductor wafer when the electric field is applied, the control system comprising a controller to control the electric field. The system of claim 1, wherein the heating source is a heating plate placed under the backside of the semiconductor wafer. For the system of claim 3, wherein the heating plate comprises a substrate having an outer surface comprising an electrically insulating layer, and Wherein, the electrically insulating layer is covered by a conductive plate, and the conductive plate is configured to be electrically coupled to the backside of the semiconductor wafer. The system of claim 3, wherein the heating plate is a conductive material, and the heating plate is configured to be electrically coupled to the backside of the semiconductor wafer. The system of claim 1, wherein the heating source comprises a plurality of heating sources configured to radiatively heat the semiconductor wafer. The system of claim 1, wherein the heating source is disposed outside the processing chamber and configured to heat the semiconductor wafer through radiant heat transfer. The system of claim 1, wherein the heating source is disposed inside the processing chamber and configured to heat the semiconductor wafer through radiant heat transfer. The system of claim 1, wherein the heating source comprises a resistive heating source. The system of claim 9, wherein the heating source comprises a mineral insulated (MI) cable, a resistor coated with ceramic, or a graphite resistor coated with pyrolytic boron nitride (PBN). The system of claim 1, wherein the heating source comprises an infrared (IR) lamp, an ultraviolet (UV) lamp, or a flash arc lamp. The system according to claim 1, wherein the electric field is arranged to be applied by maintaining a constant voltage across the first electrode and the second electrode, or A time-varying voltage is maintained across the first electrode and the second electrode, wherein the time-varying voltage includes a pulse voltage or a sinusoidal voltage. The system of claim 1, wherein the first electrode or the second electrode is coupled to a floating potential node. The system of claim 1 further includes: a scanner, wherein the heating source is a source of a laser beam arranged to heat a portion of the major surface of the semiconductor wafer intersected by the laser beam, and Wherein the scanner is configured to move the portion of the major surface intersected by the laser beam to expose the entirety of the major surface to the laser beam. The system of claim 1 further includes: a fluid inlet and a fluid outlet disposed in the processing chamber; and A heating coil is configured to heat a fluid flowing into the processing chamber. The system of claim 1 further includes: A cluster of modules includes a front-end module, a wafer transfer module, and a processing module of which the processing chamber is a part. A system for processing semiconductor wafers, the system comprising: a processing chamber; a heating source; a substrate holder configured to expose a plurality of semiconductor wafers to the heat source; a first bus bar comprising a first plurality of electrodes for contacting a first side of each of the plurality of semiconductor wafers; and A second bus bar, including a second plurality of electrodes for contacting a second side of each of the plurality of semiconductor wafers, the first bus bar and the second bus bar are jointly arranged on each of the plurality of semiconductor wafers Apply an electric field. The system of claim 17, wherein the substrate holder is configured to vertically stack the plurality of semiconductor wafers in the processing chamber. The system of claim 17, wherein the first bus bar and the second bus bar are configured to simultaneously apply an electric field in each of the plurality of semiconductor wafers, and wherein the substrate holder is configured to simultaneously apply the plurality of semiconductor wafers. A semiconductor wafer is exposed to the heat source. The system of claim 17, wherein the substrate holder comprises a quartz wafer support. The system of claim 17, wherein the substrate holder includes a conductive wafer support, and wherein the conductive wafer support includes the second bus bar. The system of claim 17 further includes: A third bus bar including a third plurality of electrodes disposed to detachably contact the first side of each of the plurality of semiconductor wafers, the third bus bar coupled to a voltage monitor.

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