JP2022113851A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a semiconductor device including a voltage conversion circuit capable of supplying stable voltage while suppressing a power consumption increase; and a method for controlling such a semiconductor device.

SOLUTION: The semiconductor device comprises: a voltage conversion part which includes a first input part for receiving input of a supply voltage, a second input part for receiving input of a reference voltage, and a third input part for receiving input of a comparison voltage, converts the supply voltage based on comparison between the reference voltage and the comparison voltage, and outputs the converted supply voltage as an output voltage from an output part; a voltage-dividing part, one terminal of which is connected to the output part, and which outputs, as the comparison voltage, from the other terminal to the third input part, a voltage obtained by dividing the output voltage; and a capacitor, one terminal of which is connected to the output part, and the other terminal of which is connected to the third input part. Upon switching of an operation mode from a low-speed mode to a high-speed mode, a decrease in the comparison voltage following a decrease in the output voltage is fed back to the voltage conversion part via the capacitor, and the output voltage increases before charging of the voltage-dividing part is completed.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a memory circuit driven by a built-in voltage conversion circuit (both booster circuit and step-down circuit).

A charge pump is often used when configuring a booster circuit in a semiconductor device having a memory circuit. For example, a variable stage charge pump disclosed in Japanese Unexamined Patent Application Publication No. 2002-200303 is known as a conventional technology of a memory circuit having a power supply circuit using a charge pump. A variable stage charge pump disclosed in US Pat. a second switch coupling the input of to the input of the second charge pump, wherein when the first switch is in the first position and the second switch is in the second position, the first A charge pump and a second charge pump are coupled in series to a common output node and the first charge pump and the second charge pump are coupled to the common output node when the first switch is in the second position and the second switch is in the first position. is coupled in parallel to

Here, as described in Japanese Unexamined Patent Application Publication No. 2002-200002, conventional semiconductor devices tend to use an external power supply voltage for the purpose of reducing power consumption. In addition, in order to improve the withstand voltage of the oxide film and to deal with the issues of flattening (stabilizing) the power supply voltage due to the miniaturization of the semiconductor device process, a power supply that requires an external power supply voltage is installed inside the semiconductor chip. Internal voltage step-down is commonly used.

On the other hand, there are many cases where a voltage higher than the voltage supplied by the power supply is required, such as write, erase, and read operations of flash memory, and in such cases, a charge pump circuit is used as a booster circuit. . A general charge pump circuit is composed of a capacitor for pumping charge and a transfer MOS (Metal Oxide Semiconductor) transistor (field effect transistor) for transferring the pumped charge to prevent backflow and increase the voltage.

Further, in order to control the output voltage of the charge pump to the target boost voltage, a sensor circuit is provided, and the pump operation is stopped when the sensor circuit detects that the voltage exceeds the target while the pump operation is continued. Then, when the sensor circuit detects that the boosted voltage has decreased due to the drive current or leakage current after stopping, the pump operation is restarted. Ringing may occur in the boosted voltage due to the pump operation and its stop and start. In some cases, a step-down power supply circuit that stably supplies voltage is added.

Japanese Patent Publication No. 11-512864

Here, when the sensor circuit is provided as described above, a P-type MOS transistor (hereinafter referred to as a "PMOS transistor") connected between the output of the boosted voltage and the ground (GND) is connected by a diode connection string or a resistance element string. It is common to generate a comparison voltage by a voltage dividing circuit.In this case, the power of the boosted voltage source is consumed by the current flowing through the voltage dividing circuit.For this reason, the microcontroller with flash memory especially at low speed operation For applications that require low current consumption, it is common to restrict the current flowing through the voltage divider circuit in order to meet the operating current standard. When switching from low-speed operation to high-speed operation, the comparison voltage does not immediately follow, and during that time the boosted voltage continues to drop, making reading difficult. Since current flows from the source to the voltage divider circuit, there is a problem that even if the current flowing through the voltage divider circuit is reduced, the loss of operating current is large. This also occurs in a step-down circuit that steps down the boosted voltage from the step-up circuit to supply power.The step-up circuit and the step-down circuit may be collectively referred to as a "voltage conversion circuit" below.

In this regard, the variable stage charge pump disclosed in Patent Document 1 aims to be able to handle different output levels with a given charge pump power supply input level, and has a problem of suppressing current consumption. is not.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a voltage conversion circuit capable of supplying a stable voltage while suppressing an increase in current consumption. aim.

A semiconductor device according to the present invention has a first input to which a first voltage is input and a second input to which a second voltage is input, and based on a comparison between the first voltage and the second voltage, a step-down circuit that outputs a voltage; an output unit that is controlled by the voltage output from the step-down circuit and outputs an output voltage; one end of which is connected to the output unit; a voltage dividing unit for outputting two voltages from the other end to the second input; and a capacitor having one end connected to the output unit and the other end connected to the second input, and operating at a first speed. or a second mode operating at a second speed higher than the first speed.

A semiconductor device according to another aspect of the present invention has a first input to which a first voltage is input and a second input to which a second voltage is input, wherein the first voltage and the second voltage are a step-down circuit that outputs a voltage based on the comparison; an output section that is controlled by the voltage output from the step-down circuit and outputs an output voltage; and one end of which is connected to the output section and divides the output voltage. a voltage dividing unit that outputs a voltage as the second voltage from the other end to the second input; and a discharge circuit connected to the output unit. based on a second mode operating at a second speed higher than the speed of .

According to the present invention, it is possible to provide a semiconductor device including a voltage conversion circuit capable of supplying a stable voltage while suppressing an increase in current consumption.

1A is a block diagram of the semiconductor device according to the first embodiment, and FIG. 1B is a timing chart showing operation waveforms of respective parts; FIG. 8A is a block diagram of a semiconductor device according to a second embodiment, and FIG. 8B is a timing chart showing operation waveforms of respective parts; FIG. 9A is a block diagram of a semiconductor device according to a third embodiment, and FIG. 9B is a timing chart showing operation waveforms of respective parts; FIG. FIG. 11 is a block diagram showing an example of a short circuit of a semiconductor device according to a third embodiment; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the following embodiments, a semiconductor device is a memory device, and a semiconductor device control method is a booster circuit control method for controlling a booster circuit that is incorporated in the memory device and generates a potential required for data access. .

[First embodiment]
A memory device 50 and a booster circuit control method according to the present embodiment will be described with reference to FIG.

As shown in FIG. 1, the memory device 50 includes a booster circuit 52 and a memory section 54 .

The booster circuit 52 includes an oscillation circuit 1, a boost clock generation circuit 2, a charge pump circuit 3, a reference voltage generation circuit 4, a voltage dividing circuit 5, a constant current source circuit 6, a timing generation circuit 7, a sensor circuit 8, a voltage step-down circuit 10, It has a voltage dividing circuit 11 and NMOS transistors 16, 17-1 to 17-4 and 18-1 to 18-4.

The charge pump circuit 3 is a circuit for increasing the voltage by combining a capacitor and a switch that operate in synchronization with the driving clock signal. , as an output voltage VCP.

The boost clock generation circuit 2 converts the clock signal from the oscillation circuit 1 into the driving clock signal for operating the charge pump circuit 3 . The oscillation circuit 1 is an oscillator for the boost clock generation circuit 2 to generate a clock signal that is the source of the drive clock signal. The oscillation circuit 1 is controlled to start/stop by a control signal SAO from the sensor circuit 8 .

The step-down circuit 10 steps down the output voltage VCP to generate a voltage for operating the memory section 54 . In this embodiment, the step-down voltage from the step-down circuit 10 is output via the NMOS transistor 16 as the output voltage VREG. A reference voltage VREF2 from a reference voltage generating circuit 4, which will be described later, is input to the non-inverting input of the step-down circuit 10, and a comparison voltage VDET2, which will be described later, is input to the inverting input. NMOS transistors 17-2 and 18-2 connected in series are connected to the step-down circuit 10. FIG. The NMOS transistor 18-2 is a transistor that supplies a constant current to the step-down circuit 10, and the step-down circuit 10 operates by being supplied with the constant current. The NMOS transistor 17-2 is a switch that controls whether the constant current flows or cuts off.

The voltage dividing circuit 11 divides the output voltage VREG to generate a comparison voltage VDET2. The voltage dividing circuit 11 includes a PMOS diode-connected string 11a and a capacitor 11b. The comparison voltage VDET2 is taken from the middle of the PMOS diode connection string 11a, and the capacitor 11b is connected between the output voltage VREG and the comparison voltage VDET2. Series-connected NMOS transistors 17-1 and 18-1 are connected to the PMOS diode connection string 11a. The NMOS transistor 18-1 is a transistor that supplies a constant current to the PMOS diode-connected series 11a, and the PMOS diode-connected series 11a operates by being supplied with the constant current. The NMOS transistor 17-1 is a switch that controls whether the constant current flows or cuts off.

A voltage dividing circuit 5 divides the output voltage VCP to generate a comparison voltage VDET which is a monitor voltage of the output voltage VCP. The configuration of the voltage dividing circuit 5 is not particularly limited, and is composed of a PMOS diode-connected string, a resistor string, or the like, but in this embodiment, it is a PMOS diode-connected string. NMOS transistors 17-3 and 18-3 connected in series are connected to the voltage dividing circuit 5. FIG. The NMOS transistor 18-3 is a transistor that supplies a constant current to the voltage dividing circuit 5, and the voltage dividing circuit 5 operates by being supplied with the constant current. The NMOS transistor 17-3 is a switch that controls whether the constant current flows or cuts off.

The reference voltage generating circuit 4 generates the reference voltage VREF2 and the reference voltage VREF to be supplied to the sensor circuit 8. FIG. The reference voltage generation circuit 4 is controlled to start/stop by a deep power down signal DPPDN. Deep power-down according to the present embodiment means power-down that stops the operation of most of the circuits associated with the memory device 50 among power-downs, and is supplied from a control circuit or the like (not shown). The deep power down signal DPPDN is an example of a control signal, and other appropriate control signals may be used.

The sensor circuit 8 monitors the voltage level of the output voltage VCP and generates a control signal SAO for controlling the oscillation circuit 1 according to the monitored voltage level. NMOS transistors 17-4 and 18-4 connected in series are connected to the sensor circuit 8. FIG. The NMOS transistor 18-4 is a transistor that supplies a constant current to the sensor circuit 8, and the sensor circuit 8 operates by being supplied with the constant current. The NMOS transistor 17-4 is a switch that controls whether the constant current flows or cuts off.

The timing generation circuit 7 is connected to the gates of the NMOS transistors 17-1 to 17-4, and controls on/off of the NMOS transistors 17-1 to 17-4 by an activation signal ENSA. A constant current source circuit 6 is connected to the gates of the NMOS transistors 18-1 to 18-4, and supplies a bias voltage VBIAS for causing constant currents to flow through the NMOS transistors 18-1 to 18-4. Timing generation circuit 7 and constant current source circuit 6 are controlled by deep power down signal DPPDN. The sources of the NMOS transistors 18-1 to 18-4 are connected to the ground (GND).

The memory section 54 includes a plurality of memory cells 30 and a driver circuit 9 that drives the plurality of memory cells 30 . The driver circuit 9 supplies a necessary voltage to the word line connected to the memory cell 30 based on the decoded signal obtained by decoding the address signal. For example, if the memory device 50 is a flash memory with advanced miniaturization, the output voltage VREG generated by the booster circuit 52 is supplied to the word line of the memory cell 30 through the driver circuit 9 to perform a read operation. The memory device 50 according to the present embodiment has a low speed operation mode for low speed reading and a high speed operation mode for high speed reading.

Next, the operation of the booster circuit 52 will be described with reference to FIG. 1(b). FIG. 1B is a timing chart showing operation waveforms of the deep power down signal DPPDN, the charge pump output voltage VCP, the step-down circuit output voltage VREG, and the decode signal. When the deep power down signal DPPDN is released, the timing generation circuit 7, constant current source circuit 6, sensor circuit 8, voltage dividing circuit 5, step-down circuit 10, voltage dividing circuit 11, and reference voltage generating circuit 4 are activated. .

When the deep power down signal DPPDN is released at time t1, the reference voltage generator circuit 4 generates the reference voltage VREF, the constant current source circuit 6 generates the bias voltage VBIAS of the constant current source, and the timing generator circuit 7 generates the activation signal. ENSA occurs. The sensor circuit 8 and the voltage dividing circuit 5 receive the activated bias voltage VBIAS and the activation signal ENSA and start operating.

The control signal SAO, which is the output signal of the sensor circuit 8, is maintained until the comparison voltage VDET generated from the voltage dividing circuit 5 becomes greater than the reference voltage VREF, that is, until the output voltage VCP of the charge pump circuit 3 becomes greater than the boost target voltage VPWL. High level (hereinafter referred to as "H"). The oscillation circuit 1 continues to generate a clock signal while the control signal SAO is H, and drives the charge pump circuit 3 via the boost clock generation circuit 2 .

When the voltage of the output voltage VCP of the charge pump circuit 3 reaches the boost target voltage VPWL, the control signal SAO becomes low level (hereinafter referred to as "L"), and the control of the output voltage VCP shifts to intermittent operation under the control of the sensor circuit 8. .

On the other hand, the step-down circuit 10 and the voltage dividing circuit 11 also receive the activated bias voltage VBIAS and the activation signal ENSA and start operating to converge the output voltage VREG to the target voltage VWL.

When the memory device 50 shifts from low-speed operation to high-speed operation at time t2, the current consuming the output voltage VREG by the driver circuit 9 increases rapidly, the balance of the step-down circuit 10 is lost, and the output voltage VREG drops temporarily. When the output voltage VREG drops, the coupling action of the capacitor 11b lowers the node voltage of the comparison voltage VDET2 and raises the gate voltage of the NMOS transistor 16, which is the output driver of the step-down circuit 10. At time t3, the output voltage VREG rises. to start.

After that, the PMOS diode-connected string 11a completes the charging necessary for the comparison voltage VDET2 to become the divided voltage of the output voltage VREG, so the output voltage VREG is controlled to the target voltage VWL (time t4). The effect of the output voltage from time t2 to t4 is called voltage drop amount ΔVWL.

As described in detail above, according to the semiconductor device and the control method of the semiconductor device according to the present embodiment, when the load of the output voltage VREG is switched to the high load associated with the high-speed operation mode, the PMOS diode connection row 11a Before the charging of the comparison voltage VDET2 to the divided voltage of the output voltage VREG is completed, the output voltage VREG starts to rise, so the voltage drop amount ΔVWL of the output voltage VREG can be reduced. Therefore, it is possible to reduce the current flowing through the PMOS diode-connected row 11a, so that both reduction in operating current and stabilization of memory cell readout (stabilization of the output voltage VREG) can be achieved.

[Second embodiment]
A memory device 50A and a booster circuit control method according to the present embodiment will be described with reference to FIG. A memory device 50A according to the present embodiment has a form in which the booster circuit 52 of the memory device 50 is replaced with a booster circuit 52A. Therefore, similar configurations are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 2A, the booster circuit 52A is obtained by adding a timing generator circuit 13 and a discharge circuit 12 to the booster circuit 52. As shown in FIG.

A timing generation circuit 13 receives a mode signal FMODE and generates a discharge signal DISC according to the mode signal FMODE. The mode signal FMODE defines the read operation speed of the memory device 50A on which the booster circuit 52A is mounted. When the mode signal FMODE is L, it is in a low speed operation (read) mode, and when it is H, it is in a high speed operation (read) mode.

The discharge circuit 12 comprises a PMOS diode-connected string 12a and an NMOS transistor 12b connected to the output voltage VREG. A discharge signal DISC is input to the gate of the NMOS transistor 12b, and the discharge circuit 12 is activated when the NMOS transistor 12b is turned on by the discharge signal DISC.

The operation of the booster circuit 52A will be described with reference to FIG. 2(b). FIG. 2(b) is a timing chart showing operation waveforms of the deep power down signal DPPDN, the charge pump output voltage VCP, the voltage step-down circuit 10 output voltage VREG, the mode signal FMODE, the discharge signal DISC, and the decode signal. be.

When the deep power-down signal DPPDN is released at time t1, the output voltage VCP of the charge pump circuit 3 and the output voltage VREG of the step-down circuit operate in the same manner as described with reference to FIG. 1(b). In the example of FIG. 2B, at time t2, a low-speed decode signal is input.

After that, when the mode signal FMODE switches from the low-speed operation mode to the high-speed operation mode at time t3, the discharge signal DISC becomes H immediately after that, and a load current approximately equal to the load current during high-speed operation flows through the discharge circuit 12. .

After the output voltage VREG converges to the target voltage VWL, the discharge signal DISC becomes L at time t4, and high speed operation (reading) is started. A period in which the discharge signal DISC is H is set as a high-speed operation setup period SUT, and the high-speed read operation is prohibited.

According to the memory device and booster circuit control method according to the present embodiment, the high-speed operation setup time can be shortened during high-speed switching, and after the high-speed operation setup period SUT, the output voltage VREG can be stably set regardless of the amount of voltage drop ΔVWL of the output voltage VREG. A read operation can be performed.

In the present embodiment, the configuration including the capacitor 11b in addition to the discharge circuit 12 has been described as an example. good too.

[Third Embodiment]
A booster circuit control method for the memory device 50B and the booster circuit 52B according to the present embodiment will be described with reference to FIG. In the present embodiment, the booster circuit 52 in the memory device 50 is changed to a booster circuit 52B. A voltage dividing circuit 20 according to the present embodiment has a shorting circuit 14 and a timing generating circuit 15 added to the voltage dividing circuit 11 . Since other configurations are the same as those of the memory device 50, similar configurations are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 3A, the voltage dividing circuit 20 includes a PMOS diode-connected string 11a, a capacitor 11b, and a short circuit .

The short circuit 14 is connected between the terminal for outputting the divided voltage VDET3 of the PMOS diode-connected string 11a and the terminal of the capacitor 11b on the comparison voltage VDET2 side. The short circuit 14 is controlled by an activation signal ENSK described below, and functions as a switch that connects or disconnects the PMOS diode connection string 11a and the capacitor 11b.

FIG. 4 shows a specific circuit example of the short circuit 14. As shown in FIG. The short circuit 14 has a pass transistor (transfer gate) 21 and an inverter 22 . Based on the activation signal ENSK, the terminal of the divided voltage VDET3 and the terminal of the comparison voltage VDET2 are connected or disconnected. According to the short circuit 14, noise is canceled by the PMOS transistor and the NMOS transistor. Therefore, when the short circuit 14 is turned off (cut off), the coupling noise causes the potential of the comparison voltage VDET2 to fluctuate, causing the activation signal ENSK. is effective in suppressing deviation of the control voltage of the output voltage VREG during the L period.

The timing generation circuit 15 receives the deep power down signal DPPDN and outputs an activation signal ENSK. The activation signal ENSK is supplied to the gate of the NMOS transistor 17-1 and the short circuit 14 to control the operations of the NMOS transistor 17-1 and the short circuit 14. FIG.

Next, the operation of the booster circuit 52B will be described with reference to FIG. 3(b). FIG. 3B is a timing chart showing operation waveforms of the deep power down signal DPPDN, the output voltage VCP of the charge pump circuit 3, the output voltage VREG of the step-down circuit 10, and the activation signal ENSK.

The activation signal ENSK output from the timing generation circuit 15 has an activation period that is the period from when the deep power-down signal DPPDN becomes L to when the output voltage VREG of the step-down circuit 10 converges to the target voltage VWL. T1 is set to H (between times t1 and t2). When the activation signal ENSK is set to H, the short circuit 14 becomes conductive and the NMOS transistor 17-1 is turned on. After that, the activation signal ENSK is set to the period H of the activation period T3 at the interval of the activation period T2 from the time t3 (from the time t3 to t4). In FIG. 3B, the activation cycle T2 is started at times t5 and t6.

While the activation signal ENSK is L, the short circuit 14 is cut off, the charge stored in the capacitor 11b maintains the comparison voltage VDET2, and controls the output voltage VREG toward the boost target voltage VPWL. The charge stored in the capacitor 11b decreases due to leakage between the electrodes of the capacitor 11b and leakage from the diffusion layer of the short circuit 14, and the control voltage of the output voltage VREG drops. By recharging the capacitor 11b during the activation period T3 (ie every activation period T2), control of the output voltage VREG is maintained towards convergence to the target voltage VWL.

According to the present embodiment, in addition to the effects similar to those of the above-described embodiment, the current flowing through the voltage dividing circuit 20 can be cut off except for the activation period T3 during operation. Even considering the increase in current consumption due to the timer operation of the circuit 15, it is possible to further reduce the operating current. In addition, compared to the intermittent operation of a conventional voltage dividing circuit that does not have the capacitor 11b, the output voltage VREG drops due to the current flowing through the voltage dividing circuit 20 during the activation period T2 excluding the activation period T3. Furthermore, since the output voltage VREG can be constantly controlled even during the intermittent operation period, the activation period T2 (intermittent period) can be lengthened and the operating current can be reduced.

1 Oscillation circuit 2 Boost clock generation circuit 3 Charge pump circuit 4 Reference voltage generation circuit 5 Voltage division circuit 6 Constant current source circuit 7 Timing generation circuit 8 Sensor circuit 9 Driver circuit 10 Voltage reduction circuit 11 Voltage division circuit 11a PMOS diode connection string 11b Capacitance 12 discharge circuit 12a PMOS diode connection string 12b NMOS transistor 13 timing generation circuit 14 short circuit 15 timing generation circuit 16, 17-1 to 17-4, 18-1 to 18-4 NMOS transistor 20 voltage dividing circuit 21 pass transistor 22 OR circuit 30 memory cells 50, 50A, 50B memory devices 52, 52A, 52B booster circuit 54 memory section

Claims (6)

a step-down circuit having a first input to which a first voltage is input and a second input to which a second voltage is input, and outputting a voltage based on a comparison between the first voltage and the second voltage;
an output unit that is controlled by the voltage output from the step-down circuit and outputs an output voltage;
a voltage dividing unit having one end connected to the output unit and outputting a voltage obtained by dividing the output voltage as the second voltage from the other end to the second input;
a capacitor having one end connected to the output section and the other end connected to the second input;
with
A semiconductor device that operates based on a first mode operating at a first speed or a second mode operating at a second speed higher than the first speed. 2. The semiconductor device according to claim 1, further comprising a discharge circuit connected to said output section. 2. The semiconductor device according to claim 1, further comprising a short circuit having one end connected to said voltage divider and the other end connected to said capacitor, and connecting or disconnecting said voltage divider and said capacitor. a step-down circuit having a first input to which a first voltage is input and a second input to which a second voltage is input, and outputting a voltage based on a comparison between the first voltage and the second voltage;
an output unit that is controlled by the voltage output from the step-down circuit and outputs an output voltage;
a voltage dividing unit having one end connected to the output unit and outputting a voltage obtained by dividing the output voltage as the second voltage from the other end to the second input;
a discharge circuit connected to the output;
with
A semiconductor device that operates based on a first mode operating at a first speed or a second mode operating at a second speed higher than the first speed. a memory cell;
5. The semiconductor device according to claim 1, further comprising a driver circuit supplied with said output voltage to drive said memory cell. 6. The semiconductor device according to claim 5, wherein said first mode is a mode for reading said memory cells at low speed, and said second mode is a mode for reading said memory cells at high speed.

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