JPH0235694A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To realize a fast operation and to stably perform a low voltage operation by performing pre-charge by energizing either a p-channel transistor or an n-channel transistor selectively replying to a control signal. CONSTITUTION:A pre-charge circuit 10 is constituted of the parallel circuit of the p-channel transistor 5 and the n-channel transistor 7, and the pre-charge is performed by energizing either the p-channel transistor 5 or then-channel transistor 7 selectively replying to the control signals S1 and S2. Therefore, the pre-charge of a bit line can be performed by performing the fast operation by the n-channel transistor 7 and a slow operation by the p-channel transistor 5. In such a way, it is possible to stably perform the low voltage operation as realizing the fast operation.

Description

[Detailed description of the invention] Industrial field of application Prior art (Figs. 4 to 7) Problems to be solved by the invention Examples of means and actions for solving the problems Explanation of the principle of the invention (Fig. 1) Book One embodiment of the invention (Figure 2.3) Effects of the invention [Summary] Regarding a semiconductor memory device, an object of the present invention is to provide a semiconductor memory device that is capable of high-speed operation and stable low-voltage operation. , in a semiconductor memory device in which a plurality of memory cells are arranged and equipped with a precharge circuit for precharging a bit line to which these memory cells are connected, the precharge circuit includes a P-channel transistor, an N-channel transistor, and a precharge circuit; The precharge is performed by selectively turning on one of the P-channel transistor and the N-channel transistor in response to a control signal.

[Industrial Application Field] The present invention relates to a semiconductor memory device, and more specifically, in a MOS transistor circuit for a system that requires low power consumption operation, the present invention uses a transistor that is advantageous for high-speed operation and a low power transistor as a precharging transistor. The present invention relates to a semiconductor memory device that selectively uses transistors that are advantageous for voltage operation.

When high-speed operation is not required for low-power operation in battery-operated electrical products, etc., there is a demand for semiconductor memory devices that can operate at lower operating speeds and lower electric-tx lightning voltages. .

[Prior Art] Recently, there has been an increasing trend for home appliances that utilize microcomputers to be equipped with timers. Along with this, clock functions have become necessary, and low power consumption has also become essential. Low power consumption requires battery backup to keep the CPU running when a power outage occurs, for example, and battery backup requires semiconductor storage devices to operate with low power consumption. In such a case, the power consumption is generally reduced by lowering the clock frequency for precharging (in the case of CMO3, the power consumption itself is dependent on the clock) and by lowering the voltage. However, when operating at a low voltage, speed is sacrificed to some extent, and once the speed is satisfied, it is no longer possible to reduce power consumption.

As a conventional precharge transistor of this type of ROM, for example, a p-channel MOS transistor shown in FIG. 4.5 is generally used. FIG. 4 is a diagram showing part of a circuit for precharging bit lines in a ROM. In this figure, ■ is a bit line, and 2a to 2n are word lines.
N-channel MO3I-transistors (hereinafter simply referred to as n-channel transistors) 4a to 4n constituting the transistors are connected, and the n-channel transistors 4a to 4n are connected in series to the bit line l.

Data writing is performed by depletion ion implantation method 2, and n-channel transistors (memory transistors) 4a to 4a corresponding to data “1°° (or “°0°”)
4n is ion-implanted with impurities to make it into a depletion type and short-circuited. The n-channel transistor 4a is connected to a power supply (2) via a P-channel MO3 transistor (hereinafter simply referred to as a p-channel transistor) 5 for precharging. . The n-channel transistor 4n is connected to the ground via the n-channel transistor 6. A clock signal φ is applied to the gates of p-channel transistor 5 and n-channel transistor 6, and when clock φ is applied at a low level, P-channel transistor 5 is turned on and bit line 1 is precharged. The succession of data is carried out by the n-channel transistor 4 selected by the word lines 2a to 2n.
The gates of only 8 to 4n are set to ``0'' level, the others are set to high level, and it is determined whether they are always on (depression) state or not, and data II 1 0 is read out. Although the explanation focuses on related circuits, the same applies to other bit lines (not shown).In the case of a circuit using this p-channel transistor 5, it is similar to a circuit using an n-channel transistor described later. Since no significant voltage drop occurs, the voltage drop in Figure 5 (a
), the bit line I is precharged to a level close to the power supply voltage VDO and operates. The discharge time in this case is determined by the capacitance, resistance, etc. of the next stage, but as shown in Figure 5(b), when operating at high speed (that is, when the clock frequency is increased) is not suitable for high-speed operation because of its long discharge time. However, when operating at a low voltage, the output level is stable because the voltage drop is small.

Also, the sixth transistor is used as a ROM precharge transistor.
There is one that uses an n-channel MOS transistor shown in FIG. FIG. 6 is a diagram showing a part of a circuit for precharging the bit line in the ROM, and the same components as those shown in FIG. 4 are given the same numbers and their explanation will be omitted.

In this figure, 7 is an n-channel transistor for precharging the bit line, and a clock signal φ is inputted to the gate of the n-channel transistor 7 via an inverter 8. This n-channel transistor 7
In the case of a circuit using n, as shown in Figure 7(a')
The precharge voltage is set to VD by channel transistor 3.
Since the voltage drop is lower than 11, discharge can be performed in a short time. Therefore, operation can be guaranteed even if the frequency is increased to a certain extent, making it suitable for high-speed operation. However, when this circuit is operated at a low voltage, the output level tends to fall below the threshold level as shown in Figure 7(b) due to the voltage drop mentioned above, so this type of circuit is not suitable for high-speed operation. However, it is not suitable for low voltage operation.

[Problem to be solved by the invention]

However, in such conventional semiconductor memory devices, the circuit that precharges with an n-channel transistor guarantees high-speed operation at normal voltage, but the problem is that operation becomes unstable when operating at low voltage. In addition, a circuit that precharges using an n-channel transistor has no voltage drop and can operate at a low voltage, but has the problem that the operating speed becomes slow during high-speed operation.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that is capable of high-speed operation and stable low-voltage operation.

[Means to solve the problem]

In order to achieve the above object, a semiconductor memory device according to the present invention includes a precharge circuit in which a plurality of memory cells are arranged and a precharge circuit for precharging a bit line to which these memory cells are connected. The charging circuit is constituted by a parallel circuit of a P-channel transistor and an n-channel transistor, and performs the precharging by selectively turning on one of the n-channel transistor and the n-channel transistor in response to a control signal. It is equipped with a semiconductor memory device.

[Function] In the present invention, the precharge transistor that precharges the memory cell with a predetermined current is configured by a parallel circuit of an n-channel transistor and an n-channel transistor, and the n-channel transistor and the n-channel transistor are connected in response to a control signal. is configured such that one of the two is selectively conductive.

Therefore, bit lines are precharged by the n-channel transistor during high-speed operation and by the n-channel transistor during low-speed operation, making it possible to perform high-speed operation and stable low-voltage operation.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a diagram illustrating the principle of a semiconductor device according to the present invention. FIG. 1 is a diagram showing a part of a circuit for precharging a bit line in a ROM, and the same components as those in the conventional example shown in FIG. 4.6 are given the same numbers and explanations are omitted. In FIG. 1, a memory cell 3 is connected to a power supply VDII via a precharge circuit 10 consisting of a parallel circuit of an n-channel transistor 7 and an n-channel transistor 5, and an OR gate is connected to the gate of the n-channel transistor 7. 11 and an inverter 8, and a clock signal φ is applied to the gate of the n-channel transistor 5 via an OR gate 12. At one end of the OR gates 11 and 12, selection signals (control signals) St and S2 are respectively provided to precharge the bit line 1 by selectively conducting one of the n-channel transistor 7 and the p-channel transistor 5. The selection signal 31. Only when S2 is applied at a low level, the n-channel transistor 7 or the p-channel transistor 5 becomes conductive to precharge the bit line 1. Sl and 82 are signals representing the operating mode, and the circuit shown in Fig. 1 can be used in the same way as the ROM shown in Figs. 4 and 6 as conventional examples, except for inputting the operating mode. .

Therefore, in the present invention, an N-channel transistor 7 having characteristics as shown in FIG. 7 and a P-channel transistor 5 having characteristics as shown in FIG.
1.12, it is switched in response to the control signals S1 and S2 input to the ROM, and it is possible to operate both the normal voltage high speed operation mode and the low voltage low speed operation mode more stably by using the same method as a conventional ROM. can.

Next, an actual semiconductor memory device based on the above basic principle will be described as an example. 2.3 are diagrams showing one embodiment of the present invention, FIG. 2 is a block configuration diagram showing an example of application to a microprocessor, and FIG. 3 is a ROM configuration diagram thereof. In FIG. 2, 21 is a microprocessor, and the microprocessor 21 has a CPU 22 and a built-in ROM 2.
3. It is composed of an operation mode control section 24 and a clock selector 25.

Two types of high and low clocks with different frequencies are input to the clock selector 25, and the clock selector 25 selects two types of high and low clocks based on the selection signal from the operation mode control unit 24 and stores the selected clocks in the built-in ROM 23 as a clock signal. Output. The operation mode control unit 24 is the CPU 2
Based on the operation mode set in step 2, two modes, high-speed operation and low-speed operation, are switched and outputted to the operation mode input terminal of the built-in ROM 23 as the operation mode (see 31 and S2 in FIG. 1). Built-in ROM23 is the memory part (
The memory cell section) is the same (common) as that of the conventional example,
A transistor for precharging is selected according to the operation mode input to the operation mode input terminal. That is, by selecting n-channel transistor 7 during high-speed operation and selecting p-channel transistor 5 during low-speed operation, both high-speed operation and low-voltage operation of built-in ROM 23 are achieved.

Further, the built-in ROM 23 stores a predetermined program and data, and the contents of the specified address are read out according to the address and read signal sent from the CPU 22.
Send to U22. The CPU 22 controls the system by setting an operation mode for switching the precharging transistor in the built-in ROM 23 in response to changes in the clock frequency or power supply voltage. The CPU 22 determines the internal state of the system based on external information (not shown), and sets the optimal operating mode based on this.

FIG. 3 is a detailed configuration diagram of the built-in ROM 23, and the same components as the circuit shown in FIG. 1.2 are given the same reference numerals. In this figure, the main clock φ is input to the OR gate 11.12 via the inverter 21, and the main clock φ inverted by the inverter 31 is inverted again by the inverters 32 to 39 and connected to each memory cell 3. The data is input to the n-channel transistor 6. An inverted signal of clock φ is applied to the gate of n-channel transistor 7 via OR gate 1, and an inverted signal of clock φ is applied to the gate of P-channel transistor 5 via OR gate 12 and inverter 8. There is. In addition, this built-in ROM 23 has two clocks, a main clock φ and a clock clock.
The switching is performed in synchronization with the operation of the CPU 22 (not shown).

In the above configuration, first, the precharge transistors are changed to P channel transistors 5 and n according to the purpose of use.
Select one of the channel transistors 7.

Under normal conditions, the precharge/discharge of the memory cell 3 is performed by only one of the p-channel transistor 5 and the n-channel transistor 7, and under specific conditions, the
PU22 outputs select signals S1 and S2 to OR gate 1.
1.12 so that both the P channel transistor 5 and the N channel transistor 7 are used.

As explained above, in this embodiment, high-speed operation and low-voltage operation are performed stably, so it can be applied to a system that requires low power consumption operation, such as when boosting a pantry bank. This can greatly contribute to the stable operation of the circuit.

〔Effect of the invention〕

According to the present invention, during high-speed operation, n
Since a channel transistor is selected and an n-channel transistor is selected during low-speed operation, high-speed operation and low-voltage operation can be performed stably.In systems that require low power consumption operation, circuit stability is achieved. You can plan your actions.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining the principle of the semiconductor memory device according to the present invention, FIG. 2.3 is a diagram showing a first embodiment of the semiconductor memory device according to the present invention, and FIG. FIG. 3 is a block configuration diagram showing an example of application to a microprocessor, FIG. 3 is a ROM configuration diagram thereof, and FIGS. 4 to 7 are diagrams showing a conventional semiconductor memory device. FIG. Figure 5 is a diagram for explaining the operation of a ROM that uses the P-channel transistor for precharging, Figure 6 is a diagram that shows the configuration of the ROM that uses the N-channel transistor for precharging, FIG. 7 is a diagram for explaining the operation of a ROM using the n-channel transistor for precharging. DESCRIPTION OF SYMBOLS 1...bit line, 2a-2n...word line, 3...memory cell, 4a-4n...n-channel transistor, 5...
・・・・・・n channel transistor, 7・・・・・・n
Channel transistor, 8.31-39... Inverter, 10... Precharge circuit, 11.12... OR gate, 21... Semiconductor storage device, 22...CPU. 23...Built-in ROM, 24...Operation mode control section, 25...Clock selector. Agent Patent Attorney Tei Iji 2a-2n: Word line 3, memory cell 8 Inverter IO precharge circuit /I, /2: Brosso configuration diagram showing an example of application of one embodiment of OR gate to a microprocessor Figure 2 teeth:

Claims (1)

[Claims] A semiconductor memory device including a plurality of memory cells arranged and a precharge circuit for precharging a bit line to which these memory cells are connected, wherein the precharge circuit is a p-channel transistor. , n
A semiconductor memory device comprising a parallel circuit with a channel transistor, and performing the precharging by selectively turning on one of the p-channel transistor and the n-channel transistor in response to a control signal.