JP2022113497A - Determination method of clock frequency of frequency synthesizer - Google Patents

Abstract

To provide a method for simply suppressing the signal level of a spurious signal contained in an output signal of a frequency synthesizer.SOLUTION: A determination method of a clock frequency of a frequency synthesizer includes the steps of: generating a first spurious characteristic; and generating a second spurious characteristic. In the step of generating the first spurious characteristic, a frequency difference relation between the frequency of an oscillation signal and the N-th spurious frequency generated in the oscillation signal due to the N-th harmonic contained in a DDS signal with respect to a settable clock frequency is identified and plotted. In the step of generating the second spurious characteristic, data of the smallest frequency difference is extracted for each clock frequency in the first spurious characteristic. The method further includes a step of determining a clock frequency of a clock signal of the frequency synthesizer, and determines the clock frequency of the frequency synthesizer on the basis of a value of the frequency difference indicated by the second spurious characteristic.SELECTED DRAWING: Figure 3

Description

The present invention relates to a method for determining the clock frequency of a frequency synthesizer.

Conventionally, there is known a frequency synthesizer that uses a signal output from a direct digital synthesizer (DDS) as an input signal for a PLL (Phase Locked Loop) circuit (see Patent Document 1, etc.). The DDS can arbitrarily change its output frequency in fine steps. For this reason, the PLL method using the DDS adjusts the frequency of the signal input to the phase comparator, which is a component of the PLL circuit, that is, the frequency of the oscillation signal output from the PLL circuit while keeping the comparison frequency high. This method is advantageous in terms of phase noise and lockup time.

JP-A-10-22825

The DDS output signal contains spurious due to harmonics of the signal's frequency. Spurs can appear in large numbers near the frequency of the output signal of the DDS due to aliasing. In particular, if the spurious frequency falls within the loop filter band of the PLL circuit, the output signal from the PLL circuit will also contain the spurious, which may cause performance degradation of equipment that operates based on the output signal. There is

In order to reduce such spurious, it is necessary to determine whether or not the output signal output from the PLL circuit includes spurious of a predetermined level or higher, and whether or not the magnitude of spurious is at an allowable level, as in Patent Document 1. Frequency synthesizers are known that determine However, in such a frequency synthesizer, processing for outputting an oscillation signal with reduced spurious is complicated, and it takes a long time to complete the operation.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to easily suppress the signal level of spurious signals contained in the output signal of a frequency synthesizer.

In a first aspect of the present invention, a clock signal source that outputs a clock signal, a DDS that outputs a DDS signal based on the clock signal output from the clock signal source, and the DDS that is output from the DDS. and a PLL circuit that outputs an oscillation signal having a frequency set with reference to the frequency of the signal. and the frequency of the N-order spurious generated in the oscillation signal due to the N-order harmonic (N is a natural number of 2 or more) contained in the DDS signal. generating a spurious characteristic; extracting data of the smallest frequency difference for each clock frequency in the first spurious characteristic to generate a second spurious characteristic; determining the clock frequency of the clock signal of the frequency synthesizer based on the frequency difference value.

In the step of determining the clock frequency, the clock frequency of data showing the maximum value of the frequency difference among the second spurious characteristics may be determined as the clock frequency of the clock signal.

In the step of determining the clock frequency, the clock frequency of data showing the maximum value of the frequency difference among the second spurious characteristics may be determined as the clock frequency of the clock signal.

In the PLL circuit, specifying a detuning frequency characteristic indicating a frequency characteristic of a spurious gain with respect to a frequency distant from the frequency of the oscillation signal; In the step of determining the clock frequency, the clock frequency of the data of the frequency difference exceeding the specified first detuning frequency of the second spurious characteristic is specified as the It may be determined as the clock frequency of the clock signal.

The step of generating the first spurious characteristic and the step of generating the second spurious characteristic are repeated to generate and generate the second spurious characteristic for each frequency of the DDS signal to be output by the DDS. plotting all of the second spurious characteristics and then extracting data of the smallest frequency difference for each of the clock frequencies to generate the second spurious characteristics common to the frequencies of the DDS signals to be output; may be further provided.

ADVANTAGE OF THE INVENTION According to this invention, it is effective in the ability to suppress the spurious signal level contained in the output signal of a frequency synthesizer simply.

1 shows a configuration example of a frequency synthesizer 10 according to this embodiment. An example of gain detuning frequency characteristics of spurious generated in the PLL circuit 130 according to the present embodiment is shown. 1 shows a first example of an operation flow for determining the clock frequency of the frequency synthesizer 10 according to this embodiment. An example of the first spurious characteristic of the PLL circuit 130 according to this embodiment is shown. An example of the second spurious characteristic of the PLL circuit 130 according to the present embodiment is shown. A second example of an operation flow for determining the clock frequency of the frequency synthesizer 10 according to this embodiment is shown. An example of the result of plotting a plurality of second spurious characteristics according to the present embodiment is shown. An example of a second spurious characteristic common to a plurality of DDS signals according to the present embodiment is shown.

<Configuration Example of Frequency Synthesizer 10>
FIG. 1 shows a configuration example of a frequency synthesizer 10 according to this embodiment. The frequency synthesizer 10 outputs an oscillation signal with a set frequency while reducing the spurious signal level. The frequency synthesizer 10 includes a clock signal source 110 , a direct digital synthesizer (DDS) 120 , a PLL circuit 130 and a controller 140 .

A clock signal source 110 outputs a clock signal. The clock signal source 110 is, for example, a clock signal source capable of outputting a clock signal with a frequency designated by the control section 140 . The clock signal source 110 outputs a clock signal with a clock frequency between 1500 MHz and 2000 MHz, for example. The clock signal output by the clock signal source 110 serves as the reference clock signal for the DDS 120 .

DDS 120 outputs a DDS signal based on the clock signal output from clock signal source 110 . The DDS 120 outputs a DDS signal having a frequency indicated by the setting data received from the control section 140 . The frequency of the DDS signal is, for example, a frequency between 600 MHz and 700 MHz. Since the operation of the DDS 120 outputting the DDS signal is known, the explanation is omitted here.

The DDS signal output by the DDS 120 may contain spurious due to the Nth harmonic (N is a natural number of 2 or more) of the DDS signal. Such high-order spurious is generated when the Nth harmonic is folded back at the clock frequency. Therefore, the frequency at which the spurious occurs varies depending on the frequency of the DDS signal, the order of harmonics, and the clock frequency. In this embodiment, the spurious caused by the N-order harmonic of the DDS signal is called the N-order spurious or the spurious.

The PLL circuit 130 outputs an oscillation signal having a frequency set with reference to the frequency of the DDS signal output from the DDS 120 . The PLL circuit 130 outputs, for example, an oscillation signal having a frequency that is a multiple of the DDS signal. A frequency output from the PLL circuit 130 is, for example, a frequency between 6000 MHz and 7000 MHz. PLL circuit 130 has voltage controlled oscillator 132 , frequency divider 134 , phase comparator 136 and loop filter 138 .

The voltage controlled oscillator 132 outputs an oscillation signal with a frequency corresponding to the input voltage. The voltage controlled oscillator 132 includes, for example, a crystal oscillator and a variable capacitance diode, and adjusts the frequency of the oscillation signal by changing the capacitance value of the variable capacitance diode based on the input voltage. Voltage controlled oscillator 132 generates an oscillation signal having a frequency set based on the DDS signal output from DDS 120 and the division ratio of frequency divider 134 . The voltage controlled oscillator 132 outputs the generated oscillation signal to the outside and supplies it to the frequency divider 134 . The oscillation signal contains spurious caused by the spurious contained in the DDS signal.

Frequency divider 134 divides the frequency of the oscillation signal output from voltage controlled oscillator 132 . The frequency dividing ratio of the frequency divider 134 is ten as an example. Note that the frequency divider 134 may be a frequency divider with a variable frequency division ratio. In this case, the frequency divider 134 divides the frequency of the oscillation signal by the frequency division ratio set by the control section 140, for example. The frequency divider 134 supplies a frequency-divided signal obtained by dividing the oscillation signal to the phase comparator 136 .

Phase comparator 136 outputs to loop filter 138 a voltage corresponding to the phase difference between the phase of the DDS signal output from DDS 120 and the phase of the frequency-divided signal output from frequency divider 134 . Loop filter 138 converts the voltage output from phase comparator 136 into a control voltage for controlling voltage controlled oscillator 132 and outputs the control voltage. Loop filter 138 is, for example, a low-pass filter. Since the operation of the PLL circuit 130 as described above is known, a more detailed description will be omitted.

The control unit 140 controls the clock signal source 110, the DDS 120, and the PLL circuit 130 to output an oscillation signal having a set frequency from the voltage controlled oscillator 132. FIG. Control unit 140 has acquisition unit 142 , storage unit 144 , and setting unit 146 .

The acquisition unit 142 acquires setting data for the frequency of the oscillation signal output by the frequency synthesizer 10 . The acquisition unit 142 acquires, for example, setting data input by a user or the like to an input device or the like. Alternatively, the acquisition unit 142 may acquire setting data supplied from an external circuit or the like.

The storage unit 144 stores information about set values that can be set for the clock signal source 110 , the DDS 120 , and the PLL circuit 130 . The storage unit 144 stores, for example, combinations of setting values such as the clock frequency of the corresponding clock signal, the frequency of the DDS signal, and the division ratio of the PLL circuit 130 in association with the frequency of the oscillation signal to be output. The combination will be described later. In addition, the storage unit 144 may store set values, threshold values, parameters, and the like used by the control unit 140 for control operations.

The setting unit 146 sets setting values for the clock signal source 110, the DDS 120, and the PLL circuit 130, respectively. For example, the setting unit 146 reads, from the storage unit 144, a combination of setting values of each unit corresponding to the frequency of the oscillation signal indicated by the setting data acquired by the acquiring unit 142, and sets the read setting values to each unit.

The control unit 140 described above is desirably configured by an integrated circuit or the like. For example, the control unit 140 includes an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor), and/or a CPU (Central Processing Unit).

When at least part of the control unit 140 is configured by a computer or the like, the storage unit 144 may be, for example, a ROM (Read Only Memory) that stores a BIOS (Basic Input Output System) of a computer or the like that implements the control unit 140, and a RAM (Random Access Memory) that serves as a work area. In addition, the storage unit 144 may store various information including an OS (Operating System), an application program, and/or a database referenced when the application program is executed. The storage unit 144 may include a large-capacity storage device such as a HDD (Hard Disk Drive) and/or an SSD (Solid State Drive). A processor such as a CPU functions as the control unit 140 by executing a program stored in the storage unit.

The frequency synthesizer 10 described above uses a combination of the clock frequency of the clock signal stored in the storage unit 144, the frequency of the DDS signal, and the division ratio of the PLL circuit 130 to generate an oscillation signal corresponding to the acquired setting data. to output Here, the frequency of the DDS signal and the set value of the division ratio of the PLL circuit 130 are determined according to the frequency of the oscillation signal to be output. For example, when the frequency of the oscillation signal to be output indicated by the setting data is 6000 MHz, the setting value of the frequency of the DDS signal is 600 MHz, and the setting value of the division ratio of the PLL circuit 130 is 10.

The output signal of the DDS 120 of the frequency synthesizer 10 contains spurious caused by harmonics of the frequency of the signal. Spurs can appear in large numbers near the frequency of the output signal of the DDS due to aliasing. In particular, when the spurious frequency is within the band of the loop filter in the PLL circuit 130, the output signal from the PLL circuit also contains the spurious.

FIG. 2 shows an example of detuning frequency characteristics of spurious gain generated in the PLL circuit 130 according to the present embodiment. The horizontal axis of FIG. 2 indicates the frequency away from the frequency of the oscillation signal as the detuning frequency Δf, and the vertical axis indicates the gain when spurious occurs at the detuning frequency Δf. The spurious gain frequency characteristic is a detuning frequency characteristic that indicates the gain frequency characteristic for a signal with a frequency away from the frequency of the oscillation signal in the PLL circuit 130 .

As shown in FIG. 2, the spurious gain becomes a smaller value as the detuning frequency Δf increases due to the attenuation characteristic of the loop filter 138 of the PLL circuit 130 . Therefore, even if spurious occurs, if the position of the generated frequency is farther than the frequency of the oscillation signal, the signal level of the spurious is reduced. Therefore, for example, it is desirable that the frequency at which spurious occurs is a frequency that is at least the cutoff frequency of the loop filter 138 away from the frequency of the oscillation signal.

The frequency at which the spurious occurs varies depending on the frequency of the DDS signal, the order of harmonics, and the clock frequency. Therefore, for example, by appropriately setting the clock frequency for each frequency of the DDS signal, the spurious signal level can be reduced. Therefore, a method of determining the clock frequency of the clock signal that further reduces the spurious signal level of the frequency synthesizer 10 will be described below.

<Example of determining the clock frequency for each frequency of the DDS signal>
FIG. 3 shows a first example of the operational flow for determining the clock frequency of the frequency synthesizer 10 according to this embodiment. The operation flow shown in FIG. 3 is executed, for example, in the manufacturing process of the frequency synthesizer 10 . The operation flow may be executed by the control unit 140 of the frequency synthesizer 10 or alternatively by a computer such as a server separate from the frequency synthesizer 10 . In this embodiment, the clock frequency that can be set is 1500 MHz to 2000 MHz, the frequencies of the DDS signal output by the DDS 120 are 600 MHz, 650 MHz, and 700 MHz, and the frequencies of the oscillation signal output by the PLL circuit 130 are 6000 MHz, 6500 MHz, and 7000 MHz.

First, the computer generates a first spurious characteristic (S210). The first spurious characteristic is a clock frequency characteristic obtained by specifying and plotting the relationship between the frequency difference between the frequency of the oscillation signal and the frequency of the N-order spurious contained in the DDS signal with respect to the settable clock frequency. Here, the frequency difference between the frequency of the oscillation signal and the frequency of the N-order spurious is defined as the spurious detuning frequency, or simply the frequency difference.

FIG. 4 shows an example of first spurious characteristics of the PLL circuit 130 according to this embodiment. The horizontal axis of FIG. 4 indicates the clock frequency, and the vertical axis indicates the spurious detuning frequency. Here, the DDS signal of the DDS 120 is assumed to be 600 MHz, and the frequency of the oscillation signal output from the PLL circuit 130 is assumed to be 6000 MHz. FIG. 4 shows an example of the result of plotting the positions of frequencies at which 2nd-order to 10th-order spurious are generated with respect to the clock frequency, with reference to the frequency of the oscillation signal.

The computer may generate the first spurious characteristic using a measuring device or the like connected to itself, or alternatively may generate such a first spurious characteristic using simulation. For example, assuming that the frequency of the DDS signal is F _DDS and the difference between the frequency of the DDS signal and the frequency of the N-order spurious is F _{delta, Np, Fsn} (F _DDS ), the difference is calculated as follows. Here, Np is the spurious order, _Fsn is the clock frequency of the clock signal, floor() is a function for rounding off decimal places, and mod(x, y) is a function for obtaining the remainder when x is divided by y. do.

(Number 1)
F _{delta, Np, Fsn} (F _DDS )=
−F _DDS +mod {floor(F _DDS *Np/(F _sn /2)), 2}*{(F _sn /2)−mod(F _DDS *Np,F _sn /2)}
+[1-mod{floor( _FDDS *Np/( _Fsn /2)),2}]*mod( _FDDS *Np, _Fsn /2)

Here, the frequency of the oscillation signal is equal to the result of multiplying the frequency FDDS of the _DDS signal by the division ratio Mm. Therefore, the computer multiplies the difference F _{delta, Np, Fsn} (F _DDS ) calculated by the equation (1) by the frequency division ratio Mm to obtain the frequency of the oscillation signal output from the PLL circuit 130 and the oscillation It is possible to calculate the spurious detuning frequency that indicates the difference from the frequency of the Nth-order spurious contained in the signal. FIG. 4 is a diagram showing the relationship between the clock frequency and the spurious detuning frequency when the division ratio Mm is 10. In FIG. From FIG. 4, it is possible to identify how far each spurious frequency is from the frequency of the oscillation signal with respect to the set clock frequency.

Next, the computer extracts data of the smallest frequency difference for each clock frequency in the first spurious characteristic to generate the second spurious characteristic (S220). FIG. 5 shows an example of the second spurious characteristic of the PLL circuit 130 according to this embodiment. FIG. 5 shows the result of extracting data with the smallest spurious detuning frequency for each clock frequency in the first spurious characteristic shown in FIG. From FIG. 5, the spurious frequency closest to the frequency of the oscillation signal can be specified for the set clock frequency.

Next, the computer determines the clock frequency of the clock signal for the frequency synthesizer 10 based on the value of the frequency difference indicated by the second spurious characteristic (S230). For example, the computer determines the clock frequency of the data showing the maximum frequency difference among the second spurious characteristics as the clock frequency of the clock signal.

In the example of FIG. 5, for example, the clock frequency F1 at which the spurious detuning frequency becomes the maximum value is determined as the clock frequency corresponding to the oscillation frequency of 6000 MHz of the PLL circuit ₁₃₀ (the frequency of the DDS signal is 600 MHz). Thereby, the spurious detuning frequency closest to the frequency of the oscillation signal output from the PLL circuit 130 can be maximized, and the signal level of the spurious can be suppressed most.

Further, the computer may determine the clock frequency of the data showing the maximum value of the frequency difference among the second spurious characteristics as the clock frequency of the clock signal. In the example of FIG. 5, the clock frequencies F ₂ , F ₃ , . may be determined. As a result, the spurious detuning frequency closest to the frequency of the oscillation signal output from the PLL circuit 130 can be increased, and the signal level of the spurious can be further suppressed.

If there is another frequency of the DDS signal to be output by the DDS 120 (S240: Yes), the computer returns to S210 to determine the clock frequency corresponding to the other frequency. The computer repeats the operations of S210 to S230 to determine clock signals corresponding to, for example, 650 MHz and 700 MHz DDS signals, respectively.

When the computer determines the clock signal corresponding to the frequency of the DDS signal to be output by the DDS 120 (S240: No), the computer associates the determined clock frequency information with the frequency of the oscillation signal, and stores the information in the storage unit 144 of the frequency synthesizer 10. (S250). As described above, the storage unit 144 of the frequency synthesizer 10 stores appropriate clock signal information for reducing the spurious signal level.

Therefore, when the frequency synthesizer 10 is operated, the control unit 140 can read data indicating the clock frequency corresponding to the frequency of the oscillation signal from the storage unit 144 and set an appropriate clock frequency for the clock signal source 110. . Thus, the frequency synthesizer 10 can easily suppress the spurious signal level contained in the output signal of the frequency synthesizer without performing complicated control operations.

Then, for example, even if the frequency synthesizer 10 acquires setting data indicating any one of frequencies of 6000 MHz, 6500 MHz, and 7000 MHz, the frequency synthesizer 10 reads data indicating the corresponding clock frequency from the storage unit 144 and selects an appropriate clock frequency. can be set by switching to As a result, the frequency synthesizer 10 can easily suppress the spurious signal level according to a plurality of settings, even if a plurality of frequencies of the oscillation signal to be output can be set.

<Example of determining a common clock frequency>
In the frequency synthesizer 10 according to the present embodiment described above, an example in which the clock frequency is determined for each frequency of the DDS signal has been described, but the present invention is not limited to this. The computer may determine a common clock frequency that suppresses spurious signal levels for the oscillation signals of multiple frequencies to be output.

FIG. 6 shows a second example of the operational flow for determining the clock frequency of the frequency synthesizer 10 according to this embodiment. In the operation flow of the second example, the same reference numerals are given to the operations that are substantially the same as those of the operation flow of the first example according to the present embodiment shown in FIG. 3, and the description thereof will be omitted.

In the case of the operation flow of the second example, the computer generates a second spurious characteristic for each frequency of the DDS signal that the DDS 120 should output. For example, the computer repeats the step of generating a first spurious characteristic (S210) and the step of generating a second spurious characteristic (S220) to generate DDS signals of frequencies of 600 MHz, 650 MHz, and 700 MHz to be output by the DDS 120. Generate three corresponding second spurious characteristics.

The computer repeats the operations of S210 and S220 when there is another frequency of the DDS signal to be output by the DDS 120 (S310: Yes). Then, when the DDS 120 generates the second spurious characteristic corresponding to the frequency of the DDS signal to be output (S310: No), the computer performs the next operation of S320.

After plotting all of the generated second spurious characteristics, the computer extracts the data with the smallest frequency difference for each clock frequency to generate the second spurious characteristics common to the frequencies of the DDS signals to be output ( S320). FIG. 7 shows an example of plotted results of a plurality of second spurious characteristics according to this embodiment. The horizontal axis of FIG. 7 indicates the clock frequency, and the vertical axis indicates the spurious detuning frequency.

FIG. 7 shows the result of plotting two second spurious characteristics when the frequencies of the DDS signal are 650 MHz and 700 MHz in addition to the second spurious characteristics shown in FIG. From FIG. 7, it is possible to specify how far the frequency of each spurious generated in the oscillation signal of a plurality of frequencies is apart from the frequency of the oscillation signal with respect to the set clock frequency.

Then, the computer extracts the data with the smallest frequency difference for each clock frequency among the plurality of second spurious characteristics shown in FIG. 7 to generate the second spurious characteristics common to the plurality of DDS signals. FIG. 8 shows an example of second spurious characteristics common to a plurality of DDS signals according to this embodiment. The horizontal axis of FIG. 8 indicates the clock frequency, and the vertical axis indicates the spurious detuning frequency. From FIG. 8, it is possible to specify the frequency of the spurious that is closest to the frequency of the oscillation signal among the spurious that occur in the oscillation signals of a plurality of frequencies with respect to the set clock frequency.

Then, the computer determines the clock frequency of the clock signal for the frequency synthesizer 10 based on the value of the frequency difference indicated by the common second spurious characteristic (S330). In the case of the example of FIG. 8, for example, the clock frequency F _MAX (1683 MHz) at which the spurious detuning frequency becomes the maximum value is determined as the common clock frequency corresponding to a plurality of oscillation frequencies.

As a result, the frequency synthesizer 10 can easily suppress the spurious signal levels contained in the oscillation signals of a plurality of frequencies, for example, simply by setting the clock frequency of the clock signal source 110 to the common clock frequency _FMAX . Instead of the clock frequency F _MAX , the clock frequency at which the spurious detuning frequency becomes the maximum value may be determined as the common clock frequency.

Note that the clock signal source 110 may be configured as a signal source that supplies only clock signals having a common clock frequency to the DDS 120 . This eliminates the need for the control section 140 to set the clock frequency to be output to the clock signal source 110 . Therefore, the frequency synthesizer 10 can suppress spurious signal levels generated in oscillation signals of a plurality of frequencies by a simpler control operation.

In the frequency synthesizer 10 according to the present embodiment described above, an example of suppressing the signal level of second-order to tenth-order spurious signals generated in the oscillation signal has been described, but the present invention is not limited to this. The signal level of higher order spurs may be suppressed by generating a first spurious characteristic plotting 11th order and higher spurs, alternatively, the first spurious characteristic plotting spurs of order less than 10th order may be suppressed. may be generated to suppress the signal level of spurs below the 10th order. In addition, even-order or odd-order spurious signal levels may be suppressed.

In the frequency synthesizer 10 according to the present embodiment described above, an example in which the clock frequency of the clock signal is determined based on the maximum value or local maximum value of the spurious detuning frequency of the second spurious characteristic has been described, but the present invention is not limited to this. no. The signal level of the spurious can be reduced if the frequency where the spurious is generated is farther away from the frequency of the oscillation signal. good too. For example, the clock frequency may be determined so that the spurious detuning frequency has a maximum value or a value near the maximum value.

Also, the clock frequency may be determined within a range in which the value of the spurious detuning frequency matches the required specifications. For example, the computer determines the clock frequency over which spurious detuning frequency values exceed a predetermined detuning frequency. Here, the predetermined detuning frequency may be specified from the frequency characteristics of the spurious gain shown in FIG.

In this case, for example, the computer, prior to the operation of S230 or S330 described above, identifies the detuning frequency characteristic that indicates the frequency characteristic of the spurious gain with respect to the frequency that is distant from the frequency of the oscillation signal, as shown in FIG. . The computer identifies such a detuning frequency characteristic by measuring the frequency characteristic of the PLL circuit 130 using, for example, a measuring device or the like connected to itself. Alternatively, the computer may use simulation to identify such detuning frequency characteristics.

Next, the computer identifies a first detuning frequency that is equal to or less than a predetermined gain in the detuning frequency characteristics. For example, when the spurious gain is -70 dB or less, the computer uses the detuning frequency characteristic shown in FIG. 2 to specify a value of 10 MHz as the first detuning frequency. The predetermined gain is input into the computer by, for example, a computer operator, user, or the like. Also, the predetermined gain may be stored in the storage unit 144 .

Then, in the operation of S230 or S330 described above, the computer determines, as the clock frequency of the clock signal, the clock frequency of the data whose frequency difference exceeds the specified first detuning frequency among the second spurious characteristics. For example, the computer determines the clock frequency in the range where the spurious detuning frequency exceeds the first detuning frequency of 10 MHz. In this case, the computer uses data over 10 MHz in the second spurious characteristic of FIG. 5 or FIG. 8 to determine the clock frequency. As a result, the gain at the frequency of the spurious generated in the oscillation signal can be made equal to or less than the predetermined gain of the gain characteristics of the PLL circuit 130, so the spurious can be easily suppressed.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes are possible within the scope of the gist thereof. be. For example, all or part of the device can be functionally or physically distributed and integrated in arbitrary units. In addition, new embodiments resulting from arbitrary combinations of multiple embodiments are also included in the embodiments of the present invention. The effect of the new embodiment caused by the combination has the effect of the original embodiment.

10 frequency synthesizer 110 clock signal source 120 DDS
130 PLL circuit 132 voltage controlled oscillator 134 frequency divider 136 phase comparator 138 loop filter 140 control unit 142 acquisition unit 144 storage unit 146 setting unit

Claims (5)

A clock signal source that outputs a clock signal, a DDS that outputs a DDS signal based on the clock signal output from the clock signal source, and a frequency that is set based on the frequency of the DDS signal output from the DDS A method for determining the clock frequency of the clock signal of a frequency synthesizer, comprising:
The frequency of the oscillation signal and the frequency of the Nth order spurious generated in the oscillation signal due to the Nth harmonic (N is a natural number of 2 or more) included in the DDS signal, relative to the settable clock frequency generating a plotted first spurious characteristic identifying the difference relationship;
extracting data of the smallest frequency difference for each clock frequency in the first spurious characteristic to generate a second spurious characteristic;
determining the clock frequency of the clock signal of the frequency synthesizer based on the value of the frequency difference indicated by the second spurious characteristic. 2. The method according to claim 1, wherein, in the step of determining the clock frequency, the clock frequency of the data exhibiting the maximum value of the frequency difference among the second spurious characteristics is determined as the clock frequency of the clock signal. 3. The clock frequency of the clock signal according to claim 1, wherein, in the step of determining the clock frequency, the clock frequency of data showing the maximum value of the frequency difference among the second spurious characteristics is determined as the clock frequency of the clock signal. Method. identifying, in the PLL circuit, a detuning frequency characteristic indicating a frequency characteristic of a spurious gain with respect to a frequency distant from the frequency of the oscillation signal;
identifying a first detuning frequency that is equal to or less than a predetermined gain in the detuning frequency characteristic;
In the step of determining the clock frequency, the clock frequency of the data of the frequency difference exceeding the specified first detuning frequency among the second spurious characteristics is determined as the clock frequency of the clock signal. Item 4. The method according to any one of Items 1 to 3. repeating the step of generating the first spurious characteristic and the step of generating the second spurious characteristic to generate the second spurious characteristic for each frequency of the DDS signal to be output by the DDS;
After all of the generated second spurious characteristics are plotted, data of the smallest frequency difference is extracted for each of the clock frequencies to generate the second spurious characteristics common to the frequencies of the DDS signals to be output. further comprising the step of
5. A method according to any one of claims 1-4.

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