JP2017212543A - Selection method, manufacturing method and frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency synthesizer capable of accelerating frequency switching, while suppressing spurious contained in an output signal.SOLUTION: A selection method includes a first step of specifying the detuning frequency characteristics indicating the gain for an oscillation signal, of a signal outputted from a PLL circuit 4, for each of multiple combinations of the frequency of a DDS signal outputted from a DDS3, and the division ratio in the PLL circuit 4, a second step of specifying the relation of the frequency of a DDS signal, and the signal level up to an N-order spurious contained in the DDS signal, a third step of specifying the detuning frequency characteristics from the frequency of an oscillation signal to an N-order spurious generated in a predetermined range, a fourth step of specifying the signal level of spurious of the oscillation signal, for each of multiple combinations, and a fifth step of selecting one of multiple combinations corresponding to the frequency of the oscillation signal, based on the signal level of the specified spurious.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a selection method, a manufacturing method, and a frequency synthesizer.

  Conventionally, a signal output from a direct digital synthesizer (DDS) is used as an input signal of a PLL (Phase Locked Loop) circuit. The DDS can arbitrarily change its output frequency in minute steps. For this reason, the PLL system using the DDS adjusts the frequency of the signal input to the phase comparator, which is a component of the PLL circuit, that is, the frequency of the oscillation signal output from the PLL circuit while keeping the comparison frequency high. This method is advantageous in terms of phase noise and lock-up time.

  However, the output signal of the DDS includes spurious due to harmonics of the frequency of the signal. Many spurs may appear near the frequency of the output signal of the DDS due to aliasing. In particular, when the spurious frequency falls within the loop filter band of the PLL circuit, the output signal from the PLL circuit also includes spurious, which may cause performance degradation of devices that operate based on the output signal. There is.

  Therefore, in Patent Document 1, a frequency divider is provided in a reference oscillator that outputs an output signal based on DDS, and a frequency dividing ratio of the frequency divider in the reference oscillator and a frequency divider in the PLL circuit are divided. There has been disclosed a frequency synthesizer that makes it possible to determine whether or not a spurious level of a predetermined level or higher is included in an output signal output from a PLL circuit when a frequency ratio is set.

Japanese Patent Laid-Open No. 10-22825

  The frequency synthesizer described in Patent Document 1 needs to determine whether or not the magnitude of spurious included in the output signal is an allowable level when the selected division ratio is used after the division ratio is selected. As a result, it took time for the determination to set the division ratio. Therefore, there is a problem that the required level for the lock-up time of the PLL is increased by the time required for the determination in the frequency synthesizer switching process.

  Therefore, the present invention has been made in view of these points, and provides a frequency division ratio selection method for providing a frequency synthesizer capable of speeding up frequency switching while suppressing spurious included in an output signal. The purpose is to do. It is another object of the present invention to provide a frequency synthesizer capable of speeding up frequency switching while suppressing spurious included in an output signal, and a method for manufacturing the same.

  A selection method according to a first aspect of the present invention includes a direct digital synthesizer, and a PLL circuit that outputs an oscillation signal having a frequency set based on a frequency division ratio of the DDS signal output from the direct digital synthesizer. , For each of a plurality of combinations of the frequency of the DDS signal and the division ratio, a detuned frequency characteristic indicating a gain of the signal output from the PLL circuit with respect to the oscillation signal is specified. A first step, a frequency of the DDS signal, and a signal level up to an Nth order spurious (N is a natural number of 2 or more) caused by an Nth order harmonic (N is a natural number of 2 or more) included in the DDS signal; And a predetermined range from the frequency of the oscillation signal output from the PLL circuit. A third step of identifying a detuning frequency up to the Nth order spurious generated in the first, a detuning frequency characteristic, a signal level up to the Nth order spurious, and the Nth order spurious for each of the plurality of combinations. A fourth step of identifying a spurious signal level at a detuning frequency within the predetermined range from the frequency of the oscillation signal based on the detuning frequency up to, and the oscillation identified for each of the plurality of combinations And a fifth step of selecting one combination from a plurality of combinations corresponding to the frequency of the oscillation signal, based on a spurious signal level at a detuning frequency within the predetermined range from the signal frequency.

  In the selection method, in the fourth step, a maximum signal level is specified among signal levels of harmonic spurious up to the Nth order spurious at a detuning frequency within the predetermined range from the frequency of the oscillation signal. May be.

  In the selection method, in the second step, based on the minimum and maximum values of the frequency division ratio that can be taken in the PLL circuit and the minimum and maximum values of the frequency that can be taken by the oscillation signal, A minimum value and a maximum value of the frequency may be specified, and the frequency of the DDS signal may be changed from the minimum value to the maximum value to specify the signal level up to the Nth order spurious included in the DDS signal.

  In the selection method, in the first step, the detuning frequency characteristic is specified for each of the plurality of combinations at each of a plurality of frequencies that the oscillation signal can take, and in the third step, the oscillation is performed. For each of a plurality of frequencies that can be taken by a signal, a detuning frequency from the frequency to the Nth order spurious generated within the predetermined range is specified, and in the fourth step, a plurality of oscillation signals that can be taken by the oscillation signal For each of the frequencies, a signal level corresponding to harmonic spurious up to the Nth order spurious at the detuned frequency within the predetermined range is specified, and in the fifth step, each of the plurality of frequencies that the oscillation signal can take On the other hand, one combination may be selected from the plurality of combinations.

  A frequency synthesizer manufacturing method according to a second aspect of the present invention outputs a direct digital synthesizer and an oscillation signal having a frequency set based on a frequency division ratio of the DDS signal output from the direct digital synthesizer. A frequency synthesizer having a PLL circuit, wherein, in the frequency synthesizer, a signal output from the PLL circuit for each of a plurality of combinations of the frequency of the DDS signal and the frequency division ratio, A first step of specifying a detuning frequency characteristic indicating a gain with respect to the oscillation signal, a frequency of the DDS signal, and an Nth order spurious attributed to an Nth order harmonic (N is a natural number of 2 or more) included in the DDS signal. Second step of specifying a relationship with a signal level up to (N is a natural number of 2 or more) A third step of specifying a detuning frequency from the frequency of the oscillation signal output from the PLL circuit to the Nth order spurious generated within a predetermined range, and the detuning frequency characteristics for each of the plurality of combinations And a spurious signal level at a detuning frequency within the predetermined range from the frequency of the oscillation signal based on the signal level up to the Nth order spurious and the detuning frequency up to the Nth order spurious. One of the plurality of combinations corresponding to the frequency of the oscillation signal, based on the step and the spurious signal level at the detuning frequency within the predetermined range from the frequency of the oscillation signal specified for each of the plurality of combinations. A fifth step of selecting a combination and before corresponding to the selected one combination The frequency and the division ratio of the DDS signal, in association with the frequency of the oscillation signal, and a sixth step of storing in a storage unit in which the frequency synthesizer has.

  A frequency synthesizer according to a third aspect of the present invention includes a direct digital synthesizer, and a PLL circuit that outputs an oscillation signal having a frequency set based on a frequency division ratio of the DDS signal output from the direct digital synthesizer. A storage unit that stores a combination of the frequency of the DDS signal and the division ratio at which the spurious of the oscillation signal is equal to or lower than a predetermined level in association with each of the plurality of frequencies of the oscillation signal that can be output by the PLL circuit And a setting unit that sets the frequency of the DDS signal corresponding to the combination associated with the selected frequency and the frequency division ratio upon receiving selection of the frequency of the oscillation signal.

  According to the present invention, it is possible to provide a frequency synthesizer capable of speeding up frequency switching while suppressing spurious included in an output signal.

It is a circuit block diagram of the frequency synthesizer concerning this embodiment. It is a flowchart which shows the flow of the process which concerns on manufacture of a frequency synthesizer. It is an example of calculation of a closed loop gain in a PLL circuit. It is a figure which shows the gain in the spurious PLL circuit contained in a DDS signal when dividing ratio is set to 100. It is a figure which shows the relationship between the frequency of a DDS signal, and the signal level of the spurious contained in the said DDS signal. It is a figure which shows the relationship between the frequency of the oscillation signal when the division ratio is 100, and the signal level of the spurious included in the DDS signal when the oscillation signal is output. It is a figure which shows the relationship between the frequency of an oscillation signal when a division ratio is set to 100, and the carrier relative frequency of a spurious. It is a figure which shows the relationship between the frequency of the oscillation signal when a frequency division ratio is set to 100, and the signal level of the spurious contained in an oscillation signal. It is a figure which shows the relationship between the frequency of an oscillation signal when a frequency division ratio is set to 100, and the spurious of the largest signal level among the spurious contained in each frequency. It is a figure which shows the relationship between the frequency of an oscillation signal, and the spurious of the largest signal level among the spurious included in each frequency in case a division ratio is 96,100,104. It is a figure which shows the relationship between the frequency of an oscillation signal, and the maximum signal level of a spurious when a frequency division ratio is specified.

[Configuration of Frequency Synthesizer 1]
FIG. 1 is a circuit configuration diagram of a frequency synthesizer 1 according to the present embodiment.
The frequency synthesizer 1 includes a control circuit 2, a direct digital synthesizer (DDS) 3, and a PLL circuit 4.

The control circuit 2 includes a storage unit 21 and a setting unit 22.
The storage unit 21 is, for example, an EEPROM. The storage unit 21 is associated with each of a plurality of frequencies of the oscillation signal that can be output from the PLL circuit 4 and has a predetermined spurious attributed to the Nth harmonic (N is a natural number of 2 or more) of the DDS signal included in the oscillation signal. A combination of the frequency of the DDS signal that is equal to or lower than the level and the frequency division ratio in the PLL circuit 4 is stored. Here, the DDS signal is a signal output from the DDS 3. In the present embodiment, this combination is such that spurious due to the Nth harmonic of the DDS signal included in the oscillation signal output from the PLL circuit 4 is minimized at a frequency within a predetermined range from the frequency of the oscillation signal. Is selected. The storage unit 21 stores the frequency of the oscillation signal, the frequency of the DDS signal, and the frequency division ratio in association with each other. In the following description, spurious due to the Nth order harmonic of the DDS signal is simply referred to as Nth order spurious or spurious.

  The setting unit 22 is, for example, an integrated circuit. The setting unit 22 receives selection of the frequency of the oscillation signal by the operation unit. Specifically, the frequency synthesizer 1 is provided with an operation unit for switching the frequency of the output signal output from the frequency synthesizer 1, that is, the oscillation signal output from the PLL circuit 4, and the setting unit 22 In response to the frequency selection operation performed by the operation unit, the selection of the frequency is accepted.

  When receiving the selection of the frequency of the oscillation signal, the setting unit 22 refers to the storage unit 21 and specifies a combination of the frequency of the DDS signal associated with the selected frequency and the frequency division ratio. The setting unit 22 outputs setting data indicating the frequency of the identified DDS signal to the DDS 3 and outputs a setting signal for the division ratio to the PLL circuit 4, thereby dividing the frequency of the DDS signal and the frequency division in the PLL circuit 4. Set the ratio.

  Based on the setting data output from the control circuit 2, the DDS 3 outputs a DDS signal having a frequency indicated by the setting data from the reference clock. The DDS 3 outputs a DDS signal to the PLL circuit 4. The DDS signal includes spurious due to harmonics of the frequency of the signal.

The PLL circuit 4 includes a voltage controlled oscillator 41, a variable frequency divider 42, a phase comparator 43, and a loop filter 44.
The voltage controlled oscillator 41 includes, for example, a crystal resonator and a variable capacitance diode, and generates an oscillation signal by changing the capacitance value of the variable capacitance diode based on the control voltage output from the loop filter 44. The voltage controlled oscillator 41 generates an oscillation signal having a frequency set based on the DDS signal output from the DDS 3 and the frequency division ratio of the variable frequency divider 42. The voltage controlled oscillator 41 outputs an oscillation signal to the outside and outputs it to the variable frequency divider 42. The oscillation signal includes spurious due to spurious included in the DDS signal.

  The variable frequency divider 42 divides the frequency of the oscillation signal output from the voltage controlled oscillator 41 by the frequency dividing ratio set by the setting unit 22 and outputs the frequency divided signal to the phase comparator 43. The frequency division ratio can be changed between a predetermined frequency division ratio Mmin to Mmax.

The phase comparator 43 outputs a voltage corresponding to the phase difference between the phase of the DDS signal output from the DDS 3 and the phase of the frequency-divided signal output from the variable frequency divider 42 to the loop filter 44.
The loop filter 44 is a low-pass filter, for example, and converts the voltage output from the phase comparator 43 into a control voltage for controlling the voltage controlled oscillator 41.

  In the frequency synthesizer 1, the spurious included in the oscillation signal output from the PLL circuit 4 and the frequency of the DDS signal selected such that the spurious contained in the detuning frequency within the predetermined range is less than or equal to the predetermined level from the frequency of the oscillation signal. An oscillation signal is output based on the combination with the circumferential ratio. Further, since the frequency synthesizer 1 stores the combination in the storage unit 21, the combination corresponding to the frequency of the oscillation signal can be selected at high speed. Therefore, the frequency synthesizer 1 can speed up the frequency switching while suppressing spurious included in the output signal.

[Method for Manufacturing Frequency Synthesizer 1]
In the manufacturing process, the frequency synthesizer 1 according to the present embodiment uses the computer (not shown) to obtain the optimum frequency of the DDS signal and the frequency for each of a plurality of frequencies that can be taken by the oscillation signal output from the PLL circuit 4. A combination with the frequency ratio is specified, and the frequency of the oscillation signal, the frequency of the DDS signal, and the frequency division ratio are associated and stored in the storage unit 21. Below, the manufacturing method of the frequency synthesizer 1 is demonstrated, referring a flowchart. FIG. 2 is a flowchart showing a flow of processing related to the manufacture of the frequency synthesizer 1.

  First, the computer corresponds to the frequency that the oscillation signal output from the PLL circuit 4 can take, the frequency of the DDS signal that corresponds to the minimum value and the maximum value of the division ratio that can be taken in the PLL circuit 4, and the frequency division For each of a plurality of combinations with the ratio, the detuning frequency characteristic indicating the gain of the signal output from the PLL circuit 4 with respect to the oscillation signal is specified (S10).

  Specifically, first, the computer measures the circuit characteristics in the PLL circuit 4 using a measuring device connected to the computer, or simulates the circuit characteristics in the PLL circuit 4, and based on the circuit characteristics, the PLL circuit 4 calculates the detuned frequency characteristic Gloop (Δf) of the closed loop gain. The computer calculates a detuning frequency characteristic Gloop (Δf) in a frequency range that the oscillation signal can take. Here, Δf is a detuning frequency indicating how many Hz away from the frequency of the oscillation signal.

  Subsequently, the computer adds a gain corresponding to the frequency multiplication to the detuned frequency characteristic Gloop (Δf) of the closed loop gain, so that the spurious gain Gpll (Δf) caused by the DDS signal in the signal output from the PLL circuit 4 is obtained. , Mm).

If the gain at the frequency F _PLL of the signal output from the PLL circuit 4 is G _loop (F _PLL , Δf) and the spurious gain when the frequency division ratio is Mm is G _{PLL, Mm} (F _PLL , Δf), G _{PLL, Mm} (F _PLL , Δf) is expressed by the following equation (1).
G _{PLL, Mm} (F _PLL , Δf) = G _loop (F _PLL , Δf) +20 log (Mm) (1)

  A plurality of frequency division ratios Mm are specified based on a combination of the frequency of the DDS signal and the frequency division ratio. Note that the number of calculations may be reduced by using a representative value or the like in a case where the frequency division ratio is close or in a region where the frequency change with respect to the control voltage in the voltage controlled oscillator 41 is small.

  FIG. 3 is a calculation example of the closed loop gain in the PLL circuit 4. In the example shown in FIG. 3, detuning in the case where one representative frequency is specified for each of the cases where the frequency of the oscillation signal output from the PLL circuit 4 is 4 to 5 GHz, 5 to 6 GHz, and 6 to 7 GHz. It is a figure which shows a frequency characteristic. FIG. 4 is a diagram showing the gain in the spurious PLL circuit 4 included in the DDS signal when the frequency division ratio Mm is 100. FIG. In the example shown in FIGS. 3 and 4, it can be confirmed that the gain of the detuning frequency in the range of about 1 MHz from the frequency of the oscillation signal is a positive value.

  Note that the number of times of detuning frequency characteristics calculation in S10 is a maximum of multiplication of the number of frequencies that can be selected by the frequency synthesizer 1 (the number of frequencies that the oscillation signal can take) and the number of division ratios that can be set However, when a part of the detuning frequency characteristic shows a linear tendency, the number of calculations may be reduced, and the part that has not been calculated may be complemented based on the calculated result.

  Subsequently, the computer uses a measuring device to measure the relationship between the frequency of the DDS signal and the signal level of the spurious signal from the second-order spurious to the N-th spurious (N is a natural number of 2 or more) included in the DDS signal. (S20). Specifically, first, in the computer, based on the minimum value and maximum value of the frequency division ratio that can be taken by the PLL circuit 4 and the minimum value and maximum value of the frequency that can be taken by the oscillation signal, the minimum frequency of the DDS signal can be obtained. Specify the value and the maximum value. Then, the computer changes the frequency of the DDS signal from the specified minimum value to the maximum value using the measuring device, and measures the signal level from the secondary spurious to the Nth spurious included in the DDS signal. By doing so, the computer measures the spurious signal level within the frequency range that the DDS signal can take, and thus can efficiently measure the spurious signal level. In the present embodiment, it is assumed that the computer measures the signal level of spurious signals from secondary spurious to tenth spurious.

  FIG. 5 is a diagram illustrating the relationship between the frequency of the DDS signal and the spurious included in the DDS signal. In the example shown in FIG. 5, the signal level of the spurious from the secondary spurious to the tenth spurious is shown. As shown in FIG. 5, it can be confirmed that the spurious signal level is higher as the order is lower. Based on the relationship between the frequency of the DDS signal and the frequency of the oscillation signal output from the PLL circuit 4, the computer generates a spurious signal from the secondary spurious to the 10th spurious contained in the oscillation signal with respect to the frequency of the oscillation signal. Calculate the level. FIG. 6 is a diagram illustrating the relationship between the frequency of the oscillation signal and the signal level of spurious included in the oscillation signal when the frequency division ratio Mm is 100. In the example shown in FIG. 6, the signal levels of spurious signals from the secondary spurious to the tenth spurious are shown. The characteristics shown in FIG. 6 show the same tendency as in FIG. 5, and it can be confirmed that the spurious signal level included in the oscillation signal is higher as the spurious order is lower.

  Note that the number of measurements in S20 is the maximum, which is multiplication of the number of frequencies that can be selected by the frequency synthesizer 1 and the number of division ratios that can be set, but the characteristics are linear as shown in FIG. 5 or FIG. When a general tendency is shown, the measurement may be performed less than the number of times of measurement, and supplementation based on the measurement result may be performed for a portion where the measurement is not performed. In S20, the computer measures the relationship between the frequency of the DDS signal and the spurious signal level from the secondary spurious to the Nth spurious included in the DDS signal, but the present invention is not limited to this. The computer may calculate the relationship between the frequency of the DDS signal and the spurious signal level from the secondary spurious to the Nth spurious included in the DDS signal based on a predetermined calculation formula.

Subsequently, the computer specifies a spurious detuning frequency from the secondary spurious to the Nth spurious generated within a predetermined range from the frequency of the oscillation signal in the output signal output from the PLL circuit 4 (S30). Specifically, for each of a plurality of frequencies that can be taken by the DDS signal, the computer calculates a difference between the frequency of the DDS signal and the frequency of the Nth order spurious included in the DDS signal. When the frequency of the DDS signal is F _DDS and the difference between the frequency of the DDS signal and the frequency of the Nth order spurious is F _{delta, Np, Fsn} (F _DDS ), the difference is calculated based on the following equation (2). The Here, Np is the order of spurious, F _sn is the frequency of the reference clock input to DDS3, floor () is a function that rounds down the decimal point, and mod (x, y) is the remainder when x is divided by y Is a function for obtaining.

F _{delta, Np, Fsn} (F _DDS ) =
_{-F DDS + mod {floor (F} DDS * Np / (F sn / 2)), 2} * {(F sn / 2) -mod (F DDS * Np, F sn / 2)}
+ [1-mod {floor ( _FDDS * Np / ( _Fsn / 2)), 2}] * mod ( _Fdds * Np, _Fsn / 2) (2)

The frequency of the oscillation signal, by using that obtained by multiplying the frequency F _DDS and the division ratio Mm of the DDS signal, the computer multiplies the division ratio Mm to a difference calculated by the equation (2) Thus, the carrier relative frequency indicating the difference between the frequency of the oscillation signal output from the PLL circuit 4 and the frequency of the Nth order spurious included in the oscillation signal is specified. FIG. 7 is a diagram showing the relationship between the frequency of the oscillation signal and the spurious carrier relative frequency when the frequency division ratio Mm is 100. FIG. In FIG. 7, it is possible to specify how far each spurious frequency is from the frequency of the oscillation signal.

  Subsequently, the computer, for each of a plurality of combinations of the frequency of the DDS signal and the frequency division ratio Mm, the detuning frequency characteristic specified in S20, the signal level of spurious up to the Nth order spurious measured in S30, and S40. On the basis of the detuning frequency up to the Nth order spurious specified in step S40, the signal level of each spurious at the detuning frequency within a predetermined range from the frequency of the oscillation signal is specified (S40).

Specifically, the signal level of the Nth order spurious when the frequency of the oscillation signal is F _PLL is L _{DDS, Np} (F _PLL ), and the signal level of each spurious at a detuning frequency within a predetermined range from F _PLL is L _{Assuming that PLL, fsn, Mm, Np} (F _PLL ), L _{PLL, fsn, Mm, Np} (F _PLL ) is expressed by the following equation (3) based on equations (1) and (2).
L _{PLL, fsn, Mm, Np} (F _PLL ) = L _{DDS, Np} (F _PLL )
+ G _{PLL, Mm} (F _{delta, Np, Fsn} (F _PLL / Mm), Mm) (3)

  FIG. 8 is a diagram illustrating the relationship between the frequency of the oscillation signal and the signal level of the spurious included in the oscillation signal when the frequency division ratio is 100. FIG. 8 shows signal levels of spurious signals from secondary spurious to tenth spurious. As shown in FIG. 8, it can be confirmed that the spurious order corresponding to the maximum signal level changes at each frequency that the oscillation signal can take.

Subsequently, as shown in FIG. 9, the computer has the maximum signal level among the signal levels of all the spurious signals from the secondary spurious to the Nth spurious at a detuning frequency within a predetermined range from the frequency F _{PLL of the} oscillation signal. The signal level spurious L _{PLLSpuri, fsn, Mm} (F _PLL ) is specified. The computer specifies the spurious signal having the maximum signal level based on the following equation (4). Here, max {x1, x2,..., Xn} (n is a natural number of 3 or more) is a function for selecting the maximum value from x1 to xn.
L _{PLLspuri, fsn, Mm} (F _PLL ) = max {L _{PLL, fsn, Mm, N1} ,..., L _{PLL, fsn, Mm, Np} } (4)

  In FIG. 9, the example in which the frequency division ratio is set to 100 has been described. However, the computer uses the oscillation signal shown in FIG. 9 for a plurality of frequency division ratios corresponding to combinations of the DDS signal and the frequency division ratio. The relationship between the frequency and the spurious at the maximum signal level shall be specified.

  Subsequently, the computer specifies each of the plurality of frequencies of the oscillation signal based on the spurious signal level at the detuning frequency within a predetermined range from the plurality of frequencies that can be taken by the oscillation signal, specified for each of the plurality of combinations. One combination is selected from a plurality of combinations corresponding to (S50).

  Specifically, the computer determines the maximum signal level corresponding to each of the plurality of frequencies that can be taken by the oscillation signal specified in S40 for a plurality of division ratios corresponding to the combination of the DDS signal and the division ratio. And a frequency division ratio that can most suppress the maximum signal level at each of the plurality of frequencies.

FIG. 10 is a diagram showing the relationship between the frequency of the oscillation signal and the maximum signal level spurious out of the spurious included in each frequency signal when the frequency division ratio is 96, 100, or 104. For example, in FIG. 10, when the frequency of the oscillation signal is _{FP PLL 1} , the computer specifies 104 as the division ratio with the smallest spurious maximum signal level.

  FIG. 11 is a diagram showing the relationship between the frequency of the oscillation signal and the maximum signal level of spurious when the frequency division ratio is specified. As shown in FIG. 11, it can be confirmed that the maximum signal level is suppressed below −70 dBc at each of a plurality of frequencies that can be taken by the oscillation signal.

  Subsequently, the computer stores the frequency and frequency division ratio of the DDS signal corresponding to the selected combination in the storage unit 21 of the frequency synthesizer 1 in association with the frequency of the oscillation signal (S60).

[Effect of this embodiment]
As described above, the selection method according to the present embodiment performs the detuning frequency characteristics, the signal level up to the Nth order spurious, and the Nth order spurious for each of a plurality of combinations of the frequency and the division ratio of the DDS signal. The spurious signal level at the detuning frequency within the predetermined range from the frequency of the oscillation signal is determined based on the detuning frequency up to and within the predetermined range from the frequency of the oscillation signal specified for each of the plurality of combinations. Based on the spurious signal level at the detuning frequency, one combination is selected from a plurality of combinations corresponding to the frequency of the oscillation signal.

  In this way, a frequency synthesizer in which the frequency of the oscillation signal and the combination selected for the frequency are stored in the storage unit 21 of the frequency synthesizer 1 can be manufactured. As a result, when the frequency synthesizer 1 accepts the selection of the frequency of the oscillation signal, as shown in FIG. 11, the frequency synthesizer 1 operates with a combination of the DDS signal and the division ratio that minimizes the spurious included in the oscillation signal. The frequency switching of the output signal output from the frequency synthesizer 1 can be speeded up while suppressing spurious included in the output signal.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Frequency synthesizer, 2 ... Control circuit, 21 ... Memory | storage part, 22 ... Setting part, 3 ... Direct digital synthesizer, 4 ... PLL circuit, 41 ... Voltage controlled oscillator 42 ... Variable frequency divider, 43 ... Position comparator, 44 ... Loop filter

Claims (6)

A frequency synthesizer comprising: a direct digital synthesizer; and a PLL circuit that outputs an oscillation signal having a frequency set based on a frequency division ratio of the DDS signal output from the direct digital synthesizer. A first step of specifying a detuning frequency characteristic indicating a gain of the signal output from the PLL circuit with respect to the oscillation signal for each of the plurality of combinations with the division ratio;
First, the relationship between the frequency of the DDS signal and the signal level up to the Nth order spurious (N is a natural number of 2 or more) caused by the Nth harmonic (N is a natural number of 2 or more) included in the DDS signal is specified. Two steps,
A third step of specifying a detuning frequency from the frequency of the oscillation signal output from the PLL circuit to the Nth order spurious generated within a predetermined range;
Based on the detuning frequency characteristic, the signal level up to the Nth order spurious, and the detuning frequency up to the Nth order spurious for each of the plurality of combinations, the frequency of the oscillation signal is within the predetermined range. A fourth step of identifying the spurious signal level at the detuning frequency;
Based on the spurious signal level at the detuning frequency within the predetermined range from the frequency of the oscillation signal, specified for each of the plurality of combinations, one combination from the plurality of combinations corresponding to the frequency of the oscillation signal A fifth step to select,
A selection method comprising: In the fourth step, the maximum signal level is specified among the respective signal levels of the harmonic spurious up to the Nth order spurious at the detuning frequency within the predetermined range from the frequency of the oscillation signal.
The selection method according to claim 1. In the second step, based on the minimum value and maximum value of the frequency division ratio that can be taken in the PLL circuit and the minimum value and maximum value of the frequency that can be taken by the oscillation signal, the minimum value of the frequency of the DDS signal and Specify the maximum value, change the frequency of the DDS signal from the minimum value to the maximum value, and specify the signal level up to the Nth order spurious included in the DDS signal.
The selection method according to claim 1 or 2. In the first step, the detuning frequency characteristic is specified for each of the plurality of combinations in each of a plurality of frequencies that the oscillation signal can take.
In the third step, for each of a plurality of frequencies that can be taken by the oscillation signal, a detuning frequency from the frequency to the Nth order spurious generated within the predetermined range is specified,
In the fourth step, for each of a plurality of frequencies that can be taken by the oscillation signal, a signal level corresponding to harmonic spurious up to Nth order spurious at a detuned frequency within the predetermined range is specified,
In the fifth step, one combination is selected from the plurality of combinations for each of a plurality of frequencies that the oscillation signal can take.
The selection method according to any one of claims 1 to 3. A frequency synthesizer manufacturing method comprising: a direct digital synthesizer; and a PLL circuit that outputs an oscillation signal having a frequency set based on a frequency division ratio of the DDS signal output from the direct digital synthesizer.
In the frequency synthesizer, for each of a plurality of combinations of the frequency of the DDS signal and the division ratio, a detuning frequency characteristic indicating a gain of the signal output from the PLL circuit with respect to the oscillation signal is specified. One step,
First, the relationship between the frequency of the DDS signal and the signal level up to the Nth order spurious (N is a natural number of 2 or more) caused by the Nth harmonic (N is a natural number of 2 or more) included in the DDS signal is specified. Two steps,
A third step of specifying a detuning frequency from the frequency of the oscillation signal output from the PLL circuit to the Nth order spurious generated within a predetermined range;
Based on the detuning frequency characteristic, the signal level up to the Nth order spurious, and the detuning frequency up to the Nth order spurious for each of the plurality of combinations, the frequency of the oscillation signal is within the predetermined range. A fourth step of identifying the spurious signal level at the detuning frequency;
Based on the spurious signal level at the detuning frequency within the predetermined range from the frequency of the oscillation signal, specified for each of the plurality of combinations, one combination from the plurality of combinations corresponding to the frequency of the oscillation signal A fifth step to select,
A sixth step of storing the frequency of the DDS signal corresponding to the selected combination and the frequency division ratio in the storage unit of the frequency synthesizer in association with the frequency of the oscillation signal;
A manufacturing method comprising: A direct digital synthesizer,
A PLL circuit that outputs an oscillation signal having a frequency set based on a frequency division ratio of the DDS signal output from the direct digital synthesizer;
A storage unit for storing a combination of the frequency of the DDS signal and the division ratio at which the spurious of the oscillation signal is equal to or lower than a predetermined level in association with each of the plurality of frequencies of the oscillation signal that can be output by the PLL circuit; ,
Upon receiving selection of the frequency of the oscillation signal, a setting unit that sets the frequency of the DDS signal corresponding to the combination associated with the selected frequency and the division ratio;
A frequency synthesizer comprising:

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