JP2022105230A - Imaging device, and manufacturing method of imaging device - Google Patents

Abstract

To provide an imaging device capable of imaging with high image quality by suppressing the influence of dark current.SOLUTION: A disclosed imaging device 100 includes multiple pixels 10. Each of the multiple pixels 10 includes: a photoelectric converter 12 that converts incident light into signal charge; a charge storage region (n-type impurity region 67n) that stores signal charge; a first transistor (reset transistor 26) that is electrically connected to the charge storage region and includes a first gate electrode, a first source, a first drain, and a first side wall positioned at the wall side of the first gate electrode; a first plug (contact plug Cp7) connected to the first gate electrode; a first silicide layer (silicide layer 75) that is in contact with the first plug; and a first insulation layer 71 that is in contact with the first side wall and the first silicide layer.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to an image pickup apparatus and a method for manufacturing the image pickup apparatus.

As a MOS (Metal Oxide Semiconductor) type image pickup device, a laminated type image pickup device has been proposed. In a laminated image pickup device, a photoelectric conversion layer is laminated on the outermost surface of a semiconductor substrate, and charges generated by photoelectric conversion in the photoelectric conversion layer are accumulated in a charge storage region (referred to as "floating diffusion (FD)"). The image pickup apparatus reads out the accumulated charge using a CCD (Chage Coupled Device) circuit or a CMOS (Complementary MOS) circuit in the semiconductor substrate. For example, Patent Document 1 discloses such an imaging device.

Further, as a non-stacked image pickup device, a technique for optimizing components of a pixel region and a peripheral circuit region in an image pickup device having an embedded photodiode has been proposed (see, for example, Patent Document 2). ..

International Publication No. 2013/190759 Japanese Unexamined Patent Publication No. 2015-233128

In the above-mentioned conventional image pickup apparatus, it is desired to develop a technique for further reducing the leakage current (hereinafter, may be referred to as "dark current").

An exemplary embodiment of the present disclosure provides an image pickup apparatus and a method for manufacturing an image pickup apparatus capable of suppressing the influence of a dark current and performing an image pickup with high image quality.

According to some non-limiting exemplary embodiments of the present disclosure, the following are provided.

The image pickup device according to one embodiment of the present disclosure is an image pickup device including a plurality of pixels, and each of the plurality of pixels has a photoelectric conversion unit and a charge storage region for accumulating charges generated by the photoelectric conversion unit. A first transistor electrically connected to the charge storage region and including a first gate electrode, a first source, a first drain and a first sidewall located on the side wall of the first gate electrode, and the first gate. It includes a first plug connected to an electrode, a first silicide layer in contact with the first plug, and a first insulating layer in contact with the first sidewall and the first silicide layer.

Also, inclusive or specific embodiments may be implemented in elements, devices, modules, systems or methods. In addition, the comprehensive or specific embodiment may be realized by any combination of elements, devices, devices, modules, systems and methods.

Also, the additional effects and advantages of the disclosed embodiments will be apparent from the specification and drawings. The effects and / or advantages are provided individually by the various embodiments or features disclosed in the specification and drawings, and not all are required to obtain one or more of these.

According to one aspect of the present disclosure, an image pickup device and a method for manufacturing an image pickup device capable of suppressing the influence of dark current and performing image pickup with high image quality are realized.

FIG. 1 is a block diagram showing an exemplary configuration of the image pickup apparatus according to the first embodiment of the present disclosure. FIG. 2 is a schematic diagram showing an exemplary circuit configuration of the image pickup apparatus according to the first embodiment of the present disclosure. FIG. 3 is a cross-sectional view schematically showing an example of the device structure of the pixels of the image pickup apparatus according to the first embodiment of the present disclosure. FIG. 4 is a schematic plan view showing an example of the layout of each element in the pixels of the image pickup apparatus according to the first embodiment of the present disclosure. FIG. 5 is an enlarged layout view and cross-sectional view of the vicinity of the reset transistor in the image pickup region of the image pickup apparatus according to the first embodiment of the present disclosure, and shows a view immediately after forming the silicide layer on the contact plug. FIG. 6 is an enlarged layout view and cross-sectional view of the vicinity of the reset transistor in the image pickup region of the image pickup apparatus according to the first embodiment of the present disclosure, and shows a view after removing the silicide block layer. FIG. 7 is an enlarged layout view and cross-sectional view of the vicinity of the reset transistor in the image pickup region of the image pickup apparatus according to the first embodiment of the present disclosure, and shows a view immediately after forming the second contact plug. FIG. 8 is a cross-sectional view showing a device structure in which the silicide block layer is left in the image pickup region of the image pickup apparatus according to the comparative example, and a device structure in which the silicide block layer in the image pickup region of the image pickup apparatus according to the first embodiment of the present disclosure is removed. The cross-sectional view of is shown. FIG. 9 shows a cross-sectional view of the image pickup apparatus according to the first embodiment of the present disclosure after the formation of the first insulating layer in the peripheral region. FIG. 10 shows a cross-sectional view of the second insulating layer after film formation in the peripheral region of the image pickup apparatus according to the first embodiment of the present disclosure. FIG. 11 shows a cross-sectional view of the fourth insulating layer after film formation in the peripheral region of the image pickup apparatus according to the first embodiment of the present disclosure. FIG. 12 shows a cross-sectional view of the silicide block layer in the peripheral region of the image pickup apparatus according to the first embodiment of the present disclosure after film formation. FIG. 13 shows a cross-sectional view of the image pickup apparatus according to the first embodiment of the present disclosure after the formation of the silicide layer in the peripheral region. FIG. 14 shows a cross-sectional view of the peripheral region of the image pickup apparatus according to the first embodiment of the present disclosure after removal of the silicide block layer. FIG. 15 shows a cross-sectional view of the first insulating layer after film formation in the peripheral region of the image pickup apparatus according to the first embodiment of the present disclosure. FIG. 16 is a cross-sectional view after the formation of the first insulating layer in the peripheral region of the image pickup apparatus according to the first embodiment of the present disclosure, and the first insulating layer when the silicide block layer of the image pickup apparatus according to the comparative example is left. The cross-sectional view after the formation of is shown. FIG. 17 is a cross-sectional view schematically showing an example of the device structure of the pixels of the image pickup apparatus according to the modified example of the first embodiment of the present disclosure. FIG. 18 is a schematic diagram showing an exemplary circuit configuration of the image pickup apparatus according to the second embodiment of the present disclosure. FIG. 19 is a schematic plan view showing an example of the layout of each element in the pixels of the image pickup apparatus according to the second embodiment of the present disclosure. FIG. 20 is a cross-sectional view schematically showing an example of the device structure of the pixels of the image pickup apparatus according to the second embodiment of the present disclosure. FIG. 21 is a cross-sectional view schematically showing an example of the device structure of the pixels of the image pickup apparatus according to the modified example of the second embodiment of the present disclosure.

(Knowledge that became the basis of the present invention)
Generally, the image pickup apparatus requires a contact, that is, a so-called charge storage region, for transmitting the signal charge photoelectrically converted by the photoelectric conversion layer to the drive circuit unit provided on the semiconductor substrate. Various pn junctions are formed in the charge storage region of the semiconductor substrate. In particular, when an impurity level due to metal is formed at these pn junctions, a leak current is generated. Moreover, since the charge due to the leak current is indistinguishable from the photoelectrically converted signal charge, it can become noise. As a result, the performance of the image pickup device deteriorates.

In the solid film experiment, the inventor of the present application formed a silicide block layer, which is a protective layer made of a silicon oxide layer that suppresses the formation of the silicide layer, and then formed the silicide layer. It was found that a metal such as Ni, Pt or Ti having a relatively high concentration of about 0 × 10 ¹² to 1.0 × 10 ¹³ [atoms / cm ^-2 ] was contained. The metal remaining in the silicide block layer diffuses into the charge storage region by the heat treatment in the subsequent process, which leads to deterioration of the dark current in the pixel portion. More specifically, in the heat treatment performed in the step after silicide formation, the metal diffuses from the single crystal silicon or polysilicon in contact with the silicide block layer contaminated with the metal at the time of silicidation formation, and diffuses into the charge storage region. As a result, metal impurity levels are generated in a semiconductor substrate such as silicon, and the dark current characteristics are deteriorated. However, it cannot be said that the above-mentioned Patent Documents 1 and 2 have taken measures to suppress such deterioration of dark current characteristics. Therefore, the inventor of the present application reduces the amount of metal diffused into the charge storage region by selectively removing the silicide block layer contaminated with silicide, and as a result, deterioration of dark current characteristics is suppressed. I came up with the idea of an image pickup device.

Based on such findings, the inventor of the present application has come up with an image pickup apparatus having a novel structure. The outline of one aspect of the present disclosure is as follows.

The image pickup device according to one aspect of the present disclosure is an image pickup device including a plurality of pixels, and each of the plurality of pixels has a photoelectric conversion unit and a charge storage region for accumulating charges generated by the photoelectric conversion unit. A first transistor electrically connected to the charge storage region and including a first gate electrode, a first source, a first drain and a first sidewall located on the side wall of the first gate electrode, and the first gate. It includes a first plug connected to an electrode, a first silicide layer in contact with the first plug, and a first insulating layer in contact with the first sidewall and the first silicide layer.

With the above configuration, the metal-contaminated silicide block layer is selectively removed, so that the amount of metal diffused into the charge storage region can be reduced. As a result, the dark current is reduced and the pixel characteristics are improved. Further, since the first silicide layer is formed on the surface of the first plug connected to the first gate electrode of the first transistor, the contact resistance in the connection between the first plug and the conductive structure is reduced, and the first High-speed operation of the transistor becomes possible.

Here, a second transistor including a second gate electrode, a second source, and a second drain is provided, and the second gate electrode includes a first semiconductor layer and a second silicide layer located on the first semiconductor layer. The first insulating layer may be in contact with the second silicide layer.

With the above configuration, in the silicated second transistor, the contact resistance between the second gate electrode and the contact plug can be reduced, so that the delay during driving of the second transistor is reduced, and the second transistor is reduced. It is possible to improve the operating speed of.

Further, a peripheral circuit for outputting a drive signal for driving the plurality of pixels may be provided, and the peripheral circuit may include the second transistor.

With the above configuration, the vertical scanning circuit, the horizontal scanning circuit, the column signal processing circuit, and the control circuit, which are mounted as peripheral circuits of the pixel portion, include the second transistor sylated, and as a result, the peripheral circuit It enables high-speed operation and contributes to the improvement of the frame rate of the image sensor.

Further, the peripheral circuit includes a third transistor including a third gate electrode, a third source and a third drain, the third gate electrode includes a second semiconductor layer, and the first insulating layer is the first. 2 It may be in contact with the semiconductor layer.

With the above configuration, in order to improve the resistance to electrostatic discharge due to ESD (Electro-Static Discharge) constituting the peripheral circuit, a region in which silicide is not formed is provided in a part of the source region and the drain region. By providing a resistance element connected in series with such a non- silicide third transistor, the withstand voltage can be improved. Further, since the silicide block layer contaminated with metal is also removed, the dark current is reduced and the pixel characteristics are improved.

Further, the peripheral circuit may include a resistance element, the resistance element may include a third semiconductor layer, and the first insulating layer may be in contact with the third semiconductor layer.

With the above configuration, the peripheral circuit includes a non- silicide resistance element. Therefore, for example, as in the ADC (Analog-to-Digital Converter) of the peripheral circuit, the larger the number of bits and the higher the accuracy, the smaller the variation in resistance value is suppressed. The required circuit is realized. In particular, in the case of a high-precision ADC having a resolution exceeding 10 bits, it is generally necessary to suppress the variation in the resistance value of each resistance element to be smaller than 1%. Therefore, in order to prevent the resistance from fluctuating depending on the temperature due to the extremely insensitivity to the temperature characteristics (low temperature coefficient), a non- silicide resistance element is provided as an element required in the column signal processing circuit of the peripheral circuit. In addition, it is a circuit that requires high resistance, such as DAC (Digital-to-Analog-Converter), and can be mounted on peripheral circuits in a small area, and the variation in resistance ratio between non- silicide resistant elements is small, that is, absolute. A resistance element is also provided in which the ratio does not vary even if the value varies. Further, since the silicide block layer contaminated with metal is also removed, the dark current is reduced and the pixel characteristics are improved.

Further, the first semiconductor layer and the third semiconductor layer may be made of the same material.

With the above configuration, the non- silicide transistor for ESD countermeasures and the non- silicide resistance element necessary for suppressing the variation in resistance value can be efficiently mounted in the peripheral circuit at the same time by using the same material without using different materials. Will be possible, and cost reduction will be possible.

Further, the first transistor may reset the signal charge accumulated in the charge storage region.

With the above configuration, the surface of the plug connected to the gate electrode of the reset transistor electrically connected to the charge storage region is covered with silicide, so that the contact resistance between the plug and the conductive structure connected to the plug is reduced. To.

A method of manufacturing an image pickup apparatus according to one aspect of the present disclosure includes a first transistor including a first gate electrode, a first source and a first drain, and a first sidewall located on a side wall of the first gate electrode. The first step of forming a protective layer located above the first gate electrode and the first sidewall on the provided semiconductor substrate, and the first plug penetrating the protective layer and connecting to the first gate electrode. The second step of forming the protective layer, the third step of forming the first silicide layer on the first plug and the protective layer, the fourth step of removing the protective layer, the first sidewall and the first step. The fifth step of forming the first insulating layer covering the silicide layer is included in this order.

With the above configuration, the protective layer, which is a silicide block layer contaminated with metal, is removed, so that the dark current is reduced and the pixel characteristics are improved. Further, since the first silicide layer is formed on the first plug connected to the first gate electrode of the first transistor, the contact resistance in the connection between the first plug and the conductive structure is reduced, and the first transistor is used. High-speed operation is possible.

Here, the fourth step may be performed by wet etching.

With the above configuration, since the protective layer is removed by wet etching, etching damage to the surface layer of the semiconductor substrate due to ion impact due to plasma generation can be suppressed as compared with removal by dry etching. In addition, it is possible to prevent charge-up to the gate protective layer due to charged particles.

Further, the wet etching may be APM (Ammonia-hydrogen Peroxide Mixture) etching.

With the above configuration, it is possible to selectively remove only the protective layer without removing the first silicide layer.

Further, the first insulating layer may be a silicon nitride layer.

With the above configuration, since the first insulating layer is formed of a stable silicon nitride layer, the first insulating layer can serve as an etching stopper for dry etching when the contact plug is formed after the first insulating layer.

Further, the first insulating layer may be formed by using an ALD (Atomic Layer Deposition) method.

With the above configuration, the film formation by the ALD method has sufficiently high coverage, so that the first insulating layer can be formed even with a slight gap after the protective layer is removed.

Further, the protective layer may be a silicon oxide layer.

With the above configuration, since the protective layer is composed of a silicon oxide layer, the protective layer can be easily removed by wet etching.

Further, the protective layer may be formed by a CVD (Chemical Vapor Deposition) method using ozone and TEOS (TetraEthOxySilane) as a source gas.

With the above configuration, it is possible to suppress the diffusion of impurities by forming a film by low temperature treatment. Further, since the film formation by CVD has good coverage, it is possible to form a film without generating voids (gap) even if the space between the gate electrodes of the transistor becomes narrow.

Further, a sixth step of heating the semiconductor substrate in a diffusion furnace may be included between the second step and the third step.

With the above configuration, it becomes possible to impart conductivity to the first plug. Further, by performing heating before forming the silicide, it becomes possible to suppress the aggregation of the silicide and prevent the resistance value from increasing.

Further, in the sixth step, the semiconductor substrate may be heated at a temperature of 800 ° C. or higher.

With the above configuration, crystal defects due to damage during ion implantation or dry etching into the charge storage region can be recovered. Further, as the film quality of the protective layer becomes dense, the metal is captured by the protective layer when the silicide layer is formed.

Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings.

The present disclosure is not limited to the following embodiments. Further, it can be appropriately changed as long as it does not deviate from the range in which the effect of the present invention is exhibited. Furthermore, it is also possible to combine one embodiment with another. In the following description, the same or similar components are designated by the same reference numerals. In addition, duplicate explanations may be omitted. Further, in the present specification, "planar view" means a view from a direction perpendicular to the semiconductor substrate.

(Embodiment 1)
The structure and function of the image pickup apparatus according to the first embodiment will be described with reference to FIGS. 1 to 4.

FIG. 1 is a block diagram showing an exemplary configuration of the image pickup apparatus 100 according to the first embodiment of the present disclosure. The image pickup apparatus 100 shown in FIG. 1 has a plurality of pixels 10 and peripheral circuits 40 formed on the semiconductor substrate 60. The pixel 10 has a photoelectric conversion unit 12 that converts incident light into a signal charge.

In the example shown in FIG. 1, the pixels 10 are arranged in a plurality of rows and columns of m rows and n columns. Here, m and n independently represent integers of 1 or more. The pixels 10 are arranged on the semiconductor substrate 60, for example, in two dimensions to form an imaging region R1.

The number and arrangement of the pixels 10 is not limited to the illustrated example. For example, the number of pixels 10 included in the image pickup apparatus 100 may be one. In this example, the center of each pixel 10 is located on a grid point of a square grid, but for example, a plurality of pixels 10 are located so that the center of each pixel 10 is located on a grid point of a triangular grid or a hexagonal grid, for example. Pixels 10 may be arranged. For example, the pixels 10 may be arranged one-dimensionally, and in this case, the image pickup apparatus 100 may be used as a line sensor.

In the configuration exemplified in FIG. 1, the peripheral circuit 40 includes a vertical scanning circuit 42 and a horizontal signal readout circuit 44. As illustrated in FIG. 1, the peripheral circuit 40 may additionally include a control circuit 46. Further, as will be described later, the peripheral circuit 40 may further include a voltage supply circuit that supplies a predetermined voltage to, for example, a pixel 10. The peripheral circuit 40 may further include, for example, a signal processing circuit or an output circuit.

The peripheral circuit 40 is provided in, for example, the peripheral region R2 located around the imaging region R1. In the example shown in FIG. 1, the peripheral region R2 is an annular region surrounding the periphery of the imaging region R1, but is not limited to this. The peripheral region R2 may be an L-shaped region along two sides of the imaging region R1 or a long region along one side of the imaging region R1.

The vertical scanning circuit 42, also referred to as a row scanning circuit, has a connection with an address signal line 34 provided corresponding to each row of the plurality of pixels 10. As will be described later, the signal line provided corresponding to each line of the plurality of pixels 10 is not limited to the address signal line 34, and the vertical scanning circuit 42 has a plurality of types of signals for each line of the plurality of pixels 10. Wires can be connected. The horizontal signal readout circuit 44, also referred to as a row scanning circuit, has a connection with a vertical signal line 35 provided corresponding to each row of the plurality of pixels 10.

The control circuit 46 receives, for example, command data and a clock given from the outside of the image pickup apparatus 100, and controls the entire image pickup apparatus 100. Typically, the control circuit 46 has a timing generator and supplies a drive signal to the vertical scanning circuit 42 and the horizontal signal readout circuit 44. In FIG. 1, the arrow extending from the control circuit 46 schematically represents the flow of the output signal from the control circuit 46. The control circuit 46 may be implemented, for example, by a microcontroller including one or more processors. The function of the control circuit 46 may be realized by a combination of a general-purpose processing circuit and software, or may be realized by hardware specialized for such processing.

FIG. 2 schematically shows an exemplary circuit configuration of the image pickup apparatus 100 according to the first embodiment of the present disclosure. In FIG. 2, four pixels 10A arranged in two rows and two columns are represented as representatives in order to avoid complication of the drawing. Each of these pixels 10A is an example of the pixel 10 shown in FIG. 1, has a photoelectric conversion structure 12A as a photoelectric conversion unit 12, and includes a signal detection circuit 14A electrically connected to the photoelectric conversion structure 12A. As will be described in detail later with reference to the drawings, the photoelectric conversion structure 12A includes a photoelectric conversion layer arranged above the semiconductor substrate 60. That is, here, a stacked image pickup device is exemplified as the image pickup device 100. In addition, in this specification, terms such as "upper", "lower", "upper surface" and "lower surface" are used only for designating mutual arrangement between members, and when the image pickup apparatus 100 is used. It is not intended to limit the posture.

The photoelectric conversion structure 12A of each pixel 10A has a connection with the storage control line 31. During the operation of the image pickup apparatus 100, a predetermined voltage is applied to the storage control line 31. For example, in the case of using the positive charge as the signal charge among the positive and negative charges generated by the photoelectric conversion, a positive voltage of, for example, about 10 V is applied to the storage control line 31 during the operation of the image pickup apparatus 100. obtain. In the following, a case where holes are used as signal charges will be illustrated.

In the configuration exemplified in FIG. 2, the signal detection circuit 14A includes a signal detection transistor 22, an address transistor 24, and a reset transistor 26. As will be described in detail later with reference to the drawings, the signal detection transistor 22, the address transistor 24 and the reset transistor 26 are typically field effect transistors formed on the semiconductor substrate 60 supporting the photoelectric conversion structure 12A. .. Hereinafter, unless otherwise specified, an example of using an N-channel MOS as a transistor will be described.

As schematically shown in FIG. 2, the gate of the signal detection transistor 22 is electrically connected to the photoelectric conversion structure 12A. By applying a predetermined voltage to the storage control line 31 during operation, for example, holes can be stored as signal charges in the charge storage node (charge storage region) FD. Here, the charge storage node FD is a node that connects the gate of the signal detection transistor 22 to the photoelectric conversion unit 12, and as will be described later with reference to the drawings, the impurity region formed on the semiconductor substrate 60 is one of them. Included in the part. In the illustrated example, the charge storage node FD has a function of temporarily holding the charge generated by the photoelectric conversion structure 12A.

One of the drain and the source of the signal detection transistor 22 is connected to the power supply wiring 32. The power supply voltage VDD is supplied to each pixel 10A during the operation of the image pickup apparatus 100. The power supply voltage VDD is, for example, 3.3 V. The other of the drain and source of the signal detection transistor 22 is connected to the vertical signal line 35 via the address transistor 24. The signal detection transistor 22 receives the supply of the power supply voltage VDD to the other of the drain and the source, and outputs a signal voltage according to the amount of the signal charge stored in the charge storage node FD.

The address signal line 34 is connected to the gate of the address transistor 24 connected between the signal detection transistor 22 and the vertical signal line 35. Therefore, the vertical scanning circuit 42 applies a row selection signal for controlling on and off of the address transistor 24 to the address signal line 34, so that the output of the signal detection transistor 22 of the selected pixel 10A is output from the corresponding vertical signal line. It can be read to 35. The arrangement of the address transistor 24 is not limited to the example shown in FIG. 2, and may be between the drain of the signal detection transistor 22 and the power supply wiring 32.

A load circuit 45 and a column signal processing circuit 47 are connected to each of the vertical signal lines 35. The load circuit 45 forms a source follower circuit together with the signal detection transistor 22. The column signal processing circuit 47 is also called a row signal storage circuit, and performs noise suppression signal processing and analog-to-digital conversion represented by, for example, correlated double sampling. The horizontal signal reading circuit 44 sequentially reads signals from the plurality of column signal processing circuits 47 to the horizontal common signal line 49. The load circuit 45 and the column signal processing circuit 47 may be part of the peripheral circuit described above.

A reset signal line 36 having a connection with the vertical scanning circuit 42 is connected to the gate of the reset transistor 26. Similar to the address signal line 34, the reset signal line 36 is provided for each line of the plurality of pixels 10A. The vertical scanning circuit 42 can select the pixel 10A to be reset in units of rows by applying a row selection signal to the address signal line 34. Further, the vertical scanning circuit 42 can switch the reset transistor 26 in the selected row on and off by applying a reset signal to the gate of the reset transistor 26 via the reset signal line 36. When the reset transistor 26 is turned on, the potential of the charge storage node FD is reset.

In this example, one of the drain and source of the reset transistor 26 is connected to the charge storage node FD, and the other of the drain and source is the corresponding one of the feedback lines 53 provided for each row of the plurality of pixels 10A. It is connected to one. That is, in this example, the voltage of the feedback line 53 is supplied to the charge storage node FD as the reset voltage for initializing the charge of the photoelectric conversion unit 12.

In the configuration exemplified in FIG. 2, the image pickup apparatus 100 has a feedback circuit 16A including an inverting amplifier 50 as a part of the feedback path. As shown in FIG. 2, the inverting amplifier 50 is provided for each row of the plurality of pixels 10A, and the feedback line 53 described above is connected to a corresponding output terminal of the plurality of inverting amplifiers 50. There is. The inverting amplifier 50 may be part of the peripheral circuit 40 described above.

As shown in FIG. 2, the inverting input terminal of the inverting amplifier 50 is connected to the vertical signal line 35 of the corresponding column, and the non-inverting input terminal of the inverting amplifier 50 has a reference voltage Vref during operation of the image pickup apparatus 100. Will be supplied. By turning on the address transistor 24 and the reset transistor 26, it is possible to form a feedback path for negative feedback of the output of the pixel 10. By forming the feedback path, the voltage of the vertical signal line 35 converges to the reference voltage Vref, which is the input voltage to the non-inverting input terminal of the inverting amplifier 50. In other words, the formation of the feedback path resets the voltage of the charge storage node FD to a voltage such that the voltage of the vertical signal line 35 becomes the reference voltage Vref. As the reference voltage Vref, a voltage of any magnitude within the range of the power supply voltage and the ground can be used. The reference voltage Vref is, for example, 1V or a positive voltage in the vicinity of 1V. By forming the feedback path, it is possible to reduce the reset noise generated by turning off the reset transistor 26.

Subsequently, the details of the device structure of the pixel 10A will be described with reference to FIGS. 3 and 4.

FIG. 3 is a cross-sectional view schematically showing an example of the device structure of the pixel 10A of the image pickup apparatus 100 according to the first embodiment of the present disclosure. FIG. 4 is a schematic plan view showing an example of the layout of each element in the pixel 10A of the image pickup apparatus 100 according to the present embodiment. FIG. 4 schematically shows the arrangement of each element formed on the semiconductor substrate 60 when the pixel 10A shown in FIG. 3 is viewed along the normal direction of the semiconductor substrate 60. By cutting and unfolding the pixel 10A along the line III-III in FIG. 4, the cross section shown in FIG. 3 can be obtained.

In FIG. 4, the description of the first insulating layer 71, the second insulating layer 72, the third insulating layer 73, the fourth insulating layer 74, and the silicide layer 75 is omitted in order to simplify the schematic diagram.

See FIG. The pixel 10A includes a semiconductor substrate 60, a photoelectric conversion structure 12A arranged above the semiconductor substrate 60, and a conductive structure 89. As shown in the figure, the photoelectric conversion structure 12A is supported by an interlayer insulating layer 90 that covers the semiconductor substrate 60. The conductive structure 89 is arranged inside the interlayer insulating layer 90. In the illustrated example, the interlayer insulating layer 90 includes a plurality of insulating layers. The conductive structure 89 includes a part of each of the plurality of wiring layers arranged inside the interlayer insulating layer 90. The plurality of wiring layers arranged in the interlayer insulating layer 90 is, for example, a wiring having at least one of an address signal line 34, a reset signal line 36, a vertical signal line 35, a power supply wiring 32, and a feedback line 53 as a part thereof. May include layers. Needless to say, the number of insulating layers and the number of wiring layers in the interlayer insulating layer 90 are not limited to this example and can be set arbitrarily.

The photoelectric conversion structure 12A includes a pixel electrode 12a formed on the interlayer insulating layer 90, a counter electrode 12c arranged on the side where light is incident, and a photoelectric conversion layer 12b arranged between these electrodes. The photoelectric conversion layer 12b of the photoelectric conversion structure 12A is formed of an organic material or an inorganic material. The inorganic material is, for example, amorphous silicon. The photoelectric conversion layer 12b receives the light incident through the counter electrode 12c and generates positive and negative charges by photoelectric conversion. The photoelectric conversion layer 12b is typically formed continuously over a plurality of pixels 10A. The photoelectric conversion layer 12b may include a layer made of an organic material and a layer made of an inorganic material. The photoelectric conversion layer 12b may be provided separately for each pixel 10A.

The counter electrode 12c is a translucent electrode formed of a transparent conductive material. The transparent conductive material is, for example, ITO (Indium Tin Oxide). The term "translucent" as used herein means that the photoelectric conversion layer 12b transmits at least a part of light having a wavelength that can be absorbed, and it is essential that the light is transmitted over the entire wavelength range of visible light. is not. Typically, the counter electrode 12c is formed over the plurality of pixels 10A, similarly to the photoelectric conversion layer 12b. That is, the counter electrode 12c is shared by the plurality of pixels 10A. In other words, the photoelectric conversion unit 12 provided for each pixel 10A includes a portion of the counter electrode 12c that is different for each pixel 10A. The counter electrode 12c may be provided separately for each pixel 10A.

Although not shown in FIG. 3, the counter electrode 12c has a connection with the above-mentioned storage control line 31. During operation of the image pickup apparatus 100, the potential of the storage control line 31 is controlled to make the potential of the counter electrode 12c higher than the potential of the pixel electrode 12a, for example. Thereby, the positive charge among the positive and negative charges generated by the photoelectric conversion can be selectively collected by the pixel electrode 12a. The counter electrode 12c may be formed in the form of a single layer continuous over a plurality of pixels 10A. This makes it possible to collectively apply a predetermined potential to the counter electrodes 12c of the plurality of pixels 10A.

The pixel electrode 12a is formed of, for example, a metal, a metal nitride, or polysilicon to which conductivity is imparted by doping with impurities. The metal here is, for example, aluminum or copper. The pixel electrode 12a is electrically separated from the pixel electrode 12a of the other pixel 10 by being spatially separated from the pixel electrode 12a of the other adjacent pixel 10.

The conductive structure 89 includes a plurality of wires and contact plugs, one end of which is connected to a pixel electrode 12a. The other end of the conductive structure 89 is connected to an n-type impurity region 67n, which is an example of a charge storage region described later. The plurality of wires may be formed of, for example, a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide. As will be described later, the plurality of wirings and contact plugs may be formed of photoresist provided with conductivity. By connecting the other end of the conductive structure 89 to the circuit element formed on the semiconductor substrate 60, the pixel electrode 12a of the photoelectric conversion unit 12 and the circuit on the semiconductor substrate 60 are electrically connected to each other.

Here, attention is paid to the semiconductor substrate 60. As schematically shown in FIG. 3, the semiconductor substrate 60 includes a support substrate 61 and one or more semiconductor layers formed on the support substrate 61. Here, a p-type silicon substrate is exemplified as the support substrate 61.

In the configuration exemplified in FIG. 3, the semiconductor substrate 60 has a p-type semiconductor layer 61p on the support substrate 61, an n-type semiconductor layer 62n on the p-type semiconductor layer 61p, and a p-type semiconductor layer on the n-type semiconductor layer 62n. It has 63p and a p-type semiconductor layer 65p as a first semiconductor layer located on the p-type semiconductor layer 63p. Typically, the p-type semiconductor layer 63p is formed over the entire surface of the support substrate 61. Each of the p-type semiconductor layer 61p, the n-type semiconductor layer 62n, the p-type semiconductor layer 63p, and the p-type semiconductor layer 65p is typically formed by ion implantation of impurities into the semiconductor layer formed by epitaxial growth. The impurity concentrations in the p-type semiconductor layer 63p and the p-type semiconductor layer 65p are similar to each other and higher than the impurity concentration in the p-type semiconductor layer 61p.

The n-type semiconductor layer 62n as the second semiconductor layer is located between the p-type semiconductor layer 61p and the p-type semiconductor layer 63p. Although not shown in FIG. 3, a well contact (not shown) is connected to the n-type semiconductor layer 62n. The well contact is provided outside the image pickup region R1, and the potential of the n-type semiconductor layer 62n is controlled via the well contact during the operation of the image pickup apparatus 100. By providing the n-type semiconductor layer 62n, the inflow of minority carriers from the support substrate 61 or peripheral circuits into the charge storage region where signal charges are stored is suppressed.

Further, in this example, the semiconductor substrate 60 has a p-type region 64 provided between the p-type semiconductor layer 63p and the support substrate 61 so as to penetrate the p-type semiconductor layer 61p and the n-type semiconductor layer 62n. Have. The p-type region 64 has a higher impurity concentration than the p-type semiconductor layer 63p and the p-type semiconductor layer 65p, and has a function of electrically connecting the p-type semiconductor layer 63p and the support substrate 61 to each other.

The support substrate 61 has a connection with a substrate contact provided outside the imaging region R1, which is not shown in FIG. During the operation of the image pickup apparatus 100, the potentials of the support substrate 61 and the p-type semiconductor layer 63p are controlled via the substrate contacts. Further, by arranging the p-type semiconductor layer 65p so as to be in contact with the p-type semiconductor layer 63p, it is possible to control the potential of the p-type semiconductor layer 65p via the p-type semiconductor layer 63p during the operation of the image pickup apparatus 100. be.

In the configuration illustrated in FIG. 3, the n-type impurity region 67n, which is an example of the charge storage region, is formed in the p-type semiconductor layer 65p. As schematically shown in FIG. 3, the n-type impurity region 67n is formed in the vicinity of the surface of the semiconductor substrate 60, and at least a part thereof is located on the surface of the semiconductor substrate 60. Here, the n-type impurity region 67n includes a first region 67a and a second region 67b located in the first region 67a and having a relatively higher impurity concentration than the first region 67a.

An insulating layer is arranged on the main surface of the semiconductor substrate 60 on the photoelectric conversion structure 12A side. In this example, the main surface of the semiconductor substrate 60 on the photoelectric conversion structure 12A side is covered with the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73. The first insulating layer 71 is, for example, a silicon nitride layer. The second insulating layer 72 is, for example, a silicon dioxide layer, and the third insulating layer 73 is, for example, a silicon dioxide layer. The second insulating layer 72 may have a laminated structure including a plurality of insulating layers, and similarly, the third insulating layer 73 may also have a laminated structure including a plurality of insulating layers. The third insulating layer 73 is a so-called gate insulating layer.

The second insulating layer 72 and the gate electrodes 22e, 24e, and 26e are provided on the third insulating layer 73. The gate electrodes 22e, 24e, and 26e are formed with high concentrations of n-type impurities by ion implantation. Due to this n-type impurity, the gate electrodes 22e, 24e, and 26e have low resistance and are imparted with conductivity. A fourth insulating layer 74 is provided on the side wall portion of the gate electrodes 22e, 24e, and 26e via a part of the second insulating layer 72. A sidewall spacer (also referred to as a "sidewall") is formed on the fourth insulating layer. The fourth insulating layer has a laminated structure including a plurality of insulating layers. For example, it is preferably formed of a plurality of layers of a silicon dioxide layer and a silicon nitride layer, and it is desirable that the silicon nitride layer is in contact with the first insulating layer 71. As a result, during dry etching of sidewall formation, the second insulating layer 72 functions as an etching stopper due to the etching selectivity between the silicon nitride layer of the fourth insulating layer 74 and the silicon dioxide of the second insulating layer 72. Etching to the mold impurity region 67n can be suppressed. As a result, the surface of the semiconductor substrate 60 in the imaging region R1 does not expose the semiconductor substrate 60 during dry etching, and the particles ionized by plasma irradiation during dry etching do not directly collide with the n-type impurity region 67n. Dark current is reduced by suppressing crystal defects due to damage during so-called dry etching.

The second insulating layer 72 is an offset sidewall spacer (also referred to as an “offset sidewall”), which reduces the overlap capacitance for improving the circuit speed of the transistor when forming the transistor of the peripheral circuit 40 and silicides in the semiconductor substrate 60. This layer is provided to improve the short channel of the transistor by heat treatment in a furnace furnace (diffusion furnace) before layer formation. This heat treatment is carried out to recover defects in the impurity region formed by ion implantation. The device rules created are used when forming transistors with gate lengths finer than submicrons, preferably finer than 130 nm. When the gate length is longer than 150 nm, the second insulating layer 72 may be omitted.

The laminated structure of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73 is provided with a contact hole h1, a contact hole h2, a contact hole h3, and a contact hole h4. That is, each of the contact hole h1, the contact hole h2, the contact hole h3, and the contact hole h4 is connected to the semiconductor substrate 60 via the laminated structure of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73. ing. For example, the contact hole h1 is provided on the second region 67b of the n-type impurity region 67n. The contact hole h2 is provided on the n-type impurity region 68an. The contact hole h3 is provided on the n-type impurity region 68bn. The contact hole h4 is provided on the n-type impurity region 68dn.

In the example shown in FIG. 3, the contact hole h1 is provided in the contact plug Cp1 connected to the conductive structure 89 via the silicide layer 75, and is connected to the second region 67b. As a result, the n-type impurity region 67n is electrically connected to the pixel electrode 12a of the photoelectric conversion unit 12 via the contact plug Cp1, the silicide layer 75, and the conductive structure 89. The signal charge generated by the photoelectric conversion unit 12 is accumulated in the n-type impurity region 67n.

The junction capacitance formed by the pn junction between the p-type semiconductor layer 65p as a p-well and the n-type impurity region 67n functions as a capacitance for accumulating at least a part of the signal charge. As a result, the n-type impurity region 67n functions as a charge storage region that temporarily holds the signal charge. It can be said that the conductive structure 89 and the n-type impurity region 67n form at least a part of the above-mentioned charge storage node FD.

The formation of the second region 67b in the n-type impurity region 67n is not essential. However, by connecting the contact plug Cp1 to the second region 67b having a relatively high impurity concentration, the effect of reducing the contact resistance can be obtained.

A signal detection circuit 14A is formed on the semiconductor substrate 60. As described above, the signal detection circuit 14A includes a signal detection transistor 22, an address transistor 24, and a reset transistor 26.

The signal detection transistor 22 includes an n-type impurity region 68bn as one of the source and drain, and the n-type impurity region 68cn as the other of the source and drain. The signal detection transistor 22 further includes a gate electrode 22e provided on the third insulating layer 73. The portion of the third insulating layer 73 located between the gate electrode 22e and the semiconductor substrate 60 functions as the gate insulating layer of the signal detection transistor 22. The gate electrode 22e is connected to the pixel electrode 12a and the n-type impurity region 67n via the contact plug Cp5 and the conductive structure 89. For example, the gate electrode 22e is connected to a portion of the conductive structure 89 where the pixel electrode 12a and the contact plug Cp1 are connected to each other in the layer where the address signal line 34 and the reset signal line 36 are located.

A contact plug Cp3 is connected to the n-type impurity region 68bn. A part of the contact plug Cp3 is provided in the contact hole h3. The power supply wiring 32 described above as a source follower power supply is electrically connected to the contact plug Cp3. The power supply wiring 32 is not shown in FIG.

The address transistor 24 includes an n-type impurity region 68cn as one of the source and drain, and the n-type impurity region 68dn as the other of the source and drain. The address transistor 24 further includes a gate electrode 24e provided on the third insulating layer 73. The portion of the third insulating layer 73 located between the gate electrode 24e and the semiconductor substrate 60 functions as the gate insulating layer of the address transistor 24. The address signal line 34 is connected to the gate electrode 24e via the contact plug Cp6 and the conductive structure 89. In this example, the n-type impurity region 68cn is shared between the address transistor 24 and the signal detection transistor 22, so that these transistors are electrically connected to each other.

A contact plug Cp4 is connected to the n-type impurity region 68dn. A part of the contact plug Cp4 is provided in the contact hole h4. The contact plug Cp4 is electrically connected to the vertical signal line 35.

The reset transistor 26 is an example of a first transistor electrically connected to a charge storage region, and has an n-type impurity region 67n, which is an n-type charge storage region, as a source as a first source and a drain as a first drain. Included as one and includes the n-type impurity region 68an as the other of the drain and source. That is, one of the source and drain of the reset transistor 26 and the charge storage region are shared, whereby one of the source and drain of the reset transistor 26 and the charge storage region are electrically connected. The reset transistor 26 further includes a gate electrode 26e as a first gate electrode provided on the third insulating layer 73. The portion located between the gate electrode 26e and the semiconductor substrate 60 functions as a gate insulating layer of the reset transistor 26. The reset signal line 36 is connected to the gate electrode 26e via a contact plug Cp7, a silicide layer 75, and a conductive structure 89, which are examples of the first plug. The contact plug Cp7 is connected to the gate electrode 26e as the first gate electrode, and is formed of, for example, polyvinyl that is doped with impurities in order to have conductivity.

The n-type impurity region 68an is connected to the contact plug Cp2 as shown in FIG. A part of the contact plug Cp2 is provided in the contact hole h2. The contact plug Cp2 is electrically connected to the feedback line 53 via the silicide layer 75 and the conductive structure 89.

A silicide layer 75 (that is, a metal semiconductor compound layer), which is an example of the first silicide layer containing the first silicide, is formed on the upper surface and the side surface of the contact plugs Cp1 to Cp7. The silicide layer 75 is made of a metal layer, and can reduce the contact resistance at the connection portion with the conductive structure 89. Since the silicide layer 75 is deposited by using the long slow sputtering method, the film thickness on the side surfaces of the contact plugs Cp1 to Cp7 is thinner than that on the upper surface.

The first insulating layer 71 is in contact with the silicide layer 75 and the fourth insulating layer 74 which is a sidewall. The first insulating layer 71 is a silicon nitride layer, and the interlayer insulating layer 90 is a silicon dioxide layer. During contact etching of the conductive structure 89, the first insulating layer 71 functions as an etching stopper due to the etching selectivity between the silicon nitride layer of the first insulating layer 71 and the silicon dioxide of the interlayer insulating layer 90, and excessive etching of the silicide layer 75 is performed. Can be reduced. In particular, it is effective in reducing excessive etching of the silicide layer 75 on the contact plugs Cp5, Cp6, and Cp7 on the gate electrodes 22e, 24e, and 26e whose height is increased by the film thickness of the gate electrode.

The first insulating layer 71 may be in contact with the bottom portion (below the contact plug) on which the silicide layer 75 of the contact plugs Cp1 to 7 is not formed. At the time of forming the silicide layer 75, a silicide block layer (not shown), which is a protective layer for selectively blocking the formation of the silicide layer 75, was present, but was subsequently removed. That is, at the time of forming the silicide, the metal is contained in the silicide block layer with a metal content of about 1.0 × 10 ¹² to 1.0 × 10 ¹³ [atoms / cm ^-2 ], so that after the silicide layer 75 is formed, the metal is contained. The silicide block layer has been removed by a chemical solution (wet etching). The silicide block layer is formed of, for example, a silicon oxide layer, specifically, a silicon dioxide layer having a film thickness of about 20 to 35 nm, and after the silicide layer 75 is formed, the silicon dioxide layer is reduced to about 10 to 25 nm. The reason why the film thickness of silicon dioxide decreases is to remove oxide residue that inhibits the reaction before sputtering called single-wafer chemical dry cleaning (CDT) during sputtering film formation when forming a metal. This is because of the treatment for cleaning the surface of the contact plugs Cp1 to Cp1 and the film reduction due to the chemical solution at the time of forming the silicide layer 75. Further, the silicon dioxide layer is used as the silicide block layer because it can be easily removed by wet etching. Another possible insulating layer used in the semiconductor manufacturing process is a silicon nitride layer, which is difficult to remove by wet etching. For example, the silicon nitride layer can be wet-etched with phosphoric acid at a high temperature (150 to 170 ° C.), but is not suitable for the step of removing the silicide block layer because it is also etched with a metal at the same time. Therefore, in this embodiment, a silicon dioxide layer is used as the silicide block layer.

The first insulating layer 71 is formed by a film forming method called ALD (Atomic Layer Deposition) having good coverage, and is also formed in the gap between the bottom of the contact plugs Cp1 to Cp1 to 7 and the second insulating layer 72. In this cross-sectional view, the contact plugs Cp1 to Cp1 to 7 are schematically shown as a quadrangle, but may have an inverted trapezoidal shape.

The silicide block layer is formed by forming a silicon dioxide layer over the entire surface of the semiconductor substrate 60 after forming a non- silicide transistor and a non- silicide resistance element in the peripheral circuit 40 and forming a second insulating layer 72 in the imaging region R1. It is formed. The silicide block layer is a film that is selectively removed by photolithography and dry etching and is left for forming a non- silicide transistor or a non- silicide resistance element, and a film left in the imaging region R1.

The first insulating layer 71 is a characteristic structure in contact with the fourth insulating layer 74 (sidewall) and the silicide layer 75 on the contact plugs Cp5, Cp6, and Cp7 on the gate electrodes 22e, 24e, and 26e. Due to the formation of the first insulating layer 71, the metal at the time of forming the silicide penetrates into the n-type impurity region 67n through the contact hole h1 by the heat treatment in the post-step after the silicide formation, and the metal diffused into the n-type impurity region 67n causes impurities. It is possible to prevent the formation of levels.

FIGS. 5 to 7 show in detail the process of forming the first insulating layer 71 in the imaging region R1 in the order of steps.

FIG. 5 is an enlarged layout view and cross-sectional view of the vicinity of the reset transistor 26 in the imaging region R1, and shows a view immediately after the silicide layer 75 is formed on the contact plugs Cp1 to Cp7. That is, FIG. 5 shows a first gate electrode and a first gate electrode on a semiconductor substrate including a first transistor including a first gate electrode, a first sidewall located on the side wall of the first gate electrode, a first source and a first drain. 1 A first step of forming a protective layer located above the sidewall, a second step of forming a first plug that penetrates the protective layer and connects to the first gate electrode, and on the first plug and the protective layer. The cross-sectional view immediately after the completion of the 3rd step of forming the silicide is shown. Although the reset transistor 26 is illustrated, the address transistor 24 and the signal detection transistor 22 are shown as an example because the formation process is the same. FIG. 5A shows a layout, and FIG. 5B shows a cross-sectional view taken along the line VV in FIG. 5A. As shown in FIG. 5B, the silicide layer 75 is formed on the upper surface and the side surface of the contact plugs Cp1, Cp2, and Cp7. The contact plugs Cp1, Cp2 and Cp7 are made of phosphorus-doped polysilicon. Next, the phosphorus-doped polysilicon has been heat treated to impart conductivity. Examples of the first silicide include titanium silicide, cobalt silicide, nickel silicide, and the like, but in the present embodiment, the silicide layer 75 will be described as nickel (Ni) silicide which is advantageous in thin wire resistance. The silicide layer 75 containing Ni is preferably selected from a NiSi layer, a NiPtSi layer, and a laminate thereof, and can be formed as follows. Here, an example of forming a NiSi layer will be described. First, a metal layer (thickness of about 5 to 20 nm), which is a Ni layer, is formed on the upper surfaces of the contact plugs Cp1, Cp2, Cp7 and the silicide block layer 76 by a sputtering method. As the sputtering method, a long slow sputtering method is used. The long slow sputtering method has a long distance between the target (NiSi alloy in this case) and the semiconductor substrate 60, and the normal sputtering method has a distance of about 40 to 70 mm, but the long slow sputtering method has a distance of about 200 to 300 mm. .. As a result, when plasma is generated in the vacuum chamber, sputtered particles (not shown) are radially ejected by the argon gas ions colliding with the target and reach the semiconductor substrate 60. If the distance to the semiconductor substrate 60 is short, the sputtered particles that are radially ejected are deposited on the side walls of the contact plugs Cp1, Cp2, and Cp7 because there are many sputtered particle components that are obliquely incident. However, if the distance to the silicon substrate is long as in the long slow sputtering method, the sputtered particles increase the directivity, reduce the components incident from an angle, and suppress the deposition on the side wall portion. This has the advantage that the chemical solution time for the bottom of the contact plugs Cp1, Cp2, and Cp7 when removing the silicide block layer 76 can be shortened. At this time, Ni is contained in the silicide block layer 76. Subsequently, the first heat treatment is performed in a lample annealing device, for example, at 250 to 350 ° C.

As a result, the Ni2Si layer is formed. Then, the unreacted metal layer is selectively removed from the Ni2Si layer with a chemical solution using SPM (hydrosulfuric acid hydrogen peroxide, Salfaric Acid / Hydrogen Peroxide (/ Water) Mixture) or the like. At this time, Ni on the silicide block layer 76 is removed. Subsequently, a second heat treatment is performed in a lample annealing device, for example, at 350 to 400 ° C. As a result, a NiSi layer is formed. In FIG. 5, the contact plugs Cp1, Cp2, and Cp7 are not exposed in a plan view. The gate electrode 26e of the reset transistor 26 is covered with a second insulating layer 72 except for the connection portion (h5) of the contact plug Cp7 on the upper surface and the side wall portion except for the third insulating layer 73 which is in contact with the lower surface. In FIG. 5, the gate electrode 26e of the reset transistor 26 is not exposed in a plan view. The silicide block layer 76 covers the second insulating layer 72 and is in contact with the fourth insulating layer 74 (sidewall) except for the contact holes h1, h2, and h5. In FIG. 5, only the silicide layer 75 and the silicide block layer 76 are exposed in a plan view.

6A and 6B are an enlarged layout view (FIG. 6 (a)) and a sectional view (FIG. 6 (a) sectional view taken along the line VI-VI) in the vicinity of the reset transistor 26 in the imaging region R1. FIG. The figure after removing the silicide block layer 76 which is a protective layer which follows is shown. That is, FIG. 6 shows a cross-sectional view immediately after the fourth step of removing the protective layer is completed. The silicide block layer 76 of FIG. 5 is selectively etched with a chemical solution so as to have an etching selectivity with that of the silicide layer 75. Here, there are two types of etching, wet etching and dry etching. The reason for using wet etching is that compared to dry etching, it is possible to suppress etching damage to the surface layer of the semiconductor substrate 60 due to ion impact due to plasma generation. This is because. Further, it is desirable to use wet etching because it is possible to prevent the charged particles from charging up to the third insulating layer 73.

As a specific chemical solution, the silicide block layer 76 having a size of about 10 to 25 nm can be removed by using an APM (Ammonia-hydrogen Peroxide Mixture) solution. At this time, the silicide layer 75 is not etched by the APM solution. A second insulating layer 72 is formed on the side wall of the gate electrode 26e so as to surround the gate electrode 26e, and a fourth insulating layer 74 is formed so as to surround the side wall of the gate electrode 26e via the second insulating layer 72. There is. After removing the silicide block layer 76 shown in FIG. 6, the silicide layer 75, the second insulating layer 72, and the fourth insulating layer 74 are exposed in a plan view.

As shown in FIG. 6B, the radius of the contact hole h1 is d, and the radius of the contact plug Cp1 including the silicide layer 75 is D. When the width (D) is large, the first insulating layer 71 is less likely to enter the gap of (Dd). Therefore, when the width (D) is 30 nm or more, a part of the silicide block layer 76 may remain in the vicinity of the contact hole h1. At this time, the silicide block layer 76 left in the vicinity of the contact hole h1 is not exposed to the metal because it is protected by the contact plug Cp1 during the sputtering film formation of the metal at the time of forming the silicide. Therefore, since the silicide block layer 76 left in the vicinity of the contact hole h1 is a layer that is not contaminated with metal, it does not cause deterioration of dark current. In general, the process design of the (Dd) width is determined by the exposure equipment (lithography) used in the process, and the superposition accuracy (that is, the deviation when a new pattern is formed on the already formed pattern). ) Is good, the width (D) can be reduced.

7A and 7B are an enlarged layout view ((a) of FIG. 7) and a cross-sectional view (cross-sectional view of FIG. 7A by lines VII-VII) in the vicinity of the reset transistor 26 in the imaging region R1. The figure immediately after forming the contact plugs Ca1 to Ca3 is shown. That is, FIG. 7 shows a cross-sectional view immediately after the fifth step of forming the first insulating layer 71 covering the first sidewall and the first silicide, and the subsequent formation of the second contact plugs Ca1 to Ca3. The second contact plugs Ca1, Ca2, and Ca3 are connected to the first wiring layer (not shown) included in the conductive structure 89. At this time, the interlayer insulating layer 90 is a silicon dioxide layer formed by CVD (Chemical Vapor Deposition), and is polished by CMP (Chemical Vapor Deposition) and flattened before the formation of the second contact plug. During etching to form the second contact plugs Ca1, Ca2, and Ca3, the first insulating layer 71 serves as an etching stopper. After that, a conductor such as W (tungsten), which is a conductive material, is embedded in the formed holes. Immediately after the formation of the second contact plug, the interlayer insulating layer 90 and the second contact plugs Ca1, Ca2, and Ca3 are exposed in a plan view. The first insulating layer 71 is in contact with the interlayer insulating layer 90 below.

FIG. 8 is a cross-sectional view ((a) of FIG. 8) showing a device structure in which the silicide block layer 76 of the imaging region of the imaging apparatus according to the comparative example is left, and imaging of the imaging apparatus 100 according to the first embodiment of the present disclosure. A cross-sectional view ((b) of FIG. 8) of the device structure from which the silicide block layer 76 of the region R1 has been removed is shown. In FIG. 8A, a schematic view shows that a metal (annular shape in the drawing) is contained in the silicide block layer 76 except for the bottoms of the contact plugs Cp1, Cp2, and Cp7. The metal is captured in the n-type impurity region 67n via the polysilicon, which is the material of the contact plug Cp1, by diffusion due to the heat treatment in the subsequent step, and forms an impurity level due to the metal. The impurity level of this metal causes deterioration of dark current. In FIG. 8B, since the layer containing the metal does not exist, the impurity level of the metal is not formed and the concern about deterioration of the dark current is reduced.

As described above, FIGS. 5 to 8 show the process of removing the silicide block layer 76 and forming the first insulating layer 71 in the imaging region R1 according to the process order. Next, the peripheral region R2 is also shown in the same manner.

FIG. 9 shows a cross-sectional view of the peripheral region R2 after the formation of the first insulating layer 71. 9 (a) shows a silicide transistor 55 which is an example of a second transistor, FIG. 9 (b) shows a non- silicide transistor 56 which is an example of a third transistor, and FIG. 9 (c) shows. , The non- silicide resistance element 57, which is an example of the non- silicide resistance element, is shown.

In FIG. 9A, a p-type impurity region (p-well) 80 is formed on the semiconductor substrate 60 including the device separation region 69. Hereinafter, the n-type MOS transistor is mainly described, but a p-type MOS transistor may be used. Here, the formation of the p-type MOS transistor will be omitted. In the p-type impurity region 80, the n-type impurity region 81 and the n + -type impurity region 82 are injected to form an LDD (Lightly Doped Drain) structure. A silicide layer 75, which is an example of a second silicide layer containing the second silicide, is formed on the source and drain formed in the n + type impurity region 82, which is an example of the second source and the second drain. Examples of the second silicide include titanium silicide, cobalt silicide, nickel silicide and the like. A gate electrode 55e is formed via a third insulating layer 73, which is a gate insulating layer, and a silicide layer 75 is also formed on the gate electrode 55e. A second insulating layer 72 is formed on the side wall of the gate electrode 55e, and unlike the imaging region R1, it does not remain on the surface of the semiconductor substrate 60. The fourth insulating layer 74, which is a sidewall, is formed so as to be in contact with the second insulating layer 72. The first insulating layer 71 is in contact with the silicide layer 75.

FIG. 9B shows the structure of the non- silicide transistor 56 which is an example of the third transistor, and is above the source and drain formed in the n + type impurity region 82 which is an example of the third source and the third drain. , The silicide layer 75 is not formed on the gate electrode 56e, which is an example of the third gate electrode. The first insulating layer 71 is in contact with the upper surfaces of the source and drain formed in the n + type impurity region 82 and the upper surface of the gate electrode 56e. In recent years, the role of this transistor has become highly integrated as the transistor becomes finer and denser, and as a result, it becomes vulnerable to damage caused by electrostatic discharge (hereinafter referred to as surge). For example, a surge invading from an external connection pad destroys transistors included in an input circuit, an output circuit, an input / output circuit, an internal circuit, and the like, resulting in deterioration of performance. Therefore, the peripheral circuit 40 has an electrostatic discharge having a region between the pad for external connection and the input circuit, the output circuit, the input / output circuit, or the internal circuit so that the source / drain portion of the transistor does not form silicide. A surge countermeasure is implemented by providing a (ESD) protection transistor. The non- silicide transistor 56 shown in FIG. 9B is suitable as such an ESD protection transistor.

FIG. 9C shows a non- silicide resistance element 57, which is formed on the element separation region 69. A resistance element main body 57e, which is a gate electrode composed of polysilicon as an example of the third semiconductor layer, is formed via a third insulating layer 73, which is a gate insulating layer, and a second side wall of the resistance element main body 57e is formed. The two insulating layers 72 are formed, and the fourth insulating layer 74, which is a sidewall, is formed via the second insulating layer 72. A first insulating layer 71 is coated on the resistance element main body 57e. The non- silicide resistance element 57 can be used for forming a high-precision ADC having a resolution exceeding 10 bits used in a column signal processing circuit and forming a DAC that can be formed in a small area.

10 to 15 show in detail the process up to the formation of the first insulating layer 71 in the peripheral region R2 shown in FIG. 9 in the order of steps. 10 to 15 (a) show the silicide transistor 55 shown in FIG. 9 (a), and FIGS. 10 to 15 (b) show the non- silicide transistor 56 shown in FIG. 9 (b). 10 to 15 (c) show the non- silicide resistance element 57 shown in FIG. 9 (c).

FIG. 10 shows a cross-sectional view of the second insulating layer 72 after film formation in the peripheral region R2. On the third insulating layer 73, which is the gate insulating layer, the gate electrodes 55e and 56e made of a polysilicon layer and the resistance element main body 57e are formed by chemical vapor deposition (CVD). N-type impurities are introduced into the gate electrodes 55e and 56e and the resistance element main body 57e by ion implantation. The n-type impurity is, for example, phosphorus. Next, the polysilicon layer and the gate insulating layer are etched by photolithography and dry etching. Next, an HTO (High Temperature Oxide) film is formed by CVD at 700 to 800 ° C., and the second insulating layer 72 is coated with the gate electrodes 55e and 56e, the resistance element main body 57e, and the surface of the semiconductor substrate 60.

FIG. 11 shows a cross-sectional view of the fourth insulating layer 74 after film formation in the peripheral region R2. The second insulating layer 72 is dry-etched and exposed to the surface of the semiconductor substrate 60. At this time, the second insulating layer 72 is selectively left on the side wall portions of the gate electrodes 55e and 56e and the resistance element main body 57e by anisotropic etching during dry etching. In the silicide transistor 55 formed in FIG. 11A, the second insulating layer 72 is called an offset sidewall layer, and is unique to the method of reducing the overlap capacitance of the silicide transistor 55 and manufacturing the image pickup apparatus 100. It plays a major role in improving the short channel of the silicide transistor 55, which deteriorates from the heat treatment by the furnace furnace (diffusion furnace) before layer formation. Further, regarding the dry etching at the time of forming the offset sidewall layer, the imaging region R1 is covered with a resist (not shown) and is not dry-etched. Therefore, the second insulating layer 72 remains in the imaging region R1.

Next, the n-type impurity region 81 is formed using the gate electrodes 55e and 56e, the resistance element main body 57e, and the second insulating layer 72 as masks. This n-type impurity region 81 is performed to form an LDD, and is also called extension injection. Next, the fourth insulating layer 74 is formed by CVD. The fourth insulating layer 74 may be a single film or a plurality of layers. The contents described below are a two-layer structure of a silicon dioxide layer and a silicon nitride layer, and the silicon nitride layer is formed on the outer side further away from the gate electrode. For example, in a batch type vertical hot wall type decompression CVD apparatus, the silicon dioxide layer is formed by using TEOS ( _{TetraEthOxySilane, Si (OC 2H 5) 4 ) as} an organic liquid raw material gas. This technique is used because of its excellent film thickness uniformity and coverage. Next, the silicon nitride layer is formed with BTBAS (BIS (TERTIARY-BUTYL-AMINO) SILANE, SiH _{2 (} NH (C 4H ₉ )) ₂ ) as the organic liquid raw material gas. .. This method is used because of the low film formation temperature and excellent coverage.

FIG. 12 shows a cross-sectional view of the silicide block layer 76 in the peripheral region R2 after film formation. The fourth insulating layer 74 is etched by dry etching to expose the surface of the semiconductor substrate 60. Then, source / drain implantation is performed by ion implantation. The source / drain injection has a higher impurity concentration than the extension injection performed in FIG. Extension injection and source / drain injection are not performed on the non- silicide resistance element 57.

Next, the silicide block layer 76 is formed of a silicon dioxide layer having a film thickness of about 20 to 35 nm. The silicide block layer 76 is formed by, for example, a quasi-normal pressure CVD (that is, SACVD (Sub-Atmosphere Pressure-CVD)) method using TEOS and ozone as a source gas. The silicon dioxide layer can be grown by performing a gas phase reaction in a temperature range of 350 to 450 ° C. and a pressure range of 10 to 50 Torr. The SACVD method is used because it can be processed at low temperature and has excellent coverage. Since all the impurity formation by injection into the semiconductor substrate 60 in the imaging region R1 and the peripheral region R2 is completed in the steps up to the silicide block layer 76, it is possible to suppress the diffusion of impurities by forming a film by low temperature treatment. It will be possible. Further, due to the recent reduction in the element area, the distance between the transistor elements has been reduced in order to increase the number of wafers that can be taken. Therefore, since the space between the gate electrodes of the transistor in the peripheral region R2 is becoming narrower, the SACVD method with good step coverage can form a film without generating voids (gap) between the gate electrodes. become.

Next, as a sixth step of heating the semiconductor substrate 60 in the diffusion furnace, the temperature is 800 ° C. by the diffusion furnace in order to recover the crystal defects due to the ion implantation in the n-type impurity region 67n portion of the imaging region R1 and the damage during dry etching. The above heat treatment is added. As a result, the dark current is reduced and the film quality of the silicide block layer 76 formed by the SACVD method becomes dense, and when the silicide layer 75 is formed in the next step, the metal penetrates the silicide block layer 76 and the surface of the semiconductor substrate 60 is formed. Metal is trapped in the silicide block layer 76 without reaching. If a heat treatment of 800 ° C. or higher is added by a diffusion furnace after the formation of the silicide layer 75, the low-resistance metal silicide has a problem that aggregation occurs when the high-temperature heat treatment is applied and the resistance value increases. It is desirable to do it.

FIG. 13 shows a cross-sectional view of the peripheral region R2 after the formation of the silicide layer 75. That is, FIG. 13 shows a cross-sectional view immediately after the third step of forming silicide is completed. After covering the three regions of the non- silicide transistor 56 and the non- silicide resistance element 57 of the imaging region R1 and the peripheral region R2 with a resist (not shown), dry etching is performed. As a result, the silicide transistor 55 is exposed on the n + type impurity region 82 and the gate electrode 55e, which are sources and drains on the semiconductor substrate 60. Next, the silicide layer 75 containing Ni is formed on the n + type impurity region 82 and the gate electrode 55e by the method described in FIG. The silicide block layer 76 formed on the non- silicide transistor 56 and the non- silicide resistance element 57 contains a metal at this time.

FIG. 14 shows a cross-sectional view of the peripheral region R2 after removal of the silicide block layer 76. That is, FIG. 14 shows a cross-sectional view immediately after the fourth step of removing the protective layer is completed. As described in FIG. 6, the APM can selectively remove only the silicide block layer 76 without removing the silicide layer 75. At this time, in order to suppress etching by APM on the second insulating layer 72 and the element separation region 69 formed of silicon dioxide, the concentration of the APM chemical solution is diluted to about 1 to 10%. As a result, it becomes possible to cope with only the silicide block layer 76 by adjusting the time of APM etching, and it becomes possible to minimize the etching to the second insulating layer 72 and the element separation region 69.

FIG. 15 shows a cross-sectional view of the first insulating layer 71 after film formation in the peripheral region R2. That is, FIG. 15 shows a cross-sectional view immediately after the fifth step of forming the first insulating layer covering the silicide is completed. A silicon nitride layer (ALD-SiN layer) is formed by an atomic layer deposition method (ALD method). For example, when forming a silicon nitride layer, DCS (SiH ₂ Cl ₂ , dichlorsilane) and NH ₃ (ammonia) are alternately supplied to enable high-quality film formation at a low temperature of 300 to 500 ° C. As described above, in the ALD method, the film formation is performed by alternately supplying a plurality of types of reactive gases one by one. The film thickness is controlled by the number of cycles of the reactive gas supply. For example, assuming that the film formation rate is 0.1 nm / cycle, when forming a film of 2 nm, the treatment is performed for 20 cycles. This enables uniform film thickness control at the atomic layer level. Further, since the ALD method has sufficiently high coverage, it is possible to form a film even with a slight gap after removal of the silicide block layer 76 shown in FIG.

16 is a cross-sectional view ((a) to (c) of FIGS. 16) after the formation of the first insulating layer 71 in the peripheral region R2 of the image pickup apparatus 100 according to the first embodiment of the present disclosure, and the silicide block layer. The cross-sectional view ((d)-(f) of FIG. 16) after the formation of the 1st insulating layer 71 of the image pickup apparatus which concerns on the comparative example when 76 is left is shown. 16 (a) and 16 (d) indicate a silicide transistor 55, FIGS. 16 (b) and 16 (e) indicate a non- silicide transistor 56, and FIGS. 16 (c) and 16 (f). However, the non- silicide resistance element 57 is shown. The silicide transistor 55 shown in FIGS. 16A and 16D has the same structure. On the other hand, the non- silicide transistor 56 shown in FIGS. 16B and 16 has a different structure. The non-silicide transistor 56 shown in FIG. 16 (b) does not have the silicide block layer 76 formed below the first insulating layer 71, but the non- silicide transistor 56 shown in FIG. 16 (e). Is different in that the silicide block layer 76 is formed below the first insulating layer 71. The non- silicide resistance element 57 shown in FIGS. 16 (c) and 16 (f) has a different structure. The non-silicide resistance element 57 shown in FIG. 16 (c) does not have the silicide block layer 76 formed below the first insulating layer 71, but the non- silicide resistance element shown in FIG. 16 (f). 57 is different in that the silicide block layer 76 is formed below the first insulating layer 71.

(Modified Example of Embodiment 1)
FIG. 17 is a cross-sectional view schematically showing an example of the device structure of the pixel 10A of the image pickup apparatus according to the modified example of the first embodiment of the present disclosure. Each contact plug Cp1 to Cp7 differs from the first embodiment shown in FIG. 3 only in that the silicide layer 75 on the upper surface and the side surface of the contact plug is removed. In order to reduce the contact resistance in the connection between the contact plugs Cp1 to Cp1 to 7 and the conductive structure, it is desirable to form the silicide layer 75, but when the contact plugs Cp1 to 7 are doped with impurities at a high concentration, silicides are formed. The layer 75 may be omitted.

In the manufacture of the image pickup apparatus according to this modification, after the contact plugs Cp1 to Cp7 are formed, a protective film is additionally formed with a silicon dioxide layer having a film thickness of about 20 to 35 nm by the SACVD method. In order to form a silicide transistor which is an example of the second transistor in the peripheral region R2, it is necessary to expose the semiconductor substrate and the surface portion of the gate electrode. Therefore, unlike the first embodiment, it is necessary to adjust the dry etching time of the silicide block layer 76. Further, after the silicide layer 75 is formed on the second transistor, unlike the first embodiment, the film thickness of the silicide block layer 76 is different, so that it is necessary to adjust the APM etching time. As described above, the only difference between the manufacturing process and the first embodiment is the change in the dry etching time and the APM etching time of the silisad block layer 76, and all the other manufacturing processes are the same as those in the first embodiment. It is feasible.

From the above, in the image pickup apparatus 100 of the present disclosure, the dark current is reduced by removing the silicide block layer 76, and the transistor provided with the silicide enables high-speed operation. Further, by providing a non- silicide transistor in the peripheral circuit, ESD countermeasures are taken and destruction of the transistor element is suppressed. Further, by using the non- silicide resistance element in the ADC or DAC in the peripheral circuit, the element performance required in the column signal processing circuit is provided, and the pixel characteristics are improved.

(Embodiment 2)
Next, the structure and function of the image pickup apparatus according to the second embodiment will be described with reference to FIGS. 18 to 20.

FIG. 18 schematically shows an exemplary circuit configuration of the image pickup apparatus 200 according to the second embodiment of the present disclosure. In FIG. 18, four pixels 210A arranged in two rows and two columns are shown as representatives in order to avoid complication of the drawing. Each of these pixels 210A is an example of the pixel 10 shown in FIG. 1, has an embedded photodiode 228 as a photoelectric conversion unit 12, and is composed of a plurality of MOS transistors electrically connected to the photodiode 228. The signal detection circuit 240A is included. As will be described in detail later with reference to the drawings, the photodiode 228 includes a photoelectric conversion unit arranged in the semiconductor substrate 60. That is, here, the image pickup device of the embedded photodiode 228 is exemplified as the image pickup device 200.

Hereinafter, the same components as those of the first embodiment are designated by the same reference numerals as those of the first embodiment, the description thereof will be omitted, and the points different from those of the first embodiment will be mainly described.

In the configuration exemplified in FIG. 18, the signal detection circuit 240A includes a transfer transistor 227, a signal detection transistor 22, an address transistor 24, and a reset transistor 26. As will be described in detail later with reference to the drawings, the transfer transistor 227, the signal detection transistor 22, the address transistor 24 and the reset transistor 26 typically have a field effect formed on the semiconductor substrate 60 supporting the photodiode 228. It is a transistor. Hereinafter, unless otherwise specified, an example of using an N-channel MOS as a transistor will be described.

The photodiode 228 serves to store the photoelectric conversion and the signal charge generated by the photoelectric conversion, and has a connection with the transfer transistor 227. During operation of the image pickup apparatus 200, a transfer control line 237 is connected to the gate of the transfer transistor 227. The photodiode 228 photoelectrically converts incident light from the outside to generate a signal charge according to the amount of light. The signal charge is transferred to the floating diffusion (FD) unit, which is an example of the charge storage region, through the photodiode 228 and the transfer transistor 227. At this time, the electric charge is transferred to the FD section, so that the potential of the FD section changes. That is, the FD unit functions as a charge-voltage conversion unit. Further, the FD unit includes a source or drain of the reset transistor 26 for discharging the signal charge and a gate electrode of the signal detection transistor 22 that converts the signal charge of the FD unit into a voltage signal.

FIG. 19 is a schematic plan view showing an example of the layout of each element in the pixel 210A of the image pickup apparatus 200 according to the second embodiment of the present disclosure. The image pickup apparatus 200 according to the present embodiment has an embedded photodiode 228. The photodiode 228 is laid out on the same plane as the transfer transistor 227, the signal detection transistor 22, the address transistor 24 and the reset transistor 26 (that is, the main surface of the semiconductor substrate 60).

FIG. 20 is a cross-sectional view schematically showing an example of the device structure of the pixel 210A of the image pickup apparatus 200 according to the second embodiment of the present disclosure. By cutting and unfolding the pixel 210A along the XIX-XIX line in FIG. 19, the cross section shown in FIG. 20 can be obtained.

As shown in this figure, the photodiode 228 is formed in the vicinity of the surface of the semiconductor substrate 60, and at least a part thereof is located on the surface of the semiconductor substrate 60. The photodiode 228 is composed of, for example, a first conductive type first region 228a such as a p-type and a second conductive type second region 228b such as an n-type. The transfer transistor 227 shares a photodiode 228 as one of the source and drain, and shares an n-type impurity region 67n, which is an example of the charge storage region, as the other of the source and drain. The gate electrode 227e of the transfer transistor 227, the contact plug Cp28 connected to the gate electrode 227e, the silicide layer 275 covering the upper surface and the side surface of the contact plug Cp28, the fourth insulating layer 274 located on the side wall of the gate electrode 227e, and the fourth insulating layer. The first insulating layer 71 and the like in contact with the 274 and the silicide layer 275 have the same structure as the reset transistor 26. Therefore, the transfer transistor 227 is electrically connected to the charge storage region, the gate electrode 227e as the first gate electrode, the fourth insulating layer 274 as the first sidewall located on the side wall of the first gate electrode, and the first. It is also an example of a first transistor including a source and a first drain. The silicide layer 275 does not have to be formed.

A passivation layer 290 composed of a silicon nitride layer is formed on the upper surface of the interlayer insulating layer 90, and a microlens 291 is formed on the passivation layer 290 and above the photodiode 228. ing. A flattening layer or a color filter may be formed between the persistence layer 290 and the microlens 291.

In the image pickup apparatus 200 according to the present embodiment as described above, the dark current is reduced by removing the silicide block layer 76, and the transistor provided with the silicide enables high-speed operation, as in the first embodiment. ..

FIG. 21 is a cross-sectional view schematically showing an example of the device structure of the pixel 310A of the image pickup apparatus according to the modified example of the second embodiment of the present disclosure. In each transistor, the third insulating layer 73 is formed as the gate insulating layer only directly under each gate electrode, which is different from the second embodiment shown in FIG. 20. Note that the silicide layer 275 does not have to be formed, as in the second embodiment of FIG. Further, the film configurations of the third insulating layer 73, the second insulating layer 72, and the first insulating layer 71 on the photodiode 228 are the same as those in FIG. 20. In the image pickup apparatus according to the modified example of the second embodiment as well, the dark current is reduced by removing the silicide block layer 76, and the transistor provided with the silicide operates at high speed, as in the first and second embodiments. Will be possible.

Although the image pickup apparatus and the manufacturing method of the image pickup apparatus according to the present disclosure have been described above based on the first and second embodiments and the modified examples, the present disclosure is not limited to these embodiments and the modified examples. do not have. As long as it does not deviate from the gist of the present disclosure, various modifications that can be conceived by those skilled in the art are applied to the embodiments and modifications, and other embodiments constructed by combining some components in the embodiments and modifications are also available. , Included within the scope of this disclosure.

For example, in the second embodiment and its modifications, the peripheral circuit may have the same configuration as that of the first embodiment. As a result, the image pickup device of the embedded photodiode is equipped with a silicide transistor in the peripheral circuit to enable high-speed operation of the peripheral circuit, and by including a non- silicide transistor, ESD countermeasures are taken and the transistor is provided. Destruction of the element is suppressed. Further, by using the non- silicide resistance element in the ADC or DAC in the peripheral circuit, the element performance required in the column signal processing circuit is provided, and the pixel characteristics are improved.

The image pickup apparatus of the present disclosure is useful for, for example, a digital camera as an image pickup apparatus capable of suppressing the influence of a dark current and performing an image pickup with high image quality. More specifically, the image pickup apparatus of the present disclosure can be used for, for example, a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, and the like.

10, 10A, 210A, 310A Pixel 12 Photoelectric conversion unit 12A Photoelectric conversion structure 12a Pixel electrode 12b Photoelectric conversion layer 12c Opposite electrode 14A, 240A Signal detection circuit 16A Feedback circuit 22 Signal detection transistor 24 Address transistor 26 Reset transistor 22e, 24e, 26e , 55e, 56e, 227e Gate electrode 31 Storage control line 32 Power supply wiring 34 Address signal line 35 Vertical signal line 36 Reset signal line 40 Peripheral circuit 42 Vertical scanning circuit 44 Horizontal signal readout circuit 45 Load circuit 46 Control circuit 47 Column signal processing circuit 50 Inversion amplifier 53 Feedback line 55 silicide transistor 56 non- silicide transistor 57 non- silicide resistance element 57e resistance element body 60 semiconductor substrate 61 support substrate 61p, 63p, 65p p-type semiconductor layer 62n n-type semiconductor layer 67n, 68an-68dn n-type impurities Region 69 Element separation region 71 First insulating layer 72 Second insulating layer 73 Third insulating layer 74, 274 Fourth insulating layer (sidewall)
75, 275 silicide layer 76 silicide block layer (protective layer)
80 p-type impurity region (p-well)
81 n-type impurity region 82 n + -type impurity region 89 Conductive structure 90 Interlayer insulation layer 100, 200 Imaging device 227 Transfer transistor 228 Photodiode (PD)
237 Transfer control line 290 Passivation layer 291 Microlens R1 Imaging area R2 Peripheral area FD Charge storage node Cp1, Cp2, Cp3, Cp4, Cp5, Cp6, Cp7, Cp28 Contact plug Ca1, Ca2, Ca3 Second contact plug h1, h2, h3, h4, h5 contact hole d radius of contact hole h1 radius of DCp1

Claims (16)

An image pickup device equipped with a plurality of pixels.
Each of the plurality of pixels
Photoconverter and
A charge storage region that stores the charge generated by the photoelectric conversion unit, and
A first transistor electrically connected to the charge storage region and comprising a first gate electrode, a first source, a first drain and a first sidewall located on the side wall of the first gate electrode.
The first plug connected to the first gate electrode and
The first silicide layer in contact with the first plug and
The first insulating layer in contact with the first sidewall and the first silicide layer,
An image pickup device equipped with. A second transistor including a second gate electrode, a second source and a second drain,
The second gate electrode includes a first semiconductor layer and a second silicide layer located on the first semiconductor layer.
The first insulating layer is in contact with the second silicide layer.
The imaging device according to claim 1. A peripheral circuit that outputs a drive signal for driving the plurality of pixels is provided.
The peripheral circuit includes the second transistor.
The imaging device according to claim 2. The peripheral circuit includes a third transistor including a third gate electrode, a third source and a third drain.
The third gate electrode includes a second semiconductor layer, and the third gate electrode includes a second semiconductor layer.
The first insulating layer is in contact with the second semiconductor layer.
The imaging device according to claim 3. The peripheral circuit includes a resistance element.
The resistance element includes a third semiconductor layer, and the resistance element includes a third semiconductor layer.
The first insulating layer is in contact with the third semiconductor layer.
The imaging device according to claim 3 or 4. The first semiconductor layer and the third semiconductor layer are made of the same material.
The imaging device according to claim 5. The first transistor resets the signal charge stored in the charge storage region.
The imaging device according to any one of claims 1 to 6. The first gate electrode and the first gate electrode are on a semiconductor substrate including a first transistor including a first gate electrode, a first source and a first drain, and a first sidewall located on a side wall of the first gate electrode. 1 The first step of forming a protective layer located above the sidewall,
A second step of forming a first plug that penetrates the protective layer and connects to the first gate electrode.
A third step of forming the first silicide layer on the first plug and the protective layer, and
The fourth step of removing the protective layer and
The fifth step of forming the first insulating layer covering the first sidewall and the first silicide layer, and the fifth step.
A method of manufacturing an image pickup apparatus, which includes the above in this order. The fourth step is performed by wet etching.
The method for manufacturing an image pickup apparatus according to claim 8. The wet etching is APM (Ammonia-hydrogen Peroxide Mixture) etching.
The method for manufacturing an image pickup apparatus according to claim 9. The first insulating layer is a silicon nitride layer.
The method for manufacturing an image pickup apparatus according to any one of claims 8 to 10. The first insulating layer is formed by using an ALD (Atomic Layer Deposition) method.
The method for manufacturing an image pickup apparatus according to any one of claims 8 to 11. The protective layer is a silicon oxide layer.
The method for manufacturing an image pickup apparatus according to any one of claims 8 to 12. The protective layer is formed by a CVD (Chemical Vapor Deposition) method using ozone and TEOS (TetraEthOxySilane) as a source gas.
The method for manufacturing an image pickup apparatus according to claim 13. Between the second step and the third step, a sixth step of heating the semiconductor substrate in a diffusion furnace is included.
The method for manufacturing an image pickup apparatus according to any one of claims 8 to 14. In the sixth step, the semiconductor substrate is heated at a temperature of 800 ° C. or higher.
The method for manufacturing an image pickup apparatus according to claim 15.

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