JP2022092389A - Comparator circuit - Google Patents

Abstract

To provide a comparator circuit with sufficiently reduced power consumption.SOLUTION: A comparator circuit 100 includes a preamplifier circuit 10 that generates a first preamplifier output signal and a second preamplifier output signal on the basis of a first input signal and a second input signal, a latch circuit 20 that compares the first preamplifier output signal and the second preamplifier output signal to generate the first output signal and the second output signal, and a detection circuit 30 that generates a control signal that operates or stops the preamplifier circuit 10 on the basis of the first preamplifier output signal and the second preamplifier output signal.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a comparator circuit.

In recent years, development has been promoted to reduce the power consumption of a comparator circuit in a sequential comparison type A / D converter utilizing energy harvesting. For example, in Patent Document 1, the preamplifier circuit 301 and the latch circuit 312 are configured in two stages, and the current consumption of the preamplifier circuit 301 is reduced during the period when the comparison operation is not performed (about half of the clock cycle). , A dynamic comparator 400 with reduced power consumption is disclosed (see FIG. 11).

Here, the operation of the dynamic comparator 400 will be briefly described. When the CLK is switched from 1 to 0 at the start of the comparison operation, the MP4 is turned on and a current is supplied from the power supply terminal to the preamplifier circuit 301. MP0 and MP1 cause a drain current proportional to the input voltage INP and the input voltage INM to flow from the power supply terminal to the terminal OUTP and the terminal OUTM. As a result, electric charges are accumulated in the terminal OUTP and the terminal OUTM in proportion to the difference between the input voltage INP and the input voltage INM, and the voltage of the terminal OUTP and the voltage of the terminal OUTM rise. When the voltage of the terminal OUTP and the voltage of the terminal OUTM exceed the threshold voltage of MN0 and the threshold voltage of MN1, the voltage of the terminal OUTP and the terminal OUTM become 1 based on the difference between the input voltage INP and the input voltage INM. It is separated into 0 and the comparison operation ends. After the comparison operation is completed, the voltage of the terminal OUTP ≠ the voltage of the terminal OUTM, so the output of the NOR circuit is switched from 1 to 0, CLK_LAT1 is switched from 0 to 1, and MP4 is switched from the on operation to the off operation. , The supply of current from the power supply terminal to the preamplifier circuit 301 is cut off.

As described above, the dynamic comparator 400 reduces the current consumption of the preamplifier circuit 301 during the period when the comparison operation is not performed by stopping the preamplifier circuit 301 after the detection circuit 350 detects the end of the comparison operation. I'm letting you.

US Patent Application Publication No. 2019/0207562

However, in the conventional dynamic comparator, the preamplifier circuit is also operating while the latch circuit is operating, so that the current consumption of the preamplifier circuit during this period cannot be reduced. Therefore, there has been a demand to further reduce the power consumption of the dynamic comparator.

An object of the present disclosure made in view of such circumstances is to provide a comparator circuit in which power consumption is sufficiently reduced.

The comparator circuit according to one embodiment includes a preamp circuit that generates a first preamp output signal and a second preamp output signal based on a first input signal and a second input signal, and the first preamp output signal and the second preamp output signal. Control to operate or stop the preamp circuit based on the latch circuit that compares the preamp output signals and generates the first output signal and the second output signal, and the first preamp output signal and the second preamp output signal. It is characterized by comprising a detection circuit for generating a signal.

Further, in the comparator circuit according to the embodiment, the detection circuit delays the detection signal for detecting the first preamplifier output signal or the second preamplifier output signal, or the latch circuit delays the detection signal for detecting the first preamplifier output signal. Alternatively, the preamplifier circuit is provided with a detection control circuit that detects the first preamplifier output signal or the second preamplifier output signal later than the detection of the second preamplifier output signal, and is based on the output signal of the detection control circuit. It is characterized by stopping.

Further, in the comparator circuit according to the embodiment, the detection circuit further includes a control signal generation circuit, the detection control circuit has a threshold voltage of the first threshold voltage, and the first preamp output signal is the first. A first detection transistor that detects whether or not the threshold voltage has been exceeded, and a second detection transistor that detects whether or not the threshold voltage is the second threshold voltage and the second preamp output signal exceeds the second threshold voltage. Based on the switch that precharges the node to which the drain of the first detection transistor and the drain of the second detection transistor are connected to the first voltage, the first preamp output signal, and the second preamp output signal. It has a delay circuit that delays a detection signal indicating the voltage of the node and generates a delay signal, and the control signal generation circuit generates the control signal based on the clock signal and the delay signal. , It is characterized in that it outputs to the preamplifier circuit.

Further, in the comparator circuit according to the embodiment, the latch circuit includes a first input transistor having a threshold voltage of a first threshold voltage and a second input transistor having a threshold voltage of a second threshold voltage. The detection circuit further includes a control signal generation circuit, and the detection control circuit has a third threshold voltage whose threshold voltage is larger than the first threshold voltage, and whether the first preamp output signal exceeds the third threshold voltage. A first detection transistor for detecting whether or not the transistor is present, and a fourth threshold voltage whose threshold voltage is larger than the second threshold voltage, and a second for detecting whether or not the second preamp output signal exceeds the fourth threshold voltage. The control signal generation circuit includes a detection transistor, a switch for precharging a node to which the drain of the first detection transistor and the drain of the second detection transistor are connected to a first voltage, and the control signal generation circuit is a clock signal. The control signal is generated based on the detection signal indicating the voltage of the node and the detection signal, and is output to the preamplifier circuit.

Further, in the comparator circuit according to the embodiment, the preamplifier circuit includes an input differential including a first transistor in which the first input signal is input to the gate and a second transistor in which the second input signal is input to the gate. A pair, a current control switch in which the control signal is input to the gate, a source is connected to the power supply terminal, a drain is connected to the source of the first transistor and the source of the second transistor, and an inverting clock signal is connected to the gate. A first initialization switch that is input, the source is connected to the ground terminal, the drain is connected to the drain of the first transistor, the inverting clock signal is input to the gate, the source is connected to the ground terminal, and the drain. The latch circuit comprises a second initialization switch connected to the drain of the second transistor, and the latch circuit is gated by a third transistor in which the second preamp output signal is input to the gate and a gate of the first preamp output signal. An input differential pair including a fourth transistor input to, a fifth transistor whose source is connected to the power supply terminal, a drain connected to the drain of the third transistor, and a source connected to the power supply terminal. A sixth transistor in which the drain is connected to the drain of the fourth transistor, a seventh transistor in which the gate is connected to the gate of the fifth transistor and the drain is connected to the source of the third transistor, and the gate is the first. The eighth transistor, which is connected to the gate of the six-transistor and whose drain is connected to the source of the fourth transistor, and the clock signal is input to the gate, the source is connected to the power supply terminal, and the drain is of the fifth transistor. The third initialization switch connected to the drain, the fourth initialization switch in which the clock signal is input to the gate, the source is connected to the power supply terminal, and the drain is connected to the drain of the sixth transistor, and the above. It comprises a fifth initialization switch in which a clock signal is input to the gate, a source is connected to the ground terminal, and a drain is connected to the source of the seventh transistor and the source of the eighth transistor. ..

According to the present disclosure, it is possible to provide a comparator circuit in which power consumption is sufficiently reduced.

It is a schematic diagram which shows an example of the structure of the comparator circuit which concerns on 1st Embodiment. It is a figure which shows an example of the structure of the comparator circuit which concerns on 1st Embodiment. It is a timing chart which shows an example of the operation of the comparator circuit which concerns on 1st Embodiment. It is a figure which shows an example of the structure of the comparator circuit which concerns on the modification 1. It is a figure which shows an example of the structure of the comparator circuit which concerns on 2nd Embodiment. It is a figure which shows an example of the structure of the delay circuit in the comparator circuit which concerns on 2nd Embodiment. It is a figure which shows an example of the structure of the delay circuit in the comparator circuit which concerns on 2nd Embodiment. It is a timing chart which shows an example of the operation of the comparator circuit which concerns on 2nd Embodiment. It is a figure which shows an example of the structure of the comparator circuit which concerns on the modification 2. It is a figure which shows an example of the structure of the comparator circuit which concerns on 3rd Embodiment. It is a figure which shows an example of the structure of the comparator circuit which concerns on 3rd Embodiment. It is a figure which shows an example of the structure of the comparator circuit which concerns on the modification 3. It is a figure which shows an example of the structure of the comparator circuit which concerns on the modification 3. It is a figure which shows an example of the structure of the comparator circuit which concerns on the modification 3. It is a figure which shows an example of the structure of the comparator circuit which concerns on the conventional.

Hereinafter, embodiments will be described in detail with reference to the drawings. In the present specification, the "state in which A and B are connected" means that A and B are directly connected, and that A and B affect the electrical connection state. It also includes the case of being indirectly connected via C which does not reach. Further, in the present specification, "H level" indicates a voltage corresponding to the first logical state (for example, power supply voltage VDD), and "L level" means a second logical state different from the first logical state. It shall indicate the corresponding voltage (eg, ground voltage VSS). Further, the threshold voltage of each transistor is not particularly limited in its value and can be arbitrarily set.

[First Embodiment]
<Comparator circuit>
An example of the configuration of the comparator circuit 100 according to the first embodiment will be described with reference to FIG.

As shown in FIG. 1, the comparator circuit 100 includes a preamplifier circuit 10, a latch circuit 20, and a detection circuit 30.

In the preamplifier circuit 10, the first input signal V _INP is input from the input terminal 11, and the second input signal V _INN (first input signal V _INP > second input signal V _INN ) is input from the input terminal 12. The preamplifier circuit 10 generates a first preamplifier output signal V _OXP and a second preamplifier output signal V _OXN based on the first input signal V _INP and the second input signal V _INN . The preamplifier circuit 10 outputs the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN to the latch circuit 20 and the detection circuit 30. In this specification, the case where the first input signal V _INP is higher than the second input signal V _INN will be described as an example, but the magnitude relationship between the first input signal V _INP and the second input signal V _INN is described. It is not limited to this.

Further, in the preamplifier circuit 10, a control signal _VIAMP is input from the detection circuit 30. For example, the control signal _VIAMP is a control signal for operating the preamplifier circuit 10. For example, the control signal _VIAMP is a control signal for stopping the preamplifier circuit 10. The preamplifier circuit 10 operates or stops based on the control signal _VIAMP .

In the latch circuit 20, the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN are input from the preamplifier circuit 10. The latch circuit 20 generates a first output signal V _OUTP and a second output signal V _OUTN based on the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN . The latch circuit 20 outputs the first output signal V _OUTP to the output terminal 21, and outputs the second output signal V _OUTN to the output terminal 22.

In the detection circuit 30, the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN are input from the preamplifier circuit 10. The detection circuit 30 generates a control signal _VIAMP for operating or stopping the preamplifier circuit 10 based on the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN . The detection circuit 30 outputs the control signal _VIAMP to the preamplifier circuit 10.

For example, when the first preamplifier output signal V _OXP exceeds the first threshold voltage V _th1 , the detection circuit 30 generates a control signal V _IAMP for stopping the preamplifier circuit 10 and outputs it to the preamplifier circuit 10. As a result, the preamplifier circuit 10 is stopped.

For example, when the first preamplifier output signal V _OXP does not exceed the first threshold voltage V _th1 , the detection circuit 30 generates a control signal V _IAMP for operating the preamplifier circuit 10 and outputs it to the preamplifier circuit 10. As a result, the preamplifier circuit 10 operates.

For example, when the second preamplifier output signal _VOXN exceeds the second threshold voltage Vth2, the detection circuit 30 generates a control signal V _IAMP for _stopping the preamplifier circuit 10 and outputs it to the preamplifier circuit 10. As a result, the preamplifier circuit 10 is stopped.

For example, when the second preamplifier output signal _VOXN does not exceed the second threshold voltage Vth2, the detection circuit 30 generates a control signal V _IAMP for _operating the preamplifier circuit 10 and outputs it to the preamplifier circuit 10. As a result, the preamplifier circuit 10 operates.

The comparator circuit 100 according to the first embodiment stops the preamplifier circuit 10 after the latch circuit 20 starts operating. As a result, the preamplifier circuit 10 can be stopped while the latch circuit 20 is operating, so that the current consumption of the preamplifier circuit 10 during this period can be reduced. Therefore, it is possible to realize the comparator circuit 100 in which the power consumption is sufficiently reduced as compared with the conventional comparator circuit.

Next, an example of the circuit configuration of the comparator circuit 100 according to the first embodiment will be described with reference to FIG.

≪Preamplifier circuit≫
The preamplifier circuit 10 includes a first transistor M1, a second transistor M2, a current control switch MSWI, a first initialization switch MSW1, and a second initialization switch MSW2. The configuration of the preamplifier circuit 10 is not particularly limited, and the preamplifier circuit 10 may have a known configuration.

The first transistor M1 and the second transistor M2 form an input differential pair, and are composed of, for example, a photodiode (positive-channel metal oxide semiconductor). The first input signal _VINP is input to the gate of the first transistor M1 from the input terminal 11. The second input signal V _INN , which is lower than the first input signal V _INP , is input to the gate from the input terminal 12 of the second transistor M2.

The gate of the first transistor M1 is connected to the input terminal 11. The source of the first transistor M1 is connected to the drain of the current control switch MSWI. The drain of the first transistor M1 is connected to the drain of the first initialization switch MSW1 and the node 101. The above-mentioned second preamplifier output signal _VOXN is a signal indicating the voltage of the node 101.

The gate of the second transistor M2 is connected to the input terminal 12. The source of the second transistor M2 is connected to the drain of the current control switch MSWI. The drain of the second transistor M2 is connected to the drain of the second initialization switch MSW2 and the node 102. The first preamplifier output signal V _OXP described above is a signal indicating the voltage of the node 102.

The current control switch MSWI is composed of, for example, a polyclonal. In the current control switch MSWI, the control signal _VIAMP is input to the gate from the detection circuit 30. For example, the current control switch MSWI is turned on when the control signal 0 for operating the preamplifier circuit 10 is input to the gate. At this time, a current is supplied from the power supply terminal to the preamplifier circuit 10. For example, the current control switch MSWI operates off when the control signal 1 for stopping the preamplifier circuit 10 is input to the gate. At this time, no current is supplied from the power supply terminal to the preamplifier circuit 10. That is, after the latch circuit 20 starts operating, a control signal for stopping the preamplifier circuit 10 is input from the detection circuit 30 to the preamplifier circuit 10, so that the latch circuit 20 operates in the comparator circuit 100. During that time, the preamplifier circuit 10 can be stopped.

The gate of the current control switch MSWI is connected to the detection circuit 30. The source of the current control switch MSWI is connected to the power supply terminal. In the current control switch MSWI, the drain is connected to the source of the first transistor M1 and the source of the second transistor M2.

The first initialization switch MSW1 and the second initialization switch MSW2 are composed of, for example, an IGMP (negative-channel metal oxide semiconductor). In the first initialization switch MSW1 and the second initialization switch MSW2, an inverting clock signal CKB is input to the gate.

The gate of the first initialization switch MSW1 is connected to the inverting clock signal input terminal. The source of the first initialization switch MSW1 is connected to the ground terminal. The drain of the first initialization switch MSW1 is connected to the node 101. The gate of the second initialization switch MSW2 is connected to the inverting clock signal input terminal. The source of the second initialization switch MSW2 is connected to the ground terminal. The drain of the second initialization switch MSW2 is connected to the node 102.

≪Latch circuit≫
The latch circuit 20 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a third initialization switch MSW3, and a third. It includes a 4 initialization switch MSW4 and a 5th initialization switch MSW5. The structure of the latch circuit 20 is not particularly limited, and the latch circuit 20 may have a known structure.

The third transistor M3 and the fourth transistor M4 form an input differential pair, and are composed of, for example, an IGMP. The second preamplifier output signal _VOXN is input to the gate of the third transistor M3 from the preamplifier circuit 10. The first preamplifier output signal _VOXP is input to the gate of the fourth transistor M4 from the preamplifier circuit 10.

The gate of the third transistor M3 is connected to the preamplifier circuit 10 and the detection circuit 30. For example, when the voltage of the node 101 exceeds the threshold voltage of the second detection transistor MOX2, the detection circuit 30 outputs a control signal _VIAMP for stopping the preamplifier circuit 10 to the preamplifier circuit 10. For example, when the voltage of the node 101 does not exceed the threshold voltage of the second detection transistor MOX2, the detection circuit 30 outputs a control signal _VIAMP for operating the preamplifier circuit 10 to the preamplifier circuit 10.

The source of the third transistor M3 is connected to the drain of the seventh transistor M7. The drain of the third transistor M3 is connected to the drain of the fifth transistor M5, the drain of the third initialization switch MSW3, the gate of the sixth transistor M6, the gate of the eighth transistor M8, and the output terminal 21.

The gate of the fourth transistor M4 is connected to the preamplifier circuit 10 and the detection circuit 30. For example, when the voltage of the node 102 exceeds the threshold voltage of the first detection transistor MOX1, the detection circuit 30 outputs a control signal _VIAMP for stopping the preamplifier circuit 10 to the preamplifier circuit 10. For example, when the voltage of the node 102 does not exceed the threshold voltage of the first detection transistor MOX1, the detection circuit 30 outputs a control signal _VIAMP for operating the preamplifier circuit 10 to the preamplifier circuit 10.

The source of the fourth transistor M4 is connected to the drain of the eighth transistor M8. The drain of the fourth transistor M4 is connected to the drain of the sixth transistor M6, the drain of the fourth initialization switch MSW4, the gate of the fifth transistor M5, the gate of the seventh transistor M7, and the output terminal 22.

The fifth transistor M5 and the sixth transistor M6 are composed of, for example, a FIGURE. The 7th transistor M7 and the 8th transistor M8 are composed of, for example, an IGMP. The fifth transistor M5 and the seventh transistor M7, and the sixth transistor M6 and the eighth transistor M8 are cross-coupled to the output terminal 21 and the output terminal 22.

The gate of the fifth transistor M5 is connected to the output terminal 22, the gate of the seventh transistor M7, the drain of the fourth transistor M4, the drain of the sixth transistor M6, and the drain of the fourth initialization switch MSW4. The source of the fifth transistor M5 is connected to the power supply terminal, the source of the sixth transistor M6, the source of the third initialization switch MSW3, and the source of the fourth initialization switch MSW4. The drain of the fifth transistor M5 is connected to the drain of the third initialization switch MSW3, the drain of the third transistor M3, the gate of the sixth transistor M6, the gate of the eighth transistor M8, and the output terminal 21.

The gate of the sixth transistor M6 is connected to the output terminal 21, the gate of the eighth transistor M8, the drain of the third transistor M3, the drain of the fifth transistor M5, and the drain of the third initialization switch MSW3. The source of the sixth transistor M6 is connected to the power supply terminal, the source of the fifth transistor M5, the source of the third initialization switch MSW3, and the source of the fourth initialization switch MSW4. The drain of the sixth transistor M6 is connected to the drain of the fourth transistor M4, the drain of the fourth initialization switch MSW4, the gate of the fifth transistor M5, the gate of the seventh transistor M7, and the output terminal 22.

The gate of the seventh transistor M7 is connected to the output terminal 22, the gate of the fifth transistor M5, the drain of the fourth transistor M4, the drain of the sixth transistor M6, and the drain of the fourth initialization switch MSW4. The source of the seventh transistor M7 is connected to the drain of the fifth initialization switch MSW5 and the source of the eighth transistor M8. The drain of the seventh transistor M7 is connected to the source of the third transistor M3.

The gate of the eighth transistor M8 is connected to the output terminal 21, the gate of the sixth transistor M6, the drain of the third transistor M3, the drain of the fifth transistor M5, and the drain of the third initialization switch MSW3. The source of the eighth transistor M8 is connected to the drain of the fifth initialization switch MSW5 and the source of the seventh transistor M7. The drain of the eighth transistor M8 is connected to the source of the fourth transistor M4.

The third initialization switch MSW3 and the fourth initialization switch MSW4 are composed of, for example, polyclonal. A clock signal CK is input to the gate of the third initialization switch MSW3 and the fourth initialization switch MSW4.

The gate of the third initialization switch MSW3 is connected to the clock signal input terminal. The source of the third initialization switch MSW3 is connected to the power supply terminal, the source of the fifth transistor M5, the source of the sixth transistor M6, and the source of the fourth initialization switch MSW4. In the third initialization switch MSW3, the drain is connected to the output terminal 21, the drain of the third transistor M3, the drain of the fifth transistor M5, the gate of the sixth transistor M6, and the gate of the eighth transistor M8.

The gate of the fourth initialization switch MSW4 is connected to the clock signal input terminal. In the fourth initialization switch MSW4, the source is connected to the power supply terminal, the source of the fifth transistor M5, the source of the sixth transistor M6, and the source of the third initialization switch MSW3. In the fourth initialization switch MSW4, the drain is connected to the output terminal 22, the drain of the fourth transistor M4, the drain of the sixth transistor M6, the gate of the fifth transistor M5, and the gate of the seventh transistor M7.

The fifth initialization switch MSW5 is composed of, for example, an Now. A clock signal CK is input to the gate of the fifth initialization switch MSW5. The fifth initialization switch MSW5 is inserted to prevent leakage current of the third transistor M3 and the fourth transistor M4.

The gate of the fifth initialization switch MSW5 is connected to the clock signal input terminal. The source of the fifth initialization switch MSW5 is connected to the ground terminal. In the fifth initialization switch MSW5, the drain is connected to the source of the seventh transistor M7 and the source of the eighth transistor M8.

≪Detection circuit≫
The detection circuit 30 includes a first detection transistor MOX1, a second detection transistor MOX2, a switch MSWOX, and a NAND circuit 31.

The first detection transistor MOX1 and the second detection transistor MOX2 are composed of, for example, an IGMP.

The first detection transistor MOX1 detects whether or not the first preamplifier output signal _VOXP exceeds the threshold voltage _VthM4 of the fourth transistor M4, and outputs the detection result as the detection signal _VOXO to the NAND circuit 31. For example, when the relationship of the first preamplifier output signal V _OXP ≥ the threshold voltage V _thM4 of the fourth transistor M4 is satisfied, the first detection transistor MOX1 has a detection signal V _OXO (for example, L level) indicating that the latch circuit 20 has started operation. Signal) is output to the NAND circuit 31. For example, when the relationship of the first preamplifier output signal V _OXP <threshold voltage V _thM4 of the fourth transistor M4 is satisfied, the first detection transistor MOX1 has a detection signal V _OXO that the latch circuit 20 has not started operation (for example, The H level signal) is output to the NAND circuit 31. The first detection transistor MOX1 indirectly detects whether or not the latch circuit 20 has started operation.

The second detection transistor MOX2 detects whether or not the second preamplifier output signal _VOXN exceeds the threshold voltage _VthM3 of the third transistor M3, and outputs the detection result as the detection signal _VOXO to the NAND circuit 31. For example, when the relationship of the second preamplifier output signal V _OXN ≧ the threshold voltage V _thM3 of the third transistor M3 is satisfied, the second detection transistor MOX2 has a detection signal V _OXO (for example, L level) indicating that the latch circuit 20 has started operation. Signal) is output to the NAND circuit 31. For example, when the relationship of the second preamplifier output signal _VOXN <threshold voltage _VthM3 of the third transistor M3 is satisfied, the second detection transistor MOX2 indicates that the latch circuit 20 has not started the operation of the detection signal _VOXO ( For example, an H level signal) is output to the NAND circuit 31. The second detection transistor MOX2 indirectly detects whether or not the latch circuit 20 has started operation.

The above-mentioned detection signal V _OXO is a signal indicating the voltage of the node 103 to which the drain of the first detection transistor MOX1 and the drain of the second detection transistor MOX2 are connected.

The gate of the first detection transistor MOX1 is connected to the preamplifier circuit 10 and the latch circuit 20. The source of the first detection transistor MOX1 is connected to the ground terminal. The drain of the first detection transistor MOX1 is connected to the drain of the switch MSWOX and the node 103.

The gate of the second detection transistor MOX2 is connected to the preamplifier circuit 10 and the latch circuit 20. The source of the second detection transistor MOX2 is connected to the ground terminal. The drain of the second detection transistor MOX2 is connected to the drain of the switch MSWOX and the node 103.

The switch MSWOX is composed of, for example, a polyclonal. A clock signal CK is input to the gate of the switch MSWOX. The switch MSWOX precharges the voltage of the node 103 to which the drain of the first detection transistor MOX1 and the drain of the second detection transistor MOX2 are connected to the power supply voltage (for example, the first voltage). When the switch MSWOX is turned on, the power supply terminal and the node 103 are in a conductive state, and when the switch MSWOX is turned off, the power supply terminal and the node 103 are in a non-conducting state.

In the switch MSWOX, the gate is connected to the clock signal input terminal. The source of the switch MSWOX is connected to the power supply terminal. In the switch MSWOX, the drain is connected to the drain of the first detection transistor MOX1, the drain of the second detection transistor MOX2, and the node 103.

In the NAND circuit 31, the clock signal CK is input from the clock signal input terminal, and the detection signal _VOXO is input from the node 103. The NAND circuit 31 calculates the negative logical product of the clock signal CK and the detection signal _VOXO . The NAND circuit 31 outputs the calculation result as a control signal _VIAMP to the preamplifier circuit 10.

The comparator circuit 100 according to the first embodiment does not stop the preamplifier circuit after detecting the end of the comparison operation as in the conventional comparator circuit, but after the latch circuit 20 starts the operation, the preamplifier circuit 10 To stop. As a result, the preamplifier circuit 10 can be stopped while the latch circuit 20 is operating, so that the current consumption of the preamplifier circuit 10 during this period can be reduced. Therefore, it is possible to realize the comparator circuit 100 in which the power consumption is sufficiently reduced as compared with the conventional comparator circuit.

<Operation of comparator circuit>
An example of the operation of the comparator circuit 100 according to the first embodiment will be described with reference to FIG. 3 by using a timing chart. In FIG. 3, the clock signal CK, the first input signal V _INP , the detection signal V _OXO , the control signal V _IAMP , the first preamplifier output signal V _OXP , and the first output signal V _OUTP are shown by solid lines, and the second input signal V _INN is shown. , The second preamplifier output signal V _OXN and the second output signal V _OUTN are shown by broken lines.

In the period before time t ₀ , the clock signal CK is at the L level before the comparator circuit 100 starts the comparison operation. The current control switch MSWI is turned off, the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN are set to L level, and the first output signal V _OUTP and the second output signal V _OUTN are set to H level. It is set. The switch MSWOX is turned on and the voltage of the node 103 is precharged to the H level. When the current control switch MSWI is turned off, the supply of current from the power supply terminal to the preamplifier circuit 10 is cut off, and the preamplifier circuit 10 is stopped.

When the comparator circuit 100 starts the comparison operation at time _t0 , the clock signal CK is switched from the L level to the H level, and at the same time, the control signal _VIAMP is switched from the H level to the L level, and the current control switch MSWI is turned off. Switch to on operation. The supply of current from the power supply terminal to the preamplifier circuit 10 is started, and the preamplifier circuit 10 operates.

From time t ₀ to time t ₁ , the preamplifier circuit 10 sends a current to the parasitic capacitance of the node 101 and the parasitic capacitance of the node 102 based on the first input signal V _INP and the second input signal V _INN . Then, the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN are increased.

At time t ₁ , when the first preamplifier output signal V _OXP exceeds the first threshold voltage V _th1 or the second preamplifier output signal V _OXN exceeds the second threshold voltage V _th 2, the latch circuit 20 starts operation. do. As a result, the detection signal V _OXO switches from the H level to the L level, the control signal _VIAMP switches from the L level to the H level, and the current control switch MSWI switches from the on operation to the off operation. The supply of current from the power supply terminal to the preamplifier circuit 10 is cut off, and the preamplifier circuit 10 is stopped. In this way, the comparator circuit 100 stops the preamplifier circuit 10 after the latch circuit 20 starts operating.

From time t ₁ to time t ₂ , the third transistor M3 and the fourth transistor M4 draw out the charges charged in the parasitic capacitance of the output terminal 21 and the parasitic capacitance of the output terminal 22, and the first output signal V _OUTP . , The second output signal V _OUTN drops to near the middle between the H level and the L level.

At time t2, the first preamplifier output signal V _OXP and the _second preamplifier output signal V _OXN stop rising while maintaining the potential difference proportional to the first input signal V _INP and the second input signal V _INN , but latch. The circuit 20 continues to operate. The first output signal V _OUTP and the second output signal V _OUTN are in an equilibrium state near the middle between the H level and the L level.

From time t ₂ to time t ₃ , the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN continue to hold the potential difference at time t ₂ , and the first input signal V _INP > second input signal. Since it is a V _INN , the first output signal V _OUTP rises toward the H level from the equilibrium state near the middle between the H level and the L level, and the second output signal V _OUTN is the H level and the L level. From the equilibrium state near the middle of, it descends toward the L level and continues to spread with positive feedback.

At time t3 _, the first output signal V _OUTP converges at the H level and the second output signal V _OUTN converges at the L level. Then, as a comparison result of the first input signal V _INP and the second input signal V _INN , the first output signal V _OUTP (H level) is output from the output terminal 21, and the second output signal V _OUTN (L level) is output. It is output from the terminal 22.

As described above, in the comparator circuit 100 according to the first embodiment, unlike the conventional comparator circuit, the preamplifier circuit may be stopped after the output signal output from the latch circuit is completely separated and stabilized. The preamplifier circuit after detecting that at least one of the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN exceeds the threshold voltage of MOX1 and MOX2 and the latch circuit 20 has started operation. Stop 10 This makes it possible to realize the comparator circuit 100 in which the power consumption is sufficiently reduced.

[Modification 1]
An example of the configuration of the comparator circuit 100'according to the first modification will be described with reference to FIG.

The difference between the comparator circuit 100'according to the first embodiment and the comparator circuit 100 according to the first embodiment is that the third transistor M3 and the fourth transistor M4 in the comparator circuit 100 according to the first embodiment are composed of ordinary comparators. On the other hand, the third transistor M3'and the fourth transistor M4' in the comparator circuit 100'according to the first modification are low vth negative-channel metal oxide semiconductors (NMOS) in which the amount of impurities injected is adjusted. It is a point composed of. Since the other configurations are the same as those of the comparator circuit 100 according to the first embodiment, duplicated description will be omitted.

In the comparator circuit 100'according to the first modification, the detection control circuit 300 includes a first detection transistor MOX1, a second detection transistor MOX2, and a switch MSWOX. The detection control circuit 300 detects the first preamplifier output signal V _OXP or the second preamplifier output signal V _OXN later than the latch circuit 20 detects the first preamplifier output signal V _OXP or the second preamplifier output signal V _OXN . do.

The third transistor (second input transistor) M3'and the fourth transistor (first input transistor) M4' form an input differential pair and are composed of a low threshold MIMO. The second preamplifier output signal _VOXN is input to the gate of the third transistor M3'from the preamplifier circuit 10. The first preamplifier output signal _VOXP is input to the gate of the fourth transistor M4'from the preamplifier circuit 10.

The third transistor M3'is configured so that its threshold voltage (second threshold voltage V _th2 ) is lower than the threshold voltage (fourth threshold voltage) of the second detection transistor MOX2 included in the detection circuit 30. By configuring the threshold voltage of the third transistor M3'to be lower than the threshold voltage of the second detection transistor MOX2, the third transistor M3'is turned on in response to an increase in the second preamplifier output signal _VOXN . It is possible to guarantee the order in which the second detection transistor MOX2 is turned on after the operation. As a result, it is possible to reliably guarantee the context of the temporal order in which the detection circuit 30 is operated and the preamplifier circuit 10 is stopped after the latch circuit 20 has started operation. Therefore, in the comparator circuit 100', it is possible to prevent the detection circuit 30 from erroneously stopping the preamplifier circuit 10 before the latch circuit 20 actually starts operating.

The gate of the third transistor M3'is connected to the gate of the second detection transistor MOX2. The source of the third transistor M3'is connected to the drain of the seventh transistor M7. The drain of the third transistor M3'is connected to the drain of the fifth transistor M5, the drain of the third initialization switch MSW3, the gate of the sixth transistor M6, the gate of the eighth transistor M8, and the output terminal 21.

The fourth transistor M4'is configured so that its threshold voltage (first threshold voltage V _th1 ) is lower than the threshold voltage (third threshold voltage) of the first detection transistor MOX1 included in the detection circuit 30. By configuring the threshold voltage of the 4th transistor M4'to be lower than the threshold voltage of the 1st detection transistor MOX1, the 4th transistor M4'is turned on in response to an increase in the 1st preamplifier output signal V _OXP . After that, it is possible to guarantee the order in which the first detection transistor MOX1 is turned on. As a result, it is possible to reliably guarantee the context of the temporal order in which the detection circuit 30 is operated and the preamplifier circuit 10 is stopped after the latch circuit 20 has started operation. Therefore, in the comparator circuit 100', it is possible to prevent the detection circuit 30 from erroneously stopping the preamplifier circuit 10 before the latch circuit 20 actually starts operating.

The gate of the fourth transistor M4'is connected to the gate of the first detection transistor MOX1. The source of the fourth transistor M4'is connected to the drain of the eighth transistor M8. The drain of the fourth transistor M4'is connected to the drain of the sixth transistor M6, the drain of the fourth initialization switch MSW4, the gate of the fifth transistor M5, the gate of the seventh transistor M7, and the output terminal 22.

Next, an example of the operation of the comparator circuit 100'according to the first modification will be briefly described.

Before the comparator circuit 100'starts the comparison operation, the clock signal CK is at the L level. The current control switch MSWI is turned off, the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN are set to L level, and the first output signal V _OUTP and the second output signal V _OUTN are set to H level. It is set. The switch MSWOX is turned on and the voltage of the node 103 is precharged to the H level. When the current control switch MSWI is turned off, the supply of current from the power supply terminal to the preamplifier circuit 10 is cut off, and the preamplifier circuit 10 is stopped.

After that, when the comparator circuit 100'starts the comparison operation, the clock signal CK switches from the L level to the H level, and at the same time, the control signal _VIAMP switches from the H level to the L level, and the current control switch MSWI operates from the off operation to the on operation. Switch to. The supply of current from the power supply terminal to the preamplifier circuit 10 is started, and the preamplifier circuit 10 operates.

After that, from time t ₀ to time t ₁ , the preamplifier circuit 10 applies a current to the parasitic capacitance of the node 101 and the parasitic capacitance of the node 102 based on the first input signal V _INP and the second input signal V _INN . The first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN are raised by pouring.

After that, when the first preamplifier output signal V _OXP exceeds the first threshold voltage V _th1 or the second preamplifier output signal V _OXN exceeds the second threshold voltage V _th 2, the latch circuit 20 starts operation. At this time, the threshold voltage of the third transistor M3'is lower than the threshold voltage of the second detection transistor MOX2, and the threshold voltage of the fourth transistor M4'is lower than the threshold voltage of the first detection transistor MOX1. Since it is configured to be low, first, the third transistor M3'and the fourth transistor M4'are turned on, and then the first detection transistor MOX1 and the second detection transistor MOX2 are turned on. As a result, the detection signal V _OXO switches from the H level to the L level, the control signal _VIAMP switches from the L level to the H level, and the current control switch MSWI switches from the on operation to the off operation. The supply of current from the power supply terminal to the preamplifier circuit 10 is cut off, and the preamplifier circuit 10 is stopped. In this way, the comparator circuit 100'stops the preamplifier circuit 10 after the latch circuit 20 surely starts operating.

After that, the third transistor M3'and the fourth transistor M4' draw out the charges charged to the parasitic capacitance of the output terminal 21 and the parasitic capacitance of the output terminal 22, and the first output signal V _OUTP and the second output signal V _OUTN are obtained. , It descends to near the middle between the H level and the L level.

After that, the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN stop rising while maintaining a small potential difference proportional to the first input signal V _INP and the second input signal V _INN , but the latch circuit. 20 continues the operation. The first output signal V _OUTP and the second output signal V _OUTN are in an equilibrium state near the middle between the H level and the L level.

After that, the first preamplifier output signal V _OXP and the _second preamplifier output signal V _OXN continue to hold the potential difference at time t2, and the first input signal V _INP > the second input signal V _INN , so that they are the first output signals. The V _OUTP rises from the equilibrium state near the middle between the H level and the L level toward the H level, and the second output signal V _OUTN is from the equilibrium state near the middle between the H level and the L level. It descends toward the L level and continues to spread with positive feedback.

After that, the first output signal V _OUTP converges at the H level, and the second output signal V _OUTN converges at the L level. Then, as a comparison result of the first input signal V _INP and the second input signal V _INN , the first output signal V _OUTP (H level) is output from the output terminal 21, and the second output signal V _OUTN (L level) is output. It is output from the terminal 22.

In addition, in order to ensure the context of the temporal order in which the detection circuit 30 is operated and the preamplifier circuit 10 is stopped after the latch circuit 20 has started operation, at least the "fourth transistor M4" is used. It suffices to satisfy the relationship of "the threshold voltage of the first detection transistor MOX1" and "the threshold voltage of the third transistor M3" <the threshold voltage of the second detection transistor MOX2 ". Therefore, for example, the first detection transistor MOX1'and the second detection transistor MOX2' are composed of high-threshold IGMP (high vth negative-channel metal oxide semiconductors), and the third transistor M3 and the fourth transistor M4 are composed of ordinary MIMO. You may. Alternatively, for example, the first detection transistor MOX1'and the second detection transistor MOX2' may be configured with a high threshold modulus, and the third transistor M3'and the fourth transistor M4' may be configured with a low threshold modulus.

If the detection circuit 30 is operated to stop the preamplifier circuit 10 before the latch circuit 20 starts operating, the first preamplifier output signal V _OXP does not exceed the first threshold voltage V _th1 or , The rise of the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN stops in a state where the second preamplifier output signal V _OXN does not exceed the second threshold voltage V _th2 . As a result, the latch circuit 20 cannot operate normally, and as a comparison result of the first input signal V _INP and the second input signal V _INN , the H level (first output signal V _OUTP ) is output from the output terminal 21. It outputs, H level (second output signal V _OUTN ) is output from the output terminal 22, and it stops. Therefore, in the comparator circuit 100', in order to suppress such a malfunction, the threshold voltage of the fourth transistor M4'is lower than the threshold voltage of the first detection transistor MOX1, and the threshold voltage of the third transistor M3'is the second. It is preferable to satisfy the relationship that the voltage is lower than the threshold voltage of the detection transistor MOX2.

The comparator circuit 100'according to the first modification stops the preamplifier circuit 10 after the latch circuit 20 surely starts operating. As a result, the preamplifier circuit 10 can be reliably stopped while the latch circuit 20 is operating, so that the current consumption of the preamplifier circuit 10 during this period can be reduced. Therefore, it is possible to realize the comparator circuit 100'with sufficiently reduced power consumption as compared with the conventional comparator circuit.

[Second Embodiment]
An example of the configuration of the comparator circuit 100A according to the second embodiment will be described with reference to FIG.

The difference between the comparator circuit 100A according to the second embodiment and the comparator circuit 100 according to the first embodiment is that the detection circuit 30 in the comparator circuit 100 according to the first embodiment does not include a delay circuit. The detection circuit 30A in the comparator circuit 100A according to the second embodiment is a point including a delay circuit. Since the other configurations are the same as those of the comparator circuit 100 according to the first embodiment, duplicated description will be omitted.

In the comparator circuit 100A according to the second embodiment, the detection control circuit 300A includes a first detection transistor MOX1, a second detection transistor MOX2, a switch MSWOX, and a delay circuit 32. The detection control circuit 300A delays the detection signal V _OXO that has detected the first preamplifier output signal V _OXP or the second preamplifier output signal V _OXN .

The detection circuit 30A includes a first detection transistor MOX1, a second detection transistor MOX2, a switch MSWOX, a NAND circuit (control signal generation circuit) 31, and a delay circuit 32.

The delay circuit 32 is provided between the NAND circuit 31 and the node 103 to which the drain of the first detection transistor MOX1 and the drain of the second detection transistor MOX2 are connected. In the delay circuit 32, the detection signal _VOXO is input from the node 103. The delay circuit 32 delays the detection signal V _OXO based on the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN , and generates a delay signal V _OXD . The delay circuit 32 outputs the delay signal V _OXD to the NAND circuit 31.

For example, the delay circuit 32 delays the detection signal _VOXO until the rise of the first preamplifier output signal _VOXP and the second preamplifier output signal _VOXN substantially stops (see the arrow in FIG. 7). As a result, the detection circuit 30A erroneously preamps the circuit before the _first preamplifier output signal V _OXP exceeds the first threshold voltage V _th1 or before the second preamplifier output signal V _OXN exceeds the second threshold voltage V th 2. It is possible to suppress the malfunction of stopping the 10. That is, it is possible to reliably guarantee the context of the temporal order in which the detection circuit 30A is operated and the preamplifier circuit 10 is stopped after the latch circuit 20 has started operation.

In the NAND circuit 31, the clock signal CK is input from the clock signal input terminal, and the delay signal _VOXD is input from the delay circuit 32. The NAND circuit 31 calculates the negative logical product of the clock signal CK and the delay signal _VOXD . The NAND circuit 31 outputs the calculation result as a control signal _VIAMP to the preamplifier circuit 10.

As shown in FIG. 6A, for example, the delay circuit 32 may be composed of N inverters (N is an even number) INV1, INV2, ..., INVN. In the delay circuit 32, the delay amount such as the rise time or the fall time in the delay signal V _OXD is adjusted by adjusting the MOS size of each of the N inverters INV1, INV2, ..., INVN. .. Since the delay circuit 32 has this configuration, the transition of the delay signal _VOXD can be easily made steep, so that the penetration current of the NAND circuit 31 can be suppressed.

As shown in FIG. 6B, for example, the delay circuit 32 may be composed of a resistor R _DLY and a capacitor C _DLY . In the delay circuit 32, the delay amount such as the rise time or the fall time in the delay signal _VOXD is adjusted by adjusting the RC time constant. When the delay circuit 32 has the configuration, the configuration of the delay circuit 32 itself can be simplified and the power consumption can be reduced.

Next, with reference to FIG. 7, an example of the operation of the comparator circuit 100A according to the second embodiment will be described with reference to a timing chart. In FIG. 7, the clock signal CK, the first input signal V _INP , the delay signal V _OXD , the control signal V _IAMP , the first preamplifier output signal V _OXP , and the first output signal V _OUTP are shown by solid lines, and the second input signal V _INN is shown. , The second preamplifier output signal V _OXN and the second output signal V _OUTN are shown by broken lines. The same operation as that of the comparator circuit 100 according to the first embodiment will be omitted.

In the period before time t ₀ , the clock signal CK is at the L level before the comparator circuit 100A starts the comparison operation. The current control switch MSWI is turned off, the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN are set to L level, and the first output signal V _OUTP and the second output signal V _OUTN are set to H level. It is set. The switch MSWOX is turned on and the voltage of the node 103 is precharged to the H level. When the current control switch MSWI is turned off, the supply of current from the power supply terminal to the preamplifier circuit 10 is cut off, and the preamplifier circuit 10 is stopped.

When the comparator circuit 100A starts the comparison operation at time _t0 , the clock signal CK is switched from the L level to the H level, and at the same time, the control signal _VIAMP is switched from the H level to the L level, and the current control switch MSWI is turned off. Switch to on operation. The supply of current from the power supply terminal to the preamplifier circuit 10 is started, and the preamplifier circuit 10 operates.

From time t ₀ to time t ₁ , the preamplifier circuit 10 sends a current to the parasitic capacitance of the node 101 and the parasitic capacitance of the node 102 based on the first input signal V _INP and the second input signal V _INN . Then, the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN are increased.

At time t ₁ , when the first preamplifier output signal V _OXP exceeds the first threshold voltage V _th1 or the second preamplifier output signal V _OXN exceeds the second threshold voltage V _th 2, the latch circuit 20 starts operation. do. At that time, the delay circuit 32 detects the detection signal until the rise of the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN is substantially stopped so that the control signal V _IAMP does not switch from the L level to the H level. Delay _VOXO (see arrow in FIG. 7). As a result, the current supply from the power supply terminal to the preamplifier circuit 10 continues, and the preamplifier circuit 10 continues to operate.

Further, since the latch circuit 20 operates, the third transistor M3 and the fourth transistor M4 draw out the charges charged in the parasitic capacitance of the output terminal 21 and the parasitic capacitance of the output terminal 22, and the first output signal V _OUTP and the first output signal V OUTP. 2 The output signal V _OUTN descends to near the middle between the H level and the L level.

_At time t2, the delay signal _VOXD switches from H level to L level. Further, the first output signal V _OUTP and the second output signal V _OUTN descend to the vicinity of the middle between the H level and the L level, and then reach an equilibrium state near the middle between the H level and the L level.

Since the first input signal V _INP > the second input signal V _INN between the time t ₂ and the time t ₃ , the first output signal V _OUTP is in a balanced state near the middle between the H level and the L level. Then, the second output signal V _OUTN rises toward the H level, falls from the equilibrium state near the middle between the H level and the L level, falls toward the L level, and continues to spread by positive feedback.

At time t3 _, the control signal _VIAMP switches from L level to H level, and the current control switch MSWI switches from on operation to off operation. The supply of current from the power supply terminal to the preamplifier circuit 10 is cut off, and the preamplifier circuit 10 is stopped. The first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN stop rising. The first output signal V _OUTP converges at the H level, and the second output signal V _OUTN converges at the L level. Then, as a comparison result of the first input signal V _INP and the second input signal V _INN , the first output signal V _OUTP (H level) is output from the output terminal 21, and the second output signal V _OUTN (L level) is output. It is output from the terminal 22. In this way, the delay circuit 32 delays the detection signal _VOXO for an appropriate period _, and the control signal at time t3 when the rise of the first preamplifier output signal _VOXP and the second preamplifier output signal _VOXN completely stops. By switching the _VIAMP from the L level to the H level, the context of the temporal order of operating the detection circuit 30A and stopping the preamplifier circuit 10 after the latch circuit 20 starts operating is surely guaranteed. be able to.

In the comparator circuit 100A according to the second embodiment, as compared with the comparator circuit 100 according to the first embodiment, the preamplifier output signal rises after the preamplifier output signal exceeds the threshold voltage at the time when the preamplifier circuit 10 is stopped. Is delayed until it stops. However, the comparator circuit 100A according to the second embodiment significantly improves the preamplifier circuit 10 as compared with the conventional comparator circuit that stops the preamplifier circuit after the output signal output from the latch circuit is completely separated and stabilized. Can be stopped quickly.

The comparator circuit 100A according to the second embodiment stops the preamplifier circuit 10 after the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN surely exceed the threshold voltage. As a result, the power consumption is sufficiently reduced while ensuring the context of the temporal order in which the detection circuit 30A is operated and the preamplifier circuit 10 is stopped after the latch circuit 20 starts operation. The comparator circuit 100A can be realized.

[Modification 2]
Next, an example of the configuration of the comparator circuit 100A'according to the modification 2 will be described with reference to FIG.

The comparator circuit 100A'according to the second embodiment is different from the comparator circuit 100A according to the second embodiment, whereas the comparator circuit 100A according to the second embodiment has a photoresist input configuration, whereas the comparator circuit 100A according to the second embodiment is related to the second embodiment. The comparator circuit 100A'is a point having an IGMP input configuration. Since the other configurations are the same as those of the comparator circuit 100A according to the second embodiment, duplicated description will be omitted.

The preamplifier circuit 10A'includes a first transistor M1, a second transistor M2, current control switches MSWI1 and MSWI2, a first initialization switch MSW1, and a second initialization switch MSW2. The first initialization switch MSW1 and the second initialization switch MSW2 are composed of, for example, polyclonal. The first transistor M1, the second transistor M2, and the current control switch MSWI are composed of, for example, an IGMP.

The latch circuit 20A'contains the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the sixth initialization switch MSW6. A seventh initialization switch MSW7 is provided. The third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are composed of, for example, CICS. The seventh transistor M7, the eighth transistor M8, the sixth initialization switch MSW6, and the seventh initialization switch MSW7 are composed of, for example, an IGMP.

The detection circuit 30A'includes a first detection transistor MOX1, a second detection transistor MOX2, a switch MSWOX, a delay circuit 32, and a NOR circuit 33. The first detection transistor MOX1 and the second detection transistor MOX2 are composed of, for example, polyclonal. The switch MSWOX is composed of, for example, an MFP.

In the NOR circuit 33, the inverting clock signal CKB is input from the inverting clock signal input terminal, and the delay signal _VOXD is input from the delay circuit 32. The NOR circuit 33 calculates the NOR of the clock signal CK and the delay signal V _OXD . The NOR circuit 33 outputs the calculation result as a control signal _VIAMP to the preamplifier circuit 10A'.

Next, an example of the operation of the comparator circuit 100A'according to the second modification will be briefly described. The same operation as that of the comparator circuit 100A according to the second embodiment will be omitted.

Before the comparator circuit 100A'starts the comparison operation, the clock signal CK is at the L level. The first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN are set to H level.

After that, when the comparator circuit 100A'starts the comparison operation, the clock signal CK is switched from the L level to the H level, and at the same time, the control signal _VIAMP is switched from the L level to the H level, and the current control switch MSWI is operated from the off operation to the on operation. Switch to. The supply of current from the power supply terminal to the preamplifier circuit 10A'is started, and the preamplifier circuit 10A'operates.

After that, when the preamplifier circuit 10A'continues to operate, the charges charged in the parasitic capacitance of the node 101 and the parasitic capacitance of the node 102 escape to the ground terminal.

After that, the difference between the power supply voltage VDD and the second threshold voltage V _th2 becomes larger than the first preamplifier output signal V _OXP , or the difference between the power supply voltage VDD and the first threshold voltage V _th1 becomes the second preamplifier output signal V _OXN. When it becomes larger, the third transistor M3 and the fourth transistor M4 are turned on, and the latch circuit 20A'starts the operation.

After that, the first detection transistor MOX1 and the second detection transistor MOX2 are also turned on, the detection signal V _OXO switches from L level to H level, the control signal V _IAMP switches from H level to L level, and the current control switch MSWI. Switches from on operation to off operation. The current supply from the power supply terminal to the preamplifier circuit 10A'is cut off, and the preamplifier circuit 10A' is stopped. In this way, the comparator circuit 100A'stops the preamplifier circuit 10A'after the latch circuit 20A' surely starts operating.

The comparator circuit 100A'according to the second modification stops the preamplifier circuit 10A'after the first preamplifier output signal V _OXP and the second preamplifier output signal V _OXN surely exceed the threshold voltage. As a result, after the latch circuit 20A'starts operation, the detection circuit 30A'is operated and the preamplifier circuit 10A' is stopped, which ensures sufficient power consumption while ensuring the context of the temporal order. The reduced comparator circuit 100A'can be realized.

[Third Embodiment]
An example of the configuration of the comparator circuit 100B and the comparator circuit 100C according to the third embodiment will be described with reference to FIGS. 9A and 9B.

The comparator circuit 100B according to the third embodiment is different from the comparator circuit 100 according to the first embodiment in that the comparator circuit 100 according to the first embodiment is used as a back gate of the first detection transistor MOX1 and the second detection transistor MOX2. While no voltage is applied, the comparator circuit 100B according to the third embodiment is a point where a voltage (negative voltage) is applied to the back gates of the first detection transistor MOX1 and the second detection transistor MOX2. Since the other configurations are the same as those of the comparator circuit 100 according to the first embodiment, duplicated description will be omitted.

Further, the comparator circuit 100C according to the third embodiment is different from the comparator circuit 100 according to the first embodiment in that the comparator circuit 100 according to the first embodiment is used as a back gate of the third transistor M3 and the fourth transistor M4. Whereas no voltage is applied, the comparator circuit 100C according to the third embodiment is a point where a voltage (positive voltage) is applied to the back gates of the third transistor M3 and the fourth transistor M4. Since the other configurations are the same as those of the comparator circuit 100 according to the first embodiment, duplicated description will be omitted.

As shown in FIG. 9A, the comparator circuit 100B has a configuration in which the back gate voltage V _bs is applied to the back gate of the first detection transistor MOX1 and the back gate voltage V _bs is applied to the back gate of the second detection transistor MOX2. Have. By applying a negative voltage to the back gate of the first detection transistor MOX1 and the back gate of the second detection transistor MOX2, for example, the threshold voltage _Vth and the second detection of the first detection transistor MOX1 are as shown in the following equation. The threshold voltage _Vth of the transistor MOX2 can be increased.

The back gate voltage V _bs is applied to the back gate of the first detection transistor MOX1, and the back gate voltage V _bs is applied to the back gate of the second detection transistor MOX2. It is possible to easily configure the comparator circuit 100B that satisfies the relationship of "threshold voltage of detection transistor MOX1" and "threshold voltage of third transistor M3 <threshold voltage of second detection transistor MOX2". That is, the first detection transistor MOX1 can be turned on after the fourth transistor M4 is turned on in response to the rise in the first preamplifier output signal V _OXP , and the second preamplifier output signal V _OXN can be turned on. On the other hand, the comparator circuit 100B capable of turning on the second detection transistor MOX2 after turning on the third transistor M3 can be easily configured.

The comparator circuit 100B according to the third embodiment ensures the context of the temporal order in which the detection circuit 30A is operated and the preamplifier circuit 10 is stopped after the latch circuit 20 starts operation. Power consumption can be sufficiently reduced.

As shown in FIG. 9B, the comparator circuit 100C has a configuration in which a back gate voltage V _bs is applied to the back gate of the third transistor M3 and a back gate voltage V _bs is applied to the back gate of the fourth transistor M4. By applying a positive voltage to the back gate of the third transistor M3 and the back gate of the fourth transistor M4, for example, the threshold voltage _Vth of the third transistor M3 and the threshold of the fourth transistor M4 are as shown in the following equation. The voltage _Vth can be lowered.

The back gate voltage V _bs is applied to the back gate of the third transistor M3, and the back gate voltage V _bs is applied to the back gate of the fourth transistor M4. The comparator circuit 100C satisfying the relationship of "threshold voltage of MOX1" and "threshold voltage of third transistor M3 <threshold voltage of second detection transistor MOX2" can be easily configured. That is, the first detection transistor MOX1 can be turned on after the fourth transistor M4 is turned on in response to the rise in the first preamplifier output signal V _OXP , and the second preamplifier output signal V _OXN can be turned on. On the other hand, the comparator circuit 100C capable of turning on the second detection transistor MOX2 after turning on the third transistor M3 can be easily configured.

The comparator circuit 100C according to the third embodiment ensures the context of the temporal order in which the detection circuit 30A is operated and the preamplifier circuit 10 is stopped after the latch circuit 20 starts operation. Power consumption can be sufficiently reduced.

As for the configuration of the comparator circuit, the back gate voltage V _bs is applied to the back gate of the first detection transistor MOX1 and the back gate voltage V _bs is applied to the back gate of the second detection transistor MOX2 as in the comparator circuit 100B. The configuration is not limited to the configuration in which the backgate voltage V _bs is applied to the back gate of the third transistor M3 and the back gate voltage V _bs is applied to the back gate of the fourth transistor M4, as in the comparator circuit 100C. .. For example, a backgate voltage (negative voltage) is applied to the back gate of the first detection transistor MOX1, a back gate voltage (negative voltage) is applied to the back gate of the second detection transistor MOX2, and the back of the third transistor M3. A back gate voltage (positive voltage) may be applied to the gate, and a back gate voltage (positive voltage) may be applied to the back gate of the fourth transistor M4. At least, the threshold voltage of the third transistor M3 and the fourth transistor M4 provided on the latch circuit side becomes low, and the threshold voltage of the first detection transistor MOX1 and the second detection transistor MOX2 provided on the detection circuit side becomes high. Just do it.

[Modification 3]
An example of the configuration of the comparator circuits 200A, 200B, and 200C according to the third modification will be described with reference to FIGS. 10A, 10B, and 10C.

The comparator circuits 200A, 200B, and 200C according to the third modification differ from the comparator circuit 100 according to the first embodiment in the insertion position of the current control switch MSWI and the number of current control switches MSWI. Since the other configurations are the same as those of the comparator circuit 100 according to the first embodiment, duplicated description will be omitted.

As shown in FIG. 10A, the comparator circuit 200A has a configuration in which two current control switches MSWI1 and current control switch MSWI2 are inserted between the power supply terminal and the first transistor M1 and the second transistor M2.

The preamplifier circuit 10A includes a first transistor M1, a second transistor M2, a current control switch MSWI1, a current control switch MSWI2, a first initialization switch MSW1, and a second initialization switch MSW2.

In the current control switch MSWI1, the control signal _VIAMP is input to the gate from the detection circuit 30. For example, the current control switch MSWI1 is turned on when a control signal for operating the preamplifier circuit 10 is input to the gate. For example, the current control switch MSWI1 operates off when a control signal for stopping the preamplifier circuit 10 is input to the gate.

The gate of the current control switch MSWI1 is connected to the detection circuit 30. The source of the current control switch MSWI1 is connected to the power supply terminal. In the current control switch MSWI1, the drain is connected to the source of the first transistor M1.

In the current control switch MSWI2, the control signal _VIAMP is input to the gate from the detection circuit 30. For example, the current control switch MSWI2 is turned on when a control signal for operating the preamplifier circuit 10 is input to the gate. For example, the current control switch MSWI2 operates off when a control signal for stopping the preamplifier circuit 10 is input to the gate.

The gate of the current control switch MSWI2 is connected to the detection circuit 30. The source of the current control switch MSWI2 is connected to the power supply terminal. In the current control switch MSWI2, the drain is connected to the source of the second transistor M2.

The comparator circuit 200A according to the third modification stops the preamplifier circuit 10 after the latch circuit 20 starts operating. As a result, the preamplifier circuit 10 can be stopped while the latch circuit 20 is operating, so that the current consumption of the preamplifier circuit 10 during this period can be reduced. Therefore, it is possible to realize the comparator circuit 200A in which the power consumption is sufficiently reduced as compared with the conventional comparator circuit.

As shown in FIG. 10B, the comparator circuit 200B has a configuration in which two current control switches MSWI1 and current control switches MSWI2 are inserted between the first transistor M1 and the second transistor M2 and the node 101 and the node 102. Has.

The preamplifier circuit 10B includes a first transistor M1, a second transistor M2, a current control switch MSWI1, a current control switch MSWI2, a first initialization switch MSW1, and a second initialization switch MSW2.

In the current control switch MSWI1, the control signal _VIAMP is input to the gate from the detection circuit 30. For example, the current control switch MSWI1 is turned on when a control signal for operating the preamplifier circuit 10 is input to the gate. For example, the current control switch MSWI1 operates off when a control signal for stopping the preamplifier circuit 10 is input to the gate.

The gate of the current control switch MSWI1 is connected to the detection circuit 30. The source of the current control switch MSWI1 is connected to the drain of the first transistor M1. The drain of the current control switch MSWI1 is connected to the node 101.

In the current control switch MSWI2, the control signal _VIAMP is input to the gate from the detection circuit 30. For example, the current control switch MSWI2 is turned on when a control signal for operating the preamplifier circuit 10 is input to the gate. For example, the current control switch MSWI2 operates off when a control signal for stopping the preamplifier circuit 10 is input to the gate.

The gate of the current control switch MSWI2 is connected to the detection circuit 30. The source of the current control switch MSWI2 is connected to the drain of the second transistor M2. The drain of the current control switch MSWI2 is connected to the node 102.

The comparator circuit 200B according to the third modification stops the preamplifier circuit 10 after the latch circuit 20 starts operating. As a result, the preamplifier circuit 10 can be stopped while the latch circuit 20 is operating, so that the current consumption of the preamplifier circuit 10 during this period can be reduced. Therefore, it is possible to realize the comparator circuit 200B in which the power consumption is sufficiently reduced as compared with the conventional comparator circuit.

As shown in FIG. 10C, the comparator circuit 200C has a configuration in which two are inserted between the node 101 and the node 102 and the first initialization switch MSW1 and the second initialization switch MSW2.

The preamplifier circuit 10C includes a first transistor M1, a second transistor M2, a current control switch MSWI1, a current control switch MSWI2, a first initialization switch MSW1, and a second initialization switch MSW2.

In the current control switch MSWI1, the control signal _VIAMP is input to the gate from the detection circuit 30. For example, the current control switch MSWI1 is turned on when a control signal for operating the preamplifier circuit 10 is input to the gate. For example, the current control switch MSWI1 operates off when a control signal for stopping the preamplifier circuit 10 is input to the gate.

The gate of the current control switch MSWI1 is connected to the detection circuit 30. The source of the current control switch MSWI1 is connected to the node 101. The drain of the current control switch MSWI1 is connected to the drain of the first initialization switch MSW1.

In the current control switch MSWI2, the control signal _VIAMP is input to the gate from the detection circuit 30. For example, the current control switch MSWI2 is turned on when a control signal for operating the preamplifier circuit 10 is input to the gate. For example, the current control switch MSWI2 operates off when a control signal for stopping the preamplifier circuit 10 is input to the gate.

The gate of the current control switch MSWI2 is connected to the detection circuit 30. The source of the current control switch MSWI2 is connected to the node 102. In the current control switch MSWI2, the drain is connected to the drain of the second initialization switch MSW2.

The comparator circuit 200C according to the third modification stops the preamplifier circuit 10 after the latch circuit 20 starts operating. As a result, the preamplifier circuit 10 can be stopped while the latch circuit 20 is operating, so that the current consumption of the preamplifier circuit 10 during this period can be reduced. Therefore, it is possible to realize the comparator circuit 200C in which the power consumption is sufficiently reduced as compared with the conventional comparator circuit.

<Other variants>
In the present embodiment, the threshold voltage of the third transistor M3 and the fourth transistor M4, or the first detection transistor MOX1 and the second detection transistor MOX2 are applied by applying the low threshold MOS, the high threshold MOS, the back gate effect, and the like. Although the case of adjusting the threshold voltage has been described as an example, the method of adjusting the threshold voltage is not limited to these. For example, the threshold voltage of the third transistor M3 and the fourth transistor M4 or the threshold voltage of the first detection transistor MOX1 and the second detection transistor MOX2 may be changed by adjusting the size of the MOS.

Although the above embodiments have been described as representative examples, it will be apparent to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present disclosure. Therefore, the present invention should not be construed as being limited by the above-described embodiments, and various modifications and modifications can be made without departing from the scope of claims. For example, it is possible to combine a plurality of the constituent blocks described in the configuration diagram of the embodiment into one, or to divide one constituent block into one.

10 Preamp Circuit 10A Preamp Circuit 10A'Preamp Circuit 10B Preamp Circuit 10C Preamp Circuit 11 Input Terminal 12 Input Terminal 20 Latch Circuit 20A' Latch Circuit 21 Output Terminal 22 Output Terminal 30 Detection Circuit 30A Detection Circuit 30A' Detection Circuit 31 NAND Circuit 32 Delay Circuit 33 NOR circuit 100 Comparator circuit 100'Comparator circuit 100A Comparator circuit 100A' Comparator circuit 100B Comparator circuit 100C Comparator circuit 101 node 102 node 103 node 200A Comparator circuit 200B Comparator circuit 200C Comparator circuit 300 Detection control circuit 300A Detection control circuit

Claims (5)

A preamplifier circuit that generates a first preamplifier output signal and a second preamplifier output signal based on the first input signal and the second input signal, and
A latch circuit that compares the first preamplifier output signal and the second preamplifier output signal to generate a first output signal and a second output signal.
A detection circuit that generates a control signal for operating or stopping the preamplifier circuit based on the first preamplifier output signal and the second preamplifier output signal.
A comparator circuit. The detection circuit is
The first preamplifier output signal or the detection signal for detecting the second preamplifier output signal is delayed, or the latch circuit delays the detection of the first preamplifier output signal or the second preamplifier output signal. A detection control circuit for detecting one preamplifier output signal or the second preamplifier output signal is provided.
The preamplifier circuit is stopped based on the output signal of the detection control circuit.
The comparator circuit according to claim 1. The detection circuit further includes a control signal generation circuit.
The detection control circuit is
A first detection transistor that detects whether or not the threshold voltage is the first threshold voltage and the first preamplifier output signal exceeds the first threshold voltage.
A second detection transistor that detects whether or not the threshold voltage is the second threshold voltage and the second preamplifier output signal exceeds the second threshold voltage.
A switch that precharges the node to which the drain of the first detection transistor and the drain of the second detection transistor are connected to the first voltage.
A delay circuit that delays a detection signal indicating the voltage of the node and generates a delay signal based on the first preamplifier output signal and the second preamplifier output signal.
Have,
The control signal generation circuit is
The control signal is generated based on the clock signal and the delay signal, and is output to the preamplifier circuit.
The comparator circuit according to claim 2. The latch circuit is
The first input transistor whose threshold voltage is the first threshold voltage,
A second input transistor whose threshold voltage is the second threshold voltage is provided.
The detection circuit further includes a control signal generation circuit.
The detection control circuit is
A first detection transistor for detecting whether or not the threshold voltage is a third threshold voltage larger than the first threshold voltage and the first preamplifier output signal exceeds the third threshold voltage.
A second detection transistor whose threshold voltage is a fourth threshold voltage larger than the second threshold voltage and detects whether or not the second preamplifier output signal exceeds the fourth threshold voltage.
A switch that precharges the node to which the drain of the first detection transistor and the drain of the second detection transistor are connected to the first voltage.
Have,
The control signal generation circuit is
The control signal is generated based on the clock signal and the detection signal indicating the voltage of the node, and is output to the preamplifier circuit.
The comparator circuit according to claim 2. The preamplifier circuit is
An input differential pair including a first transistor in which the first input signal is input to the gate and a second transistor in which the second input signal is input to the gate.
A current control switch in which the control signal is input to the gate, the source is connected to the power supply terminal, and the drain is connected to the source of the first transistor and the source of the second transistor.
A first initialization switch where an inverting clock signal is input to the gate, the source is connected to the ground terminal, and the drain is connected to the drain of the first transistor.
A second initialization switch in which the inverting clock signal is input to the gate, the source is connected to the ground terminal, and the drain is connected to the drain of the second transistor.
Equipped with
The latch circuit is
An input differential pair including a third transistor in which the second preamplifier output signal is input to the gate and a fourth transistor in which the first preamplifier output signal is input to the gate.
A fifth transistor in which the source is connected to the power supply terminal and the drain is connected to the drain of the third transistor.
A sixth transistor in which the source is connected to the power supply terminal and the drain is connected to the drain of the fourth transistor.
A seventh transistor in which the gate is connected to the gate of the fifth transistor and the drain is connected to the source of the third transistor.
An eighth transistor whose gate is connected to the gate of the sixth transistor and whose drain is connected to the source of the fourth transistor.
A third initialization switch in which the clock signal is input to the gate, the source is connected to the power supply terminal, and the drain is connected to the drain of the fifth transistor.
A fourth initialization switch in which the clock signal is input to the gate, the source is connected to the power supply terminal, and the drain is connected to the drain of the sixth transistor.
A fifth initialization switch in which the clock signal is input to the gate, the source is connected to the ground terminal, and the drain is connected to the source of the seventh transistor and the source of the eighth transistor.
To prepare
The comparator circuit according to any one of claims 1 to 3.

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