JP2022087228A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which can favorably read out information from memory means.

SOLUTION: In an audio light emission control board 101, an audio light SOC 102 and an audio light ROM 103 are provided. The audio light SOC 102 includes: a control core 111 which determines an execution content of a performance according to a command received from a main control unit, and executes a light emission control of a display light emission part 53 according to the determined performance content; an audio output core 112 which executes an audio output control of a speaker part 54 according to the performance content determined by the control core 111; and a memory controller 114 which executes the read-out of data from the audio light ROM 103 according to address data transmitted from a DMA 123 of the control core 111 and address data transmitted from a data transfer part 134 of the audio output core 112. Here, program data used in the control core 111 is integrally read out at the start of operation power supply.

SELECTED DRAWING: Figure 8

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a gaming machine.

Pachinko gaming machines, slot machines, and the like are known as a type of gaming machine. These gaming machines include a general-purpose control element such as a CPU and a read-only storage element such as a ROM, and a series of processes are executed by the general-purpose control element according to a program read from the read-only storage element. The game is controlled (see, for example, Patent Document 1). It is also known that a general-purpose control element, a read-only storage element, and the like are integrated into a single chip.

Further, there is also known a configuration in which a dedicated control element is used as a control element for performing sound output control and display control. In this case, the operation of the controlled device is controlled based on the processing being executed by the dedicated control element according to the data read from the read-only storage element.

Japanese Unexamined Patent Publication No. 2009-261415

Here, in a gaming machine such as the above example, it is necessary to suitably read information from a storage means, and there is still room for improvement in this respect.

The present invention has been made in view of the above-exemplified circumstances and the like, and an object of the present invention is to provide a gaming machine capable of suitably reading information from a storage means.

The invention according to claim 1 in order to solve the above problems includes a storage means for storing information in advance and a storage means.
A first control means that executes the first control using the information stored in the storage means, and
A second control means that executes the second control using the information stored in the storage means, and
Equipped with
The storage means is
Information for the program necessary for executing the program in the first control means and
The first control information necessary for determining the control mode of the controlled object when the first control is executed according to the program, and
The second control information necessary for determining the control mode of the controlled object when executing the second control in the second control means, and
Is at least remembered,
The first control means is characterized by comprising a reading means for reading the program information to the first side storage means during a period in which the reading instruction of the first control information and the second control information is not generated. do.

According to the present invention, it is possible to suitably read information from the storage means.

It is a perspective view which shows the pachinko machine in 1st Embodiment. It is a perspective view which shows the main structure of a pachinko machine by disassembling. It is a front view which shows the structure of a game board. It is a block diagram which shows the electric structure of a pachinko machine. It is explanatory drawing for demonstrating the contents of various counters used for a winning or failing lottery. It is a flowchart which shows the main process executed by MPU of a main control unit. It is a flowchart which shows the timer interrupt processing executed by the MPU of a main control unit. It is a block diagram which shows the electric structure for performing the execution control of an effect. It is explanatory drawing for demonstrating the data structure of a register. It is explanatory drawing for demonstrating an example of sequence data. It is explanatory drawing for demonstrating the data structure of the sound light ROM. It is a flowchart which shows the main process executed by the CPU of a control core. It is a time chart for demonstrating the relationship between the period in which a power-on wait process is executed in the MPU of a main control unit, and the period in which data is read out at the time of power-up in a control core. It is explanatory drawing for demonstrating the data structure of RAM. It is a flowchart which shows the process for normality determination executed by the CPU of a control core. It is a time chart which shows how a normal judgment is executed. It is a flowchart which shows the timer interrupt processing executed by the CPU of a control core. It is a flowchart which shows the operation in DMA. It is a time chart which shows how the data is read out from the sound light ROM with respect to the transmission of the address data from DMA. It is a flowchart which shows the operation in a data transfer part. It is a flowchart which shows the operation in a memory controller. It is a time chart for demonstrating the reading mode of data in the case where the period in which a read instruction is given from DMA and the period in which a read instruction is given from a data transfer unit overlap. It is explanatory drawing for demonstrating the unit reading period in the case where the sound data for the maximum channel is read in each of HWD and SCM. It is a flowchart which shows the normality determination processing executed by the CPU of the control core in 2nd Embodiment. (A) It is a flowchart which shows the operation in DMA, and (b) is the flowchart which shows the operation in a data transfer unit. It is a block diagram which shows the electric structure for performing the execution control of the staging in 3rd Embodiment. It is explanatory drawing for demonstrating the data structure of the direct-attached ROM. It is a flowchart which shows the main process executed by the CPU of a control core. (A) is a flowchart showing a command interrupt process executed by the CPU of the control core, and (b) is a flowchart showing a timer interrupt process executed by the CPU of the control core. It is a flowchart which shows the process for normality determination executed by the CPU of a control core. It is a flowchart which shows the operation in DMA. It is a time chart for demonstrating the reading mode of various data. It is explanatory drawing for demonstrating the relationship between the execution cycle of a normality determination process and the execution period of various processes.

<First Embodiment>
Hereinafter, a first embodiment of a pachinko gaming machine (hereinafter referred to as “pachinko machine”), which is a kind of gaming machine, will be described in detail with reference to the drawings. FIG. 1 is a perspective view of the pachinko machine 10, and FIG. 2 is a perspective view showing the main configurations of the pachinko machine 10 in an exploded manner. Note that, in FIG. 2, for convenience, the configuration in the gaming area of the pachinko machine 10 is omitted.

As shown in FIG. 1, the pachinko machine 10 has an outer frame 11 forming an outer shell of the pachinko machine 10 and a gaming machine main body 12 rotatably attached to the outer frame 11 in the forward direction. .. The outer frame 11 is formed by connecting wooden plates on all four sides and has a rectangular frame shape. The pachinko machine 10 is installed in the game hall by attaching and fixing the outer frame 11 to the island equipment. In the pachinko machine 10, the outer frame 11 is not an indispensable configuration, and the outer frame 11 may be provided in the island equipment of the game hall.

As shown in FIG. 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 arranged in front of the inner frame 13, and a back pack unit 15 arranged behind the inner frame 13. ing. The inner frame 13 of the gaming machine main body 12 is rotatably supported with respect to the outer frame 11. Specifically, the inner frame 13 can rotate forward with the left side as the rotation base end side and the right side as the rotation tip side in front view.

The front door frame 14 is rotatably supported by the inner frame 13, and is rotatable forward with the left side as the rotation base end side and the right side as the rotation tip side in front view. Further, the back pack unit 15 is rotatably supported on the inner frame 13, and is rotatable rearward with the left side as the rotation base end side and the right side as the rotation tip side in front view.

The gaming machine main body 12 is provided with a locking device at the rotating tip portion thereof, and has a function of locking the gaming machine main body 12 with respect to the outer frame 11 so as to be in a locked state. It has a function of locking the door frame 14 to the inner frame 13 so that it cannot be opened. Each of these locked states is released by performing an unlocking operation using the unlocking key on the cylinder lock 17 exposed on the front surface of the pachinko machine 10.

Next, the configuration of the front side of the gaming machine main body 12 will be described.

The inner frame 13 is mainly composed of a resin base 21 having an outer shape substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the central portion of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front surface of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 of the resin base 21.

Here, the configuration of the game board 24 will be described with reference to FIG. FIG. 3 is a front view of the game board 24.

An inner rail portion 25 and an outer rail portion 26 are attached to the game board 24 so as to partition a part of the outer edge of the game area PA, and the guiding means is provided by the inner rail portion 25 and the outer rail portion 26. As a guide rail is configured. The game ball launched from the game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 is guided to the upper part of the game area PA by the guide rail.

Incidentally, the game ball launch mechanism 27 has a launch rail 27a extending toward the guide rail, a ball feeding device 27b for supplying the game ball stored in the precision plate 55a described later on the launch rail 27a, and the launch rail 27a. It is equipped with a solenoid 27c, which is an electric actuator that launches the game ball supplied to the guide rail toward the guide rail. The solenoid 27c is driven and controlled by the rotation operation of the launch operation device (or operation handle) 28 provided on the front door frame 14, and the game ball is launched.

The game board 24 is formed with a plurality of large and small openings penetrating in the front-rear direction. Each opening is provided with a general winning opening 31, a special electric winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special drawing unit 37, a normal drawing unit 38, and the like. ing.

Even if a ball enters the through gate 35, the game ball is not paid out. On the other hand, when a ball enters the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls are paid out. Specifically, regarding the number of prize balls, when a ball enters the first operating port 33 or a ball enters the second operating port 34, three prize balls are paid out. , When a ball is entered into the general winning opening 31, 10 prize balls are paid out, and when a ball is entered into the special electric winning device 32, 15 prize balls are paid out. Will be executed.

The number of prize balls is arbitrary. For example, the number of prize balls in the second operating port 34 may be smaller than that in the first operating port 33, and the second operating port 34 is the first operating port. The number of prize balls may be larger than 33.

In addition, an out opening 24a is provided at the lowermost portion of the game board 24, and a game ball that has not entered various winning openings or the like is discharged from the game area PA through the out opening 24a. Further, a large number of nails 24b are planted on the game board 24 in order to appropriately disperse and adjust the falling direction of the game ball, and various members such as a windmill are arranged.

Here, the entry ball means that the game ball passes through a predetermined opening, and not only is the ball discharged from the game area PA after passing through the opening, but also from the game area PA after passing through the opening. A mode in which the flow of the gaming area PA is continued without being discharged is also included. However, in the following description, in order to clearly distinguish the ball from entering the game ball into the out opening 24a, the general winning opening 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 The entry of a game ball into a game is also referred to as a prize.

The first operating port 33 and the second operating port 34 are unitized as an operating port device and installed on the game board 24. Both the first actuating port 33 and the second actuating port 34 are open upward. Further, both the operating ports 33 and 34 are arranged in the vertical direction so that the first operating port 33 faces upward. The second actuating port 34 is provided with a universal electric accessory 34a as a guide piece made of a pair of left and right movable pieces. In the closed state of the general electric accessory 34a, the game ball cannot win the prize in the second operating port 34, and when the general electric accessory 34a is in the open state, the prize can be won in the second operating port 34.

A through gate 35 is provided on the upstream side of the second operating port 34 in the flow direction of the game ball. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the game ball winning the through gate 35 flows down the game area PA after winning. As a result, the game ball that has won the through gate 35 can win the second operating port 34.

Based on the winning of the through gate 35, the universal electric accessory 34a of the second operating port 34 is switched from the closed state to the open state. Specifically, an internal lottery is performed triggered by winning a prize in the through gate 35, and a normal map display of the normal map unit 38 provided in the lower right corner, which is an area where the game ball does not pass in the game area PA. The variable display of the pattern is performed in the part 38a. Then, when the result of the internal lottery is the winning of the electric service opening, the stop result corresponding to the result is displayed, and the variable display of the general map display unit 38a is completed, the state shifts to the general electric opening state. In the open state of the normal electric power, the public electric accessory 34a is in the open state in a predetermined manner.

The cathode ray display unit 38a is composed of a segment display device in which a plurality of segment light emitting units are arranged in a predetermined manner, but the present invention is not limited to this, and the liquid crystal display device and the organic EL display device are not limited thereto. , CRT or other types of display devices such as dot matrix displays. Further, as the pattern to be variablely displayed on the general map display unit 38a, a configuration in which a plurality of types of characters are variablely displayed, a configuration in which a plurality of types of symbols are variablely displayed, a configuration in which a plurality of types of characters are variablely displayed, or a configuration in which a plurality of types of characters are variablely displayed. A configuration in which multiple types of colors are switched and displayed can be considered.

In the normal drawing unit 38, a normal drawing holding display unit 38b is provided at a position adjacent to the normal drawing display unit 38a. The number of game balls that have won a prize in the through gate 35 is reserved up to a maximum of four, and the reserved number is displayed by lighting the normal figure reservation display unit 38b.

A winning lottery is performed triggered by winning a prize in the first operating port 33 or the second operating port 34. Then, the lottery result is clearly shown through the display effect in the symbol display device 41 of the special figure unit 37 and the variable display unit 36.

More specifically, the special figure unit 37 is provided with a special figure display unit 37a. The display area of the special figure display unit 37a is narrower than the display surface 41a of the symbol display device 41. In the special figure display unit 37a, a winning lottery is performed triggered by a prize in the first operating port 33 or a winning in the second operating port 34, so that a variable display or a predetermined display of the pattern is performed. Then, the result corresponding to the lottery result is displayed. The special figure display unit 37a is composed of a segment display device in which a plurality of segment light emitting units are arranged in a predetermined manner, but the present invention is not limited to this, and the liquid crystal display device and the organic EL display device are not limited thereto. , CRT or other types of display devices such as dot matrix displays. Further, as the pattern displayed on the special figure display unit 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a configuration in which a plurality of types of colors are displayed. Is displayed.

In the special figure unit 37, a special figure hold display unit 37b is provided at a position adjacent to the special figure display unit 37a. The number of game balls that have won a prize in the first operating port 33 or the second operating port 34 is reserved up to four, and the reserved number is displayed by lighting the special figure reservation display unit 37b.

About the symbol display device 41 In detail, the symbol display device 41 is configured as a liquid crystal display device provided with a liquid crystal display, and the display content is controlled by a display control device described later. The symbol display device 41 is not limited to the liquid crystal display device, and may be another display device having a display screen such as a plasma display device, an organic EL display device, or a CRT, and is a dot matrix display device. You may.

In the symbol display device 41, when the special symbol display unit 37a performs a variable display or a predetermined display of the symbol based on the winning of the first operating port 33 or the winning of the second operating port 34, the symbol is displayed accordingly. A variable display or a predetermined display is performed. For example, on the display surface 41a of the symbol display device 41, three symbol rows of upper, middle, and lower rows are set as a plurality of display areas, and the numbers "1" to "9" are added to each symbol row. The symbols are scrolled and displayed in ascending or descending order. In this scroll display, the scroll display in all the symbol columns is started first, the scroll display is switched to the standby display in the order of the upper symbol column → the lower symbol column → the middle symbol column, and finally the predetermined symbol display is specified in each symbol column. It ends with the symbol still displayed. Then, for example, in a game round in which the game result is a big hit result, a predetermined combination of symbols is stopped and displayed on a preset effective line on the display surface 41a of the symbol display device 41.

In the symbol display device 41, not only the display effect triggered by winning a prize in the first actuating port 33 or the second actuating port 34, but also the display effect in the open / close execution mode that shifts after winning is performed. Will be. Further, based on the winning of any of the operating ports 33 and 34, the display is started on the special figure display unit 37a and the symbol display device 41, and the game times 1 until the predetermined result is displayed and ended. Equivalent to times. Further, the mode of variable display of symbols in the symbol display device 41 is not limited to the above, and is arbitrary, such as the number of symbol rows, the direction of variable display of symbols in the symbol row, the number of symbols in each symbol row, and the like. Can be changed as appropriate. Further, the pattern to be variablely displayed by the symbol display device 41 is not limited to the above-mentioned symbol, and may be configured such that only numbers are variablely displayed as the symbol, for example.

If a big hit is won in the winning lottery based on the winning of the first operating port 33 or the winning of the second operating port 34, the mode shifts to the opening / closing execution mode in which the special electric winning device 32 can be won. The special electric winning device 32 is provided with a large winning opening (not shown) leading to the back side of the game board 24, and is provided with an opening / closing door 32a for opening and closing the large winning opening. The opening / closing door 32a is arranged in either a closed state or an open state. Specifically, the opening / closing door 32a is normally in a closed state in which the game ball cannot win a prize, and is switched to an open state in which the game ball can win a prize when the transition to the open / close execution mode is won in the internal lottery. It has become. By the way, the open / close execution mode is a mode in which the transition is made when a hit result is obtained. It should be noted that although it is not impossible to win a prize in the closed state, it may be configured in a state in which it is more difficult for the prize to occur than in the open state.

As shown in FIG. 2, the front door frame 14 is provided so as to cover the entire front surface side of the inner frame 13 in which the game board 24 having the above configuration is attached to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 so that almost the entire area of the game area PA can be visually recognized from the front. The window portion 51 has a substantially elliptical shape, and the window panel 52 is fitted therein. The window panel 52 is colorless and transparently formed by glass, but is not limited to this, and may be colorless and transparent by synthetic resin, and the gaming area PA is formed from the front of the pachinko machine 10 through the window panel 52. It may be colored and transparent as long as it is visible.

A display light emitting unit 53 is provided above the window unit 51. Further, a pair of left and right speaker units 54 for outputting sound effects and the like according to the game state are provided. Further, below the window portion 51, an upper bulging portion 55 bulging toward the front side and a lower bulging portion 56 are vertically arranged side by side. An upper plate 55a opened upward is provided inside the upper bulging portion 55, and a lower plate 56a also opened upward is provided inside the lower bulging portion 56. The upper plate 55a has a function of temporarily storing the game balls paid out from the payout device described later and guiding them to the game ball launching mechanism 27 side while arranging them in a row. Further, the lower plate 56a has a function of storing excess game balls in the upper plate 55a.

Next, the configuration of the back side of the gaming machine main body 12 will be described.

As shown in FIG. 2, a main control device 60 that controls the main control of the game is mounted on the back surface of the inner frame 13 (specifically, the game board 24). The main control device 60 has a main control board housed in a board box. The substrate box may be provided with a trace means for leaving a trace of its opening, or may be provided with a trace structure for leaving a trace of its opening. As the trace means, a plurality of case bodies constituting the substrate box are inseparably bonded, and a bonding portion that requires destruction of a predetermined part at the time of separation is configured, or an adhesive layer remains on the bonding target at the time of peeling. It is conceivable that a sealing seal that leaves a trace of the fact that it has been done is attached so as to straddle the boundary between a plurality of case bodies. Further, as the trace structure, a configuration in which an adhesive is applied to the boundary between a plurality of case bodies constituting the substrate box can be considered.

The back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main control device 60. The back pack unit 15 includes a back pack 72 formed of a transparent synthetic resin, and a payout mechanism unit 73 and a control device collective unit 74 are attached to the back pack 72.

The payout mechanism unit 73 includes a tank 75 in which game balls supplied from the island equipment of the game hall are sequentially replenished, and a payout device 76 for paying out the game balls stored in the tank 75. The game ball paid out from the payout device 76 is discharged to the upper plate 55a or the lower plate 56a through the payout passage provided on the downstream side of the payout device 76. The payout mechanism unit 73 is provided with, for example, a back pack board having a power switch for turning on and off the power supply while supplying a main power supply of AC 24 volts.

The control device collective unit 74 generates and outputs predetermined electric power required by the payout control device 77 having a function of controlling the payout device 76 and various control devices, and is accompanied by the operation of the launch operation device 28 by the player. It is equipped with a power supply / launch control device 78 for controlling the launch of a game ball. The payout control device 77 and the power supply / launch control device 78 are arranged so as to be stacked in the front-rear direction so that the payout control device 77 is behind the pachinko machine 10.

<Electrical configuration of pachinko machine 10>
FIG. 4 is a block diagram showing an electrical configuration of the pachinko machine 10.

The main control device 60 includes a main control board 61 that controls the main control of the game, and a power failure monitoring board 65 that monitors the power supply. The MPU 62 is mounted on the main control board 61. The MPU 62 is a ROM 63 that stores various control programs and fixed value data executed by the MPU 62, and a memory for temporarily storing various data and the like when the control program stored in the ROM 63 is executed. A certain RAM 64, an interrupt circuit, a timer circuit, a data input / output circuit, various counter circuits as a random number generator, and the like are built-in. It is not essential that the ROM 63 and the RAM 64 are integrated into one chip with respect to the MPU 62, and each may be individually chipped. This also applies to MPUs of control devices other than the main control device 60.

The MPU 62 is provided with an input port and an output port, respectively. A power failure monitoring board 65 and a payout control device 77 provided in the main control device 60 are connected to the input side of the MPU 62. A power supply / emission control device 78 having a function of supplying operating power is connected to the power failure monitoring board 65, and power is supplied to the MPU 62 via the power failure monitoring board 65.

Further, various sensors such as various prize detection sensors 66a to 66e are connected to the input side of the MPU 62. The various prize detection sensors 66a to 66e are provided on a one-to-one basis with respect to the winning portion corresponding to winning such as the general winning opening 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35. The detection sensor is included, and the MPU 62 determines the winning of each ball entry portion. Further, in the MPU 62, various lottery is executed based on the winning of the first operating port 33, and various lottery is executed based on the winning of the second operating port 34.

A power failure monitoring board 65, a payout control device 77, and a voice emission control device 80 are connected to the output side of the MPU 62. A prize ball command is output to the payout control device 77, for example, based on the winning determination result for the winning ball unit corresponding to the winning. Various commands such as fluctuation commands, type commands, and opening commands are output to the voice emission control device 80. Details of these various commands will be described later. The MPU 62 transmits a command to the voice emission control device 80 by parallel communication.

Further, on the output side of the MPU 62, there is a drive unit 32b for special electric power that opens and closes the opening / closing door 32a of the special electric winning device 32, and a drive unit 34b for general electric power that opens and closes the general electric accessory 34a of the second operating port 34. , The special figure unit 37 and the normal figure unit 38 are connected. Incidentally, the special figure unit 37 is provided with a special figure display unit 37a and a special figure hold display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal map unit 38 is provided with a normal map display unit 38a and a normal map hold display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 executes drive control of various drive units and various display units through the driver circuits.

That is, in the open / close execution mode, the drive control of the special electric drive unit 32b is executed in the MPU 62 so that the special electric winning device 32 is opened / closed. Further, when the open state of the utility accessory 34a is won, the drive control of the drive unit 34b for the utility is executed in the MPU 62 so that the utility accessory 34a is opened and closed. Further, at each game round, the display control of the special figure display unit 37a is executed in the MPU 62. Further, when the lottery result of whether or not to open the general electric accessory 34a is clearly shown, the display control of the general drawing display unit 38a is executed in the MPU 62. Further, when a prize is awarded to the first operating port 33 or the second operating port 34, or when the variable display is started in the special figure display unit 37a, the display control of the special figure holding display unit 37b is executed in the MPU 62. Then, when a prize is won in the through gate 35, or when the variable display is started in the normal figure display unit 38a, the display control of the normal figure hold display unit 38b is executed in the MPU 62.

The power failure monitoring board 65 relays between the main control board 61 and the power supply / emission control device 78, and monitors the DC stable 24 volt voltage, which is the maximum voltage output from the power supply / emission control device 78. The payout control device 77 controls the payout of prize balls and rental balls by the payout device 76 based on the prize ball command received from the main control device 60.

The power supply / launch control device 78 is connected to, for example, a commercial power supply (external power supply) in a game hall or the like. Then, based on the external power supplied from the commercial power source, the operating power required for each of the main control board 61, the payout control device 77, and the like is generated, and the generated operating power is supplied. By the way, the power supply / emission control device 78 is provided with a power supply unit for power failure such as a backup capacitor, and even when the power of the pachinko machine 10 is in the OFF state, the power supply unit for power failure is mainly used. Power for storage retention is supplied to the RAM 64 of the control device 60. Further, the power supply / launch control device 78 is responsible for launch control of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when predetermined launch conditions are met.

The voice emission control device 80 drives and controls the display light emission unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 90. Is. The display control device 90 executes the display control of the symbol display device 41 based on the command received from the voice emission control device 80.

<Electrical configuration for performing various lottery with MPU 62 of the main control device 60>
Next, an electrical configuration for performing various lottery in the MPU 62 of the main control device 60 will be described with reference to FIG.

The MPU 62 uses various counter information during the game to perform a big hit generation lottery, setting the display of the special figure display unit 37a, setting the symbol display of the symbol display device 41, setting the display of the normal figure display unit 38a, and the like. Specifically, as shown in FIG. 5, when the hit random number counter C1 used for the lottery for hit occurrence, the jackpot type counter C2 used for determining the jackpot type, and the symbol display device 41 are displaced and fluctuate. The reach random number counter C3 used for the reach generation lottery, the random number initial value counter CINI used for setting the initial value of the winning random number counter C1, and the variation type for determining the display duration in the special figure display unit 37a and the symbol display device 41. The counter CS is used. Further, it is decided to use the general electric accessory opening counter C4 used for the lottery as to whether or not the general electric accessory 34a of the second operating port 34 is set to the ordinary electric accessory open state. The counters C1 to C3, CINI, CS, and C4 are provided in various counter areas 64b of the RAM 64.

Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter in which 1 is added to the previous value each time the counter is updated, and the counter returns to 0 after reaching the maximum value. Each counter is updated at short intervals. The information corresponding to the hit random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is provided in the RAM 64 as an acquisition information storage means when a prize is won in the first operating port 33 or the second operating port 34. It is stored in the hold storage area 64a.

The hold storage area 64a includes a hold area RE and an execution area AE. The holding area RE includes a first holding area RE1, a second holding area RE2, a third holding area RE3, and a fourth holding area RE4, and is used in the winning history of the first operating port 33 or the second operating port 34. In addition, the combination of the numerical information of the hit random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored as the hold information in any of the hold areas RE1 to RE4.

In this case, in the first holding area RE1 to the fourth holding area RE4, when the first operating port 33 or the second operating port 34 is awarded a plurality of times in succession, the first holding area RE1 → the second Each numerical information is stored in the order of the holding area RE2 → the third holding area RE3 → the fourth holding area RE4 in chronological order. By providing the four holding areas RE1 to RE4 in this way, up to four winning histories of the game balls to the first operating port 33 or the second operating port 34 can be reserved and stored. ..

The number that can be stored on hold is not limited to four, and may be any other, such as two, three, or five or more, or may be a single number.

The execution area AE is an area for moving each numerical information stored in the first holding area RE1 of the holding area RE when starting the variable display of the special figure display unit 37a, and is the start of one game. At that time, a hit / fail judgment or the like is performed based on various numerical information stored in the execution area AE.

Each of the above counters will be described in detail.

First, the general electric utility opening counter C4 will be described. The general electric utility opening counter C4 is configured to, for example, add 1 in order within the range of 0 to 250, reach the maximum value, and then return to 0. The general electric accessory opening counter C4 is periodically updated, and is stored in the general electric holding area 64c of the RAM 64 at the timing when the game ball wins the through gate 35. Then, at a predetermined timing, a lottery is performed as to whether or not to control the general electric accessory 34a to the open state by the value of the stored general electric accessory open counter C4.

In the pachinko machine 10, a plurality of types of support modes are set so that the modes of support by the general electric accessory 34a are different from each other. Specifically, in the support mode, when compared in a situation where the game ball is continuously launched in the same manner with respect to the game area, the general electric accessory 34a of the second operating port 34 is per unit time. A high-frequency support mode and a low-frequency support mode are set so that the frequency of being in the open state is relatively high or low.

In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal-electricity open state in the general-purpose electric power opening lottery using the general-purpose electric goods opening counter C4 is the same (for example, both are 4/5). In the high-frequency support mode, the number of times the general-purpose accessory 34a is opened when the general-purpose electric accessory 34a is won is set more than in the low-frequency support mode, and one opening time is set longer. Has been done. In this case, in the high-frequency support mode, when the open state of the general electric power is won and the open state of the public electric accessory 34a occurs multiple times, from the end of one open state to the start of the next open state. The closing time is set shorter than the one-time opening time. Furthermore, in the high-frequency support mode, the minimum secured time for the next public-electric open lottery to be held after one public-electric open lottery is performed (that is, the general-purpose map), compared to the low-frequency support mode. The duration of one display on the display unit 38a) is set short.

As described above, in the high frequency support mode, the probability of winning the second operating port 34 is higher than in the low frequency support mode. In other words, in the low frequency support mode, the probability of winning the first operating port 33 is higher than that of the second operating port 34, but in the high frequency support mode, the second operation is higher than that of the first operating port 33. The probability that a prize will be awarded to the mouth 34 increases. Then, when a prize is won in the second operating port 34, a predetermined number of game balls are paid out. Therefore, in the high frequency support mode, the player plays a game while not reducing the number of balls held so much. It can be carried out.

The configuration for increasing the frequency of the high-frequency support mode to be in the open state per unit time is not limited to the above, for example, in the general open lottery. It may be configured to increase the probability of winning the public electric open state. In addition, the secured time secured for the next Fuden opening lottery after one Fuden opening lottery is performed (for example, is executed by the Fuzu display unit 38a based on the winning of the through gate 35). In a configuration in which multiple types of variable display times are prepared, the high frequency support mode is set so that a shorter reservation time is easier to select or the average reservation time is shorter than the low frequency support mode. May be good. Furthermore, the number of times of opening is increased, the opening time is lengthened, and the securing time secured for the next public power opening lottery after one public power opening lottery is held is shortened. By applying any one of the conditions or any combination of the conditions of shortening the average time and increasing the winning probability, the advantage of the high frequency support mode over the low frequency support mode may be enhanced.

Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to be incremented by 1 in order within the range of, for example, 0 to 599, reach the maximum value, and then return to 0. In particular, when the hit random number counter C1 makes one round, the value of the random number initial value counter CINI at that time is read as the initial value of the hit random number counter C1. The random number initial value counter CINI is a loop counter similar to the hit random number counter C1 (value = 0 to 599). The winning random number counter C1 is periodically updated and stored in the hold storage area 64a of the RAM 64 at the timing when the game ball wins the first operating port 33 or the second operating port 34.

The value of the random number that wins the jackpot is stored in the ROM 63 as a winning / failing table. As the pass / fail table, a pass / fail table for the low probability mode and a pass / fail table for the high probability mode are set. That is, in the pachinko machine 10, a low probability mode and a high probability mode are set as the lottery mode in the winning / failing lottery means.

In the gaming state in which the winning / failing table for the low probability mode is referred to at the time of the lottery, the number of random numbers that win the big hit is two. On the other hand, in the gaming state in which the winning / failing table for the high probability mode is referred to in the lottery, the number of random numbers that win the big hit is 20. If the winning probability in the high probability mode is higher than that in the low probability mode, the number of random numbers to be won is arbitrary.

The jackpot type counter C2 is configured to be incremented by 1 in order within the range of 0 to 29, reach the maximum value, and then return to 0. The jackpot type counter C2 is periodically updated and stored in the hold storage area 64a at the timing when the game ball wins the first operating port 33 or the second operating port 34.

In this pachinko machine 10, a plurality of jackpot results are set. These plurality of big hit results are (1) the mode of opening / closing control of the special electric winning device 32 in the opening / closing execution mode, (2) the lottery mode in the winning / failing lottery means after the opening / closing execution mode ends, and (3) the first after the opening / closing execution mode ends. A plurality of jackpot results are set by providing differences in the three conditions of the support mode in the universal electric accessory 34a of the two operating ports 34.

As an aspect of the opening / closing control of the special electric winning device 32 in the opening / closing execution mode, the frequency of winning the special electric winning device 32 from the start to the end of the opening / closing execution mode is relatively high and low. Frequent winning mode and low frequency winning mode are set. Specifically, in either the high-frequency winning mode or the low-frequency winning mode, the game is executed up to a predetermined number of round games.

Here, the round game continues until either the predetermined upper limit duration elapses or the predetermined upper limit number of game balls wins the special electric winning device 32. It is a game to play. Further, the number of round games in the open / close execution mode triggered by the jackpot result is the same as the fixed number of rounds regardless of the type of jackpot result triggered by the transition. Specifically, the maximum number of round games is set to 15 rounds regardless of which jackpot result is obtained.

Further, in the pachinko machine 10, a plurality of types of opening modes of the special electric winning device 32 are set with different opening durations from the opening of the special electric winning device 32 to the closing of the special electric winning device 32. Specifically, a long-time mode in which the opening duration is set to 29 sec, which is a long time, and a short-time mode in which the opening duration is set to 0.06 sec, which is shorter than the long time, are set. Has been done.

In the pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launch mechanism 27 is driven and controlled so that one game ball is launched toward the game area every 0.6 sec. To. In addition, the maximum number of end conditions for round games is set to nine. Then, in the long-time mode among the above-mentioned opening modes, the opening duration is set to be longer than the product of the firing cycle of the game ball and one round game. On the other hand, in the short-time mode, the opening duration is set to be shorter than the product of the firing cycle of the game ball and one round game, and more specifically, the opening duration is shorter than the firing cycle of the game ball. Therefore, when the opening is performed once in the long-time mode, it is expected that the special electric winning device 32 will be awarded the maximum number of prizes in one round game, and 1 in the short-time mode. When the number of times is opened, it is expected that the special electric winning device 32 will not be awarded, or even if the winning is generated, the number will be about one.

In the high-frequency winning mode, the special electric winning device 32 is opened once in each round game according to the long-time mode. On the other hand, in the low-frequency winning mode, the special electric winning device 32 is opened once in each round game in a short-time mode.

In addition, the number of times of opening and closing of the special electric winning device 32 in the high frequency winning mode and the low frequency winning mode, the number of round games, the opening duration for one opening, and the upper limit number in one round game are those in the high frequency winning mode. Is not limited to the above values and is arbitrary as long as the frequency of winning the special electric winning device 32 from the start to the end of the opening / closing execution mode is higher than that of the low frequency winning mode. Is.

The distribution destination of the game result for the jackpot type counter C2 is stored in the ROM 63 as a distribution table. Then, as the distribution destination, a low probability jackpot result, a low winning high probability jackpot result, and the most advantageous jackpot result are set.

The low-probability jackpot result is a jackpot result in which the open / close execution mode becomes the high-frequency winning mode, and after the open / close execution mode ends, the winning / fail lottery mode becomes the low-probability mode and the support mode becomes the high-frequency support mode. However, this high-frequency support mode shifts to the low-frequency support mode when the number of games reaches the end reference number (specifically, 100 times) after the transition.

The low-winning high-probability jackpot result is a jackpot result in which the open / close execution mode becomes the low-frequency winning mode, and after the opening / closing execution mode ends, the winning / losing lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. be. These high-probability mode and high-frequency support mode continue until the lottery result in the winning / losing lottery becomes a big hit state and the state shifts to the big hit state.

The most advantageous jackpot result is a jackpot result in which the open / close execution mode becomes the high-frequency winning mode, and after the open / close execution mode ends, the win / fail lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the winning / losing lottery becomes a big hit state and the state shifts to the big hit state.

In relation to each of the above game states, the normal game state is not an open / close execution mode, but a state in which the winning / failing lottery mode is a low probability mode and the support mode is a low frequency support mode. Further, as a game result, a configuration in which a low winning high probability jackpot result is not set may be used.

In the distribution table, among the values of the jackpot type counter C2 of "0 to 29", "0 to 9" corresponds to the low accuracy jackpot result, and "10 to 14" corresponds to the low winning high accuracy jackpot result. "15-29" corresponds to the most advantageous jackpot result.

Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to be incremented by 1 in order within the range of, for example, 0 to 238, reach a maximum value, and then return to 0. Here, in the pachinko machine 10, an expected effect is set as a kind of display effect in the symbol display device 41. The expected effect is a symbol display device 41 that is provided with a symbol display device 41 capable of displaying variable symbols, and in a gaming machine in which a final stop result is given as a result of a game that results in a predetermined jackpot. In the stage before the stop result is derived and displayed after the variable display of the symbol in the above is started, it means a display state for making the player think that the variable display state is likely to be the grant correspondence result. Specifically, regarding the grant correspondence result, the combination of symbols with the same number on any of the effective lines is stopped and displayed.

Two types of expected staging are set: a reach display and a notice display for expecting the occurrence of the reach display and the occurrence of the grant response result in the stage before the reach display occurs.

In the reach display, the combination of reach symbols is displayed by stopping and displaying a part of the symbol rows among the plurality of symbol rows displayed on the display surface 41a of the symbol display device 41, and the remaining symbols are displayed in that state. A display state in which a variable display of a symbol is performed in a symbol column is included. In addition, in the state where the combination of reach symbols is displayed as described above, the variation display of the symbols is performed in the remaining symbol rows, and the reach effect is performed by displaying a predetermined character or the like as a moving image on the background screen. , A combination of reach symbols is reduced or hidden, and a predetermined character or the like is displayed as a moving image on substantially the entire display surface 41a to perform a reach effect.

In the notice display, after the variable display of the symbol is started on the display surface 41a of the symbol display device 41, the symbol is variablely displayed in all the symbol rows, or a plurality of symbol rows. In the situation where the symbols are displayed in a variable manner in the symbol row, the mode in which the character is displayed separately from the symbols on the symbol row is included. Further, a background screen having a predetermined mode different from the previous mode and a symbol on the symbol row having a predetermined mode different from the previous mode are also included. Such a notice display may occur in any of the game times when the reach display is performed and when the reach display is not performed, but the case where the reach display is performed is higher than the case where the reach display is not performed. It is set to occur with a probability.

The reach display is executed regardless of the value of the reach random number counter C3 in the game times when the combination of the same symbols is finally stopped and displayed. Further, in the game times corresponding to the jackpot result in which the combination of the same symbols is not stopped and displayed, the game is not executed regardless of the value of the reach random number counter C3. Further, in the game round corresponding to the deviation result, it is executed when the reach random number counter C3 acquired at a predetermined timing by referring to the reach table stored in the ROM 63 corresponds to the occurrence of the reach display.

On the other hand, the determination of whether or not to display the advance notice is not performed by the main control device 60, but by the voice emission control device 80. In this case, in the voice emission control device 80, the notice display is more likely to occur in the game times corresponding to any of the jackpot results than in the game times corresponding to the missed result, and the notice display having a low appearance rate is displayed. A lottery process for displaying a notice is executed so as to satisfy at least one of the conditions that are likely to occur. Incidentally, this lottery result is reflected when the effect for the game round is executed on the symbol display device 41.

Next, the variable type counter CS will be described. The variation type counter CS is configured to be incremented by 1 in order within the range of 0 to 198, and returns to 0 after reaching the maximum value. The variation type counter CS is used in the MPU 62 to determine the display duration on the special symbol display unit 37a and the symbol display duration on the symbol display device 41. The variation type counter CS is updated once every time the normal processing described later is executed once, and is repeatedly updated even within the remaining time in the normal processing. Then, the buffer value of the variation type counter CS is acquired when the variation pattern is determined at the start of the variation display on the special symbol display unit 37a and at the start of the variation of the symbol by the symbol display device 41.

<Processing configuration of main control device 60>
Next, each process executed for advancing the game by the MPU 62 of the main control device 60 will be described. The processing of the MPU 62 is roughly divided into a main processing that is started when the power is turned on and a timer interrupt processing that is started periodically (in this embodiment, at a cycle of 4 msec).

<Main processing>
First, the main process will be described with reference to the flowchart of FIG.

In step S101, the power-on wait process is executed. In the power-on wait process, for example, the process waits without proceeding to the next process until a predetermined time for waiting (specifically, 1 sec) elapses after the main process is started. During the execution period of the power-on wait process, the operation start and the initial setting of the symbol display device 41 are completed. In the following step S102, access to the RAM 64 is permitted, and in step S103, the internal function register of the MPU 62 is set.

After that, in step S104, it is determined whether or not the RAM erasing switch provided in the power supply / emission control device 78 is manually operated, and in the following step S105, whether or not "1" is set in the power failure flag of the RAM 64. Is determined. Further, in step S106, a checksum calculation process for calculating a checksum is executed, and in the following step S107, whether or not the checksum matches the checksum saved when the power is turned off, that is, the validity of the stored data is determined. judge.

In the pachinko machine 10, when the RAM data is initialized at the time of turning on the power, for example, at the start of business of the game hall, the power is turned on while pressing the RAM erasing switch. Therefore, if the RAM erase switch is pressed, the process proceeds to step S108. Further, when the power cutoff occurrence information is not set or when an abnormality in the stored data is confirmed by the checksum, the process proceeds to step S108 in the same manner. In step S108, the RAM 64 is cleared. Then, the process proceeds to step S109.

On the other hand, when the RAM erase switch is not pressed, step S109 without executing the process of step S108, provided that the power failure flag is set to "1" and the checksum is normal. Proceed to. In step S109, the power-on setting process is executed. In the power-on setting process, a predetermined area of the RAM 64 such as initialization of the power failure flag is set as an initial value, and a command corresponding to the current gaming state is transmitted to the voice emission control device 80 in order to recognize the current gaming state. do.

After that, the process proceeds to the residual processing of steps S110 to S113. That is, although the MPU 62 is configured to periodically execute the timer interrupt processing, a residual time is generated between the timer interrupt processing of one and the next timer interrupt processing. This residual time varies depending on the processing completion time of each timer interrupt process, but the residual process of steps S110 to S113 is repeatedly executed by utilizing the irregular time. In this respect, it can be said that the residual processing in steps S110 to S113 is an irregular process that is executed irregularly.

In the residual processing, first, in step S110, interrupt prohibition is set in order to prohibit the occurrence of timer interrupt processing. In the following step S111, the random number initial value update process for updating the random number initial value counter CINI is executed, and the variation counter update process for updating the variation type counter CS is executed in step S112. In these update processes, the current numerical information is read from the corresponding counter of the RAM 64, the read numerical information is added by 1, and then the read source counter is overwritten. In this case, when the counter value reaches the maximum value, it is cleared to "0" respectively. After that, in step S113, the interrupt enable setting for switching from the state in which the occurrence of the timer interrupt process is prohibited to the state in which the timer interrupt process is permitted is set. After executing the process of step S113, the process returns to step S110, and the processes of steps S110 to S113 are repeated.

<Timer interrupt processing>
Next, the timer interrupt process will be described with reference to the flowchart of FIG. 7. The timer interrupt process is executed periodically (for example, in a 4 msec cycle).

First, the power failure information storage process is executed in step S201. In the power failure information storage process, it is monitored whether or not a power failure signal corresponding to the occurrence of a power failure is received from the power failure monitoring board 65, and if the occurrence of a power failure is specified, the power failure processing is executed.

In the following step S202, the lottery random number update process is executed. In the lottery random number update process, the jackpot random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the universal utility release counter C4 are updated. Specifically, the current numerical information was sequentially read from the jackpot random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the universal utility release counter C4, and the read numerical information was added by 1 to each. Later, a process of overwriting the read source counter is executed. In this case, when the counter value reaches the maximum value, it is cleared to "0" respectively.

After that, in step S203, the random number initial value update process is executed in the same manner as in step S111, and in step S204, the fluctuation counter update process is executed in the same manner as in step S112.

In the following step S205, fraud detection processing for monitoring whether or not a predetermined event set as a monitoring target for fraud has occurred is executed. In the fraud detection process, "1" is set in the game stop flag provided in the RAM 64 by monitoring the occurrence of a plurality of types of events and confirming that a predetermined event has occurred.

In the following step S206, it is determined whether or not the progress of the game is stopped by determining whether or not "1" is set in the game stop flag. If a negative determination is made in step S206, the processes after step S207 are executed.

In step S207, the port output process is executed. In the port output process, when the output information is set in the previous timer interrupt process, the process for outputting the output corresponding to the output information to the various drive units 32b and 34b is executed. For example, when the information to switch the special electric winning device 32 to the open state is set, the output of the drive signal to the drive unit 32b for the special electric is started, and when the information to switch to the closed state is set. Stops the output of the drive signal. Further, when the information for switching the utility accessory 34a of the second operating port 34 to the open state is set, the output of the drive signal to the drive unit 34b for the utility should be started and the state should be switched to the closed state. If the information is set, the output of the drive signal is stopped.

In the following step S208, the reading process is executed. In the reading process, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in future processing.

In the following step S209, the winning detection process is executed. In the winning detection process, the signals received from the winning detection sensors 66a to 66e are read, and the general winning opening 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 are connected. Execute the process to specify whether or not there is a prize.

In the following step S210, a timer update process for collectively updating the numerical information of a plurality of types of timer counters provided in the RAM 64 is executed. In this case, the timer counters to which the stored numerical information is subtracted and updated are collectively handled, but both the subtraction type timer counter update and the addition type timer counter update are collectively performed. It may be configured.

In the following step S211, a launch control process for controlling the launch of the game ball is executed. In the situation where the firing operation to the firing operation device 28 is continued, one game ball is launched every 0.6 sec, which is a predetermined firing cycle, as described above.

In the following step S212, as the input state monitoring process, the disconnection confirmation of the winning detection sensors 66a to 66e and the opening confirmation of the gaming machine main body 12 and the front door frame 14 are confirmed based on the information read in the reading process of step S208. conduct.

In the following step S213, the special figure special electric control process for performing the execution control of the game times and the execution control of the open / close execution mode is executed. In the special figure special electric control process, when a prize is generated in the first operating port 33 or the second operating port 34 in a situation where the number of reserved information stored in the holding storage area 64a is less than the upper limit number, the prize is awarded. The processing of storing the numerical information of the jackpot random number counter C1, the jackpot type counter C2, and the reach random number counter C3 at the time point in the hold storage area 64a in time series is executed. Further, in the special figure special electric control process, it is determined whether or not the hold information corresponds to the big hit winning on the condition that the hold information is stored and not during the game rotation or the open / close execution mode. Processing, and if it corresponds to the jackpot winning, the distribution determination processing for determining which jackpot result the pending information corresponds to is executed. In addition, in the special figure special electric control process, not only the hit / fail determination process and the distribution determination process, but also whether or not the hold information corresponds to the reach occurrence when the hold information does not correspond to the big hit winning. The determination reach determination process is executed, and the process of selecting the duration of the game round is executed by using the numerical information of the variation type counter CS at that time. Then, a variable command including information on the duration according to the result of each of these processes and a type command including information on the game result are transmitted to the voice emission control device 80, and the pattern on the special figure display unit 37a is displayed. Start variable display. As a result, one game round is started, and the special figure display unit 37a and the symbol display device 41 start the effect for the game round.

Further, in the special figure special electric control process, it is determined whether or not it is the end timing of the game round during the execution of one game round, and if it is the end timing, the display corresponding to the game result is performed. , Executes the process of ending the game. In this case, a final stop command indicating that the game round should be ended is transmitted to the voice emission control device 80. Further, in the special figure special electric control process, when the result of the game round is the result corresponding to the transition to the open / close execution mode, the process for starting the open / close execution mode is executed. At the time of this start, an opening command indicating that the open / close execution mode is started is transmitted to the voice emission control device 80. Further, in the special figure special electric control process, a process for starting each round game and a process for ending each round game are executed. In each of these processes, an open command indicating that the round game is started is transmitted to the voice emission control device 80, and a closing command indicating that the round game is ended is transmitted to the voice emission control device 80. Further, in the special figure special electric control process, an ending command indicating that the opening / closing execution mode is terminated is transmitted to the voice emission control device 80, and a winning / failing lottery mode or a support mode after the opening / closing execution mode is set. Execute the process.

After executing the special figure special electric control process of step S213 in the timer interrupt process, the normal figure general electric control process is executed in step S214. In the Fuzu Fuden control process, when a prize has been won in the through gate 35, a process for acquiring the hold information on the Fuzu side is executed, and the hold information on the Fuzu side is stored. In addition, a release determination is made for the reserved information, and further, a process for performing an effect for a normal drawing is executed with the release determination as an opportunity. Further, based on the result of the opening determination, a process of opening and closing the general electric accessory 34a of the second operating port 34 is executed.

In the following step S215, based on the processing results of the immediately preceding steps S213 and S214, the output information for reflecting the increase / decrease in the number of reserved information related to the special figure display unit 37a to the special figure reservation display unit 37b is set. , The output information for reflecting the increase / decrease number of the reserved information related to the normal figure display unit 38a in the normal figure hold display unit 38b is set. Further, in step S215, output information for updating the display contents of the special figure display unit 37a is set based on the processing results of the immediately preceding steps S213 and S214, and the display contents of the normal figure display unit 38a are set. Set the output information for updating.

In the following step S216, the contents of the command and the signal received from the payout control device 77 are confirmed, and the payout state reception process for performing the process corresponding to the check result is executed. Further, in step S217, a payout output process for setting the prize ball command as an output target is executed. In the following step S218, the external information setting process for controlling the start and end of the output of the external signal according to the processing result of the various processes executed in the timer interrupt process this time is executed. After that, the timer interrupt processing is terminated.

<Electrical configuration related to staging execution control>
Next, the electrical configuration for controlling the execution of the effect will be described with reference to the block diagram of FIG.

A voice emission control device 80 is provided as a control device for controlling the execution of the effect based on the instruction from the main control device 60. As shown in FIG. 8, the voice emission control device 80 includes a voice emission control board 101 on which a sound / light SOC 102, a sound / light ROM 103, and an amplifier circuit 104 are mounted. The sound / light SOC 102 includes a control core 111, a sound output core 112, a sound data processing unit 113, and a memory controller 114, and the sound / light SOC 102 is configured by integrating each of these elements into one chip.

The control core 111 determines the specific content of the effect based on the command received from the main control device 60, and executes the light emission control of the display light emitting unit 53 according to the determined content. Further, the control core 111 sets data according to the content of the determined effect to the register 131 provided in the sound output core 112, and issues a command according to the content of the determined effect to the display control device 90. Send to. As a result, the sound output core 112 executes sound output control in a manner in accordance with the contents instructed by the control core 111, and the display control device 90 performs display control in a manner in accordance with the contents instructed by the control core 111. Run. Incidentally, the data setting for the register 131 of the sound output core 112 by the control core 111 is performed through the data bus SL that electrically connects the control core 111 and the sound output core 112 in the sound / light SOC 102. The control core 111 and the sound output core 112 can be bidirectionally communicated with each other through the data bus SL, and the data is set from the control core 111 to the sound output core 112 as described above, and the sound output core is set. A signal indicating that sound is being output is transmitted from 112 to the control core 111.

The control core 111 is used for reading program data and control data stored in advance in the sound / light ROM 103 in addition to the CPU 121, which is a central processing unit including a control unit and a calculation unit, and executes a program. A RAM 122 for temporarily storing necessary data is built in. The RAM 122 is configured to use a memory (that is, a volatile storage means) that requires external power supply for storage retention such as SRAM and DRAM for both reading and writing, and is capable of random access and is the same. When compared in terms of the data capacity of the above, the time required for reading is faster than that of the sound / light ROM 103. The data capacity of the RAM 122 has a data capacity of a large number of bytes so that a plurality of data can be stored and held at the same time, and has a data capacity of a unit of kilobytes or megabytes. Specifically, it has a data capacity of about 4 megabytes. The data capacity is smaller than the data capacity of the sound / light ROM 103. However, the data capacity of the RAM 122 is not limited to this, and is arbitrary as long as the control core 111 can be suitably controlled.

Further, the control core 111 also has a built-in DMA 123 that gives an instruction to read data from the sound / light ROM 103 to the memory controller 114 based on the instruction from the CPU 121. When the data corresponding to the data read instruction is written to the internal register of the DMA 123 by the CPU 121, the DMA 123 is for instructing the memory controller 114 to read the data until all the data corresponding to the read instruction is read into the RAM 122. Send address data. The transmission of this address data is performed in synchronization with the clock signal periodically transmitted from the clock circuit built in the DMA 123 (for example, 4 MHz).

The sound output core 112 executes the sound output control of the speaker unit 54 according to the content of the effect determined by the control core 111. The sound output core 112 contains a register 131, an HWD 132, an SCM 133, and a data transfer unit 134.

The register 131 has a function as a storage means for temporarily storing various data used in the sound output core 112, and can be used for both reading and writing a memory that requires external power supply for storage retention. It is configured to be used. In addition, random access is possible, and when compared with the same data capacity, the time required for reading is faster than that of the sound / light ROM 103. The register 131 has a data capacity of a large number of bytes so that a plurality of data can be stored and held at the same time, and has a data capacity of a unit of kilobytes or megabytes. Specifically, it has a data capacity of about 2 megabytes. The data capacity is smaller than the data capacity of the sound / light ROM 103 and smaller than the data capacity of the RAM 122 of the control core 111. However, the data capacity of the register 131 is not limited to this, and is arbitrary as long as the sound output core 112 can be suitably controlled.

The HWD 132 and the SCM 133 have a function of creating digital musical tone data by using the sound data transmitted from the control core 111 and stored in the register 131 and read from the sound / light ROM 103 according to the sequence data and the parameter data. The sequence data includes time data indicating the output start timing and output order of a series of sounds, and the parameter data includes data that determines the pitch, volume, timbre, etc. of the sound at a predetermined timing. There is. These sequence data and parameter data are set as a pair of data corresponding to each other, and a series of sound output is possible by using these pair of sequence data and parameter data. Further, the period of sound output defined by a set of sequence data and parameter data is constant at a specific time regardless of the type of sequence data and parameter data, for example, one game round or one open / close execution. It is 2.1 sec, which is shorter than the mode. However, the present invention is not limited to this, and it may be shorter or longer than 2.1 sec. Further, the configuration may be a series of melody components, and in this case, the period of sound output determined by the sequence data and the parameter data varies depending on the type of the data.

The HWD 132 creates digital music sound data in order to reproduce pre-sampled recording data, and by creating sinusoidal data using the HWD recording data stored in advance in the sound / light ROM 103. , Enables playback of recorded data. The recorded data may be compressed data such as MP3 or uncompressed data. The SCM 133 does not create digital music sound data from recorded data for a predetermined time, but creates digital music sound data by combining rectangular wave data stored in advance in the sound light ROM 103 in chronological order, thereby creating electronic music sound data. It enables reproduction of sound (so-called pico-pico sound).

Here, the configuration of the register 131 used for creating digital musical tone data in the HWD 132 and SCM 133 will be described with reference to the explanatory diagram of FIG. The register 131 is provided with a sequence area 141, a parameter area 142, an HWD area 143, and an SCM area 144. The sequence data already described is written in the sequence area 141, and the parameter data already described is written in the parameter area 142.

The HWD 132 reads the recording data stored in the sound / light ROM 103 into the HWD area 143 by referring to the sequence data written in the sequence area 141 and the parameter data written in the parameter area 142, and records the recording data. By creating digital music sound data from the data, it is possible to output the recorded sound. The HWD area 143 is provided with the first CH area 143a to the 16th CH area 143p, and it is possible to create digital musical tone data based on different recording data in each CH area 143a to 143p. This makes it possible to simultaneously output sounds corresponding to a plurality of different recording data.

The SCM 133 reads the square wave data stored in the sound / light ROM 103 into the SCM area 144 by referring to the sequence data written in the sequence area 141 and the parameter data written in the parameter area 142, and the square wave data thereof. Electronic sound can be output by creating digital music sound data from wave data. The SCM area 144 is provided with the first CH area 144a to the 16th CH area 144p, and different digital musical tone data can be created in each of the CH areas 144a to 144p. This makes it possible to output a plurality of different electronic sounds at the same time.

The 1st CH area 143a to 16th CH area 143p of the HWD area 143 and the 1st CH area 144a to 16th CH area 144p of the SCM area 144 each have an area that can store two created digital musical tone data. It is provided, and while sound output control is being performed using digital musical tone data created in one of the memorable areas, digital corresponding to the next execution period with respect to the execution period of the sound output control. Musical tone data is created in the other memorable area. As a result, it is possible to continuously create the digital musical tone data required for the next sound output control execution period while outputting the sound, and it is possible to continuously output the sound.

Returning to the description of FIG. 8, the sound data processing unit 113 of the SOC 102 for sound and light has a function as a digital / analog converter, and the digital music data and the SCM area created in the HWD area 143 of the register 131. The digital music sound data created in 144 is converted into an analog sound signal and output to the amplifier circuit 104 formed on the voice emission control board 101. The amplifier circuit 104 amplifies the output level of the analog sound signal to a level corresponding to the volume set by the volume, and outputs the amplified sound signal to the speaker unit 54. As a result, a predetermined sound is output from the speaker unit 54. Further, when the digital musical tone data is simultaneously created in the plurality of CH areas 143a to 143p in the HWD area 143, the sound data processing unit 113 synthesizes the digital musical tone data and also in the SCM area 144. When digital musical tone data is simultaneously created in a plurality of CH areas 144a to 144p, the digital musical tone data are combined. When digital musical tone data is created in each of the HWD area 143 and the SCM area 144, the digital musical tone data are combined. When the synthesis is performed in this way, the digitally synthesized musical tone data after the synthesis is converted into an analog sound signal, amplified by the amplifier circuit 104 as described above, and then output to the speaker unit 54. This makes it possible to simultaneously output a plurality of different sounds from the speaker unit 54.

As described above, when the sound is output, the sound data, which is either the recorded data or the rectangular wave data, is read from the sound / light ROM 103 to the register 131, and the reading of the sound data is performed in the sequence area 141 of the register 131. It is performed by the data transfer unit 134 of the sound output core 112 based on the sequence data stored in.

More specifically, the sequence data SD is defined with pointer data set in accordance with the processing timing of the sound output core 112, which is specifically described by using the explanatory diagram of FIG. 10 showing an example of the sequence data. , The content data of the sound output and the content data of the data transfer are defined corresponding to each pointer data. The processing timing of the sound output core 112 is generated in synchronization with a clock signal periodically transmitted from a clock circuit (not shown) built in the sound output core 112. In this case, the period of the clock signal is shorter than the period of the clock signal of DMA123, and specifically, it is 10 MHz. When the processing timing of the sound output core 112 comes, each of the HWD 132, the SCM 133, and the data transfer unit 134 performs an operation corresponding to the sequence data and the parameter data.

The content data of the sound output in the sequence data SD is used in the HWD 132 and the SCM 133 to create digital musical tone data for each channel. In this case, the content data of the sound output is set corresponding to the pointer data, and the creation of the digital music sound data based on the content data of the sound output set corresponding to each pointer data is transferred to the register 131 in advance. It is performed using the sound data that has been created.

The content data of the data transfer in the sequence data SD is used in the data transfer unit 134 to specify the data read timing from the sound / light ROM 103, and is in the area of the sound / light ROM 103 in which the data to be read is stored. Used to identify address data. Data of data transfer Data so that there are a plurality of predetermined pointer data between the read timing of the sound data corresponding to one channel and the read timing of the sound data corresponding to the next channel. Read instruction data is set. Data for reading sound data of a data amount capable of outputting sound for a predetermined time is set in the data of one data read instruction, and the sound data is 1 for any of HWD132 and SCM133. It corresponds to one channel. Therefore, when a plurality of digital musical tone data are combined and the sound is output, data reading instructions for the number of the digital musical tone data are given. Further, the sound data read based on one data read instruction corresponds to the data that enables sound output over 700 μsec as the predetermined time in the corresponding channel. In this case, the HWD 132 and the SCM 133 each have 16 channels, and the time required to read 700 μsec of sound data for all of these 16 channels is shorter than 700 μsec. This makes it possible to create digital musical tone data that enables continuous output of sound for the next predetermined time for the predetermined time while outputting sound for the predetermined time.

Data is read from the common sound / light ROM 103 by each of the DMA 123 of the control core 111 and the data transfer unit 134 of the sound output core 112. The sound / light ROM 103 is configured to use a memory (that is, a non-volatile storage means) that does not require external power supply for storage retention as read-only. Specifically, although the NOR type flash memory is used as the sound / light ROM 103, a NAND type flash memory may be used. The sound and light ROM 103 stores various control programs and fixed value data used when executing processing according to the programs.

The data structure of the sound and light ROM 103 will be described in detail with reference to FIG. In the sound / light ROM 103, program data (1), program data (2), ..., Program data (L) for executing processing for effect control by the CPU 121 of the control core 111 are stored in advance. It is remembered. By using these program data, the CPU 121 executes main processing, timer interrupt processing, and the like, which will be described later. Further, the processing data (1), the processing data (2), ..., And the processing data (M) are stored in advance in the sound / light ROM 103. These processing data include a data table used to execute each effect, sequence data and parameter data to be provided to the sound output core 112. Further, the command data (1), the command data (2), ..., And the command data (N) are stored in advance in the sound / light ROM 103. These command data are used in the CPU 121 of the control core 111 to instruct the display control device 90 of the effect content.

In the sound / light ROM 103, in addition to the data used for executing the processing by the CPU 121 of the control core 111 as described above, the light emission data (1), the light emission data (2), ..., The light emission data (P) is stored, and sound data (1), sound data (2), ..., Sound data (Q) are stored. Information on the type of light emitting unit to be lit, the lighting period, and the lighting order of the display light emitting units 53 is set in each light emitting data during a predetermined effect period, and the contents of these light emitting patterns are each set. It differs depending on the type of emission data. Each light emission data stored in the sound light ROM 103 has a different light emission control period, and the content of the light emission pattern is different. Further, each sound data includes a recorded data composed of a sine wave, and also includes a square wave data used for outputting an electronic sound.

As shown in FIG. 8, the sound / light ROM 103 is electrically connected to the memory controller 114 of the sound / light SOC 102 via the address bus SL1 and the data bus SL2. The memory controller 114 is electrically connected to the control core 111 via the address bus SL3 and the data bus SL4, and is also electrically connected to the sound output core 112 via the address bus SL5 and the data bus SL6. ..

The address data to be read-instructed is transmitted from the DMA 123 of the control core 111 to the memory controller 114 via the address bus SL3. The memory controller 114 includes a control side address buffer 114a for storing the address data received from the DMA 123, and when the address data is newly received from the DMA 123 in a situation where the unprocessed address data is not stored, the memory controller 114 includes the control side address buffer 114a. The address data is stored in the control side address buffer 114a. At this time, a normal reception signal indicating that the address data has been normally received is transmitted from the memory controller 114 to the DMA 123 via the data bus SL4, whereby it is specified that the address data has been normally received in the DMA 123. To. On the other hand, when the unprocessed address data is newly received from the DMA 123 while the unprocessed address data is stored in the control side address buffer 114a, the address data is not stored in the control side address buffer 114a. In this case, since the normal reception signal is not transmitted to the DMA 123, it is specified that the same address data needs to be transmitted again in the DMA 123.

When corresponding to the address data transmitted from the DMA 123, the memory controller 114 transmits the address data via the address bus SL1 to the sound / optical ROM 103, and the data corresponding to the address data is sounded via the data bus SL2. Received from ROM 103. Then, the received data is transmitted to the RAM 122 of the control core 111 or the internal register of the CPU 121 via the data bus SL4.

The address data to be read-instructed is transmitted to the memory controller 114 from the data transfer unit 134 of the sound output core 112 via the address bus SL5. The memory controller 114 includes a sound output side address buffer 114b for storing the address data received from the data transfer unit 134, and is newly addressed from the data transfer unit 134 in a situation where the unprocessed address data is not stored. When the data is received, the address data is stored in the sound output side address buffer 114b. At this time, a normal reception signal indicating that the address data has been normally received is transmitted from the memory controller 114 to the data transfer unit 134 via the data bus SL6, whereby the address data is normally received by the data transfer unit 134. It is identified that it was done. On the other hand, when the unprocessed address data is newly received from the data transfer unit 134 in the situation where the unprocessed address data is stored in the sound output side address buffer 114b, the address data is not stored in the sound output side address buffer 114b. In this case, since the normal reception signal is not transmitted to the data transfer unit 134, it is specified that the data transfer unit 134 needs to transmit the same address data again.

When corresponding to the address data transmitted from the data transfer unit 134, the memory controller 114 transmits the address data to the sound and light ROM 103 via the address bus SL1, and the data corresponding to the address data via the data bus SL2. Is received from the sound / light ROM 103. Then, the received data is transmitted to the register 131 of the sound output core 112 via the data bus SL6.

A clock circuit is built in the memory controller 114, and processing in the memory controller 114 is performed in synchronization with a clock signal periodically transmitted from the clock circuit. In this case, the period of the clock signal is shorter than the period of the clock signal of the DMA 123 and the period of the clock signal of the sound output core 112, specifically 15 MHz.

<About various processes executed by SOC102 for sound and light>
Next, various processes executed by the sound / light SOC 102 will be described. First, the process executed by the CPU 121 of the control core 111 will be described. The CPU 121 executes a main process that is started at the timing when the supply of operating power to the CPU 121 is started, and a timer interrupt process that is started by interrupting the main process periodically.

<Main processing of CPU 121>
FIG. 12 is a flowchart showing the main process. First, in step S301, the initialization process of the RAM 122 is executed. Specifically, each area of the RAM 122 is cleared to "0". After that, in step S302, a data read instruction at the time of power-up is given to the DMA 123. The program for executing the processes of steps S301 and S302 is stored in advance in a boot buffer (not shown) provided in the control core 111, and the CPU 121 is the boot buffer when the supply of operating power is started. The process of step S301 and step S302 is executed by executing the process corresponding to the program stored in. Further, the process of step S303, which will be described later, is also performed according to the program stored in the boot buffer.

When the DMA 123 receives a data read instruction at the time of starting the power supply, the DMA 123 transmits the corresponding address data to the memory controller 114. Upon receiving the address data, the memory controller 114 includes program data (1), program data (2), ..., Program data (L), which are stored in advance in the sound / light ROM 103. Read processing data (1), processing data (2), ..., Processing data (M), and command data (1), command data (2), ..., Command data (N). , Transfer to RAM 122 of control core 111. As a result, the entire program data for executing the processing after step S304 and the timer interrupt processing in the CPU 121 is written to the RAM 122. Therefore, when the CPU 121 executes the processing after step S304 and the timer interrupt processing, the program data written in the RAM 122 is used. Further, except for the light emission data, all the data necessary for executing these processes are also written in advance in the RAM 122.

After that, in step S303, the CPU 121 determines whether or not the data read completion signal has been received from the DMA 123, thereby determining whether or not the data read corresponding to the data read instruction at the time of turning on the power supply has been completed. judge. If the reading of the data is not completed, the process waits in step S303.

Here, with reference to the time chart of FIG. 13, regarding the relationship between the period in which the power-on wait process is executed in the MPU 62 of the main control device 60 and the period in which the data is read out at the time of power-up in the control core 111. explain. FIG. 13A shows a period during which the power-on wait process is executed in the MPU 62 of the main control device 60, and FIG. 13B shows the timing at which the data read instruction at the time of power-up is executed in the CPU 121 of the control core 111. 13 (c) shows the period required for the data corresponding to the data read instruction to be read from the sound / light ROM 103.

When the supply of the operating power to the MPU 62 of the main control device 60 is started at the timing of t1, the power-on wait process is executed in the MPU 62 as shown in FIG. 13 (a). As a result, as described above, the MPU 62 of the main control device 60 waits without proceeding to the next process until the waiting time (specifically, 1 sec) elapses.

Immediately after the supply of the operating power to the MPU 62 of the main control device 60 is started, the supply of the operating power to the control core 111 is started, and at the timing of t2, as shown in FIG. 13 (b), the control core 111 The CPU 121 gives an instruction to read data when the power is turned on. As a result, as shown in FIG. 13C, the data corresponding to the data read instruction is transferred from the sound / light ROM 103 to the RAM 122 of the control core 111. Then, the transfer of such data is completed at the timing of t3, which is a timing before the timing of t4, which is the timing at which the power-on wait processing ends in the MPU 62 of the main control device 60.

With the above configuration, all of the program data, processing data, and command data required for the CPU 121 of the control core 111 (using the period during which the power-on wait processing is being executed in the MPU 62 of the main control device 60) ( Hereinafter, these data can be referred to as a series of program-compatible data). As a result, when it is time for the command to be transmitted from the MPU 62 of the main control device 60, the CPU 121 of the control core 111 executes all the processing by using the data written in the RAM 122 of the control core 111. Is possible. It takes about 8 msec at the longest to read a series of data corresponding to the program.

Returning to the description of the main process (FIG. 12), when the data reading is completed (step S303: YES), the interrupt permission is set in step S304. As a result, the periodic interrupt of the timer interrupt process (FIG. 17) is permitted. After that, in step S305, it is determined whether or not the normality determination is being executed by determining whether or not "1" is set in the executing flag of the normality determination provided in the RAM 122. do.

The normality determination is a determination for identifying whether or not the series of program-corresponding data read into the RAM 122 of the control core 111 at the time of power-up is abnormal data due to electrical noise or the like. .. At the time of the normality determination, the series of data corresponding to the program is read again from the ROM 103 for sound and light to the RAM 122 of the control core 111, and the read series of data corresponding to the program and the series corresponding to the program already read to the RAM 122 are supported. It is specified whether or not the series of data matches. That is, as shown in the explanatory diagrams of FIGS. 14A and 14B, the RAM 122 of the control core 111 has a program-compatible area 122a as a dedicated area for reading a series of program-compatible data when the power is turned on. In addition to this, a general-purpose area 122b for temporarily storing and holding data for light emission control and other processing is provided. As shown in FIG. 14A, a series of program-corresponding data is read out in the program-corresponding area 122a when the power supply is turned on. On the other hand, when the normality determination is started, as shown in FIG. 14 (b), the program corresponds to the general-purpose area 122b in the state where the program corresponding series of data has already been read out to the program corresponding area 122a. A series of data is newly read from the sound / light ROM 103. Then, it is determined whether or not all the corresponding bits of the series of data corresponding to these programs match.

Specifically, regarding the processing configuration for performing such a normality determination, if "1" is not set in the executing flag of the normality determination (step S305: NO), is it the start timing of the normality determination in step S306? Judge whether or not. The normal determination start timing occurs when 32 msec has elapsed from the timing at which the affirmative determination was made in step S303, or when 32 msec has elapsed from the timing at which the affirmative determination was made last time in step S306.

When it is the start timing of the normality determination, a data read instruction for normality determination is given to the DMA 123 in step S307. Upon receiving a data read instruction for normality determination, the DMA 123 transmits the corresponding address data to the memory controller 114, whereby the series of data corresponding to the program to the general-purpose area 122b of the RAM 122 is transmitted to the memory controller 114. Start reading. After that, in step S308, "1" is set in the executing flag of the normality determination in RAM 122, and then the process returns to step S304. When "1" is set in the execution flag of the normality determination, the normality determination process is executed in step S309. When the normality determination process is completed for all the series of data corresponding to the program having a data capacity of 512 bytes, the execution flag of the normality determination is cleared to "0".

<Process for determining normality of CPU 121>
FIG. 15 is a flowchart showing a normality determination process.

When the reading of the series of data corresponding to the program to the general-purpose area 122b is completed (step S401: YES), the data collation process is executed in step S402. In the data collation process, 4-byte data corresponding to each other in the program-corresponding series data stored in the program-corresponding area 122a of the RAM 122 and the program-corresponding series data stored in the general-purpose area 122b are read from each. By executing logical calculation processing such as XOR processing, it is determined whether or not the 4-byte data match.

If all the bits of the 4-byte data match (step S403: YES), the normality determination process is terminated as it is. That is, in the normal determination, the data collation process is not executed at once for the entire series of data corresponding to the program consisting of 512 bytes, but the data collation process is executed in units of 4 bytes which are the collation target bytes. Here, since the interrupt of the timer interrupt process (FIG. 17) is not prohibited when the data collation process is started, the timer interrupt process (FIG. 17) occurs even during the execution of the data collation process.

If even some of the 4-byte data do not match (step S403: NO), the data rewriting process shown in steps S404 to S407 is executed. Specifically, the execution of the timer interrupt process (FIG. 17) is prohibited in step S404, and the data rewriting instruction is given to the DMA 123 in step S405. Upon receiving a data rewriting instruction, the DMA 123 transmits the corresponding address data to the memory controller 114, so that the memory controller 114 reads out a series of program-corresponding data to the program-corresponding area 122a of the RAM 122. Let's get started. In this case, the newly read program-corresponding series of data is overwritten in the program-corresponding area 122a. The program for executing the process is excluded from the overwrite target so that the process of step S406 can be executed even during the overwriting, and the excluded program is executed when the process of step S407 is executed. It will be cleared.

When the rewriting of the program-corresponding series of data for the program-corresponding area 122a is completed (step S406: YES), the execution of the timer interrupt process (FIG. 17) is permitted in step S407, and then the normality determination process ends.

A state in which the normality determination is executed will be described with reference to the time chart of FIG. FIG. 16A shows the start timing of the normality determination, FIG. 16B shows the period during which the data is read out to the general-purpose area 122b, and FIG. 16C shows the normality determination. The period is shown, and FIG. 16D shows the period during which the overwriting to the program corresponding area 122a is executed.

At the timing of t1, the normality determination start timing is set as shown in FIG. 16A, and as shown in FIG. 16B, reading of a series of program-corresponding data for the general-purpose area 122b of the RAM 122 is started. .. After that, when the reading of the series of data corresponding to the program is completed at the timing of t2, the normality determination is started as shown in FIG. 16 (c). Then, the normality determination is completed at the timing of t3 without causing a data mismatch. In this case, as shown in FIG. 16D, overwriting of the program corresponding area 122a does not occur.

On the other hand, when the data mismatch occurs as shown in the example of the timing of t4 to t7, it is the timing when the mismatch is discovered as shown in FIGS. 16 (c) and 16 (d). At the timing of t6, overwriting of a series of data to the program corresponding area 122a is started. As a result, in a configuration in which various processes are executed by the CPU 121 of the control core 111 using the program-corresponding series of data read out to the RAM 122 when the power is turned on, the series of data remains in an abnormal state. It is possible to prevent the various processes in the CPU 121 from being continued.

In addition, in the normal judgment, the collation process is not executed at once for the entire series of data corresponding to the program, but the collation process is executed in units of 4 bytes, which is the collation target byte. Therefore, when a data abnormality is found, the collation process is executed. It is possible to start rewriting a series of data corresponding to the program at the timing when the collation process in units of 4 bytes is completed. As a result, when an abnormality occurs in the series of data corresponding to the program, the rewriting can be started at an early stage.

<Timer interrupt processing of CPU 121>
Next, a timer interrupt process that is periodically (for example, a 2 msec cycle) executed by the CPU 121 of the control core 111 will be described with reference to the flowchart of FIG.

First, in step S501, it is determined whether or not a new command is received from the MPU 62 of the main control device 60. This command includes the combination of the variable command and the type command, the final stop command, the opening command, the opening command, the closing command, and the ending command, which have already been described.

The RAM 122 of the control core 111 is provided with a ring buffer for storing and reading the command received from the MPU 62 of the main control device 60, and the command received from the MPU 62 of the main control device 60 is the ring buffer. It is sequentially stored in and is read out sequentially according to the stored order. In this case, the command storage process in the ring buffer is performed in the command receiving circuit provided separately from the CPU 121 in the control core 111. The command receiving circuit is activated when a new command is received from the MPU 62 of the main control device 60 regardless of whether or not the interrupt prohibition setting is set in the CPU 121 of the control core 111, and the newly received command is activated. In the ring buffer. By storing commands regardless of whether interrupt prohibition is set in this way, for example, the occurrence of a data error is identified in the above-mentioned normal judgment, and a series of command-compatible data is rewritten. Even in the situation where the above is being performed, the command received from the MPU 62 of the main control device 60 can be stored and held in the RAM 122 without invalidating the command. Then, after the rewriting of the series of data is completed, the CPU 121 of the control core 111 can execute the process corresponding to the command.

When an unprocessed command is stored in the ring buffer of the RAM 122 (step S501: YES), a data table for enabling the effect or notification corresponding to the command to be read this time can be executed in the RAM 122 in step S502. It is read from the program corresponding area 122a to the general-purpose area 122b and set as an execution target. After that, in step S503, the display command corresponding to the data table read this time is transmitted to the display control device 90. As a result, the symbol display device 41 is displayed and controlled by the display control device 90 so that the display effect corresponding to the data table is performed.

When a negative determination is made in step S501, or when the process of step S503 is executed, the timing for instructing to read the light emission data is obtained by referring to the data table set as the execution target in the RAM 122 in step S504. It is determined whether or not it is. When it is the timing for instructing to read the light emission data, the DMA 123 is instructed to read the light emission data in step S505. Upon receiving the instruction to read the light emission data, the DMA 123 transmits the corresponding address data to the memory controller 114, thereby causing the memory controller 114 to start reading the light emission data into the general-purpose area 122b of the RAM 122.

When a negative determination is made in step S504, or when the process of step S505 is executed, the data table set as the execution target in the RAM 122 is referred to in step S506 at the execution timing of the light emission control. Determine if it exists. When it is the execution timing of the light emission control, the light emission control of the display light emitting unit 53 is performed by using the light emission data already read in the general-purpose area 122b of the RAM 122 in step S507.

When a negative determination is made in step S506, or when the process of step S507 is executed, the instruction timing of sound output control is instructed by referring to the data table set as the execution target in the RAM 122 in step S508. It is determined whether or not it is. When it is the instruction timing of the sound output control, in step S509, the sequence data and the parameter data corresponding to the instruction of the sound output control this time are read from the program corresponding area 122a of the RAM 122, and the read sequence data and the parameter data are read out. Is written to the register 131 of the sound output core 112.

<DMA123>
Next, a processing configuration for reading data from the sound / light ROM 103 will be described. First, the flow of processing for instructing the DMA 123 of the control core 111 to read data will be described with reference to the flowchart of FIG. The DMA 123 repeatedly executes the following processing flow in a relatively short cycle. Specifically, it is repeatedly executed in a cycle of 3 μsec, but the specific cycle is arbitrary.

When the reading of the data for the reading instruction received from the CPU 121 of the control core 111 is not completed, "1" is set in the reading instruction flag provided in the DMA 123. Then, when "1" is set in the read instruction flag (step S601: YES), the address data is sent to the memory controller 114 on condition that the address data to be transmitted exists (step S602: YES). Transmit (step S603). In this case, the address data is data corresponding to the reading of 1-byte data, which is the smallest unit for reading data.

Here, when a read instruction is received from the CPU 121 of the control core 111, the data to be read for one read instruction is 2 bytes or more. Further, the data group to be read for one read instruction is continuously set on the address of the sound / light ROM 103. When the CPU 121 of the control core 111 gives an instruction to read data to the DMA 123, the CPU 121 of the control core 111 transmits the data of the start address and the data of the end address of the data group to be read to the DMA 123. When the DMA 123 receives a read instruction from the CPU 121 of the control core 111, the DMA 123 reads out the data group included in the data of the end address from the data of the start address. A read instruction is given in 1-byte units of the included multi-byte data.

When the memory controller 114 is subjected to the transmission processing of the address data corresponding to the 1-byte data, but the address data is received by the memory controller 114, the normal reception signal is sent from the memory controller 114 to the DMA 123. Will be sent. When the DMA 123 receives the normal reception signal (step S604: YES), the DMA 123 reads the data to the memory controller 114 on condition that the address data transmitted this time does not correspond to the end address (step S605: YES). The address data for giving an instruction is updated to the address data corresponding to the next 1 byte (step S606). As a result, when the DMA 123 subsequently gives a read instruction to the memory controller 114, the updated address data is transmitted to the memory controller 114. When the address data transmitted this time is the data corresponding to the end address, it means that the transmission of the address data corresponding to the current read instruction from the CPU 121 of the control core 111 is completed, so that the DMA 123 Does not transmit new address data to the memory controller 114 until a new read instruction is issued from the CPU 121.

When the DMA 123 receives 1 byte of data from the memory controller 114 (step S607: YES), the DMA 123 transmits the received 1 byte of data to the RAM 122 of the control core 111 or the internal register of the CPU 121 (step S608). Then, when the reading of all the data instructed by the CPU 121 of the control core 111 is completed (step S609: YES), the DMA 123 transmits a signal indicating the completion of reading to the CPU 121 of the control core 111 (step S610). .. As a result, it is specified that the reading of the light emission data targeted for the read instruction is completed in the CPU 121 of the control core 111, and the light emission control using the light emission data is executed. Further, when the DMA 123 transmits a signal indicating the completion of reading to the CPU 121 of the control core 111, the DMA 123 clears the read instruction flag by "0" (step S611).

Here, referring to the time chart of FIG. 19, the state in which the data is read from the sound / light ROM 103 with respect to the transmission of the address data from the DMA 123 will be described. 19 (a) shows the transmission timing of the address data from the DMA 123, FIG. 19 (b) shows the period in which the unprocessed address data is stored in the control side address buffer 114a, and FIG. 19 (c) shows the control. The period during which data is transmitted toward the core 111 is shown.

As shown in FIG. 19A, when a read instruction is given to the DMA 123 from the CPU 121 of the control core 111, the DMA 123 is a memory controller 114 until the read of the data group corresponding to the read instruction is completed. Send address data to to on a regular basis. Specifically, the address data is transmitted at the timing of t1, the timing of t3, the timing of t5, the timing of t7, the timing of t9, the timing of t11, the timing of t13, and the timing of t15.

The address data transmitted at the timing of t1, the timing of t3, the timing of t7, the timing of t11, and the timing of t15 are not processed in the control side address buffer 114a at each of these timings, as shown in FIG. 19B. Since the address data is not stored, it is stored in the control side address buffer 114a. Then, when the unprocessed address data exists in the situation where the data is not read from the sound / light ROM 103, the data is read from the sound / light ROM 103 (timing of t2 to t4). , T6 to t8 timing and t10 to t12 timing).

On the other hand, as for the address data transmitted at the timing of t5, the timing of t9, and the timing of t13, unprocessed address data is stored in the control side address buffer 114a at each of these timings, as shown in FIG. 19B. Therefore, the transmission of the address data is invalidated without being stored in the control side address buffer 114a. The invalidated address data is transmitted to the memory controller 114 at each transmission timing of the address data until it is stored in the control side address buffer 114a.

<Data transfer unit 134>
Next, with reference to the flowchart of FIG. 20, the flow of processing for instructing the data transfer unit 134 of the sound output core 112 to read data will be described. The data transfer unit 134 repeatedly executes the following processing flow at a cycle shorter than the repetition cycle of a series of processes in the DMA 123. Specifically, it is repeatedly executed in a cycle of 2 μsec, but the specific cycle is arbitrary.

When the reading of the data for the reading instruction set in the sequence data is not completed, "1" is set in the reading execution flag provided in the data transfer unit 134. When "1" is not set in the read execution flag (step S701: NO), as the content data of the data transfer corresponding to the current pointer data in the sequence data read in the register 131 of the sound output core 112. On condition that the data corresponding to the read instruction is set (step S702: YES), the address data of the data group to be read is read to the internal register of the data transfer unit 134 (step S703). When the address data is read, the read execution flag is set to "1" (step S704).

Here, the data to be read is 2 bytes or more for one read instruction in the sequence data. Further, the data group to be read for one read instruction is continuously set on the address of the sound / light ROM 103. When the read instruction data is set in the sequence data, the data includes the data of the start address and the data of the end address of the data group to be read. When the read instruction data is set in the sequence data, the data transfer unit 134 reads out the data group included in the data of the end address from the data of the start address, but the data transfer unit 134 reads the data group included in the data of the end address. Gives a read instruction in 1-byte units among the plurality of bytes of data included in the data group.

When "1" is set in the read execution flag (step S701: YES), the address data is transmitted to the memory controller 114 on condition that the address data to be transmitted exists (step S705: YES). (Step S706). In this case, the address data is data corresponding to reading of 1-byte data.

When the memory controller 114 is subjected to the transmission processing of the address data corresponding to the 1-byte data, but the address data is received by the memory controller 114, the normal reception signal is transferred from the memory controller 114. It is transmitted to the unit 134. When the data transfer unit 134 receives the normal reception signal (step S707: YES), the memory controller 114 is provided with the condition that the address data transmitted this time is not the data corresponding to the end address (step S708: YES). The address data for giving a read instruction is updated to the address data corresponding to the next 1 byte (step S709). As a result, when the data transfer unit 134 subsequently gives a read instruction to the memory controller 114, the updated address data is transmitted to the memory controller 114. If the address data transmitted this time is the data corresponding to the above end address, it means that the transmission of the address data corresponding to the current read instruction in the sequence data is completed, so that the sequence data is new. No new address data is transmitted to the memory controller 114 until a read instruction is issued.

When the data transfer unit 134 receives 1-byte data from the memory controller 114 (step S710: YES), the data transfer unit 134 receives the received 1-byte data for CH corresponding to the current read instruction in the register 131 of the sound output core 112. Write to the area (step S711). Then, when the reading of all the data instructed in the sequence data is completed (step S712: YES), the data transfer unit 134 reads out to the side corresponding to the current reading instruction among the HWD 132 and the SCM 133 of the sound output core 112. A signal indicating completion is transmitted (step S713). As a result, it is specified that the reading of the sound data targeted for the reading instruction is completed on the side of the HWD 132 and the SCM 133 corresponding to the reading instruction this time, and the sound output control using the sound data is executed. Further, when the data transfer unit 134 transmits a signal indicating the completion of reading, the read execution flag is cleared to "0" (step S714).

As described above, when the data is read from the sound and light ROM 103 for the transmission of the address data from the data transfer unit 134, and when the data is read from the sound and light ROM 103 for the transmission of the address data from the DMA 123. Similarly, the data transfer unit 134 periodically transmits the address data to the memory controller 114 until the reading of the data group corresponding to the reading instruction set in the sequence data is completed. When the address data is transmitted and the unprocessed address data is not stored in the sound output side address buffer 114b, the address data is stored in the sound output side address buffer 114b and is stored in the address data. Reading of the corresponding data is started. On the other hand, when the address data is transmitted and the unprocessed address data is stored in the sound output side address buffer 114b, the transmission of the address data is invalidated. The invalidated address data is transmitted to the memory controller 114 every time the transmission timing of the address data comes, until it is stored in the sound output side address buffer 114b.

<Memory controller 114>
Next, the flow of processing for reading data in the memory controller 114 will be described with reference to the flowchart of FIG. 21. The memory controller 114 repeatedly executes the following processing flow in a cycle shorter than the repeating cycle of the series of processing in the DMA 123 and the data transfer unit 134. Specifically, it is repeatedly executed in a cycle of 1 μsec, but the specific cycle is arbitrary.

When the memory controller 114 receives the address data from the DMA 123 (step S801 and step S802: YES), the condition is that the unprocessed address data is not stored in the control side address buffer 114a (step S803: NO). ), The received address data is stored in the control side address buffer 114a (step S804). Further, at this time, a normal reception signal indicating that the address data has been received is transmitted to the DMA 123 (step S805).

When the memory controller 114 receives the address data from the data transfer unit 134 (step S801: YES, step S802: NO), it is a condition that the unprocessed address data is not stored in the sound output side address buffer 114b. (Step S806: NO), the received address data is stored in the sound output side address buffer 114b (step S807). Further, at this time, a normal reception signal indicating that the address data has been received is transmitted to the data transfer unit 134 (step S808).

When the address data is received as described above, the memory controller 114 reads the data corresponding to the address data from the sound / light ROM 103. Specifically, when the data is not being read from the sound / light ROM 103 (step S809: NO), the condition is that the unprocessed address data is stored in the sound output side address buffer 114b (step S810: NO). YES), by transmitting the address data to the sound / light ROM 103, reading of the data corresponding to the address data is started (step S811). As a result, reading of 1-byte data corresponding to the address data is started. When the reading of the data is started, the data is set so that the memory controller 114 can specify that the address data stored in the sound output side address buffer 114b has been processed.

On the other hand, in a situation where the unprocessed address data is not stored in the sound output side address buffer 114b (step S810: NO), the condition is that the unprocessed address data is stored in the control side address buffer 114a (step). S812: YES), by transmitting the address data to the sound / light ROM 103, reading of 1-byte data corresponding to the address data is started (step S813). As a result, reading of 1-byte data corresponding to the address data is started. When the data reading is started, the data is set so that the memory controller 114 can specify that the address data stored in the control side address buffer 114a has been processed.

When the memory controller 114 starts reading the 1-byte data (step S809: YES), the memory controller 114 executes the read completion process on condition that the reading of the 1-byte data is completed (step S814: YES). Step S815). By executing the read completion process, the 1-byte data read this time is transferred to the side of the control core 111 (that is, DMA123) and the sound output core 112 (that is, the data transfer unit 134) that is the target of reading the data. Will be sent.

Next, with reference to the time chart of FIG. 22, a data reading mode will be described when the period in which the reading instruction is given from the DMA 123 and the period in which the reading instruction is given from the data transfer unit 134 overlap. 22 (a) shows a period during which address data is periodically transmitted from DMA 123, FIG. 22 (b) shows a period during which address data is periodically transmitted from the data transfer unit 134, and FIG. 22 (c) shows. Indicates a period during which the data read from the sound and light ROM 103 is transferred to the control core 111, and FIG. 22 (d) shows a period during which the data read from the sound and light ROM 103 is transferred to the sound output core 112. show.

When a read instruction is generated from the CPU 121 of the control core 111 to the DMA 123 at the timing of t1, periodic transmission of address data from the DMA 123 to the memory controller 114 is started as shown in FIG. 22 (a). In this case, since the data is not read from the sound / light ROM 103, the reading of 1-byte data from the sound / light ROM 103 to the control core 111 is started as shown in FIG. 22 (c). Will be done.

FIG. 22B shows that a read instruction is given to the sequence data read to the register 131 of the sound output core 112 at the timing of t2 while the 1-byte data is being read. As shown in the above, periodic transmission of address data from the data transfer unit 134 of the sound output core 112 to the memory controller 114 is started. However, at the timing of t2, since the data is being read out to the control core 111, the data reading for the transmission of the address data from the data transfer unit 134 is not started. After that, at the timing of t3, as shown in FIG. 22 (c), the reading of the data to the control core 111 started at the timing of t1 is completed.

By the timing of t3, the address data is newly transmitted from the DMA 123 to the memory controller 114, and the address data is transmitted from the data transfer unit 134 to the memory controller 114. Therefore, unprocessed address data is stored in both the control side address buffer 114a and the sound output side address buffer 114b of the memory controller 114. In this case, since the memory controller 114 processes the read instruction from the data transfer unit 134 with priority over the read instruction from the DMA 123, from the sound / light ROM 103 as shown in FIG. 22 (d) at the timing of t4. Reading of 1-byte data to the sound output core 112 is started. Further, as shown in FIG. 22B, since the period in which the address data is periodically transmitted from the data transfer unit 134 continues until the timing of t8, the timing of t5, the timing of t6, the timing of t7, and the timing of t8 At each of the timings, reading of 1-byte data from the sound / light ROM 103 to the sound output core 112 is started.

When the reading of the data started at the timing of t8 is completed, the unprocessed address data is not stored in the sound output side address buffer 114b, and the unprocessed address data is stored in the control side address buffer 114a. It will be in a state of being. Therefore, at the timing of t9, reading of 1-byte data from the sound / light ROM 103 to the control core 111 is started as shown in FIG. 22 (c). Further, as shown in FIG. 22A, since the period in which the address data is periodically transmitted from the DMA 123 continues until the timing of t11, the control core from the sound / optical ROM 103 at each of the timing of t10 and the timing of t11. Reading of 1-byte data to 111 is started.

Next, in a configuration in which the sound output core 112 is prioritized over the control core 111 for data reading, a device for shortening the time for waiting for data reading in the control core 111 will be described.

As described above, each of the HWD 132 and SCM 133 of the sound output core 112 has 16 channels, and it is possible to output sound corresponding to the digitally synthesized musical tone data which is the result of synthesizing the digital musical tone data created in each channel. Is. However, the sound for 16 channels may not always be synthesized, and only the sound for 1 channel may be output, or it may be a part of 16 channels such as 5 channels or 8 channels and may be plural. In some cases, the combined sound of the channels is output.

When the sound data is read out, the sound data for the number of channels to be output is read out. Further, since the digital music sound data created by each of the HWD 132 and the SCM 133 may be combined to output the sound, in this case, the sound data for the number of channels to be output in the HWD 132 and the output target in the SCM 133. The sound data for the number of channels to be used is read out by the output timing of the synthesized sound.

The sound data read instruction is defined in the sequence data, but the sound data read for one read instruction defined in the sequence data corresponds to one channel and is further predetermined in that channel. It is set to enable sound output for an hour (700 μsec). The predetermined time is the time obtained by summing the sum of the maximum number of channels of HWD132 and the maximum number of channels of SCM133 to the maximum time assumed as the time required to read one sound data having a multi-byte data structure. Is also set as a long time. The amount of sound data stored in advance in the sound / light ROM 103 is set so as to enable sound output for a predetermined time. Therefore, even if the total number of sound channels output at one time is "32" for the HWD 132 and SCM 133, or even if the number is smaller than that, the sound data that enables sound output for a predetermined time is possible. Is read out.

In the configuration in which the sound data that enables sound output for a predetermined time is read out in this way, as described above, the first CH area 143a to the 16th CH area 143p of the HWD area 143 in the register 131 of the sound output core 112. Each of the 1st CH area 144a to the 16th CH area 144p of the SCM area 144 has an area capable of storing two created digital musical sound data. Therefore, when the sound output from the speaker unit 54 is continuously performed, the sound output corresponding to the unit sound output period for a predetermined time corresponds to the next predetermined time unit sound output period. Sound data is read to enable sound output, and when the unit sound output period on the front side ends, the unit sound output period on the rear side is started using the read sound data. It becomes. That is, regardless of the number of sound channels output at one time, the unit reading period for reading the sound data for the predetermined time is repeated.

FIG. 23 is an explanatory diagram for explaining a unit read period when sound data for the maximum channel is read in each of the HWD 132 and the SCM 133. 23 (a) and 23 (b) are explanatory views for explaining the reading mode of sound data for HWD 132, and FIGS. 23 (c) and 23 (d) are reading modes of sound data for SCM 133. It is explanatory drawing for demonstrating.

Since the unit read period for reading the sound data for a predetermined time coincides with the unit sound output period for the predetermined time, "unit read period = predetermined time". Since the sound data for the HWD 132 and the sound data for the SCM 133 are read in the unit read period, half of the unit read period can be used to read the sound data for the HWD 132, and the unit read period The other half of the period is available to read the sound data for SCM133.

As described above, the unit read period is set as a time longer than the time required to read the sound data for the maximum channel. Therefore, as shown in FIG. 23A, the period T1 for accessing the sound light ROM 103 for reading the sound data for 16 channels for the HWD 132 is shorter than the half period of the unit read period, and is for sound light. T2 will occur during the period when the ROM 103 is not accessed. Similarly, as shown in FIG. 23 (c), the period T3 during which the sound light ROM 103 is accessed to read the sound data for 16 channels for the SCM 133 is shorter than the half period of the unit read period, and the sound light. T4 will occur during the period when the ROM 103 is not being accessed.

Here, when the period for reading the sound data for the HWD 132 and the period for reading the sound data for the SCM 133 are aggregated in the unit read period, the memory controller 114 issues a read instruction from the sound output core 112 as described above. Since the priority is given to the read instruction from the control core 111, a situation occurs in which the period of waiting for data read in the control core 111 becomes long. On the other hand, as described above, the unit read period is divided into a period T1 for reading the sound data for the HWD 132 and a period T3 for reading the sound data for the SCM 133, and no access is made between the respective read periods T1 and T3. Periods T2 and T4 exist. As a result, the period for waiting for data reading in the control core 111 is shortened.

In the above configuration, in the pachinko machine 10, as shown in FIGS. 23 (b) and 23 (d), the period T1 for reading the sound data for the HWD 132 and the period T3 for reading the sound data for the SCM 133 are divided for each channel. The channel unit periods T5 and T7 are set so as to sandwich the non-access unit periods T6 and T8 in between.

Specifically, since the data capacity of the sound data for a predetermined time is the same on the HWD132 side, the channel unit period T5 is constant. Therefore, the period in which the period T1 for reading the sound data for the HWD 132 is divided into 16 equal parts corresponds to the channel unit period T5. A non-access unit period T6 is set between each channel unit period T5, and the non-access unit period T6 is constant.

On the other hand, on the SCM133 side, the data capacity of the sound data for a predetermined time differs depending on the type of sound data, so that the channel unit period T7 is not constant. Therefore, the channel unit period T7 varies depending on the type of sound data. On the other hand, the non-access unit period T8 set during each channel unit period T7 is all constant.

Each channel unit period T5, T7 and each non-access unit period T6, T8 are defined at the design stage of the pachinko machine 10. Then, the content of the data transfer in the sequence data is set so that each of the defined unit periods T5 to T8 occurs. Further, the number of channel unit periods varies according to the number of channels included in the unit read period, and the length of the non-access unit period varies accordingly. Specifically, the smaller the number of channels, the longer the non-access unit period.

According to the present embodiment described in detail above, the following excellent effects are obtained.

In a configuration in which the program data and control data used in the control core 111 and the control data used in the sound output core 112 are aggregated and stored in the sound light ROM 103, the sound light ROM 103 is stored. When the memory controller 114 that manages the reading of data from the control core 111 and the sound output core 112 receives the address data, the memory controller 114 receives the address data from the sound output core 112 regardless of the reception order. Priority is given to the data read execution target over the address data received from the control core 111. As a result, it is possible to suppress the delay in reading the sound data, and it is possible to suitably output the sound. On the other hand, since it is basically light emission data that can occur in the control core 111 in duplicate with the reading of sound data, even if the reading of the light emission data is slightly delayed, it is slightly delayed in the light emission timing of the display light emitting unit 53. It is harder to give a sense of discomfort to the player than to shift the sound output.

Even when the DMA 123 of the control core 111 receives a read instruction of a data group consisting of a plurality of bytes from the CPU 121 of the control core 111, the DMA 123 of the control core 111 is instructed to read 1 byte of data by transmitting the address data once to the memory controller 114. I do. As a result, when the address data is transmitted from the sound output core 112 to the memory controller 114 even during the reading of the data group consisting of a plurality of bytes, the data corresponding to the address data is read. Is possible.

Even when the data transfer unit 134 of the sound output core 112 receives an instruction to read a data group consisting of a plurality of bytes in the sequence data, the data transfer unit 134 reads 1 byte of data by transmitting the address data to the memory controller 114 once. Give instructions. As a result, when the memory controller 114 receives the address data, the memory controller 114 may read 1 byte of data regardless of whether the source is the control core 111 or the sound output core 112. Therefore, the processing configuration of the memory controller 114 can be simplified.

Even if the memory controller 114 receives the address data from the sound output core 112 during the reading of the 1-byte data, the memory controller 114 completes the reading of the 1-byte data during the reading. As a result, it is possible to give priority to reading the sound data in the sound output core 112, but to prevent the processing for reading the data in the memory controller 114 from becoming complicated.

The memory controller 114 is provided with a control side address buffer 114a and a sound output side address buffer 114b, and when address data is transmitted from the control core 111 or the sound output core 112 during reading of 1-byte data, the address data thereof is provided. The address data is stored in the corresponding address buffers 114a and 114b. As a result, when the reading of data is completed, it is possible to immediately start reading the next data.

In particular, since the sound output side address buffer 114b, which is the priority side at the time of reading, is provided, the address data from the sound output core 112 is received in advance by the memory controller 114 during the reading of 1-byte data. Is possible. As a result, it is easy to create a situation in which the address data received from the sound output core 112 already exists when the reading of 1-byte data is completed, and it is easy to read the priority data to the sound output core 112. Become.

Further, since the control side address buffer 114a and the sound output side address buffer 114b are separately provided in the memory controller 114, the memory controller 114 receives the read-priority side address data depending on the type of the address buffers 114a and 114b. It becomes possible to judge whether or not it is. Therefore, it is possible to simplify the process when the memory controller 114 determines the execution target for reading data.

When the data transfer unit 134 of the sound output core 112 reads out the sound data that enables sound output for a predetermined time, the sound data corresponding to the next channel is obtained after the reading of the sound data corresponding to one channel is completed. The address data is transmitted so that a non-access unit period, which is a period during which the sound data is not read, occurs before the reading of the sound data is started. As a result, even if the reading of the data in the sound output core 112 is prioritized over the reading of the data in the control core 111, it is possible to generate a period for reading the data in the control core 111. Therefore, it is possible to prevent the waiting period for reading data in the control core 111 from becoming long.

Further, the data transfer unit 134 transmits the address data so as not to positively generate a non-access unit period while the sound data corresponding to one channel is read out. As a result, it becomes possible to continuously read each data included in the sound data corresponding to one channel, and the transfer destination of the sound data read by the data transfer unit 134 or the memory controller 114 is specified or determined. It is possible to suitably perform the processing for such a problem.

The data transfer unit 134 transmits the address data according to the sequence data SD, thereby causing the non-access unit period. As a result, the processing configuration for generating a non-access unit period can be simplified.

The setting mode of the read instruction data in the sequence data SD is adjusted so that the non-access unit period becomes equal in a predetermined continuous period. As a result, the non-access unit period is set evenly, and it is possible to evenly generate data read opportunities in the control core 111.

Even when the digital musical tone data having the maximum number of channels is created in both the HWD 132 and the SCM 133, the reading of each sound data is performed so that the non-access unit period occurs in the unit reading period for a predetermined time. This makes it possible to generate a non-access unit period regardless of the number of channels to be output at the same time.

In a configuration where the total time for reading the sound data of the corresponding number of channels in the unit read period is shorter than the unit read period, it is used in the unit sound output period after the corresponding unit sound output period in the unit read period. The sound data to be read is not read. This makes it possible to maximize the non-access unit period in the unit read period.

The unit read period and the amount of sound data are set so that the non-access unit period occurs regardless of whether the digital musical tone data is created by the HWD 132 or the digital musical tone data is created by the SCM 133. .. This makes it possible to generate a non-access unit period regardless of the type of digital musical tone data to be created.

In the sound output core 112, the transmission timing of the address data is adjusted so that such a non-access unit period occurs, whereas in the control core 111, the transmission timing for positively causing such a non-access unit period. Is not adjusted. As a result, the processing configuration can be simplified as compared with the configuration in which the transmission timing of the address data is adjusted in both the control core 111 and the sound output core 112.

When the DMA 123 of the control core 111 receives a read instruction from the CPU 121 of the control core 111, the DMA 123 only periodically transmits the address data until the reading of the data corresponding to the read instruction is completed. Therefore, the configuration of the DMA 123 is simplified. Is planned.

The program data (1) to the program data (L), the processing data (1) to the processing data (M), and the command data (1) to the command data (N) used in the CPU 121 of the control core 111 are When the supply of operating power to the control core 111 is started, the data is read into the RAM 122 of the control core 111. As a result, when the light emission data (1) to the light emission data (P) or the sound data (1) to the sound data (Q) are read, it is basically unnecessary to read the series of data corresponding to the above program. Therefore, a series of program-compatible data will be read during the period in which the read instruction of the light emission data (1) to the light emission data (P) and the sound data (1) to the sound data (Q) is not generated, and the program data (1). It is possible to prevent the need to wait for reading of the program data (L), the processing data (1), the processing data (M), and the command data (1) to the command data (N). ..

It is periodically checked whether or not there is an abnormality in the program-corresponding series of data, and if there is an abnormality, the program-corresponding series of data is read again to the program-corresponding area 122a of the RAM 122. This makes it possible to prevent a series of data corresponding to an abnormal program from being continuously used in the CPU 121 as it is.

When the series of data corresponding to the program is read again, the execution of the timer interrupt process is prohibited, so that the generation of new read instructions for the light emission data and the sound data to the DMA 123 and the data transfer unit 134 is prohibited. This makes it possible to prioritize the re-reading of a series of program-compatible data.

When a command is received from the MPU 62 of the main controller 60 even in a situation where a series of data corresponding to the program is being read back, the command is stored in the ring buffer of the RAM 122. This makes it possible not to invalidate the command transmitted from the MPU 62 of the main control device 60 even during the re-reading of the series of data corresponding to the program.

<Second embodiment>
In the present embodiment, when it is determined in the normality determination process in the CPU 121 of the control core 111 that there is an abnormality in the program-corresponding series of data read into the RAM 122, data other than the program-corresponding series of data is read out. It will be banned. The processing configuration for carrying out the prohibition will be specifically described. The description of the same configuration as that of the first embodiment is basically omitted.

FIG. 24 is a flowchart showing the normality determination process in the present embodiment, and in steps S901 to S905 and steps S907 to S908, the step of the normality determination process (FIG. 15) in the first embodiment. The same process as in steps S401 to S407 is executed. On the other hand, in the normality determination process in the present embodiment, when as a result of the data collation process (step S902), even some bits of the 4-byte data do not match (step S903: NO), a data rewriting instruction is given. Not only the DMA 123 (step S905) but also the rewrite priority setting is performed for the sound output core 112. Specifically, "1" is set in the rewrite priority flag provided in the register 131 of the sound output core 112.

FIG. 25A is a flowchart showing a flow of processing for instructing the DMA 123 of the control core 111 to read data, and is a case where a data rewriting instruction is received from the CPU 121 of the control core 111 (step S1001: YES). , The interrupt process to be read (step S1002) is executed. As a result, regardless of whether or not the reading of the data group corresponding to the reading instruction received from the CPU 121 is completed, the data reading instruction for overwriting the program-corresponding series of data to the program-corresponding area 122a of the RAM 122 is prioritized. Set the interrupt so that it will be done. After that, the processes shown in steps S601 to S611 of the process of DMA123 (FIG. 18) in the first embodiment are executed. If a program-compatible series of data rewrite instruction is issued in a situation where the reading of other data groups has not been completed, the data group that was in the process of being read after the program-compatible series of data has been read. Resume reading.

FIG. 25B is a flowchart showing the flow of processing for instructing the data transfer unit 134 of the sound output core 112 to read data, and when “1” is set in the rewrite priority flag of the register 131 (). Step S1101: YES), "1" is set in the read stop flag provided in the data transfer unit 134 (step S1102). When the read stop flag is not set to "1" (step S1103: NO), the data transfer unit 134 goes to steps S701 to S714 of the process of the data transfer unit 134 (FIG. 20) in the first embodiment. When the other process (step S1104) shown is executed and "1" is set in the read stop flag (step S1103: YES), the other process is not executed. That is, when the program-corresponding series of data is overwritten in the program-corresponding area 122a of the RAM 122, the reading of the data in the sound output core 112 is stopped.

According to the present embodiment described in detail above, when there is an abnormality in the series of data corresponding to the program and an instruction to rewrite the series of data corresponding to the program is issued to the program corresponding area 122a of the RAM 122, the reading of other data is stopped. Will be done. As a result, the reading of the series of data corresponding to the program can be prioritized over the reading of other data, and the rewriting of the series of data corresponding to the program can be completed at an early stage.

<Third embodiment>
In the present embodiment, the processing configuration of the CPU 121 of the control core 111 is different from that of the first embodiment. Hereinafter, the different configurations will be described. The description of the same configuration as that of the first embodiment is basically omitted.

FIG. 26 is a block diagram showing an electrical configuration for controlling the execution of the effect in the present embodiment.

In the present embodiment, the control core 111 of the sound / light SOC 102 is provided with a direct-attached ROM 201 in addition to the CPU 121, RAM 122, and DMA 123. The direct-attached ROM 201 is electrically connected to the CPU 121 via an address bus and a data bus, and the data stored in advance in the direct-attached ROM 201 can be read by the CPU 121. That is, the CPU 121 not only uses the data stored in the sound / light ROM 103, but also uses the data stored in the direct attachment ROM 201.

The direct-attached ROM 201 is configured to use a memory (that is, a non-volatile storage means) that does not require external power supply for storage retention as read-only. Specifically, although the NOR type flash memory is used as the directly attached ROM 201, a NAND type flash memory may be used. The direct attachment ROM 201 stores various control programs and fixed value data used when executing processing according to the programs.

The data structure of the directly attached ROM 201 will be described in detail with reference to FIG. 27. The direct attachment ROM 201 stores the initial start-up data (1), the initial start-up data (2), ..., And the initial start-up data (R) in advance. These initial startup data are directly read from the directly attached ROM 201 by the CPU 121 when the supply of operating power to the CPU 121 is started. The CPU 121 executes the first processing after the start of supply of the operating power by executing the processing according to the program data and the control data included in the initial startup data, and is stored in the sound / light ROM 103. Instructs to read a series of data corresponding to the program. After all of the program-compatible series of data has been read into the program-compatible area 122a of the RAM 122, the CPU 121 performs processing using the program-compatible series of data from the state of executing processing using the initial startup data. Switch to the state to execute.

In the direct attachment ROM 201, in addition to the initial startup data, command interrupt data (1), command interrupt data (2), ..., Command interrupt data (S) are stored in advance. These command interrupt data include program data and control data for executing command interrupt processing in the CPU 121. The command interrupt process is a process that is started by interrupting another process by the CPU 121 when it is specified by a latch circuit (not shown) provided in the control core 111 that a command is transmitted from the MPU 62 of the main control device 60. Is. By executing the command interrupt process, the command received from the MPU 62 of the main controller 60 can be used in the subsequent process.

In the direct attachment ROM 201, in addition to the initial startup data and command interrupt data, rewrite data (1), rewrite data (2), ..., Rewrite data (T) are stored in advance. ing. These rewrite data execute an instruction to rewrite the program-corresponding series of data when it is identified that an abnormality has occurred in the program-corresponding series of data read out in the program-corresponding area 122a of the RAM 122. Includes program data and control data for. When starting the rewriting of the series of data corresponding to the program and during the execution of the rewriting, the CPU 121 directly reads the data for rewriting from the directly attached ROM 201 and executes the corresponding processing.

Of the program data and control data required to execute various processes in the CPU 121, data other than the initial startup data, command interrupt data, and rewriting data are stored in advance in the sound / light ROM 103. ..

<Main processing of CPU 121>
Next, the main process of the CPU 121 in the present embodiment will be described with reference to the flowchart of FIG. 28.

When the supply of the operating power is started, the CPU 121 directly reads the initial start-up data from the directly attached ROM 201 to execute the processes of steps S1201 to S1203. Specifically, by first executing the initialization process of the RAM 122 in step S1201, each area of the RAM 122 is cleared to "0". After that, in step S1202, a data read instruction at the time of power-up is given to the DMA 123. When the DMA 123 receives a data read instruction at the time of turning on the power supply, the series of program-corresponding data stored in advance in the sound / light ROM 103 is read out to the program-corresponding area 122a of the RAM 122, as in the first embodiment. Address data is transmitted to the memory controller 114.

After that, in step S1203, by determining whether or not the data read completion signal has been received from the DMA 123, it is determined whether or not the data read corresponding to the data read instruction at the time of starting the power supply has been completed. If the reading of the data is not completed, the process waits in step S1203.

When it is determined that the reading of the data is completed (step S1203: YES), the CPU 121 executes the processing after step S1204 by referring to the series of program-corresponding data read out in the program-corresponding area 122a of the RAM 122. Specifically, in step S1204, execution of command interrupt processing and timer interrupt processing is permitted.

In the following step S1205, it is determined whether or not a command is received from the MPU 62 of the main control device 60. Here, when a command is received from the MPU 62 of the main control device 60, the command interrupt processing is activated in the CPU 121 of the control core 111 by latching the command in the latch circuit of the control core 111 as described above. Further, the command interrupt process is executed by directly reading the command interrupt data from the directly attached ROM 201. That is, the CPU 121 switches from the state of reading the program-corresponding series of data read to the program-corresponding area 122a of the RAM 122 to the state of directly reading the command interrupt data from the directly attached ROM 201.

In the command interrupt processing, as shown in the flowchart of FIG. 29A, first, the execution of the timer interrupt processing is prohibited in step S1301. After that, by updating the write pointer of the ring buffer 122c in step S1302, the areas for writing the command received this time among the areas of the ring buffer 122c are set in the following order with respect to the currently set area. Change to an area. When the value of the write pointer reaches the maximum value, the pointer is cleared to "0". Therefore, when the area to be written goes around once, the newly received command is overwritten in the area where the command has already been written. After that, in step S1303, the command received this time is written to the area corresponding to the write pointer of the updated result. Then, in step S1304, the execution of the timer interrupt process is permitted. When the command interrupt processing is completed, the CPU 121 switches from the state of directly reading the command interrupt data from the directly attached ROM 201 to the state of reading the program-corresponding series of data read into the program-corresponding area 122a of the RAM 122. Then, by referring to the series of data corresponding to the program, the processing that was being executed immediately before the command interrupt processing is started is restarted.

Returning to the description of the main process (FIG. 28), in step S1205, it is determined whether or not an unprocessed command is stored in the ring buffer 122c of the RAM 122. When an unprocessed command is stored, the data table for enabling the effect or notification corresponding to the command to be read this time is read from the program-compatible area 122a of the RAM 122 to the general-purpose area 122b in step S1206. Set as the execution target. In this case, the data table includes a data transmission table in which the timing of transmitting sequence data and parameter data to the sound output core 112 and the type of combination of the sequence data and parameter data are set, and an instruction to read light emission data. For light emission control in which data that can specify the timing given to the DMA 123 and the type of light emission data to be read out are set, and the execution timing of light emission control based on the light emission data read in advance is set. There is a table. A set of these data transmission table and the light emission control table is provided according to the contents of various effects, and the light emitting mode of the display light emitting unit 53 and the speaker are provided by referring to each of the corresponding tables by the CPU 121. It is possible to associate with the sound output mode from the unit 54. After that, in step S1207, the display system command corresponding to the data table read this time is transmitted to the display control device 90. As a result, the symbol display device 41 is displayed and controlled by the display control device 90 so that the display effect corresponding to the data table is performed.

When a negative determination is made in step S1205, or when the process of step S1207 is executed, it is determined in step S1208 whether or not the value of the first interrupt counter provided in the RAM 122 is "0". The first interrupt counter is a counter for specifying the execution cycle of the data transmission process in step S1209 by the CPU 121.

Here, the timer interrupt process is periodically started at a cycle of 500 μsec. In the timer interrupt process, as shown in the flowchart of FIG. 29B, first, the value of the first interrupt counter of the RAM 122 is subtracted by 1 in step S1401. A numerical value is set in the first interrupt counter so that the value of the first interrupt counter becomes "0" in a cycle of 2 msec. Further, in step S1402, the value of the second interrupt counter provided in the RAM 122 is subtracted by 1. The second interrupt counter is a counter for the CPU 121 to specify the execution cycle of the light emission control process in step S1211 in the main process (FIG. 28). A numerical value is set in the second interrupt counter so that the value of the second interrupt counter becomes "0" in a cycle of 4 msec.

Returning to the description of the main process (FIG. 28), when the value of the first interrupt counter is “0” (step S1208: YES), the data transmission process is executed in step S1209. In the data transmission process, by referring to the data transmission table used this time, it is possible to specify whether or not it is the transmission timing of sequence data and parameter data, and if it is the transmission timing, it corresponds. The type of sequence data and parameter data are written to the register 131 of the sound output core 112.

When a negative determination is made in step S1208, or when the process of step S1209 is executed, it is determined in step S1210 whether or not the value of the second interrupt counter of the RAM 122 is "0". When the value of the second interrupt counter is "0", the light emission control process is executed in step S1211. In the light emission control process, by referring to the light emission control table to be used this time, it is determined whether or not it is the timing to give the reading instruction of the light emission data, and if it is the timing to give the reading instruction, it is determined. The DMA 123 is instructed to read the corresponding light emission data. Further, in the light emission control process, it is specified whether or not it is the light emission control timing of the display light emission control unit 53 by referring to the light emission control data, and if it is the light emission control timing, the display light emission unit 53 follows the corresponding light emission data. Performs light emission control.

When a negative determination is made in step S1210, or when the process of step S1211 is executed, it is determined that "1" is not set in the executing flag of the normal determination of the RAM 122 and that it is the start timing of the normal determination. As a condition (step S1212: NO, step S1213: YES), in step S1214, a data read instruction for normality determination is given to the DMA 123. After that, in step S1215, "1" is set in the executing flag of the normality determination of the RAM 122, and then the process returns to step S1204. The processing contents of steps S1212 to S1215 are the same as those of steps S305 to S308 of the main processing (FIG. 12) in the first embodiment. On the other hand, when "1" is set in the execution flag of the normality determination (step S1212: YES), the process returns to step S1204 after the normality determination process is executed in step S1216. When the normality determination process is completed for all the series of data corresponding to the program having a data capacity of 512 bytes, the execution flag of the normality determination is cleared to "0".

<Process for determining normality of CPU 121>
FIG. 30 is a flowchart showing a normality determination process.

When the reading of the series of data corresponding to the program to the general-purpose area 122b is completed (step S1501: YES), the data collation process is executed in step S1502. In the data collation process, 4-byte data corresponding to each other in the program-corresponding series data stored in the program-corresponding area 122a of the RAM 122 and the program-corresponding series data stored in the general-purpose area 122b are read from each. By executing logical calculation processing such as XOR processing, it is determined whether or not the 4-byte data match.

If all the bits of the 4-byte data match (step S1503: YES), the normality determination process is terminated as it is. That is, in the normal determination, the data collation process is not executed at once for the entire series of data corresponding to the program consisting of 512 bytes, but the data collation process is executed in units of 4 bytes which are the collation target bytes. Here, when the data collation process is started, the interrupt of the command interrupt process (FIG. 29 (a)) and the interrupt of the timer interrupt process (FIG. 29 (b)) are not prohibited, so that the data collation process is being executed. However, the command interrupt process (FIG. 29 (a)) and the timer interrupt process (FIG. 29 (b)) occur.

If even some of the 4-byte data do not match (step S1503: NO), the data rewriting process shown in steps S1504 to S1508 is executed. Here, the data rewriting process is executed by directly reading the rewriting data from the directly attached ROM 201. That is, the CPU 121 switches from the state of reading the program-corresponding series of data read to the program-corresponding area 122a of the RAM 122 to the state of directly reading the rewriting data from the directly attached ROM 201.

In the data rewriting process, the execution of the timer interrupt process (FIG. 29 (b)) is prohibited in step S1504. As a result, even if the execution cycle of the timer interrupt process is reached, the interrupt of the timer interrupt process does not occur. On the other hand, even when the data rewriting process is executed, the execution of the command interrupt process (FIG. 29 (a)) is not prohibited. As a result, the command received from the MPU 62 of the main control device 60 can be stored in the ring buffer 122c of the RAM 122 even when the data rewriting process is being executed, so that the reception of the command is not invalidated. It becomes possible to.

In the following step S1505, a data rewriting instruction is given to the DMA 123. Upon receiving a data rewriting instruction, the DMA 123 transmits the corresponding address data to the memory controller 114, so that the memory controller 114 reads out a series of program-corresponding data to the program-corresponding area 122a of the RAM 122. Let's get started. In this case, the newly read program-corresponding series of data is overwritten in the program-corresponding area 122a. Further, in step S1506, the rewrite priority setting is performed for the sound output core 112. Specifically, "1" is set in the rewrite priority flag provided in the register 131 of the sound output core 112. The operation of the sound output core 112 when "1" is set in the rewrite priority flag is the same as that of the second embodiment.

After that, in step S1507, it is determined whether or not the rewriting of the program-corresponding series of data for the program-corresponding area 122a is completed. If the rewriting is not completed, the process waits in step S1507. When the rewriting of the series of data corresponding to the program is completed, the execution of the timer interrupt process (FIG. 29 (b)) is permitted in step S1508. As a result, the interrupt is permitted from the state in which the periodic interrupt of the timer interrupt process is prohibited. When the data rewriting process is completed, the CPU 121 switches from the state of directly reading the rewriting data from the directly attached ROM 201 to the state of reading the program-corresponding series of data read into the program-corresponding area 122a of the RAM 122. Then, by referring to the series of data corresponding to the program, the process of step S1204 in the main process (FIG. 28) is executed.

<DMA123>
Next, a processing configuration for reading data from the sound / light ROM 103 will be described. The process flow for instructing the data transfer unit 134 of the sound output core 112 to read data is the same as the process flow (FIG. 25 (b)) shown in the second embodiment, and the memory controller 114. The process flow for reading the data is the same as the process flow (FIG. 21) shown in the first embodiment. On the other hand, the flow of processing for instructing the DMA 123 of the control core 111 to read data is different from each of the above embodiments. Therefore, the flow of processing in the present embodiment for instructing the DMA 123 to read data will be described with reference to the flowchart of FIG.

When the DMA 123 receives a data read instruction from the CPU 121 of the control core 111 (step S1601: YES), the DMA 123 executes a process for storing the address data corresponding to the read instruction in the internal register of the DMA 123 (step S1602). ). Specifically, the data of the start address and the data of the end address of the data group corresponding to the read instruction this time are stored in the internal register. In this case, if the other data group is being read, the data setting process is executed so that the data at the start address and the data at the end address of the data group being read are not erased. Further, "1" is set in the read instruction flag provided in the internal register of the DMA 123 (step S1603).

When the DMA 123 newly receives a read instruction of the light emission data from the CPU 121 in a situation where the read instruction of the normality determination data corresponding to the read instruction from the CPU 121 is not completed (step S1604 and step S1605: YES), the DMA 123 is a read target. Interrupt processing of (step S1606) is executed. Specifically, the state in which the normality determination data reading instruction is being given is temporarily interrupted, and the light emission data reading instruction corresponding to the current reading instruction is started. As a result, if an instruction to read the light emission data is issued during the reading of the normality determination data, the reading of the light emission data can be prioritized, and the light emission control timing can be prevented from being delayed. ..

On the other hand, even when a new data rewriting instruction is received from the CPU 121 in a situation where the data reading corresponding to the reading instruction from the CPU 121 is not completed (step S1607 and step S1608: YES), the interrupt processing to be read is performed. Execute (step S1606). Specifically, the state in which the current read instruction of the data to be read is being given is temporarily interrupted, and the read instruction for rewriting the series of data corresponding to the program is started. This makes it possible to prioritize the rewriting of a series of data corresponding to the program over the reading of any data. It will be possible to complete it at an early stage.

The DMA 123 executes a read process regardless of whether or not a new read instruction has been received from the CPU 121 (step S1609). In the read-out process, the processes shown in steps S601 to S611 of the DMA123 process (FIG. 18) in the first embodiment are executed. In this case, if the interrupt process (step S1606) to be read has occurred, the read instruction of the data group set as the interrupt target has priority, and the data group is interrupted in the middle of execution after the reading of the data group is completed. The read instruction of the data group that had been used is restarted.

<Data reading mode>
Next, the reading mode of various data will be described with reference to the time chart of FIG. FIG. 32 (a) shows the timing when the instruction to read the normality determination data is given from the CPU 121 to the DMA 123, and FIG. 32 (b) shows the timing when the instruction to read the light emission data is given from the CPU 121 to the DMA 123. ) Indicates the timing at which the CPU 121 gives the DMA 123 a rewriting instruction for a series of data corresponding to the program, FIG. 32 (d) shows the reading period of the normality determination data, and FIG. 32 (e) shows the reading period of the light emission data. 32 (f) shows a period during which a series of program-corresponding data is read out for rewriting, and FIG. 32 (g) shows a period during which the sound data is read out by the data transfer unit 134 of the sound output core 112. ..

First, a case where an instruction to read light emission data is generated during reading of normality determination data will be described.

When the instruction to read the normality determination data is given to the DMA 123 from the CPU 121 as shown in FIG. 32 (a) at the timing of t1, the reading of the normality determination data is started as shown in FIG. 32 (d). After that, since the data of the reading instruction of the sound data is set in the sequence data read in the register 131 of the sound output core 112 at the timing of t2, as shown in FIG. 32 (g), the sound output core 112 The data transfer unit 134 starts reading the sound data. In this case, in FIGS. 32 (d) and 32 (g), it is shown that the read period of the normality determination data and the read period of the sound data overlap, but the memory controller 114 actually has the memory controller 114. While giving priority to reading the sound data, the normality determination data is read in between the reading of the sound data.

After that, at the timing of t3, as shown in FIG. 32 (b), an instruction to read light emission data is given from the CPU 121 to the DMA 123. In this case, as described above, since the reading of the light emission data is prioritized over the reading of the normality determination data, the reading of the normality determination data is temporarily interrupted as shown in FIG. 32 (d), and FIG. 32 (e). ), The reading of the light emission data is started. On the other hand, as shown in FIG. 32 (g), the reading of the sound data is continued. In this case, the memory controller 114 reads out the light emission data between the reading of the sound data while giving priority to the reading of the sound data.

After that, at the timing of t4, the reading of the light emission data is completed as shown in FIG. 32 (e), and the reading of the normality determination data is restarted as shown in FIG. 32 (d). In this case, the reading of the normality determination data is not started from the beginning, but the reading of the normality determination data is restarted from the state in the middle of the interruption at the timing of t3.

Next, a case where a rewrite instruction is generated during reading of the light emission data will be described.

When the CPU 121 gives the DMA 123 an instruction to read the light emission data as shown in FIG. 32 (b) at the timing of t5, the reading of the light emission data is started as shown in FIG. 32 (e). After that, since the data of the reading instruction of the sound data is set in the sequence data read in the register 131 of the sound output core 112 at the timing of t6, as shown in FIG. 32 (g), the sound output core 112 The data transfer unit 134 starts reading the sound data. In this case, in FIGS. 32 (e) and 32 (g), it is shown that the read period of the light emission data and the read period of the sound data overlap, but in reality, the memory controller 114 is the sound data. While giving priority to the reading of the sound data, the light emission data is read in between the reading of the sound data.

After that, at the timing of t7, as shown in FIG. 32 (c), a program-corresponding series of data rewriting instruction is given from the CPU 121 to the DMA 123. In this case, as described above, since the rewriting of the series of data corresponding to the program has priority over the reading of any data, the reading of the light emission data is temporarily interrupted as shown in FIG. 32 (e), and FIG. 32 ( As shown in g), the reading of the sound data is temporarily interrupted, and as shown in FIG. 32 (f), the rewriting of the series of data corresponding to the program is started.

After that, at the timing of t8, the rewriting of the series of data corresponding to the program is completed as shown in FIG. 32 (f), so that the reading of the light emission data is restarted as shown in FIG. 32 (e) and FIG. 32 As shown in (g), the reading of the sound data is restarted. In this case, the reading of the light emission data and the sound data is not started from the beginning, but the reading of the light emission data and the sound data is restarted from the state in which the light emission data and the sound data are interrupted at the timing of t7.

<Relationship between the execution cycle of normality judgment processing and the execution period of various processes>
Next, the relationship between the execution cycle of the normality determination process and the execution period of various processes will be described with reference to the explanatory diagram of FIG. 33.

As described above, in the normality determination process, all of the program-corresponding series of data (for example, 512 bytes) stored in the sound / light ROM 103 is read out to the general-purpose area 122b of the RAM 122 of the control core 111. This reading takes about 8 msec at the longest. Then, after the program-corresponding series of data is read out to the general-purpose area 122b, the program-corresponding series of data stored and held in the program-corresponding area 122a of the RAM 122 and the program-correspondence read out to the general-purpose area 122b of the RAM 122 this time are supported. When the series of data of the above is collated in units of 4 bytes and it is specified that the two data do not match, the series of data corresponding to the program is read out again for the program corresponding area 122a.

The execution cycle Ta of the normality determination process is 32 msec. This execution cycle Ta is the shortest period Ta1 required to execute the data transmission process (step S1209) of the main process (FIG. 28) in the execution cycle Ta, and the light emission control of the main process (FIG. 28) in the execution cycle Ta. The shortest period Ta2 required to execute the process (step S1211), the shortest period Ta3 required to execute the timer interrupt process (FIG. 29 (b)) in the execution cycle Ta, and the data collation result in the execution cycle Ta. The period is set to be longer than the sum of the shortest period Ta4 required to execute the normality determination process (FIG. 30) in a situation where no abnormality occurs. It should be noted that Ta1 is derived by "minimum execution period of data transmission processing" x Ta / "execution cycle of data transmission processing", and Ta2 is "minimum execution period of light emission control processing" x Ta / "execution of light emission control processing". Derived by "cycle", Ta3 is derived by "minimum execution period of timer interrupt processing" x Ta / "execution cycle of timer interrupt processing", and Ta4 is data collation for 512 bytes in a situation where data collation result error does not occur. It corresponds to the period required to execute the process.

Since Ta> (Ta1 + Ta2 + Ta3 + Ta4), a residual period Ta5 may occur in the execution cycle Ta of the normality determination process. As a result, even if the collation result becomes abnormal in the normality determination process and it is necessary to rewrite the series of data corresponding to the program, the rewriting can be performed by using the remaining period Ta5. However, the period Tb required for rewriting the data is longer than the remainder period Ta5. Therefore, although it depends on the timing when the collation result becomes abnormal, when the data rewriting instruction is issued, the rewriting of the series of data corresponding to the program may not be completed within the range of 32 msec. In this case, the next execution times. The normality determination process of is not executed.

According to the present embodiment described in detail above, the following excellent effects are obtained in addition to the effects described in the first embodiment.

The direct-attached ROM 201 is provided in the control core 111, and the program data and the control data are directly read from the direct-attached ROM 201 when the process for initial startup and the process for data rewriting are executed. As a result, when reading the program-compatible series of data from the sound / light ROM 103 to the RAM 122, it is only necessary to use the data stored in the direct-attached ROM 201, and it is possible to suitably read the program-compatible series of data. Become.

Further, the direct-attached ROM 201 also stores and holds command interrupt data for executing command interrupt processing. This makes it possible to execute command interrupt processing regardless of whether or not a series of program-compatible data is being read, and it is possible to reliably receive the command transmitted from the MPU 62 of the main controller 60. It will be possible.

In a configuration in which the DMA 123 executes read control of light emission data and normality determination data in response to a read instruction from the CPU 121 of the control core 111 and rewrite control of a series of data corresponding to the program, the series of data corresponding to the program can be rewritten. It has priority over reading the light emission data and the normality determination data. This makes it possible to complete the rewriting of a series of data corresponding to the program at an early stage when a collation result abnormality occurs in the normality determination process. Furthermore, when rewriting a series of data corresponding to the program, the reading of the sound data is interrupted in the data transfer unit 134 of the sound output core 112. From this point as well, it is possible to complete the rewriting of a series of data corresponding to the program at an early stage.

<Other embodiments>
It should be noted that the description is not limited to the above-described embodiment, and various modifications and improvements can be made without departing from the spirit of the present invention. For example, it may be changed as follows. Incidentally, the following configuration of another embodiment may be applied individually or in combination to the configuration of the above embodiment.

(1) The memory controller 114 is not limited to a configuration in which the sound output core 112 is prioritized over the control core 111 as a data read target, and the control core 111 is prioritized over the sound output core 112. May be. Further, the priority target may be switched depending on the situation. For example, when a series of program-corresponding data is read by the control core 111, the control core 111 is prioritized over the sound output core 112 as the data read target, and the light emission data. When is read out by the control core 111, the sound output core 112 may be prioritized over the control core 111 as the data read target.

(2) The transmission of address data to the memory controller 114 is not limited to the configuration of the two control means of the control core 111 and the sound output core 112, and may be one control means. Even in this case, among the address data transmitted from the one control means, the address data corresponding to the reading instruction of the data other than the sound data is stored in the control side address buffer 114a, and the reading instruction of the sound data is performed. By storing the corresponding address data in the sound output side address buffer 114b, it is possible to prioritize the reading of the sound data as in each of the above embodiments.

Further, three or four or more control means may be used to transmit the address data to the memory controller 114. In this case, by setting the priority of data reading among the plurality of control means in advance, even if the address data is transmitted from the plurality of control means at the same time, the data can be read according to the priority. It will be possible.

(3) The type of the control means for reading data from the common ROM such as the sound / light ROM 103 is not limited to the control core 111 and the sound output core 112, and for example, the display of the image in the symbol display device 41 is controlled. The display control means and the sound output control means such as the sound output core 112 may be configured to read data from the common ROM. Even in this case, when the memory controller 114 that manages the reading of data from the common ROM receives the address data from the display control means and the sound output control means at the same time, the memory controller 114 reads and executes the data according to a predetermined priority. It may be configured to determine the target address data.

For example, by giving priority to reading data to the display control means over reading data to the sound output control means, it is possible to prevent a delay in the display of the image on the symbol display device 41. In particular, since it is considered that the player pays attention to the display effect on the symbol display device 41 rather than the effect sound and the sound effect, it is preferable to give priority to reading the data to the display control means. Further, in the configuration, display control is performed between the completion of reading the image data of one of the image data groups necessary for displaying the image in a predetermined period and the start of reading the next image data. By generating a non-access unit period of the means, it is possible to have the sound output control means read out the sound data by using the non-access unit period.

(4) Sound data is not stored in the sound / light ROM 103, and the sound data may be stored in another ROM. In this case, the memory controller 114 is provided with a ring buffer capable of storing a plurality of address data transmitted from the control core 111, and when the memory controller 114 starts reading data corresponding to the address data, the ring buffer is provided. Of the address data stored in, the read execution target may not be determined in the order of reception, but the read execution target may be set from the address data having the highest priority. For example, when the address data for reading the effect data and the address data for reading the abnormality notification data are stored in the ring buffer at the same time, the reading of the abnormality notification data is prioritized over the reading of the effect data. It may be configured. This makes it possible to prioritize the abnormality notification over the execution of the effect. Further, in the configuration in which the address data having a high priority is selected from the plurality of address data stored in the ring buffer as described above, the data indicating the priority is attached to each address data and is read and executed. When selecting the address data, it is advisable to make a comparison judgment of the data indicating the priority.

(5) At least one of the control side address buffer 114a and the sound output side address buffer 114b of the memory controller 114 may be configured to be a ring buffer capable of storing a plurality of address data according to the reception order. For example, in a configuration in which the sound output side address buffer 114b is a ring buffer, it is possible to store a plurality of address data transmitted from the sound output core 112 at the same time, and read the address data in the order of reception. It becomes possible to make it an execution target.

(6) The memory controller 114 may be configured not to be provided with the control side address buffer 114a corresponding to the control means on the non-priority side.

(7) When the memory controller 114 reads out the data corresponding to the address data received from one of the control core 111 and the sound output core 112, it is better than reading the data corresponding to the address data received from the other. , It may be configured to read a large amount of data. For example, when reading the data corresponding to the address data received from the sound output core 112 which is the control means on the priority side, the 2-byte data is read and received from the control core 111 which is the control means on the non-priority side. When reading the data corresponding to the address data, the configuration may be such that 1 byte of data is read. This makes it possible to read the data to the control means on the priority side at an earlier stage.

(8) When the memory controller 114 receives one address data from the sound output core 112, the memory controller 114 reads out all the multi-byte sound data for one channel, which is the target of the read instruction in the sound output core 112, and controls the core. When one address data is received from the 111, the control core 111 may be configured to read a part of the light emission data of a plurality of bytes to be read.

(9) The data read from the sound and light ROM 103 to the RAM 122 of the control core 111 at the start of supplying the operating power to the control core 111 is the program data (1) to the program data (L) and the processing data (1). -It is not limited to the processing data (M) and the command data (1) to the command data (N), and all of the program data (1) to the program data (L) are to be read, and other than that. May be configured to be read when it is needed for program execution. Further, when all of the program data (1) to the program data (L) and the processing data (1) to the processing data (M) are to be read, and other than that, when it is necessary for executing the program. It may be configured to be read out. Further, all of the program data (1) to the program data (L) and the command data (1) to the command data (N) are to be read, and the other data is read when necessary for executing the program. It may be configured. Further, all of the program data (1) to the program data (L), and at least one of the processing data (1) to the processing data (M) and the command data (1) to the command data (N). The unit may be read out.

(10) The unit read period for a predetermined period is divided into a unit read period for HWD 132 and a unit read period for SCM 133, and the sound data is read so that the non-access unit period is evenly generated in each unit read period. The non-access unit period is evenly generated throughout the unit read period without being limited to the configuration in which the period is adjusted, and the unit read period for HWD 132 and the unit read period for SCM 133 are not divided. The sound data reading period may be adjusted as described above. However, even with this configuration, the length of the non-access unit period, which is evenly distributed according to the number of channels for which digital musical tone data needs to be created, varies.

(11) The sound data corresponding to one channel is not limited to the configuration in which the sound data corresponding to one channel is read in one reading period of the sound data existing so as to sandwich the non-access unit period, and the sound data corresponding to a plurality of channels is not limited. May be read out, or a part of the sound data corresponding to one channel may be read out.

(12) When the memory controller 114 receives the address data corresponding to the data read instruction having a higher priority than the data being read while reading the 1-byte data, the memory controller 114 stops reading the data in the middle of execution. Alternatively, the configuration may be interrupted to start reading the data corresponding to the newly received address data.

(13) Of the DMA 123 and the data transfer unit 134, the configuration is not limited to a configuration in which data is read out while causing a non-access unit period only in the data transfer unit 134, and a non-access unit period is generated only in the DMA 123. However, the data may be read out while the non-access unit period is generated in both the DMA 123 and the data transfer unit 134.

(14) In the third embodiment, instead of the configuration in which the residual period Ta5 is shorter than the period Tb required for data rewriting, the residual period Ta5 may be configured to be equal to or longer than the period Tb required for data rewriting. .. This makes it possible to reduce the influence on the execution cycle of the normality determination process when a series of program-corresponding data rewrites occur.

(15) When determining whether or not the program-corresponding series of data read into the program-corresponding area 122a of the RAM 122 is normal, first, after reading all the program-corresponding series of data into the general-purpose area 122b of the RAM 122, The program-corresponding series of data read out in the program-corresponding area 122a and the program-corresponding series of data read out in the general-purpose area 122b are collated in 4-byte units. Instead of reading all of the series of data corresponding to the program to the general-purpose area 122b, only 4 bytes, which is the data to be collated when performing the collation processing, may be read and the collation processing may be performed.

(16) The collation process for specifying whether or not the series of program-corresponding data read out in the program-corresponding area 122a is normal is not limited to the configuration in which the collation process is performed in 4-byte units, and is not limited to 1 byte or 1 byte. It may be configured in byte units of less than 4 bytes such as 2 bytes, or in byte units of more than 4 bytes such as 5 bytes or 6 bytes. Further, the entire series of data corresponding to the program may be configured to be executed once for the collation process.

(17) When rewriting of the series of data corresponding to the program read in the program corresponding area 122a of the RAM 122 occurs, processing other than the processing for waiting for the rewriting of the series of data corresponding to the program is completed is executed. It may be configured to be. For example, it monitors whether or not a command for abnormality notification is received from the MPU 62 of the main control device 60, and if the command is received, directly outputs a processing program and control data for starting abnormality notification. It may be configured to be stored in advance in the attached ROM 201 so that the abnormality notification can be started even in the situation where the series of data corresponding to the program is being rewritten.

(18) As in the case where the series of data corresponding to the program is rewritten, the reading of the data for normality determination to the general-purpose area 122b of the RAM 122 is prioritized over the reading of the light emission data and the reading of the sound data. May be good.

(19) A configuration for periodically monitoring whether or not the data read from the ROM to the RAM is normal may be applied to data other than a series of program-compatible data.

For example, the MPU 62 of the main control device 60, which has a low probability mode and a high probability mode as the winning / failing lottery mode, refers to the winning / losing lottery table for the low probability mode stored in advance in the ROM 63 in the case of the low probability mode, and is in the high probability mode. If this is the case, in a configuration in which the winning / failing lottery table for the high-probability mode stored in advance in the ROM 63 is referred to, the corresponding winning / losing lottery table is stored and held in the RAM 64 while at least one of the low-probability mode and the high-probability mode. It is made to periodically confirm whether or not the winning / failing lottery table stored in the RAM 64 is normal. Then, when it is specified that there is an abnormality in the data of the winning / failing lottery table read out to the RAM 64, the winning / failing lottery table is read again. As a result, the possibility that an abnormal winning / failing lottery table is used is reduced while suppressing the frequency of reading the winning / failing lottery table from the ROM 63.

Further, for example, the control core 111 does not have a configuration in which all of the program-corresponding series of data is read out to the program-corresponding area 122a of the RAM 122, but a configuration in which all of the data tables for determining the execution contents of the effect are read in advance to the RAM 122. In, it is necessary to periodically check whether or not these data tables are normal. When it is identified that the data table read from the RAM 122 has an abnormality, the data table is excluded from the target of use, and another data table is used as a substitute. This reduces the possibility of using an abnormal data table while eliminating the need to reload the data table.

(20) Display control based on the command transmitted from the main control device 60 instead of the configuration in which the display control device 90 is controlled by the voice emission control device 80 based on the command transmitted from the main control device 60. The device 90 may be configured to control the voice emission control device 80. Further, instead of the configuration in which the voice emission control device 80 and the display control device 90 are separately provided, a configuration in which both control devices are provided as one control device may be used, and the function of one of the two control devices may be provided. May be integrated in the main control device 60, and both functions of both control devices may be integrated in the main control device 60. Further, the configuration of the command transmitted from the main control device 60 to the voice emission control device 80 and the configuration of the command transmitted from the voice emission control device 80 to the display control device 90 are also arbitrary.

(21) Other types of pachinko machines different from the above embodiments, for example, a pachinko machine in which an electric accessory is opened a predetermined number of times when a game ball enters a specific area of a special device, or a game ball in a specific area of a special device. The present invention can also be applied to a pachinko machine, which is a big hit when a right is entered, a pachinko machine equipped with other accessories, an arrange ball machine, a game machine such as a sparrow ball, and the like.

In addition, a non-bullet type gaming machine, for example, a plurality of reels having a plurality of types of symbols attached in the circumferential direction is provided, the reels are started to rotate by inserting medals and operating the start lever, and the stop switch is operated. After the reels have stopped after a predetermined time has passed, if a specific symbol or a combination of specific symbols is established on the effective line that can be seen from the display window, a privilege such as paying out a medal is given to the player. The present invention can also be applied to slot machines.

In addition, the main body of the gaming machine, which is supported by the outer frame so as to be openable and closable, is equipped with a storage unit and a take-in device, and the start lever is operated after a predetermined number of game balls stored in the storage unit are taken in by the take-in device. The present invention can also be applied to a gaming machine in which a pachinko machine and a slot machine are fused to start rotation of a reel.

<About the invention group extracted from each of the above embodiments>
Hereinafter, the characteristics of the invention group extracted from each of the above-described embodiments will be described while showing the effects and the like as necessary. In the following, for the sake of easy understanding, the corresponding configurations in each of the above embodiments are appropriately shown in parentheses or the like, but the present invention is not limited to the specific configurations shown in the parentheses or the like.

<Characteristic A group>
Features A1. A storage means (ROM103 for sound and light) that stores information in advance,
A management means (memory controller 114) that reads out the information corresponding to the read instruction information from the storage means when the read instruction information is received, and
Equipped with
When the management means receives a plurality of read instruction information, the management means determines the read instruction information to be executed for reading the information according to a predetermined priority different from the reception order of the read instruction information. A gaming machine characterized by comprising means (a function of executing the processes of steps S810 to S813 in the memory controller 114).

According to the feature A1, the read instruction information to be executed for reading the information is determined according to the priority different from the reception order of the read instruction information. Therefore, the information having a high priority is obtained at an early stage regardless of the reception order. It can be read.

Feature A2. A request responding means (DMA123, data transfer unit 134) for transmitting the read instruction information to the management means on condition that there is a request to read the information is provided.
When the management means receives the read instruction information, the management means reads the unit information, which is an amount of information smaller than the amount of information corresponding to the read request.
The determination of the read instruction information to be executed by the determination means may occur after the reading of the unit information is completed even if the reading of the information corresponding to the reading request is not completed. The gaming machine according to the feature A1.

According to the feature A2, the amount of information to be read is suppressed for one transmission of the read instruction information, and even if the reading of the information corresponding to the read request is not completed, the information is read once. When the reading of the information for the transmission of the reading instruction information is completed, the reading instruction information to be executed is determined according to the priority, so that the information having a high priority can be read at an early stage.

Feature A3. The gaming machine according to feature A2, wherein the unit information is the smallest unit of information that can be read out.

According to the feature A3, since the information to be read is the smallest unit of information that can be read for one transmission of the read instruction information, the frequency of determining the read instruction information to be executed is increased. Is possible.

Feature A4. A request responding means (DMA123, data transfer unit 134) for transmitting the read instruction information to the management means on condition that there is a request to read the information is provided.
The request responding means is any one of the features A1 to A3, characterized in that the reading instruction information is transmitted to the management means to instruct the reading of information having a smaller amount of information than the information corresponding to the reading request. The gaming machine according to 1.

According to the feature A4, since the request responding means is configured to instruct to read out the information with a smaller amount of information than the information corresponding to the read request by transmitting the read instruction information once, the information with a small amount of information is read out. In the configuration in which the above is actively performed, the management means only needs to read the information according to the read instruction information.

Feature A5. Even if the management means receives the read instruction information having a higher priority than the read instruction information that triggered the reading of the information during the execution of reading the information, the management means continues to read the information during the execution. The gaming machine according to any one of features A1 to A4.

According to the feature A5, when the management means starts reading the information corresponding to the reading instruction information, the reading of the information is completed regardless of the subsequent reception status of the reading instruction information. This makes it possible to read out high-priority information at an early stage, but not to complicate the process for reading out the information.

Feature A6. One of the features A1 to A5, wherein the management means includes instruction information storage means (control side address buffer 114a, sound output side address buffer 114b) for storing the received read instruction information. The described gaming machine.

According to the feature A6, even if new read instruction information is received in the middle of reading the information, the new read instruction information can be stored in the instruction information storage means, so that the reading of the information is completed. In that case, it is possible to start reading new information at an early stage. Further, since the reading instruction information is stored in the instruction information storage means, if the reading instruction information having a high priority is stored in the instruction information storage means by the time the reading of the information is completed, the high priority reading is performed. The instruction information is the target for reading the information. Therefore, it is possible to increase the chance that the information corresponding to the high-priority read instruction information is read.

Feature A7. A first control means (control core 111) that executes the first control using the information stored in the storage means, and
A second control means (sound output core 112) that executes the second control using the information stored in the storage means, and
Equipped with
The determination means reads out the read instruction information received from the priority side control means among the first control means and the second control means, rather than the read instruction information received from the non-priority side control means. The gaming machine according to any one of features A1 to A6, which is characterized in that priority is given to determining a target.

According to the feature A7, the reading of information by the priority side control means among the first control means and the second control means can be prioritized over the reading of the information by the non-priority side control means.

Feature A8. The first control means includes a first request responding means (DMA123) for transmitting the read instruction information to the management means on condition that there is a request to read the information.
The second control means includes a second request responding means (data transfer unit 134) that transmits the read instruction information to the management means on condition that there is a request to read the information.
When the management means receives the read instruction information from at least the side corresponding to the control means on the non-priority side of the first request responding means and the second request responding means, the information corresponding to the read request is obtained. Reads out unit information, which is a small amount of information.
The determination of the read instruction information to be executed by the determination means may occur after the reading of the unit information is completed even if the reading of the information corresponding to the reading request is not completed. The gaming machine according to the feature A7.

According to the feature A8, at least for the control means on the non-priority side, the amount of information to be read is suppressed for one transmission of the read instruction information, and the reading of the information corresponding to the read request is completed. Even if this is not the case, when the reading of the information for one transmission of the reading instruction information is completed, the reading instruction information to be executed is determined while giving priority to the control means on the priority side. Information can be read out at an early stage by the control means on the priority side.

Feature A9. The gaming machine according to feature A8, wherein the unit information is the smallest unit of information that can be read out.

According to the feature A9, at least for the control means on the non-priority side, since the information to be read is the smallest unit of information that can be read for one transmission of the read instruction information, the read instruction to be executed is to be executed. It is possible to increase the frequency with which information decisions are made.

Feature A10. The first control means includes a first request responding means (DMA123) for transmitting the read instruction information to the management means on condition that there is a request to read the information.
The second control means includes a second request responding means (data transfer unit 134) that transmits the read instruction information to the management means on condition that there is a request to read the information.
Of the first request responding means and the second request responding means, at least the side corresponding to the control means on the non-priority side receives the read instruction information from the information corresponding to the read request by transmitting the read instruction information to the management means. The gaming machine according to any one of the features A7 to A9, characterized in that the reading of information with a small amount of information is instructed.

According to the feature A10, at least the control means on the non-priority side is configured to instruct to read out a smaller amount of information than the information corresponding to the read request by transmitting the read instruction information once, so that the amount of information is small. In a configuration in which the amount of information is positively read out, the management means only needs to read out the information according to the read instruction information.

Feature A11. Even if the management means receives the read instruction information having a higher priority than the read instruction information that triggered the reading of the information during the execution of reading the information, the management means continues to read the information during the execution. The gaming machine according to any one of the features A7 to A10.

According to the feature A11, when the management means starts reading the information corresponding to the reading instruction information, the reading of the information is completed regardless of the subsequent reception status of the reading instruction information. This makes it possible to read out high-priority information at an early stage, but not to complicate the process for reading out the information.

Feature A12. The management means includes instruction information storage means (control side address buffer 114a, sound output side address buffer 114b) for storing the read instruction information.
When the read instruction information received from the priority side control means is stored in the instruction information storage means at the information read start timing, the determination means sets the read instruction information as an execution target for reading the information. The gaming machine according to any one of the features A7 to A11.

According to the feature A12, for example, even if new read instruction information is received from the priority side control means while reading the information to the non-priority side control means, the new read instruction information is stored in the instruction information storage means. Therefore, when the reading of the information is completed, it is possible to start reading the information to the control means on the priority side at an early stage.

Feature A13. The management means
The priority side storage means (sound output side address buffer 114b) for storing the read instruction information received from the priority side control means, and
The non-priority side storage means (control side address buffer 114a) for storing the read instruction information received from the non-priority side control means, and the non-priority side storage means (control side address buffer 114a).
The gaming machine according to any one of the features A7 to A12.

According to the feature A13, the storage means for storing the read instruction information received from the priority side control means and the read instruction information received from the non-priority side control means are different. As a result, when the read instruction information is stored in the storage means on the priority side, the management means targets the read instruction information as the execution target for reading the information, and the read instruction information is not stored in the storage means on the priority side. In this case, the read instruction information stored in the storage means on the non-priority side may be set as the execution target for reading the information. That is, since it is possible to distinguish between the priority side and the non-priority side depending on the type of storage means, it is possible to simplify the process when the management means determines the execution target of reading information.

Feature A14. When at least one of the priority side control means and the non-priority side control means reads out the predetermined correspondence information for use in the predetermined period, the partial information of the predetermined correspondence information is read out. Adjustment means (data transfer unit 134, sequence data SD) that adjusts the transmission timing of the read instruction information so that a non-read period occurs from the completion to the start of reading other partial information in the predetermined correspondence information. ), The gaming machine according to any one of features A7 to A13.

According to the feature A14, even when the predetermined correspondence information for use in a predetermined period is read, the read instruction information is transmitted so that the read is performed in units of partial information, and one partial information. The read instruction information is transmitted so that a non-read period occurs between the completion of the reading of the information and the transmission of the read instruction information corresponding to the next partial information reading. This makes it possible to prevent the waiting period for reading information in the other control means from becoming long.

Feature A15. The gaming machine according to feature A14, wherein the one control means is the priority control means.

Since the control means on the priority side has priority over the control means on the non-priority side when determining the execution target for reading information, the control means on the priority side is read out to the control means on the priority side at an early stage, but the control on the priority side is performed. If the transmission of the read instruction information from the means is continued, the control means on the non-priority side is not given an opportunity to read the information, and the control means on the non-priority side waits for a long period of time to read the information. There is a possibility that it will end up. On the other hand, since the non-reading period is positively set in the control means on the priority side, the opportunity for reading the information is secured in the control means on the non-priority side, and a long period of time for waiting for reading the information is secured. The conversion is suppressed.

Feature A16. The adjusting means is adjustment information in which the transmission timing of the read instruction information for each partial information included in the predetermined correspondence information is predetermined.
The gaming machine according to feature A14 or A15, wherein the one control means transmits the read instruction information according to the transmission timing defined in the adjustment information.

According to the feature A16, the non-reading period can be generated only by transmitting the reading instruction information according to the adjustment information.

Feature A17. The gaming machine according to any one of features A14 to A16, wherein the adjustment is performed by the adjusting means so that the non-reading period becomes uniform in a predetermined continuous period.

According to the feature A17, since the non-reading period is set evenly, it is possible to evenly generate the reading opportunity of the information in the other control means.

Feature A18. One of the control means is
A plurality of sound information storage means (CH areas 143a to 143p, 144a to 144p) for storing sound information created by using the information read from the storage means, and
Output executing means (sound data processing unit 113, HWD132, SCM133) that controls the sound output means so that the sound corresponding to the sound information stored in the plurality of sound information storage means can be output at the same time.
Equipped with
The predetermined correspondence information is information for creating a plurality of sound information to be output at the same time in the predetermined period.
Described in any one of features A14 to A17, wherein the partial information is information used for creating a part of the sound information among a plurality of sound information corresponding to the predetermined correspondence information. Game machine.

According to the feature A18, in a configuration in which the information is read out in units of a part of the information when the information is read out for use in a predetermined period, the part of the information is one of a plurality of sound information to be output at the same time. This information is used to create the sound information of the club. That is, the information for creating one sound information is not divided, but is divided into some information units. This makes it possible to easily handle the read information even when the information is read in units of some information.

Feature A19. The gaming machine according to feature A18, wherein the partial sound information is sound information stored in one of the sound information storage means.

According to the feature A19, since the unit of some information is divided into the units of sound information, the frequency of occurrence of the non-reading period is increased while the divisional reading of the information for creating one sound information is not possible. Is possible.

Feature A20. Information used to create the predetermined period and each sound information so that the non-reading period occurs even when the sound is output using the maximum number of the sound information that can be simultaneously output. The gaming machine according to feature A18 or A19, characterized in that is set to.

According to the feature A20, it is possible to generate a non-reading period regardless of the type of sound information to be output at the same time.

Feature A21. In a configuration that does not require the predetermined period to read out the information necessary for outputting the sound for the predetermined period, the information necessary for outputting the sound for the predetermined period is read out in the predetermined period, while the predetermined period is read. The gaming machine according to any one of features A18 to A20, characterized in that information necessary for outputting sound exceeding the above amount is not read out.

According to the feature A21, since the information read in a predetermined period for sound output is limited to the information necessary for sound output for a predetermined period, the non-reading period can be maximized in the predetermined period. It will be possible.

Feature A22. One of the control means is
The first creation means (HWD132) that creates the first sound information using the information created in the first aspect and stores the first sound information in the first sound information storage means among the sound information storage means. When,
A second creation means (SCM133) that creates second sound information using the information created in the second aspect and stores the second sound information in the second sound information storage means among the sound information storage means. And, with
The predetermined period and the non-reading period occur regardless of whether the information for creating the first sound information is read or the information for creating the second sound information is read. The gaming machine according to any one of features A18 to A21, characterized in that information used for creating each sound information is set.

According to the feature A22, the non-reading period occurs regardless of whether the information for creating the first sound information is read or the information for creating the second sound information is read. Regardless of the type of sound information to be output, the other control means suppresses a long period of waiting for information to be read.

Feature A23. When the other control means of the priority side control means and the non-priority side control means reads out the specific correspondence information for use in a specific period, the specific correspondence regarding the transmission timing of the read instruction information. A feature characterized in that no adjustment is made so that a non-reading period occurs from the completion of reading a part of the information to the start of reading the other part of the specific correspondence information. The gaming machine according to any one of A14 to A22.

According to the feature A23, in the configuration in which the transmission timing of the read instruction information is adjusted by one control means, the transmission timing of the read instruction information is not adjusted by the other control means, so that the transmission timing is adjusted by both control means. The processing configuration can be simplified as compared with the configuration in which the above is performed.

Feature A24. The other control means, when reading the specific correspondence information, is characterized in that the read instruction information corresponding to each partial information included in the specific correspondence information is periodically transmitted. The gaming machine described in.

According to the feature A24, since the other control means only needs to periodically transmit the read instruction information corresponding to a part of the information until the reading of the specific correspondence information is completed, the other control means reads the information. The processing configuration of is simplified.

Feature A25. The storage means is
Program information (program data (1) to program data (L), processing data (1) to processing data (M), command data (1) necessary for executing a program in the first control means. ) ~ Command data (N)) and
The first control information (light emission data (1) to light emission data (P)) necessary for determining the control mode of the controlled object when the first control is executed according to the program.
The second control information (sound data (1) to sound data (Q)) necessary for determining the control mode of the controlled object when the second control means executes the second control,
Is at least remembered,
The first control means reads the program information to the first side storage means (RAM 122) during a period in which the first control information and the second control information read instruction are not generated (step S302 in the CPU 121). The gaming machine according to any one of features A7 to A24, characterized in that it is provided with a function of executing the processing of DMA123).

According to the feature A25, the program information can be read at an early stage by reading the program information during the period in which the reading instruction of the first control information and the second control information is not generated.

Feature A26. The gaming machine according to feature A25, wherein the reading means reads out the program information to the first side storage means when the supply of operating power to the first control means is started.

According to the feature A26, when the supply of the operating power to the first control means is started, all of the program information is read out to the first side storage means, so that the first control information and the second control information are subsequently read. It is possible to eliminate the need to read the program information at the timing when the information read instruction is generated.

Feature A27. The first control means is
After the program information is read out to the first-side storage means by the read-out means, the re-reading means (in the first embodiment, the step in the CPU 121) rereads the program-use information to the first-side storage means. The function of executing the process of S405 and DMA123, and in the second embodiment, the function of executing the process of step S905 in the CPU 121 and DMA123).
When the program information is newly read by the re-reading means, the means for limiting the reading of the first control information and the second control information (CPU 121 in the first embodiment). The function of executing the process of step S404 in the second embodiment, the function of executing the process of step S906 in the CPU 121 in the second embodiment, and the function of executing the process of step S1506 in the CPU 121 in the third embodiment).
The gaming machine according to the feature A26, which is characterized by the above.

According to the feature A27, the program information is read out again, so that the first control means can execute the program using the normal program information. In this case, when the program information is read again, the reading of the first control information and the second control information is restricted, so that the program information can be read again at an early stage.

Feature A28. The first control means includes a storage execution means for storing the information in the storage means (ring buffer of the RAM 122) when the information is received from the outside of the first control means, and the information stored in the storage means can be used. It is a configuration that executes the corresponding control.
Any of the features A25 to A27 characterized in that the information for the program is stored in the storage means by the storage execution means even in a situation where the information for the program is read out to the first side storage means. The gaming machine described in 1.

According to the feature A28, even when the information is received from the outside of the first control means in the situation where the program information is read out to the first side storage means, the information is stored in the storage means. Therefore, it is possible to prevent the information from being invalidated.

Feature A29. The first control means is
When the information confirmation timing comes after the program information is read into the first-side storage means, the confirmation means for confirming whether or not the program information has been rewritten (in the first embodiment, step S402 in the CPU 121). And a function of executing the process of step S403, in the second embodiment, a function of executing the process of step S902 and step S903 in the CPU 121, and in the third embodiment, a function of executing the process of step S1502 and step S1503 in the CPU 121). When,
When it is confirmed by the confirmation means that the rewriting of the program information has occurred, the re-reading means (first embodiment) for newly reading the program information to the first-side storage means. The function and DMA123 for executing the process of step S405 in the CPU 121, the function and DMA123 for executing the process of step S905 in the CPU 121 in the second embodiment, and the function and the function for executing the process of step S1505 in the CPU 121 in the third embodiment and DMA123) and
The gaming machine according to any one of the features A25 to A28, which comprises the above-mentioned feature A25 to A28.

According to the feature A29, if there is an abnormality in the program information read out by the first side storage means, the program information is read out again to the first side storage means, so that the program information is abnormal. Nevertheless, the possibility that the program will be executed by the first control means is reduced.

It should be noted that, with respect to the configuration of any one of the features A1 to A29, any one or a plurality of the features A1 to A29, the features B1 to B10, the features C1 to C5, the features D1 to D8, and the features E1 to E11 are used. May be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic B group>
Feature B1. A storage means (ROM103 for sound and light) that stores information in advance,
A first control means (control core 111) that executes the first control using the information stored in the storage means, and
A second control means (sound output core 112) that executes the second control using the information stored in the storage means, and
A management means (memory controller 114) that reads out the information corresponding to the read instruction information from the storage means when the read instruction information is received, and
Equipped with
When one of the first control means and the second control means reads out the predetermined correspondence information for use in the predetermined period, after the reading of a part of the predetermined correspondence information is completed. An adjustment means (data transfer unit 134, sequence data SD) for adjusting the transmission timing of the read instruction information so that a non-read period occurs before the start of reading some other information in the predetermined correspondence information is provided.
When the other control means of the first control means and the second control means reads the specific correspondence information for use in a specific period, the transmission timing of the read instruction information is one of the specific correspondence information. A gaming machine characterized in that no adjustment is made so that a non-reading period occurs between the completion of reading out part information and the start of reading out other partial information in the specific correspondence information.

According to the feature B1, even when the predetermined correspondence information for use in the predetermined period is read, the read instruction information is transmitted so that the read is performed in the unit of the partial information, and the partial information is one. The read instruction information is transmitted so that a non-read period occurs between the completion of the reading of the information and the transmission of the read instruction information corresponding to the reading of the next partial information. This makes it possible to prevent the waiting period for reading information in the other control means from becoming long.

Further, in the configuration in which the transmission timing of the read instruction information is adjusted by one control means, the transmission timing of the read instruction information is not adjusted by the other control means, so that the transmission timing is adjusted by both control means. Compared to the above, the processing configuration can be simplified.

Feature B2. The management means has priority over the read instruction information received from the one control means to the read instruction information received from the other control means when determining the execution target for reading the information (memory controller 114). The gaming machine according to feature B1, wherein the gaming machine is provided with a function of executing the processes of steps S810 to S813 in the above.

According to the feature B2, the reading of information by the priority side control means among the first control means and the second control means can be prioritized over the reading of the information by the non-priority side control means.

In this case, since the control means on the priority side has priority over the control means on the non-priority side when determining the execution target for reading information, the information is read out to the control means on the priority side at an early stage. When the transmission of the read instruction information from the priority side control means is continued, the non-priority side control means is not given an opportunity to read the information, and the non-priority side control means waits for the information read. May be prolonged. On the other hand, since the non-reading period is positively set in the control means on the priority side, the opportunity for reading the information is secured in the control means on the non-priority side, and a long period of time for waiting for reading the information is secured. The conversion is suppressed.

Feature B3. The adjusting means is adjustment information in which the transmission timing of the read instruction information for each partial information included in the predetermined correspondence information is predetermined.
The gaming machine according to feature B1 or B2, wherein the one control means transmits the read instruction information according to the transmission timing defined in the adjustment information.

According to the feature B3, the non-reading period can be generated only by transmitting the reading instruction information according to the adjustment information.

Feature B4. The gaming machine according to any one of features B1 to B3, wherein the adjustment is performed by the adjusting means so that the non-reading period becomes uniform in a predetermined continuous period.

According to the feature B4, since the non-reading period is set evenly, it is possible to evenly generate the reading opportunity of the information in the other control means.

Feature B5. The other control means, when reading the specific correspondence information, is characterized in that the read instruction information corresponding to each partial information included in the specific correspondence information is periodically transmitted. The gaming machine according to any one of B4.

According to the feature B5, since the other control means only needs to periodically transmit the read instruction information corresponding to a part of the information until the reading of the specific correspondence information is completed, the other control means reads the information. The processing configuration of is simplified.

Feature B6. One of the control means is
A plurality of sound information storage means (CH areas 143a to 143p, 144a to 144p) for storing sound information created by using the information read from the storage means, and
Output executing means (sound data processing unit 113, HWD132, SCM133) that controls the sound output means so that the sound corresponding to the sound information stored in the plurality of sound information storage means can be output at the same time.
Equipped with
The predetermined correspondence information is information for creating a plurality of sound information to be output at the same time in the predetermined period.
Described in any one of features B1 to B5, wherein the partial information is information used for creating a part of the sound information among a plurality of sound information corresponding to the predetermined correspondence information. Game machine.

According to feature B6, in a configuration in which information is read out in units of partial information when reading information for use in a predetermined period, the partial information is one of a plurality of sound information to be output at the same time. This information is used to create the sound information of the club. That is, the information for creating one sound information is not divided, but is divided into some information units. This makes it possible to easily handle the read information even when the information is read in units of some information.

Feature B7. The gaming machine according to feature B6, wherein the partial sound information is sound information stored in one of the sound information storage means.

According to the feature B7, since the unit of some information is divided into the units of sound information, the frequency of occurrence of the non-reading period is increased while the divisional reading of the information for creating one sound information is not possible. Is possible.

Feature B8. Information used to create the predetermined period and each sound information so that the non-reading period occurs even when the sound is output using the maximum number of the sound information that can be simultaneously output. The gaming machine according to feature B6 or B7, characterized in that is set to.

According to the feature B8, it is possible to generate a non-reading period regardless of the type of sound information to be output at the same time.

Feature B9. In a configuration that does not require the predetermined period to read out the information necessary for outputting the sound for the predetermined period, the information necessary for outputting the sound for the predetermined period is read out in the predetermined period, while the predetermined period is read. The gaming machine according to any one of features B6 to B8, characterized in that information necessary for outputting sound exceeding the above value is not read out.

According to the feature B9, since the information read in a predetermined period for sound output is limited to the information necessary for sound output for a predetermined period, the non-reading period can be maximized in the predetermined period. It will be possible.

Feature B10. One of the control means is
The first creation means (HWD132) that creates the first sound information using the information created in the first aspect and stores the first sound information in the first sound information storage means among the sound information storage means. When,
A second creation means (SCM133) that creates second sound information using the information created in the second aspect and stores the second sound information in the second sound information storage means among the sound information storage means. And, with
The predetermined period and the non-reading period occur regardless of whether the information for creating the first sound information is read or the information for creating the second sound information is read. The gaming machine according to any one of features B6 to B9, characterized in that information used for creating each sound information is set.

According to the feature B10, the non-reading period occurs regardless of whether the information for creating the first sound information is read or the information for creating the second sound information is read. Regardless of the type of sound information to be output, the other control means suppresses a long period of waiting for information to be read.

In addition, with respect to the configuration of any one of the features B1 to B10, any one or a plurality of the features A1 to A29, the features B1 to B10, the features C1 to C5, the features D1 to D8, and the features E1 to E11 are used. May be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic C group>
Features C1. A storage means (ROM103 for sound and light) that stores information in advance,
A first control means (control core 111) that executes the first control using the information stored in the storage means, and
A second control means (sound output core 112) that executes the second control using the information stored in the storage means, and
Equipped with
The storage means is
Program information (program data (1) to program data (L), processing data (1) to processing data (M), command data (1) necessary for executing a program in the first control means. ) ~ Command data (N)) and
The first control information (light emission data (1) to light emission data (P)) necessary for determining the control mode of the controlled object when the first control is executed according to the program.
The second control information (sound data (1) to sound data (Q)) necessary for determining the control mode of the controlled object when the second control means executes the second control,
Is at least remembered,
The first control means reads the program information to the first side storage means (RAM 122) during a period in which the first control information and the second control information read instruction are not generated (step S302 in the CPU 121). A gaming machine characterized by having a function of executing the processing of DMA123).

According to the feature C1, the program information can be read at an early stage by reading the program information during the period in which the reading instruction of the first control information and the second control information is not generated.

Feature C2. The gaming machine according to feature C1, wherein the reading means reads out the program information to the first side storage means when the supply of operating power to the first control means is started.

According to the feature C2, when the supply of the operating power to the first control means is started, all of the program information is read out to the first side storage means, so that the first control information and the second control information are subsequently read. It is possible to eliminate the need to read the program information at the timing when the information read instruction is generated.

Feature C3. The first control means is
After the program information is read out to the first-side storage means by the read-out means, the re-reading means (in the first embodiment, the step in the CPU 121) rereads the program-use information to the first-side storage means. The function of executing the process of S405 and DMA123, and in the second embodiment, the function of executing the process of step S905 in the CPU 121 and DMA123).
When the program information is newly read by the re-reading means, the means for limiting the reading of the first control information and the second control information (CPU 121 in the first embodiment). The function of executing the process of step S404 in the second embodiment, and in the second embodiment, the function of executing the process of step S906 in the CPU 121).
The gaming machine according to the feature C2, which is characterized by having.

According to the feature C3, the program information is read out again, so that the first control means can execute the program using the normal program information. In this case, when the program information is read again, the reading of the first control information and the second control information is restricted, so that the program information can be read again at an early stage.

Feature C4. The first control means includes a storage execution means for storing the information in the storage means (ring buffer of the RAM 122) when the information is received from the outside of the first control means, and the information stored in the storage means can be used. It is a configuration that executes the corresponding control.
Any of the features C1 to C3 characterized in that the information for the program is stored in the storage means by the storage execution means even in a situation where the information for the program is read out to the first side storage means. The gaming machine described in 1.

According to the feature C4, even when the information is received from the outside of the first control means in the situation where the program information is read out to the first side storage means, the information is stored in the storage means. Therefore, it is possible to prevent the information from being invalidated.

Feature C5. The first control means is
When the information confirmation timing comes after the program information is read into the first-side storage means, the confirmation means for confirming whether or not the program information has been rewritten (in the first embodiment, step S402 in the CPU 121). And the function of executing the process of step S403, and in the second embodiment, the function of executing the process of step S902 and step S903 in the CPU 121).
When it is confirmed by the confirmation means that the rewriting of the program information has occurred, the re-reading means (first embodiment) for newly reading the program information to the first-side storage means. The function and DMA123 for executing the process of step S405 in the CPU 121, and in the second embodiment, the function and DMA123) for executing the process of step S905 in the CPU 121.
The gaming machine according to any one of features C1 to C4, characterized in that

According to the feature C5, if there is an abnormality in the program information read out by the first side storage means, the program information is read out again to the first side storage means, so that the program information is abnormal. Nevertheless, the possibility that the program will be executed by the first control means is reduced.

In addition, with respect to the configuration of any one of the features C1 to C5, any one or a plurality of the features A1 to A29, the features B1 to B10, the features C1 to C5, the features D1 to D8, and the features E1 to E11 are used. May be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic D group>
Feature D1. A storage means (ROM103 for sound and light) that stores information in advance,
A management means (memory controller 114) that reads out the information corresponding to the read instruction information from the storage means when the read instruction information is received, and
A plurality of sound information storage means (CH areas 143a to 143p, 144a to 144p) for storing sound information created by using the information read from the storage means, and
Output executing means (sound data processing unit 113, HWD132, SCM133) that controls the sound output means so that the sound corresponding to the sound information stored in the plurality of sound information storage means can be output at the same time.
When reading the predetermined correspondence information for creating a plurality of sound information to be output at the same time in a predetermined period, among the plurality of sound information corresponding to the predetermined correspondence information by transmitting one of the read instruction information. Read instruction means (data) so that a part of the information used for creating a part of the sound information is read, and the whole of the predetermined correspondence information is read by transmitting the read instruction information a plurality of times. Transfer unit 134) and
A gaming machine characterized by being equipped with.

According to the feature D1, when the predetermined correspondence information is read, the reading instruction information is transmitted so that the predetermined correspondence information is read in units of some information. Therefore, the predetermined correspondence is performed even during the reading of the predetermined correspondence information. It is possible to create an opportunity for the management means to accept reading instruction information of information different from the information.

Further, in a configuration in which information is read out in units of some information when reading information for use in a predetermined period, the part information is part of sound information out of a plurality of sound information to be output at the same time. Information used to create. That is, some units of information are divided without dividing the information for creating one sound information. This makes it possible to easily handle the read information even when the information is read in units of some information.

Feature D2. The read instruction means has the read instruction information so that a non-read period occurs from the completion of reading the partial information of the predetermined correspondence information to the start of reading the other partial information in the predetermined correspondence information. The gaming machine according to feature D1, wherein the gaming machine is provided with an adjusting means (sequence data SD) for adjusting the transmission timing of the machine.

According to the feature D2, it is possible to secure a period during which the read instruction information of the information different from the information included in the predetermined correspondence information can be received even during the reading of the predetermined correspondence information.

Feature D3. The adjusting means is adjustment information in which the transmission timing of the read instruction information for each partial information included in the predetermined correspondence information is predetermined.
The gaming machine according to feature D2, wherein the read instruction means transmits the read instruction information according to the transmission timing defined in the adjustment information.

According to the feature D3, it is possible to generate a non-reading period only by transmitting the reading instruction information according to the adjustment information.

Feature D4. The gaming machine according to feature D2 or D3, wherein the adjustment is performed by the adjusting means so that the non-reading period becomes uniform in a predetermined continuous period.

According to the feature D4, since the non-reading period is set evenly, it is possible to evenly generate the reading opportunity of the information different from the predetermined correspondence information.

Feature D5. Information used to create the predetermined period and each sound information so that the non-reading period occurs even when the sound is output using the maximum number of the sound information that can be simultaneously output. The gaming machine according to any one of features D2 to D4, characterized in that is set to.

According to the feature D5, it is possible to generate a non-reading period regardless of the type of sound information to be output at the same time.

Feature D6. In a configuration that does not require the predetermined period to read out the information necessary for outputting the sound for the predetermined period, the information necessary for outputting the sound for the predetermined period is read out in the predetermined period, while the predetermined period is read. The gaming machine according to any one of features D2 to D5, characterized in that information necessary for outputting sound exceeding the above amount is not read out.

According to the feature D6, since the information read in a predetermined period for sound output is limited to the information necessary for sound output for a predetermined period, the non-reading period can be maximized in the predetermined period. It will be possible.

Feature D7. One of the control means is
The first creation means (HWD132) that creates the first sound information using the information created in the first aspect and stores the first sound information in the first sound information storage means among the sound information storage means. When,
A second creation means (SCM133) that creates second sound information using the information created in the second aspect and stores the second sound information in the second sound information storage means among the sound information storage means. And, with
The read instruction means is one of the read instruction information regardless of whether the information for creating the first sound information is read or the information for creating the second sound information is read. The gaming machine according to any one of features D1 to D6, characterized in that the partial information is read out by transmitting the above.

According to the feature D7, information different from the predetermined correspondence information is read out regardless of whether the information for creating the first sound information is read out or the information for creating the second sound information is read out. It is possible to create an opportunity for the management means to accept the instruction information.

Feature D8. The gaming machine according to any one of features D1 to D7, wherein the partial sound information is sound information stored in one of the sound information storage means.

According to the feature D8, since the unit of some information is divided into the units of sound information, the information different from the predetermined correspondence information can be read while the information for creating one sound information cannot be read separately. It is possible to generate many opportunities for receiving read instruction information.

In addition, with respect to the configuration of any one of the features D1 to D8, any one or a plurality of the features A1 to A29, the features B1 to B10, the features C1 to C5, the features D1 to D8, and the features E1 to E11 are used. May be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic E group>
Features E1. A first storage means (ROM103 for sound and light) that stores information in advance, and
A second storage means (program corresponding area 122a) in which predetermined information read from the first storage means is written, and
A predetermined control means (CPU121) that executes a predetermined control using the write information (a series of data corresponding to the program) written in the second storage means, and
When the information confirmation timing comes, the confirmation means for confirming whether or not the written information written in the second storage means is normal (in the first embodiment, the processes of steps S402 and S403 in the CPU 121 are performed. A function to execute, a function to execute the processes of steps S902 and S903 in the CPU 121 in the second embodiment, and a function to execute the processes of steps S1502 and S1503 in the CPU 121 in the third embodiment).
A gaming machine characterized by being equipped with.

According to the feature E1, in the configuration in which the predetermined control is executed by using the write information written from the first storage means to the second storage means, the write information written to the second storage means is normal. It is performed when the confirmation timing comes to confirm whether or not there is. As a result, if the write information written in the second storage means is abnormal, it is possible to take some measures, and there is a possibility that the predetermined control will continue to be executed as it is by using the abnormal write information. Is reduced.

Feature E2. When it is confirmed by the confirmation means that the write information is not normal, the rewrite means for newly writing the write information to the second storage means (in the first embodiment, step S405 in the CPU 121). It has a function to execute processing and DMA123, a function to execute the processing of step S905 in the CPU 121 in the second embodiment and DMA123, and a function to execute the processing in step S1505 in the CPU 121 and DMA123 in the third embodiment. The gaming machine according to the feature E1.

According to the feature E2, when there is an abnormality in the writing information written in the second storage means, the writing of the writing information in the second storage means is executed again, so that the writing information is abnormal. However, the possibility that the written information will continue to be used in the predetermined control means is reduced.

Feature E3. When the write information is newly written by the rewrite means, the means for restricting the reading of information different from the write information from the first storage means (in the first embodiment, step S404 in the CPU 121). The function of executing the process of step S906 in the CPU 121 in the second embodiment, and the function of executing the process of step S1506 in the CPU 121 in the third embodiment) are provided. Feature The gaming machine described in E2.

According to the feature E3, when the written information is written again, the reading of the information different from the written information is restricted, so that the written information can be rewritten at an early stage.

Feature E4. The write information includes program information (program data (1) to program data (L), processing data (1) to processing data (M), which are necessary for executing a program in the predetermined control means. Includes command data (1) to command data (N))
When the writing information is newly written by the rewriting means, the predetermined control means uses the information stored in the third storage means (directly attached ROM 201) to perform a writing process (steps S1504 to CPU 121). The gaming machine according to feature E2 or E3, characterized in that the function of executing the process of step S1508) is executed.

According to the feature E4, when the program is executed by the predetermined control means, the program information written in the second storage means may be referred to, so that the program information is directly read from the first storage means when the program is executed. No need arises.

In this case, a third storage means is provided separately from the first storage means and the second storage means, and in a situation where the written information is being rewritten, the information stored in the third storage means is used. Then, the processing during writing is executed. As a result, it is not necessary to perform rewriting in such a manner that the processing during writing can be executed when rewriting the writing information. Therefore, it is possible to satisfactorily rewrite the writing information.

Feature E5. The confirmation means reads the same information as the written information from the first storage means and specifies whether or not the read information and the written information match, so that the written information is normal. The gaming machine according to any one of features E1 to E4, characterized in that it is confirmed whether or not it is.

According to the feature E5, when determining whether or not the written information written in the second storage means is normal, the information corresponding to the written information stored in the first storage means is directly read out. Since the information is collated, it is possible to accurately determine whether or not it is normal.

Feature E6. Means for reading the same information as the written information from the first storage means and writing it to the confirmation storage means (general-purpose area 122b) (in the first embodiment, the function of executing the process of step S307 in the CPU 121 and the DMA 123, the third In the embodiment of the above, the function of executing the process of step S1214 in the CPU 121) is provided.
The confirmation means is characterized in that after all the writing of the same information as the writing information to the confirmation storage means is completed, a process for confirming whether or not the writing information is normal is executed. Features The gaming machine according to E5.

According to the feature E6, when determining whether or not the written information written in the second storage means is normal, all of the same information as the written information is first read from the first storage means and confirmed. The information written in the storage means for confirmation and then written in the storage means for confirmation is used to determine whether or not the written information is normal. This makes it possible to collectively write information to the confirmation storage means, as compared with a configuration in which information is sequentially written to the confirmation storage means according to the progress of determination as to whether or not it is normal. It is possible to simplify the processing configuration for instructing the writing of information to the confirmation storage means.

Feature E7. Even if it is time to read the same information in a situation where information different from the same information is being read, the feature E5 or the feature E5 is characterized in that the writing of the different information is prioritized. The gaming machine described in E6.

According to the feature E7, it is possible to prioritize the reading of other information over the information for performing the normality determination. As a result, it is possible to execute the normal determination while giving priority to the execution of the process different from the normal determination.

Feature E8. Features E5 to E7 are characterized in that when it is time to read out information different from the same information in a situation where the same information is being read out, the reading of the different information is prioritized. The gaming machine according to any one of.

According to the feature E8, it is possible to prioritize the reading of other information over the information for performing the normality determination. As a result, it is possible to execute the normal determination while giving priority to the execution of the process different from the normal determination.

Feature E9. The gaming machine according to any one of features E1 to E8, wherein the confirmation means confirms whether or not a part of the written information is normal in one confirmation process.

According to the feature E9, since it is determined whether or not a part of the written information is normal in one confirmation process, whether or not it is normal after confirming all of the written information. It is possible to deal with the occurrence of an abnormality earlier than the configuration in which the determination is made.

Feature E10. The predetermined control means includes a storage execution means (a function of executing command interrupt processing in the CPU 121) for storing the information in the storage means (ring buffer 122c) when the information is received from the outside of the predetermined control means. It is a configuration that executes control corresponding to the information stored in the storage means.
Any of the features E1 to E9 characterized in that the information is stored in the storage means by the storage execution means even in a situation where the writing of the writing information to the second storage means is being executed. The gaming machine described in 1.

According to the feature E10, even when the information is received from the outside of the predetermined control means in the situation where the write information is written to the second storage means, the information is stored in the storage means and can be used. Therefore, it is possible to prevent the information from being invalidated.

Feature E11. The gaming machine according to any one of features E1 to E10, wherein the written information includes program information necessary for executing a program in the predetermined control means.

According to the feature E11, when the program is executed by the predetermined control means, the program information written in the second storage means may be referred to, so that the program information is directly read from the first storage means when the program is executed. No need arises.

In addition, with respect to the configuration of any one of the features E1 to E11, any one or a plurality of the features A1 to A29, the features B1 to B10, the features C1 to C5, the features D1 to D8, and the features E1 to E11 are used. May be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

The invention of the feature A group, the invention of the feature B group, the invention of the feature C group, the invention of the feature D group and the invention of the feature E group can solve the following problems.

Pachinko gaming machines, slot machines, and the like are known as a type of gaming machine. These gaming machines include a general-purpose control element such as a CPU and a read-only storage element such as a ROM, and a series of processes are executed by the general-purpose control element according to a program read from the read-only storage element. The game is controlled. It is also known that a general-purpose control element, a read-only storage element, and the like are integrated into a single chip.

Further, there is also known a configuration in which a dedicated control element is used as a control element for performing sound output control and display control. In this case, the operation of the controlled device is controlled based on the processing being executed by the dedicated control element according to the data read from the read-only storage element.

Here, in a gaming machine such as the above example, it is necessary to suitably read information from a storage means, and there is still room for improvement in this respect.

The following shows the basic configuration of a gaming machine to which each of the above features can be applied or is applied to each feature.

Pachinko gaming machine: An operating means operated by a player, a game ball launching means for launching a game ball based on the operation of the operating means, a ball passage for guiding the launched game ball to a predetermined game area, and a game. A gaming machine that includes each gaming component arranged in an area and grants a privilege to a player when a gaming ball passes through a predetermined passing portion of each gaming component.

Rotating machine such as a slot machine: Equipped with a picture display device that variably displays a plurality of pictures, the variable display of the plurality of pictures is started due to the operation of the start operation means, and is caused by the operation of the stop operation means. A gaming machine in which the variable display of the plurality of symbols is stopped after a lapse of a predetermined time, and a privilege is given to the player according to the symbols after the stop.

10 ... Pachinko machine, 103 ... ROM for sound and light, 111 ... Control core, 112 ... Sound output core, 113 ... Sound data processing unit, 114 ... Memory controller, 114a ... Control side address buffer, 114b ... Sound output side address buffer, 121 ... CPU, 122 ... RAM, 122a ... Program compatible area, 122b ... General purpose area, 122c ... Ring buffer, 123 ... DMA, 132 ... HWD, 133 ... SCM, 134 ... Data transfer unit, 143a to 143p, 144a to 144p ... CH area, 201 ... Directly attached ROM, SD ... Sequence data.

Claims (1)

A storage means for storing information in advance,
A first control means that executes the first control using the information stored in the storage means, and
A second control means that executes the second control using the information stored in the storage means, and
Equipped with
The storage means is
Information for the program necessary for executing the program in the first control means and
The first control information necessary for determining the control mode of the controlled object when the first control is executed according to the program, and
The second control information necessary for determining the control mode of the controlled object when executing the second control in the second control means, and
Is at least remembered,
The first control means is characterized by comprising a reading means for reading the program information to the first side storage means during a period in which the reading instruction of the first control information and the second control information is not generated. A game machine to play.

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