JP2022077406A - Method of manufacturing nitride semiconductor device, and nitride semiconductor device - Google Patents

Abstract

To provide a method of manufacturing a nitride semiconductor device capable of having a P-type region with high density and small variance in density, and the nitride semiconductor device.SOLUTION: A method of manufacturing a nitride semiconductor device comprises the processes of: injecting ions of an acceptor element into a nitride semiconductor; forming a protective film on the nitride semiconductor after the ion injection of the acceptor element; and performing a heat treatment on the nitride semiconductor having the protective film formed to activate the acceptor elements, and thus forming a P-type region in the nitride semiconductor. The protective film is formed of an N-type semiconductor.SELECTED DRAWING: Figure 4D

Description

The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

A nitride semiconductor device having a vertical MOS (Metal Oxide Semiconductor) structure is known (see, for example, Patent Document 1). Further, in the nitride semiconductor device, P-type conductivity can be controlled by using magnesium (Mg) as a dopant (see, for example, Patent Document 2).

In a nitride semiconductor device, in order to realize good ohmic contact, it is necessary to selectively form a high-concentration P-type region in the nitride semiconductor. As a method for selectively forming a P-type region, ion implantation is desirable from the viewpoint of cost, productivity, and reliability. However, when Mg is ion-implanted into a nitride semiconductor at a high concentration and heat treatment is performed at a high temperature exceeding 1300 ° C. to activate Mg, Mg is segregated in a rod shape at high density. When Mg segregates in a rod shape at a high density, the Mg concentration decreases in a region other than the region where segregation occurs (see, for example, Non-Patent Document 1). Further, when the heat treatment is further performed in an ultra-high pressure atmosphere at a high temperature exceeding 1400 ° C., Mg diffuses deeply and the concentration decreases (see, for example, Non-Patent Document 2). Therefore, it has been difficult to form a P-type region having a high concentration and a small variation in concentration by ion implantation.

Japanese Unexamined Patent Publication No. 2019-096744 Japanese Unexamined Patent Publication No. 2014-08698

Kumar et. al. , J. Apple. Phys. 126 (2019) 235704. H. Sakurai et. al. , Apple. Phys. Let. 115, 142104 (2019). G. Miceli, A. Pasqualello PRB (2016).

When Mg is activated by the heat treatment and becomes a P-type region, the Fermi level in the P-type region approaches the valence band. As the Fermi level approaches the valence band, the energy for forming Mg acceptors (ie, the energy required to put Mg into the Ga site of GaN) increases and the activation of Mg becomes unstable (eg, non-patented). See Document 3). It is considered that the above-mentioned high-density segregation of Mg is caused by unstable activation of Mg and easy segregation of Mg through defects.

The present invention has been devised by the present inventor based on such an idea, and is a method for manufacturing a nitride semiconductor device capable of realizing a P-type region having a high concentration and a small variation in concentration. It is an object of the present invention to provide a nitride semiconductor device.

In order to solve the above problems, the method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes a step of ion-injecting an acceptor element into a nitride semiconductor and an ion-injected nitride semiconductor onto the nitride semiconductor. It comprises a step of forming a protective film and a step of forming a P-type region in the nitride semiconductor by subjecting the nitride semiconductor on which the protective film is formed to heat treatment to activate the acceptor element. .. The protective film is made of an N-type semiconductor.

The nitride semiconductor device according to one aspect of the present invention includes a nitride semiconductor and a P-type region provided in the nitride semiconductor. The concentration of the acceptor element in the P-type region is 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less. The density of acceptor segregation in the surface layer portion of the P-type region is lower than the density of the acceptor segregation in the portion deeper than the surface layer portion in the P-type region.

According to the present invention, it is possible to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of realizing a P-type region having a high concentration and a small variation in concentration.

FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view showing a configuration example of the vertical MOSFET according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a configuration example of the vertical MOSFET according to the first embodiment of the present invention. FIG. 4A is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of processes. FIG. 4B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of processes. FIG. 4C is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of processes. FIG. 4D is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of processes. FIG. 4E is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of processes. FIG. 4F is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of processes. FIG. 4G is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of processes. FIG. 5 is a band diagram of the contact portion between the GaN and the protective film (N-type semiconductor) and its vicinity, and shows the valence band, conduction band, and Fermi before and after the heat treatment for activating the acceptor element. It is a figure which shows the level. FIG. 6 is a band diagram of GaN when the protective film is an insulating film, showing valence bands, conduction bands, and Fermi levels before and after heat treatment for activating acceptor elements. be. FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN. FIG. 8 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a modified example of the first embodiment of the present invention. FIG. 9 is a cross-sectional view showing a configuration example of the GaN semiconductor device according to the second embodiment of the present invention. FIG. 10A is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of processes. FIG. 10B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of processes. FIG. 10C is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of processes. FIG. 10D is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of processes. FIG. 10E is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of processes. FIG. 11 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a modified example of the second embodiment of the present invention.

An embodiment of the present invention will be described below. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

Further, in the following description, the direction may be described by using the words in the X-axis direction, the Y-axis direction, and the Z-axis direction. For example, the X-axis direction and the Y-axis direction are directions parallel to the surface 10a of the GaN substrate 10 described later. The X-axis direction and the Y-axis direction are also referred to as horizontal directions. The Z-axis direction is a direction perpendicularly intersecting the surface 10a of the GaN substrate 10. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

Further, in the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down". "Top" and "bottom" do not necessarily mean vertical to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. "Upper" and "lower" are merely expedient expressions for specifying relative positional relationships in regions, layers, films, substrates, and the like, and do not limit the technical idea of the present invention. For example, if the paper surface is rotated 180 degrees, it goes without saying that "upper" becomes "lower" and "lower" becomes "upper".

Further, in the following description, + and-attached to P and N indicating the conductive type are semiconductor regions having a relatively high or low impurity concentration as compared with the semiconductor regions not marked with + and-, respectively. Means. However, even if the semiconductor regions have the same P and P (or N and N), it does not mean that the impurity concentrations of the respective semiconductor regions are exactly the same.

<Embodiment 1>
(Configuration example)
FIG. 1 is a plan view showing a configuration example of a gallium nitride semiconductor device according to the first embodiment of the present invention (an example of the “nitride semiconductor device” of the present invention; hereinafter, a GaN semiconductor device) 100. FIG. 1 is a plan view of XY. As shown in FIG. 1, the GaN semiconductor device 100 has an active region 110 and an edge termination region 130. The active region 110 has a gate pad 112 and a source pad 114. The gate pad 112 and the source pad 114 are electrode pads electrically connected to the gate electrode 23 and the source electrode 25, which will be described later, respectively.

In a plan view from the Z-axis direction, the edge termination region 130 surrounds the active region 110. The edge termination region 130 may have one or more of a guard ring structure and a JTE (Junction Termination Extension) structure. The edge termination region 130 may have a function of preventing electric field concentration in the active region 110 by expanding the depletion layer generated in the active region 110 to the edge termination region 130.

FIG. 2 is a plan view showing a configuration example of the vertical MOSFET 1 according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a configuration example of the vertical MOSFET 1 according to the first embodiment of the present invention. FIG. 2 shows a part of the active region 110 shown in FIG. 1 in an enlarged manner, and shows the shapes of the gate electrode 23 and the source electrode 25 in a plan view from the Z-axis direction. Therefore, the gate pad 112 and the source pad 114 are shown. Is omitted. FIG. 3 shows a cross section of the plan view of FIG. 2 cut along the XX'line.

The GaN semiconductor device 100 shown in FIGS. 2 and 3 includes a gallium nitride substrate (an example of the “nitride semiconductor” of the present invention; hereinafter, a GaN substrate) 10 and a plurality of vertical MOSFETs 1 (present) provided on the GaN substrate 10. An example of the "electric field effect transistor" of the present invention). In the GaN semiconductor device 100, the vertical MOSFET 1 is repeatedly provided in one direction (for example, the X-axis direction). One vertical MOSFET 1 is a repeating unit structure, and the unit structures are arranged side by side in one direction (for example, the X-axis direction).

As shown in FIGS. 2 and 3, the vertical MOSFET 1 includes an N-type drift region 12, a P-type well region 14, and a P + -type contact region 16 provided on the GaN substrate 10 (“P-type” of the present invention. An example of a region ”), an N + type source region 18, a gate insulating film 21 provided on the surface 10a of the GaN substrate 10, a gate electrode 23 provided on the gate insulating film 21, and the surface of the GaN substrate 10. The source electrode 25 (an example of the "electrode" of the present invention) provided on the 10a side and electrically connected to the contact region 16 and the source region 18 and the drift region 12 provided on the back surface 10b side of the GaN substrate 10 are electrically connected. It has a drain electrode 27 and a drain electrode 27 which are connected to each other.

The GaN substrate 10 is a GaN single crystal substrate. The GaN substrate 10 is, for example, an N− type substrate. The GaN substrate 10 has a front surface 10a and a back surface 10b located on the opposite side of the front surface 10a. For example, the GaN substrate 10 is a low dislocation self-supporting GaN substrate having a through-dislocation density of less than 1 × 10 ⁷ cm ^-2 .

The donor element (N-type impurity) contained in the GaN substrate 10 may be one or more of Si (silicon), Ge (germanium), and O (oxygen). Further, the acceptor element (P-type impurity) contained in the GaN substrate 10 may be one or more kinds of elements such as Mg (magnesium), Ca (calcium), Be (beryllium) and Zn (zinc).

Since the GaN substrate 10 is a low dislocation self-supporting GaN substrate, the leakage current in the power device can be reduced even when a power device having a large area is formed on the GaN substrate 10. This makes it possible to manufacture power devices at a high non-defective rate. Further, in the heat treatment included in the manufacturing process of the vertical MOSFET 1, it is possible to prevent the ion-implanted impurities from deeply diffusing along the dislocations.

The GaN substrate 10 may be N-type instead of N-type. Further, the GaN substrate 10 may include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. In this case, the GaN single crystal substrate may be N + type or N type, and the GaN layer may be N type or N− type. Further, the GaN single crystal substrate may be a low dislocation self-supporting GaN substrate.

In the vertical MOSFET 1, the GaN substrate 10 may contain one or more elements of aluminum (Al) and indium (In). The GaN substrate 10 may be a mixed crystal semiconductor containing a small amount of Al and In in GaN, that is, AlxInyGa1-x-yN (0 ≦ x <1, 0 ≦ y <1). Note that GaN is the case where x = y = 0 in AlxInyGa1-x−yN.

The GaN substrate 10 is provided with a drift region 12, a well region 14, a contact region 16, and a source region 18, respectively. The well region 14, the contact region 16, and the source region 18 are regions in which impurities are ion-implanted from the surface 10a of the GaN substrate 10 to a predetermined depth and the impurities are activated by heat treatment, respectively.

For example, the contact region 16 is provided on the surface side of the well region 14. The well region 14 is a P-shaped region, and the contact region 16 is a P + -shaped region. The contact region 16 has a higher concentration of P-type impurities than the well region 14. The well region 14 and the contact region 16 contain at least one of Mg and Be as an acceptor element.

For example, the well region 14 and the contact region 16 contain Mg as an acceptor element. The concentration of Mg in the well region 14 is 1 × 10 ¹⁶ cm ^-3 or more and 3 × 10 ¹⁸ cm ^-3 or less. The concentration of Mg in the contact region 16 is 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less.

The drift region 12 is an N− type region, and the source region 18 is an N + type region. The source region 18 has a higher concentration of N-type impurities than the drift region 12. The drift region 12 and the source region 18 contain, for example, Si as N-type impurities. For example, the N-type impurity concentration in the drift region 12 is the same as the N-type impurity concentration in the GaN substrate 10. In this case, the drift region 12 may not be ion-implanted with N-type impurities. The concentration of Si in the drift region 12 is 1 × 10 ¹⁵ cm ^-3 or more and 1 × 10 ¹⁷ cm ^-3 or less.

The source region 18 is provided on the surface side of the well region 14. The source region 18 is formed by ion-implanting Si into the surface side of the well region 14 and activating Si by heat treatment. The concentration of Si in the source region 18 is 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²² cm ^-3 or less.

The upper portion of the source region 18 is exposed on the surface 10a of the GaN substrate 10. The source region 18 has one side portion in the X-axis direction and the other side portion located on the opposite side in the X-axis direction. One side and bottom of the source region 18 are in contact with the well region 14, and the other side of the source region 18 is in contact with the contact region 16. One side of the source region 18 is located on the 141 side of the region (hereinafter referred to as the channel region) in which the channel of the vertical MOSFET 1 is formed. The channel of the vertical MOSFET 1 is formed in the well region 14.

The contact region 16 is exposed on the surface 10a of the GaN substrate 10. Both sides of the contact region 16 in the X-axis direction are in contact with the source region 18, and the bottom portion is in contact with the well region 14. The well region 14, the contact region 16 and the source region 18 have a striped shape extending in the Y-axis direction.

The upper portion (hereinafter, upper region) 121 of the drift region 12 is exposed on the surface 10a of the GaN substrate 10. The upper region 121 is in contact with the gate insulating film 21 on the surface 10a. The upper region 121 is located between a pair of well regions 14 facing each other in the Y-axis direction. The upper region 121 may be referred to as a JFET region. The upper region 121 may be N-shaped instead of N-shaped. As a result, the on-resistance of the vertical MOSFET 1 can be reduced.

The lower portion (hereinafter, lower region) 122 of the drift region 12 is in contact with the bottom of the well region 14. The lower region 122 is located between the upper region 121 and the drain electrode 27, and between the well region 14 and the drain electrode 27, respectively. The lower region 122 is continuously provided in the X-axis direction among a plurality of vertical MOSFETs 1 (that is, a plurality of unit structures) that are repeated in the X-axis direction.

The drift region 12 functions as a current path between the drain electrode 27 and the channel region 141. The contact region 16 is a region for making contact between the well region 14 and the electrode (for example, the source electrode 25). The contact region 16 also functions as a hole extraction path at the time of gate off.

The gate insulating film 21 is, for example, a silicon oxide film (SiO ₂ film). The gate insulating film 21 is provided on, for example, a flat surface 10a.

The gate electrode 23 is provided above the channel region 141 via the gate insulating film 21. For example, the gate electrode 23 is a planar type provided on a flat gate insulating film 21. The gate electrode 23 is made of a material different from that of the gate pad 112. The gate electrode 23 is formed of impurity-doped polysilicon, and the gate pad 112 is formed of an alloy of Al or Al—Si.

The source electrode 25 is provided on the surface 10a of the GaN substrate 10. The source electrode 25 is in contact with a part of the source region 18 and the contact region 16. The source electrode 25 may also be provided on the gate electrode 23 via an interlayer insulating film (not shown). The interlayer insulating film may cover the upper portion and the side portion of the gate electrode 23 so that the gate electrode 23 and the source electrode 25 are not electrically connected.

The source electrode 25 is made of the same material as the source pad 114. For example, the source electrode 25 made of an alloy of Al or Al—Si also serves as the source pad 114. The source electrode 25 may have a barrier metal layer between the surface 10a of the GaN substrate 10 and Al (or Al—Si). Titanium (Ti) may be used as the material of the barrier metal layer. The drain electrode 27 is provided on the back surface 10b side of the GaN substrate 10 and is in contact with the back surface 10b. The drain electrode 27 is also made of the same material as the source electrode 25.

In FIG. 3, the gate terminal, the source terminal, and the drain terminal are indicated by G, D, and S, respectively. For example, when a potential equal to or higher than the threshold voltage is applied to the gate electrode 23 via the gate terminal G, an inversion layer is formed in the channel region 141. When a predetermined high potential is applied to the drain electrode 27 and a low potential (for example, a ground potential) is applied to the source electrode 25 in a state where the inversion layer is formed in the channel region 141, the source is supplied from the drain terminal D. Current flows to the terminal S. Further, when a potential lower than the threshold voltage is applied to the gate electrode 23, the inversion layer is not formed in the channel region 141, and the current is cut off. As a result, the vertical MOSFET 1 can switch the current between the source terminal S and the drain terminal D.

In the GaN semiconductor device 100 shown in FIGS. 1 to 3, the contact region 16 has a surface layer portion with less Mg segregation. The depth of the surface layer portion from the surface 10a is 1 nm or more and 30 nm or less. The density of Mg segregation in the surface layer portion of the contact region 16 is lower than the density of Mg segregation in the portion deeper than the surface layer portion (hereinafter referred to as the deep portion) in the contact region 16.

For example, Mg segregation is classified into rod-shaped Mg segregation and non-rod-shaped Mg segregation. The rod-shaped Mg segregation is a segregation having a length of 30 nm or more in one direction and a Mg concentration of 5 × 10 ²⁰ cm ^-3 or more. Non-rod-shaped Mg segregation is segregation in which the length in one direction is less than 30 nm and the Mg concentration is 5 × 10 ²⁰ cm ^-3 or more. In the surface layer portion of the contact region 16, the density of rod-shaped acceptor segregation is 1 × 10 ¹⁴ cm ^-3 or less, and the density of non-rod-shaped acceptor segregation is less than 1 × 10 ¹⁵ cm ^-3 . The density of rod-shaped acceptor segregation and the density of non-rod-shaped acceptor segregation in the deep part of the contact region 16 are higher than each density in the surface layer portion of the contact region 16.

As will be described later, this is realized by covering the surface of the contact forming region 16'with a protective film (N-type semiconductor) in advance when the Mg ion-implanted into the contact forming region 16'is activated by heat treatment. Will be done. By bringing the protective film (N-type semiconductor) into contact with the contact forming region 16', a depletion layer is formed on the surface layer of the contact forming region 16', and the Fermi level in the depletion layer is suppressed from approaching the valence band. (More preferably, it is closer to the conduction band). As a result, Mg segregation of the surface layer portion of the contact region 16 is suppressed.

(Production method)
Next, a method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention will be described. 4A to 4G are cross-sectional views showing the manufacturing method of the GaN semiconductor device 100 according to the first embodiment of the present invention in the order of processes. Note that FIGS. 4A to 4G show the manufacturing method of one of the plurality of vertical MOSFETs 1 repeatedly arranged in the X-axis direction in the order of processes. Further, the GaN semiconductor device 100 is manufactured by various devices such as a film forming device, an exposure device, an etching device, an ion implantation device, and a heat treatment device. Hereinafter, these devices are collectively referred to as manufacturing devices.

As shown in FIG. 4A, the manufacturing apparatus ion-implants Mg as an acceptor element into the region (hereinafter, well-forming region) 14 ′ in which the well region 14 (see FIG. 3) is formed in the GaN substrate 10. For example, the manufacturing apparatus forms the mask M1 on the surface 10a of the GaN substrate 10. The mask M1 is a SiO ₂ film or a photoresist that can be selectively removed from the GaN substrate 10. The mask M1 has a shape that opens above the well-forming region 14'and covers above the other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M1 is formed. After ion implantation, the manufacturing apparatus removes the mask M1 from the GaN substrate 10.

In the step shown in FIG. 4A, the injection energy (acceleration voltage) is set so that the depth from the surface 10a of the GaN substrate 10 to the injection peak position is 200 nm or more and 1500 nm or less, and as an example, it is 500 nm. Further, in this step, the dose amount of Mg is set so that the Mg concentration at the implantation peak position of the ion-implanted Mg is 1 × 10 ¹⁶ cm ^-3 or more and 3 × 10 ¹⁸ cm ^-3 or less.

Alternatively, in the step shown in FIG. 4A, Mg is injected so that not only the injection peak position but also the Mg concentration in the entire well forming region 14'is 1 × 10 ¹⁶ cm ^-3 or more and 3 × 10 ¹⁸ cm ^-3 or less. Energy and dose amount may be set. The step shown in FIG. 4A may be performed by one-stage ion implantation in which the acceleration energy is one condition, or may be performed by multi-stage ion implantation in which the acceleration energy is a plurality of conditions.

Next, as shown in FIG. 4B, the manufacturing apparatus ion-implants Mg as an acceptor element into the region where the contact region is formed (hereinafter referred to as the contact formation region) 16'in the GaN substrate 10. For example, the manufacturing apparatus forms the mask M2 on the GaN substrate 10. The mask M2 is a SiO ₂ film or a photoresist. The mask M2 has a shape that opens above the contact forming region 16'and covers above the other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M2 is formed. After ion implantation, the manufacturing apparatus removes the mask M2 from the GaN substrate 10.

In the step shown in FIG. 4B, the injection energy (acceleration voltage) is set so that the depth from the surface 10a of the GaN substrate 10 to the injection peak position is 1 nm or more and 200 nm or less, and as an example, it is 10 nm or more and 100 nm or less. .. Further, in this step, the Mg concentration at the injection peak position of the ion-injected Mg is 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less, and is 1 × 10 ²⁰ cm ^-3 as an example. As described above, the dose amount of Mg is set.

Alternatively, in the step shown in FIG. 4B, the Mg concentration not only at the injection peak position but also in the entire contact forming region 16'is 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less, and 1 × 10 as an example. The injection energy of Mg and the dose amount may be set so as to be ²⁰ cm ^-3 . The step shown in FIG. 4B may be performed by one-stage ion implantation using a single acceleration energy, or may be performed by multi-stage ion implantation using different acceleration energies.

Next, as shown in FIG. 4C, the manufacturing apparatus forms the protective film 30 on the surface 10a of the GaN substrate 10. As a result, at least the contact forming region 16'on the surface 10a of the GaN substrate 10 comes into direct contact with the protective film 30. The surfaces of the well forming region 14'and the upper region 121 may be in direct contact with the protective film 30 or may be covered with an insulating film (not shown).

The protective film 30 is made of an N + type semiconductor (an example of the "N-type semiconductor" of the present invention). For example, the protective film 30 is made of N + type aluminum nitride (AlN) or N + type silicon nitride (SiN). AlN or SiN has high heat resistance, has good adhesion to the GaN substrate 10, impurities do not diffuse from the protective film 30 to the GaN substrate 10, and can be selectively removed from the GaN substrate 10. Therefore, it is suitable for the protective film 30.

The concentration of the donor element (for example, Si) contained in the protective film 30 is, for example, 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less. The concentration of the donor element contained in the protective film 30 may be a value equal to or higher than the concentration of the acceptor element ion-implanted into the contact forming region 16'.

The thickness of the protective film 30 at the time of film formation is a value equal to or greater than the depth from the surface of the surface layer portion of the contact forming region 16'(or the contact region 16 (see FIG. 3)). For example, the lower limit of the thickness of the protective film 30 is 1 nm when the depth of the surface layer portion of the contact forming region 16'(or the contact region 16) is 1 nm, and when the depth of the surface layer portion is 30 nm. It is 30 nm. The upper limit of the thickness of the protective film 30 is not particularly limited, but the upper limit is 1 μm from the viewpoint of suppressing a decrease in the film formation throughput of the protective film 30 and suppressing the occurrence of warpage or the like on the GaN substrate 10. It is preferably 500 nm, and more preferably 500 nm. From the above, as an example, the thickness of the protective film 30 at the time of film formation is 1 nm or more and 1 μm or less, and more preferably 1 nm or more and 500 nm or less.

Next, the manufacturing apparatus heat-treats the GaN substrate 10 covered with the protective film 30 at a maximum temperature of 1300 ° C. or higher and 2000 ° C. or lower. This heat treatment is, for example, a rapid heat treatment. This heat treatment activates the Mg ion-implanted into the GaN substrate 10, and as shown in FIG. 4D, the P-type well region 14 and the P + -type contact region 16 are formed on the GaN substrate 10, and the P + type contact region 16 is formed. The drift region 12 is defined. Further, by this heat treatment, the defects caused by the ion implantation of Mg in the GaN substrate 10 can be recovered to some extent. After the heat treatment, the manufacturing apparatus removes the protective film 30 from the surface 10a of the GaN substrate 10.

Next, as shown in FIG. 4E, the manufacturing apparatus ion-implants Si as a donor element into the region (hereinafter, source formation region) 18 ′ in which the source region 18 (see FIG. 3) is formed in the GaN substrate 10. .. For example, the manufacturing apparatus forms a mask M3 on the surface 10a of the GaN substrate 10. The mask M3 is a SiO ₂ film or a photoresist. The mask M3 has a shape that opens above the source forming region 18'and covers above the other regions. The manufacturing apparatus ion-implants Si into the GaN substrate 10 on which the mask M3 is formed. After ion implantation, the manufacturing apparatus removes the mask M3 from the GaN substrate 10.

Next, the manufacturing apparatus heat-treats the GaN substrate 10 at a maximum temperature of 1200 ° C. or lower. This heat treatment is, for example, a rapid heat treatment. By this heat treatment, Si ion-implanted into the GaN substrate 10 is activated, and as shown in FIG. 4F, an N + type source region 18 is formed on the GaN substrate 10. Further, by this heat treatment, the defects caused by the ion implantation of Si in the GaN substrate 10 can be recovered to some extent.

Next, as shown in FIG. 4G, the manufacturing apparatus forms the gate insulating film 21 on the GaN substrate 10. Next, the manufacturing apparatus forms the gate electrode 23 and the source electrode 25. Next, the manufacturing apparatus forms an interlayer insulating film (not shown) on the surface 10a of the GaN substrate 10 so as to cover the gate electrode 23 and the source electrode 25. Next, the manufacturing apparatus forms a gate pad 112 (see FIG. 1) that is electrically connected to the gate electrode 23 and a source pad 114 (see FIG. 1) that is electrically connected to the source electrode 25. After that, the manufacturing apparatus forms the drain electrode 27 on the back surface 10b of the GaN substrate 10. Through such a process, the GaN semiconductor device 100 including the vertical MOSFET 1 is completed.

(Fermi level of depletion layer generated in GaN)
FIG. 5 is a band diagram of the contact portion between the GaN and the protective film (N-type semiconductor) and its vicinity, and shows the valence band Ev and the conduction band Ec before and after the heat treatment for activating the acceptor element. , Fermi level Ef. In addition, Mg is ion-implanted as an acceptor element in the GaN shown in FIG.

As shown in FIG. 5, a depletion layer is formed at the contact portion between the GaN and the protective film. The band structure is bent in the depletion layer, and the Fermi level Ef of GaN and the Fermi level Ef of the protective film (N-type semiconductor) match. When heat treatment is performed in this state, Mg is activated in GaN and the Fermi level approaches the valence band, but the band structure is bent in the depletion layer. Therefore, in the region where the depletion layer is generated in GaN (that is, the surface layer portion of GaN), the approach of the Fermi level Ef to the valence band is suppressed as compared with the region where the depletion layer is not generated.

When the acceptor concentration in GaN is 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less, and the donor concentration in the protective film is 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less. The width (depth) of the depletion layer formed in GaN by contact with the protective film is approximately 1 nm or more and 30 nm or less. The higher the donor concentration in the protective film, the wider the width of the depletion layer formed in GaN.

FIG. 6 is a band diagram of GaN when the protective film is an insulating film, and shows the valence band Ev, the conduction band Ec, and the Fermi level Ef before and after the heat treatment for activating the acceptor element. It is a figure which shows. When the protective film is an insulating film, the depletion layer does not occur as shown in FIG. 6, and the band structure in the depletion layer does not bend. When the GaN covered with the insulating film is heat-treated, the Mg contained in the GaN is activated and the Fermi level of the GaN approaches the valence band.

(Suppression of Mg segregation by controlling Fermi level)
FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN. This graph is the data calculated by the first principle calculation. The horizontal axis of FIG. 7 indicates the Fermi level Ef (eV), and the vertical axis of FIG. 7 indicates energy (eV). The solid line (a) in FIG. 7 shows the relationship between the formation energy of the Mg acceptor (that is, the energy required to insert Mg into the Ga site of GaN) and the Fermi level Ef of GaN. The broken line (b) in FIG. 7 shows the relationship between the energy required for Ga to enter between the lattices of GaN and the Fermi level Ef of GaN.

In FIG. 7, as the Fermi level Ef approaches 0 (eV) (that is, the Fermi level Ef approaches the valence band and the conductive type of GaN approaches the P type), the formation energy of the Mg acceptor increases. .. Further, as the Fermi level approaches 0 (eV), the energy required for Ga to enter between the lattices of GaN becomes smaller.

From the graph of FIG. 7, it can be seen that the closer the Fermi level of GaN is to the valence band and the more the conductive type of GaN is closer to the P type, the more difficult it is for Mg to be activated and the more difficult it is to function as an acceptor. In other words, it can be seen that the closer the Fermi level of GaN is to the conduction band and the more the conductive type of GaN is closer to the N type, the easier it is for Mg to be activated and the easier it is to function as an acceptor.

In the embodiment of the present invention, the surface layer portion of the contact forming region 16'is formed into a depletion layer by contact with the protective film 30 which is an N-type semiconductor, and the Fermi level Ef of the depletion layer approaches the valence band Ev. It is suppressed. The Fermi level Ef on the surface layer of the contact forming region 16'is controlled so as not to approach the valence band. As a result, in the surface layer portion of the contact region 16, Mg is easily activated and easily functions as an acceptor.

(Effect of Embodiment 1)
As described above, the method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention includes a step of ion-implanting Mg into the contact forming region 16'of the GaN substrate 10 and a GaN substrate 10 having Mg ion-implanted. The contact region 16 is formed on the GaN substrate 10 by the step of forming the protective film 30 on the contact forming region 16'and by heat-treating the GaN substrate 10 on which the protective film 30 is formed to activate Mg. It is equipped with a process. The protective film 30 is made of an N + type semiconductor.

According to this, when the contact forming region 16'and the protective film 30 come into contact with each other, a depletion layer is formed on the surface layer portion of the contact forming region 16', and the Fermi level of this surface layer portion is the Fermi level of the protective film 30. Matches the rank. Since the protective film 30 is made of an N + type semiconductor, it is possible to prevent the Fermi level of the depletion layer generated in the surface layer portion from approaching the valence band.

As a result, in the surface layer portion of the contact forming region 16', the formation energy of the Mg acceptor can be maintained in a low state, and the Mg can be easily activated. It is possible to suppress the variation in Mg concentration due to the above. As a result, it is possible to realize a P + type contact region 16 having a high concentration, a small variation in concentration, and a small amount of Mg segregation on the surface layer portion. Further, by joining the source electrode 25 to such a P + type contact region 16, it is possible to realize a source contact having excellent ohmic properties.

Further, in the above manufacturing method, the ion implantation conditions of Mg are set so that the concentration of the donor element contained in the protective film 30 is higher than the concentration of Mg ion-implanted into the GaN substrate 10. May be. According to this, since the width (depth) of the depletion layer formed on the GaN substrate 10 can be increased, it becomes easy to expand the region of the surface layer portion where the Mg segregation is small in the depth direction.

(Modification example)
In the first embodiment described above, it has been described that the N + type source region 18 is formed after the P + type contact region 16 is formed. However, in the embodiment of the present invention, the formation of the source region 18 may be performed before the formation of the contact region 16. For example, in the step of ion-implanting Si into the source forming region 18'shown in FIG. 4E and the heat treatment step for activating Si shown in FIG. 4F, Mg is added to the contact region 16'shown in FIG. 4B. It may be performed before the step of ion implantation. Even with such a method, the manufacturing apparatus can manufacture the vertical MOSFET 1. Further, in this method, it is not necessary to consider Mg segregation in the contact forming region 16'when performing the heat treatment for activating Si. Therefore, the maximum temperature of the heat treatment for activating Si may be set to 1300 ° C. or higher, and it becomes easy to increase the activation rate of Si in the source region 18.

Further, in the first embodiment, it has been described that the protective film 30 is removed from the surface 10a of the GaN substrate 10 after the contact region 16 is formed by the heat treatment. However, in the embodiment of the present invention, at least a part of the protective film 30 may be left on the contact region 16.

FIG. 8 is a cross-sectional view showing a configuration example of the GaN semiconductor device 100A according to the modified example of the first embodiment of the present invention. As shown in FIG. 8, the GaN semiconductor device 100A includes a GaN substrate 10 and a plurality of vertical MOSFETs 1A provided on the GaN substrate 10 and repeatedly provided in one direction (for example, the X-axis direction). In the vertical MOSFET 1A shown in FIG. 8, the difference from the vertical MOSFET 1 shown in FIG. 3 is that the protective film 30 is between the contact region 16 and the source electrode 25, and between the source region 18 and the source electrode 25. Is the point that is left (intervened).

In the vertical MOSFET 1A, the thickness of the protective film 30 left between the contact region 16 and the source electrode 25 and between the source region 18 and the source electrode 25 is, for example, 1 nm or more and 1 μm or less, and more. It is preferably 1 nm or more and 500 nm or less. The protective film 30 functions as a tunnel film. The thickness of the protective film 30 may be the same as that at the time of film formation, but it may be thinned by etching. By thinning the protective film 30, the tunnel effect of the protective film 30 can be enhanced.

Even with such a configuration, the contact region 16 and the source electrode 25 and the source region 18 and the source electrode 25 are electrically connected. Therefore, the vertical MOSFET 1A shown in FIG. 8 operates in the same manner as the vertical MOSFET 1 shown in FIG. 3 and the like.

Further, in the modified example shown in FIG. 8, the protective film 30 is left on the contact region 16 even after the vertical MOSFET 1A is completed. Therefore, when the source region 18 is formed after the contact region 16 is formed, even if the maximum temperature of the heat treatment for activating Si in the source region 18 is set to 1300 ° C. or higher, Mg in the contact region 16 is formed. Segregation can be suppressed. As a result, the heat treatment temperature for activating Si in the source region 18 can be increased, so that it becomes easy to increase the activation rate of Si in the source region 18.

<Embodiment 2>
(Constitution)
FIG. 9 is a cross-sectional view showing a configuration example of the GaN semiconductor device 200 according to the second embodiment of the present invention. As shown in FIG. 9, the GaN semiconductor device 200 according to the second embodiment is provided on the GaN substrate 10, the PN diode 2 provided on the GaN substrate 10 (an example of the “diode” of the present invention), and the GaN substrate 10. It is provided with a guard ring structure 17 that surrounds the PN diode 2.

The PN diode 2 includes an N-type region 13 provided on the GaN substrate 10, a P-type region 15 provided on the GaN substrate 10, a P + type contact region 16 provided on the GaN substrate 10, and a GaN substrate 10. The insulating film 19 provided on the surface 10a of the GaN substrate 10 and the anode electrode 35 provided on the surface 10a side of the GaN substrate 10 and electrically connected to the contact region 16 (“electrode” of the present invention. (Example), and a cathode electrode 37 provided on the back surface 10b side of the GaN substrate 10 and electrically connected to the N-type region 13. In the PN diode 2, the N-type region 13 is the cathode region and the P-type region 15 is the anode region.

The P-type region 15 is formed by ion-implanting an acceptor element into an N-type GaN substrate 10 and heat-treating it. The acceptor element is, for example, Mg.

The insulating film 19 is, for example, a silicon oxide (SiO ₂ ) film. The insulating film 19 is provided with an opening H19 having a contact region 16 as a bottom surface. The anode electrode 35 is connected to the contact region 16 through the opening H19.

The anode electrode 35 and the cathode electrode 37 are made of, for example, an alloy of Al or Al—Si. The anode electrode 35 and the cathode electrode 37 may have a barrier metal layer between the anode electrode 35 and the cathode electrode 10. Ti may be used as the material of the barrier metal layer.

The guard ring structure 17 has, for example, a structure in which the PN diode 2 is surrounded by a plurality of P-shaped regions in a ring shape. The guard ring structure 17 can easily spread the depletion layer toward the outer peripheral side of the GaN substrate 10 when a reverse bias is applied to the PN diode 2, and can suppress electric field concentration on the PN diode 2. As a result, the guard ring structure 17 can improve the withstand voltage of the PN diode 2.

(Production method)
Next, a method for manufacturing the GaN semiconductor device 200 according to the second embodiment of the present invention will be described. 10A to 10E are cross-sectional views showing the manufacturing method of the GaN semiconductor device 200 according to the second embodiment of the present invention in the order of processes. As shown in FIGS. 10A and 10B, in the GaN substrate 10, the manufacturing apparatus includes a region (hereinafter, P-type forming region) 15 ′ in which the P-type region 15 (see FIG. 9) is formed and a contact forming region 16 ′. Mg is ion-implanted as an acceptor element. For this ion implantation, the ion implantation conditions are set so that the implantation depth of the acceptor element is shallower and the implantation concentration of the acceptor element is higher in the contact formation region 16'than in the P-type formation region 15'. .. Further, this ion implantation may be performed by multi-stage ion implantation using the same mask.

For example, the manufacturing apparatus forms the mask M11 on the surface 10a of the GaN substrate 10. The mask M11 is a SiO ₂ film or a photoresist that can be selectively removed from the GaN substrate 10. The mask M11 has a shape that opens above the P-shaped forming region 15'(also above the contact forming region 16', as shown in FIG. 10B) and covers above the other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M11 is formed, and introduces Mg into the P-type forming region 15'. The ion implantation conditions at this time are, for example, the same as the ion implantation conditions in the step shown in FIG. 4A.

Next, as shown in FIG. 10B, the manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M11 is formed, and introduces Mg into the contact forming region 16'. The ion implantation conditions at this time are, for example, the same as the ion implantation conditions in the step shown in FIG. 4B. After ion implantation into the P-shaped forming region 15'and the contact forming region 16', the manufacturing apparatus removes the mask M11 from the GaN substrate 10.

Next, as shown in FIG. 10C, the manufacturing apparatus ionizes Mg as an acceptor element in the region (hereinafter, guard ring forming region) 17 ′ in which the guard ring structure 17 (see FIG. 9) is formed in the GaN substrate 10. inject. For example, the manufacturing apparatus forms the mask M12 on the surface 10a of the GaN substrate 10. The mask M12 has a shape that opens above the guard ring forming region 17'and covers above the other regions. The mask M12 is a SiO ₂ film or a photoresist that can be selectively removed from the GaN substrate 10. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M12 is formed, and introduces Mg into the guard ring forming region 17'. The ion implantation conditions at this time may be, for example, the same as or different from the ion implantation conditions in the step shown in FIG. 4A. After ion implantation into the guard ring forming region 17', the manufacturing apparatus removes the mask M12 from the GaN substrate 10.

Next, as shown in FIG. 10D, the manufacturing apparatus forms the protective film 30 on the surface 10a of the GaN substrate 10. As a result, at least the contact forming region 16'on the surface 10a of the GaN substrate 10 comes into direct contact with the protective film 30. Further, the entire surface 10a of the GaN substrate 10 may be in direct contact with the protective film 30.

Next, the manufacturing apparatus heat-treats the GaN substrate 10 covered with the protective film 30 at a maximum temperature of 1300 ° C. or higher and 2000 ° C. or lower. This heat treatment is, for example, a rapid heat treatment. This heat treatment activates Mg introduced into the GaN substrate 10, and as shown in FIG. 10E, the GaN substrate 10 has a P-type region 15, a P + -type contact region 16, and a P-type guard ring structure 17. Is formed, and the N-type region 13 is defined. Further, by this heat treatment, the defects caused by the ion implantation of Mg in the GaN substrate 10 can be recovered to some extent. After the heat treatment, the manufacturing apparatus removes the protective film 30 from the surface 10a of the GaN substrate 10.

Note that FIG. 10E shows an embodiment in which the P-shaped region 15 is more widely diffused in the lateral direction than the contact forming region 16, but this is only an example. In the second embodiment of the present invention, the P-shaped region 15 and the contact forming region 16 have the same lateral diffusion, and the entire surface side of the P-shaped region 15 is covered with the contact forming region 16. You may.

Next, the manufacturing apparatus forms an insulating film 19 (see FIG. 9) on the surface 10a of the GaN substrate 10, and forms an opening H19 (see FIG. 9) in the insulating film 19. Next, the manufacturing apparatus forms the anode electrode 35 and the cathode electrode 37. Through such a process, the GaN semiconductor device 200 including the PN diode 2 shown in FIG. 9 is completed.

(Effect of Embodiment 2)
As described above, the method for manufacturing the GaN semiconductor device 200 according to the second embodiment of the present invention includes a step of ion-implanting Mg into the contact forming region 16'of the GaN substrate 10 and a GaN substrate 10 in which Mg is ion-implanted. The contact region 16 is formed on the GaN substrate 10 by the step of forming the protective film 30 on the contact forming region 16'and by heat-treating the GaN substrate 10 on which the protective film 30 is formed to activate Mg. It is equipped with a process. The protective film 30 is made of an N + type semiconductor.

According to this, it is possible to realize a P + type contact region 16 having a high concentration, a small variation in concentration, and a small amount of Mg segregation on the surface layer portion, similarly to the GaN semiconductor device 100 according to the first embodiment. Further, by joining the anode electrode 35 to such a P + type contact region 16, it is possible to realize an anode contact having excellent ohmic contact.

(Modification example)
Similar to the first embodiment, in the second embodiment, at least a part of the protective film 30 may be left on the contact region 16. FIG. 11 is a cross-sectional view showing a configuration example of the GaN semiconductor device 200A according to the modified example of the second embodiment of the present invention. As shown in FIG. 11, the GaN semiconductor device 200A includes a GaN substrate 10 and a PN diode 2A provided on the GaN substrate 10. The difference between the PN diode 2A shown in FIG. 11 and the PN diode 2 shown in FIG. 9 is that the protective film 30 is left (intervened) between the contact region 16 and the anode electrode 35. be.

In the PN diode 2A, the thickness of the protective film 30 left between the contact region 16 and the anode electrode 35 is, for example, 1 nm or more and 1 μm or less, and more preferably 1 nm or more and 500 nm or less. The protective film 30 functions as a tunnel film. With such a configuration, since the contact region 16 and the anode electrode 35 are electrically connected, the operation is the same as that of the PN diode 2 described above.

Further, in the production method shown in FIGS. 10A to 10E, it has been described that Mg is implanted as an acceptor element into the P-type forming region 15'and the contact forming region 16' by using the mask M11 in multiple stages. However, in the second embodiment of the present invention, the ion implantation into the P-type forming region 15'and the ion implantation into the contact forming region 16' may be performed using different masks. Even with such a method, it is possible to manufacture a semiconductor device having the same structure as the GaN semiconductor device 200 shown in FIG. In this method, the number of manufacturing steps increases, but for example, it is possible to form the shape of the contact region 16 in a plan view different from that of the P-shaped region 15.

Further, in the production method shown in FIGS. 10A to 10E, it has been described that Mg is ion-implanted as an acceptor element into the guard ring forming region 17'using the mask M12. However, in the second embodiment of the present invention, the ion implantation into the guard ring forming region 17'may be performed using the mask M11. Even with such a method, it is possible to manufacture a semiconductor device having the same structure as the GaN semiconductor device 200 shown in FIG. In this method, the guard ring structure 17 is formed in a structure in which the P + type region 16 is arranged on the P type region 15.

(Other embodiments)
As mentioned above, the invention has been described by embodiments 1 and 2 and modifications, but the statements and drawings that form part of this disclosure should not be understood as limiting the invention. Various alternative embodiments and modifications will be apparent to those skilled in the art from this disclosure.

For example, the gate insulating film 21 is not limited to the SiO ₂ film, and may be another insulating film. As the gate insulating film 21, a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si ₃ N ₄ ) film, and an aluminum oxide (Al ₂ O ₃ ) film can also be used. Further, as the gate insulating film 21, a composite film or the like in which several single-layer insulating films are laminated can also be used. A vertical MOSFET in which an insulating film other than the SiO ₂ film is used as the gate insulating film 21 may be referred to as a vertical MISFET. MISFET means a more comprehensive isolated gate transistor including MOSFET.

Further, in the first embodiment, it has been explained that the contact region 16 is included in the vertical MISFET. However, embodiments of the present invention are not limited to this. The contact region 16 may be included in the horizontal MISFET in which the current flows in the horizontal direction of the GaN substrate, instead of the vertical MISFET in which the current flows in the vertical direction of the GaN substrate.

Further, in the first embodiment, it has been described that the electrode in contact with the contact region 16 is the source electrode 25. In the second embodiment described above, it has been described that the electrode in contact with the contact region 16 is the anode electrode 35. However, embodiments of the present invention are not limited to this. The contact region 16 may be in contact with an electrode other than the source electrode and the anode electrode. Further, the P-type region exemplified in the contact region 16 may be included in an element other than the MOSFET and the PN diode, and may be included in, for example, a bipolar transistor, a capacitive element, a resistance element, or the like.

As described above, it goes without saying that the present technique includes various embodiments not described here. At least one of the various omissions, substitutions and modifications of the components may be made without departing from the gist of the embodiments and modifications described above. Further, the effects described in the present specification are merely exemplary and not limited, and other effects may be obtained.

1,1A vertical MOSFET
2, 2A PN diode 10 GaN substrate 10a Front surface 10b Back surface 12 Drift region 13 N-type region 14 Well region 14'Well formation region 15 P-type region 15'P-type formation region 16 Contact region 16'Contact formation region 17 Guard ring structure 17'Guard ring formation region 18 Source region 18'Source formation region 19 Insulation film 21 Gate insulation film 23 Gate electrode 25 Source electrode 27 Drain electrode 30 Protective film 35 Anode electrode 37 Cathode electrode 100, 100A, 200, 200A GaN semiconductor device 110 Active Region 112 Gate Pad 114 Source Pad 121 Upper Region 122 Lower Region 130 Edge Termination Region 141 Channel Region D Drain Terminal Ec Conduction Band Ef Fermi Level Ev Diode Electrode Band G Gate Terminal H19 Openings M1, M2, M3, M11, M12 Mask S source terminal

Claims (16)

The process of ion-implanting acceptor elements into nitride semiconductors,
A step of forming a protective film on the nitride semiconductor into which the acceptor element is ion-implanted, and
A step of forming a P-type region in the nitride semiconductor by heat-treating the nitride semiconductor on which the protective film is formed to activate the acceptor element is provided.
A method for manufacturing a nitride semiconductor device, wherein the protective film is composed of an N-type semiconductor. Claimed to set the ion implantation conditions of the acceptor element so that the concentration of the donor element contained in the protective film is higher than the concentration of the acceptor element ion-implanted into the nitride semiconductor. The method for manufacturing a nitride semiconductor device according to 1. The ion implantation condition of the acceptor element is set so that the concentration of the acceptor element ion-implanted into the nitride semiconductor is 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less. Or the method for manufacturing a nitride semiconductor device according to 2. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 3, wherein the maximum temperature of the heat treatment is 1300 ° C. or higher and 2000 ° C. or lower. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 4, wherein the nitride semiconductor is gallium nitride. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 5, wherein the acceptor element contains at least one of magnesium and beryllium. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 6, wherein the protective film is aluminum nitride or silicon nitride. Nitride semiconductor and
A P-type region provided in the nitride semiconductor is provided.
The concentration of the acceptor element in the P-type region is 1 × 10 ¹⁹ cm ^-3 or more and 1 × 10 ²¹ cm ^-3 or less.
A nitride semiconductor device in which the density of acceptor segregation in the surface layer portion of the P-type region is lower than the density of the acceptor segregation in a portion deeper than the surface layer portion in the P-type region. The acceptor segregation
Rod-shaped acceptor segregation with a length of 30 nm or more in one direction and a concentration of the acceptor element of 5 × 10 ²⁰ cm ^-3 or more.
Classified as non-rod-like acceptor segregation, the length in one direction is less than 30 nm and the concentration of the acceptor element is 5 × 10 ²⁰ cm ^-3 or more.
The eighth aspect of the invention, wherein in the surface layer portion, the density of the rod-shaped acceptor segregation is 1 × 10 ¹⁴ cm ^-3 or less, and the density of the non-rod-shaped acceptor segregation is less than 1 × 10 ¹⁵ cm ^-3 . Nitride semiconductor device. The nitride semiconductor device according to claim 8 or 9, wherein the depth from the surface of the surface layer portion is 1 nm or more and 30 nm or less. The nitride semiconductor device according to any one of claims 8 to 10, further comprising an electrode provided on the surface layer portion. The nitride semiconductor device according to claim 11, further comprising a protective film made of an N-type semiconductor interposed between the surface layer portion and the electrode. The nitride semiconductor device according to claim 12, wherein the concentration of the dopant element in the protective film is higher than the concentration of the acceptor element in the surface layer portion. The nitride semiconductor device according to claim 12, wherein the thickness of the protective film is a value equal to or greater than the depth from the surface of the surface layer portion and a value of 1 μm or less. The P-type well region provided in the nitride semiconductor and
A field effect transistor provided in the nitride semiconductor and having a channel formed in the well region is provided.
The nitride semiconductor device according to any one of claims 8 to 14, wherein the P-type region has a higher concentration of the acceptor element than the well region and is electrically connected to the well region. A diode provided in the nitride semiconductor is provided.
The nitride semiconductor device according to any one of claims 8 to 14, wherein the P-shaped region is an anode region of the diode.

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