JP2022073883A - Semiconductor device including reference voltage circuit - Google Patents

Abstract

To suppress the shift of threshold voltage in a high-temperature shelf test of a semiconductor device including a reference voltage circuit using an enhancement type transistor to set P-type polycrystalline silicon as a gate electrode.SOLUTION: A semiconductor device includes an enhancement type transistor using P-type polycrystalline silicon as a first gate electrode, and a depletion type transistor using N-type polycrystalline silicon as a second gate electrode. The enhancement type transistor includes a non-water-permeable film provided locally covering the first gate electrode through an interlayer insulating film over the first gate electrode, and a nitride film including an opening that is larger than the first gate electrode and smaller than the non-water-permeable film and provided covering the periphery of the non-water-permeable film. The depletion type transistor includes a reference voltage circuit including a nitride film covering the depletion type transistor entirely and provided directly in an interlayer insulating film over the second gate electrode.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device including a reference voltage circuit having an N-type MOS transistor with a P-type gate electrode.

By using two N-type MOS transistors (enhancement type and depletion type), it is possible to configure a reference voltage circuit that outputs a constant voltage against fluctuations in the power supply voltage.

In a reference voltage circuit, it is often required to suppress fluctuations in the output voltage due to temperature. Therefore, as shown in Patent Document 1, in two N-type MOS transistors (enhancement type and depletion type) constituting a reference voltage circuit (Vref circuit), a gate electrode is configured while making the impurity concentration in the channel region the same. There is a method of changing the conductive type of the polycrystalline silicon to be the same N-type in the past, and changing only the gate electrode of the enhancement type transistor to the P-type polycrystalline silicon. Utilizing the difference in work function caused by the difference in the conductive type of the gate electrode, the enhanced MOS transistor having a polycrystalline silicon having a P-type conductive type as a gate electrode and the polycrystalline silicon having an N-type conductive type A reference voltage is generated by providing a difference in the threshold voltage (Vth) of the depletion type MOS transistor having the gate electrode.

In this case, since the impurity concentration in the channel region is the same, the influence of the temperature change on the threshold voltage of both transistors is also the same, and the fluctuation of the reference voltage obtained from the difference between the thresholds of both transistors can be suppressed. It will be possible.

Hereinafter, a gate electrode made of polycrystalline silicon having a P-type conductive type is referred to as a P-type gate electrode, and a gate electrode made of polycrystalline silicon having an N-type conductive type is referred to as an N-type gate electrode. A MOS transistor having polycrystalline silicon as a gate electrode is referred to as a P-type gate electrode MOS transistor, and a MOS transistor having N-type conductive polycrystalline silicon as a gate electrode is referred to as an N-type gate electrode MOS transistor. A Vref circuit configured by using a P-type gate electrode MOS transistor and an N-type gate electrode MOS transistor is referred to as a Vref circuit using a different electrode gate.

Japanese Unexamined Patent Publication No. 2008-293409

In order to evaluate the reliability of the Vref circuit using this hemimorphite, the P-type gate electrode MOS transistor was used in the high temperature standing test, which is one of the accelerated tests conducted under stricter environmental conditions than in actual use. It turns out that it can cause a threshold voltage shift. This shift causes the reference voltage to fluctuate, leading to a shift in the characteristics of the IC in the long-term reliability test. One of the causes of the threshold voltage shift is the influence of hydrogen. However, although the shift amount of this threshold voltage is as small as several millivolts, it cannot be ignored in applications that require a high degree of stability of the reference voltage obtained from the threshold voltage.

Therefore, the present invention provides a semiconductor device provided with a reference voltage circuit using a transistor structure capable of suppressing a threshold voltage shift occurring in a P-type gate electrode MOS transistor in a high temperature standing test. That is the issue.

In order to solve the above problems, the semiconductor device provided with the reference voltage circuit according to the embodiment of the present invention has the following configuration. That is, an enhancement type MOS transistor having a P-type conductive type polycrystalline silicon as a first gate electrode, a depletion type MOS transistor having an N-type conductive type polycrystalline silicon as a second gate electrode, and a depletion type MOS transistor. A semiconductor device including a reference voltage circuit comprising, further, the enhancement type MOS transistor covers the first gate electrode via an interlayer insulating film arranged on the upper part of the first gate electrode. Around the impermeable film having a locally provided impermeable film and an opening provided in plan view larger than the first gate electrode and smaller than the impermeable film. The depletion-type MOS transistor has a nitride film provided so as to cover it, and the depletion-type MOS transistor is provided directly on an interlayer insulating film arranged above the second gate electrode, and the depletion-type MOS transistor is provided in a plan view. It is a semiconductor device provided with a reference voltage circuit characterized by having a nitride film that covers the above without gaps.

The semiconductor device provided with the reference voltage circuit according to the present invention has a nitride film, which is a protective film that is a source of hydrogen diffusion, which is a factor that causes a shift in the threshold voltage in a high temperature standing test, in a P-type gate electrode MOS transistor. By removing it from the upper part of the P-type gate electrode, the diffusion of hydrogen is suppressed and the fluctuation of the interface state due to leaving at a high temperature is suppressed. It is possible to easily suppress fluctuations in IC characteristics without changing the process. Since the range from which the nitride film is removed is local and the impermeable film is under the opening from which the nitride film has been removed, the intrusion of water is sufficiently suppressed and there is no risk of causing a decrease in reliability.

It is a top view of the semiconductor device provided with the reference voltage circuit which concerns on 1st Embodiment of this invention. FIG. 3 is a schematic cross-sectional view taken along the cutting line A of FIG. FIG. 3 is a schematic cross-sectional view taken along the cutting line B of FIG. It is an equivalent circuit diagram of the reference voltage circuit which concerns on 1st Embodiment. It is a comparative figure of the shift amount in a high temperature leaving test. It is a schematic cross-sectional view of the semiconductor device provided with the reference voltage circuit which concerns on 2nd Embodiment of this invention. It is a schematic cross-sectional view of the semiconductor device provided with the reference voltage circuit which concerns on 3rd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor device provided with a reference voltage circuit according to the first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view taken along the cutting line A of FIG. 1, and FIG. 3 is a schematic cross-sectional view taken along the cutting line B of FIG.

As shown in FIG. 1, the semiconductor device 100 provided with a reference voltage circuit has an enhancement type MOS transistor 1 and a depletion type MOS transistor 2. The conductive type of the enhancement type MOS transistor 1 and the depletion type MOS transistor 2 are both N type, and are sometimes called N channels.
As shown in FIGS. 2 and 3, the enhancement type MOS transistor 1 is provided on the surface of the P-type well 8 arranged on the N-type substrate 7, and the P-type gate is provided via the gate oxide film. A source 9A and a drain 9B, both of which are N-type high-concentration layers, are provided sandwiching the electrode 3. An intermediate insulating film 10 is provided so as to cover the P-type gate electrode 3, and a first metal wiring 11 is provided on the intermediate insulating film 10. An interlayer insulating film 12 is provided so as to cover the first metal wiring 11, and the impermeable film 5 is locally arranged so as to cover the P-type gate electrode 3 on the interlayer insulating film 12. The impermeable film 5 is covered from the periphery of the opening 6 to the outside by the final protective film 13 arranged on the interlayer insulating film 12, but the opening 6 provided on the upper surface of the impermeable film 5 is final. Not covered by the protective film 13. The final protective film 13 has an opening 6 on the impermeable film 5 to expose the surface of the impermeable film 5.

As can be seen from FIG. 1, in a plan view, the impermeable membrane 5 covers the entire surface of the P-type gate electrode 3, so that it is larger than the P-type gate electrode 3. Further, the opening 6 is provided larger than the P-type gate electrode 3 so as to include the entire surface of the P-type gate electrode 3 inside, but since the opening 6 is provided inside the impermeable membrane 5, the opening 6 is provided inside. It will be smaller than the impermeable membrane 5.

As shown in FIG. 2, the depletion type MOS transistor 2 is different from the P type well 8 provided with the enhancement type MOS transistor 1 on the surface of another P type well 8 arranged on the N type substrate 7. A source 9C and a drain 9D, both of which are N-type high-concentration layers, are provided so as to sandwich the N-type gate electrode 4 provided via a gate oxide film. An intermediate insulating film 10 is provided so as to cover the N-type gate electrode 4, and a first metal wiring 11 is provided on the intermediate insulating film 10. The interlayer insulating film 12 is provided so as to cover the first metal wiring 11, and the entire surface is covered by the final protective film 13 arranged on the interlayer insulating film 12. Since the final protective film 13 covering the depletion type MOS transistor 2 is not provided with the opening 6, the entire surface of the depletion type MOS transistor 2 is covered with the final protective film 13 without any gaps.

As shown in FIG. 1, the drain 9B of the enhancement type MOS transistor 1 is connected to the source 9C of the depletion type MOS transistor 2 by the first metal wiring 11. By the same metal wiring, the P-type gate electrode 3 of the enhancement type MOS transistor 1 and the N-type gate electrode 4 of the depletion type MOS transistor 2 are also connected and have the same potential. Normally, the source 9A of the enhancement type MOS transistor 1 is connected to the ground potential wiring, and the drain 9D of the depletion type MOS transistor 2 is connected to the power supply potential wiring by the first metal wiring 11.

FIG. 4 is an equivalent circuit diagram showing a portion of a reference voltage circuit of a semiconductor device including the reference voltage circuit described with reference to FIGS. 1 to 3. It has an enhancement type MOS transistor 1 and a depletion type MOS transistor 2 connected in series, the source of the enhancement type MOS transistor 1 is connected to the ground potential _VSS , and the drain of the depletion type MOS transistor 2 is the power supply potential. Connected to _VDD . The reference voltage V _ref is output from the connection point between the enhancement type MOS transistor 1 and the depletion type MOS transistor 2.

Next, a method of manufacturing a semiconductor device provided with the reference voltage circuit will be described. The enhancement type MOS transistor and the depletion type MOS transistor constituting the reference voltage circuit are provided near the surface of the N-type silicon substrate or the P-type well separately formed in the N-type well. After the device separation region is formed by LOCOS or STI, a gate oxide film is formed, and a photoresist silicon film to be a gate electrode is deposited. After the polycrystalline silicon film is formed with a thickness of 100 nm to 400 nm, for example, BF ₂ is ion-injected into the gate electrode region of the enhanced MOS transistor to form P-type polysilicon, which is a depletion type MOS transistor. For example, phosphorus is ion-injected into the gate electrode region of the above to carry out ion-injection of impurities so as to form N-type photoresist. After that, polycrystalline silicon is patterned and processed to form a gate electrode.

Next, an intermediate insulating film covering the gate electrode is formed, a contact hole is formed, and then a metal film to be a first metal wiring layer is formed. After that, an interlayer insulating film and a required number of multilayer wiring layers are formed.
A non-permeable layer is formed in the uppermost layer of the multilayer wiring, and in the patterning thereof, at least the enhancement type MOS transistor constituting the reference voltage circuit is laid out so as to cover the gate electrode, and the patterning is performed. Use a water permeable membrane. It is also possible to arrange the impermeable membrane not only on the gate electrode of the enhancement type MOS transistor but also on the gate electrode of the depletion type MOS transistor.
As the impermeable layer, a metal wiring layer to be the uppermost layer can be used. Amorphous silicon formed by sputtering can also be used instead of metal.

After patterning the impermeable layer, a final protective film is formed. The structure of the final protective film may be a single-layer structure of a plasma nitride film or a two-layer structure of an oxide film and a plasma nitride film. Since hydrogen contained in this plasma nitride film is desorbed in the high temperature standing test and captured as an interface state, the final protective film of the region portion of the impermeable membrane arranged on the gate electrode of the above-mentioned reference voltage circuit is used. Etch and remove. By doing so, it becomes possible to prevent the diffusion of hydrogen from the plasma nitride film located directly above the P-type gate electrode, and it is possible to suppress the total amount of diffused hydrogen.

FIG. 5 compares the shift amount shown in the high temperature standing test by the semiconductor device provided with the reference voltage circuit shown by FIGS. 1 to 4 with the shift amount in the semiconductor device provided with the reference voltage circuit having the conventional structure. be. Assuming that the shift amount in the conventional structure is 1, it can be seen that the shift amount is reduced to 0.6 in the structure according to the first embodiment. From this comparison result, a non-permeable film covering the P-type gate electrode 3 is arranged above the P-type gate electrode 3 of the enhancement type MOS transistor 1, and a plasma nitride film which is a final protective film is arranged on the impermeable film. It can be seen that it is possible to suppress the shift amount of the threshold voltage in the high temperature leaving test by providing the opening in which the above is removed.

FIG. 6 is a schematic cross-sectional view of a semiconductor device provided with a reference voltage circuit according to a second embodiment of the present invention. The difference from the first embodiment is that the polyimide film 15 covering the final protective film 13 arranged above the reference voltage circuit is provided. Although the impermeable membrane 5 does not allow moisture to pass through, moisture may invade from the interface between the impermeable membrane 5 and the final protective film 13 in the vicinity covered by the final protective film 13. Unlike hydrogen, water causes corrosion, so it is important to prevent the ingress of water in semiconductor devices. Therefore, by arranging the polyimide film 15 provided on the final protective film 13 so as to cover the opening 6 located on the surface of the impermeable film 5 without gaps, the interface between the impermeable film 5 and the final protective film 13 is provided. Therefore, it has a structure that suppresses the invasion of moisture. Since polyimide is hydrophobic, it has the effect of delaying the invasion of water.

FIG. 7 is a schematic cross-sectional view of a semiconductor device provided with a reference voltage circuit according to a third embodiment of the present invention. The difference from the first embodiment is that a corrosion-resistant oxide film is provided on the surface of the impermeable film 5 which is the bottom of the opening 6. This cites the use of a metal wiring layer or the use of amorphous silicon deposited by sputtering as an example of the impermeable membrane 5 in the first embodiment. When a metal wiring layer is used, since there is an opening, corrosion due to moisture or the like may occur in the impermeable membrane 5 using the metal wiring layer. Therefore, by providing a corrosion-resistant oxide film 16 that covers at least the surface of the non-permeable film 5 which is the bottom of the opening without gaps so that the impermeable film 5 is not corroded, the semiconductor device is provided. It is possible to increase the reliability against corrosion.

Examples of the corrosion-resistant oxide film 16 include alumina (aluminum oxide: Al ₂ O ₃ ), which is a metal oxide, and ceramics. Alumina can be formed by oxidation in an oxygen atmosphere or anodization when the impermeable membrane 5 contains aluminum as a main component. The ceramic film can be formed by coating a thin film mainly composed of a ceramic component. Since these oxides have high corrosion resistance and can be formed at a relatively low temperature, they can be used in semiconductor devices.

The opening 6 needs to be longer than the first channel width at least in the first channel width direction and is provided so as to cover the first channel region. However, the opening 6 may be shorter than the first channel length in the first channel length direction and may be set inside the first channel region.

It is considered that the fluctuation of the interface state due to leaving at a high temperature is mainly caused by the desorption of hydrogen due to the oxidation process existing here, mainly in the region where the bondability between the gate insulating film and the semiconductor substrate is low. In particular, this region with low coupling property may be concentrated at the boundary between the device separation region and the channel region. Therefore, by sufficiently covering this region, the opening 6 suppresses hydrogen invasion from the nitride film which is a protective film, and suppresses binding and desorption with hydrogen existing in a region having low bondability. It will be possible.

On the other hand, unbonded silicon hands generated by plasma etching processing at the time of forming the gate electrode are likely to be unevenly distributed at the boundary between the channel region and the source / drain region. This unbonded hand is not terminated by hydrogen and acts as a fixed charge, which tends to increase the threshold voltage. Therefore, the reference voltage output by the reference voltage circuit can be stabilized by positively promoting the intrusion of hydrogen from the nitride film which is the protective film and suppressing the rise and variation of the threshold voltage. Therefore, the opening 6 may be configured to be shorter than the first channel length in the first channel length direction and set inside the first channel region to promote hydrogen intrusion.

1. 1. N-channel enhancement type transistor 2. N-channel depletion type transistor 3. Gate electrode made of P-type polycrystalline silicon (P-type gate electrode)
4. Gate electrode made of N-type polycrystalline silicon (N-type gate electrode)
5. Impermeable membrane 6. Opening provided in the final protective film 7. N-type substrate 8. P-type wells 9A, 9C. N-type high-concentration layer (source)
9B, 9D. N-type high-concentration layer (drain)
10. Intermediate insulating film 11. First metal wiring 12. Interlayer insulating film 13. Final protective film 14. Element separation insulating film 15. Polyimide film 16. Impermeable membrane

Claims (7)

An enhancement type having a first channel region having a first channel length direction and a first channel width direction and a polycrystalline silicon having a P-type conductive type covering the first channel region as a first gate electrode. With MOS transistor
Depression type having a second channel region having a second channel length direction and a second channel width direction and polycrystalline silicon having an N-type conductive type covering the second channel region as a second gate electrode. With MOS transistor
A semiconductor device equipped with a reference voltage circuit having a
The enhancement type MOS transistor has an impermeable film locally provided over the first gate electrode via an interlayer insulating film arranged on the upper part of the first gate electrode, and a water-permeable film in plan view. It has a nitride film provided to wrap around the impermeable membrane, including the first gate electrode and having an opening provided smaller than the impermeable membrane.
The reference is characterized in that the depletion type MOS transistor has a nitride film directly provided on an interlayer insulating film arranged above the second gate electrode and covers the depletion type MOS transistor without gaps in a plan view. A semiconductor device equipped with a voltage circuit. The first aspect of claim 1, wherein the opening is longer than the first channel width in the first channel width direction and shorter than the first channel length in the first channel length direction. A semiconductor device equipped with a reference voltage circuit. An enhancement type MOS transistor having polycrystalline silicon having a P-type conductive type as a first gate electrode, and an enhancement type MOS transistor.
A depletion type MOS transistor having an N-type conductive type polycrystalline silicon as a second gate electrode, and a depletion type MOS transistor.
A semiconductor device equipped with a reference voltage circuit having a
The enhancement type MOS transistor has an impermeable film locally provided over the first gate electrode via an interlayer insulating film arranged on the upper part of the first gate electrode, and a water-permeable film in plan view. It has a nitride film provided to wrap around the impermeable membrane, having an opening provided larger than the first gate electrode and smaller than the impermeable membrane.
The reference is characterized in that the depletion type MOS transistor has a nitride film directly provided on an interlayer insulating film arranged above the second gate electrode and covers the depletion type MOS transistor without gaps in a plan view. A semiconductor device equipped with a voltage circuit. The semiconductor device provided with the reference voltage circuit according to any one of claims 1 to 3, wherein the impermeable film is the uppermost wiring layer. The semiconductor device provided with the reference voltage circuit according to any one of claims 1 to 3, wherein the impermeable film is amorphous silicon. Claim 1 is further provided with a polyimide film that covers the final protective film, and the polyimide film covers an opening located on the surface of the impermeable film provided in the final protective film without a gap. A semiconductor device provided with the reference voltage circuit according to any one of 3 to 3. The semiconductor device according to any one of claims 1 to 3, further comprising a corrosion-resistant oxide film that covers the surface of the impermeable film without gaps. ..

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