JP2022067701A - Method for manufacturing silicon single crystal - Google Patents

Abstract

To provide a silicon single crystal and a silicon wafer having improved distribution of in-plane resistivity.SOLUTION: A method for manufacturing a silicon single crystal comprises: adding a main dopant and a conductive auxiliary dopant having opposite polarity to grow a first silicon single crystal (S22); cutting a crystal portion grown while adding the auxiliary dopant from the first silicon single crystal to prepare a wafer sample (S23); measuring distribution of resistivity of the wafer sample in a radial direction at a first pitch (S24); calculating a deviation index of resistivity PA-RRG in each of a plurality of resistivity evaluation regions obtained by dividing the wafer sample in the radial direction at a second pitch wider than the first pitch (S25); calculating a division dope frequency and division dope amount of the auxiliary dopant necessary for setting the maximum of PA-RRG calculated from the wafer sample to a value equal to or less than a target value (S26); and adding the auxiliary dopant of the division dope amount at the division dope frequency to grow a second silicon single crystal (S27).SELECTED DRAWING: Figure 4

Description

The present invention relates to a method for producing a silicon single crystal, and more particularly to a method for producing a silicon single crystal to which not only a main dopant but also a sub-dopant having a conductive type having a polarity opposite to the main dopant is added.

Most of the silicon single crystals used as substrate materials for semiconductor devices are manufactured by the CZ method. In the CZ method, a seed crystal is immersed in a silicon melt contained in a quartz rut, and the seed crystal and the quartz rut are gradually pulled up while rotating, so that a single crystal having a large diameter is formed below the seed crystal. Grow. According to the CZ method, it is possible to produce a high quality silicon single crystal with a high yield.

In the growth of a silicon single crystal, various doping agents (dopants) are used to adjust the resistivity of the single crystal. Typical dopants are boron (B), phosphorus (P), arsenic (As), antimony (Sb) and the like. Usually, these dopants are put into a quartz crucible together with the polysilicon raw material and melted together with the polysilicon by heating with a heater. As a result, a silicon melt containing a predetermined amount of dopant is produced.

However, since the dopant concentration in the silicon single crystal changes in the pull-up axial direction due to segregation, it is difficult to obtain a uniform resistivity in the pull-up axial direction. To solve this problem, it is effective to add a conductive dopant having a polarity opposite to that of the main dopant during the pulling of the silicon single crystal. For example, by adding a p-type topant to the silicon melt during the pulling up of the n-type silicon single crystal, it is possible to suppress a decrease in the resistance of the silicon single crystal due to the influence of segregation of the n-type dopant. Such a method of adding a conductive type sub-dopant having the opposite polarity to the main dopant is called a counter-doping method.

Regarding the counterdope method, for example, in Patent Document 1, a dopant of a type having the opposite polarity (for example, p-type) to that of the initially introduced type (for example, n-type) is charged so as to satisfy a predetermined relational expression. A method for making the resistivity distribution in the crystal longitudinal direction uniform is described. Further, Patent Document 2 describes a granular doping agent supply device and a method.

Japanese Unexamined Patent Publication No. 3-247585 Japanese Patent Application Laid-Open No. 6-1688

According to the conventional counter-doping method in which granular sub-dopants are continuously charged, it is possible to improve the in-plane resistivity distribution. However, the granular sub-dopant often becomes fine, and when such a fine granular sub-dopant is dropped toward the melt in the crucible, it becomes too light and becomes an inert gas flowing in the furnace. It is agitated and flies to unexpected places, and adheres to places other than the silicon melt, which causes a high probability of dislocation of single crystals. Further, when handling a fine and minute amount of sub-dopant, there is a problem of measurement accuracy, and the amount of input tends to vary. For this reason, in the counterdope method, it is necessary to add a certain amount of sub-dopant.

However, if the amount of additional input of the sub-dopant at one time is too large, the difference in in-plane resistivity is large due to the difference in growth timing between the crystal center portion and the outer peripheral portion before and after counter-doping, and the in-plane resistivity distribution deteriorates. do. In particular, when the in-plane change in resistivity when viewed at the chip size level is large, it becomes a problem in the manufacture of power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), so the crystal parts before and after counter-doping are wafers. Cannot be used as a product.

Therefore, an object of the present invention is to provide a method for producing a silicon single crystal capable of improving the in-plane resistivity distribution.

In order to solve the above problems, the method for producing a silicon single crystal according to the present invention includes a step of adding a sub-dopment having a conductive type having a polarity opposite to that of the main dopant to grow a first silicon single crystal, and adding the sub-dopant. A step of cutting out the crystal portion grown during the period from the first silicon single crystal to prepare a wafer sample, a step of measuring the radial distribution of the resistivity of the wafer sample at the first pitch, and the wafer sample. PA-RRG (Partial Area-Resistivity Radial Gradient), which is an index of resistivity deviation in each of a plurality of resistivity evaluation regions obtained by partitioning the film in a second pitch wider than the first pitch in the radial direction. A step, a step of obtaining the number of divided dopings and the divided doping amount of the sub-dampant required for the maximum value of the PA-RRG obtained from the wafer sample to be equal to or less than the target value, and the sub-dopment of the divided doping amount. Is added at the number of division dopings to grow a second silicon single crystal.

Until now, it has been considered that the number of times of dopant input should be as small as possible, and therefore, the maximum amount of dopant added per dopant has been set within the range satisfying the resistivity standard. However, in the method for producing a silicon single crystal according to the present invention, the amount of dopant input per batch is reduced in consideration of the in-plane resistivity distribution at the chip size level, so that the growth axis direction of the silicon single crystal after counter-doping It is possible to control a sudden change in resistivity in the water and improve the in-plane resistivity distribution before and after counter-doping.

In the present invention, the number of division dopings is the minimum value among positive integers larger than the value obtained by dividing the maximum value (PA-RRG _max ) of the PA-RRG by the target value (PA-RRG _target ). Is preferable. In this way, by intermittently charging the sub-dopant by reducing the number of times the sub-dopant is charged as much as possible, the amount of the sub-dopant added can be correctly controlled, and the probability of dislocation of the single crystal can be reduced.

In the method for producing a silicon single crystal according to the present invention, before growing the first silicon single crystal, the maximum doping amount at one time when the sub-dopant is added is obtained from the resistance standard required for the silicon wafer. Further including a step, in the step of growing the first silicon single crystal, the sub-dopant having the maximum doping amount is added, and the divided doping amount is a value obtained by dividing the maximum doping amount by the number of divided dopings. Is preferable. In this way, by setting a plurality of resistivity evaluation regions on the silicon wafer and evaluating the RRG of the silicon wafer for each resistivity evaluation region, the in-plane resistivity distribution of the silicon wafer is evaluated at the chip size level. Can be done.

In the present invention, the PA-RRG is preferably a value expressed as a percentage by dividing the difference between the maximum value and the minimum value of the resistivity in the resistivity evaluation region by the minimum value. In this way, by evaluating the resistivity deviation in the plurality of resistivity evaluation regions for each resistivity evaluation region, resistivity evaluation at the chip size level can be realized, and as a substrate material for power semiconductor devices such as IGBTs. Suitable silicon wafers can be provided.

In the present invention, the second pitch is preferably three times or more the first pitch. This makes it possible to improve the reliability of the measured values of PA-RRG.

In the present invention, the first pitch is preferably 1 mm or more and 5 mm or less, and more preferably 1 mm or more and 2 mm or less. Further, the second pitch is preferably 10 mm or more and 20 mm or less. As a result, the reliability of resistivity evaluation of the silicon wafer can be improved.

In the present invention, the target value of PA-RRG is preferably 5% or less. This makes it possible to provide a silicon wafer suitable as a substrate material for a power semiconductor device such as an IGBT.

According to the present invention, it is possible to provide a method for producing a silicon single crystal capable of improving the in-plane resistivity distribution.

FIG. 1 is a schematic cross-sectional view showing the configuration of a single crystal manufacturing apparatus according to an embodiment of the present invention. FIG. 2 is a flowchart for explaining a method for producing a silicon single crystal according to an embodiment of the present invention. 3A and 3B are diagrams for explaining the counterdoping method, and are graphs showing changes in resistivity in the crystal growth direction of a silicon single crystal. FIG. 4 is a flowchart for explaining a method of determining the number of divided dopings and the amount of divided doping of the sub-dopant at the time of counter-doping. FIG. 5 is a graph showing the measurement results of the resistivity distribution of the wafer sample according to the comparative example and the example. The horizontal axis shows the distance [mm] from the center of the wafer, and the vertical axis shows the resistivity [Ωcm]. .. FIG. 6 is a graph showing PA-RRG in each resistivity evaluation region of wafer samples according to Comparative Examples and Examples. The horizontal axis is the position of the resistivity evaluation region (-6 to +6), and the vertical axis is PA-RRG. [%] Are shown respectively.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view showing the configuration of a single crystal manufacturing apparatus according to an embodiment of the present invention.

As shown in FIG. 1, the single crystal manufacturing apparatus 1 includes a chamber 10 constituting a pulling furnace for a silicon single crystal 2, a quartz rut 12 installed in the chamber 10, and a graphite susceptor supporting the quartz rut 12. 13, a shaft 14 that supports the susceptor 13 so as to be able to move up and down and rotatably, a heater 15 arranged around the susceptor 13, a heat shielding member 16 arranged above the quartz rut 12, and above the quartz rut 12. A single crystal pulling wire 17 arranged coaxially with the shaft 14, a wire winding mechanism 18 arranged above the chamber 10, a dopant supply device 20 for adding the dopant 5 into the quartz apex 12, and each part. It is provided with a control unit 30 for controlling the above.

The chamber 10 is composed of a main chamber 10a, a top chamber 10b that covers the upper opening of the main chamber 10a, and an elongated cylindrical pull chamber 10c connected to the upper opening of the top chamber 10b. The susceptor 13, the heater 15, and the heat shielding member 16 are provided in the main chamber 10a. The susceptor 13 is fixed to the upper end of a shaft 14 provided in the vertical direction through the center of the bottom of the chamber 10, and the shaft 14 is moved up and down and rotationally driven by the shaft drive mechanism 19.

The heater 15 is used to melt the polycrystalline silicon raw material filled in the quartz crucible 12 to generate the silicon melt 3. The heater 15 is a carbon resistance heating type heater, and is provided so as to surround the quartz crucible 12 in the susceptor 13. A heat insulating material 11 is provided on the outside of the heater 15. The heat insulating material 11 is arranged along the inner wall surface of the main chamber 10a, whereby the heat retaining property in the main chamber 10a is enhanced.

The heat shielding member 16 is provided to prevent the silicon single crystal 2 from being heated by the radiant heat from the heater 15 and the quartz crucible 12 and to suppress the temperature fluctuation of the silicon melt 3. The heat shielding member 16 is a substantially cylindrical member whose diameter decreases from the upper side to the lower side, and is provided so as to cover the upper part of the silicon melt 3 and surround the growing silicon single crystal 2. It is preferable to use graphite as the material of the heat shielding member 16. An opening larger than the diameter of the silicon single crystal 2 is provided in the center of the heat shielding member 16 to secure a pulling path for the silicon single crystal 2. As shown, the silicon single crystal 2 is pulled upward through the opening. Since the diameter of the opening of the heat shielding member 16 is smaller than the diameter of the quartz crucible 12 and the lower end portion of the heat shielding member 16 is located inside the quartz crucible 12, the upper end of the rim of the quartz crucible 12 is from the lower end of the heat shielding member 16. The heat shielding member 16 does not interfere with the quartz crucible 12 even if it is raised upward.

Although the amount of melt in the quartz rut 12 decreases with the growth of the silicon single crystal 2, the rise of the quartz rut 12 is controlled so that the distance (gap) between the melt surface and the heat shielding member 16 becomes constant. It is possible to control the evaporation amount of the dopant from the silicon melt 3 by suppressing the temperature fluctuation of the silicon melt 3 and keeping the flow velocity of the Ar gas flowing near the melt surface (purge gas guide path) constant. Therefore, it is possible to improve the stability of the crystal defect distribution, the oxygen concentration distribution, the resistivity distribution, etc. in the pulling axis direction of the silicon single crystal 2.

Above the quartz crucible 12, a wire 17 which is a pulling shaft of the silicon single crystal 2 and a wire winding mechanism 18 for winding the wire 17 are provided. The wire winding mechanism 18 has a function of rotating the silicon single crystal 2 together with the wire 17. The wire winding mechanism 18 is arranged above the pull chamber 10c, the wire 17 extends downward from the wire winding mechanism 18 through the inside of the pull chamber 10c, and the tip of the wire 17 is inside the main chamber 10a. It has reached the space. FIG. 1 shows a state in which the silicon single crystal 2 being grown is suspended from the wire 17. When pulling up the single crystal, the seed crystal is immersed in the silicon melt 3, and the single crystal is grown by gradually pulling up the wire 17 while rotating the quartz rut pot 12 and the seed crystal, respectively.

A gas intake port 10d for introducing Ar gas (purge gas) into the chamber 10 is provided in the upper part of the pull chamber 10c, and a gas for exhausting the Ar gas in the chamber 10 is provided at the bottom of the main chamber 10a. An exhaust port 10e is provided. The Ar gas supply source 31 is connected to the gas intake port 10d via the mass flow controller 32, Ar gas from the Ar gas supply source 31 is introduced into the chamber 10 from the gas intake port 10d, and the introduced amount is the mass flow controller. It is controlled by 32. Further, since the Ar gas in the sealed chamber 10 is exhausted to the outside of the chamber 10 from the gas exhaust port 10e, it is possible to recover the SiO gas and CO gas in the chamber 10 and keep the inside of the chamber 10 clean. Become.

A vacuum pump 33 is connected to the gas exhaust port 10e via a pipe, and the inside of the chamber 10 is in a constant depressurized state by controlling the flow rate with the valve 34 while sucking Ar gas in the chamber 10 with the vacuum pump. It is kept in. The air pressure in the chamber 10 is measured by a pressure gauge, and the amount of Ar gas exhausted from the gas exhaust port 10e is controlled so that the air pressure in the chamber 10 is constant.

The dopant supply device 20 includes a dopant supply tube 21 drawn from the outside of the chamber 10 into the inside thereof, a dopant hopper 22 installed outside the chamber 10 and connected to the upper end of the dopant supply tube 21, and a dopant supply tube 21. It is provided with a seal cap 23 for sealing the opening 10f of the top chamber 10b through which the top chamber 10b penetrates.

The dopant supply pipe 21 is a pipe that reaches directly above the silicon melt in the quartz crucible 12 from the installation position of the dopant hopper 22 through the opening 10f of the top chamber 10b. During the pulling up of the silicon single crystal 2, the granular dopant 5 is added from the dopant supply device 20 to the silicon melt 3 in the quartz crucible 12. The dopant 5 discharged from the dopant hopper 22 is added to the silicon melt 3 through the dopant supply pipe 21. Although the form of the added dopant 5 has been described as granular, it may be in the form of a plate. The form of the dopant is not particularly limited as long as it can be added to the silicon melt 3 in the quartz crucible 12 from the dopant supply device 20.

FIG. 2 is a flowchart for explaining a method for manufacturing a silicon single crystal 2 according to an embodiment of the present invention.

As shown in FIG. 2, in the production of the silicon single crystal 2, the quartz crucible 12 is first filled with the polycrystalline silicon raw material together with the main dopant (raw material filling step S11). The main dopant for pulling up an n-type silicon single crystal is, for example, phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) or a compound containing these, and the sub-dopants are, for example, boron (B) and aluminum. (Al), gallium (Ga), indium (In) or a compound containing these. The main dopant for pulling up a p-type silicon single crystal is, for example, boron (B), aluminum (Al), gallium (Ga), indium (In) or a compound containing these, and the sub-dopant is, for example, phosphorus (P). , Arsenic (As), antimony (Sb), bismuth (Bi) or a compound containing these.

Next, the polysilicon in the quartz crucible 12 is heated by the heater 15 and melted to generate the silicon melt 3 containing the main dopant (melting step S12).

Next, the seed crystal attached to the tip of the wire 17 is lowered and landed on the silicon melt 3 (step S13). After that, a crystal pulling step (steps S14 to S17) is carried out in which the seed crystal is gradually pulled up while maintaining the contact state with the silicon melt 3 to grow the silicon single crystal 2.

In the crystal pulling step, a necking step S14 for forming a neck portion in which the crystal diameter is narrowed to eliminate dislocations, a shoulder portion growing step S15 for forming a shoulder portion in which the crystal diameter is gradually increased, and a crystal diameter. The straight body part growing step S16 for forming a straight body part maintained at a specified diameter (for example, about 300 mm) and the tail part growing step S17 for forming a tail part having a gradually reduced crystal diameter are carried out in order. Finally, the silicon single crystal 2 is separated from the melt surface. From the above, the silicon single crystal ingot is completed.

It is preferable that the straight body portion growing step S16 has at least one counter-doping step (additional doping step) in which a sub-dopant having a conductive type having a polarity opposite to that of the main dopant is charged into the silicon melt 3. As a result, it is possible to suppress a change in resistivity in the crystal longitudinal direction of the straight body portion of the silicon single crystal 2.

Next, a counterdope for adding a sub-dopant having a conductive type having a polarity opposite to that of the main dopant will be described in detail.

3 (a) and 3 (b) are graphs showing changes in resistivity in the crystal growth direction of a silicon single crystal, and the horizontal axis is a relative value with the total length of the straight body of the crystal as 1, and the vertical axis is a vertical axis. Is shown as a relative value with the resistivity as a reference being 1.

As shown by the broken lines in FIGS. 3 (a) and 3 (b), in the case of a silicon single crystal doped with phosphorus alone as the main dopant, the resistivity of the silicon single crystal is highest at the start of raising, and gradually increases as the pulling progresses. When the crystal length exceeds about 0.44, the resistivity deviates from the standard.

Therefore, as shown by the solid line in FIGS. 3 (a) and 3 (b), before the resistivity falls below the lower limit of the standard, a conductive type sub-dopant having the opposite polarity to the main dopant is additionally charged into the silicon melt to resist the resistance. Increase the rate. In the example of FIG. 3A, the first counterdope is performed at the position where the crystal length is about 0.44, and the second counterdope is performed at the position where the crystal length is 0.63. As a result, the length of the silicon single crystal whose resistivity is within the standard can be made as long as possible, and the production yield of the silicon single crystal can be increased.

However, as shown in FIG. 3A, when as much subdopant as possible is added so that the resistivity rises from the lower limit value to the upper limit value of the standard at one counterp, the silicon single crystal is added immediately after the topant is added. There is a problem that the resistivity of the device suddenly changes and the in-plane resistivity distribution at the chip size level of a power semiconductor device such as an IGBT deteriorates.

Therefore, in the present embodiment, as shown in FIG. 3B, the in-plane resistivity is suppressed by suppressing a sudden change in resistivity by reducing the amount of dopant added at one time and increasing the number of times of dopant input. The distribution, especially the in-plane resistivity distribution in a small area corresponding to the chip size (Partial Area) can be improved.

It is preferable that the number of divided dopings and the amount of divided doping of the sub-dopant capable of improving the in-plane resistivity distribution are as small as possible as long as the resistivity standard is satisfied. For example, it is considered that the in-plane resistivity distribution is improved by continuously adding a very small amount of the sub-dopant or intermittently adding a very small amount of the sub-dopant at a high frequency. However, in this case, it is necessary to prepare and input fine granular dopants, and such fine granular doping agents are too light to fly to unexpected places and adhere to places other than the silicon melt. Therefore, it causes a high probability of dislocation of a single crystal. Further, when handling a fine and minute amount of dopant, there is a problem of measurement accuracy, and the amount of input tends to vary. For this reason, in counterdope, it is necessary to add an appropriate amount of sub-dopant at an appropriate number of times.

Hereinafter, a method for determining the number of divided dopings and the amount of divided doping of the sub-dopant at the time of counter-doping will be described in detail.

FIG. 4 is a flowchart for explaining a method of determining the number of divided dopings and the amount of divided doping of the sub-dopant at the time of counter-doping.

As shown in FIG. 4, in the method of determining the counter-doping condition according to the present embodiment, first, the maximum doping amount at one time when the sub-dopant is added is calculated from the resistivity standard required for the silicon wafer (step). S21). The maximum doping amount refers to the amount of sub-dopant input required to increase the resistivity of a silicon single crystal from the standard lower limit value to the standard upper limit value.

Next, a silicon single crystal (first silicon single crystal) is grown while performing one or a plurality of counter-dopings. In the one-time or a plurality of counter-dopings, the amount of the sub-dopant dropped per one time is set to the maximum doping amount obtained by the above calculation (step S22).

Next, a crystal portion grown during the counterdoping period is cut out from the silicon single crystal thus obtained to prepare a sample for resistivity evaluation of a silicon wafer (step S23).

Next, the radial distribution of the resistivity of the wafer sample is measured (step S24). The resistivity measurement pitch (first pitch) is not particularly limited, but is preferably 1 mm or more and 5 mm or less, and more preferably 1 mm or more and 2 mm or less. The method for measuring the resistivity of the silicon wafer is not particularly limited, but it is preferable to measure the resistivity by the four-probe method.

Next, the wafer sample is partitioned in the radial direction at a predetermined pitch, a plurality of resistivity evaluation regions are set, and PA-RRG (Partial Area-Resistivity Radial Gradient), which is an index of resistivity deviation in each resistivity evaluation region, is set. ) (Step S25). PA-RRG is an index showing the magnitude of in-plane variation of resistivity in a specific section region instead of the entire surface of the wafer, and has a maximum value ρ _max and a minimum value ρ _min of the resistivity in the resistivity evaluation region. The value obtained by dividing the difference by the minimum value ρ _min is expressed as a percentage. That is, it can be obtained as PA-RRG = (ρ _max −ρ _min ) / ρ _min × 100 [%].

The section pitch (second pitch) in the resistivity evaluation region is a value arbitrarily determined based on the chip size of the semiconductor device manufactured using the silicon wafer, and is preferably 10 mm or more and 20 mm or less, preferably 12 mm or more. It is particularly preferably 16 mm or less. Alternatively, the section pitch in the resistivity evaluation region is preferably three times or more the radial measurement pitch (first pitch) of the resistivity. In other words, the resistivity measurement pitch is preferably a pitch that can measure three or more points in the resistivity evaluation region. This makes it possible to improve the reliability of the measured values of PA-RRG.

Next, the number of divided dopings and the amount of divided doping of the sub-dopant necessary for the maximum value PA-RRG _max of the plurality of PA-RRGs obtained from the wafer sample to be equal to or less than the target value PA-RRG _target are obtained (step S26). .. The number of division dopings of the sub-dopant can be obtained as the minimum value among positive integers larger than the value obtained by dividing the maximum value PA-RRG _max of PA-RRG by the target value PA-RRG _target . In this way, by intermittently charging the sub-dopant by reducing the number of times the sub-dopant is charged as much as possible, the amount of the sub-dopant added can be correctly controlled, and the probability of dislocation of the single crystal can be reduced.

After that, the subsequent silicon single crystal (second silicon single crystal) is grown while counter-doping the sub-dopant of the number of division dopings and the division doping amount so that PA-RRG is equal to or less than the target value (step S27). ).

As described above, in the method for producing a silicon single crystal according to the present embodiment, the number of divided dopings and the amount of divided doping of the sub-dopant are determined in advance so that the PA-RRG is equal to or less than the target value, and counter-doping is performed accordingly. Therefore, it is possible to manufacture a silicon wafer in which the in-plane resistivity distribution in a narrow region corresponding to the chip size is improved so as to satisfy the standard.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the present invention, and these are also the present invention. Needless to say, it is included in the range.

(Comparative example)
An n-type silicon single crystal having a diameter of about 200 mm having phosphorus as a main dopant and boron as a secondary dopant was grown by the CZ method. At that time, counter-doping was performed twice while the straight body was being pulled up. A wafer sample was prepared by cutting out a crystal portion solidified immediately after charging the sub-dopant of the silicon single crystal, and the in-plane resistivity distribution of the wafer sample was measured by a four-probe method.

Next, the wafer sample was partitioned in the radial direction at a pitch of 12 to 16 mm, and 13 resistivity evaluation regions were set. Table 1 shows the range of each resistivity evaluation region. The "position" is a numbered resistivity evaluation region divided in the radial direction.

Subsequently, PA-RRG (Partial Area-Resistivity Radial Gradient) of each resistivity evaluation region was obtained based on the resistivity distribution of the wafer sample. Since the resistivity distribution was measured at a pitch of 2 mm in the radial direction, the number of resistivity data obtained from one resistivity evaluation region is 7 to 9 points.

FIG. 5 is a graph showing the measurement results of the resistivity distribution of the wafer sample according to the comparative example and the example. The horizontal axis shows the distance [mm] from the center of the wafer, and the vertical axis shows the resistivity [Ωcm]. ..

As shown in FIG. 5, the resistivity of the wafer sample according to the comparative example was lower in the central portion than in the outer peripheral portion. It is considered that this is because the outer peripheral portion of the wafer is solidified before the central portion, so that the dopant concentration is lowered and the resistivity of the outer peripheral portion is increased.

FIG. 6 is a graph showing PA-RRG in each resistivity evaluation region of wafer samples according to Comparative Examples and Examples. The horizontal axis is the position of the resistivity evaluation region (-6 to +6), and the vertical axis is PA-RRG. [%] Are shown respectively.

As shown in FIG. 6, the PA-RRG of the wafer sample according to the comparative example became the maximum at the position 3, and the maximum value PA-RRG _max of the PA-RRG was 10.55%.

(Example)
In order to suppress the fluctuation of the in-plane resistivity distribution generated after counter-doping and keep the PA-RRG in each resistivity evaluation region below the target value, the number of divided dopings of the sub-dopant (boron) was determined. When the target value of PA-RRG obtained from the resistivity standard is 2.5%, if the amount of the sub-dopant dropped at one time is divided into 1/5 or less and charged, the increase value of the resistivity is 1/5. Therefore, PA-RRG can be improved to 2.5% or less. In this calculation, the rate of increase in resistivity was estimated based on the resistivity at the center of the wafer. In the comparative example, the counter dope was performed twice, so that it is sufficient to carry out the split dope 5 × 2 = 10 times or more.

Based on the above results, as shown in FIG. 3 (b), the in-plane of the silicon wafer when the divided doping amount of the sub-dopant is reduced to 1/5 and the number of divided dopings is set to 5 times (10 times in total). The resistivity distribution and PA-RRG are shown in FIGS. 5 and 6.

As shown in FIG. 5, the resistivity of the wafer sample according to the embodiment has a very small difference between the outer peripheral portion and the central portion, and the in-plane variation of the resistivity has become small. Further, as shown in FIG. 6, the PA-RRG of the wafer sample according to the embodiment was also very small, and the maximum value of PA-RRG could be set to 2.5% or less, which is the target value.

1 Single crystal manufacturing equipment 2 Silicon single crystal 3 Silicon melt 5 Dopant 10 Chamber 10a Main chamber 10b Top chamber 10c Pull chamber 10d Gas intake port 10e Gas exhaust port 10f Opening 11 Insulation material 12 Quartz rut 13 Suceptor 14 Shaft 15 Heater 16 Heat shield member 17 Wire 18 Wire winding mechanism 19 Shaft drive mechanism 20 Dopant supply device 21 Dopant supply tube 22 Dopant hopper 23 Seal cap 30 Control unit 31 Ar Gas supply source 32 Mass flow controller 33 Vacuum pump 34 Valve S11 Raw material filling process S12 Melting Process S14 Necking process S15 Shoulder part growing process S16 Straight body part growing process S17 Tail part growing process

Claims (7)

A step of growing a first silicon single crystal by adding a sub-dopant having a conductive type having a polarity opposite to that of the main dopant.
A step of cutting out a crystal portion grown during the period of adding the sub-dopant from the first silicon single crystal to prepare a wafer sample.
The step of measuring the radial distribution of the resistivity of the wafer sample at the first pitch, and
A step of obtaining PA-RRG, which is a deviation index of resistivity in each of a plurality of resistivity evaluation regions obtained by partitioning the wafer sample in a second pitch wider than the first pitch in the radial direction.
A step of obtaining the number of divided dopings and the amount of divided doping of the sub-dopant necessary for the maximum value of the PA-RRG obtained from the wafer sample to be equal to or less than the target value.
A method for producing a silicon single crystal, which comprises a step of adding the sub-dopant of the divided doping amount at the number of times of the divided doping to grow a second silicon single crystal. The method for producing a silicon single crystal according to claim 1, wherein the number of division dopings is the minimum value among positive integers larger than the maximum value of PA-RRG divided by the target value. Before growing the first silicon single crystal, a step of obtaining the maximum doping amount at one time when adding the sub-dopant from the resistivity standard required for the silicon wafer is further provided.
In the step of growing the first silicon single crystal, the sub-dopant having the maximum doping amount is added.
The method for producing a silicon single crystal according to claim 1 or 2, wherein the split doping amount is a value obtained by dividing the maximum doping amount by the number of split dopings. The PA-RRG is a value expressed as a percentage by dividing the difference between the maximum value and the minimum value of the resistivity in the resistivity evaluation region by the minimum value, and is any one of claims 1 to 3. The method for producing a silicon single crystal according to the section. The method for producing a silicon single crystal according to any one of claims 1 to 4, wherein the second pitch is three times or more the first pitch. The method for producing a silicon single crystal according to any one of claims 1 to 5, wherein the first pitch is 1 mm or more and 5 mm or less. The method for producing a silicon single crystal according to any one of claims 1 to 6, wherein the second pitch is 10 mm or more and 20 mm or less.

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