JP2022037770A - Method for reducing occurrence rate of cracks in semiconductor wafer - Google Patents

Abstract

To provide a method for reducing the occurrence rate of cracks in a semiconductor wafer in a wafer manufacturing process or device forming process.SOLUTION: A method of reducing the occurrence rate of cracks in a semiconductor wafer includes: a first step in which scratches can be formed on the semiconductor wafer in a process of manufacturing the semiconductor wafer from a semiconductor ingot and forming a semiconductor device on the manufactured semiconductor wafer; a second step in which stress is applied to the semiconductor wafer that has undergone the first step and the semiconductor wafer can be cracked; and a third step, between the first step and the second step, of performing a bending test in which stress corresponding to stress applied to the semiconductor wafer in the second step is applied to the semiconductor wafer to determine whether or not the semiconductor wafer is cracked, and transferring the unbroken semiconductor wafer to the second step.SELECTED DRAWING: Figure 1

Description

The present invention relates to a method for reducing the occurrence rate of cracks in a semiconductor wafer.

Conventionally, silicon wafers have been widely used as substrates for semiconductor devices. Silicon wafers are subjected to, for example, slicing treatment, flattening treatment, chamfering treatment, and etching for single crystal silicon ingots grown by the Czochralski (CZ) method, the floating zone melting (Floating Zone, FZ) method, or the like. Manufactured by subjecting to treatment, heat treatment, double-sided polishing, finish polishing, etc. (wafer manufacturing process).

In the semiconductor device, the silicon wafer manufactured as described above is subjected to, for example, a film forming process, an exposure / development process, an etching process, and an impurity diffusion process to form an LSI on the surface of the silicon wafer (pre-process) and dicing. It is formed by performing a treatment, a thinning treatment, a mounting treatment, a bonding treatment, a molding treatment, etc. (post-process) (device forming process).

In the pre-processes of the wafer manufacturing process and the device forming process on the wafer, impacts, stresses, and the like are often applied to the silicon wafer, and scratches are likely to be formed on the silicon wafer. For example, in the wafer manufacturing process, the wafer end abuts on the inner peripheral surface of the holder during the grinding process or the polishing process, so that an impact is applied to the wafer end. Similarly, in the pre-process of the device forming step, in the oxidative heat treatment step which is the first heat treatment step, scratches are likely to be formed on the silicon wafer due to contact with a jig such as a boat.

When scratches are formed on the silicon wafer as described above, the fracture strength of the wafer is lowered, and when stress is applied to the silicon wafer in the subsequent process, the silicon wafer may be cracked. If the silicon wafer is broken, it is necessary to perform cleaning and inspection of the equipment in the recovery work and the processing thereof, and there is a concern that a great loss may occur in the manufacture of the silicon wafer or the formation of the semiconductor device.

Against this background, Patent Document 1 describes an apparatus capable of accurately evaluating the strength of the wafer end in order to prevent scratches on the wafer end during the wafer manufacturing process.

Japanese Unexamined Patent Publication No. 2011-027430

The apparatus described in Patent Document 1 can perform a fracture test of a wafer and accurately measure the strength of the wafer itself. However, Patent Document 1 does not study reducing the occurrence rate of wafer cracking.

Therefore, an object of the present invention is to propose a method for reducing the occurrence rate of cracks in a semiconductor wafer in a wafer manufacturing process or a device forming process.

The present invention that solves the above problems is as follows.
[1] A method for suppressing the occurrence rate of cracks in a semiconductor wafer.
In the process of manufacturing a semiconductor wafer from a semiconductor ingot and forming a semiconductor device on the manufactured semiconductor wafer, a first step in which a scratch can be formed on the semiconductor wafer and a stress on the semiconductor wafer after the first step are applied. During the second step, where the semiconductor wafer can be cracked under load,
In the second step, a bending test is performed in which a stress corresponding to the stress applied to the semiconductor wafer is applied to the semiconductor wafer to determine whether or not the semiconductor wafer is cracked, and the unbroken semiconductor wafer is referred to as the first. A method for reducing the occurrence rate of cracks in a semiconductor wafer, which comprises a third step of transporting to two steps.

[2] The method according to the above [1], wherein the third step is performed immediately before the second step.

[3] The method according to [1] or [2], wherein the third step is performed on all of the semiconductor wafers that have undergone the first step.

[4] The method according to [1] or [2], wherein the third step is performed only on a part of the semiconductor wafer that has undergone the first step.

[5] A fourth step of inspecting the appearance of the semiconductor wafer is further provided between the first step and the third step, and the semiconductor wafer determined to be defective in the fourth step is further provided with the first step. The method according to any one of the above [1] to [4], wherein the three steps are performed.

[6] The third step is any one of the above [1] to [5], wherein the semiconductor wafer is rotated in the circumferential direction of the wafer and a plurality of arrangements in which the positions of stress applied to the semiconductor wafer are different are arranged. The method described in the section.

[7] The method according to any one of [1] to [6] above, wherein the semiconductor wafer is a silicon wafer.

According to the present invention, it is possible to reduce the occurrence rate of cracks in a semiconductor wafer in a wafer manufacturing process or a device forming process.

It is a figure which shows the flowchart of an example of the method of reducing the occurrence rate of cracking of a semiconductor wafer by this invention. It is a figure which shows the three-point bending test apparatus. It is a figure which shows the 4-point bending test apparatus. It is a figure which shows the flowchart of another example of the method of reducing the occurrence rate of cracking of a semiconductor wafer by this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a flowchart of a method for reducing the occurrence rate of cracks in a semiconductor wafer according to the present invention. The method for reducing the occurrence rate of cracks in a semiconductor wafer according to the present invention is a first step in the process of manufacturing a semiconductor wafer from a semiconductor ingot and forming a semiconductor device on the manufactured semiconductor wafer, in which scratches may be formed on the semiconductor wafer. The stress applied to the semiconductor wafer in the second step between (step S1) and the second step (step S2) in which the semiconductor wafer that has undergone the first step is stressed and the semiconductor wafer can be cracked. A third step (step S3) of transporting the unbroken semiconductor wafer to the second step is provided by performing a bending test in which a stress corresponding to the above is applied to the semiconductor wafer to determine whether or not the semiconductor wafer is cracked. It is a feature.

As described above, in the wafer manufacturing process and the device forming process, scratches are formed on the surface of the semiconductor wafer, which is the substrate of the semiconductor device, in a certain processing process (first step), and in the subsequent processing step (second step). The semiconductor wafer can crack. When wafer cracking occurs in the second step, a large loss is caused in the manufacture of semiconductor wafers or the formation of semiconductor devices by cleaning and inspecting the equipment. In order to reduce such loss, it is important to reduce the occurrence rate of cracks in the semiconductor wafer.

Therefore, the present inventors have diligently studied ways to reduce the occurrence rate of cracks in semiconductor wafers. As a result, in the wafer manufacturing process and the device forming process, the semiconductor wafer is cracked due to stress applied to the semiconductor wafer in the previous stage (first step) in which scratches can be formed on the surface of the semiconductor wafer and the semiconductor wafer that has undergone the first step. A bending test is performed in which a stress corresponding to the stress applied to the semiconductor wafer in the second step is applied to the semiconductor wafer during the subsequent step (second step) to determine whether or not the semiconductor wafer is cracked. However, he came up with the idea of performing the third step of transporting the unbroken semiconductor wafer to the second step, and completed the present invention. Hereinafter, each step will be described.

First, the first step is a step in which a semiconductor wafer is processed to form scratches on the surface of the semiconductor wafer in the wafer manufacturing step or the device forming step. In the present invention, the "scratch" means a scratch unintentionally formed on the surface of a semiconductor wafer by contact with a component such as an apparatus in a series of steps of a wafer manufacturing process and a device forming process, for example. Includes scratches and cracks.

Examples of such a first step include a wire saw process, a chamfering process, a surface grinding process, a heat treatment process, a double-sided polishing process, and a finish polishing process in a wafer manufacturing process. In particular, scratches are likely to be formed in the wire saw process, the chamfering process, the heat treatment process, and the double-sided polishing process.

For example, in the wire saw process, if cutting is started with foreign matter attached to the wire, cracks may be introduced into the semiconductor wafer. Further, in the chamfering process, the surface grinding process, and the polishing process, if there is a defect in the grindstone or the pad, cracks may be introduced in the semiconductor wafer. Further, in the heat treatment step, in the semiconductor wafer, a member having a hard surface that supports the semiconductor wafer comes into contact with the semiconductor wafer during the heat treatment, so that cracks may be introduced in the semiconductor wafer.

In addition, examples of the first step include steps involving raising and lowering the temperature, such as an oxidation step, a CVD step, and an impurity diffusion step in the device forming step.

Further, even in a part of the transfer steps between the steps of processing the semiconductor wafer, scratches may be formed on the surface of the semiconductor wafer. The transfer step in which such scratches can be formed is also included in the first step.

The second step is a step after the first step, which is a step in which a semiconductor wafer is processed in a wafer manufacturing step or a device forming step, and a stress is applied to the semiconductor wafer to cause the semiconductor wafer to crack. .. Examples of such a second step include a chamfering step, a surface grinding step, a polishing step, and a heat treatment step in the wafer manufacturing process. In the chamfering process, the surface grinding process, and the polishing process, the grinding material or the polishing material is pressed against the semiconductor wafer, so that a force is applied to the semiconductor wafer. Further, in the heat treatment step, a thermal stress is applied to the semiconductor wafer due to a temperature difference in the semiconductor wafer, and the semiconductor wafer may be cracked.

Further, as the second step, a high-speed elevating temperature heat treatment step in the device forming step can be mentioned.

In the present invention, the first step and the second step are different steps from each other.

In the present invention, is the semiconductor wafer cracked by performing a bending test in which a stress corresponding to the stress applied to the semiconductor wafer in the second step is applied to the semiconductor wafer between the first step and the second step described above? It is determined whether or not the wafer is broken, and the third step of transporting the unbroken semiconductor wafer to the second step is performed. As a result, it is possible to prevent the semiconductor wafer from cracking in the second step, and it is possible to reduce the occurrence rate of cracking of the semiconductor wafer.

The third step, which is the bending test step, can be performed, for example, by using the mechanical strength measuring device for a silicon wafer described in Japanese Patent Application Laid-Open No. 2011-27430, which is a patent application filed by the present applicant.

FIG. 2 shows a mechanical strength measuring device described in Japanese Patent Application Laid-Open No. 2011-27430 for applying stress to a semiconductor wafer by performing a three-point bending test on the semiconductor wafer. In the apparatus shown in FIG. 2, the pressing member 2 is placed from directly above the semiconductor wafer w in a state where the semiconductor wafer w is placed on a pair of rod-shaped support members 1a and 1b arranged in parallel with each other at predetermined intervals. Is lowered to press the center of the wafer. As a result, a test load is applied to the semiconductor wafer w to bend and deform the semiconductor wafer w in the direction of wrapping the pressing member 2, and a three-point bending test is performed on the semiconductor wafer w. At this time, scratches on the surface of the wafer can be prevented by forming the portion in contact with the wafer with a material softer than silicon, such as coating the surface of the pressing member 2 with Teflon (registered trademark).

The longitudinal dimensions of the support members 1a and 1b and the pressing member 2 are set to about 1.1 to 1.6 times the diameter of the wafer w, and the distance between the support members 1a and 1b is about 0.5 of the diameter of the wafer w. By setting the value to about 0.7 times, the test load can be stably applied to the semiconductor wafer w, which is preferable. Arithmetic mean roughness Ra: By setting the surface of the wafer contact portion in the range of 0.4 μm or more and 3.0 μm or less, slippage between the support member and the wafer and between the pressing member and the wafer can be suppressed, and the semiconductor wafer w is set. The stress applied can be applied. This device can be used as the bending test device of the third step in the present invention.

Further, FIG. 3 shows another mechanical strength measuring device described in Japanese Patent Application Laid-Open No. 2011-27430, and stress is applied to the semiconductor wafer by performing a four-point bending test on the semiconductor wafer. Shown is a mechanical strength measuring device. In the apparatus shown in FIG. 3, the semiconductor wafer w is placed on a pair of rod-shaped support members 1a and 1b arranged in parallel with each other at a predetermined interval, and the semiconductor wafer w is placed at a predetermined interval from directly above the semiconductor wafer w. A pair of rod-shaped pressing members 2a and 2b arranged in parallel with each other are lowered to press the central portion of the wafer. As a result, a test load is applied to the semiconductor wafer w to bend and deform the semiconductor wafer w in the direction of wrapping the pressing members 2a and 2b, and a four-point bending test is performed on the semiconductor wafer w.

The longitudinal dimensions of the support members 1a and 1b and the pressing members 2a and 2b are set to about 1.1 to 1.6 times the diameter of the wafer w, and the distance between the support members 1a and 1b is about 0 of the diameter of the wafer w. .. By setting the distance between the pressing members 2a and 2b to about 0.1 to 0.35 times the diameter of the wafer w, the test load can be stably applied to the semiconductor wafer w. Is possible and preferable. Further, by setting the surface of the wafer contact portion in the range of arithmetic mean roughness Ra: 0.4 μm or more and 3.0 μm or less, slippage between the support member and the wafer and between the pressing member and the wafer can be suppressed, and the semiconductor wafer w. The stress set in can be applied. This device can be used as the bending test device of the third step in the present invention.

By using the apparatus shown in FIGS. 2 and 3 as the bending test apparatus in the third step of the present invention, it is possible to apply a stress corresponding to the stress applied in the second step to the semiconductor wafer.

In the bending test using the bending test device, the test load is applied to the portions where the pressing members 2, 2a and 2b come into contact with each other. Therefore, when the position of the scratch on the surface of the semiconductor wafer w deviates from the pressing members 2, 2a and 2b, the force applied to the scratch may be weakened. When the position where the scratch is formed is apparent by visual inspection or the like, the scratch is arranged directly under the pressing members 2, 2a and 2b. If the existence of scratches and the position of scratches are unknown, the semiconductor wafer w can be rotated in the circumferential direction of the wafer, and a bending test can be performed on a plurality of arrangements in which the positions of stress applied to the semiconductor wafer w are different. preferable. This can be done, for example, by rotating the semiconductor wafer w at predetermined angles (for example, 30 °).

Further, the semiconductor wafer w used in the method of the present invention is not particularly limited, and is limited to group IV semiconductors such as silicon, germanium and silicon carbide, and group III-V such as gallium arsenide, indium arsenide, gallium nitride and aluminum nitride. It can be a semiconductor wafer. Above all, it can be suitably applied to silicon wafers.

The third step can be performed only on a part of the semiconductor wafer that has undergone the first step. That is, depending on the processing process, it may be difficult to perform a bending test on all semiconductor wafers. In such a case, a bending test can be performed on some semiconductor wafers. It is not possible to uniquely determine at what rate the bending test can suppress the crack occurrence rate of the semiconductor wafer because it depends on the process. Therefore, the frequency of cracking of the semiconductor wafer in the second step may be measured in advance, and the bending test may be performed at a rate at which the crack occurrence rate can be reduced.

However, it is preferable that the third step is performed on all the semiconductor wafers that have undergone the first step. As a result, it is possible to prevent the semiconductor wafer that has undergone the first step from cracking in the second step, and it is possible to further suppress the occurrence rate of cracks in the semiconductor wafer.

Further, the third step can be performed immediately before the second step. This makes it possible to reduce the number of times of the third step, which is a bending test, and reduce the occurrence rate of cracks in the semiconductor wafer.

Further, in the wafer manufacturing process, there is a process (visual inspection process) of detecting surface abnormalities such as cracks by a surface inspection device or a visual visual inspection, and in the visual inspection process, cracks that cause the semiconductor wafer to crack are found in the wafer. If it is detected on the surface and determined to be abnormal, treatment (disposal) is taken to remove it from the wafer manufacturing process line.

However, the wafer removed from the production line does not always crack during the second process. When the cause determined to be abnormal is the presence of an aggregate of LPD (Light Point Defect) that does not affect the decrease in the breaking strength of the semiconductor wafer on the wafer surface, or the case of microcracks existing only on the outermost layer of the wafer. , It may be removed by the polishing step or the etching step which is the second step, and it is considered that cracks do not occur. If these semiconductor wafers are removed from the wafer manufacturing process line as defective products and discarded, the production volume will decrease.

Therefore, as shown in FIG. 2, the semiconductor wafer that has undergone the second step is transported to the fourth step, which is the visual inspection step, and the semiconductor wafer determined to be a non-defective product in the fourth step is transported to the second step, and is a defective product. In the wafer manufacturing process of discarding the semiconductor wafer determined to be defective, the third step, which is a bending test, is performed on the defective semiconductor wafer. Then, the unbroken semiconductor wafer is transported to the second step.

As a result, only the cracked semiconductor wafer can be excluded from the semiconductor wafers determined to be abnormal and excluded from the wafer manufacturing process line, and the unbroken semiconductor wafer can be returned to the wafer manufacturing process line again. As a result, it is possible to suppress the occurrence rate of cracks in the semiconductor wafer and improve the productivity of wafer manufacturing.

Hereinafter, examples of the present invention will be described, but the present invention is not limited to the examples.

<Examination of stress to be applied to the wafer>
When the semiconductor wafer is a silicon wafer having a diameter of 300 mm, the first step in which scratches can be formed on the surface of the silicon wafer is the wire saw step in the wafer manufacturing process, and the second step in which the silicon wafer can be cracked is the grinding step. In the third step, which is a bending test step performed between the first step and the second step, how much stress should be applied to the silicon wafer in order to prevent the silicon wafer from cracking in the second step is examined. did.

First, 300 wafers that were judged to be defective in the visual inspection were collected. Next, using the three-point bending test apparatus shown in FIG. 2, the stress applied was changed by 10 MPa, and it was determined whether or not the silicon wafer was cracked. Then, the unbroken silicon wafer was transferred to the grinding process, and it was confirmed whether or not the silicon wafer was cracked in the grinding process. The results obtained are shown in Table 1.

As shown in Table 1, when the stress applied to the silicon wafer in the third step, which is the bending test step, is 70 MPa or less, the silicon wafer not cracked in the third step is subjected to the stress loading step (second step). A crack occurred in a certain grinding process. However, when the stress applied to the silicon wafer in the third step is 60 MPa, all the wafers are not cracked in the third step, whereas when the stress applied is 70 MPa, in the third step. Two silicon wafers broke. That is, when the stress applied to the silicon wafer in the third step is 70 MPa, it can be seen that the two silicon wafers could be prevented from cracking in the second step.

Further, when the stress applied to the silicon wafer in the third step is 80 MPa or more, the silicon wafer not cracked in the third step is not cracked in the grinding step which is the stress loading step (second step). rice field. However, when the stress applied to the silicon wafer was 130 MPa or more, all the silicon wafers were cracked in the third step. Regarding this, when the stress applied to the silicon wafer was 80 MPa or more and 120 MPa or less, the silicon wafer that did not crack in the third step did not crack in the second step, so that the silicon wafer was 130 MPa or more in the third step. It turns out that stress is applied excessively. As described above, the stress applied to the silicon wafer in the third step is 80 MPa or more and 120 MPa. In this case, it is possible to prevent the silicon wafer from cracking in the grinding process which is the second step, and it is possible to prevent over-detection. Further, it is not necessary to evaluate the presence or absence of cracks by visual inspection.

(Example 1)
According to the flowchart shown in FIG. 1, the method for reducing the occurrence rate of cracks in a semiconductor wafer according to the present invention was carried out. Specifically, the single crystal silicon ingot grown by the Czochralski (CZ) method was transferred to the outer peripheral grinding process to adjust the diameter to 300 mm, and then transferred to the wire saw process (first step). Each of the obtained 1190 silicon wafers was subjected to a three-point bending test step (third step) using the apparatus shown in FIG. 2 before being transferred to the grinding step (second step). At that time, the stress applied to the silicon wafer was set to 80 MPa. As a result, seven silicon wafers were broken. The 1183 unbroken silicon wafers were transferred to the grinding process and subjected to batch grinding. As a result, no silicon wafer was broken in the grinding process. In this way, the rate of occurrence of cracks in silicon wafers in the grinding process is 0%, and the ratio of the number of silicon wafers that have passed through the grinding process to the number of silicon wafers that have passed through the wire saw process is 99.4%. Met.

(Conventional example 1)
The single crystal silicon ingot grown by the CZ method was transferred to the same process as in Example 1. However, each of the 1432 silicon wafers obtained by the wire saw step (first step) was directly conveyed to the grinding step (second step). As a result, eight silicon wafers were cracked in the grinding process. Since the remaining silicon wafers that had been ground at the same time as the cracked silicon wafers could not be used, as a result, 30 silicon wafers including the cracked wafers were discarded. As described above, the rate of occurrence of cracks in the silicon wafer in the grinding process is 0.6%, and the ratio of the number of silicon wafers that have passed through the grinding process to the number of silicon wafers that have passed through the wire saw process is 97. It was 9%.

(Example 2)
The single crystal silicon ingot grown by the CZ method was transferred to the same process as in Example 1. However, the feed rate of the single crystal silicon ingot in the wire saw process was made faster than that in Example 1. By increasing the feed rate of the single crystal silicon ingot, the time required for the wire saw process can be shortened, but the frequency of scratches being formed on the obtained silicon wafer also increases, and cracks are likely to occur in the grinding process. Specifically, a bending test was performed on each of the 561 silicon wafers obtained by increasing the feed rate in the wire saw process. As a result, 38 silicon wafers were broken. As a result of transporting 523 unbroken silicon wafers to the grinding process, none of them cracked in the grinding process. In this way, the rate of occurrence of cracks in silicon wafers in the grinding process is 0%, and the ratio of the number of silicon wafers that have passed through the grinding process to the number of silicon wafers that have passed through the wire saw process is 93.2%. Met.

(Conventional example 2)
The single crystal silicon ingot grown by the CZ method was transferred to the same process as in Example 2. However, the bending test process was not performed on the silicon wafer between the wire saw process and the grinding process. Specifically, as a result of transporting 523 silicon wafers obtained in the wire saw process to the grinding process, 41 silicon wafers were cracked. At the same time, 67 silicon wafers that had been ground were discarded, and a total of 108 silicon wafers were discarded. As described above, the rate of occurrence of cracks in silicon wafers in the grinding process is 7.8%, and the ratio of the number of silicon wafers that have passed through the grinding process to the number of silicon wafers that have passed through the wire saw process is 79. It was 3%.

(Example 3)
According to the flowchart shown in FIG. 4, the method for reducing the occurrence rate of cracks in a semiconductor wafer according to the present invention was carried out. Specifically, the single crystal silicon ingot grown by the Czochralski (CZ) method was transferred to the outer peripheral grinding process to adjust the diameter to 300 mm, and then transferred to the wire saw process. Each of the 2876 obtained silicon wafers was transferred to a grinding etching step (first step). The etching allowance at that time was set to 20 μm. Subsequently, a visual inspection (fourth step) was performed before transporting the silicon wafer that had undergone the first step to the double-sided polishing step (second step). As a result, 64 sheets were determined to be defective. Further, a bending test (third step) was performed on each of the 64 silicon wafers determined to be defective. As a result, only 11 sheets were broken. A total of 2865 silicon wafers, the remaining 53 wafers that were not broken in the third process and 2812 wafers that were judged to be non-defective in the fourth process, were transferred to the double-sided polishing process (second process) and made into silicon wafers in a batch manner. On the other hand, double-sided polishing treatment was applied. As a result, seven silicon wafers were cracked in the double-sided polishing process, and a total of 30 silicon wafers were discarded, including the silicon wafers that had been subjected to double-sided polishing at the same time as the cracked silicon wafers. As described above, the rate of occurrence of cracks in silicon wafers in the double-sided polishing process is 0.2%, and the ratio of the number of silicon wafers that have passed the double-sided polishing process to the number of silicon wafers that have passed the grinding and etching process is It was 98.6%.

(Conventional Example 3)
Similar to Example 3, the silicon wafer was transferred to the processing step. However, for each of the 2641 silicon wafers that have undergone the grinding and etching process, 47 silicon wafers that are judged to be defective by visual inspection are discarded, and 2594 silicon wafers that are judged to be non-defective are transported to the double-sided polishing process. did. As a result, seven silicon wafers were cracked in the double-sided polishing process, and a total of 25 silicon wafers were discarded, including the silicon wafers that had been subjected to double-sided polishing at the same time as the cracked silicon wafers. In this way, the rate of occurrence of cracks in silicon wafers in the double-sided polishing process is 0.3%, and the ratio of the number of silicon wafers that have passed the double-sided polishing process to the number of silicon wafers that have passed the grinding and etching process is It was 97.3%.

(Example 4)
The silicon wafer was treated in the same manner as in Example 3. However, in the grinding etching process, the etching allowance was set to 10 μm. The etching process is performed to remove the processing strain layer remaining on the silicon wafer. However, if the machining allowance for the etching process is reduced, the wafer can be made thinner during the wire saw process and the etching time can be shortened, resulting in manufacturing efficiency. Can be increased. However, since the amount removed is small, processing strain remains, scratches remain, and the possibility of cracking during manufacturing increases. As a result of setting the etching allowance to 10 μm, 95 silicon wafers were judged to be defective in the visual inspection (4th step) of 751 silicon wafers that had undergone the grinding and etching process, and these silicon wafers were bent. The test was conducted. As a result, 35 silicon wafers were broken. As a result of transporting 60 unbroken wafers to the double-sided polishing process and performing double-sided polishing, 11 silicon wafers were cracked, and the total of the cracked silicon wafers was combined with the silicon wafers that had been double-sided polished at the same time. 55 silicon wafers were discarded. In this way, the rate of occurrence of cracks in silicon wafers in the double-sided polishing process is 1.5%, and the ratio of the number of silicon wafers that have passed the double-sided polishing process to the number of silicon wafers that have passed the grinding and etching process is It was 88.0%.

(Conventional Example 4)
The silicon wafer was transferred to the processing process in the same manner as in the conventional example 3. As a result, of the 635 silicon wafers that had undergone the grinding and etching process, 82 were discarded as defective products in the visual inspection process, and 553 silicon wafers judged to be non-defective products were transferred to the double-sided polishing process. As a result, 10 silicon wafers were cracked in the double-sided polishing process, and a total of 50 silicon wafers were discarded, including the silicon wafers that had been subjected to double-sided polishing at the same time as the cracked silicon wafers. As described above, the rate of occurrence of cracks in the silicon wafer in the double-sided polishing process is 1.8%, and the ratio of the number of silicon wafers that have passed the double-sided polishing process to the number of silicon wafers that have passed the grinding and etching process is It was 79.2%.

(Example 5)
According to the flowchart shown in FIG. 1, the method for reducing the occurrence rate of cracks in a semiconductor wafer according to the present invention was carried out. Specifically, a silicon wafer having a diameter of 300 mm obtained in the wafer manufacturing process was transferred to the device forming process. First, a bending test (third step) was performed on each of the 197 silicon wafers that had undergone the oxidative heat treatment step (first step), which is the first heat treatment step in the device forming step, using the apparatus shown in FIG. went. As a result, the four silicon wafers were broken. The remaining 193 silicon wafers that were not cracked were transferred to the high-speed elevating and heating heat treatment step (second step). At that time, as the high-speed elevating and heating heat treatment, a single-wafer type flash lamp annealing (FLA) treatment capable of instantaneously heating the surface of the silicon wafer was adopted. During the FLA process, a large temperature difference occurs between the front and back surfaces of the silicon wafer, and the silicon wafer is loaded with stress that warps the wafer during heating. As a result of this embodiment, the number of silicon wafers cracked in the high-speed elevating and heating heat treatment process was 0. As described above, the rate of occurrence of cracks in the silicon wafer in the high-speed elevating heat treatment process is 0%, and the number of silicon wafers that have passed the high-speed elevating heat treatment process is the same as the number of silicon wafers that have passed the oxidative heat treatment process. The ratio was 98.0%.

(Conventional Example 5)
Similar to Example 5, a silicon wafer having a diameter of 300 mm obtained in the wafer manufacturing process was transferred to the device forming process. However, the 312 silicon wafers that had undergone the oxidative heat treatment step (first step), which is the first heat treatment step, were directly transferred to the high-speed elevating temperature heat treatment step (second step). As a result, 10 silicon wafers were broken in the high-speed elevating and heating heat treatment process. As described above, the rate of occurrence of cracks in the silicon wafer in the high-speed elevating temperature heat treatment process is 3.2%, and the number of silicon wafers that have passed the oxidative elevating heat treatment process is compared with that of the silicon wafer that has passed the high-speed elevating temperature heat treatment process. The ratio of the number of sheets was 96.8%.

According to the present invention, it is possible to reduce the occurrence rate of cracks in a semiconductor wafer in a wafer manufacturing process or a device forming process, which is useful in the semiconductor industry.

1a, 1b Support member 2,2a, 2b Pressing member w Wafer

Claims (7)

It is a method of suppressing the occurrence rate of cracks in semiconductor wafers.
In the process of manufacturing a semiconductor wafer from a semiconductor ingot and forming a semiconductor device on the manufactured semiconductor wafer, a first step in which a scratch can be formed on the semiconductor wafer and a stress on the semiconductor wafer after the first step are applied. During the second step, where the semiconductor wafer can be cracked under load,
In the second step, a bending test is performed in which a stress corresponding to the stress applied to the semiconductor wafer is applied to the semiconductor wafer to determine whether or not the semiconductor wafer is cracked, and the unbroken semiconductor wafer is referred to as the first. A method for reducing the occurrence rate of cracks in a semiconductor wafer, which comprises a third step of transporting to two steps. The method according to claim 1, wherein the third step is performed immediately before the second step. The method according to claim 1 or 2, wherein the third step is performed on all of the semiconductor wafers that have undergone the first step. The method according to claim 1 or 2, wherein the third step is performed only on a part of the semiconductor wafer that has undergone the first step. Between the first step and the third step, a fourth step of inspecting the appearance of the semiconductor wafer is further provided, and the third step is performed on the semiconductor wafer determined to be defective in the fourth step. The method according to any one of claims 1 to 4. The method according to any one of claims 1 to 5, wherein the third step is performed for a plurality of arrangements in which the semiconductor wafer is rotated in the circumferential direction of the wafer and the positions of stress applied to the semiconductor wafer are different. The method according to any one of claims 1 to 6, wherein the semiconductor wafer is a silicon wafer.

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