JP2022030915A - Game machine - Google Patents

Abstract

To provide a game machine that can suppress the adverse effects on the progress of a game due to the occurrence of troubles related to LCD control as much as possible.SOLUTION: A game machine includes reservation storage means for reserving and storing random number information acquired when a symbol start condition is satisfied until it is subjected to symbol variation by symbol display means, and profit state generating means for generating a profit state when a stop symbol after variation of the symbol display means becomes in a specific mode. The game machine can display a reservation notification image on liquid crystal display means, and outputs odd image data and even image data to the liquid crystal display means via wiring paths different from each other. For the reservation notification image, dynamic display with a change in a vertical direction is executed. Therefore, even if either the odd image data or the even image data is missing, dynamic display of the reservation notification image can be identified easily.SELECTED DRAWING: Figure 81

Description

The present invention relates to gaming machines such as pachinko machines and slot machines.

Most gaming machines such as pachinko machines are equipped with a liquid crystal display means for displaying a production image or the like. This liquid crystal display means is displayed and controlled based on an image data signal output from a VDP (Video Display Processor) circuit mounted on a control board and other control signals (Patent Document 1).

JP-A-2017-093632

In a conventional gaming machine, if even a part of the control signal related to the liquid crystal control is lost due to some trouble, the liquid crystal display means cannot continue the game normally, for example, an image that cannot be identified by the player is displayed. There was a possibility.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a gaming machine capable of suppressing an adverse effect on the progress of a game due to the occurrence of troubles related to liquid crystal control as much as possible.

The present invention is a symbol display means capable of variablely displaying a symbol based on random number information acquired when a symbol start condition is satisfied, and a predetermined upper limit until the random number information is subjected to symbol variation by the symbol display means. A display that controls the display of the hold storage means for holding and storing up to the number of images, the profit state generating means for generating a profit state when the stop symbol after the change of the symbol display means becomes a specific mode, and the liquid crystal display means. In a gaming machine provided with control means and capable of displaying a number of hold notification images corresponding to the number of random number information stored in the hold storage means on the liquid crystal display means, the display control means has an odd number of pixels. The odd image data corresponding to the above and the even image data corresponding to the even pixels adjacent to the odd pixels are configured to be output to the liquid crystal display means via different wiring paths, and the hold notification image is used. On the other hand, by executing the dynamic display accompanied by the change in the vertical direction, the dynamic display of the hold notification image can be easily identified regardless of whether the odd image data or the even image data is missing. It is configured to be.
Further, when the hold notification image is shifted in the horizontal direction, it may be configured to execute a dynamic display accompanied by a movement in the vertical direction.

According to the present invention, it is possible to suppress the adverse effect on the progress of the game due to the occurrence of troubles related to liquid crystal control as much as possible.

It is an overall front view of the pachinko machine which concerns on 1st Embodiment of this invention. It is an exploded perspective view of the pachinko machine. It is an exploded perspective view of the glass door of the pachinko machine. It is a top view which shows the operation effect means of the pachinko machine, the cross operation button, the volume adjustment button, the light amount adjustment button and the like. It is a front view of the game board of the pachinko machine. It is a front view of the game information display means of the pachinko machine. It is a rear view of the pachinko machine. It is an exploded perspective view of the production board case and the production control unit of the pachinko machine. It is a plan sectional view of the production board case and the production control unit of the pachinko machine. It is a block diagram which shows the whole circuit composition of the pachinko machine. It is explanatory drawing about the specification of the liquid crystal display means in the pachinko machine. It is explanatory drawing about the specification of the liquid crystal control signal in the pachinko machine. It is a block diagram which shows the structure of the liquid crystal display means in the pachinko machine. It is a block diagram which shows the whole structure of the composite chip in the pachinko machine. It is a block diagram which shows the main composition of the composite chip in the pachinko machine. It is explanatory drawing about the index space, the index table, the virtual drawing space and the drawing area in the pachinko machine. It is a block diagram which described the internal structure of the data transfer circuit in the pachinko machine together with the related circuit structure. It is a block diagram which described the internal structure of the display circuit in the pachinko machine together with the related circuit structure. It is explanatory drawing of the data valid signal ENAB in the pachinko machine. It is a figure which shows the 1st wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which shows the 2nd wiring layer in the liquid crystal control board. It is a figure which shows the 3rd wiring layer in the liquid crystal control board. It is a figure which shows the 4th wiring layer in the liquid crystal control board. It is a figure which shows the 5th wiring layer in the liquid crystal control board. It is a figure which shows the 6th wiring layer in the liquid crystal control board. It is a figure which shows the terminal information of the composite chip arranged on the liquid crystal control board. It is a figure which shows the terminal information of the control ROM arranged on the liquid crystal control board. It is a figure which extracted the wiring lines P1 to P71 from the 1st wiring layer of the liquid crystal control board. It is a figure which extracted the wiring lines P1 to P71 from the 2nd wiring layer of the liquid crystal control board. It is a figure which extracted the wiring lines P1 to P71 from the 3rd wiring layer of the liquid crystal control board. It is a figure which extracted the wiring lines P1 to P71 from the 4th wiring layer of the liquid crystal control board. It is a figure which extracted the wiring lines P1 to P71 from the 5th wiring layer of the liquid crystal control board. It is a figure which extracted the wiring lines P1 to P71 from the 6th wiring layer of the liquid crystal control board. It is an enlarged view of the region E1a in FIG. 28. It is an enlarged view of the region E1b in FIG. 28. It is an enlarged view of the region E1c in FIG. 28. It is an enlarged view of the region E3a in FIG. It is an enlarged view of the region E3b in FIG. It is an enlarged view of the region E3c in FIG. It is an enlarged view of the region E4 in FIG. 31. It is an enlarged view of the region E6a in FIG. 33. It is an enlarged view of the region E6b in FIG. 33. It is an enlarged view of the region E6c in FIG. 33. It is an enlarged view of the region E6d in FIG. 33. It is a figure which shows typically the wiring path of the wiring path P1 to P8 in the liquid crystal control board of the pachinko machine which concerns on 1st Embodiment of this invention. It is a figure which shows typically the wiring lines P9 to P17 in the liquid crystal control board. It is a figure which shows typically the wiring lines P18 to P26 in the liquid crystal control board. It is a figure which shows typically the wiring lines P27-P34 in the liquid crystal control board. It is a figure which shows typically the wiring lines P35 to P42 in the liquid crystal control board. It is a figure which shows typically the wiring lines P43 to P47 in the liquid crystal control board. It is a figure which shows typically the wiring lines P48 to P51 in the liquid crystal control board. It is a figure which shows typically the wiring lines P52 to P61 in the liquid crystal control board. It is a figure which shows typically the wiring lines P62 to P71 in the liquid crystal control board. It is a circuit diagram of the decoding circuit in the liquid crystal control board. It is a circuit diagram of the reset circuit in the liquid crystal control board. It is a figure which shows the silk printing pattern on the 1st wiring layer side in the liquid crystal control board. It is a figure which shows the 1st wiring layer in the liquid crystal interface board of the pachinko machine. It is a figure which shows the 2nd and 5th wiring layers in the liquid crystal interface board. It is a figure which shows the 3rd wiring layer in the liquid crystal interface board. It is a figure which shows the 4th wiring layer in the liquid crystal interface board. It is a figure which shows the 6th wiring layer in the liquid crystal interface board. It is a figure which extracted only the wiring lines P101 to P124 from the 1st wiring layer in the liquid crystal interface board. It is a figure which extracted the wiring lines P101 to P124 from the 2nd and 5th wiring layers of the liquid crystal interface board. It is a figure which extracted the wiring lines P101 to P124 from the 3rd wiring layer of the liquid crystal interface board. It is a figure which extracted the wiring lines P101 to P124 from the 4th wiring layer of the liquid crystal interface board. It is a figure which extracted the wiring lines P101 to P124 from the 6th wiring layer of the liquid crystal interface board. It is an enlarged view of the region E11a in FIG. 62. It is an enlarged view of the region E11b in FIG. 62. It is an enlarged view of the region E11c in FIG. 62. FIG. 6 is an enlarged view of the region E16a in FIG. 66. It is an enlarged view of the region E16b in FIG. FIG. 6 is an enlarged view of the region E16c in FIG. 66. It is a figure which shows typically the wiring lines P101 to P110 in the liquid crystal interface board of the pachinko machine which concerns on 1st Embodiment of this invention. It is a figure which shows typically the wiring lines P111 to P120 in the liquid crystal interface board. It is a figure which shows typically the wiring lines P121 to P124 in the liquid crystal interface board. It is a circuit diagram in the vicinity of the liquid crystal IF third connector in the liquid crystal interface board. It is a circuit diagram in the vicinity of the liquid crystal IF second connector in the liquid crystal interface board. It is a circuit diagram of the main part in the liquid crystal interface board of the pachinko machine. It is a block diagram which shows the schematic structure of the production control part of the pachinko machine. It is a figure which shows the type of the hold notification image and the jackpot reliability in the pachinko machine. It is explanatory drawing of the dynamic display at the time of the display start, the display | display, and the end of the display of the hold notification image in the pachinko machine. It is explanatory drawing which shows the display state of the hold notification image when either odd number image data and even number image data are missing in the pachinko machine. It is a figure which shows the distribution of the color information in the pixel unit when either the odd-numbered image data and the even-numbered image data is missing in the same pachinko machine, and (a) is a figure which a plurality of kinds of color information are distributed in the vertical direction. The case (b) shows the case where it is also distributed in the horizontal direction. It is explanatory drawing of the dynamic display at the time of shift of the hold notification image in the pachinko machine. It is a figure which shows the color distribution of the decorative pattern in the pachinko machine. It is a figure which shows the dynamic display of the decorative pattern in the pachinko machine. It is a figure which shows the operation guidance image of the pachinko machine. It is a figure which shows the example of the rainbow background image used in the full-scale rainbow image production of the pachinko machine. It is a figure which shows the time change of the rainbow background image of the pachinko machine. It is a figure which shows the specific example of the hit branch button effect NB1 of the pachinko machine. It is a figure which shows the time change of the band production image in the pachinko machine. It is a figure which shows the kind of the operation guidance image in the pachinko machine. It is a figure which shows the time change (in the case of moving 2 dots per frame) in the vicinity of the boundary of the operation valid period notification image in the same pachinko machine, (a) is the case where there is no omission of image data, (b). Indicates the case where either the odd-numbered image data or the even-numbered image data is missing. It is a figure which shows the time change when the boundary of the operation valid period notification image moves 1 dot by 1 dot every frame, (a) is the case where there is no omission of image data, (b) is an odd image data and an even image. It shows the case where any of the data is missing. It is a figure which shows the case where the color information changes in the vertical direction in the partial rainbow image production of the pachinko machine. It is a figure which shows the case where the color information changes in the left-right direction in the partial rainbow image production of the pachinko machine. It is a figure which shows the setting suggestion effect selection table of the pachinko machine. It is a figure which shows the screen display example in the setting suggestion effect of the pachinko machine. It is an explanatory diagram showing the color distribution in pixel units when moving by a predetermined dot for each frame in a rainbow effect that changes in the left-right direction with respect to the position and time of the pachinko machine, and when even / odd pixels are missing. be. It is a figure which shows the time change of the band effect image in the pachinko machine which concerns on the 2nd Embodiment of this invention. (A) is an example in which a star-shaped figure displayed during a reach effect is a rainbow image, and (b) is a diagram showing an example in which a reach title character is a rainbow image.

Hereinafter, embodiments of the invention will be described in detail with reference to the drawings. 1 to 99 illustrate the first embodiment in which the present invention is adopted for a pachinko machine. In FIGS. 1 and 2, the gaming machine main body 1 includes an outer frame 2 and a front frame 3 arranged on the front side of the outer frame 2. The front frame 3 is pivotally attached to the outer frame 2 via a vertical first hinge 4 arranged on one end side in the left-right direction, for example, on the left end side, and is pivotally attached to the outer frame 2 so as to be openable and detachable. The outer frame 2 can be locked in a closed state by the locking means 5 provided on the opposite side, for example, the right end side.

The front frame 3 includes an inner frame 6 and a front door 7 arranged on the front side of the inner frame 6. The front door 7 is pivotally attached to the inner frame 6 via a second hinge 8 in the vertical direction arranged on one end side in the left-right direction, for example, the left end side, and is pivotally attached to the inner frame 6 by the locking means 5. It can be locked in the closed state.

As shown in FIG. 2, the outer frame 2 is formed in a rectangular shape by a pair of left and right vertical frame members 2a and 2b and a pair of upper and lower horizontal frame members 2c and 2d. For example, a front cover member 9 made of synthetic resin is attached to the front lower portion of the outer frame 2 so as to connect the front lower portions of the left and right vertical frame members 2a and 2b along the front edge of the lower horizontal frame member 2d. There is. The front cover member 9 projects to the front side of the left and right vertical frame members 2a and 2b, and the inner frame 6 is arranged on the upper side thereof. Further, in the outer frame 2, for example, the outer frame upper hinge metal fitting 11 constituting the first hinge 4 is arranged in the upper left portion, and the outer frame lower hinge metal fitting 12 is also arranged in the upper left side of the front cover member 9 in the lower left portion.

The inner frame 6 is made of synthetic resin, and has a rectangular frame portion 13 that can substantially contact the front edge side of the outer frame 2 on the upper side of the front cover member 9, and a game board provided on the upper side of the frame portion 13. The mounting portion 14 and the lower mounting portion 15 provided on the lower side in the frame portion 13 are integrally provided, for example. For example, the game board 16 is detachably mounted on the game board mounting portion 14 from the front side, and the lower mounting portion 15 is arranged with the launching means 17, the lower speaker 18, and the like on the front side thereof. Further, in the inner frame 6, the main body frame upper hinge metal fittings 19 constituting the first hinge 4 and the main body frame upper hinge metal fittings 20 constituting the second hinge 8 are, for example, in the upper left portion, and the first, second hinges 4, 8 are provided. The hinge metal fittings 21 under the main body frame constituting the above are arranged, for example, in the lower left.

The front door 7 includes a resin door base 22 formed in a rectangular shape corresponding to the front side of the inner frame 6. In the door base 22, window holes 24a of the glass window 24 are formed corresponding to the front side of the game area 23 formed in the game board 16, and a plurality of window holes 24a (here, four) are formed around the window holes 24a, for example. Various effect means such as the upper speaker 25, the frame first movable effect means 26, the frame second movable effect means 27, and the blower means 28 are arranged.

On the upper front side of the door base 22, the side unit 30 is mounted on at least a part of the outer circumference of the window hole 24a, for example, a front view inverted L-shaped portion corresponding to the upper side to the right side of the window hole 24a (FIG. 1). , Fig. 3). As shown in FIGS. 2 and 3, the side unit 30 operates the fixing screw 30a, the fixing lever 30b, etc. on the back side of the front frame 3 with the front frame 3 open without using a special tool. By doing so, it can be easily attached and detached. On the front side of the side unit 30, as shown in FIG. 1, a frame first movable effect means 26 having a frame first movable body 26a, a frame second movable effect means 27 having a frame second movable body 27a, and a blowing means. A production means such as 28 is installed.

The frame first movable body 26a of the frame first movable effect means 26 is formed in an arbitrary three-dimensional shape (here, a shape with a butterfly as a motif), and slide movement in a substantially front-back direction is performed by driving a driving means (not shown in the figure). It is possible. The frame second movable body 27a of the frame second movable effect means 27 slides in a substantially front-rear direction by being driven by a driving means (not shown), and vibrates by a vibrating means (not shown) arranged in the grip portion 27b. It is also possible for the player to push the grip portion 27b. Further, the blowing means 28 can blow air toward the player's hand at the timing when the player grips the grip portion 27b. Further, on the front side of the front door 7 including the side unit 30, a frame lamp 304 composed of a large number of LEDs 301a to 301d is arranged so as to substantially surround the glass window (display window) 24.

On the lower front side of the door base 22, the upper plate 33, which stores the game balls discharged from the payout means 32 arranged on the rear side of the inner frame 6 and supplies them to the launching means 17, and the upper plate 33 are full. A lower plate 34 for storing surplus balls and the like, a launch handle 35 for operating the launching means 17, and the like are arranged, and a lower decorative cover 36 that substantially covers the upper plate 33, the lower plate 34, etc. from the front side is attached. Has been done. The lower decorative cover 36 is formed, for example, in a forward-facing bulge shape, and for example, various operation means such as an operation effect means 37, a cross operation button 38, a volume adjustment button 39, and a light amount adjustment button 40 are provided on the upper side thereof. (Fig. 4). The operation effect means 37 is used for a notice effect during a symbol change and other effects, and includes a vertically movable effect button 41 that can be pressed and operated by the player.

As shown in FIG. 2, a glass unit 50 that substantially closes the window hole 24a from the rear side is detachably mounted on the back side of the door base 22, and is attached to the edges on the first, second hinges, and 8 sides. The vertical hinge end side reinforcing sheet metal 51a arranged along the vertical direction, the vertical opening / closing end side reinforcing sheet metal 51b arranged along the opening / closing end side edge, and the left and right arranged below the window hole 24a. The lower reinforcing sheet metal 51c in the direction is detachably fixed by screwing or the like. Further, on the door base 22, the hinge metal fittings 52a on the glass door constituting the second hinge 8 are arranged, for example, in the upper left portion, and the hinge metal fittings 52b below the glass door are arranged in the lower left portion, for example.

Further, for example, a ball feed unit 53a, a lower plate guide unit 53b, and the like are mounted on the back side of the lower reinforcing sheet metal 51c. The ball feeding unit 53a is for supplying the game ball in the upper plate 33 to the launching means 17, and is arranged corresponding to the front side of the launching means 17 arranged on the inner frame 6 side, and the launching means 17 is provided. By operating the ball feed solenoid 53c in synchronization with the firing operation of the above plate 33, the game balls in the upper plate 33 are supplied one by one onto the firing rail 17a of the launching means 17.

The launching means 17 includes a launching rail 17a arranged in an inclined shape that rises to the left when viewed from the front, and a launching ball stopper 17b that supports a game ball supplied on the launching rail 17a by the ball feeding unit 53a at a launching standby position. A striking mallet 17c that is arranged corresponding to a launch standby position on the launch rail 17a and can swing around a drive shaft in the front-rear direction, and a launch drive means 17d such as a rotary solenoid that swings and drives the striking mallet 17c. When the firing handle 35 is rotationally operated, the firing driving means 17d continuously drives the striking mallet 17c in the striking direction (clockwise direction) with a firing intensity corresponding to the amount of operation.

The lower plate guide unit 53b guides the surplus ball when the upper plate 33 is full and the foul ball that has returned without reaching the game area 23 even though it was launched by the launching means 17 to the lower plate 34. For example, it is arranged adjacent to the ball feed unit 53a on the first, second hinges, 4 and 8 sides thereof.

As shown in FIG. 5, the game board 16 includes a base plate 55 made of a veneer plate, a polycarbonate plate, or the like, and a guide rail 56 for guiding a game ball launched from the launching means 17 is annular to the front side of the base plate 55. In addition to the unit parts such as the central display frame unit 57, the starting winning unit 58, and the normal winning unit 59, a large number of game nails (not shown) are arranged in the game area 23 inside the guide rail 56. Further, for example, a game information display means 60 is arranged in the lower outer part of the game area 23.

As shown in FIG. 6, the game information display means 60 includes four LED groups composed of eight LEDs 70, and a total of 32 LEDs 70 thereof are a normal symbol display means 61 and a normal hold number display means 62. , 1st special symbol display means 63, 2nd special symbol display means 64, 1st special hold quantity display means 65, 2nd special hold quantity display means 66, variation shortening notification means 67, right-handed notification means 68 and round number notification. A predetermined number is assigned to the means 69. That is, each of the eight LEDs 70 belonging to the first and second LED groups 60a and 60b constitutes the first and second special symbol display means 63 and 64, respectively, and the eight LEDs 70 belonging to the third LED group 60c are two. Each of the eight LEDs 70 belonging to the fourth LED group 60d constitutes a first special hold quantity display means 65, a second special hold quantity display means 66, a normal hold quantity display means 62, and a variation shortening notification means 67, respectively. Two form the normal symbol display means 61, the other two form the right-handed notification means 68, and the remaining four form the round number notification means 69, respectively.

On the plurality of unit parts 57 to 59 of the game board 16, a normal symbol starting means 71, a first special symbol starting means 72, a second special symbol starting means 73, a large winning means 74, a plurality of ordinary winning means 75, and the like are placed. It is provided. Further, on the rear side of the base plate 55, in addition to the liquid crystal display means (image display means) 76, a board movable effect means 77 or the like provided with a movable accessory 77a that can move the front side of the liquid crystal display means 76 is arranged. ..

The movable accessory 77a is formed in a horizontally long rectangular box shape, and its left and right ends are supported so as to be vertically movable on the outside of the side edge of the liquid crystal display means 76, and the liquid crystal display means is driven by a drive means (not shown). It is possible to move up and down between the origin position on the upper side of the display means 76 (see FIG. 5) and the operation position on the front side of the liquid crystal display means 76. Further, on the front side of the movable accessory 77a, a movable accessory lamp 314 composed of a plurality of LEDs 311 is arranged.

The central display frame unit 57 constitutes a display frame for the liquid crystal display means 76 and the movable accessory 77a, and an opening window 80 corresponding to the liquid crystal display means 76 on the rear side is formed substantially in the center, and the base plate 55 is formed. It is detachably mounted from the front side with respect to the mounting hole (not shown) formed in the front-rear direction. As shown in FIG. 5, the central display frame unit 57 is arranged on the outside of the mounting hole along the front surface of the base plate 55, and the front mounting plate 81 through which the game ball can pass, and the liquid crystal display means 76. Arranged between the left and right lower ends of the decorative frame 82, which is arranged in the shape of a front view gate extending from both the left and right sides to the upper side on the front side of the LCD and is projected forward on the inner peripheral side of the front mounting plate 81. It is equipped with a stage 83 to be played. The game ball launched by the launching means 17 and entering the upper side of the game area 23 is distributed to the left and right at the top of the decorative frame 82, and the left flow path 84a on the left side and the right flow path 84b on the right side of the central display frame unit 57. Flow down either.

The central display frame unit 57 is provided with a warp inlet 85 through which a game ball can flow in, on at least one side of the left flow path 84a side and the right flow path 84b side, for example, on the left flow path 84a side. The game ball that has flowed into the warp inlet 85 while flowing down the left flow path 84a freely rolls in the left-right direction on the stage 83, and then has a central drop portion 86 provided corresponding to the center in the left-right direction of the game area 23. It falls to the front side from any of the other parts.

Further, on the front side of the central display frame unit 57, a panel lamp 324 composed of a large number of LEDs 321a to 321c is arranged so as to correspond to at least a part of the outer circumference of the liquid crystal display means 76, for example, both the left and right sides and the upper side. A part of the board lamp 324 may also be arranged in the starting winning unit 58, the normal winning unit 59, and the like.

As shown in FIG. 5, the start winning unit 58 is arranged on the lower side of the central display frame unit 57 along the guide rail 56, and is detachably attached to the base plate 55 from the front side. As shown in FIG. 5, the normal winning unit 59 is arranged along the guide rail 56 on the left side of the starting winning unit 58 under the central display frame unit 57, and is detachably attached to the base plate 55 from the front side. ing.

The normal symbol starting means 71 is for starting the variable display of the normal symbol by the normal symbol display means 61, and is composed of a passing gate or the like through which the game ball can pass, and is a game ball detection switch for detecting the passage of the game ball. (Not shown). As shown in FIG. 5, the ordinary symbol starting means 71 is provided, for example, on the front side of the front mounting plate 81 in the right portion of the central display frame unit 57, and allows a game ball flowing down the right flow path 84b to pass through. ing.

The ordinary symbol display means 61 is for displaying a normal symbol in a variable manner, and as shown in FIG. 6, is composed of a predetermined number (here, two) of LEDs 70 in the game information display means 60, and is a normal symbol starting means. Based on the fact that the 71 detects the game ball, after those two LEDs 70 constituting the normal symbol emit light in the normal fluctuation light emission pattern, the normal random number information acquired at the time of the game ball detection by the normal symbol starting means 71 is used. If the included hit determination random number value matches a predetermined hit determination value, the fluctuation is stopped in the hit mode, and in other cases, the fluctuation is stopped in the off mode. It should be noted that the two LEDs 70 constituting the normal symbol can display one or more hit modes and one or more missed modes depending on the combination of their light emitting modes (for example, lighting / extinguishing), and are in normal fluctuation. As the light emission pattern, for example, a plurality of specific types (here, two types) of light emission modes are switched at predetermined time intervals (for example, 128 ms).

Further, when the ordinary symbol starting means 71 detects a game ball during the ordinary holding period including the symbol change of the ordinary symbol display means 61 and the ordinary profit state, the ordinary random number information acquired by the detection is predetermined. The maximum number of reserved pieces, for example, 4 pieces, is held and stored, and each time the normal holding period ends, one piece is consumed and the normal symbol is changed. The stored number of ordinary random number information (ordinary hold number) is notified to the player by the ordinary hold number display means 62 or the like. As shown in FIG. 6, the normal hold number display means 62 is composed of a predetermined number (here, two) of LEDs 70 in the game information display means 60, and each of the two LEDs 70 emits light (for example, lighting / lighting /). By combining (blinking / extinguishing), it is possible to display 5 types of normal hold numbers of 0 to 4.

The first special symbol starting means 72 is for starting the symbol variation by the first special symbol display means 63, is composed of non-opening / closing winning means having no opening / closing means, and is a game ball for detecting a winning game ball. It is equipped with a detection switch (not shown). As shown in FIG. 5, the first special symbol starting means 72 is provided in, for example, the starting winning unit 58, and is arranged in an upward opening shape on the lower side corresponding to the central drop portion 86 of the stage 83, and is left. Due to the existence of a winning route from the warp inlet 85 on the flow path 84a side via the stage 83, the probability that the game ball flowing down the left flow path 84a is higher than that of the game ball flowing down the right flow path 84b. It is possible to win a prize at. When a game ball wins a prize in the first special symbol starting means 72, a predetermined number of game balls are paid out as prize balls per winning prize.

The second special symbol starting means 73 is for starting the symbol variation by the second special symbol display means 64, and the game ball can be won in the open state and cannot be won (or from the open state) by the operation of the opening / closing unit 88. A game ball detection switch (not shown) that detects a winning game ball, and an opening / closing drive means such as an electromagnetic solenoid that opens / closes the opening / closing unit 88. When the stop symbol after the change of the normal symbol display means 61 becomes a hit mode and a normal profit state occurs, the opening / closing unit 88 changes from the closed state to the open state for a predetermined time. There is.

As shown in FIG. 5, the second special symbol starting means 73 is arranged, for example, on the front mounting plate 81 on the right side of the central display frame unit 57 and on the downstream side of the normal symbol starting means 71, and is a right flow path. The game ball that has flowed down 84b can win a prize. The opening / closing portion 88 can swing around a rotation axis in the left-right direction provided on the lower side, for example, and in the closed state, the opening / closing portion 88 becomes substantially flush with the front mounting plate 81 so that the game ball can pass through the front side and is opened. In the state, the front side of the front mounting plate 81 has an inclined shape that descends backward so that the game ball can win a prize backward. When a game ball wins a prize in the second special symbol starting means 73, a predetermined number of game balls per winning prize are paid out as prize balls.

As shown in FIG. 6, the first special symbol display means (symbol display means) 63 is composed of a predetermined number (here, eight) of LEDs 70 in the game information display means 60, and the first special symbol start means 72 On condition that the game ball is detected, after the eight LEDs 70 constituting the first special symbol emit light in the light emission pattern during the special fluctuation, when the game ball is detected by the first special symbol starting means 72 (the symbol starting condition is). If the big hit judgment random number value included in the first special random number information acquired in (when it is established) matches the predetermined big hit judgment value (when it becomes a big hit in the random number lottery), it is a big hit mode and also small. If it matches the hit determination value (when a small hit is obtained by random number lottery), the fluctuation is stopped in the small hit mode, and in other cases, the fluctuation is stopped in the off mode. When the stop symbol after the change of the first special symbol display means 63 becomes the big hit mode, the big hit game is executed, and when the stop symbol becomes the small hit mode, the small hit game is executed (profit state generating means).

As shown in FIG. 6, the second special symbol display means (symbol display means) 64 is composed of a predetermined number (here, eight) of LEDs 70 in the game information display means 60, and the second special symbol start means 73 On condition that the game ball is detected, after the eight LEDs 70 constituting the second special symbol emit light in the light emission pattern during the special fluctuation, when the game ball is detected by the second special symbol starting means 73 (the symbol starting condition is). If the big hit judgment random number value included in the second special random number information acquired in (when it is established) matches the predetermined big hit judgment value (when it becomes a big hit in the random number lottery), it is a big hit mode and also small. If it matches the hit determination value (when a small hit is obtained by random number lottery), the fluctuation is stopped in the small hit mode, and in other cases, the fluctuation is stopped in the off mode. When the stop symbol after the change of the second special symbol display means 64 becomes the big hit mode, the big hit game is executed, and when the stop symbol becomes the small hit mode, the small hit game is executed (profit state generating means).

The first and second special symbol display means 63 and 64 have one or a plurality of big hit modes, one or a plurality of small hit modes, and one or a plurality of light emission modes (for example, lighting / extinguishing) of each of the eight LEDs 70. It is possible to display the out-of-range mode, and the light emission pattern during the special fluctuation is adapted to switch the light emission mode of a specific plurality of types (here, two types) at predetermined time intervals (for example, 128 ms).

Further, during the special holding period including during the symbol change of the first special symbol display means 63, the symbol change of the second special symbol display means 64, and the big hit game, the first and second special symbol starting means 72, 73 play a game. When the sphere is detected, the first and second special random number information acquired by the sphere are stored in the holding storage means up to a predetermined upper limit holding number, for example, 4 each. Then, when the reserved memory on the second special symbol side is 1 or more at the end of the special reserved period, one reserved memory of the second special symbol is digested to change the second special symbol, and the first When only the reserved memory on the special symbol side is 1 or more, one reserved memory of the 1st special symbol is digested and the 1st special symbol is changed. As described above, in the present embodiment, when both the first special symbol and the second special symbol do not change, and both the first special symbol side and the second special symbol side have reserved memory. Is designed to give priority to the change of the second special symbol.

In the case of the present embodiment, the player strikes left at the first special symbol starting means 72 during the normal gaming state other than the special gaming state described later, and the normal symbol starting means 71 and the first during the special gaming state. 2 Since the player strikes right at the special symbol starting means 73, the first special symbol mainly fluctuates during the normal gaming state, and the second special symbol mainly fluctuates during the special gaming state.

The number of first and second special random number information (first and second special reserved numbers) stored in the reserved storage means is the first and second special reserved number display means 65, 66, the liquid crystal display means 76, and the like. Notifies the player by. Here, as shown in FIG. 6, the first and second special reserved number display means 65 and 66 are composed of a predetermined number (here, two each) of LEDs 70 in the game information display means 60, and their light emitting modes (in this case, two). For example, by combining lighting / blinking / extinguishing), it is possible to display 5 types of 1st and 2nd special hold numbers of 0 to 4.

In addition, there are two types of big hit probabilities (big hit probabilities) in the big hit determination (random number lottery) performed based on the game ball detection by the first and second special symbol starting means 72 and 73. , It is set to a high probability during the probability change state among the special game states described later, and to a low probability otherwise. Further, in the present embodiment, the set value can be set to any of a plurality of stages (here, 6 stages), and the jackpot probability (low probability and high probability) changes according to the set value (settings 1 to 6). .. For example, the larger the set value, the higher the jackpot probability.

If the big hit judgment result is a miss, select either one or a plurality of types of misses, and if the big hit judgment result is a small hit, select either one or a plurality of types of small hits. However, when the jackpot determination result is a jackpot, one or a plurality of types of jackpots (for example, two types of probabilistic jackpot and non-probability variable jackpot) are selected. Here, the probabilistic jackpot is a jackpot that causes a probabilistic state (first special gaming state) as a special gaming state after the end of the jackpot game, and the non-probability jackpot is a special gaming state as a special gaming state after the end of the jackpot game, for example, a time saving state. It is a big hit that causes (second special game state), and the distribution is performed based on the big hit symbol random value and the like.

During the time saving state, for example, the fluctuation time of the first and second special symbol display means 63 and 64 is switched to a shortened fluctuation time shorter than the normal fluctuation time for the first and second special symbols, and the winning probability for the normal symbol. From the normal probability to the high probability, the fluctuation time changes from the normal fluctuation time to the shortened fluctuation time, and the opening / closing pattern of the second special symbol starting means 73 in the normal profit state changes from the normal opening / closing pattern (for example, 0.2 seconds × 1 opening). It is possible to switch to a special opening / closing pattern (for example, 2 seconds x 3 times opening). The time saving state starts when the big hit game ends, and ends when, for example, the first and second special symbols fluctuate a predetermined number of times (for example, 50 times), or when the next big hit game occurs by then. Further, during the probability change state, in addition to the same switching as in the time saving state, for example, the jackpot probability can be switched from a low probability to a high probability. The probability change state starts when the big hit game ends, and ends, for example, when the next big hit game occurs.

The large winning means 74 is an opening / closing type winning means provided with an opening / closing plate 89 that can switch between an open state in which the game ball can win and a closed state in which the game ball cannot win. As shown in FIG. 5, for example, the central display frame unit 57. A game ball detection switch (not shown) for detecting a winning game ball and an opening / closing driving means such as an electromagnetic solenoid for opening / closing the opening / closing plate 89 are provided on the downstream side of the second special symbol starting means 73. Moreover, because it is arranged on the upstream side of the first special symbol starting means 72, the game ball that has flowed down the right flow path 84b can win a prize with a higher probability than the game ball that has flowed down the left flow path 84a. It has become. When the first and second special symbols of the first and second special symbol display means 63 and 64 stop in the jackpot mode (specific mode) after the change, the jackpot opening means 74 opens in a predetermined jackpot opening pattern. (Big hit game) When stopped in the same small hit mode, it is released in a predetermined small hit opening pattern (small hit game). When a game ball wins in the large prize-winning means 74, a predetermined number of game balls are paid out as prize balls per prize.

Further, the liquid crystal display means 76 can variablely display the decorative symbol 90 in parallel with the variable display of the first and second special symbols by the first and second special symbol display means 63 and 64, and the first and first special symbols. 2 Various images such as the first and second hold notification images X1 to X4, Y1 to Y4, and the changing hold notification image Z indicating the number of special hold notifications can be displayed.

Here, the decorative symbol 90 includes a plurality of symbol sequences (three in the left-right direction in the example of FIG. 5) composed of a plurality of symbol symbols and other symbols, and each symbol constituting each of these symbol sequences is , As shown in FIG. 5, it is composed of a combination of a symbol body portion 90a composed of numbers such as 1 to 8 and others, and a character or other decorative portion 90b attached to the symbol body portion 90a. The decorative design 90 can be arbitrarily changed in display mode such as enlargement or reduction, change of display position, and erasure of decorative portion 90b.

The decorative symbol 90, for example, starts fluctuation by vertical scrolling, horizontal scrolling, etc. for each symbol row according to a predetermined fluctuation pattern substantially at the same time as the fluctuation start of the first and second special symbols, and the stop symbol on the predetermined effective line is generated. For example, the final stop is performed substantially at the same time as the fluctuation stop of the first and second special symbols so as to have a predetermined mode. In the decorative symbol 90, for example, the case where all the stop symbols on the effective line are the same is the big hit effect mode, and the other cases are the small hit effect mode or the missed effect mode, and the first and second special symbols are the big hit effect mode. In that case, the decorative symbol 90 is in the big hit effect mode, and when the first and second special symbols are in the small hit mode, the decorative symbol 90 is in the small hit effect mode, and the first and second special symbols are in the off mode. If this is the case, the decorative symbol 90 will be removed and the effect will be produced.

Further, regarding the first and second hold notification images X1 to X4, Y1 to Y4, and the changing hold notification image Z, the first is based on the fact that the first and second special symbol starting means 72 and 73 detect the game ball. , When the number of the second special hold is increased, one additional first and second hold notification images X1 to Y1 are displayed on the liquid crystal display means 76, and the first and second special symbol display means 63, When the number of the first and second special holdings decreases based on the start of new fluctuations of the first and second special symbols according to 64, for example, the changing hold notification image Z is deleted, and the first and second special hold notification images Z are deleted. The hold notification images X1 to Y1 are shifted one by one toward the front side of the queue (for example, the right side of the screen), and the extruded first and second hold notification images X1 and Y1 are moved to, for example, a predetermined position. It is moved to change to a new pending notification image Z during fluctuation.

Further, as shown in FIG. 7, a back case 91 for supporting the liquid crystal display means 76 on the rear side of the game board 16 is mounted on the back side of the game board 16, and a main control is provided on the back side of the back case 91. The main board case 94 in which the main control board 93 constituting the unit 92 is housed, the effect interface board 96 constituting the effect control unit 95, the liquid crystal interface board 97, the liquid crystal control board 98, and the effect board case in which the ROM board 99 is stored. 100 etc. are detachably attached.

Here, the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98, and the ROM board 99 will be described in detail with reference to FIGS. 8 and 9 in detail of the state of being stored in the effect board case 100.

The effect interface board 96 and the liquid crystal interface board 97 are arranged so that the surfaces 96a and 97a are on the rear side and are close to each other on the left and right sides. The effect interface board 96 and the liquid crystal interface board 97 are the effect IF first and second connectors CN11 and CN12 arranged along the edge of the effect interface board 96 on the liquid crystal interface board 97 side, and the liquid crystal interface board 97. The liquid crystal IF first and second connectors CN21 and CN22 arranged along the edge of the effect interface board 96 side are directly connected to each other in the left-right direction. In the production interface board 96, various electronic components are arranged on both the front and back surfaces, but various ICs such as an audio processor 101 and a digital amplifier 102, and various connectors such as liquid crystal IF 1st to 3rd connectors CN21 to CN23. The audio ROM 103 and the like are arranged on the surface 96a side. Further, regarding the liquid crystal interface substrate 97, various electronic components are arranged on both the front and back surfaces of the liquid crystal interface substrate 97, and the liquid crystal IF 1st to 3rd connectors CN21 to CN23 and the liquid crystal connection 1st for connecting the liquid crystal display means 76 are connected. Various connectors such as the second connector CN24 and CN25 are arranged on the surface 97a side.

Further, the liquid crystal control board 98 is on the rear side of the effect interface board 96 and the liquid crystal interface board 97 so that the front surface 98a faces backward and the back surface 98b faces the front surfaces 96a and 97a of the effect interface board 96 and the liquid crystal interface board 97. Have been placed. In the liquid crystal control board 98, the liquid crystal control first connector CN31 provided on the back surface 98b side thereof is attached to the production IF third connector CN13 on the production interface board 96 side, and the liquid crystal control second connector CN32 also provided on the back surface 98b side. Is directly connected to the liquid crystal IF third connector CN23 on the liquid crystal interface board 97 side, respectively, so that the effect interface board 96 and the liquid crystal interface board 97 are integrated. In the liquid crystal control board 98, various electronic components are arranged on both the front and back surfaces, and the composite chip 104, the control ROM 105, the DRAM 106, the liquid crystal control third connector CN33, etc. are arranged on the front surface 98a side, and the liquid crystal control third connector CN33 and the like are arranged on the back surface 98b side. The liquid crystal control first and second connectors CN31, CN32 and the like are arranged in.

Further, the ROM substrate 99 is adjacent to the liquid crystal control substrate 98, for example, so that the front surface 99a faces backward and the back surface 99b faces the front surface 97a of, for example, the liquid crystal interface substrate 97 among the effect interface substrate 96 and the liquid crystal interface substrate 97. It is located below it. The ROM board 99 is formed by directly connecting the ROM first connector CN41 arranged on the upper edge portion on the surface 99a side to the liquid crystal control third connector CN33 arranged on the lower edge portion of the liquid crystal control board 98. It is integrated with the liquid crystal control board 98. In the ROM board 99, various electronic components are arranged on both the front and back surfaces, but the CGROM 107, the ROM first connector CN41, and the like are arranged on the surface 99a side.

As described above, the boards 96 to 99 are directly connected to each other by directly connecting the connectors to each other, so that the front surfaces 96a and 97a of the effect interface board 96 and the liquid crystal interface board 97 and the back surfaces 98b and 99b of the liquid crystal control board 98 and the ROM board 99 are used. Are connected and integrated in a state where they face each other with a predetermined gap. Therefore, when the substrates 96 to 99 are connected to each other, the back surface 98b side of the liquid crystal control substrate 98 is hidden behind the effect interface substrate 96 and the liquid crystal interface substrate 97 and cannot be visually recognized.

The effect substrate case 100 is made of a transparent synthetic resin, and is formed in a substantially box shape by a base body 111 that covers the back surface side of the substrates 96 to 99 and a cover body 112 that covers the front surface side of the substrates 96 to 99. When the boards 96 to 99 are stored in the effect board case 100, the liquid crystal control board 98 and the ROM board 99 are first connected to each other by direct connection of the connector, and then screwed to a predetermined position inside the cover body 112. Fix it. At this time, the surfaces 98a and 99a of the liquid crystal control substrate 98 and the ROM substrate 99 face each other with a predetermined gap on the inner surface side of the back wall 113 of the cover body 112.

Next, the effect interface board 96 and the liquid crystal interface board 97 are fitted into a predetermined position inside the cover body 112 from the back side of the liquid crystal control board 98 and the ROM board 99 in a state of being directly connected to each other by the direct connection of the connector. At this time, the effect IF third connector CN13 on the effect interface board 96 side is the liquid crystal control first connector CN31 on the liquid crystal control board 98 side, and the liquid crystal IF third connector CN23 on the liquid crystal interface board 97 side is the liquid crystal on the liquid crystal control board 98 side. It is coupled to the control second connector CN32 respectively.

Subsequently, the base body 111 is fitted to the cover body 112 from the back surfaces 96b and 97b of the effect interface board 96 and the liquid crystal interface board 97. Further, by screwing from the outside of the base body 111 to the screwing base 115 on the cover body 112 side via the through holes 114 of the effect interface substrate 96 and the liquid crystal interface substrate 97, the substrates 96 to 99 are produced as the effect substrate. It is fixed in a predetermined position in the case 100. The effect board case 100 in which the boards 96 to 99 are stored is detachably attached to the back side of the back case 91 with the base body 111 facing the front side and the cover body 112 facing the rear side.

Further, as shown in FIG. 7, a back cover 121 that covers the back side of the game board 16 so as to be openable and closable is detachably attached to the back side of the front frame 3, and the game ball tank 122 and the tank rail 123 are attached to the upper side thereof. However, the payout means 32 and the payout passage 124 are mounted on one side of each of the left and right sides, and when a game ball wins a prize in a winning opening such as a large winning means 74, or a ball lending command is issued from an automatic ball lending machine (not shown). At that time, the game ball in the game ball tank 122 is paid out by the payout means 32 via the tank rail 123, and the game ball is guided to the upper plate 33 via the payout passage 124. The back cover 121 is arranged so as to cover substantially the entire effect board case 100 and a part of the upper side of the main board case 94 from the rear side.

Further, a board mounting base 125 is detachably mounted on the lower portion of the back side of the front frame 3, and a power supply board case 127 in which the power supply board 126 is stored and a payout launch control board are mounted on the back side of the board mounting base 125. The payout launch board case 129 in which 128 is stored is detachably attached to each.

FIG. 10 is a block diagram showing the overall configuration of the control system of this pachinko machine. As shown in FIG. 10, the overall circuit configuration of the pachinko machine is composed of a board-side member 131 mounted on the game board 16 side and a frame-side member 132 mounted on the front frame 3 side.

First, the outline of the board side member 131 will be described. The board-side member 131 includes a main control board 93 that constitutes the main control unit 92, an effect interface board 96 that constitutes the effect control unit 95, a liquid crystal interface board 97, a liquid crystal control board 98, and a ROM board 99, as well as a game board relay board. It is composed of 133, an LED connection board 134, a main control relay board 135, a power supply relay board 136, a frame LED relay board 137, and the like.

The main control board 93 comprehensively controls the game, and is a game ball detection switch provided in the ordinary symbol starting means 71, the big winning means 74, etc., an opening / closing driving means provided in the big winning means 74, etc., and a game. Various sensors for magnetism, radio waves, vibration, etc., game information display means 60, etc. arranged in each part of the board 16 are directly connected via a relay board such as a game board relay board 133 or without a relay board. Has been done. Further, the main control board 93 is connected to the effect interface board 96 via the effect control harness 138, and can transmit the control command CMD and the strobe signal STB.

The main control relay board 135, the power supply relay board 136, and the frame LED relay board 137 are for connecting the board side member 131 to the frame side member 132, and the main control board 93 is dispensed and fired via the main control relay board 135. It is connected to the control board 128, and the effect interface board 96 is connected to the power supply board 126 via the power supply relay board 136, and to the LED connection board 139 under the frame via the frame LED relay board 137, respectively. On the main control relay board 135, the power supply relay board 136, and the frame LED relay board 137 on the game board 16 side, the board-side first to third connectors CN1a to CN3a are arranged corresponding to the rear side of the game board 16, respectively. Further, on the game board mounting portion 14 (FIG. 2) on the inner frame 6 side, the frame-side first to third connectors CN1b to CN3b are arranged so as to face the board-side first to third connectors CN1a to CN3a, respectively. When the game board 16 is mounted on the game board mounting portion 14 of the inner frame 6 from the front side, the board-side first to third connectors CN1a to CN3a are coupled to the frame-side first to third connectors CN1b to CN3b, respectively. It has become so. The frame-side first connector CN1b is provided on one end side of the payout launch control relay harness 141 connected to the payout launch control board 128, and the frame-side second connector CN2b is an effect control power supply connected to the power supply board 126. The third connector CN3b on the frame side is provided on one end side of the harness 142, and is provided on one end side of the lower frame LED connection harness 143 connected to the lower frame LED connection board 139.

The effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98, and the ROM board 99 constituting the effect control unit 95 are integrated with each other by directly connecting the connectors to each other without using a harness as described above. ..

Further, the liquid crystal display means 76 is connected to the liquid crystal interface substrate 97 from the liquid crystal connection first and second connectors CN24 and CN25 via the liquid crystal connection first and second harness 144 and 145. Further, the LED connection board 134 is connected to the effect interface board 96 via the LED connection harness 146. The LED connection substrate 134 includes various LED substrates such as the LED substrate 312 constituting the movable accessory lamp 314 and the LED substrates 322a to 322c constituting the panel lamp 324, as well as a motor used for driving control of the movable accessory 77a. A movable body driving means such as a solenoid, a position detection switch, etc. are connected.

Here, the specifications of the liquid crystal display means 76 will be described with reference to FIG. 11 and the like. The liquid crystal display means 76 is a liquid crystal color display having 1280 pixels in the horizontal direction and 1024 pixels in the vertical direction, and controls signals (ODD signal, EVEN signal) corresponding to odd pixels (ODD) and even pixels (EVEN) adjacent to each other in the left-right direction. , It is configured to be received by the receiving unit RV (RVa + RVb) via separate LVDS (Low Voltage Differential Signaling) transmission lines. Therefore, in the present embodiment, in accordance with this specification, the ODD signal (first signal) is transmitted via the first transmission line LVDS1 by the liquid crystal connection first connector CN24, the liquid crystal connection first harness 144, etc. The EVEN signal (second signal) is transmitted via the two transmission lines LVDS2 (lower left in FIG. 10).

Further, in the liquid crystal display means 76, the operation clock CK that regulates the internal operation is defined so that the frequency thereof is in the range of 40 MHz to 70 MHz (typical value is 54 MHz). This operating clock CK corresponds to the dot clock DCK, but in the following description, for convenience, the frequency of the operating clock CK is 54 MHz, which is a typical value. A configuration in which the update time (frame rate) required for updating an image of one frame in the 54 MHz operating clock CK is about 1/60 second will be described.

As its specifications, the liquid crystal display means 76 has two pixels adjacent to each other in the left-right direction of the display screen, based on the ODD signal received from the first transmission line LVDS1 and the EVEN signal received from the second transmission line LVDS2. It is configured to process simultaneously with the operating clock CK. As a result, the pixel data of 1280 pixels corresponding to one horizontal line is updated with an operation time of 640/54 MHz = 11.85 μS, and this operation is repeated for 1024 lines in the vertical direction, so that one frame is 1280 × 1024. The pixel image display is updated. The image is updated in a non-interlaced manner for each line, such as 1st line → 2nd line → ... → 1024th line.

However, as shown in FIG. 11, as the specifications of the liquid crystal display means 76, a waiting time (blank period) WTh for 204 clocks as a typical value in the horizontal direction is provided, and a typical value for 42 lines in the vertical direction is provided. It is stipulated that a waiting time (blank period) WTv is provided. Therefore, the actual screen update cycle considering these standby times WTh and WTv is (204 + 640) × (42 + 1024) / 54 MHz ≈ 16.66 ms in the calculation based on the above-mentioned typical value, so that the frame rate is about 60 Hz. Will be.

The horizontal standby time WTh and the vertical standby time WTv each specify an allowable range for a typical value, and in reality, a value different from the above-mentioned typical value can be selected. However, since the frame rate is 1/60 second, it is necessary to accurately set the horizontal and vertical standby times WTh and WTv so that (WTh + 640) × (WTv + 1024) / 54 MHz = 1/60 second.

Further, the liquid crystal display means 76 does not require the horizontal synchronization signal HS and the vertical synchronization signal VS, while the transmission of the H level data valid signal ENAB is required at the time of transmission of the ODD signal and the EVEN signal. That is, at the timing when a significant signal (ODD / EVEN signal) is transmitted to the first and second transmission lines LVDS1 and LVDS2, the data valid signal ENAB needs to be at the active level (H level).

Therefore, in the present embodiment, based on the specifications of the liquid crystal display means 76 described above, the liquid crystal control board (display control means) 98 and the liquid crystal display means 76 are LVDS in a dual link transmission line having a dot clock (pixel clock) DCK of 54 MHz. They are connected (FIGS. 13 and 18). Further, in the VDP circuit 172 (FIG. 14 and the like) mounted on the liquid crystal control board 98, a horizontal standby time WT and a vertical standby time WTv satisfying the specifications of the liquid crystal display means 76 are provided, and image data (ODD / EVENT) is provided. At the time of output of the signal), the data valid signal ENAB is set to the active level (H level).

That is, as shown in FIG. 12B, the data valid signal ENAB is configured so that only the horizontal display period THd of the horizontal synchronization period TH is the H level. Therefore, the data valid signal ENAB is always at the L level in the vertical synchronization period TV except for the vertical display period TVd (FIG. 12 (c)). The horizontal standby time WTh and the vertical standby time WTv are different from the typical values (WTh is 204, WTv is 42), but the specific design values are based on FIG. Will be described later.

In any case, as shown in FIG. 12A, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal in each operation cycle of the dot clock DCK via the differential signal lines RA2 and RB2. To. The data valid signal ENAB shown in FIGS. 12 (b) and 12 (c) is a demodulated DE signal which is discrete data transmitted by LVDS, and is a continuous discrete DE signal on the time axis. In the differential signal lines RA2 and RB2, as shown in FIG. 12A, the vertical sync signal VS and the horizontal sync signal HS are also repeatedly transmitted following the DE signal (data valid signal ENAB). The liquid crystal display means 76 of the present embodiment does not utilize the synchronization signals VS and HS, and the internal operations related to these synchronization signals HS and VS are not executed.

That is, the horizontal line feed timing of the display line in the liquid crystal display means 76 of the present embodiment is the operation after the falling timing of the data valid signal ENAB and the rising timing of the data valid signal ENAB regardless of the received horizontal synchronization signal HS. The optimum timing for the internal circuit of the liquid crystal display means 76 is defined based on the number of clock CKs (corresponding to the dot clock DCK) (640 in this embodiment) (downward arrow in FIG. 12B).

This point also applies to the vertical line feed timing after displaying an image for one frame, and the liquid crystal display means 76 is based on the continuous number of data valid signals ENAB having a predetermined pulse width (1024 in this embodiment). It is defined at the optimum timing for the internal circuit (down arrow in FIG. 12 (c)) and is not affected by the received vertical sync signal VS. As described above, in the present embodiment, since it is not necessary to transmit the horizontal sync signal HS and the vertical sync signal VS to the liquid crystal display means 76, the pulse widths of the sync signals HS and VS are PWh, PWv, front pouch FPh, FPv, and back pouch. It is not necessary to optimally set BPh, BPv, etc., and the control load on the VDP circuit 172, etc. is greatly reduced.

Further, as the internal operation of the liquid crystal display means 76, the horizontal line feed and the vertical line feed operation are executed at the optimum timing based on the internal configuration of the liquid crystal display means 76, so that the risk of unnatural display operation is eliminated. Incidentally, in the case of a display means that operates based on the horizontal synchronization signal HS or the vertical synchronization signal VS received from the outside, the pulse width of the synchronization signals HS and VS, the front pouch period before and after the synchronization signals HS and VS, and the back pouch. If the period is inappropriate, normal display operation may be impaired.

By the way, in FIG. 12A, the first transmission line LVDS1 using the differential signal lines RA0 to RA3 and RACLK transmits the signal corresponding to the odd-th pixel (ODD signal on the A side), and the difference. The second transmission line LVDS2 using the dynamic signal lines RB0 to RB3 and RBCLK transmits a signal corresponding to the even-th pixel (EVEN signal on the B side). As described above, in the present embodiment, by transmitting the ODD signal and the EVEN signal via the dual link transmission line, the frequency of the dot clock DCK can be substantially reduced to 1/2, and the noise resistance can be reduced by that amount. It is also possible to improve the transmission distance.

On the other hand, the liquid crystal display means 76 has a built-in receiving unit RV for receiving the ODD signal and the EVEN signal transmitted on the dual link transmission line, and outputs an RGB signal from two LVDS signals (ODD signal and EVEN signal). It is restored and the image for one frame (1280 × 1024 pixels) is displayed. Since each of the RGB signals is composed of ⁸ bits, a full ^- color image having a gradation of 28 × ²⁸ × 28 is displayed on the liquid crystal display means 76.

FIG. 13 is a block diagram illustrating the internal configuration of the liquid crystal display means 76 together with the related parts of the VDP circuit 172. As shown in the figure, the ODD signal is transmitted to the LVDS-parallel conversion unit RVa via the first transmission line LVDS1 (A side), and the EVEN signal is transmitted to the LVDS- via the second transmission line LVDS2 (B side). It is transmitted to the parallel conversion unit RVb. The first transmission line LVDS1 includes five differential signal lines RA0 to RA3, RACLK, and the second transmission line LVDS2 includes five differential signal lines RB0 to RB3, RBCLK.

Then, image data R0 to R5 and G0 are dispensed from the differential signal lines RA0 / RB0 out of RGB data having each 8-bit length, and image data G1 to G5 are also ejected from the differential signal lines RA1 / RB1. , B0, B1 are dispensed, and image data B2 to B5, DE signals (that is, data valid signal ENAB), VS signals and HS signals are also dispensed from the differential signal lines RA2 / RB2, and the differential signal line. Image data G6, G7, B6, B7, R6, R7 are also dispensed from RA3 / RB3. As described above, the injected VS signal and HS signal are not used.

Further, the dot clock DCK of the differential signal line RACLK / RBCLK is supplied to the PLL circuit to generate an operating clock CK having the same frequency as the dot clock DCK and having a frequency of 54 MHz. This operation clock CK defines the internal operation of the liquid crystal controller LCD_CTL, and the liquid crystal controller LCD_CTL is image data corresponding to two RGB pixels (8 bits × 3 × 2) adjacent to each other in the left-right direction in the liquid crystal panel LCD. Are collectively processed in synchronization with one operating clock CK.

Therefore, the pixels of the 1280 (= 640 × 2) dots in the horizontal direction complete the processing in the processing time of 11.85 μS (= 640/54 MHz) for 640 operation clocks CK. Since the image data corresponding to one pixel has a length of 1 byte for each of RGB (gradation degree ²⁸ × ²⁸ × ²⁸ ), the image data of all the pixels (1280 dots) constituting one line is the whole. The length is 3 × 1280 bytes.

As shown in FIG. 13, the liquid crystal controller ^LCD_CTL controls ON / OFF of the source driver SDV that drives 1280 source signal lines with drive signals of 28 (= 256) gradations, and 1024 gate signal lines. The gate driver GDV is controlled as appropriate. Specifically, the liquid crystal controller LCD_CTL operates an image update operation with a frame rate of 60 Hz by appropriately operating each part based on the DE signal (data valid signal ENAB) injected from the LVDS transmission line and the operation clock CK. Has been realized.

The pixels of the liquid crystal panel LCD are each composed of basic pixels of three colors of RGB, and the number of basic pixels corresponding to all the pixels (1280 dots) for one line is 3 × 1280, so the source driver SDV is 384. It is configured by arranging 10 driver elements having book output terminals. Image data DATs are sequentially supplied from the liquid crystal controller LCD_CTL to these 10 driver elements, and these are appropriately transferred based on the start signal SP and the transfer clock DCLK. Then, in synchronization with the latch signal LT, the analog-converted drive signal is supplied to the 3840 source signal lines. As described above, the time required to update all the pixels (1280 dots) in one line of the liquid crystal panel LCD is 11.85 μS (= 640/54 MHz).

On the other hand, the liquid crystal controller LCD_CTL updates the gate signal line to be driven by supplying the gate start signal GS and the gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is configured by arranging four driver elements having 256 output terminals.

The update timing of the gate signal line is defined based on the falling timing of the DE signal and the operation clock CK, and the horizontal line feed cycle of the gate signal line is counted by the operation clock CK, and the typical value calculation is 640 + 204 clocks. (See FIG. 11). Further, based on the number of DE signals (1024), the gate signal line to be driven is reset to the initial state, the gate start signal GS is output at the optimum timing, and the output of the gate clock signal GCLK is restarted. The vertical line feed period of the gate signal line is counted by the operation clock CK, and is 42 + 1024 clocks in the typical value calculation (see FIG. 11). However, as described above, in the present embodiment, the liquid crystal display means 76 is operated with a design different from the typical value (see FIG. 19).

Subsequently, returning to FIG. 10, the outline of the frame-side member 132 will be described. The frame-side member 132 is mainly composed of a power supply board 126 and a payout launch control board 128. The power supply board 126 receives AC24V and outputs various DC voltages. In addition to outputting DC5V, DC12V, and DC35V to the payout emission control board 128 and DC12V to the LED connection board 139 under the frame, the power supply relay board 136. DC5V, DC12V, and DC35V are output to the effect interface board 96 via the above. A backup board 147 is connected to the payout launch control board 128, and from the payout launch control board 128 to the main control board 93, in addition to DC5V, DC12V, DC35V received from the power supply board 126, a backup power supply and a power supply abnormality A signal or the like is output via the main control relay board 135.

Further, the payout launch control board 128 is rented to connect a launch drive means 17d constituting the launch means 17, an external terminal board 148 for outputting various information to an external host computer, and an external game ball lending device. In addition to the device connection terminal board 149, a frame relay board 150, a saucer relay board 151, and the like are connected.

The frame relay board 150 relays the connection between the payout motor 32a, the payout counting switch 32b, the front door / inner frame opening switch 152, etc. arranged on the inner frame 6 side and the payout launch control board 128. Further, the saucer relay board 151 relays the connection between the launch connection board 153 on the front door 7 side, the ball jam detection board 154, the frequency display board 155, etc., and the payout launch control board 128. The launch connection board 153 is connected to a variable resistor 35a constituting the launch handle 35, a launch stop switch 35b, a touch sensor 35c, a ball feed solenoid 53c provided in the ball feed unit 53a, and the like.

Further, in addition to the lower speaker 18 on the inner frame 6 side, the lower left LED connection board 156 on the front door 7 side is connected to the LED connection board 139 under the frame. The lower left LED connection board 156 of the frame is connected to the LED boards 302a to 302d constituting the frame lamp 304, the handle LED board 158 arranged on the firing handle 35, the effect button 41, the effect button 41, and the effect button LED inside the effect button LED. The connection board 159, the volume light amount button board 160 to which the volume / light amount adjustment buttons 39, 40 and the like are connected, the upper speaker 25, the side unit relay board 161 connected to the side unit 30, and the like are connected.

Subsequently, the circuit configurations of the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98, and the ROM board 99 constituting the effect control unit 95 will be described in detail with reference to FIGS. 10, 14, and the like.

As shown in FIG. 10, the effect interface board 96 reproduces an audio signal based on an instruction received from a CPU circuit 171 (FIG. 14) mounted on the composite chip 104 of the liquid crystal control board 98 in addition to various input / output buffers. It is provided with an audio processor 101, an audio ROM 103 that stores compressed audio data that is the original data of the reproduced audio signal, a digital amplifier 102 that receives an audio signal output from the audio processor 101, and the like. The voice processor 101 has a built-in WDT circuit that automatically resets the set value of the internal circuit to the default value when the internal circuit operates abnormally, and a voice control register SRG. The voice control register SRG is the composite chip 104. The audio ROM 103 is accessed based on the operation parameters received from the CPU circuit 171 to reproduce a necessary audio signal and output it to the digital amplifier 102.

The various input / output buffers mounted on the effect interface board 96 include an input buffer for receiving a control command CMD and a strobe signal STB from the main control board 93 and transferring them to the composite chip 104 of the liquid crystal control board 98, and a frame LED. An input buffer for receiving a switch signal such as an effect button 41 via the relay board 137 and transferring it to the composite chip 104 of the liquid crystal control board 98, and a serial signal received from the liquid crystal control board 98 via the frame LED relay board 137. Then, it receives a switch signal of a movable body position detection switch or the like via an output buffer for transferring to a driver IC such as an LED board and an LED connection board 134 and transfers it to a composite chip 104 of the liquid crystal control board 98. There are an input buffer, an output buffer for transferring a serial signal received from the liquid crystal control board 98 to a driver IC such as an LED board via the LED connection board 134, and the like.

The liquid crystal control board 98 includes a composite chip (chip) 104 containing a CPU circuit 171 and a VDP circuit 172, and a control ROM (ROM connected to the chip) 105 that stores a control program of the CPU circuit 171. A DRAM (Dynamic Random Access Memory) 106 or the like capable of accessing the data at high speed is mounted, and a large amount of CG data required for effect control is stored in the ROM board 99 connected to the liquid crystal control board 98. CGROM 107 is installed.

The control ROM 105 is positioned in the address space CS0 selected by the chip select signal CS0. Further, the DRAM 106 is positioned in the address space CS5 selected by the chip select signal CS5.

FIG. 14 is a circuit block diagram showing the composite chip 104 mounted on the liquid crystal control board 98, including related circuit elements. As shown in the figure, the composite chip 104 has a CPU circuit 171 that issues a display list DL at predetermined time intervals, and a VDP circuit 172 that generates image data based on the issued display list DL and drives the liquid crystal display means 76. And is built-in. The CPU circuit 171 and the VDP circuit 172 are connected to each other via a CPU IF circuit 173 that relays transmission / reception data to each other.

The CPU circuit 171 multiplies the oscillation output (for example, 100/3 MHz) from the oscillator OSC1 received at the HCLKI terminal of the composite chip 104 by frequency (for example, 8 times) to obtain a CPU operating clock of about 266.7 MHz. Here, the oscillator OSC1 is configured to output a spectrum diffused wave to take measures against EMI (Electromagnetic Interference) to prevent radio interference / electromagnetic interference.

On the other hand, in the VDP circuit 172, the oscillation output (for example, 40 MHz) from the oscillator OSC2 received at the PLLREF terminal of the composite chip 104 is frequency-multiplied as necessary, and then the system clock of the VDP circuit 172 and the display for the display device are displayed. It is used as a clock (dot clock, etc.) and a DDR clock of an external DRAM 106. That is, the output of the oscillator OSC2 functions as a reference clock for the entire VDP circuit 172.

Therefore, in consideration of the importance of this reference clock, the oscillator OSC2 is operated at the same power supply voltage of 3.3V as the VDP circuit 172, and the output enable terminal OE is H level (= 3.3V). , The reference clock is oscillated and output, and when the power supply voltage 3.3V drops below a predetermined level, an unmaskable interrupt (NMI) is configured to occur.

Further, the composite chip 104 is provided with an HBTSL terminal, and a ROM for storing a boot program (initial setting program) executed after the power is turned on (CPU reset) is specified based on the logic level of the HBTSL terminal. .. As shown in the figure, in this embodiment, HBTSL = L is set, and the zero address of the address space CS0 of the CPU circuit 171 is assigned to the control ROM 105.

A control ROM 105 that non-volatileally stores a control program and necessary control data and a work memory (RAM) 174 having a storage capacity of about 2 Mbytes are connected to the CPU IF circuit 173, and are connected to the CPU circuit 171 and VDP, respectively. It is accessible from circuit 172.

The control ROM 105 is positioned in the address space CS0 selected by the chip select signal CS0, and the work memory 174 is positioned in the address space CS6 selected by the chip select signal CS6. The work memory 174 secures a DL buffer BUF that temporarily stores a display list DL in which a series of instruction commands for specifying one frame of the liquid crystal display means 76 are described.

The CPU circuit 171 is a circuit having the same performance as a general-purpose one-chip microcomputer, and has an effect control CPU 181 that comprehensively controls image effects based on the control program of the control ROM 105, and a storage capacity of about 16 kbytes. A serial input having a built-in RAM 182 used as a CPU work area, a DMAC (Direct Memory Access Controller) 183 for realizing data transfer without going through an effect control CPU 181 and a plurality of input ports Si and output ports So. An output port (SIO) 184, a parallel input / output port (PIO) 185 having a plurality of input ports Pi and an output port Po, and a control register (REG) 186 in which set values are set to control the operation of each part, etc. It is equipped with.

The parallel input / output port 185 is connected to an external device (effect interface board 96) via an input / output circuit 187 or the like, and the effect control CPU 181 controls a switch signal such as an effect button 41 via the input / output circuit 187. It is designed to receive command CMD, interrupt signal STB, and the like.

Next, the VDP circuit 172 will be described. The VDP circuit 172 is connected to a CGROM 107 that stores compressed data that is a component of still images and moving images used for image production, an external DRAM 106 having a storage capacity of about 4 Gbit, and a liquid crystal display means 76. There is. In the present embodiment, the DRAM 106 is composed of DDR3 (Double-Data-Rate3 SDRAM), and the CGROM 107 is composed of a flash SSD (solid state drive) composed of a NAND flash memory.

As shown in FIG. 14, the VDP circuit 172 has a control register group 201 in which various operation parameters defining the operation of the VDP (Video Display Processor) can be set by the effect control CPU 181 and an image to be displayed on the liquid crystal display means 76. Regarding the built-in VRAM (video RAM) 202 of about 48 Mbytes used when generating data, the data transfer circuit 203 that executes data transmission / reception between each part inside the chip and data transmission / reception with the outside of the chip, and the built-in VRAM 202, Source and An index table IDXTBL that can specify the address information of Destiny, a preloader 204 that can execute a preload operation that READ-accesses the CGROM 107 prior to the drawing operation, and a graphic that decodes (decodes / decompresses / expands) the compressed data read from the CGROM 107. Operation of the drawing circuit 206 and the drawing circuit 206 that generate the image data for one frame of the liquid crystal display means 76 by appropriately combining the decoding (GDEC) 205 with the still image data and the moving image data after decoding (decompression). As a part, a plurality of systems that can read the image data of the geometry engine 207 that generates a stereoscopic image by appropriate coordinate conversion and the frame buffer FBa generated by the drawing circuit 206 and execute appropriate image processing in parallel, for example. Outputs by the output selection unit 209 and the output selection unit 209 that appropriately select the outputs of the display circuits 208A to 208C of the three systems (A / B / C) and the display circuits 208A to 208C of the three systems (A / B / C). The LVDS unit 210 that converts the image data to be converted into an LVDS signal, the SMC unit 211 that can transmit and receive serial data, the CPUIF unit 212 that relays data transmission and reception with the CPUIF circuit 173, and the CG bus IF that relays data reception from CGROM107. It includes a DRAMIF unit 214 that relays data transmission / reception from the external DRAM 106, a VRAMIF unit 215 that relays data transmission / reception from the built-in VRAM202, and an audio circuit SND.

FIG. 15 shows the relationship between the CPU IF unit 212, the CG bus IF unit 213, the DRAM IF unit 214 and the VRAM IF unit 215, and the control register group 201, the CGROM 107, the DRAM 106 and the built-in VRAM 202. As shown in the figure, the CG data acquired from the CGROM 107 is transferred to the preload area of the external DRAM 106 as preload data, for example, via the data transfer circuit 203 and the DRAM IF unit 214. Note that this preload operation is not essential, and the data transfer destination is not limited to the external DRAM 106, and may be the built-in VRAM 202. For example, when the preload operation is not executed, the CG data is transferred to the built-in VRAM 202 via the data transfer circuit 203 and the VRAM IF unit 215.

By the way, in the built-in VRAM 202, a decompression area of compressed data read from CGROM 107, a frame buffer area for storing image data specifying each ARGB information (32 bits = 8 × 4) of W × H display pixels of the display device, And a Z buffer area for storing the depth information of each display pixel is required. In the ARGB information, A means 8-bit α-plane data, and RGB means 8-bit data of the three primary colors.

Here, each of the above-mentioned areas of the built-in VRAM 202 is indirectly accessed by the effect control CPU 181 based on various instruction commands (textures, sprites, etc.) described in the display list DL. It is complicated to specify the Display address and Source address of the built-in VRAM 202 one by one. Therefore, in the present embodiment, in the initial processing after the CPU reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as an index space) required for drawing operation is secured, and an index number is assigned to each index space. This enables access based on the index number.

Specifically, after the CPU is reset, the built-in VRAM 202 is roughly divided into three types of memory areas, and a required number of index spaces are secured in each memory area. Then, by constructing the index table IDXTBL (see FIG. 16A) that stores the index space and the index number in association with each other, the subsequent operation based on the index number is realized.

It is also necessary to (1) add this index space after the initial processing, and conversely (2) open it. Therefore, a flag area FG capable of determining whether or not the addition / release processing is possible and whether or not the addition / release processing is actually completed during the operation of the addition / release effect control CPU 181. Is provided in the index table IDXTBL. The built-in VRAM 202 is roughly classified into three types of memory areas, two AAC areas (a1 and a2), a page area (b), and an arbitrary area (c) described below, and these three types of memory areas (a1). , A2) Corresponding to (b) and (c), the index table IDXTBL is divided into three categories (FIG. 16 (a)). As shown in the figure, in this embodiment, the first AAC region (a1) and the second AAC region (a2) are secured as the AAC region (a), but the region is not limited to this, and one of them is used. It may be just. In the following description, when the first and second AAC regions (a1 and a2) are collectively referred to, they may be referred to as an AAC region (a).

In the case of the present embodiment, the built-in VRAM 202 has (a) an index space and an AAC area in which the index number is automatically assigned by internal processing and has a memory cache function, and (b) a two-dimensional space of, for example, 4096 bits × 128 lines. The unit space is configured to be distinguishable into a page area where an index space can be secured in the range of integral multiples thereof, and (c) an arbitrary area where the start address (space start address) STx and the horizontal size Hx can be arbitrarily set. (See FIG. 16 (b)). However, in order to facilitate the internal operation of the VDP circuit 172, the space head address STx of the index space arbitrarily set in the arbitrary area (c) has a lower 11 bits of 0 and a predetermined bit (2048 bits = 256 bytes). Must be a unit.

Then, after the CPU reset, the maximum value of the address space required for each and the area start address (lower 11 bits = 0) are defined, and the AAC area (a1), the second AAC area (a2), and the page area ( b) is secured, and the remaining memory area becomes an arbitrary area (c). In order to facilitate the internal operation of the VDP circuit 172, the maximum value of the address space in the AAC area is specified in units of 2048 bits, and the maximum value of the address space in the page area is an integral multiple of the unit space of the above-mentioned 4096 bits × 128 lines. Will be done.

Next, a required number of index spaces are set in each of the regions (a1, a2), (b), and (c) secured in this way. When the arbitrary region (c) is used, the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 256 bits in order to facilitate the internal operation of the VDP circuit 172. The vertical size is a fixed value (for example, 2048 lines).

In any case, since the index space and the index number are automatically assigned to the first and second AAC regions (a1 and a2) by the VDP circuit 172, for example, the decoding destination is obtained by the SETINDEX command of the texture setting command. Is specified in the AAC area (a), and the TXLOAD (texture load) command for reading CG data from the CGROM107 only needs to specify the source address of the CGROM107 and the horizontal / vertical size after expansion (decoding). Become. Therefore, in the present embodiment, the decoding destination of a still image (texture) such as a character that temporarily appears at the time of a preview effect or an I-stream moving image is set to the AAC region (a).

Since the memory cache function is added to each of the AAC areas (a), for example, when the same texture of the CGROM 107 is read into the AAC area (a) multiple times, the AAC area is read from the second time onward. The decoded data cached in (a) can be utilized, and extra READ access and decoding processing can be suppressed. However, when the AAC region (a) is used up, old data is automatically destroyed. Therefore, in the present embodiment, when the AAC region (a) is used, the first AAC region (a1) is used in principle. It is decided to use it, and only a specific texture to be used repeatedly is acquired in the second AAC region (a2).

As the texture to be used repeatedly, for example, a character that repeatedly appears at the time of a predetermined advance notice effect, a background image when the background screen is constructed from a still image, and the like can be exemplified. In such a case, the decoding destination is set in the second AAC area (a2) by the SETINDEX command of the texture setting system command, and the texture such as a character or the background image is decoded in the second AAC area (a2) by the TXLOAD command. After that, the decoding result is protected by not using the second AAC region (a2).

After that, if the decoding destination is specified in the second AAC area (a2) by the SETINDEX command and the same TXLOAD command for reacquiring the acquired texture is executed, the acquired texture will be cache-hit. The time required for READ access to the CGROM 107 and the decoding process can be deleted. Such a cache hit function is also exhibited in the preload data pre-read in the preload area, but the cache hit preload data in the preload area is the compressed data before decoding, whereas the cache hit is performed in the AAC area. It is significant that is the expanded data after decoding.

By the way, texture is a concept that generally refers to the texture, texture, etc. of the surface of an object, but in the present embodiment, sprite image data constituting a still image, image data constituting one frame of moving images, triangles, and the like. It is used as a concept that includes not only image data to be pasted on a drawing primitive (primitive) such as a square, but also image data after decoding. Then, when copying the image data inside the built-in VRAM 202 (hereinafter referred to as "move" for convenience), the PRITE command is executed after setting the image data of the move source as a texture by the SETINDEX command of the texture setting command. Will be executed.

By executing the PRITE command, the source image data of the movement source is formally drawn in the virtual drawing space shown in FIG. 16 (c), but the drawing area in the virtual drawing space actually drawn on the display device. If the correspondence between the image and the index space that becomes the frame buffer is set in advance by the environment setting command (SETDAVR, SETDAVF) or the texture setting command (SETINDEX), for example, by drawing in the virtual drawing space by the PRITE command. , The source image data of the movement source is drawn in the predetermined index space (frame buffer) (see FIG. 16 (c)).

In any case, in the present embodiment, the built-in VRAM 202 is roughly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces can be secured in each area. , Each index space is specified by an independent index number for each region (a) (b) (c). The index number is, for example, 1 byte long, and the page area (b) and the arbitrary area (c) (excluding the AAC area (a) automatically assigned by the internal circuit) are controlled in the range of 0 to 255. The CPU 181 can freely assign an index number.

Therefore, in the present embodiment, as shown in FIG. 16A, a pair of frame buffers FBa are secured in the arbitrary area (c) for the liquid crystal display means 76, and the index numbers 255 and 254 are used in both of the double buffer structures. Is given. That is, as the frame buffer FBa for the liquid crystal display means 76, the index space 255 and the index space 254 used by switching in a toggle manner are secured. Although not particularly limited, the index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of horizontal pixels of the liquid crystal display means 76. Since each pixel is specified by ARGB information 32 bits, the horizontal size 1280 means 32 × 1280 = 40960 bits (a multiple of 256 bits).

The frame buffer FBa is secured in the arbitrary area (c) by setting the arbitrary area (c) to an arbitrary horizontal size as a multiple of 32 bytes (= 256 bits = 8 pixels). This is because if the number of horizontal pixels of the liquid crystal display means 76 is matched as described above, the reserved area is not wasted. On the other hand, in the page area (b), only a horizontal / vertical size that is an integral multiple of the unit space of 128 pixels × 128 lines can be set. However, the vertical size of the two-dimensional index space secured in the arbitrary region (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area of horizontal size 1280 × vertical size 1024 is an effective data area for the liquid crystal display means 76.

Further, in the present embodiment, when an additional index space (memory area) is secured in the arbitrary area (c) in which the frame buffer FBa is secured, an index number starting from 0 is assigned. Although not limited in any way, in the present embodiment, as a work area for a notice effect, an effect image composed of a character or other still images is made to appear on a part of the display screen in an appropriate rotation posture as needed. The index space (0) is secured in the arbitrary area (c).

However, the use of the work area is not essential, and instead of the arbitrary area (c), an index space as a work area may be secured in the page area (b). If the page area (b) is used, an index space having an index space that is a multiple of a square unit space having a horizontal size of 128 (= 4096 bits) and a vertical size of 128 can be secured, which is suitable for handling a small production image.

By the way, in the present embodiment, the image effect is realized only by the moving image including the background image. In particular, during variable production, a large number (usually 10 or more) of moving images are drawn at the same time. All of these videos are stored in the CGROM 107 in a compressed state as a series of video frames, but an I-stream video composed of only I-frames and an IP stream video composed of I-frames and P-frames. It is classified into. Here, the I frame (Intra coded frame) means a frame that compresses the input image as it is, independently of other screens. On the other hand, the P frame (Predictive coded frame) means a frame for performing forward predictive coding, and an I frame or a P frame located in the past in time is required.

Therefore, in the present embodiment, the IP stream moving image is developed not in the AAC area (a) where there is a concern about the destruction of old data, but in the page area (b). That is, a large number of index spaces (IDX0 to IDXN) are secured in the page area (b) where an index space having a multiple dimension of horizontal size 128 × vertical size 128 can be secured, and a series of video frames correspond to each video MVi. The same index space IDXi is always used for decoding. That is, the moving image MV1 is expanded in the index space IDX1, the moving image MV2 is expanded in the index space IDX2, and similarly, the moving image MVi is configured to be expanded in the index space IDXi.

More specifically, the moving image MVi will be described more specifically. After specifying in advance by the SETINDEX command that "the decoding destination of the IP stream moving image MVi is the index space (i) of the index number i in the page area (b)", The TXLOAD command for acquiring one frame of the IP stream video MVi video is executed.

Then, one video frame (any of a series of video frames) on the CGROM 107 specified by the TXLOAD command is first acquired in the AAC area (a), and then automatically activated by the graphics decoder (GDEC) 205. One acquired moving image frame is decoded and expanded in the index space (i) of the page area (b).

On the other hand, in the present embodiment, the I-stream moving image is treated the same as the still image, and the SETINDEX command is used to specify that "the decoding destination of the I-stream moving image MVj is the first AAC area (a1)". Execute the TXLOAD command. As a result, the moving image frame is acquired in the first AAC area (a1), and then the graphics decoder 205 that is automatically activated develops the decoded data in the first ACC area (a1). As described above, since the index space of the AAC area (a) is automatically generated, it is not necessary to specify the index number. The expanded volume required for the index space, that is, the horizontal size and vertical size of the decoded texture (video frame), can be determined by the TXLOAD command regardless of whether the expanded destination is the AAC area (a) or the page area (b). Be identified.

By the way, the IP stream moving image MVi and the I stream moving image MVj are generally composed of N moving image frames (I frame and P frame). Therefore, in the TXLOAD command, for example, the source address of the CGROM 107 in which the kth (1 ≦ k ≦ N) moving image frame is stored, the horizontal / vertical size after expansion, and the like are specified. Although not limited in any way, in the present embodiment in which still images are scarcely used, most of the address space 48 Mbytes (about 30 Mbytes) of the built-in VRAM 202 is allocated to the page area (b). In the present embodiment in which the still image is hardly used, only the first AAC region (a1) is secured as the AAC region, the second AAC region (a2) is not secured, and the cache hit function of the above-mentioned AAC region is secured. Do not utilize.

In addition, in order to speed up the decoding process of the compressed moving image data, it is conceivable to provide a dedicated GDEC (graphics decoder) circuit. Then, if a dedicated GDEC circuit is built in the VDP circuit 172, it is sufficient to indicate the start address of the video compressed data to the GDEC circuit in the decoding process of the compressed video data composed of N compressed video frames. It is no longer necessary to specify the start address for each of the N compressed video frames.

However, if a plurality of such dedicated GDEC circuits are built in for each compression algorithm, the internal configuration of the VDP circuit 172 becomes further complicated. Therefore, in the present embodiment, software GDEC is used, and decoding processing is realized for data such as IP stream moving image, I stream moving image, still image, and other α values by software processing corresponding to each compression algorithm. The processing time difference between the hardware processing and the software processing does not matter so much, and the processing time becomes a problem mainly in the access (READ) time from the CGROM 107.

The explanation will be continued by returning to FIG. The data transfer circuit 203 uses a resource (storage medium) inside the VDP circuit and an external storage medium as a transfer source port or a transfer destination port, and executes a data transfer operation in a DMA (Direct Memory Access) manner between them. Is. FIG. 17 is a block diagram showing the internal configuration of the data transfer circuit 203 together with the related circuit configuration.

As shown in FIG. 17, the data transfer circuit 203 is configured to transmit / receive data to / from the CGROM 107, the DRAM 106, and the built-in VRAM 202 via the integrated connection bus ICM having a router function. The CGROM 107 and the DRAM 106 are accessed via the CG bus IF unit 213 and the DMAMIF unit 214.

On the other hand, the CPU circuit 171 issues a display list DL to the drawing circuit 206 and the preloader 204 via the transfer port register TR_PORT built in the data transfer circuit 203. The CPU circuit 171 and the data transfer circuit 203 are bidirectionally connected, but when the display list DL is issued, the transfer port register TR_PORT functions as a data write port that accepts one unit of data constituting the display list DL. do. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus control unit 203d.

As shown in the figure, the effect control CPU 181 can access the transfer port register TR_PORT directly through the CPU IF unit 212, while the DMAC circuit 183 directly accesses the transfer port register TR_PORT when the DMAC circuit 183 is used. Will be done. A series of instruction commands written in the transfer port register TR_PORT (that is, instruction command sequences constituting the display list DL) are controlled by a CPU bus having a built-in FIFO buffer having a FIFO structure (32 bits x 130 stages) in units of 32 bits. It is configured to be automatically stored in the unit 203d.

Further, the data transfer circuit 203 executes a data transmission / reception operation on a transmission path of 3 channels ChA to ChC, and has a FIFO structure (64 bit × N stage) ChA control circuit 203a (N = 130 stages). ), A ChB control circuit 203b (N = 1026 stages), and a ChC control circuit 203c (N = 130 stages).

The instruction command sequence (display list DL) stored in the CPU bus control unit 203d is the drawing circuit 206 or the preloader 204 based on the set value in the data transfer register RGij (a type of various control registers 201) by the effect control CPU 181. Will be transferred to. As shown by the arrow, the display list DL is transferred from the CPU bus control unit 203d to the drawing circuit 206 via the FIFO buffer of the ChB control circuit 203b, and transferred to the preloader 204 via the FIFO buffer of the ChC control circuit 203c. It is configured to.

In this embodiment, the ChB control circuit 203b and the ChC control circuit 203c are specialized in the transfer operation of the display list DL, and the data stored in the FIFO buffer of the CPU bus control unit 203d is the ChB control circuit 203b. It is transferred to the drawing circuit 206 or the display list analyzer (Display List Analyzer) of the preloader 204 as a part of the display list DL via the FIFO buffer of the ChC control circuit 203c.

Then, the drawing circuit 206 starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 204 executes a necessary preload operation based on the transferred display list DL. By the preload operation, the CG data of the CGROM 107 is pre-read to the preload area secured in the DRAM 106, and the display list DL (hereinafter referred to as the rewrite list DL') in which the source address of the texture is changed is secured in the DRAM 106 with respect to the TXLOAD command and the like. It is stored in the created DL buffer area BUF'.

On the other hand, the ChA control circuit 203a and the connection bus access arbiter circuit 203e function for data transfer between storage media such as the CGROM 107, DRAM 106, and built-in VRAM 202. Further, the IDXTBL access arbiter circuit 203f functions when the built-in VRAM 202, which requires the address information of the index table IDXTBL, is accessed. Specifically, the ChA control circuit 203a may, for example, (a) transfer the compressed data of the CGROM 107 to the built-in VRAM 202, or (b) preload (look ahead) the compressed data of the CGROM 107 and transfer the compressed data to the external DRAM 106. , (C) Functions when transferring the look-ahead data in the preload area to the built-in VRAM 202.

Here, the ChA control circuit 203a is configured to be operable in parallel with the ChB control circuit 203b and the ChC control circuit 203c, and the above-mentioned operations (a) to (c) are the display list DL issuing operation and the operation. It can be executed in parallel with the transfer operation of the rewrite list DL'. Further, the ChB control circuit 203b and the ChC control circuit 203c can also be executed at the same time. However, since the transfer port register TR_PORT is single, when one (203b / 203c) is using the transfer port register TR_PORT, the other (203c / 203b) cannot access the transfer port register TR_PORT. Can not.

When the ChA control circuit 203a is operating, the connection bus access arbitration circuit 203e arbitrates data transmission with each storage element (CGROM107, DRAM106) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 203f arbitrates data communication with the built-in VRAM 202 by controlling the ChA control circuit 203a based on the index table IDXTBL. In the case of the present embodiment in which the preloader 204 functions, the rewrite list DL'stored in the DL buffer area BUF' of the DRAM 106 is connected to the drawing circuit 206 via the connection bus access arbiter circuit 203e and the ChB control circuit 203b. Will be transferred.

As described above, the data transfer circuit 203 of the present embodiment has a data transfer source arbitrarily selected from various storage resources (Resource) and a data transfer destination arbitrarily selected from various storage resources (Resource). High-speed data transfer is realized between them. The storage resource in which the data transfer circuit 203 functions includes not only the built-in VRAM 202 but also an external device via the CPU IF unit 212, the CG bus IF unit 213, and the DRAM IF unit 214.

Then, the amount of data transferred to an external device on which the ChA control circuit 203a functions, such as the amount of data to be acquired from the CGROM 107 at one time (memory sequential READ), is the amount of data transferred to the display on which the ChB control circuit 203b or ChC control circuit 203c functions. It is enormous as compared with the case of the list DL, and the amount of data transfer differs greatly from each other.

Here, it is conceivable to configure the unit data amount and the total transfer data amount to be finely set for these various data transfers, but this complicates the control operation inside the VDP and hinders the smooth transfer operation. To. Therefore, in the present embodiment, a high-speed and smooth data transfer operation is realized by uniquely defining the minimum data amount Dmin for data transfer and limiting the total transfer data amount to be an integral multiple of the minimum data amount DTmin. is doing. Although not particularly limited, in the data transfer circuit 203 of the present embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total transfer data amount is limited to an integral multiple of this.

Therefore, the instruction command sequence of the display list DL stored in the FIFO buffer of the CPU bus control unit 203d every 32 bits is transferred to the ChB control circuit 203b or the ChC control circuit 203b at the timing when the total amount reaches the minimum data amount Dmin. , Accumulated in each FIFO buffer.

The display list DL is composed of a series of instruction commands, but in the present embodiment, the display list DL corresponds to a write unit (32 bits) of the transfer port register TR_PORT, and the command length of the display list DL is an integer N times (32 bits). It consists only of the instruction command of N> 0). Therefore, the drawing circuit 206 and the preloader 204 that receive the instruction command of the display list DL via the data transfer circuit 203 can start the command analysis process (DL analyze) quickly and smoothly. It should be noted that the command length of 32 bits, which is an integer N times, does not mean that all of them are significant bits, but also includes an involuntary bit (Don't care bit), which means a 32-bit integer N times.

Next, the preloader 204 will be described. The preloader 204 is a circuit that interprets the display list DL transferred from the data transfer circuit 203 (ChC control circuit 203b) and transfers the CG data on the CGROM 107 referenced by the TXLOAD command to the preload area of the DRAM 106 in advance. be. Further, the preloader 204 stores the rewrite list DL'in which the reference destination of the CG data is rewritten to the address after the transfer in the DL buffer BUF' of the DRAM 106 with respect to this TXLOAD command. The DL buffer BUF'and the preload area are reserved in advance at the time of initial processing after the CPU reset.

Then, the rewrite list DL'is applied to the display list analyzer (DL Analyzer) of the drawing circuit 206 via the connection bus access arbiter circuit 203e and the ChB control circuit 203b of the data transfer circuit 203 at the start of the drawing operation of the drawing circuit 206. Will be transferred. Then, the drawing circuit 206 executes the drawing operation based on the rewrite list DL'. Therefore, based on the TCLOAD command or the like, the CG data that should be originally acquired from the CGROM 107 is acquired from the preload area of the DRAM 106 as the preload data that is pre-read in the preload area. In this case, the preload data can be used repeatedly unless it is overwritten and erased, and the preload data that has cache hits in the preload area is repeatedly reused.

In the present embodiment, since the preload area is set in the external DRAM 106 having a sufficient storage capacity, the above cache hit function functions effectively. Further, since the storage capacity of the external DRAM 106 is large, for example, multiple preloads that preload CG data for a plurality of frames at once are possible. That is, with respect to the operation period of the preloader 204, the operation period of a series of preload operations including the look-ahead operation of CG data is appropriately set within a range of an integral multiple of the operation cycle δ at the time of intermittent operation of the VDP circuit 172. Multiple preloads are realized.

However, in the following description, for convenience, a configuration without multiple preloads will be described. Therefore, the preloader 204 of the present embodiment completes the preload operation for one frame in one operation cycle (δ). In the present embodiment, the operation cycle δ during the intermittent operation of the VDP circuit 172 is 1/30 second, which is twice the period of the vertical synchronization signal of the liquid crystal display means 76.

Next, the drawing circuit 206 sequentially analyzes the instruction command sequence of the display list DL and the rewriting list DL'transferred via the data transfer circuit 203, and cooperates with the graphics decoder 205, the geometry engine 207, and the like. Then, it is a circuit that draws an image for one frame of the liquid crystal display means 76 in the frame buffer formed in the VRAM 202.

As described above, when the preloader 204 is made to function, the reference destination of the CG data in the rewrite list DL'is not the CGROM 107 but the preload area set in the DRAM 106. Therefore, the sequential access to the CG data generated during the execution of drawing by the drawing circuit 206 can be quickly executed, and even a high-resolution moving image with intense movement can be drawn without any problem. That is, according to the present embodiment, it is possible to perform complicated and advanced image production while utilizing an inexpensive SATA module as the CGROM 107.

By the way, regardless of whether or not the preloader 204 is made to function, even if data garbled occurs during transfer of the display list DL or the rewrite list DL', the drawing circuit 206 cannot detect this. In addition, the drawing circuit 206 may freeze due to the influence of noise or the like, and the READ / WRITE access of the built-in VRAM 202 may stop abnormally. Therefore, in the present embodiment, when the drawing circuit 206 detects an irrational instruction command (bit arrangement that cannot be analyzed), or when there is no READ / WRITE access to the built-in VRAM 202 for a certain period of time, a drawing abnormality interrupt is generated. It is configured to generate (drawing error interrupt is enabled).

Next, as described with respect to FIG. 16, the frame buffer FB secured in the arbitrary area (c) of the VRAM 202 is a double buffer divided into a drawing area and a reading area, and the two areas are alternately switched between uses. To use. Further, in the present embodiment, since one liquid crystal display means 76 is connected, as shown in FIG. 16, one section of the frame buffer FBa is secured. Therefore, the drawing circuit 206 draws image data for one frame in the drawing area (writing area) of the frame buffer FBa for the liquid crystal display means 76.

The display circuits 208A to 208C are circuits that read out the image data of the frame buffers FBa to FBc, perform final image processing, and output the image data (see FIG. 18). The final image processing includes, for example, a scaler scaling process for enlarging / reducing the image, a subtle color correction process, and a dithering process for minimizing the quantization error of the entire image. Then, the digital RGB signal (24 bits in total) that has undergone these image processing is usually output together with the horizontal sync signal HS, the vertical sync signal VS, and the like.

As shown in FIG. 18, in the present embodiment, three display circuits A / B / C for executing the above operations in parallel are provided, and each display circuits 208A to 208C have frame buffers corresponding to the respective display circuits 208A to 208C. The image data of FBa / FBb / FBc is read out, and the above final image processing is executed. However, since there is only one display device in this embodiment, the frame buffers FBb and FBc are not secured, and the display circuits 208B and 208C do not function.

Here, when the specifications of the liquid crystal display means 76 are confirmed, the liquid crystal display means 76 transmits odd pixels (ODD) and even pixels (EVEN) adjacent to each other in the left-right direction through separate LVDS (Low Voltage Differential Signaling) transmission paths. It needs to be received by the receiving unit RV (RVa, RVb). Further, the frequency of the dot clock DCK of the liquid crystal display means 76 needs to be about 40 to 70 MHz (typical value is 54 MHz), and is horizontal / so that (WTh + 640) × (WTv + 1024) / 54 MHz ≈ 1/60 second. It is necessary to set the standby time WTh / WTv in the vertical direction. Further, at the timing of outputting the image data (ODD / EVEN signal) to the liquid crystal display means 76, it is necessary to output the active level data valid signal ENAB.

Therefore, the display circuit 208A needs to output a signal satisfying all the above specifications. 19 (a) to 19 (e) show various signals output from the display circuit 208A. First, it is necessary to determine the frequency of the dot clock DCK. In the present embodiment, the liquid crystal display means 76 is operated by the operating clock CK having a typical value of 54 MHz. The dot clock DCK of the above is set to 108 MHz (= 54 × 2).

It is substantially 108 MHz because two pixels adjacent to the left and right are processed at once in synchronization with the 54 MHz operating clock CK in the display panel LCD (see FIG. 19 (f)) having 1280 dots horizontally and 1024 lines vertically. This is because it is equivalent to operating with the dot clock DCK of.

The various operating parameters that define the operation of the display circuit 208A are defined based on the dot clock DCK having a frequency of 108 MHz. First, it is necessary to set the standby time WTh / WTv in the horizontal / vertical direction so that (WTh + 640) × (WTv + 1024) / 54 MHz ≈ 1/60 seconds. , (WTh + 1280) × (WTv + 1024) / 108 MHz ≈ 1/60 second must be satisfied.

Further, it is necessary to consider the allowable range in the specifications of the liquid crystal display means 76 for the standby time WTh / WTv in the horizontal / vertical direction. Therefore, in the present embodiment, the horizontal standby time WT is counted by the dot clock DCK of 108 MHz to be 382 clocks, and the vertical standby time WTv is 59 lines. Therefore, the time required to update the image of one frame is (382 + 1280) × (59 + 1024) / 108 MHz = 16.666 mS, and the frame rate is 1/60 second.

Corresponding to this setting, the data valid signal ENAB has a waiting time WTh (= 382/108 MHz) corresponding to the 382 clock in the image update operation of each line at the L level, and then an active section corresponding to the 1280 clock. (= 1280/108 MHz) is the active (H) level (FIG. 19 (c)). As shown in FIGS. 19 (d) and 19 (e), in the active section of the data valid signal ENAB, the image update operation is completed in a predetermined time (11.85 μS = 1280/108 MHz) for the pixels of one line of 1280 dots. Image data is output as shown. That is, 1280 pixel data (Pixel Data) are output in synchronization with the 1280 dot clock DCK. Since the liquid crystal display means 76 displays a full ^- color image having a gradation degree of 28 × 28 × 28, the pixel data of one pixel has a length of ³ × ⁸ bits.

By the way, in the present embodiment, although not required by the liquid crystal display means 76, the vertical synchronization signal VS and the horizontal synchronization signal HS are output. The vertical synchronization signal VS is output within the vertical standby time WTv, and the horizontal synchronization signal HS is output within the horizontal standby time WT. Note that FIGS. 19 (a) and 19 (b) show each operation cycle for convenience of understanding. Further, in FIG. 19 (f), circles are shown at the upper left and lower right vertices of the rectangular frame specified by TH × TV (= 1083 × 1662 clock), and “start of display operation” and “display operation” are shown, respectively. Although it is described as "end of", this circle mark means "start of V blank" which is started every 1/60 second. Since the 1083 × 1662 clock that defines the display operation matches 1/60 second, the elapsed time from the “start of the display operation” to the “end of the display operation” is 1/60 second.

Returning to FIG. 18, the output selection unit 209 of the present embodiment divides the output signal of the display circuit 208A into dual links that divide the 108 MHz dot clock DCK by two, and the LVDS unit 210a and the output signal unit 210a, respectively. It is transmitted to the LVDS unit 210b (see FIGS. 18 and 13). Then, the LVDS units 210a and 210b convert the image data (a total of 24 bits of digital RGB signals) into the first and second LVDS signals, and add a pair for transmitting the clock signal (54 MHz = 108/2) to the first and second LVDS signals. All five pairs of differential signals LVDS1 and LVDS2 are output to the liquid crystal display means 76 via two paths (see FIGS. 18 and 12).

As described above, in the liquid crystal display means 76, the ODD signal for one pixel and the EVEN signal for one adjacent pixel are processed at the same timing, so that the actual frequency of the dot clock DCK is the display circuit. It matches the 108 MHz dot clock DCK output by the 208A.

By the way, in the case of the present embodiment, the display circuits 208A to 208C are provided with underrun counters URCNTa to URCNTc for counting underrun abnormalities in which display data is not generated in time for the display timing (see FIG. 18). .. The counter values of the underrun counters URCNTa to URCNTc are configured to be automatically added for each VBLNK when an underrun abnormality occurs.

Next, the SMC (Serial Management Controller) unit 211 is a composite controller having a built-in LED controller and Motor controller. Then, the LED / Motor driver (driver IC with a built-in shift register) mounted on the external board outputs the LED drive signal and the motor drive signal in synchronization with the clock signal, while outputting the latch pulse at an appropriate timing. It is configured to be possible.

Regarding the internal circuit of the VDP circuit 172 and its operation described above, the operation content to be executed by the internal circuit is defined by the operation parameter (set value) set in the control register group 201 by the effect control CPU 181 and is the execution state of the VDP circuit 172. Can be specified by READ the operation status value of the control register group 201. The control register group 201 means a large number of VDP registers RGij mapped in an address space (0 to FFFFFF) of about 1 Mbyte on the memory map of the effect control CPU 181. The effect control CPU 181 of the CPU circuit 171 is the CPU IF unit 212. The operation parameter WRITE (setting) operation and the operation status value READ operation are executed via (see FIG. 15).

As shown in FIG. 15, the control register group 201 (VDP register RGij) has a "system control register" in which initial setting values related to system operations such as interrupt operation are written, and the built-in VRAM 202 has an AAC area (a) and a page area (a). b) The "index table register" for determining the index table IDXTBL and constructing or changing the index table IDXTBL, and the setting values related to the data transfer processing by the data transfer circuit 203 between the effect control CPU 181 and the internal circuit of the VDP circuit 172 are set. The "data transfer register" to be written, the "GDEC register" to specify the execution status of the graphics decoder 205, the "drawing register" to which the instruction command and the setting values related to the drawing circuit 206 are written, and the operation of the preloader 204. A "preloader register" in which setting values are written, a "display register" in which setting values related to the operation of the display circuit 208 are written, and a "LED control register" in which setting values related to the LED controller (SMC unit 211) are written. , A "motor control register" in which the setting value relating to the Motor controller (SMC unit 211) is written, and a "voice control register SRG" in which the setting value relating to the voice circuit SND is written. However, the voice circuit SND is not utilized in this embodiment.

In any case, the effect control CPU 181 controls the internal operation of the VDP circuit 172 by writing an appropriate set value to the predetermined VDP register RGij. Specifically, the effect control CPU 181 realizes a predetermined image effect based on the display list DL updated at an appropriate time interval and the set value in the predetermined VDP register RGij. In this embodiment, since the effect control CPU 181 is in charge of the effect control CPU 181 including the lamp effect and the motor effect, the VDP register RGij also includes the LED control register and the motor control register.

Subsequently, the details of the wiring pattern and the like of the liquid crystal control board 98 and the liquid crystal interface board 97 constituting the effect control unit 95 will be described. First, the liquid crystal control substrate 98 will be described.

The liquid crystal control board 98 has a plurality of wiring layers on the board body 190 (see FIG. 8), specifically, a first wiring layer La1 on the front surface (first surface) 98a side and a first wiring layer La1 on the back surface (second surface) 98b side. A total of 6 layers of 1st to 6th wiring layers La1 to La6 (FIGS. 20 to 25) including 6 wiring layers La6 and 2nd to 5th wiring layers La2 to La5 arranged between them are provided. There is. The second wiring layer La2 (FIG. 21) is a solid wiring layer connected to the ground, and the fifth wiring layer La5 (FIG. 24) is a solid wiring layer connected to the power supply. Further, the substrate main body 190 of the liquid crystal control substrate 98 is provided with a large number of vias (interlayer conduction portions) in the plate thickness direction, and the plurality of wiring layers La1 to La6 are provided with each other via these vias (interlayer conduction portions). It is conducting. The via used in this embodiment is a through-hole type via in which a through hole is plated, and penetrates from the front surface (first surface) 98a to the back surface (second surface) 98b of the substrate main body 190.

In the following description, regarding the in-plane directions and orientations of the wiring layers La1 to La6, as shown in the coordinate system in FIGS. 20 to 25, the left-right direction in the figure is the X direction, and the vertical direction is the Y direction. The directions are right / left, respectively, + X / -X direction (side), and upward / downward, respectively, + Y / -Y direction (side). Further, the diagonal direction is also expressed as diagonal + XY direction and diagonal-XY direction. As is clear from FIGS. 7 and 8, when the liquid crystal control board 98 is mounted on the gaming machine main body 1, the + X direction of the liquid crystal control board 98 faces upward, and the + Y direction also faces right toward the gaming machine main body 1. (To the left when viewed from the rear).

As shown in FIG. 20, in the first wiring layer (instep wiring layer) La1 on the surface 98a side, a composite chip arrangement region (first arrangement region) 191 in which a composite chip (first electronic component) 104 is arranged is used. A control ROM arrangement area (second arrangement area) 192 in which the control ROM (second electronic component, specific electronic component) 105 is arranged is provided. The composite chip arrangement region 191 is a substantially square shape corresponding to the shape of the composite chip 104, and is arranged near the central portion of the surface 98a of the liquid crystal control substrate 98. In the composite chip arrangement area 191, dot-shaped terminal connection portions corresponding to the terminals of the composite chip 104 are arranged in a matrix at substantially equal intervals. The composite chip 104 has a total of 1020 terminals arranged in 32 rows and 32 columns (however, four of the four corners are missing) on the bottom side, and each of these terminals is connected to the corresponding terminal connection portion. It is mounted in the composite chip arrangement area 191 in the state.

The control ROM placement area 192 is a substantially rectangular shape that is long in the Y direction corresponding to the shape of the ROM socket 193 (see FIG. 8) in which the control ROM 105 is mounted, and the length of the long side thereof is the length of one side of the composite chip placement area 191. It is about the same as. The control ROM arrangement area 192 is arranged in the vicinity of the + X side with respect to the composite chip arrangement area 191 and is the long side of the −X side and the + X side of the control ROM arrangement area 192. , 192b, the first edge portion 192a is the first edge portion 191a of the first to fourth edge portions 191a to 191d on the + X side, the −Y side, the −X side, and the + Y side of the composite chip arrangement region 191. On the other hand, they face each other at a predetermined distance in a state of being displaced in the −Y direction.

In the control ROM arrangement area 192, a plurality of terminal connection portions (ROM terminal connection portions) are arranged along both long sides, that is, along the first and second edge portions 192a and 192b, respectively (35 in this case). ing. Further, a ROM socket 193 that detachably supports the control ROM 105 is fixed in the control ROM arrangement area 192, and the control ROM 105 is detachably attached to the ROM socket 193 (FIG. 8). A plurality of terminals (35 each in this case) are arranged in the control ROM 105 along both ends thereof, and each terminal is connected to each terminal connection portion of the control ROM arrangement area 192 via the ROM socket 193. It is connected.

As shown in FIG. 8, the ROM socket 193 removably holds both edges of a substantially rectangular bottom wall 193a corresponding to the control ROM arrangement area 192 and a control ROM 105 mounted on the bottom wall 193a. A pair of ROM holding portions 193b are provided, and the bottom wall 193a is fixed to the surface 98a of the liquid crystal control substrate 98 in a state of covering substantially the entire control ROM arrangement area 192. Therefore, the wiring pattern (via, etc.) in the control ROM arrangement area 192 in the first wiring layer La1 is shielded by the bottom wall (shielding wall) 193a of the ROM socket 193 even when the control ROM 105 is removed from the ROM socket 193. It cannot be visually recognized from the outside. This makes it possible to improve the preventiveness against goto acts such as illegally modifying the wiring pattern connecting the composite chip 104 and the control ROM 105. Further, by drawing a wiring pattern in the control ROM arrangement area 192, it is possible to secure a wiring space in other areas.

Further, as shown in FIG. 25, in the sixth wiring layer (B wiring layer) La6 on the back surface 98b side, a first connector arrangement area 194 in which the liquid crystal control first connector CN31 is arranged and a liquid crystal control second connector CN32 are provided. A second connector arrangement area 195 to be arranged is provided. The first connector arrangement area 194 is a substantially rectangular shape long in the X direction, and is arranged in the vicinity of the + Y side edge of the back surface 98b of the liquid crystal control substrate 98. In the first connector arrangement area 194, a plurality of terminal connection portions (here, 70 each) corresponding to each terminal of the liquid crystal control first connector CN31 are arranged along a pair of long sides. Further, the second connector arrangement area 195 is a substantially rectangular shape long in the X direction, and is arranged in the vicinity of the edge portion on the −Y side of the back surface 98b of the liquid crystal control substrate 98. In the second connector arrangement area 195, a plurality of terminal connection portions (here, 50 each) corresponding to each terminal of the liquid crystal control second connector CN32 are arranged along a pair of long sides.

Of all the terminals of the composite chip 104, the terminals connected to the control ROM 105 are centrally arranged in the vicinity of the first edge portion 191a on the control ROM 105 side in the composite chip arrangement area 191. FIG. 26 shows the types (terminal information) of each of the terminals in the vicinity of the first edge portion 191a and the vicinity of the second edge portion 192b among all the terminals of the composite chip 104. The arrangement of each terminal in FIG. 26 matches the arrangement of the terminal connection portion in the composite chip arrangement area 191 in FIG. 20.

In FIG. 26A, HAD0 to HAD25 are address output terminals for outputting address information, HDT0 to HDT15 are data input / output terminals for inputting / outputting data information, and HCS0 is a chip for outputting chip select signals. The select output terminal, the lead strobe output terminal for the HRD to output the read strobe signal, and the system reset terminal for the HREST to input the system reset signal.

Further, in FIG. 26B, RA0 + and RA0- are data output terminals corresponding to the differential signal line RA0 on the first transmission line LVDS1 side, and RA1 + and RA1- are differential signal lines on the first transmission line LVDS1 side. The data output terminals RA2 + and RA2- corresponding to RA1 are the differential signal lines on the LVDS1 side of the first transmission line. The data output terminals RA3 + and RA3- corresponding to RA2 are the differential signal lines on the LVDS1 side of the first transmission line. The data output terminals RACLK + and RACLK- corresponding to RA3 are the differential signal lines on the first transmission line LVDS1 side, and the clock output terminals corresponding to RACLK, RB0 + and RB0- are the differential signal lines on the second transmission line LVDS2 side. The data output terminals RB1 + and RB1- corresponding to RB0 are the differential signal lines on the second transmission line LVDS2 side. The data output terminals RB3 + and RB3- corresponding to RB2 are the differential signal lines on the second transmission line LVDS2 side. It is a clock output terminal corresponding to RBCLK.

In the following description, the terminals of the corresponding composite chip 104, such as HAD0 to HAD25, HDT0 to HDT15, RA1 +, RA1-, RBCLK +, and RBCLK-, are used as they are for the terminal connection portion in the composite chip arrangement area 191. do. For example, the terminal connection portion HRD indicates a terminal connection portion corresponding to the lead strobe output terminal HRD.

Further, FIG. 27 shows the types (terminal information) of each terminal of the control ROM 105. Of the terminals shown in FIG. 27, A0 to A24 are address input terminals for inputting address information, Q0 to Q15 are data input / output terminals for inputting / outputting data information, and address output terminals of the composite chip 104, respectively. , Connected to the data input / output terminal. CE # is a chip select input terminal for inputting a chip select signal, and is connected to a chip select output terminal of the composite chip 104. WE # is a writable input terminal, and by connecting to a power source and always setting the H level, it is possible to switch the mode according to the value (H / L) of the OE # terminal. OE # is an outputable input terminal and is connected to the lead strobe output terminal of the composite chip 104.

RESET # is a reset terminal, and is connected to a power supply voltage monitoring integrated circuit (reset IC) together with the system reset input terminal HRESET of the composite chip 104. WP # / ACC is a write-protected / program input terminal, and by connecting to ground (L level) or power supply (H level), it is possible to switch between write prohibition / permission and program execution prohibition / permission. There is. In this embodiment, the WP # / ACC terminal is connected to the power supply and set to the H level. BYTE # is an 8-bit mode selection terminal, and by connecting to the ground (L level) or power supply (H level), it is possible to select either the 8-bit communication mode or the 16-bit communication mode.

In the following description, the symbols A0 to A24, Q0 to Q15, CE #, and the like of the terminals of the corresponding control ROM 105 are used as they are for the terminal connection portion corresponding to the control ROM arrangement area 192. For example, the terminal connection portion RESET # indicates a terminal connection portion corresponding to the reset terminal RESET #.

Hereinafter, among a large number of wiring paths provided on the liquid crystal control board 98, a plurality of types of wiring paths P1 connecting the composite chip 104, the control ROM 105, the liquid crystal control first connector CN31, the liquid crystal control second connector CN32, and the like. -Focusing on P71, the details thereof will be described with reference to the drawings. It should be noted that FIGS. 28 to 33 show only the portions constituting the wiring paths P1 to P71 extracted from the wiring patterns of the first to sixth wiring layers La1 to La6 shown in FIGS. 20 to 25. 34 to 44 are partially enlarged views thereof. Further, FIGS. 45 to 53 schematically show the wiring paths of the wiring paths P1 to P71. In FIGS. 45 to 50, the vias displayed in gray (for example, the via v86 in the wiring path P1 of FIG. 45) indicate the vias (specific interlayer conduction portion) arranged in the control ROM arrangement area 192, and are thick lines. The wiring line indicated by (for example, the wiring line cp13 in the wiring line P2 in FIG. 45) indicates a wiring line connected to the terminal connection portion on the control ROM 105 side from the inside of the control ROM arrangement area 192.

First, the wiring lines P1 to P26 connected to the address output terminals HAD0 to HAD25 of the composite chip 104 will be described. In the present embodiment, of the address output terminals HAD0 to HAD25, HAD1 to HAD25 are connected to the address input terminals A0 to A24 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31. On the other hand, the address output terminal HAD0 is connected to the liquid crystal control first connector CN31, but is not connected to the terminal on the control ROM 105 side.

Comparing the arrangement of the address output terminals HAD1 to HAD25 of the composite chip 104 (FIG. 26A) with the arrangement of the corresponding address input terminals A0 to A24 of the control ROM 105 (FIG. 27), both are clear. It's different. That is, the address output terminals HAD1 to HAD25 of the composite chip 104 are arranged in 6 rows as shown in FIG. 26 (a), and the number of columns is different for each row, but the arrangement order is constant. On the other hand, the address input terminals A0 to A24 of the control ROM 105 are arranged in two columns as shown in FIG. 27, and there is no fixed regularity in the order of arrangement in each column. Moreover, the arrangement position of the composite chip 104 and the control ROM 105 and the large number of wiring patterns are related to each other, which makes the wiring pattern routing very complicated. Therefore, it is very important to optimize the wiring pattern that connects the composite chip 104 and the control ROM 105, which can shorten the wire length of the wiring pattern, reduce noise, and slim down the entire board. It leads to the plan. Further, the same can be said not only in the relationship between the composite chip 104 and the control ROM 105, but also in the relationship between the composite chip 104 and electronic components such as various connectors. In particular, the wiring pattern connected to a plurality of electronic components such as composite chips 104 such as HAD1 to HAD25 and HDT1 to HDT25, a control ROM 105, and various connectors has a large effect by optimizing the above-mentioned problems. It becomes a thing.

Of the wiring lines P1 to P26, in the wiring line P1 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD0 provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided by the wiring line cp0. It is connected to a via v0 arranged in the vicinity of the diagonally −XY direction. The via v0 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD0) arranged around the via v0. As shown in FIG. 37, the via v0 is connected to the via v41 by a wiring path cp1 provided in the third wiring layer La3. The via v41 is arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. Then, as shown in FIG. 40, the via v41 is connected to the via v86 arranged in the control ROM arrangement area 192 by the wiring path cp2 provided in the fourth wiring layer La4. As described above, the wiring line drawn from the terminal connection portion HAD0 in the first wiring layer La1 is connected to the via v86 in the control ROM arrangement area 192 via the two wiring layers La3 and La4.

The wiring line that reaches the via v86 from the terminal connection portion HAD0 is branched into two by this via v86. As shown in FIGS. 37 and 38, the first branch path is a first connector arrangement area 194 from the via v86 via the via v205 constituting the test point TP28 by the wiring path cp3 provided in the third wiring layer La3. It is connected to the via v146 in the inside, and further, as shown in FIG. 42, is connected to the terminal connection portion had0 from the inside of the first connector arrangement area 194 by the wiring path cp4 provided in the sixth wiring layer La6. .. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA16 from the via v86 by the wiring path cp5 provided in the sixth wiring layer La6. The other end of the terminating resistor RA16 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

In the wiring line P2 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD1 provided in the composite chip arrangement region 191 of the first wiring layer La1 is located near the diagonal −XY direction by the wiring path cp11. It is connected to the via v5 arranged in. The via v5 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD1) arranged around the via v5. As shown in FIG. 40, the via v5 is connected to the via v85 arranged in the control ROM arrangement area 192 by the wiring path cp12 provided in the fourth wiring layer La4. In this way, the wiring line drawn out from the terminal connection portion HAD1 does not pass through the third wiring layer La3, but is arranged in the control ROM via the fourth wiring layer La4, unlike the wiring line drawn out from the terminal connection portion HAD0. It is connected to via v85 in region 192.

The wiring line that reaches the via v85 from the terminal connection portion HAD1 is branched into four by this via v85. As shown in FIG. 35, the first branch path is connected from the via v85 to the terminal connection portion A0 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp13 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA16 from the via v85 by the wiring path cp14 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v85 to the via v145 in the first connector arrangement area 194 by the wiring path cp15 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp16 provided in the sixth wiring layer La6 is connected to the terminal connection portion had1 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v85 to the via v182 by the wiring path cp17 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v182. 6 The wiring path cp18 provided in the wiring layer La6 is connected to the decoder IC12 constituting the decoding circuit.

Although partly omitted in the wiring diagram of FIG. 43 and the like, the decoding circuit including the decoders IC12 to IC14 is configured as shown in FIG. 54. As shown in FIG. 54, the decoders IC13 and IC14 are connected to the liquid crystal display means 76 and the like via the liquid crystal IF third connector CN23 and the like, and are connected to the data input / output terminals HDT0 to HDT15 of the composite chip 104 when the power is turned on. Data information is entered. Since the decoders IC 13 and IC 14 output data information to the liquid crystal display means 76 or the like based on the clock synchronized with the CPU input from the decoder IC 12, the CPU does not need to transmit fixed data information every time. As a result, it is not necessary to output the same data information from the CPU at predetermined time intervals, and the CPU only needs to transmit new data information when the content of the data information is changed, which simplifies the control program. It becomes possible to change.

In the wiring line P3 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD2 provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp21. It is connected to the placed via v4. The via v4 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD2) arranged around the via v4. As shown in FIG. 40, the via v4 is connected to the via v84 arranged in the control ROM arrangement area 192 by the wiring path cp22 provided in the fourth wiring layer La4.

The wiring line that reaches the via v84 from the terminal connection portion HAD2 is branched into four by this via v84. As shown in FIG. 35, the first branch path is connected from the via v84 to the terminal connection portion A1 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp23 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA16 from the via v84 by the wiring path cp24 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v84 to the via v144 in the first connector arrangement area 194 by the wiring path cp25 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp26 provided in the sixth wiring layer La6 is connected to the terminal connection portion had2 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v84 to the via v184 by the wiring path cp27 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v184. The wiring path cp28 provided in the 6 wiring layer La6 is connected to the decoder IC 12 constituting the decoding circuit.

In the wiring line P4 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD3 provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp31. It is connected to the placed via v13. The via v13 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD3) arranged around the via v13. As shown in FIG. 40, the via v13 is connected to the via v83 arranged in the control ROM arrangement area 192 by the wiring path cp32 provided in the fourth wiring layer La4.

The wiring line that reaches the via v83 from the terminal connection portion HAD3 is branched into four by this via v83. As shown in FIG. 35, the first branch path is connected from the via v83 to the terminal connection portion A2 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp33 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA16 from the via v83 by the wiring path cp34 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v83 to the via v143 in the first connector arrangement area 194 by the wiring path cp35 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp36 provided in the sixth wiring layer La6 is connected to the terminal connection portion had3 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v83 to the via v181 by the wiring path cp37 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v181. The wiring path cp38 provided in the 6 wiring layer La6 is connected to the decoder IC 12 constituting the decoding circuit.

In the wiring line P5 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD4 provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp41. It is connected to the placed via v20. The via v20 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD4) arranged around the via v20. As shown in FIG. 40, the via v20 is connected to the via v82 arranged in the control ROM arrangement area 192 by the wiring path cp42 provided in the fourth wiring layer La4.

The wiring line that reaches the via v82 from the terminal connection portion HAD4 is branched into three by this via v82. As shown in FIG. 35, the first branch path is connected from the via v82 to the terminal connection portion A3 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp43 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA15 from the via v82 by the wiring path cp44 provided in the sixth wiring layer La6. The other end of the terminating resistor RA15 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v82 to the via v142 in the first connector arrangement area 194 by the wiring path cp45 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp46 provided in the sixth wiring layer La6 is connected to the terminal connection portion had4 from the inside of the first connector arrangement area 194.

In the wiring line P6 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD5 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp51. Specifically, it is connected to the via v34 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HAD5 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v34 is connected to the via v81 arranged in the control ROM arrangement area 192 by the wiring path cp52 provided in the fourth wiring layer La4.

The wiring line that reaches the via v81 from the terminal connection portion HAD5 is branched into three by this via v81. As shown in FIG. 35, the first branch path is connected from the via v81 to the terminal connection portion A4 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp53 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected from the via v81 to the terminating resistor RA15 by the wiring path cp54 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v81 to the via v141 in the first connector arrangement area 194 by the wiring path cp55 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp56 provided in the sixth wiring layer La6 is connected to the terminal connection portion had5 from the inside of the first connector arrangement area 194.

In the wiring path P7 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD6 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp61. Specifically, it is connected to the via v39 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HAD6 is arranged on the outermost peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v39 is connected to the via v80 arranged in the control ROM arrangement area 192 by the wiring path cp62 provided in the fourth wiring layer La4.

The wiring line that reaches the via v80 from the terminal connection portion HAD6 is branched into three by this via v80. As shown in FIG. 35, the first branch path is connected from the via v80 to the terminal connection portion A5 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp63 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected from the via v80 to the terminating resistor RA15 by the wiring path cp64 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v80 to the via v140 in the first connector arrangement area 194 by the wiring path cp65 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp66 provided in the sixth wiring layer La6 is connected to the terminal connection portion had6 from the inside of the first connector arrangement area 194.

In the wiring line P8 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD7 provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp71. It is connected to the placed via v3. The via v3 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD7) arranged around the via v3. As shown in FIG. 40, the via v3 is connected to the via v79 arranged in the control ROM arrangement area 192 by the wiring path cp72 provided in the fourth wiring layer La4.

The wiring line that reaches the via v79 from the terminal connection portion HAD7 is branched into three by this via v79. As shown in FIG. 35, the first branch path is connected from the via v79 to the terminal connection portion A6 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp73 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected from the via v79 to the terminating resistor RA15 by the wiring path cp74 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v79 to the via v139 in the first connector arrangement area 194 by the wiring path cp75 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp76 provided in the sixth wiring layer La6 is connected to the terminal connection portion had7 from the inside of the first connector arrangement area 194.

In the wiring line P9 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD8 provided in the composite chip arrangement region 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp81. It is connected to the placed via v12. The via v12 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD8) arranged around the via v12. As shown in FIG. 40, the via v12 is connected to the via v78 arranged in the control ROM arrangement area 192 by the wiring path cp82 provided in the fourth wiring layer La4.

The wiring line that reaches the via v78 from the terminal connection portion HAD8 is branched into three by this via v78. As shown in FIG. 35, the first branch path is connected from the via v78 to the terminal connection portion A7 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp83 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected from the via v78 to the terminating resistor RA13 by the wiring path cp84 provided in the sixth wiring layer La6. The other end of the terminating resistor RA13 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v78 to the via v138 in the first connector arrangement area 194 by the wiring path cp85 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp86 provided in the sixth wiring layer La6 is connected to the terminal connection portion had8 from the inside of the first connector arrangement area 194.

In the wiring path P10 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD9 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp91. Specifically, it is connected to the via v33 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HAD9 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v33 is connected to the via v77 arranged in the control ROM arrangement area 192 by the wiring path cp92 provided in the fourth wiring layer La4.

The wiring line that reaches the via v77 from the terminal connection portion HAD9 is branched into three by this via v77. As shown in FIG. 35, the first branch path is connected from the via v77 to the terminal connection portion A8 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp93 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected from the via v77 to the terminating resistor RA13 by the wiring path cp94 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v77 to the via v137 in the first connector arrangement area 194 by the wiring path cp95 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp96 provided in the sixth wiring layer La6 is connected to the terminal connection portion had9 from the inside of the first connector arrangement area 194.

In the wiring path P11 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD10 provided in the composite chip arrangement region 191 of the first wiring layer La1 is located outside the composite chip arrangement region 191 by the wiring path cp101. Specifically, it is connected to the via v38 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HAD10 is arranged on the outermost peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v38 is connected to the via v76 arranged in the control ROM arrangement area 192 by the wiring path cp102 provided in the fourth wiring layer La4.

The wiring line that reaches the via v76 from the terminal connection portion HAD10 is branched into three by this via v76. As shown in FIG. 35, the first branch path is connected from the via v76 to the terminal connection portion A9 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp103 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected from the via v76 to the terminating resistor RA13 by the wiring path cp104 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v76 to the via v136 in the first connector arrangement area 194 by the wiring path cp105 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp106 provided in the sixth wiring layer La6 is connected to the terminal connection portion had10 from the inside of the first connector arrangement area 194.

In the wiring line P12 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD11 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonally −X + Y direction by the wiring line cp111. It is connected to the via v2. The via v2 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD11) arranged around the via v2. As shown in FIG. 40, the via v2 is connected to the via v75 arranged in the control ROM arrangement area 192 by the wiring path cp112 provided in the fourth wiring layer La4.

The wiring line that reaches the via v75 from the terminal connection portion HAD11 is branched into three by this via v75. As shown in FIG. 35, the first branch path is connected from the via v75 to the terminal connection portion A10 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp113 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA13 from the via v75 by the wiring path cp114 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v75 to the via v135 in the first connector arrangement area 194 by the wiring path cp115 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp116 provided in the sixth wiring layer La6 is connected to the terminal connection portion had11 from the inside of the first connector arrangement area 194.

In the wiring line P13 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD12 provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp121. It is connected to the placed via v19. The via v19 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD12) arranged around the via v19. As shown in FIG. 40, the via v19 is connected to the via v74 arranged in the control ROM arrangement area 192 by the wiring path cp122 provided in the fourth wiring layer La4.

The wiring line that reaches the via v74 from the terminal connection portion HAD12 is branched into three by this via v74. As shown in FIG. 35, the first branch path is connected from the via v74 to the terminal connection portion A11 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp123 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected from the via v74 to the terminating resistor RA11 by the wiring path cp124 provided in the sixth wiring layer La6. The other end of the terminating resistor RA11 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v74 to the via v134 in the first connector arrangement area 194 by the wiring path cp125 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp126 provided in the sixth wiring layer La6 is connected to the terminal connection portion had12 from the inside of the first connector arrangement area 194.

In the wiring line P14 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD13 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp131. Specifically, it is connected to the via v49 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD 13 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v49 is connected to the via v73 arranged in the control ROM arrangement area 192 by the wiring path cp132 provided in the fourth wiring layer La4.

The wiring line that reaches the via v73 from the terminal connection portion HAD13 is branched into two by this via v73. As shown in FIG. 41, the first branch path is connected to the terminating resistor RA11 from the via v73 by the wiring path cp133 provided in the sixth wiring layer La6.

Further, as shown in FIG. 37, the second branch path is connected from the via v73 to the via v107 arranged in the control ROM arrangement area 192 by the wiring path cp134 provided in the third wiring layer La3. , Here it is further branched into two. As shown in FIG. 35, the first branch path of the second a is a control ROM arrangement area from the via v107 to the terminal connection portion A12 of the control ROM 105 by the wiring path cp135 provided in the first wiring layer La1. It is connected from the inside of 192. Further, as shown in FIGS. 37 and 38, the second branch path of the second b is from the via v107 to the via v133 in the first connector arrangement area 194 by the wiring path cp136 provided in the third wiring layer La3. Further, as shown in FIG. 42, the wiring path cp137 provided in the sixth wiring layer La6 is connected to the terminal connection portion had13 from the inside of the first connector arrangement area 194.

In the wiring path P15 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD14 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp141. Specifically, it is connected to the via v50 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD 14 is arranged on the outermost peripheral side of the composite chip arrangement region 191. As shown in FIG. 40, the via v50 is connected to the via v72 arranged in the control ROM arrangement area 192 by the wiring path cp142 provided in the fourth wiring layer La4.

The wiring line that reaches the via v72 from the terminal connection portion HAD14 is branched into two by this via v72. As shown in FIG. 41, the first branch path is connected from the via v72 to the terminating resistor RA11 by the wiring path cp143 provided in the sixth wiring layer La6.

Further, as shown in FIG. 37, the second branch path is connected from the via v72 to the via v106 arranged in the control ROM arrangement area 192 by the wiring path cp144 provided in the third wiring layer La3. , Here it is further branched into two. As shown in FIG. 35, the first branch path of the second a is a control ROM arrangement area from the via v106 to the terminal connection portion A13 of the control ROM 105 by the wiring path cp145 provided in the first wiring layer La1. It is connected from the inside of 192. Further, as shown in FIGS. 37 and 38, the second branch path of the second b is from the via v106 to the via v132 in the first connector arrangement area 194 by the wiring path cp146 provided in the third wiring layer La3. It is connected, and as shown in FIG. 42, it is connected to the terminal connection portion had 14 from the inside of the first connector arrangement area 194 by the wiring path cp147 provided in the sixth wiring layer La6.

In the wiring line P16 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD15 provided in the composite chip arrangement region 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp151. It is connected to the placed via v11. The via v11 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD15) arranged around the via v11. As shown in FIG. 40, the via v11 is connected to the via v71 arranged in the control ROM arrangement area 192 by the wiring path cp152 provided in the fourth wiring layer La4.

The wiring line that reaches the via v71 from the terminal connection portion HAD15 is branched into two by this via v71. As shown in FIG. 41, the first branch path is connected from the via v71 to the terminating resistor RA11 by the wiring path cp153 provided in the sixth wiring layer La6.

Further, as shown in FIG. 37, the second branch path is connected from the via v71 to the via v105 arranged in the control ROM arrangement area 192 by the wiring path cp154 provided in the third wiring layer La3. , Here it is further branched into two. As shown in FIG. 35, the first branch path of the second a is a control ROM arrangement area from the via v105 to the terminal connection portion A14 of the control ROM 105 by the wiring path cp155 provided in the first wiring layer La1. It is connected from the inside of 192. Further, as shown in FIGS. 37 and 38, the second branch path of the second b is from the via v105 to the via v131 in the first connector arrangement area 194 by the wiring path cp156 provided in the third wiring layer La3. Further, as shown in FIG. 42, the wiring path cp157 provided in the sixth wiring layer La6 is connected to the terminal connection portion had15 from the inside of the first connector arrangement area 194.

In the wiring line P17 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD16 provided in the composite chip arrangement region 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp161. It is connected to the placed via v18. The via v18 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD16) arranged around the via v18. As shown in FIG. 40, the via v18 is connected to the via v70 arranged in the control ROM arrangement area 192 by the wiring path cp162 provided in the fourth wiring layer La4.

The wiring line that reaches the via v70 from the terminal connection portion HAD16 is branched into two by this via v70. As shown in FIG. 41, the first branch path is connected to the terminating resistor RA10 from the via v70 by the wiring path cp163 provided in the sixth wiring layer La6. The other end of the terminating resistor RA10 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIG. 37, the second branch path is connected from the via v70 to the via v104 arranged in the control ROM arrangement area 192 by the wiring path cp164 provided in the third wiring layer La3. , Here it is further branched into two. As shown in FIG. 35, the first branch path of the second a is a control ROM arrangement area from the via v104 to the terminal connection portion A15 of the control ROM 105 by the wiring path cp165 provided in the first wiring layer La1. It is connected from the outside of 192. Further, as shown in FIGS. 37 and 38, the second branch path of the second b is from the via v104 to the via v130 in the first connector arrangement area 194 by the wiring path cp166 provided in the third wiring layer La3. It is connected, and as shown in FIG. 42, it is connected to the terminal connection portion had16 from the inside of the first connector arrangement area 194 by the wiring path cp167 provided in the sixth wiring layer La6.

In the wiring line P18 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD17 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp171. Specifically, it is connected to the via v51 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD17 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v51 is connected to the via v69 arranged in the control ROM arrangement area 192 by the wiring path cp172 provided in the fourth wiring layer La4.

The wiring line that reaches the via v69 from the terminal connection portion HAD17 is branched into two by this via v69. As shown in FIG. 41, the first branch path is connected to the terminating resistor RA10 from the via v69 by the wiring path cp173 provided in the sixth wiring layer La6.

Further, as shown in FIG. 37, the second branch path is connected from the via v69 to the via v103 arranged in the control ROM arrangement area 192 by the wiring path cp174 provided in the third wiring layer La3. , Here it is further branched into two. As shown in FIG. 35, the first branch path of the second a is a control ROM arrangement area from the via v103 to the terminal connection portion A16 of the control ROM 105 by the wiring path cp175 provided in the first wiring layer La1. It is connected from the outside of 192. Further, as shown in FIGS. 37 and 38, the second branch path of the second b is from the via v103 to the via v129 in the first connector arrangement area 194 by the wiring path cp176 provided in the third wiring layer La3. It is connected, and as shown in FIG. 42, it is connected to the terminal connection portion had17 from the inside of the first connector arrangement area 194 by the wiring path cp177 provided in the sixth wiring layer La6.

In the wiring path P19 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD18 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp181. Specifically, it is connected to the via v52 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD18 is arranged on the outermost peripheral side of the composite chip arrangement region 191. As shown in FIG. 40, the via v52 is connected to the via v68 arranged in the control ROM arrangement area 192 by the wiring path cp182 provided in the fourth wiring layer La4.

The wiring line that reaches the via v68 from the terminal connection portion HAD18 is branched into three by this via v68. As shown in FIG. 35, the first branch path is connected from the via v68 to the terminal connection portion A17 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp183 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA10 from the via v68 by the wiring path cp184 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v68 to the via v128 in the first connector arrangement area 194 by the wiring path cp185 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp186 provided in the sixth wiring layer La6 is connected to the terminal connection portion had18 from the inside of the first connector arrangement area 194.

In the wiring line P20 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD19 provided in the composite chip arrangement region 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp191. It is connected to the placed via v1. The via v1 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD19) arranged around the via v1. As shown in FIG. 40, the via v1 is connected to the via v67 arranged in the control ROM arrangement area 192 by the wiring path cp192 provided in the fourth wiring layer La4.

The wiring line that reaches the via v67 from the terminal connection portion HAD19 is branched into three by this via v67. As shown in FIG. 35, the first branch path is connected from the via v67 to the terminal connection portion A18 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp193 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA10 from the via v67 by the wiring path cp194 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v67 to the via v127 in the first connector arrangement area 194 by the wiring path cp195 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp196 provided in the sixth wiring layer La6 is connected to the terminal connection portion had19 from the inside of the first connector arrangement area 194.

In the wiring line P21 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD20 provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring path cp201. It is connected to the placed via v10. The via v10 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD20) arranged around the via v10. As shown in FIG. 40, the via v10 is connected to the via v66 arranged in the control ROM arrangement area 192 by the wiring path cp202 provided in the fourth wiring layer La4.

The wiring line that reaches the via v66 from the terminal connection portion HAD20 is branched into three by this via v66. As shown in FIG. 35, the first branch path is connected from the via v66 to the terminal connection portion A19 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp203 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA9 from the via v66 by the wiring path cp204 provided in the sixth wiring layer La6. The other end of the terminating resistor RA9 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v66 to the via v126 in the first connector arrangement area 194 by the wiring path cp205 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp206 provided in the sixth wiring layer La6 is connected to the terminal connection portion had20 from the inside of the first connector arrangement area 194.

In the wiring path P22 (FIG. 47), as shown in FIGS. 34 and 35, the terminal connection portion HAD21 provided in the composite chip arrangement region 191 of the first wiring layer La1 has the composite chip arrangement region 191 due to the wiring path cp211. It is connected to the via v54 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD21 is arranged on the outermost peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v54 is connected to the via v65 arranged in the control ROM arrangement area 192 by the wiring path cp212 provided in the fourth wiring layer La4.

The wiring line that reaches the via v65 from the terminal connection portion HAD21 is branched into three by this via v65. As shown in FIG. 35, the first branch path is connected from the via v65 to the terminal connection portion A20 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp213 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA9 from the via v65 by the wiring path cp214 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v65 to the via v125 in the first connector arrangement area 194 by the wiring path cp215 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp216 provided in the sixth wiring layer La6 is connected to the terminal connection portion had21 from the inside of the first connector arrangement area 194.

In the wiring path P23 (FIG. 47), as shown in FIGS. 34 and 35, the terminal connection portion HAD22 provided in the composite chip arrangement region 191 of the first wiring layer La1 has the composite chip arrangement region 191 due to the wiring path cp221. It is connected to the via v53 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD22 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v53 is connected to the via v64 arranged in the control ROM arrangement area 192 by the wiring path cp222 provided in the fourth wiring layer La4.

The wiring line that reaches the via v64 from the terminal connection portion HAD22 is branched into three by this via v64. As shown in FIG. 35, the first branch path is connected from the via v64 to the terminal connection portion A21 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp223 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA9 from the via v64 by the wiring path cp224 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v64 to the via v124 in the first connector arrangement area 194 by the wiring path cp225 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp226 provided in the sixth wiring layer La6 is connected to the terminal connection portion had22 from the inside of the first connector arrangement area 194.

In the wiring line P24 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD23 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp231. It is connected to the via v21. The via v21 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD23) arranged around the via v21. As shown in FIG. 40, the via v21 is located outside the composite chip placement area 191, specifically, the composite chip placement area 191 and the control ROM placement area 192 by the wiring path cp232 provided in the fourth wiring layer La4. It is connected to the via v36 arranged between the above, and as shown in FIGS. 34 and 35, the via v63 arranged in the control ROM arrangement area 192 by the wiring path cp233 provided in the first wiring layer La1. It is connected.

The wiring line that reaches the via v63 from the terminal connection portion HAD23 is branched into three by this via v63. As shown in FIG. 35, the first branch path is connected from the via v63 to the terminal connection portion A22 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp234 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA9 from the via v63 by the wiring path cp235 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v63 to the via v123 in the first connector arrangement area 194 by the wiring path cp236 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp237 provided in the sixth wiring layer La6 is connected to the terminal connection portion had23 from the inside of the first connector arrangement area 194.

In the wiring line P25 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD24 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp241. It is connected to the via v14. The via v14 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD24) arranged around the via v14. As shown in FIG. 40, the via v14 has the wiring path cp242 provided in the fourth wiring layer La4 outside the composite chip placement area 191, specifically, the composite chip placement area 191 and the control ROM placement area 192. It is connected to the via v35 arranged between the above, and as shown in FIGS. 34 and 35, the via v62 arranged in the control ROM arrangement area 192 by the wiring path cp243 provided in the first wiring layer La1. It is connected.

The wiring line that reaches the via v62 from the terminal connection portion HAD24 is branched into four by this via v62. As shown in FIG. 35, the first branch path is connected from the via v62 to the terminal connection portion A23 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp244 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor R45 from the via v62 by the wiring path cp245 provided in the sixth wiring layer La6. The other end of the terminating resistor R45 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v62 to the via v122 in the first connector arrangement area 194 by the wiring path cp246 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp247 provided in the sixth wiring layer La6 is connected to the terminal connection portion had24 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v62 to the via v183 by the wiring path cp248 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v183. 6 The wiring path cp249 provided in the wiring layer La6 is connected to the decoder IC 12 constituting the decoding circuit.

In the wiring line P26 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD25 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp251. It is connected to the via v6. The via v6 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD25) arranged around the via v6. As shown in FIG. 40, the via v6 has a wiring path cp252 provided in the fourth wiring layer La4, and is provided outside the composite chip placement area 191, specifically, the composite chip placement area 191 and the control ROM placement area 192. It is connected to the via v40 arranged between the above, and as shown in FIGS. 34 and 35, the via v61 arranged in the control ROM arrangement area 192 by the wiring path cp253 provided in the first wiring layer La1. It is connected.

The wiring line that reaches the via v61 from the terminal connection portion HAD25 is branched into three by this via v61. As shown in FIG. 35, the first branch path is connected from the via v61 to the terminal connection portion A24 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp254 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor R44 from the via v61 by the wiring path cp255 provided in the sixth wiring layer La6. The other end of the terminating resistor R44 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v61 to the via v121 in the first connector arrangement area 194 by the wiring path cp256 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp257 provided in the sixth wiring layer La6 is connected to the terminal connection portion had25 from the inside of the first connector arrangement area 194.

Subsequently, the wiring paths P27 to P42 connected to the data input / output terminals HDT0 to HDT15 of the composite chip 104 will be described. The data input / output terminals HDT0 to HDT15 are connected to the data input / output terminals Q0 to Q15 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31.

Comparing the arrangement of the data input / output terminals HDT0 to HDT15 of the composite chip 104 (FIG. 26A) and the arrangement of the corresponding data input / output terminals Q0 to Q15 of the control ROM 105 (FIG. 27), both are It's clearly different. That is, the data input / output terminals HDT0 to HDT15 of the composite chip 104 are arranged in four rows as shown in FIG. 26 (a), and the number of columns is different for each row, but the arrangement order is constant. On the other hand, the data input / output terminals Q0 to Q15 of the control ROM 105 are arranged in two columns as shown in FIG. 27, and there is no fixed regularity in the order of arrangement in each column. Moreover, the arrangement position of the composite chip 104 and the control ROM 105 and the large number of wiring patterns are related to each other, which makes the wiring pattern routing very complicated. Therefore, it is very important to optimize the wiring pattern that connects the composite chip 104 and the control ROM 105, which can shorten the wire length of the wiring pattern, reduce noise, and slim down the entire board. It leads to the plan. Further, the same can be said not only in the relationship between the composite chip 104 and the control ROM 105, but also in the relationship between the composite chip 104 and electronic components such as various connectors. In particular, regarding the wiring pattern connected to a plurality of electronic components such as composite chips 104 such as HAD1 to HAD25 and HDT1 to HDT25, a control ROM 105, and various connectors, the above-mentioned problems are large and the effect of optimization is also large. It becomes a thing.

Of the wiring lines P27 to P42, in the wiring line P27 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT0 provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided by the wiring line cp301. It is connected to the outside of the composite chip placement area 191, specifically, the via v32 arranged between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection portion HDT0 is arranged on the outermost peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v32 is connected to the via v102 arranged in the control ROM arrangement area 192 by the wiring path cp302 provided in the fourth wiring layer La4.

The wiring line reaching the via v102 from the terminal connection portion HDT0 is branched into four by the via v102. As shown in FIG. 35, the first branch path is connected from the via v102 to the terminal connection portion Q0 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp303 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA34 from the via v102 by the wiring path cp304 provided in the sixth wiring layer La6. The other end of the terminating resistor RA34 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v102 to the via v162 in the first connector arrangement area 194 by the wiring path cp305 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp306 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt0 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v102 to the via v197 by the wiring path cp307 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v197. The wiring path cp308 provided in the 6 wiring layer La6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring path P28 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT1 provided in the composite chip arrangement region 191 of the first wiring layer La1 is located outside the composite chip arrangement region 191 by the wiring path cp311. Specifically, it is connected to the via v31 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT1 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v31 is connected to the via v101 arranged in the control ROM arrangement area 192 by the wiring path cp312 provided in the fourth wiring layer La4.

The wiring line that reaches the via v101 from the terminal connection portion HDT1 is branched into four by the via v101. As shown in FIG. 35, the first branch path is connected from the via v101 to the terminal connection portion Q1 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp313 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected from the via v101 to the terminating resistor RA34 by the wiring path cp314 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v101 to the via v161 in the first connector arrangement area 194 by the wiring path cp315 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp316 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt1 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v101 to the via v198 by the wiring path cp317 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v198. The wiring path cp318 provided in the 6 wiring layer La6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring line P29 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT2 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp321. It is connected to the via v24. The via v24 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT2) arranged around the via v24. As shown in FIG. 40, the via v24 is connected to the via v100 arranged in the control ROM arrangement area 192 by the wiring path cp322 provided in the fourth wiring layer La4.

The wiring line that reaches the via v100 from the terminal connection portion HDT2 is branched into four by the via v100. As shown in FIG. 35, the first branch path is connected from the via v100 to the terminal connection portion Q2 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp323 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected from the via v100 to the terminating resistor RA34 by the wiring path cp324 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v100 to the via v160 in the first connector arrangement area 194 by the wiring path cp325 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp326 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt2 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v100 to the via v199 by the wiring path cp327 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v199. 6 The wiring path cp328 provided in the wiring layer La6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring line P30 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT3 provided in the composite chip arrangement region 191 of the first wiring layer La1 is located near the diagonally −XY direction by the wiring line cp331. It is connected to the via v8 arranged in. The via v8 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT3) arranged around the via v8. As shown in FIG. 40, the via v8 is connected to the via v99 arranged in the control ROM arrangement area 192 by the wiring path cp332 provided in the fourth wiring layer La4.

The wiring line that reaches the via v99 from the terminal connection portion HDT3 is branched into four by this via v99. As shown in FIG. 35, the first branch path is connected from the via v99 to the terminal connection portion Q3 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp333 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA34 from the via v99 by the wiring path cp334 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v99 to the via v159 in the first connector arrangement area 194 by the wiring path cp335 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp336 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt3 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v99 to the via v200 by the wiring path cp337 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v200. 6 The wiring path cp338 provided in the wiring layer La6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring line P31 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT4 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp341. Specifically, it is connected to the via v37 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT4 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 40, the via v37 is connected to the via v98 arranged in the control ROM arrangement area 192 by the wiring path cp342 provided in the fourth wiring layer La4.

The wiring line that reaches the via v98 from the terminal connection portion HDT4 is branched into four by this via v98. As shown in FIG. 35, the first branch path is connected from the via v98 to the terminal connection portion Q4 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp343 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA32 from the via v98 by the wiring path cp344 provided in the sixth wiring layer La6. The other end of the terminating resistor RA32 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v98 to the via v158 in the first connector arrangement area 194 by the wiring path cp345 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp346 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt4 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v98 to the via v189 by the wiring path cp347 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v189. 6 The wiring path cp348 provided in the wiring layer La6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring line P32 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT5 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp351. Specifically, it is connected to the via v46 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT5 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v46 is connected to the via v97 arranged in the control ROM arrangement area 192 by the wiring path cp352 provided in the fourth wiring layer La4.

The wiring line that reaches the via v97 from the terminal connection portion HDT5 is branched into four by this via v97. As shown in FIG. 35, the first branch path is connected from the via v97 to the terminal connection portion Q5 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp353 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA32 from the via v97 by the wiring path cp354 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v97 to the via v157 in the first connector arrangement area 194 by the wiring path cp355 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp356 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt5 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v97 to the via v190 by the wiring path cp357 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v190. 6 The wiring path cp358 provided in the wiring layer La6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring line P33 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT6 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp361. It is connected to the via v17. The via v17 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT6) arranged around the via v17. As shown in FIG. 40, the via v17 is connected to the via v96 arranged in the control ROM arrangement area 192 by the wiring path cp362 provided in the fourth wiring layer La4.

The wiring line that reaches the via v96 from the terminal connection portion HDT6 is branched into four by this via v96. As shown in FIG. 35, the first branch path is connected from the via v96 to the terminal connection portion Q6 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp363 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA32 from the via v96 by the wiring path cp364 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v96 to the via v156 in the first connector arrangement area 194 by the wiring path cp365 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp366 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt6 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v96 to the via v195 by the wiring path cp367 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v195. The wiring path cp368 provided in the 6 wiring layer La6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring path P34 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT7 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp371. Specifically, it is connected to the via v45 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT7 is arranged on the outermost peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v45 is connected to the via v95 arranged in the control ROM arrangement area 192 by the wiring path cp372 provided in the fourth wiring layer La4.

The wiring line that reaches the via v95 from the terminal connection portion HDT7 is branched into four by this via v95. As shown in FIG. 35, the first branch path is connected from the via v95 to the terminal connection portion Q7 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp373 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA32 from the via v95 by the wiring path cp374 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v95 to the via v155 in the first connector arrangement area 194 by the wiring path cp375 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp376 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt7 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v95 to the via v196 by the wiring path cp377 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v196. 6 The wiring path cp378 provided in the wiring layer La6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring line P35 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT8 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp381. Specifically, it is connected to the via v44 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT8 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v44 is connected to the via v94 arranged in the control ROM arrangement area 192 by the wiring path cp382 provided in the fourth wiring layer La4.

The wiring line that reaches the via v94 from the terminal connection portion HDT8 is branched into four by this via v94. As shown in FIG. 35, the first branch path is connected from the via v94 to the terminal connection portion Q8 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp383 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA30 from the via v94 by the wiring path cp384 provided in the sixth wiring layer La6. The other end of the terminating resistor RA30 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v94 to the via v154 in the first connector arrangement area 194 by the wiring path cp385 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp386 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt8 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v94 to the via v191 by the wiring path cp387 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v191. 6 The wiring path cp388 provided in the wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring line P36 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT9 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp391. It is connected to the via v23. The via v23 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT9) arranged around the via v23. As shown in FIG. 40, the via v23 is connected to the via v93 arranged in the control ROM arrangement area 192 by the wiring path cp392 provided in the fourth wiring layer La4.

The wiring line that reaches the via v93 from the terminal connection portion HDT9 is branched into four by this via v93. As shown in FIG. 35, the first branch path is connected from the via v93 to the terminal connection portion Q9 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp393 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA30 from the via v93 by the wiring path cp394 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v93 to the via v153 in the first connector arrangement area 194 by the wiring path cp395 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp396 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt9 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v93 to the via v192 by the wiring path cp397 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v192. 6 The wiring path cp398 provided in the wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring line P37 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT10 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp401. It is connected to the via v16. The via v16 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT10) arranged around the via v16. As shown in FIG. 40, the via v16 is connected to the via v92 arranged in the control ROM arrangement area 192 by the wiring path cp402 provided in the fourth wiring layer La4.

The wiring line that reaches the via v92 from the terminal connection portion HDT10 is branched into four by this via v92. As shown in FIG. 35, the first branch path is connected from the via v92 to the terminal connection portion Q10 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp403 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA30 from the via v92 by the wiring path cp404 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v92 to the via v152 in the first connector arrangement area 194 by the wiring path cp405 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp406 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt10 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v92 to the via v193 by the wiring path cp407 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v193. 6 The wiring path cp408 provided in the wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring line P38 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT11 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp411. It is connected to the via v7. The via v7 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT11) arranged around the via v7. As shown in FIG. 40, the via v7 is connected to the via v91 arranged in the control ROM arrangement area 192 by the wiring path cp412 provided in the fourth wiring layer La4.

The wiring line that reaches the via v91 from the terminal connection portion HDT11 is branched into four by this via v91. As shown in FIG. 35, the first branch path is connected from the via v91 to the terminal connection portion Q11 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp413 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA30 from the via v91 by the wiring path cp414 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v91 to the via v151 in the first connector arrangement area 194 by the wiring path cp415 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp416 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt11 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v91 to the via v194 by the wiring path cp417 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v194. 6 The wiring path cp418 provided in the wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P39 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT12 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp421. Specifically, it is connected to the via v43 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT12 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 40, the via v43 is connected to the via v90 arranged in the control ROM arrangement area 192 by the wiring path cp422 provided in the fourth wiring layer La4.

The wiring line that reaches the via v90 from the terminal connection portion HDT12 is branched into four by the via v90. As shown in FIG. 35, the first branch path is connected from the via v90 to the terminal connection portion Q12 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp423 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA17 from the via v90 by the wiring path cp424 provided in the sixth wiring layer La6. The other end of the terminating resistor RA17 is connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v90 to the via v150 in the first connector arrangement area 194 by the wiring path cp425 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp426 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt12 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v90 to the via v185 by the wiring path cp427 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v185. 6 The wiring path cp428 provided in the wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring line P40 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT13 provided in the composite chip arrangement region 191 of the first wiring layer La1 is provided on the outside of the composite chip arrangement region 191 by the wiring path cp431. Specifically, it is connected to the via v42 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT13 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 40, the via v42 is connected to the via v89 arranged in the control ROM arrangement area 192 by the wiring path cp432 provided in the fourth wiring layer La4.

The wiring line that reaches the via v89 from the terminal connection portion HDT13 is branched into four by this via v89. As shown in FIG. 35, the first branch path is connected from the via v89 to the terminal connection portion Q13 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp433 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA17 from the via v89 by the wiring path cp434 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v89 to the via v149 in the first connector arrangement area 194 by the wiring path cp435 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp436 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt13 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v89 to the via v186 by the wiring path cp437 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v186. 6 The wiring path cp438 provided in the wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring line P41 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT14 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp441. It is connected to the via v22. The via v22 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT14) arranged around the via v22. As shown in FIG. 40, the via v22 is connected to the via v88 arranged in the control ROM arrangement area 192 by the wiring path cp442 provided in the fourth wiring layer La4.

The wiring line that reaches the via v88 from the terminal connection portion HDT14 is branched into four by this via v88. As shown in FIG. 35, the first branch path is connected from the via v88 to the terminal connection portion Q14 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp443 provided in the first wiring layer La1. Has been done. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA17 from the via v88 by the wiring path cp444 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v88 to the via v148 in the first connector arrangement area 194 by the wiring path cp445 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp446 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt14 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v88 to the via v187 by the wiring path cp447 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v187. 6 The wiring path cp448 provided in the wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring line P42 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT15 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring line cp451. It is connected to the via v15. The via v15 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT15) arranged around the via v15. As shown in FIG. 40, the via v15 is connected to the via v87 arranged in the control ROM arrangement area 192 by the wiring path cp452 provided in the fourth wiring layer La4.

The wiring line that reaches the via v87 from the terminal connection portion HDT15 is branched into four by the via v87. As shown in FIG. 35, the first branch path is a control ROM arrangement area 192 from the via v87 to the terminal connection portion Q15 / A-1 of the control ROM 105 by the wiring path cp453 provided in the first wiring layer La1. It is connected from the inside of. Further, as shown in FIG. 41, the second branch path is connected to the terminating resistor RA17 from the via v87 by the wiring path cp454 provided in the sixth wiring layer La6.

Further, as shown in FIGS. 37 and 38, the third branch path is connected from the via v87 to the via v147 in the first connector arrangement area 194 by the wiring path cp455 provided in the third wiring layer La3, and further. As shown in FIG. 42, the wiring path cp456 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt15 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v87 to the via v188 by the wiring path cp457 provided in the third wiring layer La3 as shown in FIGS. 37 and 39, and further, as shown in FIG. 43, the fourth branch path is connected to the via v188. 6 The wiring path cp458 provided in the wiring layer La6 is connected to the decoder IC14.

Subsequently, the wiring paths P43 to P45 connected to the chip select output terminal HCS0, the lead strobe output terminal HRD, and the system reset terminal HREST of the composite chip 104 will be described.

In the wiring line P43 (FIG. 50), as shown in FIG. 34, the terminal connection portion HCS0 provided in the composite chip arrangement area 191 of the first wiring layer La1 is arranged in the vicinity of the diagonally −X + Y direction by the wiring line cp501. It is connected to the via v9, which is branched into two here. The via v9 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HCS0) arranged around the via v9. As shown in FIG. 33, the first branch path in the via v9 is connected to the via v60 arranged in the control ROM arrangement area 192 by the wiring path cp502 provided in the sixth wiring layer La6, and further, FIG. 35. As shown in the above, the wiring path cp503 provided in the first wiring layer La1 is connected to the terminal connection portion CE # from the inside of the control ROM arrangement area 192.

Further, as shown in FIG. 31, the second branch path in the via v9 is connected to the via v173 by the wiring path cp504 provided in the fourth wiring layer La4, and is further branched into two here. As shown in FIG. 33, the second branch path in the via v173 is connected to the via v201 by the wiring path cp505 provided in the sixth wiring layer La6. This via v201 constitutes a test point TP33. Further, as shown in FIG. 28, the branch path of the second b in the via v173 is connected to DC 3.3V (fifth wiring layer La5) via the resistor RA12 by the wiring path cp506 provided in the first wiring layer La1. There is.

In the wiring line P44 (FIG. 50), as shown in FIG. 28, the terminal connection portion HRD provided in the composite chip arrangement region 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp511. It is connected to the placed via v25 and branches into two here. The via v25 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HRD) arranged around the via v25. As shown in FIG. 33, the first branch path in the via v25 is controlled by the wiring path cp512 provided in the sixth wiring layer La6 to the outside of the composite chip placement area 191, specifically to the composite chip placement area 191. It is connected to the via v47 arranged between the ROM arrangement area 192 and further, as shown in FIG. 35, the control ROM is arranged with respect to the terminal connection portion OE # by the wiring path cp513 provided in the first wiring layer La1. It is connected from the outside of the area 192.

Further, as shown in FIG. 30, the second branch path in the via v25 is connected to the via v172 by the wiring path cp514 provided in the third wiring layer La3, and is further branched into two here. As shown in FIG. 30, the second branch path in the via v172 is connected to the via v171 arranged near the outside of the first connector arrangement area 194 by the wiring path cp515 provided in the third wiring layer La3. Further, as shown in FIG. 33, the wiring path cp516 provided in the sixth wiring layer La6 is connected to the terminal connection portion hd from the outside of the first connector arrangement area 194. Further, as shown in FIG. 28, the branch path of the second b in the via v172 is connected to DC 3.3V (fifth wiring layer La5) via the resistor RA8 by the wiring path cp517 provided in the first wiring layer La1. There is.

In the wiring line P45 (FIG. 50), as shown in FIG. 28, the terminal connection portion HREST provided in the composite chip arrangement region 191 of the first wiring layer La1 is located outside the composite chip arrangement region 191 by the wiring path cp521. It is connected to the via v26 arranged on the + X side). The terminal connection portion HRESET is arranged on the outermost peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v26 is connected to the via v202 by the wiring path cp522 provided in the fourth wiring layer La4, and further, as shown in FIG. 33, the via v26 is connected to the wiring path cp523 provided in the sixth wiring layer La6. It is connected to the via v174 by, and here it branches into two.

As shown in FIG. 33, the first branch path in the via v174 is located in the via v108 arranged near the outside (+ X side) of the control ROM arrangement area 192 by the wiring path cp524 provided in the sixth wiring layer La6. It is connected, and as shown in FIG. 35, it is connected to the terminal connection portion SETT # from the inside of the control ROM arrangement area 192 by the wiring path cp525 provided in the first wiring layer La1. As shown in FIG. 33, the wiring path cp524 of the sixth wiring layer La6 is connected to DC 3.3V (fifth wiring layer La5) via the resistor R40, and is grounded (second wiring layer) via the capacitor C151. It is connected to La2).

Further, as shown in FIG. 28, the second branch path in the via v174 is connected to the via v204 by the wiring path cp526 provided in the first wiring layer La1. The via v204 constitutes a test point TP17. And the via v204 is connected to the reset circuit on the 6th wiring layer La6 side. That is, as shown in FIG. 33, the via v204 is connected to the resistor built-in transistor T1 by the wiring path cp527 provided in the sixth wiring layer La6, further connected to the logic integrated circuit IC7 by the wiring path cp528, and further connected to the logic integrated circuit IC7 by the wiring path cp528. It is connected to the WDT built-in reset integrated circuit (reset IC) IC 10 via the via v203 constituting the test point TP23. The wiring path cp528 is connected to DC 3.3V (fifth wiring layer La5) via the resistor R19, and the wiring path cp529 is connected to the ground (second wiring layer La2) via the capacitor C40 and the resistor R26. It is connected to DC 3.3V (fifth wiring layer La5) via each.

The reset circuit on the side of the sixth wiring layer La6 is configured as shown in FIG. 55. A system reset signal can be input to the logic integrated circuit IC7 via the liquid crystal control first connector CN31, and a reset signal can be input from the WDT built-in reset integrated circuit (reset IC) IC10. When a signal is input, a reset signal is transmitted to the composite chip 104 and the control ROM 105 via the resistor built-in transistor T1 for noise suppression. The LED data output terminal ASIBLDTB of, for example, the composite chip 104 is connected to the WDT built-in reset integrated circuit (reset IC) IC 10 for WDT reset.

Here, the test point TP23 is for checking when the reset integrated circuit IC10 is activated, and as shown in FIG. 33, on the wiring path cp421 on the sixth wiring layer La6 side and in the vicinity of the reset integrated circuit IC10. The display of "TP23", which is the identification information indicating the test point TP23, is arranged on the 6th wiring layer La6 side where the wiring path cp421 is provided, that is, on the back surface 98b side by silk printing. Is normal. On the other hand, the check work by the test point TP23 needs to be performed in the state where the board is assembled (see FIGS. 8 and 9) or the board is assembled (installed) in the main body of the gaming machine. The back surface 98b of the 98 is behind the opposite effect interface board 96 and the liquid crystal interface board 97, and the tester cannot be applied. Therefore, in the present embodiment, as shown in FIG. 56, the display of "TP23", which is the identification information indicating the test point TP23, is displayed on the front surface instead of the wiring path cp421 side where the test point TP23 is arranged, that is, the back surface 98b side. It is located on the 98a side. Since the test point TP23 is composed of the via v203 penetrating the substrate body 190, the tester can be applied from the surface 98a side of the substrate body 190 as well.

Further, the test point TP17 is provided in the via v204 connecting the wiring path cp418 on the first wiring layer La1 side and the wiring path cp419 on the sixth wiring layer La6 side, and the identification information indicating the test point TP17 is provided. The display of "TP17" is also arranged on the surface 98a side like the test point TP23.

The same applies to the other test points TP28 and TP33 described above. That is, the test point TP28 is provided on the wiring path cp3 of the third wiring layer La3, and the display of "TP28", which is the identification information indicating the test point TP28, is arranged on the surface 98a side. Further, the test point TP33 is provided on the wiring path cp505 of the sixth wiring layer La6, and the display of "TP33", which is the identification information indicating the test point TP33, is arranged on the surface 98a side.

Subsequently, the wiring lines P46 and P47 connected to the 8/16 bit mode selection terminal BYTE #, the writable input terminal WE #, and the write-protected / program input terminal WP # / ACC of the control ROM 105 will be described. These wiring lines P46 and P47 are not connected to the composite chip 104.

In the wiring line P46 (FIG. 50), as shown in FIG. 35, the terminal connection portion BYTE # provided in the control ROM arrangement area 192 of the first wiring layer La1 is connected to the via v48 by the wiring line cp531. This via v48 is arranged in the vicinity of the terminal connection portion BYTE # on the outside (-X side) of the control ROM arrangement area 192, and as shown in FIG. 32, is connected to DC 3.3V via the fifth wiring layer La5. It is connected. As described above, in the present embodiment, the 16-bit communication mode is selected by connecting the 8/16 bit mode selection terminal BYTE # of the control ROM 105 to the power supply (H level).

In the wiring line P47 (FIG. 50), as shown in FIG. 35, the terminal connection portion WE # (first predetermined terminal) provided in the control ROM arrangement area 192 of the first wiring layer La1 has a via v111 by the wiring path cp541. Is connected to. The via v111 (first predetermined interlayer conduction portion) is arranged in the vicinity of the terminal connection portion WE # on the outside (+ X side) of the control ROM arrangement region 192, and as shown in FIG. 32, the fifth wiring layer La5. It is connected to DC 3.3V via. As described above, in the present embodiment, since the writable input terminal WE # of the control ROM 105 is connected to the power supply (H level), the output impossible mode and the L level (when reading) are used at the H level (when not reading). ) Is set to the output mode, and the mode can be switched according to the value (H / L) of the outputable input terminal OE #. The outputable input terminal OE # is connected to the lead strobe output terminal HRD of the composite chip 104 as described above.

Further, in the wiring path P47, as shown in FIG. 35, the terminal connection portion WP # / ACC (second predetermined terminal) provided in the control ROM arrangement area 192 of the first wiring layer La1 is connected to the via v112 by the wiring path cp542. It is connected. The via v112 is arranged in the vicinity of the terminal connection portion WP # / ACC on the outside (+ X side) of the control ROM arrangement area 192. Further, as shown in FIG. 33, the via v112 (second predetermined interlayer conduction portion) is connected to the via v111 via the resistor R43 by the wiring path cp543 provided in the sixth wiring layer La6. The via v111 is connected to DC 3.3V via the fifth wiring layer La5 as described above. As described above, in the present embodiment, the write-protected / program input terminal WP # / ACC of the control ROM (specific electronic component) 105 is connected to the power supply (H level), so that the control ROM (specific electronic component) 105 is set to be writable and program executable. ing. Further, by connecting to the power supply via the resistor R43, the input exceeding the H level is eliminated so that the H level can be stably obtained.

For example, depending on the type of control ROM, when there is an input exceeding the H level and a mode setting different from write prohibition / permission and program execution prohibition / permission is performed, the mode is set via a resistor in this way. By configuring it to be stable at H level, even if the input exceeds the H level due to noise etc., the control ROM is set to a mode different from write prohibition / permission and program execution prohibition / permission. It is possible to prevent this from happening.

Subsequently, by connecting the decoder IC 13 and the liquid crystal control second connector CN32, wiring for transmitting the power supply control signal PS1, PS2, the backlight ON / OFF control signal XSTABY1, and the backlight dimming PWM signal VBR1 respectively. Roads P48 to P51 will be described. The connection between the data input / output terminals HDT0 to HDT7 of the composite chip 104 and the decoder IC13 has already been described as wiring lines P27 to P34 (FIG. 48). Further, in the liquid crystal control second connector CN32, a large number of terminals are arranged in two rows along the longitudinal direction (X direction), and the connector terminals ps1, ps2, xstaby1, vbr1 are in the second connector arrangement area 195. -Arranged along the second edge portion 195b on the Y side.

The wiring line P48 (FIG. 51) transmits the power supply control signal PS1. As shown in FIG. 43, the wiring line cp551 is pulled out from the decoder IC 13 of the sixth wiring layer La6 to the −Y side and connected to the via v211. Has been done. As shown in FIG. 30, the via v211 is connected to the via v212 via a wiring path cp552 arranged in the third wiring layer La3. Then, as shown in FIG. 44, the via v212 is formed in the second connector arrangement area 195 with respect to the terminal connection portion ps1 of the liquid crystal control second connector CN32 via the wiring path cp553 arranged in the sixth wiring layer La6. It is connected from the outside (-Y side).

The wiring line P49 (FIG. 51) transmits the power supply control signal PS2. As shown in FIG. 43, the wiring line cp561 is pulled out from the decoder IC 13 of the sixth wiring layer La6 to the −Y side and connected to the via v221. Has been done. As shown in FIG. 30, the via v221 is connected to the via v222 via a wiring path cp562 arranged in the third wiring layer La3. Then, as shown in FIG. 44, the via v222 has a second connector arrangement area 195 with respect to the terminal connection portion ps2 of the liquid crystal control second connector CN32 via the wiring path cp563 arranged in the sixth wiring layer La6. It is connected from the outside (-Y side).

The wiring line (B wiring line) P50 (FIG. 51) transmits the backlight ON / OFF control signal XSTABY1. As shown in FIG. 43, the wiring line cp571 is −Y from the decoder IC13 of the sixth wiring layer La6. It is pulled out to the side and connected to the via v231. As shown in FIG. 30, the via v231 is connected to the via v232 via a wiring path cp572 arranged in the third wiring layer La3. Then, as shown in FIG. 44, the via v232 of the second connector arrangement area 195 with respect to the terminal connection portion xstaby1 of the liquid crystal control second connector CN32 via the wiring path cp573 arranged in the sixth wiring layer La6. It is connected from the outside (-Y side).

The wiring path (B wiring path) P51 (FIG. 51) transmits the backlight dimming PWM signal VBR1, and as shown in FIG. 43, the wiring path cp581 is −Y from the decoder IC13 of the sixth wiring layer La6. It is pulled out to the side and connected to the via v241. As shown in FIG. 30, the via v241 is connected to the via v242 via a wiring path cp582 arranged in the third wiring layer La3. Then, as shown in FIG. 44, the via v242 is formed in the second connector arrangement area 195 with respect to the terminal connection portion vbr1 of the liquid crystal control second connector CN32 via the wiring path cp583 arranged in the sixth wiring layer La6. It is connected from the outside (-Y side).

Subsequently, the data output terminals RA0 +, RA0-, RA1 +, RA1-, RA2 +, RA2-, RA3 +, RA3-, RACLK +, RACLK- (hereinafter referred to as ODD side data output terminal group) and the liquid crystal control unit of the composite chip 104 are used. Wiring path (first wiring path, instep wiring path) P52 to P61 connecting the two connectors CN32, also data output terminals RB0 +, RB0-, RB1 +, RB1-, RB2 +, RB2-, RB3 +, RB3-, RBCLK +, RBCLK -(Hereinafter referred to as an EVEN side data output terminal group) and the wiring path (second wiring path, instep wiring path) P62 to P71 connecting the liquid crystal control second connector CN32 will be described. The wiring lines P52 to P61 form a first transmission line LVDS1 for transmitting an ODD signal, and the wiring lines P62 to P71 form a second transmission line LVDS2 for transmitting an EVEN signal.

As shown in FIGS. 26B and 36, the ODD side data output terminal group (first chip terminal) of the composite chip 104 is arranged in two rows along the second edge portion 191b of the composite chip arrangement region 191. It is arranged. That is, the data output terminals RA0-, RA1-, RA2-, RACLK-, and RA3- are arranged in the -X direction on the outermost side of the composite chip arrangement area 191 in that order, and the data output terminals are further inside them. RA0 +, RA1 +, RA2 +, RACLK +, and RA3 + are arranged in the −X direction in that order.

Further, as shown in FIGS. 26 (b) and 36, the EVEN side data output terminal group (second chip terminal) of the composite chip 104 is inside the composite chip arrangement area 191 with respect to the ODD side data output terminal group. They are arranged in two rows. That is, the data output terminals RB0-, RB1-, RB2-, RBCLK-, and RB3- are arranged in the -X direction in that order with the GND terminal row sandwiched inside the ODD side data output terminal group, and further, they are arranged in the -X direction. Inside, the data output terminals RB0 +, RB1 +, RB2 +, RBCLK +, and RB3 + are arranged in the −X direction in that order.

Further, as shown in FIGS. 33 and 36, the second connector arrangement area 195 in which the liquid crystal control second connector CN32 is arranged is located on the second edge portion 191b side of the composite chip arrangement area 191 and has the second edge portion 191b. It is arranged in an elongated shape parallel to. In the liquid crystal control second connector CN32, a large number of terminals are arranged in two rows along the longitudinal direction (X direction), and as shown in FIG. 44, the connector terminals ra0- corresponding to the ODD side data output terminal group. , Ra0 +, ra1-, ra1 +, ra2-, ra2 +, raclk-, raclk +, ra3-, ra3 + are arranged in the -X direction along the first edge portion 195a on the -Y side of the second connector arrangement region 195. The connector terminals rb0-, rb0 +, rb1-, rb1 +, rb2-, rb2 +, rbclk-, rbclk +, rb3-, rb3 + corresponding to the EVEN side data output terminal group are the second edge on the + Y side of the second connector arrangement area 195. It is arranged in the −X direction along the portion 195b.

First, the wiring lines (first wiring lines) P52 to P61 (FIG. 52) constituting the first transmission line LVDS1 will be described. In the wiring path P52 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA0- provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring path cp601. It is connected to a via (specific interlayer conduction portion) v251 arranged (near the connector). As shown in FIG. 44, the via v251 is connected to the terminal connection portion ra0- from the inside of the second connector arrangement region 195 by the wiring path cp602 of the sixth wiring layer La6.

In the wiring line P53 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA0 + provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring path cp603 ( It is connected to a via (specific interlayer conduction portion) v252 arranged near the connector). The wiring path cp603 is drawn out of the composite chip arrangement region 191 via between the terminal connection portion RA0- and the terminal connection portion RA1-next to the terminal connection portion RA0-. That is, the two wiring paths cp601 and cp603 constituting the operation signal line RA0 are arranged so as to be adjacent to each other and parallel to each other. Then, as shown in FIG. 44, the via v252 is connected to the terminal connection portion ra0 + from the inside of the second connector arrangement region 195 by the wiring path cp604 of the sixth wiring layer La6.

In the wiring line P54 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA1- provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring path cp605. It is connected to a via (specific interlayer conduction portion) v253 arranged (near the connector). As shown in FIG. 44, the via v253 is connected to the terminal connection portion ra1-from the inside of the second connector arrangement region 195 by the wiring path cp606 of the sixth wiring layer La6.

In the wiring line P55 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA1 + provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring path cp607 ( It is connected to a via (specific interlayer conduction portion) v254 arranged near the connector). The wiring path cp607 is drawn out of the composite chip arrangement region 191 via between the terminal connection portion RA1- and the terminal connection portion RA2- adjacent to the terminal connection portion RA1-. That is, the two wiring paths cp605 and cp607 constituting the operation signal line RA1 are arranged so as to be adjacent to each other and parallel to each other. Then, as shown in FIG. 44, the via v254 is connected to the terminal connection portion ra1 + from the inside of the second connector arrangement region 195 by the wiring path cp608 of the sixth wiring layer La6.

In the wiring line P56 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA2- provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring line cp609. It is connected to a via (specific interlayer conduction portion) v255 arranged (near the connector). As shown in FIG. 44, the via v255 is connected to the terminal connection portion ra2- from the inside of the second connector arrangement region 195 by the wiring path cp610 of the sixth wiring layer La6.

In the wiring line P57 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA2 + provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring line cp611 ( It is connected to a via (specific interlayer conduction portion) v256 arranged near the connector). The wiring path cp611 is drawn out of the composite chip arrangement area 191 via between the terminal connection portion RA2- and the terminal connection portion RACLK- adjacent to the terminal connection portion RA2-. That is, the two wiring paths cp609 and cp611 constituting the operation signal line RA2 are arranged so as to be adjacent to each other and parallel to each other. Then, as shown in FIG. 44, the via v256 is connected to the terminal connection portion ra2 + from the inside of the second connector arrangement region 195 by the wiring path cp612 of the sixth wiring layer La6.

In the wiring line P58 (FIG. 52), as shown in FIG. 36, the terminal connection portion RACLK- provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring path cp613. It is connected to a via (specific interlayer conduction portion) v257 arranged (near the connector). As shown in FIG. 44, the via v257 is connected to the terminal connection portion raclk- by the wiring path cp614 of the sixth wiring layer La6 from the inside of the second connector arrangement region 195.

In the wiring line P59 (FIG. 52), as shown in FIG. 36, the terminal connection portion RACLK + provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring path cp615. It is connected to a via (specific interlayer conduction portion) v258 arranged near the connector). The wiring path cp615 is drawn out of the composite chip arrangement area 191 via between the terminal connection portion RACLK- and the terminal connection portion RA3- adjacent to the terminal connection portion RACLK-. That is, the two wiring paths cp613 and cp615 constituting the operation signal line RACLK are arranged so as to be adjacent to each other and parallel to each other. Then, as shown in FIG. 44, the via v258 is connected to the terminal connection portion raclk + from the inside of the second connector arrangement region 195 by the wiring path cp616 of the sixth wiring layer La6.

In the wiring line P60 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA3- provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring path cp617. It is connected to a via (specific interlayer conduction portion) v259 arranged (near the connector). As shown in FIG. 44, the via v259 is connected to the terminal connection portion ra3- from the inside of the second connector arrangement region 195 by the wiring path cp618 of the sixth wiring layer La6.

In the wiring line P61 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA3 + provided in the composite chip arrangement area 191 of the first wiring layer La1 is provided in the second connector arrangement area 195 by the wiring line cp619. It is connected to a via (specific interlayer conduction portion) v260 arranged near the connector). The wiring path cp619 is drawn out of the composite chip arrangement region 191 via the −X side of the terminal connection portion RA3-. That is, the two wiring paths cp617 and cp619 constituting the operation signal line RA3 are arranged so as to be adjacent to each other and parallel to each other. Then, as shown in FIG. 44, the via v260 is connected to the terminal connection portion ra3 + from the inside of the second connector arrangement region 195 by the wiring path cp620 of the sixth wiring layer La6.

As shown in FIG. 36, in the first wiring layer La1, the operation signal line RA1 is provided between the wiring paths cp601 and cp603 constituting the operation signal line RA0 and the wiring paths cp605 and cp607 constituting the operation signal line RA1. Between the wiring paths cp605 and cp607 constituting the operation signal line RA2 and the wiring paths cp609 and cp611 constituting the operation signal line RA2, the wiring paths cp609 and cp611 constituting the operation signal line RA2 and the wiring paths cp6133 and cp615 constituting the operation signal line RACLK The ground wiring paths pp1 to gp4 are arranged between the wiring paths cp613 and cp615 constituting the operation signal line RACLK and the wiring paths cp617 and cp619 constituting the operation signal line RA3, respectively. The ground wiring lines gp1 to gp4 are formed in an elongated shape having a substantially constant width.

Subsequently, the wiring paths (second wiring path) P62 to P71 (FIG. 53) constituting the second transmission line LVDS2 will be described. In the wiring line P62 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB0- provided in the composite chip arrangement area 191 of the first wiring layer La1 is located near the diagonal + XY direction by the wiring line cp621. It is connected to the via v261 arranged in. The via v261 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB0-) arranged around the via v261. As shown in FIG. 44, the via v261 is connected to the terminal connection portion rb0- by the wiring path cp622 of the sixth wiring layer La6 from the outside of the second connector arrangement region 195.

In the wiring line P63 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB0 + provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp623. It is connected to the placed via v262. The via v262 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB0 +) arranged around the via v262. As shown in FIG. 44, the via v262 is connected to the terminal connection portion rb0 + from the outside of the second connector arrangement region 195 by the wiring path cp624 of the sixth wiring layer La6. The wiring path cp624 is drawn out of the composite chip arrangement region 191 via the + X side of the via v261. That is, the two wiring paths cp622 and cp624 constituting the operation signal line RB0 are arranged so as to be adjacent to each other and parallel to each other.

In the wiring line P64 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB1- provided in the composite chip arrangement area 191 of the first wiring layer La1 is located near the diagonal + XY direction by the wiring line cp625. It is connected to the via v263 arranged in. The via v263 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB1-) arranged around the via v263. As shown in FIG. 44, the via v263 is connected to the terminal connection portion rb1- from the outside of the second connector arrangement region 195 by the wiring path cp626 of the sixth wiring layer La6.

In the wiring line P65 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB1 + provided in the composite chip arrangement region 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp627. It is connected to the placed via v264. The via v264 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB1 +) arranged around the via v264. As shown in FIG. 44, the via v264 is connected to the terminal connection portion rb1 + from the outside of the second connector arrangement region 195 by the wiring path cp628 of the sixth wiring layer La6. The wiring path cp628 is drawn out of the composite chip arrangement region 191 via the via v263 and the via v261 adjacent to the via v263. That is, the two wiring paths cp626 and cp628 constituting the operation signal line RB1 are arranged so as to be adjacent to each other and parallel to each other.

In the wiring line P66 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB2- provided in the composite chip arrangement area 191 of the first wiring layer La1 is located near the diagonal + XY direction by the wiring line cp629. It is connected to the via v265 arranged in. The via v265 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB2-) arranged around the via v265. As shown in FIG. 44, the via v265 is connected to the terminal connection portion rb2- by the wiring path cp630 of the sixth wiring layer La6 from the outside of the second connector arrangement region 195.

In the wiring line P67 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB2 + provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp631. It is connected to the placed via v266. The via v266 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB2 +) arranged around the via v266. As shown in FIG. 44, the via v266 is connected to the terminal connection portion rb2 + from the outside of the second connector arrangement region 195 by the wiring path cp632 of the sixth wiring layer La6. The wiring path cp632 is drawn out of the composite chip arrangement region 191 via the via v265 and the via v263 adjacent to the via v265. That is, the two wiring paths cp630 and cp632 constituting the operation signal line RB2 are arranged so as to be adjacent to each other and parallel to each other.

In the wiring line P68 (FIG. 53), as shown in FIG. 36, the terminal connection portion RBCLK- provided in the composite chip arrangement area 191 of the first wiring layer La1 is located near the diagonal + XY direction by the wiring line cp633. It is connected to the via v267 arranged in. The via v267 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RBCLK-) arranged around the via v267. As shown in FIG. 44, the via v267 is connected to the terminal connection portion rbclk- by the wiring path cp634 of the sixth wiring layer La6 from the outside of the second connector arrangement region 195.

In the wiring line P69 (FIG. 53), as shown in FIG. 36, the terminal connection portion RBCLK + provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp635. It is connected to the placed via v268. The via v268 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RBCLK +) arranged around the via v268. As shown in FIG. 44, the via v268 is connected to the terminal connection portion rbclk + by the wiring path cp636 of the sixth wiring layer La6 from the outside of the second connector arrangement region 195. The wiring path cp636 is drawn out of the composite chip arrangement region 191 via the via v267 and the via v265 adjacent to the via v267. That is, the two wiring paths cp634 and cp636 constituting the operation signal line RBCLK are arranged so as to be adjacent to each other and parallel to each other.

In the wiring line P70 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB3- provided in the composite chip arrangement region 191 of the first wiring layer La1 is located near the diagonal + XY direction by the wiring line cp637. It is connected to the via v269 arranged in. The via v269 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB3-) arranged around the via v269. As shown in FIG. 44, the via v269 is connected to the terminal connection portion rb3- from the outside of the second connector arrangement region 195 by the wiring path cp638 of the sixth wiring layer La6.

In the wiring line P71 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB3 + provided in the composite chip arrangement area 191 of the first wiring layer La1 is located in the vicinity of the diagonal + XY direction by the wiring line cp639. It is connected to the placed via v270. The via v270 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB3 +) arranged around the via v270. As shown in FIG. 44, the via v270 is connected to the terminal connection portion rb3 + from the outside of the second connector arrangement region 195 by the wiring path cp640 of the sixth wiring layer La6. The wiring path cp640 is drawn out of the composite chip arrangement region 191 via the via v269 and the via v267 adjacent to the via v269. That is, the two wiring paths cp638 and cp640 constituting the operation signal line RB3 are arranged so as to be adjacent to each other and parallel to each other.

In the sixth wiring layer La6, as shown in FIG. 44, the operation signal line RB1 is provided between the wiring paths cp622 and cp624 constituting the operation signal line RB0 and the wiring paths cp626 and cp628 constituting the operation signal line RB1. Between the wiring paths cp626 and cp628 constituting the operation signal line RB2 and the wiring paths cp630 and cp632 constituting the operation signal line RB2, the wiring paths cp630 and cp632 constituting the operation signal line RB2 and the wiring paths cp634 and cp636 constituting the operation signal line RBCLK. The ground wiring paths pp11 to gp14 are arranged between the wiring paths cp634 and cp636 constituting the operation signal line RBCLK and the wiring paths cp638 and cp640 constituting the operation signal line RB3, respectively. The ground wiring lines gp11 to gp14 are formed in an elongated shape having a substantially constant width.

As described above, in the wiring patterns shown in FIGS. 36 and 44, the ground wiring lines gp1 to gp4 and gp11 to gp14 are arranged between the wiring path pairs of a plurality of sets (5 sets each) constituting the operation signal line. However, this is to reduce noise to the wiring lines cp601, cp622 and the like around the ground wiring lines gp1 to gp4 and gp11 to gp14. As shown in FIGS. 36 and 44, it is desirable that the ground wiring lines gp1 to gp4 and gp11 to gp14 have a wider width than the surrounding wiring lines cp601 and cp622. This is because the surrounding wiring lines cp601, cp622, etc. are wiring lines for transmitting image data, so that the design is more resistant to noise so that the design image on the screen is not difficult to see due to noise. ..

Further, as shown in FIGS. 36 and 44, the ground wiring lines gp1 to gp4 on the first wiring layer La1 side and the ground wiring lines gp11 to gp14 on the sixth wiring layer La6 side have a plurality of through holes (vias), respectively. They are connected to each other via the above, which makes it possible to further reduce noise.

Further, as shown in FIGS. 36 and 44, the ground wiring lines gp1 to gp4 on the first wiring layer La1 side and the ground wiring lines gp11 to gp14 on the sixth wiring layer La6 side are different from each other depending on the surrounding wiring pattern. Although it has a shape, it is configured to partially pass through points (regions) corresponding to each other, and is connected via through holes (vias) at the corresponding points (here, each of multiple points). It is possible to make the wiring pattern more resistant to noise and more efficient while adopting the shape according to the surrounding wiring pattern.

Summarizing the configurations of the wiring lines P1 to P71 described above, first, among the wiring lines P2 to P45 connecting the composite chip 104 and the control ROM 105, the wiring lines P2 to P43 and P45 (specific wiring lines) are shown in FIG. 35. , As shown in FIGS. 45 to 50, vias v60 to v108 (specific interlayer conduction portion; vias shown in gray in FIGS. 45 to 50) arranged in the control ROM arrangement area (second arrangement area) 192 are It is connected to the terminal connection part on the control ROM 105 side, and the wiring paths P2 to P16, P19 to P23, P35 to P43, and P45 (first specific wiring path) among them are connected to the terminals on the control ROM 105 side. Parts A0 to A14, A17 to A21, Q8 to Q15, CE #, and SETET # are connected from the inside of the control ROM arrangement area 192 (wiring lines shown by thick lines in FIGS. 45 to 50). In this way, the wiring path connecting the composite chip 104 and the control ROM 105 is arranged so as to pass through the control ROM arrangement area 192 having a relatively large space, and the terminals of the control ROM 105 are arranged as much as possible. By connecting from the inside of the control ROM arrangement area 192, the wiring pattern on the board can be arranged more efficiently, and the limited space can be used more effectively.

Wiring connected from the outside of the control ROM arrangement area 192 to the terminal connection portion on the control ROM 105 side from the vias v60 to v108 (specific interlayer conduction portion) arranged in the control ROM arrangement area (second arrangement area) 192. As for the road, specifically, the wiring line cp165, cp175, cp234, cp244, cp254, cp343, cp353, cp3633, cp373, cp303, cp313, cp323, cp333, as shown in FIG. 35, the length of the control ROM arrangement area 192. The sides 192a and 192b are arranged so as to cross the outside of each terminal connection portion. With such a configuration, the wiring length can be shortened as compared with the case of wiring avoiding the control ROM arrangement area 192, so that the wiring efficiency can be improved and noise can be reduced. Further, in the range shown in the control ROM arrangement area 192, since the control ROM 105 is actually located, the wiring pattern cannot be visually observed, and thus it is possible to prevent unauthorized access to the wiring pattern. It is possible.

Further, a wiring line connected by the first wiring layer La1 to the vias v60 to v108 (specific interlayer conduction portion) arranged in the control ROM arrangement area (second arrangement area) 192, specifically, the wiring path cp233. , Cp243 and cp253 are also arranged so as to cross the long side 192a of the control ROM arrangement area 192 on the outside of each terminal connection portion, as shown in FIG. By making such a configuration at a plurality of places in combination with the configuration of the previous stage, the effect described in the previous stage becomes more effective.

Further, the ROM socket 193 (FIG. 8) is fixed to the control ROM arrangement area 192, and the bottom wall (shielding wall corresponding to the specific interlayer conduction portion) 193a of the ROM socket 193 shields the control ROM arrangement area 192. Even when the control ROM 105 is removed from the ROM socket 193, the wiring pattern in the control ROM arrangement area 192 including the vias v60 to v108 (specific interlayer conduction portion) cannot be visually recognized from the outside and cannot be accessed.

The vias v60 to v108 (specific interlayer conduction portions) in the control ROM arrangement area 192 penetrate from the front surface (first surface) 98a to the back surface (second surface) 98b of the substrate main body 190 to enhance the heat dissipation effect. Further, the vias v60 to v108 (specific interlayer conduction portion) in the control ROM arrangement area 192 are connected to predetermined electronic components such as ICs, resistors, capacitors, and connectors on the back surface 98b side, that is, the sixth wiring layer La6 side. ..

Further, regarding the wiring paths P2 to P45 connecting the composite chip 104 and the control ROM 105, the predetermined via and the control ROM 105 are connected from the first wiring portion connecting the composite chip 104 and the predetermined via (predetermined interlayer conduction portion). It is branched into a second wiring part for connecting the above and a third wiring part for connecting a predetermined via and another electronic component such as the liquid crystal control first connector CN31. Then, the second wiring portion is in the first predetermined wiring layer such as the first wiring layer La1, and the third wiring portion is in the second predetermined wiring layer La3, the sixth wiring layer La6, etc., which is different from the first predetermined wiring layer. It is arranged in each wiring layer.

Further, among the wiring paths P2 to P45, in the wiring paths P2 to P42 for transmitting address / data information, a predetermined via (predetermined interlayer conduction portion), which is a branching point, is a control ROM arrangement area (second arrangement area). ) It is a specific interlayer conduction portion (vias shown in gray in FIGS. 45 to 50) arranged in 192, and the second wiring portion is attached to the first wiring layer La1 and at least a part of the first wiring portion. Is provided in the fourth wiring layer La4 (an example of a predetermined wiring layer different from the first wiring layer), and the third wiring portion is provided in the first wiring layer La1 (first predetermined wiring layer). This makes it possible to improve the preventiveness against goto acts such as unauthorized modification of wiring patterns and vias that transmit address / data information. Further, by drawing a wiring pattern in the control ROM arrangement area 192, it is possible to secure a wiring space in other areas. Further, especially with respect to the branching point, since the wiring pattern tends to be densely distributed over a plurality of layers of the board, a sufficient wiring space is required in the portion where the branching point is provided, but from that point as well, there is a margin in the wiring space. It is effective to arrange the branch point in the control ROM arrangement area 192 with a certain area.

Further, among the vias v60 to v107 (specific interlayer conduction portion) in the control ROM arrangement area 192, the vias v61 to v85 and v103 constituting a part of the wiring paths P2 to P26 (address wiring) for transmitting the address information. -V107 (first specific interlayer conductive portion) and vias v87 to v102 (second specific interlayer conductive portion) constituting a part of wiring paths P27 to P42 (data wiring) for transmitting data information are controlled. The terminals are arranged in the Y direction (first direction), which is the arrangement direction of the terminals in the ROM 105.

Further, the address output terminals HAD1 to HAD25 on the composite chip 104 side, the data input / output terminals HDT0 to HDT15 (first terminal), and the corresponding address input terminals A0 to A24 on the control ROM 105 side, and the data input / output terminals Q0 to Q15. The arrangement is different from that of (second terminal), and the wiring paths P2 to P42 connecting them have vias v60 to v85 and v87 to v107 (specific interlayer conduction portion) in the control ROM arrangement area 192. The arrangement of vias v60 to v85 and v87 to v107 (specific interlayer conduction portion) in the control ROM arrangement area 192 is approximated to the arrangement of the corresponding terminals (specific second terminal) on the control ROM 105 side. As a result, the wiring pattern connecting the specific interlayer conduction portion and the terminal of the control ROM can be organized, and it is not necessary to route the pattern so that the positional relationship between the plurality of wiring patterns changes (twists), for example. Therefore, the connection method is easier, and the space in the control ROM arrangement area 192 can be used more effectively. In this way, when the terminal arrangement of the composite chip 104 and the terminal arrangement of the control ROM 105 are different, a wiring pattern having a relatively short wiring distance from the specific interlayer conduction portion in the arrangement area of the control ROM 105 to the terminal of the control ROM 105. Rather than devising the routing of the specific interlayer conduction portion, by devising the routing of the wiring pattern having a relatively long wiring distance from the composite chip 104 to the specific interlayer conduction portion, the arrangement of the specific interlayer conduction portion is approximated to the terminal arrangement of the control ROM 105. Can be said to be more effective in terms of wiring efficiency.

Specifically, as shown in FIG. 35, for example, address input terminals A0 to A6 and corresponding vias v85 to v79, address input terminals A17 to A20 and corresponding vias v68 to v64, and data input / output terminals Q12 to Q15. And the corresponding vias v90 to v87 are arranged in substantially the same order in the Y direction, respectively, and the address input terminals A23, A22, A24, A16, A15 and the corresponding vias v62, v63, v61, v103, v104. , Data input / output terminals Q0 to Q3 and corresponding vias v102 to v99, data input / output terminals Q8 to Q11 and corresponding vias v94 to v91, data input / output terminals Q4 to Q7 and corresponding vias v98 to v95. , Each is arranged in the Y direction in substantially the reverse order. In this way, instead of devising the arrangement of the specific interlayer conduction part in consideration of only the terminal arrangement of the control ROM 105, the terminal arrangement on the composite chip 104 side and the terminal arrangement on the liquid crystal control first connector CN31 side which are also connected. In consideration of the above, the specific interlayer conductive portions may be arranged. This partially complicates the connection relationship with the control ROM 105, but the composite chip 104 located farther than the terminal of the control ROM 105 and the liquid crystal control first connector CN31 side with respect to the specific interlayer conduction portion. Since the connection relationship with the terminals is simplified, it is possible to improve the wiring efficiency of the entire board. That is, the wiring efficiency of the entire substrate can be improved by devising the arrangement of the specific interlayer conduction portions in the control ROM arrangement area 192 as necessary. Further, the wiring efficiency of the entire board can be improved not only in the control ROM arrangement area 192 but also by devising the arrangement of the vias serving as branch points as described above.

Further, the address output terminals HAD1 to HAD25 and the data input / output terminals HDT0 to HDT15 (first terminal) on the composite chip 104 side are the address input terminals A0 to A24 and the data input / output terminals Q0 to Q15 on the control ROM 105 side corresponding to them. The arrangement is different not only from (second terminal) but also from each terminal had1 to had25 and hdt0 to hdt15 (third terminal) of the liquid crystal control first connector CN31, and via v61 to v85 and v87 to v102 (specific interlayer conduction). The arrangement of (part) is matched (approximate) with the arrangement of each terminal had1 to had25 and hdt0 to hdt15 (third terminal) of the liquid crystal control first connector CN31. That is, as shown in FIGS. 37, 38, and 42, the arrangement of the vias v61 to v85 and v87 to v102 (specific interlayer conduction portions) in the Y direction is arranged from each terminal had1 to the corresponding liquid crystal control first connector CN31. Since it matches the arrangement of had25 and hdt0 to hdt15 in the X direction, the wiring path group (third wiring path group) connecting them can be arranged in parallel without twisting. As a result, the wiring path group (second terminal) connecting the vias v61 to v85, v87 to v102 (specific interlayer conduction portion), the address input terminals A0 to A24 on the control ROM 105 side, and the data input / output terminals Q0 to Q15 (second terminal) ( The second wiring path group) has a complicated wiring pattern including twist, but this can be easily realized by arranging it in the control ROM arrangement area 192 having a relatively large space.

Of the wiring paths P2 to P42 that transmit address / data information, the wiring paths P2 to P13 and P19 to P42 have vias v61 to v68, v74 to v85, and v87 to v102 in the control ROM arrangement area 192. The control ROM 105 side and the liquid crystal control first connector CN31 side are branched in the specific interlayer conduction portion), but the wiring paths P14 to P18 are on the control ROM 105 side in the vias v69 to v73 in the control ROM arrangement area 192. Vias v103 to v107 are separately provided in the control ROM arrangement area 192 on the wiring path connecting the vias v69 to v73 and the liquid crystal control first connector CN31 without branching, and the vias v103 to v107 branch to the control ROM 105 side. ing. With this configuration, the wiring to the liquid crystal control first connector CN31 is arranged in parallel without twisting in harmony with other wiring lines, and the wiring to the control ROM 105 also interferes with other wiring lines. It is possible to arrange efficiently while avoiding it.

In addition, the specific one-end side terminals A0 to A7, A17, A18, A20, A21, Q0 to Q3, Q8 to Q11 included in the one-end side terminals arranged on one end side of the control ROM (second electronic component) 105 and those. The first specific terminals HAD0 to HAD7, HAD17, HAD18, HAD20, HAD21, HDT0 to HDT3, HDT8 to HDT11 on the corresponding composite chip (first electronic component) 104 side are via v65 to v68, v78 to v85, v91 to v94. , V99 to v102 (first interlayer conduction portion), and a plurality of one-end side wiring paths P2 to P9, P19, P20, P22, P23, P27 to P30, P35 to P38, and a control ROM (second electron). (Parts) Specific other end side terminals A8 to A16, A19, A22 to A24, Q4 to Q7, Q12 to Q15 included in the other end side terminal arranged on the other end side of 105, and a composite chip corresponding to them (first). Electronic components) The second specific terminals HAD8 to HAD16, HAD19, HAD22 to HAD24, HDT4 to HDT7, HDT12 to HDT15 on the 104 side are via v61 to v63, v66, v74 to v77, v87 to v90, v95 to v98 (second). It is provided with a plurality of wiring paths P10 to P18, P21, P24 to P26, P31 to P34, P39 to P42 connected to each other via the interlayer conduction portion), and the first interlayer conduction portion and the second interlayer conduction portion. Are arranged in a different arrangement from the first specific terminal and the second specific terminal, respectively, and are arranged close to each other so as to have an arrangement corresponding to the specific end side terminal and the specific end side terminal.

Further, the inner connection wiring portion connected from the inside of the control ROM arrangement area 192 and the outer connection wiring portion connected from the outside are alternately arranged with respect to the plurality of ROM terminal connection portions arranged in a row. That is, as shown in FIG. 35, for the terminal connection portions Q0, Q8, Q1, Q9, Q2, Q10, Q3, and Q11 of the control ROM arrangement area 192, the external connection wiring portions cp303, cp313, cp323, and cp333 are included. The connection wiring portions cp3833, cp393, cp403, and cp413 are alternately connected. Moreover, the vias v102 to v99 on the other end side of the outer connection wiring portions cp303, cp313, cp323 and cp333 are arranged close to each other, and the vias v94 to v91 on the other end side of the inner connection wiring portions cp3833, cp393, cp403 and cp413 are arranged close to each other. Are also located close to each other. Similarly, the terminal connection portions Q15 / A-1, Q7, Q14, Q6, Q13, Q5, Q12, and Q4 of the control ROM arrangement area 192 are externally connected to the internal connection wiring portions cp453, cp443, cp433, cp423. The wiring portions cp3733, cp363, cp353, and cp343 are alternately connected. Moreover, the vias v87 to v90 on the other end side of the internal connection wiring portions cp453, cp443, cp433, cp423 are arranged close to each other, and the vias v95 to v98 on the other end side of the external connection wiring portions cp3733, cp3633, cp353, cp343 are arranged close to each other. Are also located close to each other. In this way, by arranging and grouping the inner connection wiring portion and the outer connection wiring portion in the vicinity instead of the terminal arrangement of the control ROM 105, the wiring pattern can be simplified and the wiring efficiency can be improved. ..

Further, the first wiring paths P2 to P42 for transmitting address information or data information and the second wiring path P43 for transmitting chip select information are different wiring layers, that is, the first wiring layers P2 to P42 are the fourth wiring. The layers La4 and the second wiring path P43 are connected to the vias v61 to v85, v87 to v101, and v60 (specific interlayer conduction portions) in the control ROM arrangement area 192 from the composite chip 104 side in the sixth wiring layer La6. In this way, by wiring the chip select signal, which is important in data transmission, using a wiring layer different from the wiring pattern for transmitting the address information or data information, the transmission of the wiring pattern for transmitting the address information or the data information is performed. It is possible to make it difficult for noise to get on the chip select signal, and it is possible to make a configuration that is resistant to noise. In addition, by making the wiring path pattern of the chip select signal different from other wiring paths, it becomes relatively easy to identify the wiring of the chip select signal, and whether the wiring pattern is short-circuited or not. Checks and energization checks can be performed relatively easily.

Further, in the wiring path P45 constituting the reset circuit, the wiring paths cp418 to cp421 (reset first wiring path) connecting the reset integrated circuit (reset IC) IC10 and the via v174 (predetermined interlayer conduction portion) and the via v174. The wiring paths cp413 to cp415 (reset second wiring path) connecting the (predetermined interlayer conduction section) and the reset terminal HSET of the composite chip 104, the via v174 (predetermined interlayer conduction section), and the reset terminal SETT # of the control ROM 105 are connected. A test point TP17 (first) that is provided with wiring paths cp416 and cp417 (reset third wiring path) to be connected and penetrates the liquid crystal control board 98 in the plate thickness direction on the wiring paths cp418 to cp421 (reset first wiring path). A test point) and a test point TP23 (second test point) are arranged, and the identification information "TP17" and "TP23" indicating the test points TP17 and TP23 are used, the liquid crystal control board 98 is used as another effect interface board 96, and the liquid crystal interface. When assembled together with the substrate 97 and the like, it is displayed on the front side, that is, the surface (first surface) 98a on the side opposite to the substrates 96 and 97. The reset integrated circuit (reset IC) IC10 is arranged on the back surface (second surface) 98b side. As a result, when the board is assembled (see FIGS. 8 and 9) or when the board is assembled (installed) on the main body of the gaming machine, the portion of the wiring path where the test points TP17 and TP23 are arranged cannot be visually recognized. Nevertheless, it is possible to easily perform the check work by the test points TP17 and TP23 based on the identification information displayed on the visible surface 98a side.

Further, the wiring paths cp418 to cp421 (reset first wiring path) are arranged on the wiring path cp418 (first wiring path) arranged on the front surface (first surface) 98a side and on the back surface (second surface) 98b side. It has wiring lines cp420 and cp421 (second wiring line) and via v204 (reset first interlayer conduction portion) connecting them, and a test point TP17 (first test point) is placed on the via v204 for testing. The point TP23 (second test point) is arranged on the wiring path cp421 (second wiring path).

Further, the control ROM (specific electronic component) 105 operates in an operation mode corresponding to the voltage level of the write-protected / program input terminal WP # / ACC (second predetermined terminal), and the writable input terminal WE # (first). The predetermined terminal) is connected to the power supply wiring path of the fifth wiring layer La5 via the via v111 (first predetermined interlayer conduction portion), and the write-protected / program input terminal WP # / ACC (second predetermined terminal) is a resistor. It is connected to via v111 (first predetermined interlayer conduction portion) via R43. Further, a control ROM (specific electronic component) 105 is arranged on the front surface (first surface) 98a of the liquid crystal control substrate 98, and a resistor R43 is arranged on the back surface (second surface) 98b, respectively, and via v112 (second predetermined interlayer conduction portion). The write-protected / program input terminal WP # / ACC (second predetermined terminal) and the resistor R43 are connected to each other via. In this way, the via that connects the WP # / ACC (second predetermined terminal) to the power supply wiring line via the resistor R43 is common as the via that connects the WE # (first predetermined terminal) to the power supply wiring path. It is possible to reduce the number of vias as compared with the case of connecting individually via vias.

Further, a plurality of terminals are arranged in a matrix on the bottom surface side of the composite chip 104, and among the plurality of terminals, an outer terminal arranged in the vicinity of the outer periphery of the composite chip placement region (first placement region) 191. For example, the terminals HDT0, HDT1, HDT4, HDT5 and the like arranged on the outermost peripheral side and the second row inside the outermost peripheral side are connected to the control ROM 105 by the first wiring lines P27, P28, P31, P32 and the like, and are inside the outer terminal. The inner terminals to be arranged, for example, the terminals HDT2, HDT3, HDT6 and the like are connected to the control ROM 105 by the second wiring lines P29, P30, P33 and the like, and the first wiring lines P27, P28, P31, P32 and the like are the composite chip arrangement area. Vias v32, v31, v37, v46, etc. (first interlayer conduction portion) arranged outside 191 and outer terminals HDT0, HDT1, HDT4, HDT5, etc. are connected by the first wiring layer La1 and the second wiring path P29. , P30, P33, etc. connect the vias v24, v8, v17, etc. (second interlayer conduction portion) arranged inside the composite chip arrangement region 191 and the inner terminals HDT2, HDT3, HDT6, etc. with the first wiring layer La1. is doing. Further, the distance from the inner terminals HDT2, HDT3, HDT6, etc. to the vias v24, v8, v17, etc. (second interlayer conduction portion) is set, and the distances from the outer terminals HDT0, HDT1, HDT4, HDT5, etc. It is shorter than the distance to (the first interlayer conductive part).

In the composite chip 104 in which a plurality of terminals are arranged in a matrix in this way, the outer terminals arranged near the outer periphery of the arrangement region of the composite chip 104 are connected to the vias arranged outside the composite chip 104. Therefore, a wiring space is created in the vicinity of the outer periphery of the composite chip 104, and the wiring pattern of the inner terminal of the composite chip 104 can be easily routed to the outside of the composite chip, so that the wiring efficiency can be improved. Further, regarding the above-mentioned wiring space, since the wiring space near the outer periphery of the composite chip is generated in the plurality of wiring layers of the board, no matter which wiring layer among the plurality of wiring layers is used, the wiring space is outside the composite chip. Needless to say, it becomes easier to wire the wiring pattern.

Further, the wiring paths (first wiring paths) P52 to P61 for transmitting the ODD signal (first signal) corresponding to the odd pixels are connected to the first wiring layer (instep wiring layer) La1 among the plurality of wiring layers La1 to La6. Wiring to the 6th wiring layer (B wiring layer) La6 of the plurality of wiring layers La1 to La6, which is arranged so that the wiring ratio of is the highest and transmits the EVEN signal (second signal) corresponding to even pixels. It is arranged so that the ratio is the highest.

That is, the ODD side data output terminal group (first chip terminal) to which the wiring line (first wiring line) P52 to P61 is connected is the EVEN side data output to which the wiring line (second wiring line) P62 to P71 is connected. The liquid crystal control second connector CN32 is arranged on the outer peripheral side of the composite chip 104 with respect to the terminal group (second chip terminal), and is arranged on the sixth wiring layer (B wiring layer) Lb6 side opposite to the composite chip 104. There is. The wiring paths (first wiring paths) P52 to P61 connected to the ODD side data output terminal group (first chip terminal) are vias (specific interlayer conduction portions) arranged in the vicinity of the liquid crystal control second connector CN32. ) The EVEN side data output terminal group (second chip terminal) connected to the liquid crystal control second connector CN32 via v251 to v260 and connected to the EVEN side data output terminal group (second chip terminal) is the EVEN side data. It is connected to the liquid crystal control second connector CN32 via vias (non-specific interlayer conduction portions) v261 to v270 arranged in the vicinity of the output terminal group. With such a configuration, the wiring paths (first wiring path) P52 to P61 for transmitting the ODD signal (first signal) and the wiring paths (second wiring path) P62 to P7 for transmitting the EVEN signal (second signal). At the same time, it is possible to reduce the possibility of problems due to disconnection and noise, and to disperse the risk.

Further, the liquid crystal control second connector CN32 is arranged on the second edge portion (first side) 191b side with respect to the composite chip 104, and the wiring path (instep wiring path) P52 capable of transmitting the image data signal to the liquid crystal display means 76. ~ P71 is drawn from the second edge portion (first side) 191b side of the composite chip 104 and connected to the first connector terminal of the liquid crystal control second connector CN32, and is a wiring path capable of transmitting a control signal related to the backlight. B wiring path) P50 and P51 are drawn out from the first edge portion (second side) 191a side of the composite chip 104 and connected to the second connector terminal of the liquid crystal control second connector CN32. As a result, while shortening the wiring length of the wiring path (A wiring path) P52 to P71, the wiring path (A wiring path) P52 to P71 and the wiring path (B wiring path) P50 and P51 are separated for efficiency. Wiring is possible.

Subsequently, the details such as the wiring pattern of the liquid crystal interface board 97 will be described. The liquid crystal interface board 97 has a plurality of wiring layers on the board body 220 (see FIG. 8), specifically, a first wiring layer Lb1 on the front surface (first surface) 97a side and a first wiring layer Lb1 on the back surface (second surface) 97b side. A total of 6 layers of 1st to 6th wiring layers Lb1 to Lb6 (FIGS. 57 to 61) including 6 wiring layers Lb6 and 2nd to 5th wiring layers Lb2 to Lb5 arranged between them are provided. There is. The second and fifth wiring layers Lb2 and Lb5 (FIG. 58) are solid wiring layers connected to the ground, and the fourth wiring layer Lb4 (FIG. 60) is a solid wiring layer connected to the power supply. Further, the substrate main body 220 of the liquid crystal interface board 97 is provided with a large number of through-hole type vias (interlayer conduction portions) as in the liquid crystal control board 98, and the plurality of wiring layers Lb1 to Lb6 are provided with these vias (interlayers). They are electrically connected to each other via a conductive portion).

In the following description, the in-plane directions and orientations of the wiring layers Lb1 to Lb6 are the vertical directions in FIGS. 57 to 61 based on the XY coordinate system (see FIG. 8) common to the liquid crystal control board 98. Is the X direction, the left-right direction is the Y direction, the upward / downward direction is the + X / -X direction (side), and the left / right direction is the + Y / -Y direction (side).

As shown in FIG. 57, in the first wiring layer Lb1 of the liquid crystal interface board 97, the liquid crystal IF first to third connector arrangement areas 221 to 223 in which the liquid crystal IF first to third connectors CN21 to CN23 are arranged and the liquid crystal IF first to third connector arrangement areas 221 to 223. Liquid crystal connection first and second connector arrangement areas 224 and 225 in which the liquid crystal connection first and second connectors CN24 and CN25 are arranged are provided.

The liquid crystal IF first connector arrangement region 221 is elongated in the X direction and is arranged on the + X side in the vicinity of the + Y side edge of the first wiring layer Lb1. The liquid crystal IF second connector arrangement region 222 has an elongated shape long in the X direction, and is arranged on the −X side in the vicinity of the + Y side edge of the first wiring layer Lb1. The liquid crystal IF third connector arrangement region 223 has an elongated shape long in the X direction, and is arranged at positions slightly + X and −Y side from the central portion of the first wiring layer Lb1. Further, the liquid crystal connection first and second connectors CN24 and CN25 are both elongated in the Y direction, and the liquid crystal display is located at the position closer to -Y near the edge on the -X side of the first wiring layer Lb1. It is arranged adjacent to each other so as to be the connection second connector CN25.

Hereinafter, among a large number of wiring paths provided on the liquid crystal interface board 97, attention will be paid to a plurality of types of wiring lines P101 to P124 connected to the liquid crystal display means 76 via the liquid crystal connection first and second connectors CN24 and CN25. The details will be explained with reference to the drawings. It should be noted that FIGS. 62 to 66 show only the portions constituting the wiring paths P101 to P124 extracted from the wiring patterns of the first to sixth wiring layers Lb1 to Lb6 shown in FIGS. 57 to 61. 67 to 72 are partially enlarged views thereof. 73 to 75 show schematically the wiring paths of the wiring paths P101 to P124, and FIGS. 76 to 78 show circuit diagrams corresponding to the wiring paths P101 to P124.

First, the wiring lines P101 to P110 constituting the first transmission line LVDS1 for transmitting the ODD signal will be described. The wiring paths P101 to P110 are the ODD side terminals ra0-, ra0 +, ra1-, ra1 +, ra2-, ra2 +, raclk-, raclk +, ra3-, ra3 + of the liquid crystal IF third connector CN23, and the liquid crystal connection first connector. It is arranged so as to connect the ODD side terminals ra0−, ra0 +, ra1-, ra1 +, ra2-, ra2 +, raclk−, raclk +, ra3-, ra3 + in the CN24.

The liquid crystal IF third connector CN23 is arranged in an elongated shape in the X direction as shown in FIG. 62 and the like, and a large number of terminals are arranged along the pair of long sides, and as shown in FIG. 67, the ODD side. The terminals ra0−, ra0 +, ra1-, ra1 +, ra2-, ra2 +, raclk−, raclk +, ra3-, and ra3 + are arranged in the −X direction along the long side on the −Y side in that order. The terminals ra0- and terminal ra0 +, the terminal ra1- and the terminal ra1 +, the terminal ra2- and the terminal ra2 +, the terminal rack- and the terminal raclk +, and the terminal ra3- and the terminal ra3 + are arranged next to each other. A predetermined number (here, one each) of GND terminals are arranged between them (omitted in FIG. 67).

Further, as shown in FIG. 62 and the like, the liquid crystal connection first connector CN24 has an elongated shape in the Y direction, is arranged on the −X side with respect to the liquid crystal IF third connector CN23, and has a large number along the long side of the + X side. Terminals are arranged, and as shown in FIG. 69, the ODD side terminals ra0-, ra0 +, ra1-, ra1 +, ra2-, ra2 +, rackk-, rackk +, ra3-, and ra3 + are arranged in the + Y direction in that order. It is arranged.

In the wiring lines P101 to P110 (FIG. 73), as shown in FIG. 67, in the first wiring layer Lb1, the terminal connection portions ra0−, ra0 +, ra1-, ra1 +, ra2- on the liquid crystal IF third connector arrangement area 223 side. , Ra2 +, raclk-, raclk +, ra3-, ra3 +, respectively, wiring lines cp701 to cp710 are drawn out in the −Y direction. Then, those wiring paths cp701 to cp710 are turned to the liquid crystal connection first connector CN24 side (-X side), and then, as shown in FIGS. 68 and 69, are connected to the liquid crystal display via the test points TP101 to TP110. It is connected to the terminal connection portions ra0−, ra0 +, ra1-, ra1 +, ra2-, ra2 +, raclk−, raclk +, ra3-, ra3 + on the first connector CN24 side.

As described above, in the wiring paths P101 to P110, the terminal arrangement on the liquid crystal IF third connector CN23 side and the terminal arrangement on the liquid crystal connection first connector CN24 side match in a state of facing each other, so that the wiring layer is provided. It is possible to dispose of the first wiring layer Lb1 without twisting only by the first wiring layer Lb1 without switching.

The wiring lines cp701 and cp702, the wiring lines cp703 and cp704, the wiring lines cp705 and cp706, the wiring lines cp707 and cp708, and the wiring lines cp709 and cp710 are parallel to each other while maintaining a substantially constant interval. Ground patterns are arranged between the wiring lines of the above. Further, these five sets of wiring paths are provided with meandering portions having different lengths in order to make the wiring length uniform. Since the diameters of the test points TP101 to TP110 are larger than the minimum distance between the wiring lines, the test points TP101 to TP110 are arranged so as to be spaced apart from each other with respect to the wiring lines cp701 to cp710. Then, two adjacent sets of test points, a total of five sets, are arranged so as to be alternately displaced in the X direction in order to avoid mutual interference.

Further, the wiring lines P101 to P110 are branched from the wiring lines cp701 to cp710 at the test points TP101 to TP110, and are connected to the ground (second wiring layer Lb2) via the protection diode arranged on the sixth wiring layer Lb6 side. There is. That is, the wiring paths P101 and P102 are connected to the protection diode D103, the wiring paths P103 and P104 are connected to the protection diode D105, the wiring paths P105 and P106 are connected to the protection diode D102, and the wiring paths P107 and P108 are connected to the protection diode D104. P110 is connected to the protection diode D101 respectively.

Subsequently, the wiring paths P111 to P120 constituting the second transmission line LVDS2 for transmitting the EVEN signal will be described. The wiring paths P111 to P120 are the EVEN side terminals rb0-, rb0 +, rb1-, rb1 +, rb2-, rb2 +, rbclk-, rbclk +, rb3-, rb3 + of the liquid crystal IF third connector CN23, and the liquid crystal connection first connector. It is arranged so as to connect the EVEN side terminals rb0-, rb0 +, rb1-, rb1 +, rb2-, rb2 +, rbclk-, rbclk +, rb3-, rb3 + in the CN24.

The arrangement of the EVEN side terminals in the liquid crystal IF third connector CN23 has +/- reversed as compared with the arrangement of the ODD side terminals. That is, as shown in FIG. 67, the EVEN side terminal in the liquid crystal IF third connector CN23 is rb0 +, rb0-, rb1 +, rb1-, rb2 +, rb2-, rbclk +, rbclk-, rb3 + along the long side of the + Y side. , Rb3- are arranged in the -X direction in the order. The terminal rb0 + and the terminal rb0-, the terminal rb1 + and the terminal rb1-, the terminal rb2 + and the terminal rb2-, the terminal rbclk + and the terminal rbclk-, and the terminal rb3 + and the terminal rb3- are arranged next to each other. A predetermined number (here, one each) of GND terminals are arranged between them (omitted in FIG. 67).

On the other hand, the arrangement of the EVEN side terminals in the liquid crystal connection first connector CN24 is the same as the arrangement of the ODD side terminals. That is, as shown in FIG. 69, the EVEN side terminal in the liquid crystal IF third connector CN23 is on the + Y side of the ODD side terminal, rb0-, rb0 +, rb1-, rb1 +, rb2-, rb2 +, rbclk-, rbclk +, rb3. They are arranged in the + Y direction in the order of-, rb3 +.

When the EVEN side terminal (FIG. 67) on the liquid crystal IF third connector CN23 side and the EVEN side terminal (FIG. 69) on the liquid crystal connection first connector CN24 side are compared face to face, the arrangement of both is rb0, The arrangement order of the five sets of terminal pairs of rb1, rb2, rbclk, and rb3 is opposite to each other. Therefore, since the wiring paths connecting them will be twisted with each other, it is necessary to perform wiring so as to straddle a plurality of wiring layers, unlike the wiring path on the ODD side.

In the wiring lines P111 to P120 (FIG. 74), as shown in FIG. 67, in the first wiring layer Lb1, the terminal connection portions rb0−, rb0 +, rb1-, rb1 +, rb2- on the liquid crystal IF third connector arrangement area 223 side. , Rb2 +, rbclk-, rbclk +, rb3-, rb3 +, respectively, wiring lines cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp732, cp735, cp738 are pulled out in the + Y direction. Then, the wiring lines cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp7322, cp735, cp738 are turned to the liquid crystal connection first connector CN24 side (-X side), and then the via v301 to It is connected to v310.

The wiring lines cp711 and cp714, the wiring lines cp717 and cp720, the wiring lines cp723 and cp726, the wiring lines cp729 and cp732, and the wiring lines cp735 and cp738 are parallel to each other while maintaining a substantially constant interval, and these five sets of wirings are used. Ground patterns are arranged between the roads.

Here, v301 to v310 are arranged so as to be adjacent to each other in the X direction corresponding to five sets of terminal pairs of rb0, rb1, rb2, rbclk, and rb3, and are arranged so as to be adjacent to each other in the X direction, and the wiring path cp711 on the most + Y side. , 5 pairs of vias are located in the X direction so that the vias v301 and v302 corresponding to cp714 are on the most -X side and the vias v309 and v310 corresponding to the wiring lines cp735 and cp738 on the most -Y side are on the most + Y side. Are arranged in a staggered manner.

Regarding the vias v303 to v310 corresponding to the wiring paths cp717, cp720, cp723, cp726, cp729, cp732, cp735, cp738, the-signal side vias v303, v305, v307, v309 are + signal-side vias v304, It is arranged so as to be on the -X side with respect to v306, v308, and v310, and the wiring lines cp717, cp720, cp723, cp726, cp729, cp732, cp735, cp738 are connected from the -Y side, respectively. Regarding the vias v301 and v302 corresponding to the wiring paths cp711 and cp714, the vias v301 on the-signal side are arranged so as to be on the + X side with respect to the via v302 on the + signal side, and the wiring paths cp711 and cp714 are respectively. It is connected from the + Y side.

Further, as shown in FIG. 70, v301 to v310 are connected to the wiring paths cp7122, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, cp739 on the sixth wiring layer Lb6 side. In those wiring lines cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp7366, cp739, the wiring lines cp712, cp715 corresponding to the vias v301 and v302 on the most -X side are the most on the -Y side and the most + X side. After changing the direction to the liquid crystal connection first connector CN24 side (-X side) so that the wiring lines cp736 and cp739 corresponding to the vias v309 and v310 are on the most + Y side, they are connected to the test points TP111 to TP120. ing. As a result, the arrangement order of the wiring lines cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp7366, cp739 on the sixth wiring layer Lb6 side is changed to the wiring lines cp711, cp714, cp717 on the first wiring layer Lb1 side. , Cp720, cp723, cp726, cp729, cp732, cp735, cp738, and the order is changed to match the arrangement of the EVEN side terminals in the liquid crystal connection first connector CN24.

The cp718, cp721, cp724, cp727, cp730, cp733, cp736, cp739 are pulled out in the + Y direction with respect to the vias v303 to v310, while the cp7122 and cp715 are drawn with respect to the vias v301 and v302. Since it is pulled out in the −Y direction, there is no change in the arrangement of the +/- wiring paths between the first wiring layer Lb1 side and the sixth wiring layer Lb6 side.

Since the diameters of the test points TP111 to TP120 are larger than the minimum distance between the wiring lines, the same as the test points TP101 to TP110, each wiring line cp712, cp715, cp718, cp7211, cp724, cp727, cp730, cp733 , Cp736, cp739, the axes are offset and the intervals are widened. Then, two adjacent sets of test points, a total of five sets, are arranged so as to be alternately displaced in the X direction in order to avoid mutual interference.

Further, as shown in FIG. 69, the test points TP111 to TP120 are connected to the liquid crystal display via the wiring paths cp713, cp716, cp719, cp722, cp725, cp728, cp731, cp734, cp737, cp740 on the first wiring layer Lb1 side. 1 Connector It is connected to the terminal connection portions rb0-, rb0 +, rb1-, rb1 +, rb2-, rb2 +, rbclk-, rbclk +, rb3-, rb3 + on the CN24 side.

Further, the wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp7366, cp739 on the sixth wiring layer Lb6 side are protected diodes D110, D111, D112, D108, D109 from the test points TP111 to TP120, respectively. It is connected to the ground (second wiring layer Lb2) via the above. That is, as shown in FIG. 70, the wiring paths cp712 and cp715 are connected to the protection diode D110, the wiring paths cp718 and cp721 are connected to the protection diode D111, the wiring paths cp724 and cp727 are connected to the protection diode D112, and the wiring paths cp730 and cp733 are connected to the protection diode. The wiring paths cp736 and cp739 are connected to D108, respectively, to the protection diode D109.

As described above, in the wiring paths P101 to P120 of the present embodiment, the wiring pattern before reaching the test points TP101 to TP120 (upstream side, that is, the liquid crystal IF third connector CN23 side) is shown in FIGS. 62, 70 and the like. By meandering as shown in, the wiring length of each wiring line is made substantially equal. This makes it possible to evenly measure each transmission speed during a test using the test points TP101 to TP120. Of course, as shown in FIG. 69, it is desirable that the wiring length of each wiring line is substantially equal even for the wiring pattern after passing through the test points TP101 to TP120 (downstream side, that is, the liquid crystal connection first connector CN24 side). .. This is to equalize the transmission speed of the image data in each wiring line. Further, it is desirable that these test points TP101 to TP120 are provided in front (upstream side) of the electronic component such as a diode in that it is possible to confirm whether or not the noise source is in the electronic component such as a diode.

Subsequently, the wiring path P121 for transmitting the backlight ON / OFF control signal XSTABY1 from the liquid crystal IF third connector CN23 to the liquid crystal connection second connector CN25 will be described. The backlight of the liquid crystal display means 76 is composed of light emitting diodes (LEDs) arranged vertically and horizontally and a drive driver that outputs a drive signal to synchronously turn on and drive the light emitting diodes. The CPU (built-in CPU circuit 171) controls the drive driver so that the internal operation of the drive driver is possible by outputting the backlight ON / OFF control signal XSTABY1 to the drive driver.

In the wiring line P121 (FIG. 75), as shown in FIG. 67, in the first wiring layer Lb1, the wiring line cp801 is provided from the terminal connection portion xstaby1 on the liquid crystal IF third connector arrangement area 223 (liquid crystal IF third connector CN23) side. It is pulled out in the -Y direction and connected to the via v311. As shown in FIG. 71, the via v311 is connected to the ground via the resistor RA113 in the sixth wiring layer Lb6 and is connected to the via v312 by the wiring path cp802, and is connected to the via v312 by the wiring path cp802. The logic integrated circuit IC101, the test point TP121, the transistor Q102 with a built-in resistance, the resistance R106, the transistor Q104, the resistance R105, and the test point TP122 are arranged. The via v331 is arranged on the wiring path connecting the transistor Q104 and the resistor R105. This via v331 is connected to a wiring line P123 for supplying DC12V, which will be described later.

The via v312 is connected to the via v313 via the wiring path cp803 on the third wiring layer Lb3 side as shown in FIG. 64, and further connects the wiring path cp804 on the first wiring layer Lb1 side as shown in FIG. It is connected to the terminal connection portion xstaby1 on the liquid crystal connection second connector arrangement area 225 (liquid crystal connection second connector CN25) side via the liquid crystal connection second connector arrangement area 225.

Subsequently, the wiring path P122 for transmitting the backlight dimming PWM signal VBR1 from the liquid crystal IF third connector CN23 to the liquid crystal connection second connector CN25 will be described. The liquid crystal control CPU operates the drive driver by outputting the backlight dimming PWM signal VBR1 to the drive driver whose internal operation is possible by the backlight ON / OFF control signal XSTABY1 described above. It is configured to light and drive the light emitting diode.

In the wiring line P122 (FIG. 75), as shown in FIG. 67, in the first wiring layer Lb1, the wiring line cp811 is provided from the terminal connection portion vbr1 on the liquid crystal IF third connector arrangement region 223 (liquid crystal IF third connector CN23) side. It is pulled out in the -Y direction and connected to the via v314. As shown in FIG. 71, the via v314 is connected to the ground via the resistor RA113 in the sixth wiring layer Lb6, and is connected to the via v315 by the wiring path cp812, and is connected to the via v315 by the wiring path cp812. The logic integrated circuit IC101, the test point TP123, the transistor Q101 with built-in resistance, the resistance R104, the transistor Q103, the resistance R111, and the test point TP124 are arranged. The via v332 is arranged on the wiring path connecting the transistor Q103 and the resistor R111. This via v332 is connected to a wiring line P123 for supplying DC12V, which will be described later.

Then, as shown in FIG. 64, the via v315 is connected to the via v316 via the wiring path cp813 on the third wiring layer Lb3 side, and further, as shown in FIG. 69, the wiring path cp814 on the first wiring layer Lb1 side. It is connected to the terminal connection portion xstaby1 on the liquid crystal connection second connector arrangement area 225 (liquid crystal connection second connector CN25) side.

Subsequently, a wiring path P123 for supplying DC12V from the liquid crystal IF second connector CN22 to the liquid crystal connection second connector CN25 and the like will be described based on the power supply control signal PS1 from the liquid crystal IF third connector CN23. It should be noted that the 12V power supply is configured to be supplied to the backlight power supply unit of the liquid crystal display means 76 based on the power supply control signal PS1.

In the wiring line P123 (FIG. 75), as shown in FIG. 67, in the first wiring layer Lb1, the wiring line cp821 is provided from the terminal connection portion ps1 on the liquid crystal IF third connector arrangement region 223 (liquid crystal IF third connector CN23) side. It is pulled out in the -Y direction and connected to the via v317. As shown in FIG. 71, the via v317 is connected to the ground via the resistor RA113 in the sixth wiring layer Lb6, and is connected to the via v318 by the wiring path cp822, and is connected to the via v318 by the wiring path cp822. The logic integrated circuit IC101, the transistor Q107 with built-in resistance, and the resistance R109 are arranged.

Then, as shown in FIG. 68, the via v318 is connected to the resistor R103 and the transistor Q106 via cp823 in the first wiring layer Lb1.

Further, in the wiring path P123 (FIG. 75), as shown in FIG. 68, one or a plurality (here, eight) on the liquid crystal IF second connector arrangement region 222 (liquid crystal IF second connector CN22) side in the first wiring layer Lb1. ), The solid wiring line cp824 is pulled out from the terminal connection portion dc12v to the −Y side and is connected to one or more (here, 6) vias v321. The solid wiring path cp824 is connected to the ground via capacitors C107, C110, and C114, respectively.

Then, as shown in FIG. 65, the via v321 is connected to one or more (here, 6) vias v322 via the solid wiring path cp825 of the fourth wiring layer Lb4, and further, as shown in FIG. 68, the via v321 is connected to the via v322. 1 The resistance R103 and the transistor Q106 are connected to each other via the wiring path cp826 on the wiring layer Lb1 side.

Further, as shown in FIG. 68, the transistor Q106 is connected to one or more (here, five) vias v341 and one or more (here, one) via v332 via a solid wiring line cp827. As described above, the via v332 is connected to the transistor Q103 and the resistor R111 on the wiring path P122 side in the sixth wiring layer Lb6.

Further, as shown in FIG. 65, the via v341 includes one or more (here, one) via v331 and one or more (here, five) vias via the solid wiring path cp828 of the fourth wiring layer Lb4. It is connected to v342 and via v332. As described above, the via v331 is connected to the transistor Q104 and the resistor R105 on the wiring path P121 side in the sixth wiring layer Lb6.

As shown in FIG. 72, the via v342 is connected to the capacitors C112, C104, the resistor R112, the diode D106, the test points TP125, and TP126 via the solid wiring path cp829 in the sixth wiring layer Lb6, and is also shown in FIG. As described above, in the first wiring layer Lb1, the wiring is connected to a plurality of (here, four) terminal connection portions dc12v on the liquid crystal connection second connector arrangement area 225 (liquid crystal connection second connector CN25) side via the solid wiring path cp830. There is.

Subsequently, the wiring path P124 for supplying DC5V from the liquid crystal IF second connector CN22 to the liquid crystal connection first connector CN24 will be described based on the power control signal PS2 from the liquid crystal IF third connector CN23. It should be noted that the 5V power supply is configured to be supplied to the display control unit of the liquid crystal display means 76 based on the power supply control signal PS2.

In the wiring line P124 (FIG. 75), as shown in FIG. 67, in the first wiring layer Lb1, the wiring line cp831 is provided from the terminal connection portion ps2 on the liquid crystal IF third connector arrangement region 223 (liquid crystal IF third connector CN23) side. It is pulled out in the -Y direction and connected to the via v351. As shown in FIG. 71, the via v351 is connected to the ground via the resistor RA113 in the sixth wiring layer Lb6 and is connected to the via v352 by the wiring path cp832, and is connected to the via v352 by the wiring path cp832. The logic integrated circuit IC101, the transistor Q105 with built-in resistance, and the resistance R107 are arranged.

Then, as shown in FIG. 68, the via v352 is connected to the resistor R108 via the wiring path cp833 in the first wiring layer Lb1. Further, the resistance R108 is connected to the transistor Q108 via the wiring path cp834.

Further, in the wiring path P124 (FIG. 75), as shown in FIG. 68, in the first wiring layer Lb1, a plurality (here, eight) on the liquid crystal IF second connector arrangement region 222 (liquid crystal IF second connector CN22) side. The solid wiring path cp835 is pulled out from the terminal connection portion dc5v to the −Y side and is connected to one or more (here, four) vias v353. The solid wiring path cp835 is connected to the ground via capacitors C108 and C109, respectively.

Then, as shown in FIG. 65, the via v353 is connected to one or more (here, three) vias v354 via the solid wiring path cp836 of the fourth wiring layer Lb4, and further, as shown in FIG. 68, the via v353 is connected to the via v354. It is connected to the resistor R108 and the transistor Q108 via the wiring path cp837 on the first wiring layer Lb1 side.

Further, as shown in FIG. 68, the transistor Q108 is connected to one or more (here, four) vias v355 via the solid wiring path cp838 on the first wiring layer Lb1 side. As shown in FIG. 65, the via v355 is connected to a plurality of (here, four) vias v356 via the solid wiring path cp839 of the fourth wiring layer Lb4.

Then, as shown in FIG. 72, the via v356 is connected to the solid wiring path cp840 in the sixth wiring layer Lb6. Capacitors C113, C105, resistor R110, diode D107, test points TP127, and TP128 are connected to the solid wiring line cp840, and are connected to one or more (here, four) vias v357. As shown in FIG. 69, the vias v357 are a plurality (here, four) on the liquid crystal connection first connector arrangement region 224 (liquid crystal connection first connector CN24) side in the first wiring layer Lb1 via the solid wiring path cp841. It is connected to the terminal connection part dc5v.

As described above, in the present embodiment, the power supply to the liquid crystal display means is controlled by software by the power control signals PS1 and PS2, but the present invention is not limited to this, and hardware such as a driver is used. It may be configured to control the power supply to the liquid crystal display means. In this case, the 12V power supply and the 5V power supply are supplied to the backlight power supply unit and the display control unit when the power of the gaming machine is turned on, respectively.

Here, the processing when the power is turned on by the liquid crystal control CPU will be described. The liquid crystal control CPU supplies power to the liquid crystal display means by the power control signals PS1 and PS2 as a process at the time of turning on the power, and then returns the backlight ON / OFF control signal XSTABY1 and the backlight dimming PWM to the drive driver. It is configured to perform the following processing before outputting the signal VBR1.

First, the initialization and refresh cycle of the built-in VRAM is set. By performing the refresh process based on the predetermined cycle set here, the charge loss of the memory is prevented. Therefore, even if there is a memory cell that is not accessed for a long time in VRAM, there is no possibility that the data will be lost.

Subsequently, the display circuit is initialized and the display clock that defines the operation of the display circuit is initially set by setting a predetermined register. Then, the initial setting related to the LVDS output is performed by the predetermined register setting. Further, the LVDS output of the image data is performed from the designated display circuit by setting a predetermined register. At that time, the output image data is set to output random data (all 0 data) by register setting. As a result, it is possible to prevent unnatural image data such as broken from being displayed on the liquid crystal display means side, and it is possible to confirm that the LVDS output process itself operates normally. Further, although the image data is set to be output here, the backlight ON / OFF control signal XSTABY1 and the backlight dimming PWM signal VBR1 are not yet output to the drive driver at this timing. Actually, the image based on the random data (all 0 data) is not displayed on the liquid crystal display means side. By doing so, it is configured so that meaningless image data (on display) is not visible.

Here, it was decided to output random data (all 0 data) by register setting, but as mentioned above, it is difficult to actually visually recognize the output image data at this timing, so specify random data. Instead, only the output processing of the image data (unspecified uncertain data) may be performed. In this case, since the register setting process can be reduced, the process performed when the power is turned on can be reduced, and the time until the liquid crystal display means actually lights up can be shortened as much as possible.

Further, since the dual link transmission method is adopted in this embodiment, the LVDS output setting for the ODD signal and the LVDS output setting for the EVEN signal are set for each register. At this time, common setting values are set for each parameter to be set.

Then, with reference to a predetermined register, it is confirmed whether the clock operation of the display clock for which the initial setting has been made is in a stable state. At that time, the watchdog timer for resetting the liquid crystal control CPU is cleared and waits until the register value reaches a value indicating a stable state.

Then, referring to a predetermined register, it is confirmed whether the initialization of the display circuit for which the initial setting has been performed is completed. At that time, until the value of the register reaches the value indicating the completion of initialization, the watchdog timer for resetting the liquid crystal control CPU is cleared and waits.

Then, with reference to a predetermined register, it is confirmed whether the initialization of the LVDS output for which the initial setting has been performed is completed. At that time, until the value of the register reaches the value indicating the completion of initialization, the watchdog timer for resetting the liquid crystal control CPU is cleared and waits.

Subsequently, the definitions of the AAC area, the page area, and the arbitrary area are set for the built-in VRAM (at that time, each frame buffer is secured in the arbitrary area). Furthermore, the number of display lines and the number of horizontal pixels for the liquid crystal display means to be used are set, the horizontal synchronization cycle, the horizontal standby time is set, the number of vertical synchronization lines and the vertical standby time are set, and the pulse width of the horizontal synchronization signal HS. And the setting of the number of cycles from the start of V blank, the pulse width of the vertical synchronization signal VS and the setting of the number of cycles from the start of V blank, the setting of V blank interrupt permission, the setting of the vertical / horizontal display start position for each frame buffer, Set the display area, etc.

Then, referring to a predetermined register, it is confirmed whether the initialization of the built-in VRAM that has been initialized is completed. At that time, until the value of the register reaches the value indicating the completion of initialization, the watchdog timer for resetting the liquid crystal control CPU is cleared and waits.

Finally, by setting a predetermined register, a setting for allowing the display circuit to access the built-in VRAM and permit operation to generate image data, and a setting for permitting operation of LVDS output are performed.

Then, after these processes are completed, the backlight ON / OFF control signal XSTABY1 is output to the drive driver, and after waiting for a predetermined time (about 300 ms), the backlight dimming PWM signal VBR1 is output. , Complete the lighting control of the liquid crystal display means.

In this way, after power is supplied to the liquid crystal display means by the power control signals PS1 and PS2, various settings related to the display circuit, output circuit, and image data generation are made before actually starting the lighting control. , There is no risk that inappropriate data will be output on the screen by mistake during setting. Further, since the lighting of the backlight of the liquid crystal display means is started after all of these settings are completed, it is possible to configure the display so that all the settings related to the display have already been completed when the liquid crystal display means is turned on. .. Therefore, it can be configured so that the image data can be output immediately from the time when the liquid crystal display means is turned on.

In this embodiment, various setting processes are performed before outputting the backlight ON / OFF control signal XSTABY1 and the backlight dimming PWM signal VBR1 to the drive driver, but the present invention is not limited to this. It may be performed after the output of the light ON / OFF control signal XSTABY1 and before the output of the backlight dimming PWM signal VBR1.

Subsequently, a specific example of the effect executed by the effect control unit 95 will be described. FIG. 79 conceptually shows the configuration related to the effect control realized by the effect control unit 95.

The special hold quantity display control means 95a controls the display of the first and second special hold quantity on the liquid crystal display means 76, and corresponds to the increase / decrease in the first and second special hold quantity, and the first special hold. The first hold notification images X1 to X4 for the number of pieces (up to 4), the second hold notification images Y1 to Y4 for the number of second special hold numbers (up to 4), and the changing first and second special symbols. The variable pending notification image Z corresponding to the above is displayed on the liquid crystal display means 76.

When the first and second special symbol starting means 72 and 73 receive the hold addition command regarding the first and second special hold numbers from the main control board 93 based on the detection of the game ball, the special hold number The display control means 95a additionally displays the first and second hold notification images X1 to Y1 to the end of the queue. Further, based on the start of the fluctuation of the first and second special symbols by the first and second special symbol display means 63 and 64, the hold subtraction command regarding the first and second special hold numbers is issued from the main control board 93. When received, the special hold quantity display control means 95a shifts the first and second hold notification images X1 to Y1 to the front side of the queue one by one, and pushes out the first first. 1, The second hold notification image X1 and Y1 are moved to, for example, a predetermined position and changed to the changing hold notification image Z. In the present embodiment, for example, "○ (white circle)" is set as the default for the display color (display mode) of the first and second hold notification images X1 to Y1 and the changing hold notification image Z, and the hold change described later is performed. When the advance notice is executed, it is changed according to the scenario selected by the look-ahead advance notice effect control means 95b.

The look-ahead notice effect control means 95b controls the look-ahead notice effect, and the stop symbol after the change of the first and second special symbols becomes a big hit mode based on the look-ahead determination result by the main control board 93, and is a big hit game. It is configured to be able to execute a look-ahead notice effect that gives notice of whether or not In the main control board 93, the first and second special random number information acquired when the first and second special symbol starting means 72 and 73 detect the game ball is before being subjected to the symbol variation. Pre-reading determination to determine whether or not the jackpot determination random number value included in the first and second special random number information matches the jackpot determination value at a predetermined timing of, for example, when the first and second special random number information is acquired. The process can be executed. The look-ahead determination result is transmitted from the main control board 93 by, for example, a hold addition command.

The look-ahead notice production includes "continuous notice", "pending change notice" and the like. The "continuous notice" has, for example, the same embodiment in a plurality of symbol fluctuations (during the look-ahead zone) up to the symbol variation (target variation) corresponding to the special random number information subject to the look-ahead determination based on the look-ahead determination result. It is the one that executes the production.

Further, the "hold change notice" displays the first and second hold notification images X1 to X4, Y1 to Y4, and the changing hold notification image Z in a predetermined display mode based on the look-ahead determination result. In the present embodiment, as shown in FIG. 80, three types of display modes of the hold notification image other than the default "○ (white circle)" are prepared, and one of them is selected by lottery by the notice effect control means 95b. In the case of winning, for example, when the first and second hold notification images are newly additionally displayed, or at a predetermined timing thereafter, the hold notification image is displayed in a display mode such as the winning "elephant". The display mode of the hold notification image is selected according to the jackpot reliability based on the look-ahead determination, and as shown in FIG. 80, for example, the jackpot reliability is in the order of "giraffe", "elephant", and "lion". The degree is set to be high. Further, for example, a display mode such as "Rainbow" in which the jackpot reliability is set to 100% may be provided. If the look-ahead is prohibited or if the hold change notice is not won, the hold notification image is displayed as "○ (white circle)".

Further, the hold notification image of the present embodiment is adapted to perform an operation (dynamic display) mainly for a change in the vertical direction at the start, display, and end of the display. FIGS. 81 (a) to 81 (c) show an example of each operation of the hold notification image of the “elephant” at the start of display, during display, and at the end of display. The same applies to the other "lion" and "giraffe" hold notification images. As shown in FIG. 81 (a), when the hold notification image is newly displayed (at the start of display), it bounces once in the vertical direction immediately after the hold notification image is displayed. That is, a vertical movement operation is performed on the hold notification image at the start of display.

Further, as shown in FIG. 81 (b), while the hold notification image is being displayed (after the display starts and before the display ends), the hold notification image is displayed as if it is three-dimensionally rotated around the horizontal axis. To. At this time, what is actually performed on the two-dimensional screen is the vertical deformation operation. Although the operation of the hold notification image during display is repeated, it may be performed continuously or intermittently.

Further, as shown in FIG. 81 (c), when the display of the hold notification image is ended (at the end of the display), the hold notification image is displayed so as to be sequentially erased downward (or upward). That is, a vertical deformation operation is performed on the hold notification image at the end of display.

Further, as shown in FIG. 80, the hold notification image of the present embodiment is configured so that the types of color information are distributed more in the vertical direction than in the horizontal direction, and the higher the jackpot reliability is, the more the types of color information are. Is increasing. For example, in the hold notification image of "elephant", the display color of the background portion of the character changes in three stages in the vertical direction, but the display color does not change in the horizontal direction. As a result, when the hold notification image is viewed in pixel units, the number of types of color information used on each vertical pixel line is larger than the number of types of color information used on each horizontal pixel line. Is relatively large.

By the way, as already described, in the pachinko machine of the present embodiment, the liquid crystal control board (display control means) 98 that controls the display of the liquid crystal display means 76 corresponds to odd pixels in the left-right direction with respect to the liquid crystal display means 76. The odd-numbered image data and the even-numbered image data corresponding to the even-numbered pixels in the left-right direction are configured to be output in parallel via different wiring paths, that is, the first transmission path LVDS1 and the second transmission path LVDS2. There is. Therefore, for example, even if one of the first and second transmission lines LDVS1 and LVDS2 cannot be transmitted due to disconnection or the like, as long as the other transmission line is alive, only one of the odd-numbered image data and the even-numbered image data is available. It is possible to continue the display of the liquid crystal display means 76. However, in this case, since the vertical pixel lines are missing for each line on the screen of the liquid crystal display means 76, the player may not be able to sufficiently identify the displayed contents as compared with the normal display state. ..

In that respect, the hold notification image of the present embodiment is designed to perform an operation mainly for a change in the vertical direction at the start, display, and end of the display, and therefore, it is regarded as odd-numbered image data. Even if any of the even image data is missing, the dynamic display (movement, deformation, etc.) of the hold notification image is continuously displayed as shown in FIGS. 82 (a) and 82 (b). It is along the vertical pixel line (without omission), and the player can identify the dynamic display of the hold notification image as in the normal display.

Further, since the hold notification image of the present embodiment is configured so that the types of color information are distributed more in the vertical direction than in the horizontal direction, there is a case where either odd-numbered image data or even-numbered image data is missing. However, as shown in FIG. 83 (a), the color change is along the vertical pixel line that is normally displayed, and the player can clearly recognize the color change in pixel units, so that the hold notification image is obtained. Can be identified in the same way as when displaying normally. By the way, when the types of color information are distributed in the horizontal direction, if either the odd-numbered image data or the even-numbered image data is missing, the color change position becomes ambiguous as shown in FIG. 83 (b), and the player is notified of the hold. It may not be possible to identify the image as it was when it was displayed normally.

It should be noted that the operation of the hold notification image does not have to be performed at all of the display start, display, and display end, and any of them may not be performed. Further, the operation of the hold notification image may be mainly one that changes in the vertical direction, and may be accompanied by a change in the left-right direction. Further, the dynamic display mainly for the vertical change of the hold notification image is not limited to the one shown in FIG. 81, and for example, an effect mainly for the vertical change (for example, an effect that shines in the vertical direction). ) May be displayed.

Further, when shifting the hold notification image at the start of a new symbol change, as shown in FIG. 84, not only the hold notification image is moved in the left-right direction, but also the hold notification image is moved in the up-down direction at that time (for example,). Bound operation) is performed. As a result, even if either the odd-numbered image data or the even-numbered image data is missing, the shift operation of the hold notification image is an operation along the vertically displayed (no missing) vertical pixel line. Therefore, the player can more clearly and easily recognize the shift operation of the hold notification image. In addition, instead of or in addition to the movement in the vertical direction, the deformation in the vertical direction may be accompanied.

Returning to FIG. 79, the description will be continued. The symbol variation effect control means 95c controls the display of the decorative symbol 90 and the accompanying voice output, lamp emission, and the like, and the first and second special symbols by the first and second special symbol display means 63 and 64 Various scenarios such as a variation pattern scenario corresponding to a specified variation pattern when a variation pattern command is received from the main control board 93 at the start of the variation, and a notice effect scenario selected by the normal advance notice effect control means 95d described later. When the variation of the decorative symbol 90 and the accompanying voice output, lamp emission, etc. are started, and the variation stop command is received from the main control board 93 at the end of the variation of the first and second special symbols, the stop symbol is stopped. The fluctuation of the decorative symbol 90 is stopped by the stop symbol selected based on the command and the variation pattern command, and the voice output, the lamp emission, and the like accompanying the fluctuation are stopped.

As shown in FIG. 85A, in the decorative symbol 90, the symbol main body 90a is displayed in any one of a plurality of colors, for example, an odd number symbol is displayed in red and an even number symbol is displayed in blue. However, strictly speaking, the color of the pattern main body 90a is not a single color, and many kinds of similar colors are used to express a three-dimensional effect and the like. Then, in the present embodiment, a vertical gradation is formed as shown in FIG. 85 (a) so that the types of color information in the symbol main body 90a are distributed more in the vertical direction than in the horizontal direction. As a result, even if either the odd-numbered image data or the even-numbered image data is missing, as shown in FIG. 85 (b), the color change in the symbol body portion 90a is normally displayed vertically. It is along the pixel line, and the player can clearly recognize the color change in pixel units, so that the color information of the decorative symbol 90 can be identified in the same manner as in the normal display. In the decorative pattern 90, it is sufficient that the types of color information are distributed more in the vertical direction than in the horizontal direction, and it is not always necessary to have a gradation.

Further, as shown in FIG. 86, the decorative symbol 90 displays a dynamic display accompanied by a change in the vertical direction (here, expansion / contraction deformation in the vertical direction) at the start of change, at the stop of change, at the time of reaching, and in a specific mode (here). Big hit effect mode) It is designed to be executed at a predetermined timing such as when it is established. In this way, by assuming that the dynamic display performed at a predetermined timing is accompanied by a change in the vertical direction, even if either the odd-numbered image data or the even-numbered image data is missing, the hold shown in FIG. 82 is shown. As in the case of the broadcast image, the dynamic display is along the vertical pixel line that is continuously displayed (without omission), and the player can display the dynamic display of the decorative symbol 90 as if it were normally displayed. It can be identified in the same way.

Regarding the decorative symbol 90, the dynamic display accompanied by a change in the vertical direction is not limited to deformation such as scaling, but may be any movement, rotation, or the like. In addition, since the symbol variation is also included in the dynamic display, considering the case where either the odd-numbered image data or the even-numbered image data is missing, the direction of the symbol variation (scrolling direction) is more in the vertical direction than in the horizontal direction. desirable. Further, when executing a dynamic display accompanied by a change in the horizontal direction instead of the vertical direction, it is desirable to configure the device so as to move (change) by 2 dots or more for each frame. As a result, even if either the odd-numbered image data or the even-numbered image data is missing, the lateral change of the decorative symbol 90 always appears for each frame, so that the player normally displays the dynamic display of the decorative symbol 90. It will be possible to identify as in time.

Returning to FIG. 79, the description will be continued. The normal advance notice effect control means 95d controls the normal advance notice effect. The normal advance notice effect notifies the possibility that a predetermined event may occur (for example, the jackpot reliability) during the symbol variation based on the jackpot determination result or the like by the jackpot determination process on the main control board 93 side. There are "SU notice", "timer notice", "pseudo-ream effect", "button effect", "line notice", "information notice", "rainbow effect" and the like.

Among them, for example, "button effect" (operation effect) is an effect that requires the player to operate the effect button (predetermined operation means) 41, and is produced during the operation valid period in which the operation by the effect button 41 is effective. When the operation by the button 41 satisfies the predetermined operation condition, the jackpot reliability and the like are notified by executing the predetermined post-operation effect. Of course, the operation target in the operation effect may be an operation lever, a touch panel, or the like as long as it can be operated by the player. During the operation valid period, the LED (not shown) provided in the effect button 41 emits light, and the operation guidance image 231 for urging the player to operate the effect button 41 is displayed on the liquid crystal display means 76. As shown in FIG. 87, the operation guidance image 231 is an operation showing an operation mode for the button image (operation target image) 232 showing the effect button (predetermined operation means) 41 to be operated and the effect button 41 to be operated. The mode notification image 233 and the operation validity period notification image 234 showing the elapsed status of the operation validity period are provided.

The operation valid period notification image 234 is formed in an elongated shape long in the left-right direction, and the progressed display unit 234a on one side (here, the left side) and the non-progress display unit on the other side (here, the right side) in the longitudinal direction thereof. The boundary 234c with the 234b moves sideways (here, to the right) according to the passage of time during the operation valid period, thereby notifying the elapsed status of the operation valid period. That is, the boundary 234c is located on the left end side so that the length ratio between the elapsed display unit 234a and the non-elapsed display unit 234b is 0:10 at the start of the operation valid period, and according to the passage of time during the operation valid period. After the boundary 234c moves to the right at a constant speed, the boundary 234c reaches the right end side at the expiration of the operation valid period so that the length ratio of the elapsed display unit 234a and the non-progress display unit 234b becomes 10: 0. Be controlled.

The button effect (operation effect) includes, for example, a "blow button effect" that determines that a predetermined operation condition is satisfied when the effect button 41 is operated once due to a difference in the operation mode requested from the player, and an effect button. "Continuous push button effect" that determines that the predetermined operation condition is satisfied when the 41 is continuously pressed (operated) a plurality of times, and the predetermined operation condition when the pressed (operation) state of the effect button 41 is continued for a predetermined period. A "long-press button effect" or the like for determining that is satisfied can be considered. The operation mode notification image 233 is composed of character information such as "PUSH" in the case of a blow button effect, "continuous hit" in the case of a continuous hit button effect, and "long press" in the case of a long press button effect. Of course, when the type of the button effect is limited to the one-shot button effect, the operation mode notification image 233 may be one type, and the operation mode notification image 233 may not be displayed. Further, the operation mode notification image 233 is integrated with the button image (operation target image) 232 as shown in FIG. 87, and is configured to display character information indicating the operation mode such as "PUSH" on the button image. Alternatively, it may be displayed separately from the button image (operation target image) 232.

Further, the "rainbow effect" notifies the player of the confirmation of the privilege grant (for example, the winning confirmation regarding the result of the winning lottery as to whether or not to execute the big hit game (big hit confirmation)), and the rainbow is displayed on the liquid crystal display means 76. A rainbow image effect that displays an image (gradation image), and a rainbow emission pattern that emits light emitters arranged in a predetermined part including the front frame 3 such as a frame lamp 304, a board lamp 324, and a movable accessory lamp 314. There is a production. The rainbow image effect and the rainbow light emission effect can be executed in parallel with each other, or either one can be executed independently.

The rainbow image effect includes a case where the entire surface image (for example, a background image) displayed on substantially the entire surface of the liquid crystal display means 76 is displayed in rainbow colors, and a character, a figure, and a character displayed on a part of the screen of the liquid crystal display means 76. A partial image consisting of the above may be displayed in rainbow colors. Since color display is not possible in the patent drawings, the rainbow image is simply expressed in black and white gradation in the drawings of the present application.

The rainbow image changes color in the circumferential direction around a predetermined point on the screen (FIG. 88 (a)), and changes in color in the radial direction around a predetermined point on the screen (FIG. 88 (b)). It is conceivable that the color changes in any direction such as the vertical direction and the horizontal direction (FIGS. 88 (c) and 88 (d)). Further, instead of the smooth gradation as shown in FIGS. 88 (a) to 88 (c), a gradation that gradually changes the color as shown in FIG. 88 (d) may be adopted.

Further, in the rainbow images illustrated in FIGS. 88 (a) to 88 (d), the display color is continuously or stepwise changed with respect to the position, but is also continuous (or stepwise) with respect to time. The display color may be changed to. That is, as shown in FIG. 89, it is sufficient to control all the pixels constituting the rainbow background image so that the display colors make a round and return to the original display colors in a predetermined time (for example, 3 seconds). As a result, in the case of FIG. 88 (a), the rainbow color flows clockwise or counterclockwise, and in the case of FIG. 88 (b), the rainbow color flows outward or inward in the radial direction. In the case of FIG. 88 (c), the rainbow color is displayed to flow upward or downward, and in the case of FIG. 88 (d), the rainbow color is displayed to flow to the left or right.

The various normal advance notice effects as described above can be executed individually or in combination of a plurality of types of effects. Hereinafter, a specific example of the "winning branch button effect", which is a combination of the button effect and the rainbow effect, will be described as the winning branch effect at the end of the reach effect.

In the winning branch button effect shown in FIG. 90, the button fanning effect is first executed. The button fanning effect is an effect of fanning the player's expectation by notifying in advance that the button operation will be possible soon, and the button fanning image 242 is displayed on the liquid crystal display means 76. The button fanning image 242 is a band effect image 242a arranged in a predetermined direction (here, left-right direction) at a predetermined position (here, the upper part) on the screen, and a character image (band effect related image) related to the band effect image 242a. ) With 242b.

As shown in FIG. 91, the band effect image 242a has a character information image (information image) 235 composed of a character string (display information) and characters so as to overlap at least a part of the character information image 235. It is composed of an information decoration image 236 arranged in a substantially band-shaped area along the information image 235.

The character information image 235 is a "big hit!" That is more important to the player than the first character information (first display information) 235a composed of the character string "If the character is made to laugh" and the first character information 235a. It is composed of the second character information (second display information) 235b which is composed of the character string of. The first character information 235a is displayed so as to fit within the width (vertical width) of the information decoration image 236, whereas the second character information 235b is displayed on at least one side (here, the upper side) of the information decoration image 236. It is displayed so that it sticks out. With such a configuration, the character information image 235 can be sharpened according to the importance, and the width of the information decoration image 236 for emphasizing and making the character information image 235 stand out is made as small as possible to make the background visible. It is possible to secure a sufficient amount.

Further, the second character information 235b is displayed in a color that is more visible to the information decoration image 236 than the first character information 235a. That is, for the information decoration image 236 displayed in light blue, for example, the second character information 235b is displayed in red, which is the opposite color, and the first character information 235a is displayed in other, for example, yellow. The display colors of the character information image 235 and the information decoration image 236 may be a single color or a plurality of colors, respectively, but in the case of a plurality of colors (including the case of being composed of a plurality of similar colors). Assuming that either the odd-numbered image data or the even-numbered image data is missing, it is desirable to configure the color information so that the types of color information are distributed more in the vertical direction than in the horizontal direction.

Further, as shown in FIGS. 91A to 91F, the character information image 235 performs a movement operation (first dynamic display) in a predetermined direction (here, leftward) along the information decoration image 236. Further, the second character information 235b of the character information image 235 is configured to perform an operation of jumping upward one character at a time (a second dynamic display different from the first dynamic display).

The second dynamic display is not limited to the upward jump operation, but is not limited to a two-dimensional rotation operation (for example, a rotation operation around an axis perpendicular to the screen) and a three-dimensional rotation operation (for example, a rotation around an axis in the vertical or horizontal direction). Any operation such as (operation that seems to rotate), deformation operation such as enlargement / reduction, etc. may be used. Assuming that either the odd-numbered image data or the even-numbered image data is missing, it is desirable that the second dynamic display is accompanied by a change in the vertical direction.

Further, as shown in FIG. 90, the character image 242b of the smooth face related to the band effect image 242a is displayed in the substantially center of, for example, the liquid crystal display means 76 separately from the band effect image 242a. The character image 242b may be displayed on the front side of the information decoration image 236 as one of the information images constituting the band effect image 242a. As described above, the display information constituting the information image is not limited to the character information, but may be a symbol, a pattern, or the like.

Further, while the button fanning image 242 is being displayed, the left and right decorative symbols 90 that have already stopped in the reach mode are reduced and displayed in the peripheral portion of the screen. While the decorative symbol 90 is changing, the mini symbol 240 corresponding to the decorative symbol 90 is always displayed on the liquid crystal display means 76.

Following the button fanning effect, an operation guidance image 231 for urging the player to operate the effect button 41 is displayed on the liquid crystal display means 76, and an operation valid period up to a predetermined time is started. The button effect is a blow button effect that executes a result effect when the effect button 41 is operated once. Therefore, the operation mode notification image 233 constituting the operation guidance image 231 is an operation mode notification image 233a composed of characters such as "PUSH" corresponding to the blow button effect.

Further, in the present embodiment, a plurality of types of operation guidance images are prepared, and the jackpot reliability is different for each. For example, in the first operation guidance image 231a shown in FIG. 92 (a), the inside of the button image 232a (excluding the operation mode notification image 233) is displayed in a single color, whereas the inside of the button image 232a (excluding the operation mode notification image 233) is displayed in a single color. In the two operation guidance image 231b, the inside of the button image 232a (excluding the operation mode notification image 233) is divided into a plurality of regions in the vertical direction and displayed in different colors, and the latter jackpot reliability is higher than the former. It has become.

As described above, the image data corresponding to the button image 232b of the second operation guidance image 231b having higher reliability is configured so that the types of color information are distributed more in the vertical direction than in the horizontal direction, so that the image data is odd. Even if either the image data or the even image data is missing, the color change is along the continuously displayed (no missing) vertical pixel line (see FIG. 83). Since the player or the like can clearly recognize the color change in pixel units, the second operation guidance image 231b can be clearly identified.

Further, in the present embodiment, with respect to the operation valid period notification image 234 constituting the operation guidance image 231, the boundary 234c between the elapsed display unit 234a and the non-progress display unit 234b moves by 2 dots or more in the left-right direction for each frame. It is configured to do. FIG. 93A shows how the boundary 234c moves to the right by 2 dots for each frame. In this case, even if either the odd-numbered image data or the even-numbered image data is missing, as shown in FIG. 93 (b), the boundary 234c surely moves every frame, so that the player can use the image data. It is possible to accurately recognize the elapse of the operation validity period as in the case of normal display without omission. As shown in FIG. 94 (a), when the movement of the boundary 234c for each frame is set to less than 2 dots, if either the odd-numbered image data or the even-numbered image data is missing, FIG. 94 (b) shows. As shown, the boundary 234c may appear to have not moved even after one frame, and the appearance of the boundary 234c is clearly different from that at the time of normal display.

When the player presses the effect button 41 during the operation valid period, the operation valid period ends at that point, and a rainbow effect meaning that the jackpot is confirmed is started (FIG. 90). In this rainbow effect, the rainbow image effect and the rainbow light emission effect are executed in parallel. In this rainbow image effect, the background image of the liquid crystal display means 76 becomes the rainbow background image 243, and the smiling character image 244 or the like is displayed on the front side of the rainbow background image 243. In the example of FIG. 90, the rainbow background image 243 is displayed in a rainbow color whose color changes in the circumferential direction around a predetermined point (here, the center point of the screen) on the screen, and the color distribution of the rainbow color is displayed. It changes clockwise with the passage of time. Further, the character image 244 is superimposed on the front side of the rainbow background image 243 so as to hide the center point (predetermined point). Further, in the rainbow light emission effect, the movable accessory lamp 314, the board lamp 324, and the frame lamp 304 each emit light in a rainbow light emission pattern (not shown).

Following the above rainbow production, the production will be performed after success. The post-success production of the present embodiment is composed of a first post-success production in the first half and a second post-success production in the second half. The first post-success production is a symbol-aligned production in which the decorative symbol 90 is stopped in a jackpot production mode such as "7, 7, 7". In this first post-success effect, neither the rainbow image effect nor the rainbow light emission effect is executed in order to draw the player attention to the pattern matching effect. That is, the background image of the liquid crystal display means 76 is switched from the rainbow background image 243 to the normal background or the background image 245 according to the effect of SP reach, and the partial image such as the decorative pattern 90 displayed on the front side thereof is also other than the rainbow color. It is displayed in the color of. Further, the movable accessory lamp 314, the panel lamp 324, and the frame lamp 304 emit light in a normal light emitting pattern other than the rainbow light emitting pattern corresponding to the image of the liquid crystal display means 76.

The second post-success production that follows the first post-success production is a blessing production that congratulates the establishment of the jackpot production mode. In this second post-success effect, only the rainbow light emission effect is executed out of the rainbow image effect and the rainbow light emission effect. That is, the liquid crystal display means 76 displays the blessing image 246 and the like in addition to the image of the decorative symbol 90 and the like at the time of the first successful post-production. The blessing image 246 is composed of a character image or the like having a content of congratulating the big hit effect such as "Congratulations", but is displayed in a normal color other than the rainbow color. On the other hand, the movable accessory lamp 314, the board lamp 324, and the frame lamp 304 again emit light by the rainbow light emission pattern.

In this second successful post-effect, both the rainbow image effect and the rainbow light emission effect may be executed. As an example of the rainbow image production in this case, it is conceivable that at least a part of the blessing image 246, for example, only the characters "Congratulations" are used as the rainbow. 95 and 96 (a) show an example in which the inside of the character “Congratulations” in the blessing image 246 is displayed in rainbow colors in the second composite execution mode. In the example of FIG. 95, the color information changes continuously (may be stepwise) in the vertical direction (the color information changes continuously or stepwise with respect to the position), but with respect to time. The display color does not change. In this way, by setting the change direction of the color information in the rainbow image (gradient image) to the vertical direction, even if either the odd image data or the even image data is missing, the color change of the rainbow is normal. It is along the displayed vertical pixel line, and the player can clearly recognize the color change in pixel units, so that the rainbow image can be reliably identified as in the normal display. This effect is particularly useful when a narrow area such as the inside of a character is used as a rainbow as shown in FIG. 95.

Further, in the example of FIG. 96 (a), the color information changes continuously (may be stepwise) in the left-right direction (the color information changes continuously or stepwise with respect to the position). The display color does not change with time. Further, in this case, as shown in FIG. 96 (b), the inside of the character "Congratulations" has substantially the same color information for each set of pixel lines adjacent to the left and right, that is, a plurality of types set to odd-numbered image data. The color information of is substantially common to the plurality of types of color information set in the even image data to the right of the above. This allows the player to clearly identify the rainbow image even if either the odd-numbered image data or the even-numbered image data is missing.

Subsequently, the jackpot effect control means 95e (FIG. 79) will be described. The jackpot effect control means 95e controls the jackpot middle effect performed during the jackpot game. For example, during the jackpot start interval, the jackpot round (including the inter-round interval), and the jackpot end interval, the effect corresponding to them is performed. The image is displayed on the liquid crystal display means 76, and the audio output, lamp light emission, movable body drive, and the like are executed accordingly.

In the present embodiment, it is possible to execute a setting suggestion effect that suggests a set value (any of settings 1 to 6) regarding the jackpot probability during the jackpot end interval. In this setting suggestion effect, the set value is suggested by the display color of the predetermined image (here, the character image of "probability change mode entry") displayed on the liquid crystal display means 76 during the jackpot end interval. Five colors of black, blue, yellow, red, and rainbow are prepared as display colors of "probability change mode entry", and one of these five colors is selected by lottery based on the setting suggestion effect selection table shown in FIG. 97. Be selected. The selection process regarding whether or not to execute this setting suggestion effect and the type (character color) when executing it is performed at an arbitrary timing such as at the start of the jackpot game or at the start of the jackpot end interval. In addition, since it is necessary to display the character of "probability change mode entry" in this setting suggestion effect, it is executed only in the case of the probability change big hit, but at the start of the big hit end interval at the time of non-probability change big hit, "time reduction". Characters such as "mode rush" may be displayed to perform a setting suggestion effect.

In the setting suggestion effect selection table shown in FIG. 97, the fractions for the five colors of black, blue, yellow, red, and rainbow are set for each of the settings 1 to 6. As is clear from this setting suggestion effect selection table (FIG. 97), in the setting suggestion effect, black is likely to be all settings 1 to 6, but is likely to be settings 1 to 3 (low setting). , Blue suggests that it is not setting 1 (minimum setting), yellow suggests that it is one of settings 4 to 6 (not a low setting), and red suggests that it is one of settings 5 and 6. It suggests that it is (high setting), and that the rainbow color (rainbow effect) is setting 6 (highest setting).

In this way, the rainbow effect (rainbow color effect) in which the characters of this "probability change mode entry" are rainbow-colored is to inform the player that the setting 6 is advantageous to the player, and appears during the above-mentioned symbol change. Unlike the rainbow effect, it does not notify the confirmation of the big hit, but it is common in that it notifies the confirmation of the state advantageous to the player.

When the setting suggestion effect is performed during the jackpot end interval, the operation valid period up to a predetermined time is started with the characters (for example, black) of "probability change mode entry" displayed on the liquid crystal display means 76. (Fig. 98 (a)). During the operation valid period, the operation guidance image 231 for urging the player to operate the effect button 41 is displayed on the liquid crystal display means 76 so as not to overlap with the characters of, for example, "probability change mode entry". Then, when the effect button 41 is operated during the operation valid period, the operation valid period ends at that time, and the characters of "probability change mode entry" displayed on the liquid crystal display means 76 are displayed according to the set value. Changes to the selected display color (no change if black is selected). In the case of FIG. 98, since the character of "probability change mode entry" has changed from black (FIG. 98 (a)) to rainbow color (FIG. 98 (d)), the player has the highest setting value at that time. It can be known that the setting is 6.

Further, regarding the color change (here, black → rainbow) of the character of this “probability change mode entry”, as shown in FIGS. 98 (a) to 98 (d), gradually in the vertical direction (here, downward) over a plurality of frames. It is supposed to progress. As a result, the player can clearly identify the color change of the character of "probability change mode entry" regardless of whether the odd-numbered image data or the even-numbered image data is missing. In addition, the color change of the character of this "probability change mode entry" may be configured to proceed in the left-right direction. In that case, it is desirable to change the color information by 2 dots or more in the horizontal direction for each frame. As a result, the player can clearly identify the color change of the character of "probability change mode entry" regardless of whether the odd-numbered image data or the even-numbered image data is missing.

If the operation validity period expires without the effect button 41 being operated, the character color of "probability change mode entry" may be changed at that time, or the color may be changed regardless of the selected color type. You may not perform this, or you may end the display of the characters "Enter probabilistic mode" when the operation validity period has expired.

Further, in the example of FIG. 98 (d), the characters of "probability change mode entry" have a rainbow-colored gradation, but the gradation image is stepwise (or continuous) in the left-right direction (relative to the position). Not only is the color information changing, but the color information is also changing stepwise (or continuously) with time. As for the change of the color information with respect to the time, as shown in FIG. 99A, the color information is moved to the right by 2 dots for each frame. The odd-numbered image data and the even-numbered image data corresponding to the gradation image are both changed from the color information before the change to the color information after the change. As a result, the width of each color is the same when odd-numbered image data is missing and when even-numbered image data is missing, and it is possible to express almost the same gradation as when normal (when there is no missing), and odd numbers. Regardless of whether the image data or the even image data is missing, the player can clearly identify the color change of the gradation image.

Note that FIG. 99 (b) shows a case where each color information is moved to the right by 1 dot for each frame, and FIG. 99 (c) shows a case where each color information is moved to the right by 3 dots for each frame. FIG. 99 (d) shows a case where each color information is moved to the right by 4 dots for each frame. In the case of FIG. 99 (b) (moving by 1 dot), the color change cannot be accurately expressed when odd-numbered image data is missing as shown by ○, and in the case of FIG. 99 (c) (moving by 3 dots). In (movement), there is a difference between the case where the odd-numbered image data is missing and the case where the even-numbered image data is missing in the portion indicated by ◯.

On the other hand, in the case of FIG. 99 (d) (moving by 4 dots), as in the case of FIG. 99 (a) (moving by 2 dots), there are cases where odd-numbered image data is missing and cases where even-numbered image data is missing. The width of each color is common, and it is possible to express a gradation that is almost the same as when it is normal (when there is no omission). That is, for a gradation image whose color information changes with respect to position and time, it is possible to configure the gradation image so that two or more even dots move in the left-right direction (the arrangement direction of odd pixels and even pixels) for each frame. desirable.

In this way, when the preview image is dynamically displayed, either the odd-numbered image data or the even-numbered image data is missing by changing two or more dots in the left-right direction (arrangement direction of odd-numbered pixels and even-numbered pixels) for each frame. Even in this case, it is desirable that the preview image is configured to change for each frame, but for example, it may be configured to change in the vertical direction. In this case, regardless of the magnitude of the change for each frame, even if either the odd-numbered image data or the even-numbered image data is missing, the preview image can be configured to change for each frame. Is. Further, the dynamic display in this case includes not only the temporal change of the gradation but also the movement operation of the preview image in a predetermined direction.

FIG. 100 exemplifies the second embodiment of the present invention, and partially modifies the first embodiment to display the first dynamic display with respect to the first display information and the second display information in the band effect image. Is shown, an example is shown in which a second dynamic display different from the first dynamic display is sequentially executed for the first display information and the second display information.

The band effect image 242a of the present embodiment is different from the first embodiment in the first embodiment, as shown in FIG. 91, for the first character information (first display information) 235a. Only the dynamic display (movement operation to the left) is executed, and for the second character information (second display information) 235b, the second operation display (upward movement operation) is performed in addition to the first dynamic display (movement operation to the left). In contrast to the execution of the jump operation), in the present embodiment, as shown in FIG. 100, the second operation display (upward jump operation) is changed to the first character information (first display information) 235a and the second character information (upward jump operation). Second display information) It is only a point to execute sequentially for 235b.

That is, in the band effect image 242a of the present embodiment, as shown in FIGS. 100 (a) to 100 (g), the character information image 235 is moved in a predetermined direction (here, leftward) along the information decoration image 236. An operation (first dynamic display) is performed, and an operation of jumping upward with respect to the first character information 235a and the second character information 235b constituting the character information image 235 (first dynamic display). A different second dynamic display) is performed. In the example of FIG. 100, the second dynamic display of the first character information 235a is performed simultaneously for all characters, whereas the second dynamic display of the second character information 235b is performed character by character in order. It has become like. Of course, the second dynamic display of the first character information 235a may be performed one character at a time, or the second dynamic display of the second character information 235b may be performed simultaneously for all characters. May be good.

The second dynamic display is not limited to the upward jump operation, but is not limited to a two-dimensional rotation operation (for example, a rotation operation around an axis perpendicular to the screen) and a three-dimensional rotation operation (for example, a rotation around an axis in the vertical or horizontal direction). Any operation such as (operation that seems to rotate), deformation operation such as enlargement / reduction, etc. may be used. Assuming that either the odd-numbered image data or the even-numbered image data is missing, it is desirable that the second dynamic display is accompanied by a change in the vertical direction. Further, the second dynamic display for the first character information 235a and the second dynamic display for the second character information 235b may be different from each other.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, in the liquid crystal control board 98 of the embodiment, an example in which the composite chip 104 and the liquid crystal control second connector CN32 are arranged in different wiring layers is shown, but the liquid crystal control second connector CN32 is the same wiring layer as the composite chip 104 (A). It may be arranged in the wiring layer). In this case, of the ODD side data output terminal group (first chip terminal) and the EVEN side data output terminal group (second chip terminal), the first chip terminal arranged on the outer peripheral side of the composite chip 104 is drawn out. The first wiring path is connected to the liquid crystal control second connector CN32 on the instep wiring layer side without passing through the interlayer conduction portion, and the second wiring path connected to the other second chip terminal is of the second chip terminal. It temporarily moves to the B wiring layer side via a via (non-specific interlayer conduction portion) arranged in the vicinity, and further moves to the A wiring layer side via a via (specific interlayer conduction portion) arranged in the vicinity of the liquid crystal control second connector CN32. It may be configured to return to the side and connect to the liquid crystal control second connector CN32. As a result, even when the liquid crystal control second connector CN32 is arranged in the same wiring layer (instep wiring layer) as the composite chip 104, the first wiring path is arranged so that the wiring ratio to the instep wiring layer is the highest. The second wiring path can be arranged so that the wiring ratio to the B wiring layer is the highest.

In this way, when the first chip terminal is arranged on the outer peripheral side of the chip rather than the second chip terminal, the first wiring path connected to the first chip terminal is the instep wiring in which the chip is arranged. Arrange so that the wiring ratio to the layer is the highest, and arrange the second wiring path connected to the second chip terminal so that the wiring ratio to the B wiring layer different from the A wiring layer is the highest. Is desirable.

In the embodiment, an example is shown in which the hold notification image is configured to perform dynamic display accompanied by a change in the vertical direction, but this dynamic display is not limited to movement or deformation, and they are not limited to movement or deformation. At the same time, or instead of them, a color change in the vertical direction (for example, the color distribution may move in the vertical direction with the passage of time) may be performed.

Further, for example, when the display mode changes after the display of the hold notification image is started (for example, from ○ to an elephant, from an elephant to a lion, etc.), for example, the color information is gradually switched downward from the upper side, and the color information is displayed at least in the vertical direction. It is desirable to change. This also applies to the case where the display mode of other preview images is changed.

When displaying the operation target image such as the button image 232, the dynamic display may be executed for the operation target image. As the dynamic display in this case, a moving operation or a deforming operation indicating how the operation target image is operated can be considered, but the dynamic display in that case may also be accompanied by a change in the vertical direction. desirable.

In the embodiment, the band effect image is configured to be displayed in the button fanning effect, but the band effect image can be displayed in all kinds of effects. For example, in the setting suggestion effect shown in FIGS. 97 and 98, a band effect image may be displayed in which the characters of "probability change mode entry" are used as information images.

The information image constituting the band effect image is not limited to the character information, but may be a symbol, a pattern, or the like, or may be mixed. Further, the information decoration image constituting the band effect image may be an image arranged along the information image, and is not limited to a straight band-shaped image having a constant width, even if the width (thickness) changes. It may have a curved shape or a polygonal line shape. Further, the arrangement is not limited to the left-right direction, and may be arranged in an oblique direction such as a vertical direction, an upward movement to the right, or a downward movement to the right, or may be arranged in a plurality of rows.

In the embodiment, an example in which the character information image 235 moves to the left as the first dynamic display is shown, but the first dynamic display is not limited to this, and the reciprocating movement to the left-right direction, the left-right direction, etc. It may be enlarged / reduced to or other transformations. Further, the second dynamic display may be different from the first dynamic display, and may be a two-dimensional rotation operation (for example, a rotation operation around an axis perpendicular to the screen) and a three-dimensional rotation operation (for example, vertical direction or left / right direction). Any operation such as (operation that seems to rotate around the axis in the direction), deformation operation such as enlargement / reduction, etc. may be used. Assuming that either the odd-numbered image data or the even-numbered image data is missing, it is desirable that the first and second dynamic displays are accompanied by a change in the vertical direction, but when the change is in the horizontal direction. It is desirable to configure it so that it changes by 2 dots or more for each frame.

In the embodiment, as an example of the first rainbow-colored image effect performed before the winning branch effect of whether or not to grant the privilege, an example of displaying the characters "Congratulations" in rainbow color is shown. The rainbow image in the rainbow color image production is not limited to this, and any partial image such as characters, figures, and characters can be used as the rainbow image. FIG. 101 (a) is an example in which the star-shaped figure 261 displayed during the reach effect is a rainbow image, and FIG. 101 (b) is an example in which the reach title character 262 displayed at the start of SP reach B is a rainbow image. Each example is shown.

In FIG. 101, in the star-shaped figure 261 and the reach title character 262, the color information is changed in the left-right direction, but considering the case where either the odd-numbered image data or the even-numbered image data is missing, the color information is It is desirable that the change direction is the vertical direction. Further, when the change direction of the color information is the left-right direction, it is desirable that the color information is substantially common to each set of pixel lines adjacent to the left and right (see FIG. 96 (b)).

The rainbow image effect described above displays a rainbow-colored image that covers the seven colors of red, orange, yellow, green, blue, indigo, and purple, but displays a gradation image that includes non-rainbow-colored ones. It may be used as a gradation image effect.

It is desirable not to perform the rainbow effect in the look-ahead notice effect. This is because if the rainbow effect is performed with a fluctuation before the target fluctuation that is the target of the look-ahead determination, the player mistakenly recognizes that the fluctuation will be a big hit. However, if the target of the rainbow effect is a clear look-ahead notice effect, the rainbow effect may be performed. For example, in the hold change effect, a rainbow effect in which the hold image corresponding to the target change is used as the rainbow image can be executed.

In the embodiment, for the wiring paths P2 to P42 for transmitting address information / data information between the composite chip 104 and the control ROM 105, the specific interlayer conduction portion arranged in the control ROM arrangement area (second arrangement area) 192. However, at least a part of those wiring paths P2 to P42 may not have a specific interlayer conduction portion.

In the embodiment, in the wiring paths P2 to P42, the arrangement of the vias v61 to v85 and v87 to v102 (specific interlayer conduction portion) in the Y direction is arranged in the corresponding terminals of the liquid crystal control first connector CN31 from had1 to had25 and hdt0 to. Although it is matched with the arrangement in the X direction of hdt15, the arrangement in the Y direction of vias v61 to v85 and v87 to v102 (specific interlayer conduction portion) may be matched (or approximated) with the terminal arrangement of the control ROM 105.

In the embodiment, regarding the test points that need to be checked with the board assembled, the check target is on the outer surface of the board with the board assembled, regardless of whether the check target is on the front or back of the board. Although it is configured to display the identification information of the test points, the identification information may be displayed on both sides of the substrate for such test points.

In the embodiment, among the terminals of the composite chip 104, the terminals (outer terminals) arranged in the outermost peripheral side of the composite chip placement region (first placement region) 191 and the innermost second row thereof are the first wiring layer. The terminal (inner terminal) inside the interlayer conduction portion connected to the interlayer conduction portion arranged outside the composite chip arrangement region 191 in La1 was arranged inside the composite chip arrangement region 191 in the first wiring layer La1. Although it is configured to be connected to the interlayer conduction portion, only the terminal on the outermost peripheral side in the composite chip arrangement region 191 may be used as the outer terminal, or the terminal from the outermost peripheral side to the third row may be used as the outer terminal.

Further, in the embodiment, only the wiring related to the terminal on one edge side of the composite chip 104 is specifically exemplified, but the present invention is not limited to this, and the same configuration or embodiment is also used on the other edge side of the composite chip 104. It may be configured so as to have the contents described in. As described above, by adopting the configuration described in this embodiment also on each edge side of the composite chip 104, it is possible to further improve the wiring efficiency. For example, the configuration shown in FIG. 20 can be given as an example.

In the embodiment, an example in which the first to sixth wiring layers La1 to La6 are provided on the liquid crystal control substrate 98 is shown, but the number of wiring layers may be smaller or larger than this. When reducing the number of wiring layers, the solid wiring layer for ground connection and the solid wiring layer for power supply connection may be omitted.

With respect to the connection between the terminal of the composite chip 104 and the via in the composite chip arrangement area 191, the distance between each terminal and each via may be designed to be substantially the same distance. As a result, the distances between the plurality of terminals and the vias are approximately equal to each other, so that noise is less likely to occur and the arrangement of the vias can be arranged in a more appropriate state.

Further, regarding the direction of drawing out the wiring from the terminal of the composite chip 104 toward the via, it is desirable that the wiring drawing out direction (via arrangement direction) is common to the terminals adjacent to each other in the vertical and horizontal directions. Further, when those terminals are regarded as a group, it is desirable that the wiring lead-out direction (via arrangement direction) is different from the above-mentioned direction for the terminal group different from the terminal group. By setting the wiring pull-out direction (via placement direction) for each terminal group in this way, it is easy to check and recognize the information of each terminal by the wiring pattern, so it is easy to inspect and check after completion. Become. Further, by grouping the terminals for transmitting the address information or grouping the terminals for transmitting the data information as a group, the above-mentioned effect can be further exhibited. Further, with respect to the terminals of individual signals such as chip select signals, vias may be provided in a wiring lead-out direction different from that of the above-mentioned group to facilitate confirmation and recognition. Further, by providing vias in the common wiring lead-out direction for the chip select signal terminals, it may be difficult to identify important terminals such as chip select signals and signal lines, and the configuration may be resistant to fraudulent activities.

As shown in FIG. 34, a wiring pattern may be provided so as to reach within or near the control ROM arrangement area 192 without via vias, such as the wiring path cp221 connected to the HAD22 terminal of the composite chip 104. By wiring in this way, the number of vias around the composite chip 104 can be reduced, so that the space can be used as a place for installing other wiring and vias. Further, although the wiring path cp221 is connected to the via v53, the wiring path cp221 is not limited to this, and may be configured to be connected to the terminal of the control ROM 105 without going through the via.

As shown in FIG. 35, address information and data information are transmitted for wiring patterns of special terminals such as OE #, WE #, BYTE #, WP # ACC, CE #, and SETT # among the terminals of the control ROM 105. The connection distance from the via may be set shorter than the wiring pattern. As a result, it is possible to easily distinguish the types of wiring patterns at the time of assembling the board, at the time of inspection, and the like. On the contrary, by setting a long connection distance, it may be configured so that the types of wiring patterns can be easily distinguished. Further, since it is a terminal connection pattern for controlling the operation of the control ROM 105, it is desirable to set a relatively short wiring pattern in consideration of noise and the like.

As shown in FIG. 35, in the control ROM arrangement area 192, the first via arrangement group (v61 to v85, etc.) and the second via arrangement group (v87 to v102, etc.) are arranged so as to be offset in the X-axis direction. It is possible to easily draw out the wiring pattern from each array group in the Y-axis direction. If the first via array group and the second via array group are arranged in the Y-axis direction without shifting in the X-axis direction, they will not fit in the control ROM arrangement area 192 and will protrude in the X-axis direction. By arranging them so as to be offset in the Y-axis direction, the first via arrangement group and the second via arrangement group can be accommodated in the control ROM arrangement area 192, and the wiring space in the control ROM arrangement area 192 can be further reduced. It will be possible to utilize it effectively.

Further, even if the first via array group and the second via array group are shifted in the Y-axis direction and arranged so as to overlap each other in the X-axis direction, if they fit within the control ROM arrangement area 192, they are shifted in the Y-axis direction. They may be arranged so as to overlap in the X-axis direction. In this case, it becomes difficult to draw out the wiring pattern from each array group in the Y-axis direction, but at least the drawing out in the X-axis direction is not limited. Further, for example, when the first via array group or the second via array group is a branching point, the arrangement of the connection terminals at the branch destination is taken into consideration, and the sequences are arranged so as to be shifted in the Y-axis direction and overlapped in the X-axis direction. If the arrangement is more efficient, it may be configured as such. Similarly, they may be arranged so as to be offset in the X-axis direction and overlap in the Y-axis direction. Depending on the shape of the control ROM placement area 192 and the way in which the wiring pattern is routed, it may be more suitable for the placement relationship.

As shown in FIG. 28, the physical connection distance is determined by determining the arrangement relationship between the composite chip 104 and the control ROM 105 according to the position of the terminal arrangement of the composite chip 104 having a connection relationship with the terminal of the control ROM 105. It may be configured to be close to each other. This is not particularly limited to the control ROM 105, and the wiring efficiency is improved by determining the arrangement position, arrangement direction, distance, etc. of the electronic components connected to those terminals based on the position of each terminal of the composite chip 104. be able to. Of course, the above-mentioned arrangement relationship may be used only for a specific electronic component such as the control ROM 105, whereby the partial wiring efficiency can be improved, but more preferably, a plurality of electronic components have the same arrangement relationship. By doing so, the wiring efficiency of the entire board can be improved.

Further, for wiring that requires connecting the composite chip 104 and a plurality of electronic components, such as a wiring pattern for transmitting address information and data information, the first electronic component having a short distance from the composite chip 104 (eg, control). Wiring efficiency is achieved by providing the first electronic component, which is closer to the ROM 105) and the second electronic component farther away (eg, the liquid crystal control first connector CN31), on the side where the connection terminal of the composite chip 104 is located. May be increased. Needless to say, the wiring efficiency can be further improved by providing both the first electronic component and the second electronic component farther away from the first electronic component on the side where the connection terminal of the composite chip is located. Further, the wiring efficiency may be improved by providing the distant second electronic component of the first electronic component and the second electronic component on the side where the connection terminal of the composite chip 104 is located. In this case, the first electronic component is arranged on a side different from the side where the connection terminal of the composite chip is located, which may seem inefficient at first glance, but wiring for transmitting address information and data information on the entire board. When considering the wiring efficiency of the pattern, it may be more effective. Further, the first electronic component is not limited to the control ROM, and may be a connector, a (terminating) resistor, or the like. Similarly, the second electronic component is not limited to the connector, but may be a control ROM or a (terminating) resistor.

As shown in FIG. 27, the terminal of the control ROM 105 has a terminal (NC terminal or the like) that is not connected to the terminal of the composite chip 104, and in FIG. 35 (although the NC terminal or the like is omitted here), the control is performed. Vias for connecting wiring patterns that are connected to terminals other than NC terminals to locations (areas) that are displaced in the X-axis direction with respect to locations in the ROM layout area 192 where the NC terminals of the control ROM 105 are located (FIG. 35). In the above, v80 to v85 and the like may be provided). The reason for this configuration is that NC terminals and the like do not need to consider the wiring pattern to be connected and the arrangement of vias, so wiring space tends to be relatively likely to occur around them, so that area is utilized. This is because the via can be placed. Further, since there is enough space around the NC terminal or the like, there is an advantage that the wiring pattern from the via can be easily drawn out in the Y-axis direction or the X-axis direction. Further, not only the NC terminal but also the VCS terminal and the GND terminal have the same configuration, so that the above-mentioned effect can be obtained.

As shown in FIG. 40, vias (eg, v49 to v54) for connecting the wiring pattern for connecting the terminal of the composite chip 104 and the terminal of the control ROM 105 are placed near or around the outside of the control ROM arrangement area 192. By providing and configuring the wiring pattern so as to be routed in the control ROM arrangement area 192 via the via, the via can be visually recognized from the outside of the board without being shielded by the control ROM 105 or the like, so that the control ROM is arranged. Compared with a wiring pattern in which a via is not provided near or around the outer side of the area 192, it becomes easier to check and inspect the wiring pattern connecting the terminal of the composite chip 104 and the terminal of the control ROM 105, and the control ROM arrangement area 192 Wiring efficiency can be further improved by arranging vias near the outside.

As shown in FIGS. 35 and 37, the vias v69 to v73 are arranged and arranged in the control ROM arrangement area 192 together with other vias, but the vias v103 to v107 are arranged in connection with the terminals of the control ROM 105. It is configured to draw out the wiring pattern to the control ROM arrangement area 192 via the above. In this way, the wiring pattern for connecting the vias (v69 to v73) arranged together with the other specific interlayer conduction portions and the terminals of the control ROM 105 is set in the control ROM arrangement area 192 via another via (v103 to v107). It can be configured to improve the wiring efficiency by routing. Further, even in that case, since the vias v69 to v73 are arranged in the same manner as the other vias, it is possible to relatively easily perform inspections such as confirmation of connection relationship and energization check.

In the embodiment, the composite chip 104 of VDP + CPU is exemplified, but a CPU chip having no VDP function may be used. Further, the control ROM is not limited to the storage medium for storing the control program of the CPU, and may be a ROM for storing audio data and image data.

Vias located in the composite chip placement area 191 and the control ROM placement area 192 may be used as test points for continuity check. In this case, it is desirable to configure the test point notation (display of identification information) by silk printing in the vicinity or the periphery of the via located in the composite chip arrangement area 191 or the control ROM arrangement area 192. As a result, the continuity check of the composite chip 104 and the control ROM 105 can be easily performed, and the silk-printed notation of the test point can be arranged by utilizing the composite chip placement area 191 and the control ROM placement area 192.

As shown in FIG. 55, by connecting the SRESET signal and the WTDOG signal to the common logic integrated circuit IC7, it is possible to appropriately perform the reset process when the reset signal is input due to any reset factor. It has become. Further, the output information (reset signal) from the logic integrated circuit IC7 is output not only to the composite chip 104 and / or the control ROM 105, but also to the decoders IC13 and IC14 shown in FIG. 54 (FIG. 55). By configuring the system so as to output from the IO-RST of the above, it is possible to execute the reset process for the liquid crystal display means 76. As a result, it is possible to realize a synchronous or substantially the same timing reset operation by hardware such as different electronic components.

Further, in order to reset an external ROM such as a CG ROM or an audio ROM, a reset signal may be separately output to the composite chip 104 (output from the DDR-RST of FIG. 55). As described above, even if the output target is the same composite chip 104, it may be configured to output a different reset signal for each reset target. As a result, the circuit configuration can be configured so that the reset process can be performed according to the reset target and the reset purpose. Further, as shown in FIG. 55, the IO-RST signal and the DDR-RST signal are also signals output from the logic integrated circuit IC7, and the SRESET signal and / or the WTDOG signal are logical as in the CPU-RST signal. It is a signal output to the trigger that it is input to the integrated circuit IC7.

Further, although the common logic integrated circuit IC7 is used in the embodiment, the present invention is not limited to this, and a plurality of logic integrated circuits may be provided. In this case, a different logic integrated circuit may be used for each of the CPU-RST signal, IO-RST signal, and DDR-RST signal, or the CPU-RST signal and the IO-RST signal and DDR-RST signal are different. It may be configured to use a logic integrated circuit. When a plurality of logic integrated circuits are used in this way, although it is costly, it is possible to prevent the reset signal from being output to all the hardware due to a defect. Even in this case, a common SRESET signal and / or a WTDOG signal is input to different logic integrated circuits.

As shown in FIG. 27, the terminal of the control ROM 105 has a terminal (NC or the like) that is not connected to the terminal of the composite chip 104, and the control ROM is arranged in FIG. 35 (although the NC terminal or the like is omitted here). A location (area) shifted in the X-axis direction with respect to the location of the NC terminal of the control ROM in the region 192, and a location (region) shifted in the X-axis direction with respect to the location of the terminal other than the NC terminal. Therefore, the number of vias installed in the control ROM arrangement area 192 may be different. In this way, by making the number of vias arranged different for each corresponding place (area), the space in the control ROM arrangement area 192 may be effectively utilized. In addition, as a matter of course, the wiring pattern drawn from the via is connected to the terminals other than the NC terminal, so there is an advantage that the connection distance becomes shorter when arranging in the vicinity, and conversely, the NC terminal is located. When the wiring pattern drawn from the via drawn from the place (region) shifted in the X-axis direction is connected to the place to be connected, the connection distance becomes long, but the wiring space is relatively large. , There is a merit that it becomes easy to route.

Further, among the vias in the control ROM arrangement area 192, vias that are not directly connected to the terminals of the control ROM (eg, a plurality of vias located between v68 and v74 in FIG. 35) are as shown in FIG. In addition, it may be provided in a place (region) shifted in the X-axis direction with respect to a place where a terminal other than the NC terminal is located. This is because the wiring pattern is not drawn out from these vias on the first wiring layer La1, so that there is little possibility of hindering the wiring space in the control ROM arrangement area 192. On the contrary, it may be provided in a position (area) shifted in the X-axis direction with respect to the position where the NC terminal of the control ROM 105 is located in the control ROM arrangement area 192. In this case, a wiring space can be provided by a portion (region) shifted in the X-axis direction with respect to a location where a terminal other than the NC terminal is located. In any case, in the embodiment, the via arrangement as shown in FIG. 35 is constructed while considering the above-mentioned merits and considering the connection relationship with electronic components (eg, connector) other than the control ROM. ing.

In the example of FIG. 35, vias for conducting wiring patterns for transmitting address information are arranged in a predetermined array, and vias for conducting wiring patterns for transmitting data information are arranged in a predetermined array. The via arrangement is installed so as to be a group, but the via is not limited to this, and the via that conducts the wiring pattern for transmitting address information and the via that conducts the wiring pattern for transmitting data information are arranged in a predetermined arrangement. They may be installed so as to form one via group by arranging them side by side. In this case, since the vias that conduct the wiring patterns that transmit different information can be densely packed, the installation range of the vias can be made relatively small. Further, as in the vias v87 to v90 shown in FIG. 35, some vias may be arranged as a small group in the array of vias for conducting the wiring pattern for transmitting data information. The same configuration may be used for vias that conduct a wiring pattern for transmitting address information.

In the example of FIG. 35, vias for conducting a wiring pattern for transmitting address information and vias for conducting a wiring pattern for transmitting data information are arranged in a predetermined arrangement in the control ROM arrangement area 192. However, the vias may be arranged in a predetermined arrangement outside the control ROM arrangement area 192. In this case, the control ROM arrangement area 192 cannot be utilized, but since the wiring pattern is connected from the outside of the control ROM arrangement area 192 to the terminal of the control ROM 105, check the connection status for each terminal of the control ROM. There is a merit that it becomes easier. However, since the required wiring space is relatively large as compared with the case where the control ROM arrangement area 192 is used, it is desirable to adopt such a configuration when there is a relatively large space.

As shown in FIG. 35, regarding the wiring pattern of special terminals such as OE #, WE #, BYTE #, WP # / ACC among the terminals of the control ROM 105, the wiring pattern is from the outside of the control ROM arrangement area 192 to the terminals. May be configured to make it easier to check the connection status by connecting. Further, CE # and SETET # may have the same configuration. However, in the embodiment, CE #, which is a chip select input terminal for inputting a chip select signal, and RESET #, which is a reset terminal for inputting a reset signal, are likely to be subject to problems and problems, and therefore are wired. The wiring pattern is connected to each terminal from the control ROM arrangement area 192 so that the pattern is not tampered with.

As shown in FIG. 34, with respect to the terminals of the composite chip 104 and the vias in the composite chip arrangement area 191, the composite chips are similar to the terminals of the composite chips linearly arranged in the Y-axis direction (and / or the X-axis direction). By arranging the vias in the arrangement area 191 so as to be aligned linearly in the Y-axis direction (and / or the X-axis direction), it is easy to check the arrangement of each terminal and the arrangement of the vias, and also to make it easier to check the space. Vias can be arranged in an aligned manner in the composite chip arrangement area 191 with a small margin.

Further, as shown in FIG. 34, the terminals of the composite chip 104 linearly arranged in the Y-axis direction (and / or the X-axis direction) and the vias linearly arranged in the Y-axis direction (and / or the X-axis direction). It is desirable to arrange them so that they do not overlap each other in the Y-axis direction (and / or the X-axis direction). With such a configuration, the vias can be arranged while avoiding terminals located next to each other or in the vicinity, for example, so that the wiring pattern from the vias can be easily arranged.

Further, as shown in FIG. 34, the via in the composite chip placement region 191 is an outer terminal (eg, HAD18, HAD14, HAD10, HAD6, HAD21, HDT12, HDT7, HDT4) arranged in the vicinity of the outer periphery of the composite chip placement region 191. , HDT0) and / or terminals arranged inside it (eg, HAD17, HAD13, HAD9, HAD5, HAD22, HDT13, HDT8, HDT5, HDT1) and each overlap in the X-axis direction (and / or Y-axis direction). It is desirable to arrange them in a position where they do not become. As a result, the vias can be arranged while avoiding the outer terminals and / or the terminals arranged inside the outer terminals, so that the wiring pattern from the vias can be easily arranged. That is, if the vias are arranged avoiding the outer terminal and / or the terminal arranged inside the outer terminal in the first wiring layer La1, the outer terminal and / or the inner side thereof are obtained when the wiring pattern is drawn from the via in different wiring layers. It is possible to draw out the wiring pattern linearly in the X-axis direction (and / or the Y-axis direction) without worrying about the terminals arranged in.

Further, the outer terminals (eg, HAD18, HAD14, HAD10, HAD6, HAD21, HDT12, HDT7, HDT4, HDT0) arranged near the outer periphery of the composite chip arrangement area 191 shown in FIG. The first specific via (eg, v18 to v18) is related to a via (eg, V11 to V24, etc.) arranged so as to avoid terminals (eg, HAD17, HAD13, HAD9, HAD5, HAD22, HDT13, HDT8, HDT5, HDT1). For v24) and the second specific via (eg v11 to v17) located inside the composite chip 104 than the first specific via, avoid the outer terminal and / or the terminal arranged inside the outer terminal. As a result, the first wiring layer La1 is arranged so as to overlap each other in the X-axis direction. In this case, the second specific via located inside the composite chip 104 than the first specific via is, for example, in a wiring layer different from the first wiring layer La1 as shown in FIG. 40. 1 The wiring pattern may be configured to avoid a specific via. In this way, the plurality of wiring layers are used and arranged inside the composite chip arrangement area 191 so as to avoid the outer terminals arranged near the outer periphery of the composite chip arrangement area 191 and / or the terminals arranged inside the outer terminals. A first specific via or a second specific via may be provided, and a wiring pattern drawn from the second specific via may be provided so as to avoid the first specific via. This makes it possible to efficiently draw out the wiring pattern from the inside of the composite chip arrangement area 191 where the wiring space is relatively small to the outside of the composite chip arrangement area 191. Further, here, a specific terminal or a specific via is shown as an example based on FIGS. 34 and 40, but the present invention is not limited to this, and other terminals and vias may have the same configuration. For example, in FIG. 34, the one edge side of the composite chip 104 is taken as an example, but the other edge side may have the same configuration. Further, when the first wiring layer La1 in the composite chip arrangement area 191 has a relatively large wiring space, the first specific via is moved in the X-axis direction (and / or the Y-axis direction) in the first wiring layer La1. It may be configured to install a second specific via to avoid it.

As described above, the vias in the composite chip arrangement region 191 shown in FIG. 34 are arranged so as to be linearly arranged in the Y-axis direction (and / or the X-axis direction), and as a matter of course, it is shown in FIG. 40. Even in different wiring layers, the vias in the composite chip arrangement region 191 are arranged linearly in the Y-axis direction (and / or the X-axis direction). Here, the first via (example: v21), the second via (example: v14) located inside the composite chip placement region 191 from the first via, and the inside of the composite chip placement region 191 from the second via. There is a third via (eg v6) located in, the first via travels out of the composite chip placement area 191 by a wiring pattern drawn linearly in the X-axis direction, and the second via is the first via. The first wiring pattern drawn linearly in the X-axis direction through the wiring pattern drawn out for the first distance in the direction avoiding the above and the control ROM 105 to be connected are linearly drawn out in the direction in which the control ROM 105 is located. The two wiring patterns proceed to the outside of the composite chip arrangement area 191 and the third via is drawn out by the first distance in the direction of avoiding the first via and / or the second via (avoid the first via from the second via). A wiring pattern drawn linearly in the Y-axis direction (the same direction as the wiring pattern drawn out by the first distance in the direction) and a wiring pattern drawn out linearly in the Y-axis direction (the wiring pattern length up to this point is the first in the direction of avoiding the first via from the second via). The first wiring pattern drawn linearly in the X-axis direction and the control ROM 105 to be connected are drawn linearly in the direction in which the control ROM 105 is located. It is configured to proceed to the outside of the composite chip arrangement area 191 according to the wiring pattern. In this way, when the first via, the second via, and the third via are arranged in this order toward the inside of the composite chip placement region 191, the via located on the outside is first placed in the composite chip placement region 191. It may be configured to provide a wiring pattern so as to avoid it. As a result, the wiring space in the composite chip arrangement area 191 can be effectively utilized.

Further, in the above-mentioned example, the relationship between the first via, the second via, and the third via is shown by taking a specific via as an example, but the same configuration can be applied to other vias shown in the figure. desirable. As described above, by making the same configuration at a plurality of locations, it is possible to effectively utilize the wiring space in the composite chip arrangement area 191 as compared with the implementation at a single location. Further, the above-mentioned example shows that the wiring layer is different from the first wiring layer La1 in the composite chip arrangement area 191. However, the present invention is not limited to this, and the wiring layer 1 is configured to be used. You may. However, since a plurality of terminals of the composite chip 104 are arranged in the first wiring layer La1, it is assumed that there is relatively little margin in the wiring space. Therefore, the wiring layer different from that of the first wiring layer La1 is used. Is desirable.

Further, in the example of FIG. 34, like the terminals of the composite chip 104 linearly arranged in the Y-axis direction from HAD1 to HAD0, the drawing directions of the wiring patterns drawn from the respective terminals are different (eg, HAD1 and HAD0 are different). The vias connected to each terminal are arranged linearly in the Y-axis direction in the −XY direction, HAD8, HAD3, HAD15, HAD20 in the + XY direction, and HAD11 in the −X + Y direction). In this way, the terminals of the composite chip 104 linearly arranged in the Y-axis direction (and / or the X-axis direction) and the vias connected by the wiring patterns are linearly aligned in the Y-axis direction (and / or the X-axis direction). It is not necessary to arrange them so that they are arranged in a line, and the terminals of the composite chip 104 that are not related to each other linearly arranged in the Y-axis direction (and / or the X-axis direction) and the vias connected by the wiring pattern are connected in the Y-axis direction. It may be arranged so as to be aligned linearly (and / or in the X-axis direction). Even with this configuration, as a result, the terminal arrangement and via arrangement of the composite chip 104 can be arranged so as to be linearly arranged in the Y-axis direction (and / or the X-axis direction). It is possible to achieve the same effect as.

In the example of FIG. 34, wiring patterns are drawn out in substantially the same direction from a plurality of terminals (eg, HDT6, HDT10, HDT15, HAD24) of the composite chip 104 arranged in a straight line in the Y-axis direction, and the composite chip arrangement is performed respectively. Vias (eg, v17 to v14) are arranged so as to be linearly arranged in the Y-axis direction in the region 191. Then, as shown in FIG. 40, the wiring pattern is led from the first wiring layer La1 to the fourth wiring layer La4 via these vias, and the wiring pattern is drawn out from the fourth wiring layer La4. In this way, the terminals of the composite chip 104 having the common conduction destination from the via (here, the fourth wiring layer La4) may be configured to draw out the wiring pattern from each terminal in the same direction. Similarly, the vias connected to each terminal may be arranged so as to be linearly arranged in the Y-axis direction within the composite chip arrangement region 191. Further, in this case, as shown in FIG. 34, the address output terminal for outputting the address information and the data input / output terminal for inputting / outputting the data information may be configured as described above, or the address. The above-mentioned configuration may be made only with the address output terminal for outputting information or only the data input / output terminal for inputting / outputting data information. With such a configuration, it becomes easy to confirm the arrangement of each terminal, the arrangement of vias, and the wiring pattern serving as a connection path. Further, not only the terminals of the composite chip 104 having the common conduction destination from the via (here, the fourth wiring layer La4) but also the connection connected from the via to the connection destination (example: control ROM 105) through the wiring pattern. The terminals of the composite chip 104 having the same type may be configured as described above. In addition, the wiring route from the via to the connection destination (eg, control ROM 105) through the wiring pattern (which wiring layer passes through, what wiring pattern is used for wiring, etc.) is almost common. The terminals of the composite chip 104 may have the above-mentioned configuration. With such a configuration, it becomes easy to confirm the arrangement of each terminal, the arrangement of vias, and the wiring pattern serving as a connection path.

In the above description, "the arrangement of vias v60 to v85 and v87 to v107 (specific interlayer conduction portion) in the control ROM arrangement area 192 is approximated to the arrangement of the corresponding terminals on the control ROM 105 side (specific second terminal). The word "approximate" is used, such as "is.", But this "approximate" may be one in which the arrangements of all the terminals and vias in the connection relationship match, or it is in the connection relationship. The arrangement may be the same for some terminals and vias. Further, when there are a plurality of connectors having a connection relationship (eg, a control ROM terminal and a connector terminal for a predetermined via), the arrangement of one or both terminals may be the same. Further, when there are a plurality of connection destinations, there is no problem if they are the same electronic component, but if they are different electronic components, there is a high possibility that the arrangement of both terminals is different. In that case, it is practically impossible to have a via array that exactly matches the array of both terminals. Therefore, in order to match the arrangement of both terminals as much as possible, the arrangement may be partially common. For example, an array of a part of the terminals of the first connection destination (an array of a part of the terminals of the control ROM 105) and an array of a part of the terminals of the second connection destination (an array of a part of the terminals of the connector), respectively. There may be a via array corresponding to a part of the array of, or an array of a part of the terminals of the first connection destination (an array of a part of the terminals of the control ROM), but the terminal of the second connection destination. It corresponds to the first via array that does not correspond to a part of the array of (the array of some of the terminals of the connector) and the array of some of the terminals of the first connection destination (the array of some of the terminals of the control ROM) However, it may be configured to include a second via array corresponding to a partial arrangement of terminals of the second connection destination (arrangement of a part of the terminals of the connector). Then, it is assumed that such an arrangement of vias is also in the above-mentioned "approximate" relationship.

Regarding the assembly of boards, "assembly" may mean that one control board is completed by combining a plurality of boards, or a state in which a harness is inserted into a connector for one board to make it conductive. It may also be connected to another board via a harness. Further, the present invention is not limited to a plurality of substrates or a single substrate, and various electronic components necessary for operation may be attached to the substrate.

The contents of the above embodiments can be combined in any way, and by combining them, the wiring efficiency can be improved more effectively, and the board configuration can be made resistant to noise and fraudulent activities.

In addition, all the terminal arrangements, wiring patterns, installation positions of electronic components, etc. shown in the figure were constructed by seeking the optimum solution, and as a result of combining all the configurations shown in the figure, more suitable wiring efficiency was obtained. It is possible to reduce the size of the substrate and reduce noise.

Further, the present invention can be similarly implemented in various ball game machines such as arrange ball machines and sparrow ball game machines, as well as in game machines other than ball game machines such as slot machines.

63 First special symbol display means (design display means)
64 Second special symbol display means (design display means)
98 LCD control board (display control means)
X1 to X4, Y1 to Y4 Hold notification image

Claims (2)

A symbol display means capable of variablely displaying a symbol based on random number information acquired when the symbol start condition is satisfied, and a symbol display means.
A hold storage means for holding and storing the random number information up to a predetermined upper limit number until the random number information is subjected to a symbol change by the symbol display means, and a hold storage means.
A profit state generating means that generates a profit state when the stop symbol after the change of the symbol display means becomes a specific mode, and a profit state generating means.
It is equipped with a display control means that controls the display of the liquid crystal display means.
In a gaming machine capable of displaying a number of hold notification images corresponding to the number of random number information stored in the hold storage means on the liquid crystal display means.
The display control means outputs the odd-numbered image data corresponding to the odd-numbered pixels and the even-numbered image data corresponding to the even-numbered pixels adjacent to the odd-numbered pixels to the liquid crystal display means via different wiring paths. Configure and
By executing a dynamic display with a change in the vertical direction on the hold notification image, even if either the odd number image data or the even image data is missing, the hold notification image is dynamically displayed. A gaming machine characterized in that the display is configured to be easy to identify. The gaming machine according to claim 1, wherein when the hold notification image is shifted in the horizontal direction, a dynamic display accompanied by a movement in the vertical direction is executed.

Images