JP7123996B2 - game machine - Google Patents

Description

The present invention relates to gaming machines such as pachinko machines and slot machines.

In a game machine such as a pachinko machine, various control means such as effect control means, payout control means, launch control means, and main control means for performing integrated control thereof are mounted in a form distributed over a plurality of substrates. Each control board is equipped with electronic parts such as a composite chip (LSI) with a built-in CPU circuit, various ICs, ROMs, capacitors, resistors, connectors, etc., and wiring patterns for connecting these electronic parts are For example, it is formed across a plurality of wiring layers (Patent Document 1).

JP 2019-187989 A

Recent game machines are equipped with a large number of various effects means such as movable bodies and image display means, and since these tend to be large, it is necessary to efficiently arrange a large number of parts in a limited space. Various boards arranged on the rear side of the main body of the game machine are no exception, and it is required to efficiently arrange complicated wiring patterns in order to minimize the size of the boards.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a gaming machine capable of arranging wiring patterns on a substrate more efficiently.

The present invention comprises a substrate having a plurality of wiring layers and an interlayer conductive portion in the plate thickness direction for connecting the plurality of wiring layers to each other, a chip having a built-in CPU circuit on the substrate, and the chip. and a predetermined electronic component different from the chip and the ROM , wherein the chip is arranged in a first wiring layer of the plurality of wiring layers. and a second placement area where the ROM is placed, the chip has a plurality of first terminals capable of outputting and/or inputting predetermined information, and the ROM inputs and/or outputs the predetermined information. the predetermined electronic component includes a plurality of third terminals capable of inputting and/or outputting predetermined information; and the arrangement of the plurality of first terminals is such that the plurality of second terminals and the arrangement of the plurality of third terminals, respectively, and among the interlayer conduction portions, the plurality of predetermined interlayer conduction portions arranged in the second arrangement region and the plurality of first terminals a group of first wiring paths connecting the plurality of predetermined interlayer conduction portions and the plurality of second terminals respectively; a group of wiring paths connecting the plurality of predetermined interlayer conduction portions and the plurality of second terminals; and a third wiring path group connecting each of the plurality of predetermined interlayer conductive portions, the arrangement of the plurality of predetermined interlayer conductive portions being approximated to the array of the plurality of third terminals , and the second wiring path group connecting the plurality of predetermined interlayers to each other. The array corresponding to the conducting portion is converted into the array corresponding to the second terminal in the second arrangement area and connected to the second terminal .

According to the present invention, wiring patterns on a substrate can be arranged more efficiently.

1 is an overall front view of a pachinko machine according to an embodiment of the present invention; FIG. It is an exploded perspective view of the pachinko machine. It is an exploded perspective view of the glass door of the pachinko machine. FIG. 2 is a plan view of a main portion showing operation effect means, a cross operation button, a volume adjustment button, a light amount adjustment button, etc. of the same pachinko machine; It is a front view of the game board of the pachinko machine. It is a front view of the game information display means of the pachinko machine. It is a rear view of the pachinko machine. It is an exploded perspective view of the performance board case and the performance control unit of the pachinko machine. It is a plan cross-sectional view of the performance board case and the performance control unit of the same pachinko machine. It is a block diagram showing the overall circuit configuration of the pachinko machine. FIG. 2 is a circuit block diagram illustrating a composite chip mounted on a liquid crystal control board of the same pachinko machine, including related circuit elements. It is a diagram showing a wiring pattern of a first wiring layer in the liquid crystal control board of the same pachinko machine. It is a figure which shows the wiring pattern of the 2nd wiring layer in the liquid crystal control board of the same pachinko machine. It is a figure which shows the wiring pattern of the 3rd wiring layer in the liquid crystal control board of the same pachinko machine. It is a figure which shows the wiring pattern of the 4th wiring layer in the liquid crystal control board of the same pachinko machine. It is a figure which shows the wiring pattern of the 5th wiring layer in the liquid crystal control board of the same pachinko machine. It is a figure which shows the wiring pattern of the 6th wiring layer in the liquid crystal control board of the same pachinko machine. It is a figure which shows the terminal information of the composite chip arrange|positioned at the liquid crystal control board of the same pachinko machine. It is a figure which shows the terminal information of control ROM arrange|positioned at the liquid crystal control board of the same pachinko machine. FIG. 3 is a diagram showing only wiring paths P1 to P47 extracted from the first wiring layer of the liquid crystal control board of the same pachinko machine. FIG. 3 is a diagram of only wiring paths P1 to P47 extracted from the second wiring layer of the liquid crystal control board of the same pachinko machine. FIG. 4 is a diagram of only wiring paths P1 to P47 extracted from a third wiring layer in the liquid crystal control board of the same pachinko machine; FIG. 4 is a diagram of only wiring paths P1 to P47 extracted from a fourth wiring layer in the liquid crystal control board of the same pachinko machine; FIG. 10 is a diagram of only wiring paths P1 to P47 extracted from the fifth wiring layer of the liquid crystal control board of the same pachinko machine; FIG. 10 is a diagram showing only wiring paths P1 to P47 extracted from a sixth wiring layer in the liquid crystal control board of the same pachinko machine; 21 is an enlarged view of a region E1a in FIG. 20; FIG. 21 is an enlarged view of a region E1b in FIG. 20; FIG. 23 is an enlarged view of a region E3a in FIG. 22; FIG. 23 is an enlarged view of a region E3b in FIG. 22; FIG. 23 is an enlarged view of a region E3c in FIG. 22; FIG. 24 is an enlarged view of a region E4 in FIG. 23; FIG. 26 is an enlarged view of a region E6a in FIG. 25; FIG. 26 is an enlarged view of a region E6b in FIG. 25; FIG. FIG. 26 is an enlarged view of a region E6c in FIG. 25; FIG. 2 is a diagram schematically showing wiring paths of wiring paths P1 to P8 on the liquid crystal control board of the pachinko machine according to one embodiment of the present invention; FIG. 4 is a diagram schematically showing wiring paths of wiring paths P9 to P17 on a liquid crystal control board of the same pachinko machine; FIG. 4 is a diagram schematically showing wiring paths of wiring paths P18 to P26 on a liquid crystal control board of the pachinko machine; FIG. 4 is a diagram schematically showing wiring paths of wiring paths P27 to P34 on a liquid crystal control board of the pachinko machine; FIG. 4 is a diagram schematically showing wiring paths of wiring paths P35 to P42 on a liquid crystal control board of the same pachinko machine; FIG. 4 is a diagram schematically showing wiring paths of wiring paths P43 to P47 on a liquid crystal control board of the pachinko machine; It is a circuit diagram of a decoding circuit in the liquid crystal control board of the pachinko machine. It is a circuit diagram of a reset circuit in the liquid crystal control board of the pachinko machine. It is a figure which shows the silk-print pattern of the 1st wiring layer side in the liquid crystal control board of the same pachinko machine.

Embodiments of the invention will be described in detail below with reference to the drawings. 1 to 43 illustrate an embodiment in which the present invention is applied to a pachinko machine. 1 and 2, a gaming machine body 1 includes an outer frame 2 and a front frame 3 arranged in front of the outer frame 2. As shown in FIG. The front frame 3 is pivotally attached to the outer frame 2 so as to be openable and detachable via a vertical first hinge 4 arranged at one end in the left-right direction, for example, the left end. The outer frame 2 can be locked in the closed state by a locking means 5 provided on the opposite side, for example, the right end side.

The front frame 3 includes an inner frame 6 and a front door 7 arranged on the front side of the inner frame 6. - 特許庁The front door 7 is pivotally attached to the inner frame 6 via a vertical second hinge 8 disposed at one end in the left-right direction, for example, at the left end so as to be openable and detachable. can be locked in the closed state.

As shown in FIG. 2, the outer frame 2 is formed in a rectangular shape by a pair of left and right vertical frame members 2a and 2b and a pair of upper and lower horizontal frame members 2c and 2d. A front cover member 9 made of, for example, synthetic resin is attached to the front lower portion of the outer frame 2 so as to connect the front lower portions of the left and right vertical frame members 2a and 2b along the front edge of the lower horizontal frame member 2d. there is The front cover member 9 protrudes forward from the left and right vertical frame members 2a and 2b, and the inner frame 6 is arranged on the upper side thereof. In the outer frame 2, an outer frame upper hinge metal fitting 11 constituting the first hinge 4 is disposed, for example, at the upper left portion, and an outer frame lower hinge metal fitting 12 is disposed above the front cover member 9 at the lower left portion.

The inner frame 6 is made of synthetic resin, and has a rectangular frame portion 13 that can substantially contact the front edge side of the outer frame 2 on the upper side of the front cover member 9, and a game board provided on the upper side inside the frame portion 13. A mounting portion 14 and a lower mounting portion 15 provided on the lower side in the frame portion 13 are integrally provided, for example. A game board 16 is detachably attached to the game board mounting portion 14, for example, from the front side. In the inner frame 6, a main body frame upper hinge metal fitting 19 constituting the first hinge 4 and a main body frame upper hinge metal fitting 20 constituting the second hinge 8 are arranged, for example, at the upper left portion of the first and second hinges 4, 8. Main body frame lower hinge metal fittings 21 are arranged, for example, in the lower left part.

The front door 7 has a resin door base 22 formed in a rectangular shape corresponding to the front side of the inner frame 6 . The door base 22 is formed with window holes 24a of a glass window 24 corresponding to the front side of the game area 23 formed on the game board 16. For example, a plurality of windows (four here) are formed around the window holes 24a. Various production means such as an upper speaker 25, a first frame movable body 26, a second frame movable body 27, and an air blowing means 28 are arranged.

On the upper front side of the door base 22, a side unit 30 is attached to at least a portion of the outer circumference of the window hole 24a, for example, an inverted L-shaped portion corresponding to the upper side and the right side of the window hole 24a. An upper decorative cover 31 is attached to a portion, for example, the left side of the window hole 24a. Inside the side unit 30 and inside the upper decorative cover 31, a large number of LEDs are arranged, which constitute electric decorations for presentation. As shown in FIGS. 2 and 3, the side unit 30 operates a fixing screw 30a, a fixing lever 30b, etc. on the back side of the front frame 3 without using a special tool while the front frame 3 is open. By doing so, it can be easily attached and detached. Normally, the front frame 3 is commonly used for a plurality of models, and by mounting a different game board 16 for each model on the front frame 3, the playability and design unique to the model are realized. In the machine, a part of the front side of the front frame 3 is made into a side unit 30 which is more easily detachable than other parts, and the side unit 30 has a design with a sense of unity with the game board 16 and a unique function. By doing so, it is possible to increase the degree of freedom in design and function for each model while standardizing most of the front frame 3 .

The side unit 30 of the present embodiment is mounted with a first frame movable body 26, a second frame movable body 27, an air blowing means 28, and the like, in addition to the illumination LED. The first frame movable body 26 can be slid substantially in the front-rear direction by being driven by drive means (not shown). The second frame movable body 27 can be slid substantially in the front-rear direction by being driven by drive means (not shown), and can be pushed by the player. The air blowing means 28 can blow air toward the player's hands at the timing when the player operates the frame second movable body 27, for example.

On the front side of the lower portion of the door base 22, an upper tray 33 for storing game balls put out from the putting out means 32 arranged on the rear side of the inner frame 6 and supplying them to the shooting means 17, and the upper tray 33 is full. A lower tray 34 for storing surplus balls, etc., and a firing handle 35 operated to operate the firing means 17 are arranged, and a lower decorative cover 36 that substantially covers the upper tray 33, the lower tray 34, etc. from the front side is attached. It is The lower decorative cover 36 is formed, for example, in a forward-facing bulging shape, and various operation means such as an operation presentation means 37, a cross operation button 38, a volume adjustment button 39, and a light amount adjustment button 40 are provided on the upper side thereof, for example. (Fig. 4).

The operation effect means 37 is used for advance notice effect during pattern variation and other effects, and includes a vertically moving effect button 41 that can be operated by the player to press, and a third frame arranged inside the effect button 41. A movable body 42 and the like are provided. The third frame movable body 42 is composed of, for example, a substantially spherical rotating body rotatable about a horizontal axis, and is rotatable in both forward and reverse directions by a rotation drive motor 43 .

As shown in FIG. 4, the cross-shaped operation button 38 has four operation buttons 38a to 38d for up, down, left, and right. used. The volume adjustment button 39 is used by the player to adjust the volume, and as shown in FIG. and a minus button 39b to be operated. The light amount adjustment button 40 is used by the player to adjust the light amount, and as shown in FIG. and a minus button 40b to be operated. In this embodiment, the volume adjustment button 39 dedicated to volume adjustment and the light amount adjustment button 40 dedicated to light amount adjustment are provided. It may also be used for adjustment.

On the back side of the door base 22, as shown in FIG. 2, a glass unit 50 is detachably attached to substantially block the window hole 24a from the rear side, and the edges of the first and second hinges 4, 8 are provided with the glass unit 50. A vertical hinge end side reinforcing sheet metal 51a arranged along, a vertical opening/closing end side reinforcing sheet metal 51b arranged along the edge of the opening/closing end side, and left and right sides arranged under the window hole 24a. The direction lower reinforcing sheet metal 51c is detachably fixed by screws or the like. Further, on the door base 22, a glass door upper hinge metal fitting 52a and a glass door lower hinge metal fitting 52b constituting the second hinge 8 are disposed, for example, at the upper left portion and the lower left portion, respectively.

Further, for example, a ball feeding unit 53a, a lower tray guide unit 53b, and the like are mounted on the back side of the lower reinforcing sheet metal 51c. The ball feeding unit 53a is for supplying game balls in the upper tray 33 to the shooting means 17, and is arranged in front of the shooting means 17 arranged on the inner frame 6 side. By activating the ball feed solenoid 53c in synchronization with the shooting operation, the game balls in the upper tray 33 are supplied one by one onto the shooting rail 17a of the shooting means 17. As shown in FIG.

The shooting means 17 includes a shooting rail 17a which is arranged in an upward leftward sloping shape when viewed from the front, and a shooting ball stopper 17b which supports the game ball supplied onto the shooting rail 17a by the ball feeding unit 53a at a shooting standby position. , a striking hammer 17c arranged corresponding to a shooting standby position on the shooting rail 17a and capable of swinging around a drive shaft in the front-rear direction; When the shooting handle 35 is rotated, the shooting drive means 17d continuously drives the hammer 17c in the striking direction (clockwise) with a shooting intensity corresponding to the amount of operation.

The lower tray guide unit 53b guides surplus balls when the upper tray 33 is full and foul balls that have returned without reaching the game area 23 despite being shot by the shooting means 17 to the lower tray 34. For example, it is arranged adjacent to the ball feeding unit 53a on the side of the first and second hinges 4 and 8 thereof.

As shown in FIG. 5, the game board 16 has a base plate 55 made of plywood, polycarbonate, or the like. In addition to unit parts such as a central display frame unit 57, a starting winning unit 58, and a normal winning unit 59, a large number of game nails (not shown) are arranged in the game area 23 inside the guide rails 56. , and a game information display means 60 is arranged outside the game area 23, for example, on the lower side. Of course, the game information display means 60 may be arranged within the game area 23 .

As shown in FIG. 6, the game information display means 60 is provided with four LED groups composed of, for example, eight LEDs 70. A total of 32 LEDs 70 are normal symbol display means 61 and normal reserved number display means. 62, 1st special symbol display means 63, 2nd special symbol display means 64, 1st special reserved number display means 65, 2nd special reserved number display means 66, fluctuation shortening notification means 67, right hitting notification means 68 and number of rounds A predetermined number of them are assigned to the notification means 69 . That is, the eight LEDs 70 belonging to the first and second LED groups 60a and 60b constitute the first and second special symbol display means 63 and 64, respectively, and the eight LEDs 70 belonging to the third LED group 60c are two. Eight LEDs 70 belonging to the fourth LED group 60 d constitute the first special reserved number display means 65, the second special reserved number display means 66, the normal reserved number display means 62, and the fluctuation reduction notification means 67, respectively. , two of them constitute normal symbol display means 61, the other two constitute right-handed informing means 68, and the remaining four constitute round number informing means 69, respectively.

On the plurality of unit parts 57 to 59 of the game board 16, normal symbol starting means 71, first special symbol starting means 72, second special symbol starting means 73, big winning means 74, a plurality of normal winning means 75, etc. is provided. In addition to the liquid crystal display unit (image display means) 76, movable bodies such as a first board movable body 77, a second movable board 78, and a third movable board 79 are arranged on the rear side of the base plate 55. there is

The central display frame unit 57 constitutes a display frame for the liquid crystal display unit 76 and the movable bodies 77 to 79, and has an opening window 80 corresponding to the liquid crystal display unit 76 on the rear side formed substantially in the center. It is detachably attached from the front side to an attachment hole (not shown) formed in the front-rear direction penetrating portion 55 . As shown in FIG. 5, the central display frame unit 57 includes a front mounting plate 81 arranged outside the mounting hole along the front surface of the base plate 55 and through which game balls can pass, and a liquid crystal display unit 76. A decorative frame 82 arranged in a substantially gate shape in front view extending from both left and right sides to the upper side on the front side of the , and protruding forward on the inner peripheral side of the front mounting plate 81, and arranged between the left and right lower ends of the decorative frame 82 and a stage 83 to be performed. The game balls fired by the shooting means 17 and entering the upper part of the game area 23 are distributed to the left and right at the top of the decoration frame 82, and are distributed to the left flow path 84a on the left side of the central display frame unit 57 and the right flow path 84b on the right side. or flow down.

The central display frame unit 57 is provided with a warp entrance 85 through which game balls can flow in at least one of the left flow path 84a and the right flow path 84b, for example, the left flow path 84a. A game ball that flows into the warp entrance 85 while flowing down the left flow path 84a rolls freely in the left-right direction on the stage 83, and then moves to a central drop portion 86 provided corresponding to the center in the left-right direction of the game area 23. and the other portion to the front.

Both the first board movable body 77 and the third board movable body 79 are arranged in a horizontally long shape on the front side of the liquid crystal display unit 76, and both left and right sides thereof are supported outside the opening window 80 so as to be vertically movable. They can be moved up and down individually by an up-and-down driving means (not shown). The second board movable body 78 is a three-dimensional object formed in a predetermined shape such as a character, is arranged in front of the first board movable body 77, and is vertically movable integrally with the first board movable body 77. At the same time, it can be rotated about the center axis in the front-rear direction with respect to the first movable board 77 by being driven by a rotation drive means (not shown).

As shown in FIG. 5, the starting prize winning unit 58 is arranged below the central display frame unit 57 along the guide rail 56 and is detachably attached to the base plate 55 from the front side. As shown in FIG. 5, the normal winning unit 59 is arranged below the central display frame unit 57 and to the left of the starting winning unit 58 along the guide rail 56, and is detachably attached to the base plate 55 from the front side. ing.

The normal symbol starting means 71 is for starting variable display of normal symbols by the normal symbol display means 61, and is composed of a passage gate or the like through which a game ball can pass, and is a game ball detection switch for detecting passage of a game ball. (illustration omitted). As shown in FIG. 5, the normal symbol starting means 71 is provided, for example, on the front side of the front attachment plate 81 on the right side of the central display frame unit 57, so that game balls flowing down the right flow path 84b can pass through. ing.

The normal symbol display means 61 is for variably displaying normal symbols, and as shown in FIG. Based on the detection of the game ball by the 71, after the two LEDs 70 constituting the normal pattern emit light in the light emission pattern during normal fluctuation, the normal random number information acquired when the game ball is detected by the normal symbol starting means 71 If the included hit determination random value matches a predetermined hit determination value, the variation is stopped in a win mode, and in other cases, in a losing mode. In addition, the two LEDs 70 constituting the normal pattern can display one or more winning modes and one or more losing modes depending on the combination of their light emission modes (for example, lighting / extinguishing), and during normal fluctuation The light emission pattern is such that, for example, a plurality of specific types (here, two types) of light emission modes are switched every predetermined time (for example, 128 ms).

In addition, when the normal symbol starting means 71 detects the game ball during the normal holding period including during the symbol fluctuation of the normal symbol display means 61 and during the normal profit state, the normal random number information acquired thereby is predetermined. The set upper limit reserved number, for example, 4, is reserved and stored, and each time the normal reserved period ends, one is consumed and the normal pattern is varied. The stored number of normal random number information (normal reserved number) is notified to the player by the normal reserved number display means 62 or the like. The normal reserved number display means 62 is composed of a predetermined number (here, two) of LEDs 70 in the game information display means 60 as shown in FIG. By combining flashing/lighting out, it is possible to display 5 types of normal pending numbers from 0 to 4.

The first special symbol starting means 72 is for starting the symbol variation by the first special symbol display means 63, and is composed of a non-opening/closing type winning means having no opening/closing means, and detects a winning game ball. A detection switch (not shown) is provided. This first special symbol starting means 72 is provided in, for example, the starting winning unit 58 as shown in FIG. Since there is a winning route via the stage 83 from the warp entrance 85 on the side of the flow path 84a, the game ball flowing down the left flow path 84a has a higher probability than the game ball flowing down the right flow path 84b. It is possible to win a prize at In addition, when the game ball wins the first special symbol starting means 72, a predetermined number of game balls per one win are paid out as prize balls.

The second special symbol starting means 73 is for starting the symbol variation by the second special symbol display means 64, and by operating the opening/closing part 88, the game ball can A game ball detection switch (not shown) that detects a game ball that has won a prize, and an opening/closing drive means such as an electromagnetic solenoid that opens/closes the opening/closing portion 88. When the normal profit state occurs due to the winning mode of the stopped symbol after the change of the normal symbol display means 61, the opening/closing part 88 changes from the closed state to the open state for a predetermined time. there is

This second special symbol starting means 73 is arranged on the front mounting plate 81 in the right part of the central display frame unit 57 and downstream of the normal symbol starting means 71 as shown in FIG. A game ball flowing down 84b can win a prize. The opening/closing part 88 can swing about, for example, a rotation axis in the left-right direction provided on the lower side. In the state, the front side of the front mounting plate 81 is tilted downward backward, and the game ball is made to win backward. When game balls win in the second special symbol starting means 73, a predetermined number of game balls are paid out as prize balls per one win.

As shown in FIG. 6, the first special symbol display means 63 is composed of a predetermined number (eight in this case) of LEDs 70 in the game information display means 60, and the first special symbol starting means 72 detects a game ball. On the condition that, after the eight LEDs 70 constituting the first special symbol emit light in the light emission pattern during special fluctuation, the first special random number information acquired when the game ball is detected by the first special symbol starting means 72 is included in the When the received big hit judgment random value coincides with a predetermined big hit judgment value, the variation is stopped in the first big win mode, and in the other cases, the fluctuation is stopped in the first losing mode. When the stop symbol after the variation of the first special symbol display means 63 becomes the first jackpot mode, the first special profit state occurs.

As shown in FIG. 6, the second special symbol display means 64 is composed of a predetermined number (eight in this case) of LEDs 70 in the game information display means 60, and the second special symbol starting means 73 detects a game ball. On the condition that, after those eight LEDs 70 constituting the second special symbol emit light in the light emission pattern during special fluctuation, the second special random number information acquired when the game ball is detected by the second special symbol starting means 73 is included in the When the received big hit judgment random value coincides with a predetermined big hit judgment value, the variation is stopped in the second big win mode, and in the other cases, the variation is stopped in the second losing mode. When the stop symbol after the variation of the second special symbol display means 64 becomes the second jackpot mode, the second special profit state occurs.

The first and second special symbol display means 63 and 64 are provided with one or a plurality of first and second jackpot modes and one or a plurality of first, The second deviation mode can be displayed, and the special fluctuating light emission pattern switches between a plurality of specific types (here, two types) of light emission modes at predetermined time intervals (for example, 128 ms).

Also, the first and second special symbols are started during the special holding period including during the symbol variation of the first special symbol display means 63, during the symbol variation of the second special symbol display means 64, and during the first and second special profit states. When the means 72 and 73 detect game balls, the first and second special random number information obtained thereby are retained and stored up to a predetermined upper limit retained number, for example, four each. Then, when the reserved memory on the side of the second special pattern is 1 or more at the time when the special reserved period ends, one reserved memory of the second special pattern is digested to change the second special pattern, and the first special pattern is changed. When only the reserved memory on the side of the special design is 1 or more, one reserved memory of the first special design is digested to change the first special design. As described above, in this embodiment, both the first special symbol and the second special symbol are not fluctuating, and when both the first special symbol side and the second special symbol side have reserved memory, is to preferentially change the second special symbol.

The stored numbers of the first and second special random number information (first and second special reserved numbers) are notified to the player by the first and second special reserved number display means 65 and 66, the liquid crystal display unit 76 and the like. be. Here, the first and second special reserved number display means 65 and 66 are composed of a predetermined number (here, two each) of LEDs 70 in the game information display means 60 as shown in FIG. For example, it is possible to display 5 kinds of first and second special holding numbers of 0 to 4 by combining lighting/blinking/lighting out.

The big winning means 74 is an opening/closing type winning means having an opening/closing plate 89 capable of switching between an open state in which game balls can win and a closed state in which game balls cannot win. provided with a game ball detection switch (not shown) for detecting a winning game ball, and an opening and closing driving means such as an electromagnetic solenoid for opening and closing the opening and closing plate 89, and the downstream side of the second special symbol starting means 73 And by being arranged on the upstream side of the first special symbol starting means 72, the game ball flowing down the right flowing path 84b can win with a higher probability than the game ball flowing down the left flowing path 84a. It has become. This big winning means 74 is the first special symbol that occurs when the first and second special symbols of the first and second special symbol display means 63 and 64 stop in the first and second big winning modes (specific modes) after the variation. , in the second special profit state, the opening/closing plate 89 is opened forward according to one or more kinds of opening patterns, and the game balls falling thereon are allowed to enter inside. When a game ball wins the big winning means 74, a predetermined number of game balls are paid out as prize balls per winning.

In parallel with the variable display of the first and second special symbols by the first and second special symbol display means 63 and 64, the liquid crystal display unit 76 can variably display the effect symbol 90. 2 It is possible to display various images such as the first and second reserved images X1 to X4 and Y1 to Y4 indicating the special reserved number, and the suspended image Z during fluctuation.

Here, the production pattern 90 has a plurality of pattern rows (here, three in the left-right direction) composed of a plurality of patterns such as number patterns. 2, the pattern body 90a composed of numbers such as 1 to 8, etc., and a decoration part 90b such as characters attached to the pattern body 90a are combined. It is possible to arbitrarily change the display mode of the effect pattern 90, such as enlargement or reduction, change of the display position, deletion of the decorative portion 90b, and the like.

The production pattern 90, for example, starts to fluctuate by vertical scrolling or the like for each pattern row according to a predetermined fluctuation pattern approximately at the same time as the first and second special patterns start to fluctuate, and a stop pattern on a predetermined effective line is in a predetermined mode. For example, the first and second special symbols are stopped at the same time as the final stop. In the production pattern 90, for example, when all the stop patterns on the effective line are the same, it is a big hit production mode, and when it is not, it is a dissimilar production mode. In this case, the performance pattern 90 becomes a big win performance mode, and when the first and second special symbols become the first and second loss modes, the performance pattern 90 becomes a loss performance mode.

In addition, regarding the first and second reserved images X1 to X4, Y1 to Y4, and the suspended image Z during fluctuation, the first and second special symbol starting means 72 and 73 detect the game ball. 2. When the number of special reserved images increases, the first and second reserved images X1-, Y1- are additionally displayed on the liquid crystal display unit 76, and the first and second special symbol display means 63, 64 are displayed. When the first and second special reserved numbers decrease based on the start of the new fluctuation of the first and second special symbols, for example, the suspended image Z during fluctuation is erased, and the first and second reserved images X1 to , Y1~ toward the front side of the queue (for example, the right side of the screen) by one piece at a time, and move the first and second pending images X1 and Y1 pushed out to, for example, a predetermined position to create a new change. The image Z is changed to the middle reserved image Z.

On the back side of the game board 16, as shown in FIG. 7, a back case 91 for supporting the liquid crystal display unit 76 on the back side of the game board 16 is attached. A main board case 94 housing a main control board 93 constituting a part 92, a production interface board 96 constituting a production control part 95, a liquid crystal interface board 97, a liquid crystal control board 98 and a ROM board 99 are stored in a production board case. 100 and the like are detachably attached.

Here, details of how the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98 and the ROM board 99 are stored in the effect board case 100 will be described with reference to FIGS.

The effect interface board 96 and the liquid crystal interface board 97 are arranged so that their respective surfaces 96a and 97a face the rear side and are adjacent to each other in the left and right directions. The effect interface board 96 and the liquid crystal interface board 97 are arranged along the edge of the effect interface board 96 on the side of the liquid crystal interface board 97. The effect IF first and second connectors CN11 and CN12 The first and second liquid crystal IF connectors CN21 and CN22 arranged along the edge on the effect interface board 96 side are directly connected in the horizontal direction to be integrated with each other. Various electronic components are arranged on both front and back sides of the effect interface board 96. Various ICs such as the audio processor 101 and the digital amplifier 102, various connectors such as the liquid crystal IF first to third connectors CN21 to CN23, The audio ROM 103 and the like are arranged on the surface 96a side. Various electronic components are arranged on both front and back surfaces of the liquid crystal interface board 97, but various connectors such as the liquid crystal IF first to third connectors CN21 to CN23 are arranged on the surface 97a side.

The liquid crystal control board 98 is arranged behind the effect interface board 96 and the liquid crystal interface board 97 so that the front surface 98a faces rearward and the back surface 98b faces the surfaces 96a and 97a of the effect interface board 96 and the liquid crystal interface board 97. are placed. The liquid crystal control board 98 connects the liquid crystal control first connector CN31 provided on the back surface 98b side to the effect IF third connector CN13 on the effect interface board 96 side, and the liquid crystal control second connector CN32 also provided on the back surface 98b side. are directly connected to the third liquid crystal IF connector CN23 on the side of the liquid crystal interface board 97, the effect interface board 96 and the liquid crystal interface board 97 are integrated. Various electronic components are arranged on both front and back sides of the liquid crystal control board 98. The composite chip 104, the control ROM 105, the DRAM 106, the liquid crystal control third connector CN33, etc. are arranged on the front surface 98a side, and the rear surface 98b side. , liquid crystal control first and second connectors CN31, CN32, etc. are arranged.

The ROM board 99 is arranged adjacent to the liquid crystal control board 98 so that the front surface 99a faces backward and the rear surface 99b faces the display interface board 96 and the liquid crystal interface board 97, for example, the front surface 97a of the liquid crystal interface board 97. placed below it. The ROM board 99 directly connects the ROM first connector CN41 arranged at the upper edge on the surface 99a side to the liquid crystal control third connector CN33 arranged at the lower edge of the liquid crystal control board 98. It is integrated with the liquid crystal control board 98 . Various electronic components are arranged on both the front and back surfaces of the ROM board 99, but the CGROM 107, ROM first connector CN41, etc. are arranged on the surface 99a side.

As described above, the substrates 96 to 99 are connected to each other by directly connecting the connectors to each other. are opposed to each other with a predetermined gap therebetween and are connected and integrated. Therefore, when the substrates 96 to 99 are connected to each other, the rear surface 98b side of the liquid crystal control substrate 98 is hidden by the effect interface substrate 96 and the liquid crystal interface substrate 97 and cannot be viewed.

The effect board case 100 is made of a transparent synthetic resin, and is formed in a substantially box shape with a base body 111 covering the back sides of the boards 96-99 and a cover body 112 covering the front sides of the boards 96-99. When the boards 96 to 99 are stored in the presentation board case 100, the liquid crystal control board 98 and the ROM board 99 are first connected to each other by direct connectors, and then screwed to a predetermined position inside the cover body 112. fixed. At this time, the surfaces 98a and 99a of the liquid crystal control board 98 and the ROM board 99 are opposed to the inner surface side of the back wall 113 of the cover body 112 with a predetermined gap therebetween.

Next, the effect interface board 96 and the liquid crystal interface board 97 are connected to each other by direct connectors, and the liquid crystal control board 98 and the ROM board 99 are fitted into predetermined positions inside the cover body 112 from the rear side. At this time, the effect IF third connector CN13 on the effect interface board 96 side connects to the liquid crystal control first connector CN31 on the liquid crystal control board 98 side, and the liquid crystal IF third connector CN23 on the liquid crystal interface board 97 side connects to the liquid crystal on the liquid crystal control board 98 side. Each is coupled to a control second connector CN32.

Subsequently, the base body 111 is fitted to the cover body 112 from the back surfaces 96b and 97b of the presentation interface board 96 and the liquid crystal interface board 97. As shown in FIG. Further, by screwing to the screw base 115 on the side of the cover body 112 through the through holes 114 of the effect interface board 96 and the liquid crystal interface board 97 from the outside of the base body 111, the boards 96 to 99 are connected to the effect board. It is fixed at a predetermined position inside the case 100 . A presentation board case 100 storing boards 96 to 99 is detachably attached to the rear side of the back case 91 with the base body 111 directed to the front side and the cover body 112 directed to the rear side.

On the back side of the front frame 3, as shown in FIG. 7, a back cover 121 is detachably attached to cover the back side of the game board 16 in an openable and closable manner. However, the payout means 32 and the payout passage 124 are mounted on the left and right sides respectively, and when a game ball enters a winning opening of the big winning means 74 or the like, or a ball lending command is issued from an automatic ball lending machine (not shown). When there is, the game balls in the game ball tank 122 are put out by the putting out means 32 via the tank rail 123, and the game balls are guided to the upper tray 33 through the putting-out passage 124.例文帳に追加In addition, the back cover 121 is arranged so as to cover substantially the entire effect board case 100 and a part of the upper side of the main board case 94 from the rear side.

A board mounting base 125 is detachably mounted on the lower back side of the front frame 3. On the back side of the board mounting base 125, a power board case 127 in which a power board 126 is stored, and a payout firing control board. 128 is housed in a payout ejection board case 129, which is detachably mounted.

FIG. 10 is a block diagram showing the overall circuit configuration of this pachinko machine. As shown in FIG. 10, the overall circuit configuration of this pachinko machine is composed of a board-side member 131 mounted on the game board 16 side and a frame-side member 132 mounted on the front frame 3 side.

The board-side member 131 includes a main control board 93 that constitutes the main control unit 92, an effect interface board 96 that constitutes the effect control unit 95, a liquid crystal interface board 97, a liquid crystal control board 98, a ROM board 99, and a game board relay board. 133, an LED connection board 134, a main control relay board 135, a power relay board 136, a frame LED relay board 137, and the like.

The main control board 93 performs overall game control, and includes a game ball detection switch provided in the normal symbol starting means 71 and the big winning means 74, etc., an opening and closing driving means provided in the big winning means 74, etc., a game Various sensors such as magnetism, radio waves, vibration, etc., and the game information display means 60, etc., arranged in each part of the board 16 are directly connected via a relay board such as the game board relay board 133 or directly without a relay board. It is Also, the main control board 93 is connected to the effect interface board 96 via the effect control harness 138, and is capable of transmitting the control command CMD and the strobe signal STB.

The main control relay board 135, the power relay board 136, and the frame LED relay board 137 are for connecting the board-side member 131 to the frame-side member 132. It is connected to the control board 128, and the effect interface board 96 is connected to the power supply board 126 via the power relay board 136, and to the frame LED connection board 139 via the frame LED relay board 137, respectively. On the main control relay board 135, the power relay board 136, and the frame LED relay board 137 on the game board 16 side, board-side first to third connectors CN1a to CN3a are arranged respectively corresponding to the rear side of the game board 16, In the game board mounting portion 14 (FIG. 2) on the inner frame 6 side, the frame side first to third connectors CN1b to CN3b are arranged so as to face the board side first to third connectors CN1a to CN3a, respectively. When the game board 16 is mounted on the game board mounting portion 14 of the inner frame 6 from the front side, the board side first to third connectors CN1a to CN3a are coupled to the frame side first to third connectors CN1b to CN3b, respectively. It has become so. In addition, the first frame-side connector CN1b is provided on one end side of the payout-emission control relay harness 141 connected to the payout-emission control board 128, and the second frame-side connector CN2b is the effect control power supply connected to the power supply board 126. The frame-side third connector CN3b is provided on one end side of the harness 142 and is provided on one end side of the frame-lower LED connection harness 143 connected to the frame-lower LED connection board 139 .

Also, the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98 and the ROM board 99, which constitute the effect control section 95, are integrated with each other by directly connecting the connectors without using a harness as already described. ing.

The liquid crystal display unit 76 is connected to the liquid crystal interface board 97 via a backlight harness 144 and a liquid crystal display unit harness 145 . An LED connection board 134 is connected to the effect interface board 96 via an LED connection harness 146 . In addition to various LED boards on the game board 16 side, the LED connection board 134 is connected to motors used for drive control of the movable bodies 77 to 79, movable body drive means such as solenoids, position detection switches, and the like.

The frame-side member 132 is configured around a power supply board 126 and a payout firing control board 128 . The power supply board 126 receives AC 24V and outputs various DC voltages, and outputs DC 5V, DC 12V, and DC 35V to the payout launch control board 128, and DC 12V to the underframe LED connection board 139. In addition, the power supply relay board 136 DC5V, DC12V, and DC35V are output to the effect interface board 96 via. A backup board 147 is connected to the payout firing control board 128, and from the payout firing control board 128 to the main control board 93, in addition to DC5V, DC12V, and DC35V received from the power supply board 126, a backup power supply, a power failure Signals and the like are output via the main control relay board 135 .

In addition, the payout shooting control board 128 includes a shooting driving means 17d constituting the shooting means 17, an external terminal board 148 for outputting various information to an external host computer, etc., and a rental board for connecting an external game ball rental device. In addition to the device connection terminal plate 149, a frame relay board 150, a tray relay board 151, and the like are connected.

The frame relay board 150 relays the connection between the payout motor 32a, the payout counting switch 32b, the front door/inner frame open switch 152, etc. and the payout firing control board 128, which are arranged on the inner frame 6 side. Also, the tray relay board 151 relays the connection between the discharge connection board 153 on the front door 7 side, the clogged ball detection board 154, the frequency display board 155, etc. and the payout discharge control board 128. The firing connection board 153 is connected to the variable resistor 35a, the firing stop switch 35b, the touch sensor 35c, and the ball feeding solenoid 53c provided in the ball feeding unit 53a.

In addition to the lower speaker 18 on the inner frame 6 side, the frame lower LED connection board 139 is connected to the frame lower left LED connection board 156 on the front door 7 side. To the lower left LED connection board 156 of the frame, an LED board 157 that constitutes the illumination on the front door 7 side, a handle LED board 158 arranged on the firing handle 35, a production button 41 and an LED board inside thereof are connected. A button LED connection board 159, a volume/light amount button board 160 to which the volume/light amount adjustment buttons 39 and 40 are connected, the upper speaker 25, a side unit relay board 161 to be connected to the side unit 30, and the like are connected.

Next, the circuit configurations of the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98 and the ROM board 99 that constitute the effect control section 95 will be described in detail with reference to FIGS. 10 and 11. FIG.

As shown in FIG. 10, the presentation interface board 96 reproduces audio signals based on instructions received from various input/output buffers as well as from a CPU circuit 171 (FIG. 11) mounted on the composite chip 104 of the liquid crystal control board 98. an audio processor 101, an audio ROM 103 for storing compressed audio data or the like which is original data of an audio signal to be reproduced, a digital amplifier 102 for receiving an audio signal output from the audio processor 101, and the like. The audio processor 101 incorporates a WDT circuit that automatically resets the set value of the internal circuit to a default value when the internal circuit malfunctions, and an audio control register SRG. Based on the operation parameters received from the CPU circuit 171 , the audio ROM 103 is accessed to reproduce a necessary audio signal and output it to the digital amplifier 102 .

Various input/output buffers mounted on the effect interface board 96 include input buffers for receiving control commands CMD and strobe signals STB from the main control board 93 and transferring them to the composite chip 104 on the liquid crystal control board 98, frame LED An input buffer for receiving switch signals such as the effect button 41 via the relay board 137 and transferring them to the composite chip 104 of the liquid crystal control board 98, and a serial signal received from the liquid crystal control board 98 via the frame LED relay board 137 and an output buffer for transferring to a driver IC such as an LED board, and an LED connection board 134 for receiving a switch signal such as a position detection switch of a movable body and transferring it to the composite chip 104 of the liquid crystal control board 98 . There are an input buffer, an output buffer for transferring a serial signal received from the liquid crystal control board 98 to a driver IC such as an LED board via the LED connection board 134, and the like.

The liquid crystal control board 98 includes a composite chip (chip) 104 containing a CPU circuit 171, a control ROM (ROM connected to the chip) 105 for storing a control program for the CPU circuit 171, and a large amount of data at high speed. An accessible DRAM (Dynamic Random Access Memory) 106 is mounted, and a ROM board 99 connected to the liquid crystal control board 98 is mounted with a CGROM 107 for storing a large amount of CG data necessary for effect control. ing.

The control ROM 105 is located in the address space CS0 selected by the chip select signal CS0. The DRAM 106 is positioned in the address space CS5 selected by the chip select signal CS5.

FIG. 11 is a circuit block diagram showing the composite chip 104 mounted on the liquid crystal control board 98, including related circuit elements. As shown, the composite chip 104 includes a CPU circuit 171 that issues a display list DL at predetermined time intervals, and a VDP circuit 172 that generates image data based on the issued display list DL and drives the liquid crystal display unit 76. and are built-in. The CPU circuit 171 and the VDP circuit 172 are connected via a CPUIF circuit 173 that relays transmission/reception data between them.

The CPU circuit 171 frequency-multiplies (eg, 8-fold) the oscillation output (eg, 100/3 MHz) from the oscillator OSC1 received at the HCLKI terminal of the composite chip 104 to generate a CPU operating clock of about 266.7 MHz. Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby taking measures against EMI (Electromagnetic Interference) for preventing radio interference/electromagnetic interference.

On the other hand, the VDP circuit 172 frequency-multiplies the oscillation output (for example, 40 MHz) from the oscillator OSC2 received at the PLLREF terminal of the composite chip 104 as necessary, and converts it into the system clock of the VDP circuit 172 and the display for the display device. It is used as a clock (dot clock, etc.) and as a DDR clock for the external DRAM 106 . That is, the output of oscillator OSC2 functions as a reference clock for the entire VDP circuit 172. FIG.

Therefore, considering the importance of this reference clock, the oscillator OSC2 is operated at the same power supply voltage of 3.3 V as the VDP circuit 172, and the output enable terminal OE is at H level (=3.3 V). , a reference clock is oscillated, and when the power supply voltage of 3.3 V drops below a predetermined level, a non-maskable interrupt (NMI) is generated.

The composite chip 104 is also provided with an HBTSL terminal, and based on the logic level of this HBTSL terminal, a ROM for storing a boot program (initial setting program) to be executed after power-on (CPU reset) is specified. . As shown, in this embodiment, HBTSL is set to L, and zero address in the address space CS0 of the CPU circuit 171 is assigned to the control ROM 105. FIG.

The CPUIF circuit 173 is connected to a control ROM 105 for storing control programs and necessary control data in a non-volatile manner, and a work memory (RAM) 174 having a storage capacity of about 2M bytes. It is accessible from circuit 172 .

Control ROM 105 is located in address space CS0 selected by chip select signal CS0, and work memory 174 is located in address space CS6 selected by chip select signal CS6. The work memory 174 reserves a DL buffer BUF for temporarily storing a display list DL containing a series of instruction commands specifying one frame of the liquid crystal display unit 76 .

The CPU circuit 171 is a circuit having performance equivalent to that of a general-purpose one-chip microcomputer, and has an effect control CPU 181 that controls overall image effects based on the control program of the control ROM 105, and a storage capacity of about 16 kbytes. A built-in RAM 182 used as a work area for the CPU, a DMAC (Direct Memory Access Controller) 183 for realizing data transfer without going through the production control CPU 181, and a plurality of input ports Si and output ports So. An output port (SIO) 184, a parallel input/output port (PIO) 185 having a plurality of input ports Pi and output ports Po, a control register (REG) 186 in which setting values are set to control the operation of each of these parts, etc. It has

The parallel input/output port 185 is connected to an external device (effect interface board 96) via an input/output circuit 187 or the like. It receives a command CMD, an interrupt signal STB, and the like.

Also, in this embodiment, the SMC (Serial Management Controller) 188 of the VDP circuit 172 is used for the lighting effect and the movable body effect. The SMC unit 188 incorporates an LED controller and a motor controller, and is capable of outputting serial signals in clock synchronization. Also, the motor controller can output a latch pulse at any timing based on the set value in a predetermined control register, and can input a serial signal in a clock synchronous manner. Therefore, in this embodiment, the motor drive signal and the LED drive signal are output from the SMC unit 187 in synchronization with the clock signal, while the latch pulse is output as the operation control signal ENABLE at appropriate timing. Further, the origin sensor signals SN0 to SNn from the motor groups M1 to Mn constituting the movable body driving means are serially input in a clock synchronous manner.

Next, the details of the wiring pattern and the like of the liquid crystal control board 98 that constitutes the effect control section 95 will be described. The liquid crystal control board 98 has a plurality of wiring layers on a board body 190 (see FIG. 8). 1st to 6th wiring layers L1 to L6 (FIGS. 12 to 17) consisting of 6 wiring layers L6 and 2nd to 5th wiring layers L2 to L5 arranged therebetween. there is The second wiring layer L2 (FIG. 13) is a solid wiring layer connected to the ground, and the fifth wiring layer L5 (FIG. 16) is a solid wiring layer connected to the power supply. In addition, a large number of vias (interlayer conduction portions) are provided in the substrate body 190 of the liquid crystal control substrate 98 in the plate thickness direction, and a plurality of wiring layers L1 to L6 are interconnected through these vias (interlayer conduction portions). Conducted. The vias used in this embodiment are plated through-hole type vias that penetrate from the front surface (first surface) 98a of the substrate body 190 to the rear surface (second surface) 98b.

12 to 17, the left-right direction is the X direction, and the up-down direction is the Y direction. +X/−X directions (sides) are the rightward/leftward directions, and +Y/−Y direction (sides) are the upward/downward directions. The diagonal directions are also expressed as diagonal +XY direction and diagonal -XY direction. 7 and 8, when the liquid crystal control board 98 is attached to the main body 1 of the game machine, the +X direction of the liquid crystal control board 98 faces upward, and the +Y direction of the liquid crystal control board 98 faces rightward toward the main body 1 of the game machine. (facing left when viewed from the back).

As shown in FIG. 12, the first wiring layer L1 on the side of the surface 98a includes a composite chip placement region (first placement region) 191 in which a composite chip (first electronic component) 104 is placed, a control ROM (second A control ROM placement area (second placement area) 192 in which the electronic component, specific electronic component) 105 is placed is provided. The composite chip arrangement area 191 has a substantially square shape corresponding to the shape of the composite chip 104 and is arranged near the central portion of the surface 98 a of the liquid crystal control substrate 98 . In the composite chip arrangement area 191, dot-shaped terminal connection portions corresponding to respective terminals of the composite chip 104 are arranged in a matrix at approximately equal intervals. The composite chip 104 has a total of 1020 terminals arranged in 32 rows and 32 columns (4 corners are missing) on the bottom side, and each terminal is connected to a corresponding terminal connection portion. It is attached to the composite chip placement area 191 in this state.

The control ROM placement area 192 has a substantially rectangular shape elongated in the Y direction corresponding to the shape of the ROM socket 193 (see FIG. 8) in which the control ROM 105 is mounted. It is about the same as The control ROM arrangement area 192 is arranged in the vicinity of the +X side with respect to the composite chip arrangement area 191, and the first and second edges 192a which are the long sides of the control ROM arrangement area 192 on the -X side and the +X side. , 192b faces the first edge 191a on the +X side in the composite chip placement area 191 with a predetermined distance therebetween while being shifted in the -Y direction.

In the control ROM arrangement area 192, a plurality of (here, 35 each) terminal connection portions (ROM terminal connection portions) are arranged along both long sides, that is, along the first and second edges 192a and 192b. ing. A ROM socket 193 for detachably supporting the control ROM 105 is fixed in the control ROM arrangement area 192, and the control ROM 105 is detachably mounted in the ROM socket 193 (FIG. 8). The control ROM 105 has a plurality of terminals (here, 35 terminals each) arranged along both ends thereof, and each of these terminals is connected to each terminal connection part of the control ROM arrangement area 192 via the ROM socket 193 . It is connected.

As shown in FIG. 8, the ROM socket 193 detachably holds a substantially rectangular bottom wall 193a corresponding to the control ROM arrangement area 192 and both edges of the control ROM 105 mounted on the bottom wall 193a. The bottom wall 193a is fixed to the surface 98a of the liquid crystal control board 98 so as to cover substantially the entire control ROM arrangement area 192. As shown in FIG. Therefore, the wiring patterns (vias, etc.) in the control ROM arrangement area 192 in the first wiring layer L1 are shielded by the bottom wall (shielding wall) 193a of the ROM socket 193 even when the control ROM 105 is removed from the ROM socket 193. It cannot be visually recognized from the outside. This makes it possible to increase the preventiveness against fraudulent acts such as unauthorized modification of the wiring pattern connecting the composite chip 104 and the control ROM 105 . By drawing wiring patterns in the control ROM arrangement area 192, wiring space can be secured in other areas.

Further, as shown in FIG. 17, the sixth wiring layer L6 on the back surface 98b side has a first connector arrangement region 194 in which the liquid crystal control first connector CN31 is arranged and a second connector arrangement region 194 in which the liquid crystal control second connector CN32 is arranged. A connector placement area 195 is provided. The first connector arrangement area 194 has a substantially rectangular shape elongated in the X direction, and is arranged near the edge on the +Y side of the rear surface 98 b of the liquid crystal control board 98 . In the first connector arrangement area 194, a plurality of (here, 70 pieces each) terminal connection portions corresponding to the respective terminals of the liquid crystal control first connector CN31 are arranged along a pair of long sides. The second connector arrangement area 195 has a substantially rectangular shape elongated in the X direction, and is arranged in the vicinity of the −Y side edge of the rear surface 98 b of the liquid crystal control board 98 . In the second connector arrangement area 195, a plurality of (here, 50 pieces each) terminal connection portions corresponding to the respective terminals of the liquid crystal control second connector CN32 are arranged along a pair of long sides.

Among all the terminals of the composite chip 104 , the terminals connected to the control ROM 105 are arranged intensively in the vicinity of the first edge 191 a on the control ROM 105 side in the composite chip placement area 191 . FIG. 18 shows the types (terminal information) of some of the terminals in the vicinity of the first edge 191a among all the terminals of the composite chip 104. FIG. The arrangement of each terminal in FIG. 18 matches the arrangement of the terminal connection portions in the composite chip arrangement area 191 in FIG.

In FIG. 18, HAD0 to HAD25 are address output terminals for outputting address information, HDT0 to HDT15 are data input/output terminals for inputting/outputting data information, and HCS0 is a chip select output terminal for outputting a chip select signal. , HRD is a read strobe output terminal for outputting a read strobe signal, and HRESET is a system reset terminal for inputting a system reset signal. In the following description, the reference numerals HAD0 to HAD25, HDT0 to HDT15, etc. of the corresponding terminals of the composite chip 104 are used as they are for the terminal connection portions in the composite chip placement area 191. FIG. For example, the terminal connection portion HRD indicates the terminal connection portion corresponding to the read strobe output terminal HRD.

FIG. 19 also shows the type (terminal information) of each terminal of the control ROM 105 . 19, A0 to A24 are address input terminals for inputting address information, Q0 to Q15 are data input/output terminals for inputting/outputting data information, and address output terminals of the composite chip 104, respectively. , are connected to the data input/output terminals. CE# is a chip select input terminal for inputting a chip select signal and is connected to the chip select output terminal of the composite chip 104 . WE# is a writable input terminal, and by connecting it to the power supply and keeping it at H level, it is possible to switch the mode according to the value (H/L) of the OE# terminal. OE# is an output enable input terminal and is connected to the read strobe output terminal of the composite chip 104 .

RESET# is a reset terminal, which is connected to a power supply voltage monitoring integrated circuit (reset IC) together with a system reset input terminal HRESET of the composite chip 104 . WP#/ACC is a write prohibition/program input terminal, and by connecting it to the ground (L level) or power supply (H level), it is possible to switch between write prohibition/permission and program execution prohibition/permission. there is In this embodiment, the WP#/ACC terminal is connected to the power supply and set to H level. BYTE# is an 8/16-bit mode selection terminal, and by connecting it to the ground (L level) or power supply (H level), it is possible to select either the 8-bit communication mode or the 16-bit communication mode.

In the following description, for the terminal connection portions corresponding to the control ROM arrangement area 192, the symbols A0 to A24, Q0 to Q15, CE#, etc. of the corresponding terminals of the control ROM 105 are used as they are. For example, the terminal connection portion RESET# indicates the terminal connection portion corresponding to the reset terminal RESET#.

Among the many wiring paths provided on the liquid crystal control board 98, a plurality of types of wiring paths P1 to P47 including the wiring path connecting the composite chip 104 and the control ROM 105 will be focused on below. will be described with reference to. 20 to 25 show only the portions forming the wiring paths P1 to P47, respectively, extracted from the wiring patterns of the first to sixth wiring layers L1 to L6 shown in FIGS. 12 to 17. FIG. , and FIGS. 26 to 34 are partially enlarged views thereof. 35 to 40 schematically show the wiring paths of the wiring paths P1 to P47. 35 to 40, vias displayed in gray (for example, via v86 in wiring path P1 in FIG. 35) indicate vias (specific inter-layer conductive portions) arranged in control ROM placement area 192, and are indicated by thick lines. (for example, the wiring path cp13 in the wiring path P2 in FIG. 35) indicated by , indicates the wiring path connected from the inside of the control ROM arrangement area 192 to the terminal connection portion on the control ROM 105 side.

First, wiring paths P1 to P26 connected to address output terminals HAD0 to HAD25 of composite chip 104 will be described. In this embodiment, among the address output terminals HAD0 to HAD25, HAD1 to HAD25 are connected to the address input terminals A0 to A24 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31. On the other hand, the address output terminal HAD0 is connected to the liquid crystal control first connector CN31, but is not connected to the terminal on the control ROM 105 side.

Comparing the arrangement of the address output terminals HAD1 to HAD25 of the composite chip 104 (FIG. 18) with the arrangement of the corresponding address input terminals A0 to A24 of the control ROM 105 (FIG. 19), there is a clear difference between the two. there is That is, the address output terminals HAD1 to HAD25 of the composite chip 104 are arranged in six rows as shown in FIG. The address input terminals A0 to A24 of the ROM 105 are arranged in two columns as shown in FIG. 19, and there is no regularity in the arrangement order in each column. In addition, the arrangement positions of the composite chip 104 and the control ROM 105 and the number of wiring patterns are related to each other, so that the routing of the wiring patterns becomes very complicated. Therefore, it is very important to optimize the routing of the wiring pattern that connects the composite chip 104 and the control ROM 105. This makes it possible to shorten the length of the wiring pattern, thereby reducing noise and slimming down the entire board. It leads to plan. The same applies not only to the relationship between the composite chip 104 and the control ROM 105, but also to the relationship between the composite chip 104 and electronic components such as various connectors. In particular, the wiring pattern connected to a plurality of electronic components such as the composite chip 104 such as HAD1 to HAD25 and HDT1 to HDT25, the control ROM 105, and various connectors poses a great deal of the above-mentioned problems, so the effect of optimization is great. become a thing.

Among the wiring paths P1 to P26, in the wiring path P1 (FIG. 35), as shown in FIG. It is connected to the via v0 arranged in the vicinity in the diagonal -XY direction. The via v0 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD0) arranged around it. As shown in FIG. 28, the via v0 is connected to the via v41 by a wiring path cp1 provided in the third wiring layer L3. This via v41 is arranged between the composite chip placement area 191 and the control ROM placement area 192 . As shown in FIG. 31, the via v41 is connected to the via v86 arranged in the control ROM arrangement region 192 by a wiring path cp2 provided in the fourth wiring layer L4. Thus, the wiring path drawn from the terminal connection portion HAD0 in the first wiring layer L1 is connected to the via v86 in the control ROM placement area 192 via the two wiring layers L3 and L4.

The wiring path extending from the terminal connection portion HAD0 to the via v86 branches into two at the via v86. As shown in FIGS. 28 and 29, the first branch path extends from the via v86 through the via v205 constituting the test point TP28 to the first connector placement region 194 by the wiring path cp3 provided in the third wiring layer L3. 33, is connected to the terminal connection portion had0 from inside the first connector placement region 194 by a wiring path cp4 provided in the sixth wiring layer L6, as shown in FIG. . Also, as shown in FIG. 32, the second branch path is connected from the via v86 to the terminating resistor RA16 by a wiring path cp5 provided in the sixth wiring layer L6. The termination resistor RA16 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 through a predetermined via (not shown in the wiring diagram).

In the wiring path P2 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD1 provided in the composite chip placement region 191 of the first wiring layer L1 is connected to the vicinity of the diagonal -XY direction by the wiring path cp11. is connected to the via v5 located in the . The via v5 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD1) arranged around it. As shown in FIG. 31, this via v5 is connected to a via v85 arranged in the control ROM arrangement region 192 by a wiring path cp12 provided in the fourth wiring layer L4. Thus, unlike the wiring path drawn from the terminal connection portion HAD0, the wiring path drawn from the terminal connection portion HAD1 does not pass through the third wiring layer L3, but passes through the fourth wiring layer L4. It is connected to via v85 in region 192 .

The wiring path extending from the terminal connection portion HAD1 to the via v85 branches into four at the via v85. As shown in FIG. 27, the first branch path is connected from the via v85 to the terminal connection portion A0 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp13 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v85 to the terminating resistor RA16 by the wiring path cp14 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v85 to the via v145 in the first connector placement region 194 by the wiring path cp15 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp16 provided in the sixth wiring layer L6 is connected to the terminal connection portion had1 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v85 to the via v182 by the wiring path cp17 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp18 provided in the sixth wiring layer L6 is connected to the decoder IC12 constituting the decoding circuit.

Although omitted in the wiring diagrams such as FIG. 34, the decoding circuit including the decoders IC12 to IC14 is configured as shown in FIG. As shown in FIG. 41, the decoders IC13 and IC14 are connected to the liquid crystal display unit 76 and the like via the liquid crystal IF third connector CN23 and the like. Data information is entered. Since the decoders IC13 and IC14 output data information to the liquid crystal display unit 76 and the like based on the clock synchronized with the CPU input from the decoder IC12, the CPU does not need to transmit fixed data information each time. This eliminates the need to output the same data information from the CPU every predetermined time, and the CPU only needs to transmit new data information when the content of the data information is changed, thus simplifying the control program. become possible.

In the wiring path P3 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD2 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp21. It is connected to the placed via v4. The via v4 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD2) arranged around it. As shown in FIG. 31, this via v4 is connected to a via v84 arranged in the control ROM arrangement region 192 by a wiring path cp22 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD2 to the via v84 branches into four at the via v84. As shown in FIG. 27, the first branch path is connected from the via v84 to the terminal connection portion A1 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp23 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v84 to the terminating resistor RA16 by a wiring path cp24 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v84 to the via v144 in the first connector placement region 194 by the wiring path cp25 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp26 provided in the sixth wiring layer L6 is connected to the terminal connection part had2 from inside the first connector arrangement area 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v84 to the via v184 by the wiring path cp27 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp28 provided in the sixth wiring layer L6 is connected to the decoder IC12 constituting the decoding circuit.

In the wiring path P4 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD3 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp31. It is connected to the placed via v13. The via v13 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD3) arranged around it. As shown in FIG. 31, this via v13 is connected to a via v83 arranged in the control ROM arrangement region 192 by a wiring path cp32 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD3 to the via v83 branches into four at the via v83. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM arrangement area 192 to the terminal connection portion A2 of the control ROM 105 from the via v83 by the wiring path cp33 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v83 to the terminating resistor RA16 by a wiring path cp34 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v83 to the via v143 in the first connector placement region 194 by the wiring path cp35 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp36 provided in the sixth wiring layer L6 is connected to the terminal connection part had3 from inside the first connector arrangement area 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v83 to the via v181 by the wiring path cp37 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp38 provided in the sixth wiring layer L6 is connected to the decoder IC12 constituting the decoding circuit.

In the wiring path P5 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD4 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp41. It is connected to the placed via v20. The via v20 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD4) arranged around it. As shown in FIG. 31, this via v20 is connected to a via v82 arranged in the control ROM arrangement region 192 by a wiring path cp42 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD4 to the via v82 branches into three at the via v82. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM arrangement area 192 to the terminal connection portion A3 of the control ROM 105 from the via v82 by the wiring path cp43 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v82 to the terminating resistor RA15 by a wiring path cp44 provided in the sixth wiring layer L6. The termination resistor RA15 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 through a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v82 to the via v142 in the first connector placement area 194 by the wiring path cp45 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp46 provided in the sixth wiring layer L6 is connected to the terminal connection part had4 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P6 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD5 provided in the composite chip placement area 191 of the first wiring layer L1 is arranged outside the composite chip placement area 191 by the wiring path cp51. Specifically, it is connected to the via v34 arranged between the composite chip placement area 191 and the control ROM placement area 192 . Note that the terminal connection portion HAD5 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . As shown in FIG. 31, the via v34 is connected to the via v81 arranged in the control ROM arrangement area 192 by a wiring path cp52 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD5 to the via v81 branches into three at the via v81. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM arrangement area 192 to the terminal connection portion A4 of the control ROM 105 from the via v81 by the wiring path cp53 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v81 to the terminating resistor RA15 by a wiring path cp54 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v81 to the via v141 in the first connector placement region 194 by the wiring path cp55 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp56 provided in the sixth wiring layer L6 is connected to the terminal connection part had5 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P7 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD6 provided in the composite chip placement area 191 of the first wiring layer L1 is arranged outside the composite chip placement area 191 by the wiring path cp61. Specifically, it is connected to the via v39 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection portion HAD6 is arranged on the outermost side of the composite chip arrangement area 191 . As shown in FIG. 31, the via v39 is connected to the via v80 arranged in the control ROM arrangement region 192 by a wiring path cp62 provided in the fourth wiring layer L4.

A wiring path extending from the terminal connection portion HAD6 to the via v80 branches into three at the via v80. As shown in FIG. 27, the first branch path is connected from the via v80 to the terminal connection portion A5 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp63 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v80 to the terminating resistor RA15 by a wiring path cp64 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v80 to the via v140 in the first connector placement region 194 by the wiring path cp65 provided in the third wiring layer L3. As shown in FIG. 33, a wiring path cp66 provided in the sixth wiring layer L6 is connected to the terminal connection portion had6 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P8 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD7 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp71. It is connected to the placed via v3. The via v3 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD7) arranged around it. As shown in FIG. 31, the via v3 is connected to a via v79 arranged in the control ROM arrangement region 192 by a wiring path cp72 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD7 to the via v79 branches into three at the via v79. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM arrangement area 192 to the terminal connection portion A6 of the control ROM 105 from the via v79 by the wiring path cp73 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v79 to the terminating resistor RA15 by a wiring path cp74 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v79 to the via v139 in the first connector placement region 194 by the wiring path cp75 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp76 provided in the sixth wiring layer L6 is connected to the terminal connection part had7 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P9 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD8 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp81. It is connected to the placed via v12. The via v12 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD8) arranged around it. As shown in FIG. 31, this via v12 is connected to a via v78 arranged in the control ROM arrangement region 192 by a wiring path cp82 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD8 to the via v78 branches into three at the via v78. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM arrangement area 192 to the terminal connection portion A7 of the control ROM 105 from the via v78 by the wiring path cp83 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v78 to the terminating resistor RA13 by a wiring path cp84 provided in the sixth wiring layer L6. The termination resistor RA13 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 through a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v78 to the via v138 in the first connector placement area 194 by the wiring path cp85 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp86 provided in the sixth wiring layer L6 is connected to the terminal connection portion had8 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P10 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD9 provided in the composite chip placement area 191 of the first wiring layer L1 is arranged outside the composite chip placement area 191 by the wiring path cp91. Specifically, it is connected to the via v33 arranged between the composite chip placement area 191 and the control ROM placement area 192 . The terminal connection portion HAD9 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 31, the via v33 is connected to a via v77 arranged in the control ROM arrangement region 192 by a wiring path cp92 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD9 to the via v77 is branched into three at the via v77. As shown in FIG. 27, the first branch path is connected from the via v77 to the terminal connection portion A8 of the control ROM 105 from inside the control ROM arrangement area 192 by a wiring path cp93 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v77 to the terminating resistor RA13 by a wiring path cp94 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v77 to the via v137 in the first connector placement region 194 by the wiring path cp95 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp96 provided in the sixth wiring layer L6 is connected to the terminal connection part had9 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P11 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD10 provided in the composite chip placement area 191 of the first wiring layer L1 is arranged outside the composite chip placement area 191 by the wiring path cp101. Specifically, it is connected to the via v38 arranged between the composite chip placement area 191 and the control ROM placement area 192 . The terminal connection portion HAD10 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 31, the via v38 is connected to a via v76 arranged in the control ROM arrangement region 192 by a wiring path cp102 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD10 to the via v76 branches into three at the via v76. As shown in FIG. 27, the first branch path is connected from the via v76 to the terminal connection portion A9 of the control ROM 105 from inside the control ROM placement area 192 by the wiring path cp103 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v76 to the terminating resistor RA13 by the wiring path cp104 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v76 to the via v136 in the first connector placement region 194 by the wiring path cp105 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp106 provided in the sixth wiring layer L6 is connected to the terminal connection part had10 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P12 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD11 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal -X+Y direction by the wiring path cp111. is connected to the via v2 connected to the The via v2 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD11) arranged around it. As shown in FIG. 31, this via v2 is connected to a via v75 arranged in the control ROM arrangement region 192 by a wiring path cp112 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD11 to the via v75 branches into three at the via v75. As shown in FIG. 27, the first branch path is connected from the via v75 to the terminal connection portion A10 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp113 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v75 to the terminating resistor RA13 by the wiring path cp114 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v75 to the via v135 in the first connector placement area 194 by the wiring path cp115 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp116 provided in the sixth wiring layer L6 is connected to the terminal connection part had11 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P13 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD12 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp121. It is connected to the placed via v19. The via v19 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD12) arranged around it. As shown in FIG. 31, this via v19 is connected to a via v74 arranged in the control ROM arrangement region 192 by a wiring path cp122 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD12 to the via v74 branches into three at the via v74. As shown in FIG. 27, the first branch path is connected from the via v74 to the terminal connection portion A11 of the control ROM 105 from inside the control ROM placement area 192 by the wiring path cp123 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v74 to the terminating resistor RA11 by the wiring path cp124 provided in the sixth wiring layer L6. The termination resistor RA11 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v74 to the via v134 in the first connector placement region 194 by the wiring path cp125 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp126 provided in the sixth wiring layer L6 is connected to the terminal connection part had12 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P14 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD13 provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the outside of the composite chip placement area 191 by the wiring path cp131. Specifically, it is connected to the via v49 arranged on the +Y side of the control ROM arrangement area 192 . The terminal connection portion HAD13 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 31, the via v49 is connected to the via v73 arranged in the control ROM arrangement region 192 by a wiring path cp132 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD13 to the via v73 branches into two at the via v73. As shown in FIG. 32, the first branch path is connected from the via v73 to the terminating resistor RA11 by a wiring path cp133 provided in the sixth wiring layer L6.

Also, as shown in FIG. 28, the second branch path is connected from the via v73 to the via v107 arranged in the control ROM arrangement area 192 by the wiring path cp134 provided in the third wiring layer L3. , where it branches further into two. As shown in FIG. 27, the first branch path 2a is connected to the terminal connection portion A12 of the control ROM 105 from the via v107 by the wiring path cp135 provided in the first wiring layer L1. 192 is connected from the inside. As shown in FIGS. 28 and 29, the second branch path 2b is connected from the via v107 to the via v133 in the first connector placement area 194 by the wiring path cp136 provided in the third wiring layer L3. Further, as shown in FIG. 33, a wiring path cp137 provided in the sixth wiring layer L6 is connected to the terminal connection part had13 from inside the first connector arrangement region 194. FIG.

In the wiring path P15 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD14 provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the outside of the composite chip placement area 191 by the wiring path cp141. Specifically, it is connected to the via v50 arranged on the +Y side of the control ROM arrangement area 192 . The terminal connection portion HAD14 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 31, the via v50 is connected to a via v72 arranged in the control ROM arrangement region 192 by a wiring path cp142 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD14 to the via v72 branches into two at the via v72. As shown in FIG. 32, the first branch path is connected from the via v72 to the terminating resistor RA11 by a wiring path cp143 provided in the sixth wiring layer L6.

Also, as shown in FIG. 28, the second branch path is connected from the via v72 to the via v106 arranged in the control ROM arrangement area 192 by the wiring path cp144 provided in the third wiring layer L3. , where it branches further into two. As shown in FIG. 27, the first branch path 2a is connected to the terminal connection portion A13 of the control ROM 105 from the via v106 by the wiring path cp145 provided in the first wiring layer L1. 192 is connected from the inside. As shown in FIGS. 28 and 29, the second 2b branch path is connected from the via v106 to the via v132 in the first connector placement region 194 by the wiring path cp146 provided in the third wiring layer L3. Further, as shown in FIG. 33, a wiring path cp147 provided in the sixth wiring layer L6 is connected to the terminal connection part had14 from inside the first connector arrangement area 194. FIG.

In the wiring path P16 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD15 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp151. It is connected to the placed via v11. The via v11 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD15) arranged around it. As shown in FIG. 31, this via v11 is connected to a via v71 arranged in the control ROM arrangement region 192 by a wiring path cp152 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD15 to the via v71 branches into two at the via v71. As shown in FIG. 32, the first branch path is connected from the via v71 to the terminating resistor RA11 by a wiring path cp153 provided in the sixth wiring layer L6.

Also, as shown in FIG. 28, the second branch path is connected from the via v71 to the via v105 arranged in the control ROM arrangement area 192 by the wiring path cp154 provided in the third wiring layer L3. , where it branches further into two. As shown in FIG. 27, the first branch path 2a is connected to the terminal connection portion A14 of the control ROM 105 from the via v105 by the wiring path cp155 provided in the first wiring layer L1. 192 is connected from the inside. As shown in FIGS. 28 and 29, the second 2b branch path is connected from the via v105 to the via v131 in the first connector placement area 194 by the wiring path cp156 provided in the third wiring layer L3. Further, as shown in FIG. 33, a wiring path cp157 provided in the sixth wiring layer L6 is connected to the terminal connection part had15 from inside the first connector arrangement region 194. FIG.

In the wiring path P17 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD16 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp161. It is connected to the placed via v18. The via v18 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD16) arranged around it. As shown in FIG. 31, this via v18 is connected to a via v70 arranged in the control ROM arrangement region 192 by a wiring path cp162 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD16 to the via v70 branches into two at the via v70. As shown in FIG. 32, the first branch path is connected from the via v70 to the terminating resistor RA10 by a wiring path cp163 provided in the sixth wiring layer L6. The other end of the termination resistor RA10 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (not shown in the wiring diagram).

Also, as shown in FIG. 28, the second branch path is connected from the via v70 to the via v104 arranged in the control ROM arrangement area 192 by the wiring path cp164 provided in the third wiring layer L3. , where it branches further into two. As shown in FIG. 27, the first branch path 2a is connected to the terminal connection portion A15 of the control ROM 105 from the via v104 by the wiring path cp165 provided in the first wiring layer L1. 192 from outside. As shown in FIGS. 28 and 29, the second branch path 2b is connected from the via v104 to the via v130 in the first connector placement region 194 by the wiring path cp166 provided in the third wiring layer L3. Further, as shown in FIG. 33, a wiring path cp167 provided in the sixth wiring layer L6 is connected to the terminal connection part had16 from inside the first connector arrangement area 194. FIG.

In the wiring path P18 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD17 provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the outside of the composite chip placement area 191 by the wiring path cp171. Specifically, it is connected to the via v51 arranged on the +Y side of the control ROM arrangement area 192 . The terminal connection portion HAD17 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 31, the via v51 is connected to a via v69 arranged in the control ROM arrangement region 192 by a wiring path cp172 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD17 to the via v69 branches into two at the via v69. As shown in FIG. 32, the first branch path is connected from the via v69 to the termination resistor RA10 by a wiring path cp173 provided in the sixth wiring layer L6.

Also, as shown in FIG. 28, the second branch path is connected from the via v69 to the via v103 arranged in the control ROM arrangement area 192 by the wiring path cp174 provided in the third wiring layer L3. , where it branches further into two. As shown in FIG. 27, the first branch path 2a is connected to the terminal connection portion A16 of the control ROM 105 from the via v103 by the wiring path cp175 provided in the first wiring layer L1. 192 from outside. As shown in FIGS. 28 and 29, the second branch path 2b is connected from the via v103 to the via v129 in the first connector placement region 194 by the wiring path cp176 provided in the third wiring layer L3. Further, as shown in FIG. 33, a wiring path cp177 provided in the sixth wiring layer L6 is connected to the terminal connection part had17 from inside the first connector arrangement area 194. FIG.

In the wiring path P19 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD18 provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the outside of the composite chip placement area 191 by the wiring path cp181. Specifically, it is connected to the via v52 arranged on the +Y side of the control ROM arrangement area 192 . It should be noted that the terminal connection portion HAD18 is arranged on the outermost side of the composite chip arrangement area 191 . As shown in FIG. 31, the via v52 is connected to the via v68 arranged in the control ROM arrangement region 192 by a wiring path cp182 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD18 to the via v68 branches into three at the via v68. As shown in FIG. 27, the first branch path is connected from the via v68 to the terminal connection portion A17 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp183 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v68 to the terminating resistor RA10 by the wiring path cp184 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v68 to the via v128 in the first connector placement region 194 by the wiring path cp185 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp186 provided in the sixth wiring layer L6 is connected to the terminal connection part had18 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P20 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD19 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp191. It is connected to the placed via v1. The via v1 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD19) arranged around it. As shown in FIG. 31, this via v1 is connected to a via v67 arranged in the control ROM arrangement region 192 by a wiring path cp192 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD19 to the via v67 branches into three at the via v67. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM placement area 192 from the via v67 to the terminal connection portion A18 of the control ROM 105 by the wiring path cp193 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v67 to the terminating resistor RA10 by a wiring path cp194 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v67 to the via v127 in the first connector placement region 194 by the wiring path cp195 provided in the third wiring layer L3. As shown in FIG. 33, a wiring path cp196 provided in the sixth wiring layer L6 is connected to the terminal connection part had19 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P21 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD20 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp201. It is connected to the placed via v10. The via v10 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD20) arranged around it. As shown in FIG. 31, this via v10 is connected to a via v66 arranged in the control ROM arrangement region 192 by a wiring path cp202 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD20 to the via v66 branches into three at the via v66. As shown in FIG. 27, the first branch path is connected from the via v66 to the terminal connection portion A19 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp203 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v66 to the terminating resistor RA9 by a wiring path cp204 provided in the sixth wiring layer L6. The terminating resistor RA9 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 through a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v66 to the via v126 in the first connector placement region 194 by the wiring path cp205 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp206 provided in the sixth wiring layer L6 is connected to the terminal connection part had20 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P22 (FIG. 37), as shown in FIGS. 26 and 27, the terminal connection portion HAD21 provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the composite chip placement area 191 by the wiring path cp211. is connected to the via v54 arranged on the outside of the control ROM arrangement area 192, specifically on the +Y side of the control ROM arrangement area 192. As shown in FIG. The terminal connection portion HAD21 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. The via v54 is connected to the via v65 arranged in the control ROM arrangement region 192 by a wiring path cp212 provided in the fourth wiring layer L4, as shown in FIG.

The wiring path extending from the terminal connection portion HAD21 to the via v65 branches into three at the via v65. As shown in FIG. 27, the first branch path is connected from the via v65 to the terminal connection portion A20 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp213 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v65 to the terminating resistor RA9 by a wiring path cp214 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v65 to the via v125 in the first connector placement region 194 by the wiring path cp215 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp216 provided in the sixth wiring layer L6 is connected to the terminal connection part had21 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P23 (FIG. 37), as shown in FIGS. 26 and 27, the terminal connection portion HAD22 provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the composite chip placement area 191 by the wiring path cp221. is connected to the via v53 arranged on the outside of the control ROM arrangement area 192, specifically on the +Y side of the control ROM arrangement area 192. As shown in FIG. The terminal connection portion HAD22 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 31, the via v53 is connected to the via v64 arranged in the control ROM arrangement region 192 by a wiring path cp222 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HAD22 to the via v64 branches into three at the via v64. As shown in FIG. 27, the first branch path is connected from the via v64 to the terminal connection portion A21 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp223 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v64 to the terminating resistor RA9 by a wiring path cp224 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v64 to the via v124 in the first connector placement region 194 by the wiring path cp225 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp226 provided in the sixth wiring layer L6 is connected to the terminal connection part had22 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P24 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD23 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp231. is connected to the via v21. The via v21 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD23) arranged around it. As shown in FIG. 31, the via v21 is formed outside the composite chip placement region 191, specifically, between the composite chip placement region 191 and the control ROM placement region 192 by the wiring path cp232 provided in the fourth wiring layer L4. 26 and 27, the via v63 arranged in the control ROM arrangement area 192 is connected to the via v36 arranged between It is connected.

The wiring path extending from the terminal connection portion HAD23 to the via v63 branches into three at the via v63. As shown in FIG. 27, the first branch path is connected from the via v63 to the terminal connection portion A22 of the control ROM 105 from outside the control ROM arrangement area 192 by the wiring path cp234 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v63 to the terminating resistor RA9 by a wiring path cp235 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v63 to the via v123 in the first connector placement region 194 by the wiring path cp236 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp237 provided in the sixth wiring layer L6 is connected to the terminal connection part had23 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P25 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD24 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp241. is connected to via v14. The via v14 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD24) arranged around it. As shown in FIG. 31, the via v14 is formed outside the composite chip placement region 191, specifically, between the composite chip placement region 191 and the control ROM placement region 192 by the wiring path cp242 provided in the fourth wiring layer L4. 26 and 27, the wiring path cp243 provided in the first wiring layer L1 connects to the via v62 arranged in the control ROM arrangement region 192. It is connected.

The wiring path extending from the terminal connection portion HAD24 to the via v62 branches into four at the via v62. As shown in FIG. 27, the first branch path is connected from the outside of the control ROM arrangement area 192 to the terminal connection portion A23 of the control ROM 105 from the via v62 by the wiring path cp244 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v62 to the terminating resistor R45 by the wiring path cp245 provided in the sixth wiring layer L6. The terminating resistor R45 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 through a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v62 to the via v122 in the first connector placement area 194 by the wiring path cp246 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp247 provided in the sixth wiring layer L6 is connected to the terminal connection part had24 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v62 to the via v183 by the wiring path cp248 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp249 provided in the sixth wiring layer L6 is connected to the decoder IC12 constituting the decoding circuit.

In the wiring path P26 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD25 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp251. is connected to via v6. The via v6 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD25) arranged around it. As shown in FIG. 31, the via v6 is formed outside the composite chip placement region 191, specifically, between the composite chip placement region 191 and the control ROM placement region 192 by the wiring path cp252 provided in the fourth wiring layer L4. 26 and 27, the wiring path cp253 provided in the first wiring layer L1 connects the via v61 arranged in the control ROM arrangement region 192 to the via v40 arranged between It is connected.

The wiring path extending from the terminal connection portion HAD25 to the via v61 branches into three at the via v61. As shown in FIG. 27, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v61 to the terminal connection portion A24 of the control ROM 105 by the wiring path cp254 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v61 to the terminating resistor R44 by the wiring path cp255 provided in the sixth wiring layer L6. The terminating resistor R44 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 through a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v61 to the via v121 in the first connector placement region 194 by the wiring path cp256 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp257 provided in the sixth wiring layer L6 is connected to the terminal connection part had25 from inside the first connector arrangement region 194. As shown in FIG.

Next, the wiring paths P27 to P42 connected to the data input/output terminals HDT0 to HDT15 of the composite chip 104 will be described. The data input/output terminals HDT0 to HDT15 are connected to the data input/output terminals Q0 to Q15 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31.

Comparing the arrangement of the data input/output terminals HDT0 to HDT15 of the composite chip 104 (FIG. 18) with the corresponding arrangement of the data input/output terminals Q0 to Q15 of the control ROM 105 (FIG. 19), there is a clear difference between the two. is doing. That is, the data input/output terminals HDT0 to HDT15 of the composite chip 104 are arranged in four rows as shown in FIG. The data input/output terminals Q0 to Q15 of the control ROM 105 are arranged in two columns as shown in FIG. 19, and the arrangement order in each column is not regular. In addition, the arrangement positions of the composite chip 104 and the control ROM 105 and the number of wiring patterns are related to each other, so that the routing of the wiring patterns becomes very complicated. Therefore, it is very important to optimize the routing of the wiring pattern that connects the composite chip 104 and the control ROM 105. This makes it possible to shorten the length of the wiring pattern, thereby reducing noise and slimming down the entire board. It leads to plan. The same applies not only to the relationship between the composite chip 104 and the control ROM 105, but also to the relationship between the composite chip 104 and electronic components such as various connectors. In particular, the wiring pattern connected to a plurality of electronic components such as the composite chip 104 such as HAD1 to HAD25 and HDT1 to HDT25, the control ROM 105, and various connectors poses a great deal of the above-mentioned problems, so the effect of optimization is great. become a thing.

Among the wiring paths P27 to P42, in the wiring path P27 (FIG. 38), as shown in FIG. It is connected to a via v32 arranged outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. FIG. Terminal connection portion HDT0 is arranged on the outermost side of composite chip arrangement region 191 . As shown in FIG. 31, the via v32 is connected to the via v102 arranged in the control ROM arrangement region 192 by a wiring path cp302 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT0 to the via v102 branches into four at the via v102. As shown in FIG. 27, the first branch path is connected from the outside of the control ROM arrangement area 192 to the terminal connection portion Q0 of the control ROM 105 from the via v102 by the wiring path cp303 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v102 to the terminating resistor RA34 by the wiring path cp304 provided in the sixth wiring layer L6. The termination resistor RA34 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 through a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v102 to the via v162 in the first connector placement region 194 by the wiring path cp305 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp306 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt0 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v102 to the via v197 by the wiring path cp307 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp308 provided in the sixth wiring layer L6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P28 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT1 provided in the composite chip placement area 191 of the first wiring layer L1 is arranged outside the composite chip placement area 191 by the wiring path cp311. Specifically, it is connected to the via v31 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection portion HDT1 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . The via v31 is connected to the via v101 arranged in the control ROM arrangement region 192 by a wiring path cp312 provided in the fourth wiring layer L4, as shown in FIG.

The wiring path extending from the terminal connection portion HDT1 to the via v101 branches into four at the via v101. As shown in FIG. 27, the first branch path is connected from the via v101 to the terminal connection portion Q1 of the control ROM 105 from outside the control ROM arrangement area 192 by the wiring path cp313 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v101 to the terminating resistor RA34 by a wiring path cp314 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v101 to the via v161 in the first connector placement region 194 by the wiring path cp315 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp316 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt1 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v101 to the via v198 by the wiring path cp317 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp318 provided in the sixth wiring layer L6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P29 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT2 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp321. is connected to via v24. The via v24 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT2) arranged around it. As shown in FIG. 31, the via v24 is connected to the via v100 arranged in the control ROM arrangement region 192 by a wiring path cp322 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT2 to the via v100 branches into four at the via v100. As shown in FIG. 27, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v100 to the terminal connection portion Q2 of the control ROM 105 by the wiring path cp323 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v100 to the terminating resistor RA34 by a wiring path cp324 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v100 to the via v160 in the first connector placement area 194 by the wiring path cp325 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp326 provided in the sixth wiring layer L6 connects to the terminal connection portion hdt2 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v100 to the via v199 by the wiring path cp327 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp328 provided in the sixth wiring layer L6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P30 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT3 provided in the composite chip placement region 191 of the first wiring layer L1 is connected to the vicinity of the diagonal -XY direction by the wiring path cp331. is connected to the via v8 located in the . The via v8 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT3) arranged around it. As shown in FIG. 31, this via v8 is connected to a via v99 arranged in the control ROM arrangement region 192 by a wiring path cp332 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT3 to the via v99 branches into four at the via v99. As shown in FIG. 27, the first branch path is connected from the outside of the control ROM arrangement area 192 to the terminal connection portion Q3 of the control ROM 105 from the via v99 by the wiring path cp333 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v99 to the terminating resistor RA34 by a wiring path cp334 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v99 to the via v159 in the first connector placement region 194 by the wiring path cp335 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp336 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt3 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v99 to the via v200 by the wiring path cp337 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp338 provided in the sixth wiring layer L6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P31 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT4 provided in the composite chip placement area 191 of the first wiring layer L1 is arranged outside the composite chip placement area 191 by the wiring path cp341. Specifically, it is connected to the via v37 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection part HDT4 is arranged on the outermost side of the composite chip arrangement area 191 . The via v37 is connected to a via v98 arranged in the control ROM arrangement region 192 by a wiring path cp342 provided in the fourth wiring layer L4, as shown in FIG.

The wiring path extending from the terminal connection portion HDT4 to the via v98 branches into four at the via v98. As shown in FIG. 27, the first branch path is connected from the outside of the control ROM arrangement area 192 to the terminal connection portion Q4 of the control ROM 105 from the via v98 by the wiring path cp343 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v98 to the terminating resistor RA32 by a wiring path cp344 provided in the sixth wiring layer L6. The termination resistor RA32 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 through a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v98 to the via v158 in the first connector placement region 194 by the wiring path cp345 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp346 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt4 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v98 to the via v189 by the wiring path cp347 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp348 provided in the sixth wiring layer L6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P32 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT5 provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the outside of the composite chip placement area 191 by the wiring path cp351. Specifically, it is connected to the via v46 arranged between the composite chip placement area 191 and the control ROM placement area 192 . Note that the terminal connection portion HDT5 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . The via v46, as shown in FIG. 31, is connected to a via v97 arranged in the control ROM arrangement region 192 by a wiring path cp352 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT5 to the via v97 branches into four at the via v97. As shown in FIG. 27, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v97 to the terminal connection portion Q5 of the control ROM 105 by the wiring path cp353 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v97 to the terminating resistor RA32 by a wiring path cp354 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v97 to the via v157 in the first connector placement region 194 by the wiring path cp355 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp356 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt5 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v97 to the via v190 by the wiring path cp357 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp358 provided in the sixth wiring layer L6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P33 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT6 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp361. is connected to via v17. The via v17 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT6) arranged around it. As shown in FIG. 31, the via v17 is connected to a via v96 arranged in the control ROM arrangement region 192 by a wiring path cp362 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT6 to the via v96 branches into four at the via v96. As shown in FIG. 27, the first branch path is connected from the outside of the control ROM arrangement area 192 to the terminal connection portion Q6 of the control ROM 105 from the via v96 by the wiring path cp363 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v96 to the terminating resistor RA32 by a wiring path cp364 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v96 to the via v156 in the first connector placement region 194 by the wiring path cp365 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp366 provided in the sixth wiring layer L6 connects to the terminal connection portion hdt6 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v96 to the via v195 by the wiring path cp367 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp368 provided in the sixth wiring layer L6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P34 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT7 provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the outside of the composite chip placement area 191 by the wiring path cp371. Specifically, it is connected to the via v45 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection part HDT7 is arranged on the outermost side of the composite chip arrangement area 191 . The via v45 is connected to a via v95 arranged in the control ROM arrangement region 192 by a wiring path cp372 provided in the fourth wiring layer L4, as shown in FIG.

The wiring path extending from the terminal connection portion HDT7 to the via v95 branches into four at the via v95. As shown in FIG. 27, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v95 to the terminal connection portion Q7 of the control ROM 105 by the wiring path cp373 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v95 to the terminating resistor RA32 by a wiring path cp374 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v95 to the via v155 in the first connector placement region 194 by the wiring path cp375 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp376 provided in the sixth wiring layer L6 connects to the terminal connection portion hdt7 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v95 to the via v196 by the wiring path cp377 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp378 provided in the sixth wiring layer L6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P35 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT8 provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the outside of the composite chip placement area 191 by the wiring path cp381. Specifically, it is connected to the via v44 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection portion HDT8 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . As shown in FIG. 31, the via v44 is connected to a via v94 arranged in the control ROM arrangement region 192 by a wiring path cp382 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT8 to the via v94 branches into four at the via v94. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v94 to the terminal connection portion Q8 of the control ROM 105 by the wiring path cp383 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v94 to the terminating resistor RA30 by a wiring path cp384 provided in the sixth wiring layer L6. The termination resistor RA30 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 through a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v94 to the via v154 in the first connector placement region 194 by the wiring path cp385 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp386 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt8 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v94 to the via v191 by the wiring path cp387 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp388 provided in the sixth wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P36 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT9 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp391. is connected to the via v23. The via v23 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT9) arranged around it. As shown in FIG. 31, this via v23 is connected to a via v93 arranged in the control ROM arrangement region 192 by a wiring path cp392 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT9 to the via v93 branches into four at the via v93. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM arrangement area 192 to the terminal connection portion Q9 of the control ROM 105 from the via v93 by the wiring path cp393 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v93 to the terminating resistor RA30 by a wiring path cp394 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v93 to the via v153 in the first connector placement region 194 by the wiring path cp395 provided in the third wiring layer L3. As shown in FIG. 33, a wiring path cp396 provided in the sixth wiring layer L6 connects to the terminal connection portion hdt9 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v93 to the via v192 by the wiring path cp397 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp398 provided in the sixth wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P37 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT10 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp401. is connected to via v16. The via v16 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT10) arranged around it. As shown in FIG. 31, this via v16 is connected to a via v92 arranged in the control ROM arrangement region 192 by a wiring path cp402 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT10 to the via v92 branches into four at the via v92. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v92 to the terminal connection portion Q10 of the control ROM 105 by the wiring path cp403 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v92 to the terminating resistor RA30 by a wiring path cp404 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v92 to the via v152 in the first connector placement region 194 by the wiring path cp405 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp406 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt10 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v92 to the via v193 by the wiring path cp407 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp408 provided in the sixth wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P38 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT11 provided in the composite chip arrangement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp411. is connected to via v7. The via v7 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT11) arranged around it. As shown in FIG. 31, this via v7 is connected to a via v91 arranged in the control ROM arrangement region 192 by a wiring path cp412 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT11 to the via v91 branches into four at the via v91. As shown in FIG. 27, the first branch path is connected from the via v91 to the terminal connection portion Q11 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp413 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v91 to the terminating resistor RA30 by the wiring path cp414 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v91 to the via v151 in the first connector placement region 194 by the wiring path cp415 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp416 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt11 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v91 to the via v194 by the wiring path cp417 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp418 provided in the sixth wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P39 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT12 provided in the composite chip placement area 191 of the first wiring layer L1 is arranged outside the composite chip placement area 191 by the wiring path cp421. Specifically, it is connected to the via v43 arranged between the composite chip placement area 191 and the control ROM placement area 192 . The terminal connection portion HDT12 is arranged on the outermost side of the composite chip arrangement region 191 . As shown in FIG. 31, the via v43 is connected to a via v90 arranged in the control ROM arrangement region 192 by a wiring path cp422 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT12 to the via v90 branches into four at the via v90. As shown in FIG. 27, the first branch path is connected from the via v90 to the terminal connection portion Q12 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp423 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v90 to the terminating resistor RA17 by a wiring path cp424 provided in the sixth wiring layer L6. The terminal resistor RA17 has the other end connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (not shown in the wiring diagram).

28 and 29, the third branch path is connected from the via v90 to the via v150 in the first connector placement region 194 by the wiring path cp425 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp426 provided in the sixth wiring layer L6 connects to the terminal connection portion hdt12 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v90 to the via v185 by the wiring path cp427 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp428 provided in the sixth wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P40 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT13 provided in the composite chip placement area 191 of the first wiring layer L1 is arranged outside the composite chip placement area 191 by the wiring path cp431. Specifically, it is connected to the via v42 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection portion HDT13 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . As shown in FIG. 31, the via v42 is connected to the via v89 arranged in the control ROM arrangement region 192 by a wiring path cp432 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT13 to the via v89 branches into four at the via v89. As shown in FIG. 27, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v89 to the terminal connection portion Q13 of the control ROM 105 by the wiring path cp433 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v89 to the terminating resistor RA17 by a wiring path cp434 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v89 to the via v149 in the first connector placement region 194 by the wiring path cp435 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp436 provided in the sixth wiring layer L6 connects to the terminal connection portion hdt13 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v89 to the via v186 by the wiring path cp437 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp438 provided in the sixth wiring layer L6 is connected to the decoder IC14 constituting the decoding circuit.

In the wiring path P41 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT14 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp441. is connected to the via v22. The via v22 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT14) arranged around it. As shown in FIG. 31, this via v22 is connected to a via v88 arranged in the control ROM arrangement region 192 by a wiring path cp442 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT14 to the via v88 is branched into four at the via v88. As shown in FIG. 27, the first branch path is connected from the via v88 to the terminal connection portion Q14 of the control ROM 105 from inside the control ROM placement area 192 by the wiring path cp443 provided in the first wiring layer L1. It is Also, as shown in FIG. 32, the second branch path is connected from the via v88 to the terminating resistor RA17 by a wiring path cp444 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v88 to the via v148 in the first connector placement region 194 by the wiring path cp445 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp446 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt14 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v88 to the via v187 by the wiring path cp447 provided in the third wiring layer L3, and further, as shown in FIG. A wiring path cp448 provided in the sixth wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P42 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT15 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp451. is connected to via v15. The via v15 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT15) arranged around it. As shown in FIG. 31, this via v15 is connected to a via v87 arranged in the control ROM arrangement region 192 by a wiring path cp452 provided in the fourth wiring layer L4.

The wiring path extending from the terminal connection portion HDT15 to the via v87 branches into four at the via v87. As shown in FIG. 27, the first branch path is connected to the terminal connection portion Q15/A-1 of the control ROM 105 from the via v87 by the wiring path cp453 provided in the first wiring layer L1. connected from the inside. Also, as shown in FIG. 32, the second branch path is connected from the via v87 to the terminating resistor RA17 by a wiring path cp454 provided in the sixth wiring layer L6.

28 and 29, the third branch path is connected from the via v87 to the via v147 in the first connector placement region 194 by the wiring path cp455 provided in the third wiring layer L3. As shown in FIG. 33, the wiring path cp456 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt15 from inside the first connector arrangement region 194. As shown in FIG. 28 and 30, the fourth branch path is connected from the via v87 to the via v188 by the wiring path cp457 provided in the third wiring layer L3, and further, as shown in FIG. It is connected to the decoder IC 14 by a wiring path cp458 provided in the sixth wiring layer L6.

Next, wiring paths P43 to P45 connected to the chip select output terminal HCS0, the read strobe output terminal HRD, and the system reset terminal HRESET of the composite chip 104 will be described.

In the wiring path P43 (FIG. 40), as shown in FIG. 26, the terminal connection portion HCS0 provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal -X+Y direction by the wiring path cp501. is connected to the via v9 connected to it, and is branched into two here. The via v9 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HCS0) arranged around it. As shown in FIG. 25, the first branch path in the via v9 is connected to the via v60 arranged in the control ROM placement area 192 by the wiring path cp502 provided in the sixth wiring layer L6. 2, the wiring path cp503 provided in the first wiring layer L1 is connected to the terminal connection portion CE# from inside the control ROM arrangement region 192. As shown in FIG.

Also, as shown in FIG. 23, the second branch path in the via v9 is connected to the via v173 by a wiring path cp504 provided in the fourth wiring layer L4, where it is further branched into two. The 2a-th branch path in this via v173 is connected to the via v201 by a wiring path cp505 provided in the sixth wiring layer L6, as shown in FIG. This via v201 forms a test point TP33. Also, as shown in FIG. 20, the 2b-th branch path in the via v173 is connected to DC 3.3V (fifth wiring layer L5) through a resistor RA12 by a wiring path cp506 provided in the first wiring layer L1. there is

In the wiring path P44 (FIG. 40), as shown in FIG. 20, the terminal connection portion HRD provided in the composite chip placement region 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp511. It is connected to the arranged via v25 and branches into two here. The via v25 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HRD) arranged around it. As shown in FIG. 25, the first branch path in the via v25 is connected to the outside of the composite chip placement area 191, specifically the composite chip placement area 191 and controlled by the wiring path cp512 provided in the sixth wiring layer L6. It is connected to the via v47 arranged between the ROM arrangement area 192 and furthermore, as shown in FIG. It is connected from outside the area 192 .

Also, as shown in FIG. 22, the second branch path in the via v25 is connected to the via v172 by a wiring path cp514 provided in the third wiring layer L3, and is further branched into two. As shown in FIG. 22, the 2a branch path of the via v172 is connected to the via v171 arranged near the outside of the first connector placement region 194 by a wiring path cp515 provided in the third wiring layer L3. Further, as shown in FIG. 25, the wiring path cp516 provided in the sixth wiring layer L6 is connected to the terminal connection portion hrd from the outside of the first connector arrangement region 194. As shown in FIG. Also, as shown in FIG. 20, the 2b-th branch path in the via v172 is connected to DC 3.3V (fifth wiring layer L5) through a resistor RA8 by a wiring path cp517 provided in the first wiring layer L1. there is

In the wiring path P45 (FIG. 40), as shown in FIG. 20, the terminal connection portion HRESET provided in the composite chip placement area 191 of the first wiring layer L1 is connected to the outside of the composite chip placement area 191 ( +X side). The terminal connection portion HRESET is arranged on the outermost side of the composite chip arrangement area 191 . The via v26 is connected to the via v202 by a wiring path cp522 provided in the fourth wiring layer L4, as shown in FIG. is connected to via v174 by , where it branches into two.

As shown in FIG. 25, the first branch path in the via v174 is connected to the via v108 arranged near the outside (+X side) of the control ROM arrangement area 192 by the wiring path cp524 provided in the sixth wiring layer L6. Further, as shown in FIG. 27, a wiring path cp525 provided in the first wiring layer L1 is connected to the terminal connection portion RESET# from inside the control ROM arrangement area 192. FIG. As shown in FIG. 25, the wiring path cp524 of the sixth wiring layer L6 is connected to DC 3.3 V (fifth wiring layer L5) through a resistor R40, and grounded (second wiring layer L5) through a capacitor C151. L2).

Also, as shown in FIG. 20, the second branch path in the via v174 is connected to the via v204 by a wiring path cp526 provided in the first wiring layer L1. This via v204 constitutes the test point TP17. The via v204 is connected to the reset circuit on the sixth wiring layer L6 side. That is, as shown in FIG. 25, the via v204 is connected to the resistor built-in transistor T1 by a wiring path cp527 provided in the sixth wiring layer L6, further connected to the logic integrated circuit IC7 by a wiring path cp528, and further connected to the logic integrated circuit IC7 by a wiring path cp529. , is connected to the WDT built-in reset integrated circuit (reset IC) IC10 via a via v203 forming the test point TP23. The wiring path cp528 is connected to DC 3.3V (fifth wiring layer L5) through a resistor R19, the wiring path cp529 is connected to the ground (second wiring layer L2) through a capacitor C40, and the resistor R26 is connected. are connected to DC 3.3V (fifth wiring layer L5) via the Via.

The reset circuit on the sixth wiring layer L6 side is constructed as shown in FIG. A system reset signal can be input to the logic integrated circuit IC7 via the liquid crystal control first connector CN31, and a reset signal can be input from the WDT built-in reset integrated circuit (reset IC) IC10. When a signal is input, a reset signal is transmitted to the composite chip 104 and the control ROM 105 via the resistor built-in transistor T1 for noise countermeasures. For example, a data output terminal ASIBLDTB for LED of the composite chip 104 is connected to the WDT built-in reset integrated circuit (reset IC) IC10 for resetting the WDT.

Here, the test point TP23 is for checking when the reset integrated circuit IC10 operates, and as shown in FIG. Therefore, the identification information "TP23" indicating the test point TP23 is displayed by silk printing on the sixth wiring layer L6 side where the wiring path cp421 is provided, that is, on the back surface 98b side. is normal. On the other hand, the check operation by the test point TP23 must be performed with the board assembled (see FIGS. 8 and 9) or with the board assembled (installed) in the game machine main body. The rear surface 98b of 98 cannot be touched by a tester because it is shaded by the presentation interface board 96 and the liquid crystal interface board 97 facing each other. Therefore, in this embodiment, as shown in FIG. 43, the display of "TP23", which is the identification information indicating the test point TP23, is displayed on the wiring path cp421 side where the test point TP23 is arranged, that is, not on the back surface 98b side but on the front surface. It is arranged on the 98a side. Since the test point TP23 is configured by the via v203 penetrating the substrate body 190, it is possible to apply the tester from the surface 98a side of the substrate body 190 as well.

The test point TP17 is provided in the via v204 that connects the wiring path cp418 on the first wiring layer L1 side and the wiring path cp419 on the sixth wiring layer L6 side. The display of "TP17" is also arranged on the surface 98a side like the test point TP23.

The same applies to the other test points TP28 and TP33 described above. That is, the test point TP28 is provided on the wiring path cp3 of the third wiring layer L3, but the display of "TP28", which is the identification information indicating the test point TP28, is arranged on the surface 98a side. Also, the test point TP33 is provided on the wiring path cp505 of the sixth wiring layer L6, but the display of "TP33", which is the identification information indicating this test point TP33, is arranged on the surface 98a side.

Next, wiring paths P46 and P47 connected to the 8/16-bit mode selection terminal BYTE#, writable input terminal WE#, and write inhibit/program input terminal WP#/ACC of the control ROM 105 will be described. These wiring paths P46 and P47 are not connected to the composite chip 104. FIG.

In the wiring path P46 (FIG. 40), as shown in FIG. 27, the terminal connection portion BYTE# provided in the control ROM arrangement region 192 of the first wiring layer L1 is connected to the via v48 by the wiring path cp531. The via v48 is arranged in the vicinity of the terminal connection portion BYTE# on the outside (-X side) of the control ROM arrangement area 192, and as shown in FIG. It is connected. Thus, in this embodiment, the 16-bit communication mode is selected by connecting the 8/16-bit mode selection terminal BYTE# of the control ROM 105 to the power supply (H level).

In the wiring path P47 (FIG. 40), as shown in FIG. 27, the terminal connection portion WE# (first predetermined terminal) provided in the control ROM arrangement region 192 of the first wiring layer L1 is connected to the via v111 by the wiring path cp541. is connected with This via v111 (first predetermined inter-layer conductive portion) is arranged near the terminal connection portion WE# on the outside (+X side) of the control ROM arrangement area 192, and as shown in FIG. is connected to DC 3.3V through As described above, in this embodiment, the writable input terminal WE# of the control ROM 105 is connected to the power supply (H level), so that when it is at H level (when not reading), it is in the output disabled mode, and when it is at L level (when it is reading). ), the mode can be switched according to the value (H/L) of the output enable input terminal OE#. Output enable input terminal OE# is connected to read strobe output terminal HRD of composite chip 104 as described above.

In the wiring path P47, as shown in FIG. 27, the terminal connection portion WP#/ACC (second predetermined terminal) provided in the control ROM arrangement area 192 of the first wiring layer L1 is connected to the via v112 by the wiring path cp542. It is connected. The via v112 is arranged near the terminal connection portion WP#/ACC outside the control ROM arrangement area 192 (on the +X side). As shown in FIG. 25, the via v112 (second predetermined inter-layer conductive portion) is connected to the via v111 through a resistor R43 by a wiring path cp543 provided in the sixth wiring layer L6. This via v111 is connected to DC 3.3V through the fifth wiring layer L5 as described above. As described above, in the present embodiment, the write inhibit/program input terminal WP#/ACC of the control ROM (specific electronic component) 105 is connected to the power supply (H level), so that it is set to be writable and program executable. ing. Also, by connecting to the power supply through a resistor R43, an input exceeding the H level is eliminated and the H level is stably set.

For example, depending on the type of control ROM, when there is an input exceeding H level, if a mode setting different from write prohibition/permission and program execution prohibition/permission is performed, the Even if the input exceeds the H level due to noise, etc., the control ROM is set to a mode different from prohibition/permission of writing and prohibition/permission of program execution by configuring the control ROM so that it is stably at the H level. It is possible to prevent this from happening.

To summarize the configuration of the wiring paths P1 to P47 described above, among the wiring paths P2 to P45 connecting the composite chip 104 and the control ROM 105, the wiring paths P2 to P43 and P45 (specific wiring paths) are shown in FIG. , as shown in FIGS. 35 to 40, vias v60 to v108 (specific inter-layer conductive portions; vias indicated in gray in FIGS. 35 to 40) arranged in the control ROM arrangement area (second arrangement area) 192 are Further, wiring paths P2 to P16, P19 to P23, P35 to P43, and P45 (first specific wiring paths) among them are connected to terminal connections on the control ROM 105 side. The parts A0 to A14, A17 to A21, Q8 to Q15, CE# and RESET# are connected from the inside of the control ROM arrangement area 192 (wiring lines indicated by thick lines in FIGS. 35 to 40). Thus, the wiring path connecting the composite chip 104 and the control ROM 105 is arranged so as to pass through the control ROM arrangement area 192 which has a relatively large space, and the terminals of the control ROM 105 are connected as much as possible. By connecting from the inside of the control ROM arrangement area 192, the wiring patterns on the substrate can be arranged more efficiently, and the limited space can be used more effectively.

Wiring connecting vias v60 to v108 (specific inter-layer conductive portions) arranged in the control ROM arrangement area (second arrangement area) 192 to terminal connection parts on the control ROM 105 side from outside the control ROM arrangement area 192 As shown in FIG. It is arranged so as to cross sides 192a and 192b on the outside of each terminal connection portion. By configuring in this way, the wiring length can be shortened compared to the case of wiring avoiding the control ROM arrangement area 192, so that the wiring efficiency can be improved and noise can be reduced. In addition, since the control ROM 105 is actually located in the range indicated by the control ROM arrangement area 192, the wiring pattern cannot be visually observed, and therefore unauthorized access to the wiring pattern can be prevented. It is possible.

Also, a wiring path, more specifically, a wiring path cp233, is connected in the first wiring layer L1 to the vias v60 to v108 (specific inter-layer conductive portions) arranged in the control ROM placement area (second placement area) 192. , cp243 and cp253 are also arranged so as to cross the long side 192a of the control ROM arrangement area 192 outside the respective terminal connection portions, as shown in FIG. By adopting such a configuration at a plurality of locations together with the configuration in the preceding paragraph, the effect described in the preceding paragraph becomes more effective.

A ROM socket 193 (FIG. 8) is fixed to the control ROM arrangement area 192, and the bottom wall (shielding wall corresponding to the specific inter-layer conduction part) 193a of the ROM socket 193 shields the control ROM arrangement area 192. Even when the control ROM 105 is removed from the ROM socket 193, the wiring pattern in the control ROM arrangement area 192 including the vias v60 to v108 (specific inter-layer conduction portions) cannot be visually recognized from the outside and cannot be accessed.

The vias v60 to v108 (specific inter-layer conductive portions) in the control ROM arrangement area 192 penetrate from the front surface (first surface) 98a to the rear surface (second surface) 98b of the substrate body 190, thereby enhancing the heat radiation effect. The vias v60 to v108 (specific inter-layer conductive portions) in the control ROM arrangement area 192 are connected to predetermined electronic components such as ICs, resistors, capacitors, connectors, etc. on the back surface 98b side, that is, on the sixth wiring layer L6 side. .

As for the wiring paths P2 to P45 connecting the composite chip 104 and the control ROM 105, the first wiring portion connecting the composite chip 104 and a predetermined via (predetermined inter-layer conductive portion) is connected to the predetermined via and the control ROM 105. and a third wiring portion for connecting predetermined vias to other electronic components such as the liquid crystal control first connector CN31. The second wiring portion is formed in a first predetermined wiring layer such as the first wiring layer L1, and the third wiring portion is formed in a second predetermined wiring layer L3 and sixth wiring layer L6 which are different from the first predetermined wiring layer. They are arranged in wiring layers, respectively.

Among the wiring paths P2 to P45, for the wiring paths P2 to P42 for transmitting address/data information, predetermined vias (predetermined inter-layer conductive portions) serving as branch points are located in the control ROM layout area (second layout area). ) 192 (vias indicated in gray in FIGS. 35 to 40), the second wiring portion is on the first wiring layer L1, and at least a part of the first wiring portion are provided in the fourth wiring layer L4 (an example of a predetermined wiring layer different from the first wiring layer), and the third wiring portion is provided in the first wiring layer L1 (first predetermined wiring layer). This makes it possible to improve the preventiveness against fraudulent acts such as unauthorized modification of wiring patterns and vias for transmitting address/data information. By drawing wiring patterns in the control ROM arrangement area 192, wiring space can be secured in other areas. In addition, particularly at branch points, wiring patterns tend to be densely packed over multiple layers of the substrate, so a sufficient wiring space is required at the branch point. It is effective to place the branch point in the control ROM placement area 192 with the .

In addition, among the vias v60 to v107 (specific inter-layer conductive portions) in the control ROM arrangement area 192, the vias v61 to v85 and v103 forming part of the wiring paths P2 to P26 (address wiring) for transmitting address information. ∼ v107 (first specific interlayer conduction portion) and vias v87 to v102 (second specific interlayer conduction portion) forming part of wiring paths P27 to P42 (data wiring) for transmitting data information are controlled. They are arranged in the Y direction (first direction), which is the arrangement direction of the terminals in the ROM 105 .

Address output terminals HAD1 to HAD25 and data input/output terminals HDT0 to HDT15 (first terminal) on the composite chip 104 side, and corresponding address input terminals A0 to A24 and data input/output terminals Q0 to Q15 on the control ROM 105 side. The wiring paths P2 to P42 connecting them have vias v60 to v85 and v87 to v107 (specific inter-layer conductive portions) in the control ROM arrangement area 192, The arrangement of vias v60 to v85 and v87 to v107 (specific inter-layer conduction portions) in the control ROM arrangement area 192 is approximated to the arrangement of corresponding terminals (specific second terminals) on the control ROM 105 side. As a result, it is possible to arrange the wiring patterns that connect the specific interlayer conductive portions and the terminals of the control ROM, and for example, there is no need to arrange the patterns so that the positional relationship between a plurality of wiring patterns changes (twists). Therefore, the connection method is easier, and the space in the control ROM arrangement area 192 can be used more effectively. In this way, when the terminal arrangement of the composite chip 104 and the terminal arrangement of the control ROM 105 are different, a wiring pattern with a relatively short wiring distance from the specific inter-layer conductive portion in the arrangement area of the control ROM 105 to the terminals of the control ROM 105 can be used. Rather than devising the routing of the specific interlayer conductive portion, by devising the routing of a wiring pattern having a relatively long wiring distance from the composite chip 104 to the specific interlayer conductive portion, the arrangement of the specific interlayer conductive portion is approximated to the terminal arrangement of the control ROM 105. is more effective in terms of wiring efficiency.

Specifically, as shown in FIG. 27, for example, address input terminals A0 to A6 and corresponding vias v85 to v79, address input terminals A17 to A20 and corresponding vias v68 to v64, and data input/output terminals Q12 to Q15. and vias v90 to v87 corresponding thereto are arranged in substantially the same order in the Y direction. , Data input/output terminals Q0 to Q3 and corresponding vias v102 to v99, data input/output terminals Q8 to Q11 and corresponding vias v94 to v91, data input/output terminals Q4 to Q7 and corresponding vias v98 to v95 are arranged in substantially reversed order in the Y direction. In this way, rather than considering only the terminal arrangement of the control ROM 105 and devising the arrangement of the specific interlayer conductive portions, the terminal arrangement on the side of the composite chip 104 and the terminal arrangement on the liquid crystal control first connector CN31 side, which are also connected in the same manner, are not devised. Considering the above, the specific inter-layer conductive portions may be arranged. Although this partly complicates the connection relationship with the control ROM 105, the connection between the composite chip 104 and the liquid crystal control first connector CN31 side located farther than the terminals of the control ROM 105 is based on the specified inter-layer conduction portion. Since the connection relationship with the terminals is simplified, it is possible to improve the wiring efficiency of the entire board. That is, in the control ROM arrangement area 192, the wiring efficiency of the entire substrate can be improved by devising the arrangement of the specific inter-layer conductive portions as necessary. Also, the wiring efficiency of the entire substrate can be improved not only within the control ROM placement area 192, but also by devising the arrangement of vias serving as branch points as described above.

Address output terminals HAD1 to HAD25 and data input/output terminals HDT0 to HDT15 (first terminals) on the composite chip 104 side correspond to address input terminals A0 to A24 and data input/output terminals Q0 to Q15 on the control ROM 105 side. (second terminal), but also the terminals had1 to had25 and hdt0 to hdt15 (third terminal) of the liquid crystal control first connector CN31 are arranged differently. ) are made to match (approximately) the arrangement of the terminals had1 to had25 and hdt0 to hdt15 (third terminals) of the liquid crystal control first connector CN31. That is, as shown in FIGS. 28, 29 and 33, the vias v61 to v85 and v87 to v102 (specific inter-layer conductive portions) are arranged in the Y direction so that the corresponding terminals had1 to Since it matches the arrangement of had25 and hdt0 to hdt15 in the X direction, the wiring path group (third wiring path group) connecting them can be arranged in parallel without twisting. As a result, a wiring path group ( The second wiring path group) has a complicated wiring pattern including twists, but this can be easily realized by arranging it in the control ROM arrangement area 192 which has a relatively large space.

Among wiring paths P2 to P42 for transmitting address/data information, wiring paths P2 to P13 and P19 to P42 are vias v61 to v68, v74 to v85, and v87 to v102 ( The wiring paths P14 to P18 are branched to the control ROM 105 side and the liquid crystal control first connector CN31 side at the specific inter-layer conduction portion). Vias v103 to v107 are separately provided in the control ROM arrangement area 192 on the wiring path connecting the vias v69 to v73 and the liquid crystal control first connector CN31 without branching, and the vias v103 to v107 branch to the control ROM 105 side. ing. With this configuration, the wiring to the liquid crystal control first connector CN31 is arranged in parallel without being twisted in harmony with other wiring paths, and the wiring to the control ROM 105 is also prevented from interfering with other wiring paths. It is possible to efficiently arrange while avoiding.

Further, specific one end terminals A0 to A7, A17, A18, A20, A21, Q0 to Q3, Q8 to Q11 included in one end terminals arranged on one end side of the control ROM (second electronic component) 105 and The corresponding first specific terminals HAD0 to HAD7, HAD17, HAD18, HAD20, HAD21, HDT0 to HDT3, HDT8 to HDT11 on the side of the corresponding composite chip (first electronic component) 104 are connected to vias v65 to v68, v78 to v85, v91 to v94. , v99 to v102 (first interlayer conductive portions), a plurality of one end side wiring paths P2 to P9, P19, P20, P22, P23, P27 to P30, P35 to P38, a control ROM (second electronic Specific other-end terminals A8-A16, A19, A22-A24, Q4-Q7, Q12-Q15 included in the other-end terminals arranged on the other-end side of component) 105 and their corresponding composite chips (first The second specific terminals HAD8 to HAD16, HAD19, HAD22 to HAD24, HDT4 to HDT7, HDT12 to HDT15 on the electronic component) 104 side are connected to vias v61 to v63, v66, v74 to v77, v87 to v90, v95 to v98 (second a plurality of other end side wiring paths P10 to P18, P21, P24 to P26, P31 to P34, P39 to P42, which are connected to each other via a first interlayer conduction portion and a second interlayer conduction portion; are arranged close to each other so as to have different arrangements from those of the first specific terminal and second specific terminal and correspond to the specific one-end terminal and the specific other-end terminal, respectively.

In addition, internal connection wiring portions connected from the inside of the control ROM arrangement area 192 and external connection wiring portions connected from the outside are alternately arranged with respect to the plurality of ROM terminal connection portions arranged in a row. That is, as shown in FIG. 27, for the terminal connection portions Q0, Q8, Q1, Q9, Q2, Q10, Q3, and Q11 of the control ROM arrangement area 192, the external connection wiring portions cp303, cp313, cp323, cp333 and the internal wiring portions are connected. The connection wiring portions cp383, cp393, cp403, and cp413 are alternately connected. Moreover, the vias v102 to v99 on the other end side of the external connection wiring portions cp303, cp313, cp323, and cp333 are arranged close to each other, and the vias v94 to v91 on the other end side of the internal connection wiring portions cp383, cp393, cp403, and cp413. are also arranged close to each other. Similarly, the terminal connection portions Q15/A-1, Q7, Q14, Q6, Q13, Q5, Q12, and Q4 of the control ROM arrangement area 192 are connected to the internal connection wiring portions cp453, cp443, cp433, and cp423. The wiring portions cp373, cp363, cp353 and cp343 are alternately connected. Moreover, the vias v87 to v90 on the other end side of the internal connection wiring portions cp453, cp443, cp433, and cp423 are arranged close to each other, and the vias v95 to v98 on the other end side of the external connection wiring portions cp373, cp363, cp353, and cp343. are also arranged close to each other. In this way, by arranging and grouping the internal connection wiring section and the external connection wiring section in close proximity instead of the terminal arrangement of the control ROM 105, the routing of the wiring pattern can be simplified and the wiring efficiency can be improved. .

The first wiring paths P2 to P42 for transmitting address information or data information and the second wiring path P43 for transmitting chip select information are in different wiring layers. The layer L4 and the second wiring path P43 are connected to the vias v61 to v85, v87 to v101 and v60 (specific inter-layer conductive portions) in the control ROM arrangement area 192 from the composite chip 104 side in the sixth wiring layer L6. In this way, by wiring the chip select signal, which is important in data transmission, using a wiring layer different from the wiring pattern for transmitting address information or data information, transmission of the wiring pattern for transmitting address information or data information can be achieved. It is possible to make it difficult for noise to get on the chip select signal, and it is possible to have a configuration that is resistant to noise. Further, by making the pattern of the wiring path for the chip select signal different from that of other wiring paths, it becomes relatively easy to specify the wiring of the chip select signal, and it is possible to check whether the wiring pattern is short-circuited. It is possible to relatively easily perform checks and energization checks.

Further, in the wiring path P45 constituting the reset circuit, the wiring paths cp418 to cp421 (reset first wiring paths) connecting the reset integrated circuit (reset IC) IC10 and the via v174 (predetermined interlayer conduction portion), and the via v174 Wiring paths cp413 to cp415 (reset second wiring path) connecting (predetermined interlayer conductive portion) and reset terminal HRESET of composite chip 104, via v174 (predetermined interlayer conductive portion) and reset terminal RESET# of control ROM 105 are connected. Wiring paths cp416 and cp417 (third reset wiring path) are provided for connection, and a test point TP17 (first reset wiring path) penetrating through the liquid crystal control board 98 in the board thickness direction is provided on the wiring paths cp418 to cp421 (first reset wiring path). test point) and test point TP23 (second test point), identification information "TP17" and "TP23" indicating these test points TP17 and TP23, liquid crystal control board 98 to another effect interface board 96, liquid crystal interface It is shown on the surface (first surface) 98a opposite to the substrates 96 and 97 when assembled together with the substrate 97 and the like. The reset integrated circuit (reset IC) IC10 is arranged on the rear surface (second surface) 98b side. As a result, when the board is assembled (see FIGS. 8 and 9) or when the board is assembled (installed) in the game machine main body, the part of the wiring path where the test points TP17 and TP23 are arranged cannot be visually recognized. In spite of this, it is possible to easily perform checking work using the test points TP17 and TP23 based on the identification information displayed on the visible surface 98a side.

Wiring paths cp418 to cp421 (reset first wiring path) are arranged on the front surface (first surface) 98a side and wiring path cp418 (first wiring path) on the back surface (second surface) 98b side. Wiring paths cp420 and cp421 (second wiring paths) and a via v204 (reset first interlayer conduction portion) connecting them are provided, and a test point TP17 (first test point) is arranged in the via v204 to perform a test. A point TP23 (second test point) is placed on the wiring path cp421 (second wiring path).

Further, the control ROM (specific electronic component) 105 operates in an operation mode according to the voltage level of the write inhibit/program input terminal WP#/ACC (second predetermined terminal), and the writable input terminal WE# (first A predetermined terminal) is connected to the power supply wiring path of the fifth wiring layer L5 via a via v111 (first predetermined interlayer conductive portion), and a write inhibit/program input terminal WP#/ACC (second predetermined terminal) is connected to a resistor It is connected to via v111 (first predetermined inter-layer conductive portion) through R43. A control ROM (specific electronic component) 105 is arranged on the surface (first surface) 98a of the liquid crystal control board 98, and a resistor R43 is arranged on the rear surface (second surface) 98b. A write inhibit/program input terminal WP#/ACC (second predetermined terminal) and a resistor R43 are connected via the . Thus, the via for connecting WP#/ACC (second predetermined terminal) to the power supply wiring path via resistor R43 is commonly used as the via for connecting WE# (first predetermined terminal) to the power supply wiring path. , the number of vias can be reduced compared to connecting via individual vias.

A plurality of terminals are arranged in a matrix on the bottom side of the composite chip 104. Out of the plurality of terminals, the outer terminals arranged near the outer circumference of the composite chip arrangement area (first arrangement area) 191, For example, the terminals HDT0, HDT1, HDT4, HDT5, etc. arranged in the second row on the outermost peripheral side and inside thereof are connected to the control ROM 105 by first wiring paths P27, P28, P31, P32, etc., and are arranged inside the outer terminals. Arranged inner terminals such as terminals HDT2, HDT3, HDT6, etc. are connected to the control ROM 105 by second wiring paths P29, P30, P33, etc., and first wiring paths P27, P28, P31, P32, etc. are connected to the composite chip layout area. Vias v32, v31, v37, v46, etc. (first interlayer conductive portions) arranged outside 191 and external terminals HDT0, HDT1, HDT4, HDT5, etc. are connected in a first wiring layer L1, and a second wiring path P29 is connected. , P30, P33, etc. connect the vias v24, v8, v17, etc. (second interlayer conductive portions) arranged inside the composite chip placement region 191 and the inner terminals HDT2, HDT3, HDT6, etc., in the first wiring layer L1. is doing. Also, the distances from the inner terminals HDT2, HDT3, HDT6, etc. to the vias v24, v8, v17, etc. (second interlayer conductive portions) are set to the distances from the outer terminals HDT0, HDT1, HDT4, HDT5, etc. It is shorter than the distance to (the first interlayer conductive portion).

Thus, in the composite chip 104 having a plurality of terminals arranged in a matrix, the outer terminals arranged in the vicinity of the outer periphery of the arrangement area of the composite chip 104 are connected to the vias arranged outside the composite chip 104. Therefore, a wiring space is generated near the outer periphery of the composite chip 104, and the wiring pattern of the inner terminal of the composite chip 104 can be easily routed to the outside of the composite chip, so that the wiring efficiency can be improved. As for the wiring space described above, since a wiring space in the vicinity of the outer periphery of the composite chip is generated in a plurality of wiring layers of the substrate, even if any wiring layer among the plurality of wiring layers is used, the wiring space may extend to the outside of the composite chip. It goes without saying that it becomes easy to wire the wiring pattern.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the embodiment, the wiring paths P2 to P42 for transmitting address information/data information between the composite chip 104 and the control ROM 105 are connected to specific inter-layer conduction lines arranged in the control ROM arrangement area (second arrangement area) 192. However, at least some of the wiring paths P2 to P42 may not have the specific inter-layer conductive portion.

In the embodiment, the vias v61 to v85 and v87 to v102 (specific inter-layer conduction portions) in the wiring paths P2 to P42 are arranged in the Y direction so that the corresponding terminals had1 to had25 and hdt0 to the terminals of the liquid crystal control first connector CN31 The Y-direction arrangement of the vias v61 to v85 and v87 to v102 (specific inter-layer conductive portions) may be made to match (or approximate) the terminal arrangement of the control ROM105.

In the embodiment, regardless of whether the test points to be checked exist on the front or back of the board, the test points that need to be checked while the board is assembled are placed on the outer surface of the board when the board is assembled. Although configured to display test point identification information, such test point identification information may be displayed on both sides of the board.

In the embodiment, among the terminals of the composite chip 104, the terminals (outer terminals) arranged in the second row on the outermost side and the inner side of the composite chip arrangement area (first arrangement area) 191 are formed in the first wiring layer. In L1, it is connected to the inter-layer conductive portion arranged outside the composite chip placement region 191, and the terminals (inner terminals) inside thereof are arranged inside the composite chip placement region 191 in the first wiring layer L1. Although it is configured to be connected to the interlayer conductive portion, only the terminals on the outermost side in the composite chip placement area 191 may be used as outer terminals, or the terminals in the third row from the outermost side may be used as outer terminals.

Further, in the embodiment, only the wiring related to the terminal on the one edge side of the composite chip 104 was specifically illustrated, but the configuration is not limited to this, and the other edge side of the composite chip 104 has the same configuration or embodiment. may be configured to have the contents described in . Thus, by adopting the configuration described in this embodiment also on each edge side of the composite chip 104, it is possible to further increase the wiring efficiency. For example, a configuration as shown in FIG. 12 is given as an example.

In the embodiment, an example in which the first to sixth wiring layers L1 to L6 are provided on the liquid crystal control board 98 is shown, but the number of wiring layers may be less or more than this. When the number of wiring layers is reduced, the solid wiring layer for ground connection and the solid wiring layer for power supply connection may be omitted.

The connection between the terminals of the composite chip 104 and the vias in the composite chip placement area 191 may be designed such that the distances between the terminals and the vias are substantially the same. As a result, the distances between the plurality of terminals and the vias are substantially equal, so that noise is less likely to enter and the vias can be arranged in a more appropriate state.

In addition, with regard to the directions in which wirings are drawn out from the terminals of the composite chip 104 toward the vias, it is desirable that vertically and horizontally adjacent terminals have the same wiring drawing direction (via arrangement direction). Further, when these terminals are treated as one group, it is desirable that the direction of drawing out the wiring (the direction of arranging the vias) for another group of terminals is different from that described above. By setting the wiring lead-out direction (via arrangement direction) for each terminal group in this way, it becomes easy to check and recognize the information of each terminal by the wiring pattern, so that inspection and checking after completion is facilitated. Become. Further, by grouping terminals for transmitting address information into one group and terminals for transmitting data information into one group, the above-described effects can be exhibited more effectively. Further, with respect to terminals for individual signals such as chip select signals, confirmation and recognition may be facilitated by providing vias in a wiring lead-out direction different from that of the above-described one group. In addition, by providing vias in a common wiring lead-out direction for terminals for chip select signals as well, important terminals and signal lines for chip select signals are made difficult to identify, and a configuration that is strong against fraudulent acts may be provided.

As shown in FIG. 26, a wiring pattern may be provided that reaches the control ROM placement area 192 or its vicinity without vias, such as the wiring path cp221 connected to the HAD22 terminal of the composite chip 104 . By wiring in this manner, the number of vias around the composite chip 104 can be reduced, so that the corresponding space can be used as a location for installing other wirings and vias. Further, although the wiring path cp221 is connected to the via v53, it may be configured to be connected to the terminal of the control ROM 105 without via the via.

As shown in FIG. 27, wiring patterns of special terminals such as OE#, WE#, BYTE#, WP#ACC, CE#, and RESET# among the terminals of the control ROM 105 transmit address information and data information. The connection distance from the via may be set shorter than the wiring pattern. As a result, it is possible to easily distinguish the types of wiring patterns during board assembly, inspection, and the like. Conversely, by setting a long connection distance, it may be configured such that the types of wiring patterns can be easily distinguished. Also, since it is a terminal connection pattern for controlling the operation of the control ROM 105, it is desirable to use a relatively short wiring pattern in consideration of noise and the like.

As shown in FIG. 27, in the control ROM placement area 192, by displacing the first via array group (v61 to v85, etc.) and the second via array group (v87 to v102, etc.) in the X-axis direction, It is possible to make it easier to pull out wiring patterns in the Y-axis direction from each array group. If the first via array group and the second via array group are arranged in the Y-axis direction without being shifted in the X-axis direction, they will not fit in the control ROM arrangement area 192 and protrude. By arranging them so as to overlap in the Y-axis direction, the first via array group and the second via array group can be accommodated in the control ROM arrangement area 192, and the wiring space in the control ROM arrangement area 192 can be further reduced. Effective utilization is possible.

Even if the first via array group and the second via array group are shifted in the Y-axis direction and arranged so as to overlap in the X-axis direction, if they fit within the control ROM placement area 192, they are shifted in the Y-axis direction. may be arranged so as to overlap in the X-axis direction. In this case, it becomes difficult to pull out the wiring patterns in the Y-axis direction from each array group, but at least in the X-axis direction, there is no restriction. Also, for example, when the first via array group or the second via array group is the branch point, after considering the arrangement of the connection terminals at the branch destinations, they are arranged so as to be shifted in the Y-axis direction and overlapped in the X-axis direction. It may be so arranged if it results in a more efficient arrangement. Similarly, they may be arranged so as to be shifted in the X-axis direction and overlapped in the Y-axis direction. Depending on the shape of the control ROM layout area 192 and how the wiring pattern is routed, there may be a case where a more suitable layout relationship is obtained.

As shown in FIG. 20, by determining the layout relationship between the composite chip 104 and the control ROM 105 according to the position of the terminal arrangement of the composite chip 104 connected to the terminals of the control ROM 105, the physical connection distance can be reduced. It may be configured to be closer. This is not limited to the control ROM 105 in particular, but is based on the position of each terminal of the composite chip 104. By determining the arrangement position, the arrangement direction, the distance, etc. of the electronic parts connected to these terminals, the wiring efficiency is increased. be able to. Of course, only specific electronic components, such as the control ROM 105, may be placed in the above-described arrangement relationship, thereby partially improving the wiring efficiency. By doing so, the wiring efficiency of the entire substrate can be improved.

In addition, regarding wiring that needs to connect composite chip 104 and a plurality of electronic components, such as a wiring pattern for transmitting address information and data information, a first electronic component (eg, control wiring) that is close to composite chip 104 (ROM 105) and a second electronic component farther away (e.g. liquid crystal control first connector CN31). may be increased. Further, it goes without saying that wiring efficiency can be further improved by providing both the first electronic component and the farther second electronic component on the side where the connection terminals of the composite chip are located. Moreover, wiring efficiency may be improved by providing the far second electronic component of the first electronic component and the second electronic component on the side where the connection terminal of the composite chip 104 is located. In this case, the first electronic component is placed on a side different from the side on which the connection terminals of the composite chip are located. Considering the wiring efficiency of the pattern, it may be more effective. Also, the first electronic component is not limited to the control ROM, and may be a connector, (terminating) resistor, or the like. Similarly, the second electronic component is not limited to a connector, and may be a control ROM or (terminating) resistor.

As shown in FIG. 19, the terminals of the control ROM 105 include terminals (NC terminals, etc.) that are not connected to the terminals of the composite chip 104. In FIG. A via for connecting a wiring pattern connected to a terminal other than the NC terminal is provided in a location (region) shifted in the X-axis direction from the location where the NC terminal of the control ROM 105 is located in the ROM arrangement region 192 (see FIG. 27). corresponds to v80 to v85) may be provided. The reason for this configuration is that there is no need to consider the wiring patterns and via layouts connected to the NC terminals, etc., so there is a tendency for wiring spaces to occur relatively easily around them, so that area is utilized. This is because vias can be placed by In addition, since there is enough space around the NC terminals and the like, there is an advantage that the wiring pattern can be easily pulled out from the via in the Y-axis direction or the X-axis direction. Moreover, the above effects can be obtained by applying the same configuration not only to the NC terminal but also to the VCC terminal and the GND terminal.

As shown in FIG. 31, vias (eg v49 to v54) for connecting wiring patterns for connecting the terminals of the composite chip 104 and the terminals of the control ROM 105 are provided near or around the outside of the control ROM arrangement area 192. A wiring pattern is routed in the control ROM placement area 192 through the via, so that the via can be visually recognized from the outside of the substrate without being shielded by the control ROM 105 or the like. Compared to a wiring pattern in which vias are not provided in the vicinity of the outside of the area 192 or around it, confirmation and inspection of the wiring pattern connecting the terminals of the composite chip 104 and the terminals of the control ROM 105 are facilitated. Wiring efficiency can be improved by arranging vias near the outside.

As shown in FIGS. 27 and 28, the vias v69 to v73 are arranged in the control ROM placement area 192 together with other vias. The wiring pattern is drawn out to the control ROM arrangement area 192 via the . In this way, the wiring pattern that connects the vias (v69 to v73) arranged together with the other specific interlayer conductive portions and the terminals of the control ROM 105 is arranged in the control ROM placement area 192 via another via (v103 to v107). can be arranged to increase the wiring efficiency. Even in this case, since the vias v69 to v73 are arranged in the same manner as the other vias, it is possible to relatively easily perform inspections such as confirmation of the connection relationship and checking of energization.

Although the VDP+CPU composite chip 104 is exemplified in the embodiment, a CPU chip without the VDP function may be used. Also, the control ROM is not limited to a storage medium for storing control programs for the CPU, and may be a ROM for storing audio data and image data.

Vias located in the composite chip placement area 191 and the control ROM placement area 192 may be used as test points for continuity check. In this case, it is desirable to display test points (identification information display) by silk printing near or around the vias located in the composite chip placement area 191 and the control ROM placement area 192 . As a result, continuity check of the composite chip 104 and the control ROM 105 can be easily performed, and the composite chip placement area 191 and the control ROM placement area 192 can be used to place silk-printed notations of test points.

As shown in FIG. 42, by connecting the SRESET signal and the WTDOG signal to a common logic integrated circuit IC7, it is possible to appropriately perform reset processing when a reset signal is input due to any reset factor. It's becoming Further, the output information (reset signal) from the logic integrated circuit IC7 is output not only to the composite chip 104 and/or the control ROM 105, but also to the decoders IC13 and IC14 shown in FIG. output from the IO-RST), it is possible to execute the reset process for the liquid crystal display unit 76. FIG. As a result, reset operations can be realized synchronously or at approximately the same timing by hardware such as different electronic components.

Also, in order to reset an external ROM such as a CGROM or a voice ROM, a separate reset signal may be output to the composite chip 104 (output from the DDR-RST in FIG. 42). In this manner, even when the output target is the same composite chip 104, a different reset signal may be output for each reset target. Accordingly, a circuit configuration can be provided in which reset processing can be performed according to the reset target and reset purpose. Further, as shown in FIG. 42, the IO-RST signal and the DDR-RST signal are also signals output from the logic integrated circuit IC7. This is a signal that is triggered by being input to the integrated circuit IC7.

In addition, although the common logic integrated circuit IC7 is used in the embodiment, the present invention is not limited to this, and a plurality of logic integrated circuits may be provided. In this case, different logic integrated circuits may be used for the CPU-RST signal, the IO-RST signal, and the DDR-RST signal, or different logic integrated circuits may be used for the CPU-RST signal, the IO-RST signal, and the DDR-RST signal. It may be configured to use a logic integrated circuit. When a plurality of logic integrated circuits are used in this way, although it is costly, it is possible to prevent a reset signal from being output to all hardware due to a problem. Even in this case, different logic integrated circuits are configured to receive a common SRESET signal and/or WTDOG signal.

As shown in FIG. 19, the terminals of the control ROM 105 include terminals (NC, etc.) that are not connected to the terminals of the composite chip 104. In FIG. A location (region) shifted in the X-axis direction with respect to the location where the NC terminal of the control ROM is located in the region 192, and a location (region) shifted in the X-axis direction with respect to the location where terminals other than the NC terminal are located. , the number of vias arranged in the control ROM arrangement area 192 may be varied. In this way, the space in the control ROM arrangement area 192 may be effectively utilized by varying the number of vias arranged for each corresponding location (area). In addition, of course, the wiring pattern pulled out from the via is connected to the terminals other than the NC terminal, so there is an advantage that the connection distance is shortened when arranging them close to each other. When a wiring pattern drawn from a via drawn out from a position (region) shifted in the X-axis direction with respect to the position where the X-axis is to be connected is connected, the connection distance becomes long, but the wiring space has a relatively large margin. , there is an advantage that routing becomes easy.

Among the vias in the control ROM arrangement area 192, vias that are not directly connected to the terminals of the control ROM (for example, a plurality of vias located between v68 and v74 in FIG. 27) are as shown in FIG. Alternatively, it may be provided at a location (region) shifted in the X-axis direction with respect to locations where terminals other than the NC terminals are located. This is because the wiring pattern is not drawn out from these vias on the first wiring layer L1, so there is little possibility that the wiring space in the control ROM arrangement area 192 will be obstructed. Conversely, it may be provided in a location (area) shifted in the X-axis direction with respect to the location where the NC terminal of the control ROM 105 is located in the control ROM layout area 192 . In this case, a wiring space can be provided by a location (region) shifted in the X-axis direction with respect to locations where terminals other than the NC terminals are located. In any case, in the embodiment, the via arrangement as shown in FIG. 27 is constructed in consideration of the above-mentioned merits and with an awareness of the connection relationship with electronic parts (eg, connectors) other than the control ROM. ing.

In the example of FIG. 27, vias for conducting wiring patterns for transmitting address information are arranged in a predetermined array, and vias for conducting wiring patterns for transmitting data information are arranged in a predetermined array. Although the via arrays are arranged in groups, the vias are not limited to this, and the vias that conduct the wiring patterns for transmitting the address information and the vias that conduct the wiring patterns for transmitting the data information are arranged in a predetermined arrangement. They may be arranged so as to form one via group. In this case, the vias for conducting the wiring patterns that transmit different information can be densely arranged, so that the installation range of the vias can be made relatively small. In addition, like vias v87 to v90 shown in FIG. 27, some vias may be arranged as small groups in the array of vias that conduct wiring patterns for transmitting data information. A via for conducting a wiring pattern for transmitting address information may also have a similar configuration.

In the example of FIG. 27, vias for conducting wiring patterns for transmitting address information and vias for conducting wiring patterns for transmitting data information are arranged in a predetermined arrangement in the control ROM arrangement area 192 . , the vias may be arranged in a predetermined arrangement outside the control ROM arrangement area 192 . In this case, the control ROM arrangement area 192 cannot be utilized, but since the wiring pattern is connected from the outside of the control ROM arrangement area 192 to the terminals of the control ROM 105, check the connection status for each terminal of the control ROM. It has the advantage of being easier. However, since the required wiring space is relatively large compared to the case where the control ROM placement area 192 is used, it is desirable to employ such a configuration when the space is relatively free.

As shown in FIG. 27, the wiring patterns of special terminals such as OE#, WE#, BYTE#, WP#/ACC among the terminals of the control ROM 105 are arranged from the outside of the control ROM arrangement area 192 to the terminals. , the connection status may be easily checked. Also, CE# and RESET# may be configured in the same manner. However, in the embodiment, CE#, which is a chip select input terminal for inputting a chip select signal, and RESET#, which is a reset terminal for inputting a reset signal, are likely to be subject to problems and failures. A wiring pattern is connected to each terminal from within the control ROM placement area 192 so that the pattern is not tampered with.

As shown in FIG. 26, with respect to the terminals of the composite chip 104 and the vias in the composite chip placement area 191, the composite chip terminals are arranged linearly in the Y-axis direction (and/or the X-axis direction). By arranging the vias in the arrangement region 191 in a straight line in the Y-axis direction (and/or the X-axis direction), it is possible to easily confirm the arrangement of each terminal and the arrangement of the vias, and at the same time, the space is reduced. Vias can be arranged in an aligned manner within the composite chip placement area 191, which has relatively little margin.

Also, as shown in FIG. 26, terminals of the composite chip 104 linearly aligned in the Y-axis direction (and/or X-axis direction) and vias linearly aligned in the Y-axis direction (and/or X-axis direction) are preferably arranged so as not to overlap each other in the Y-axis direction (and/or the X-axis direction). By configuring in this way, the vias can be arranged, for example, avoiding the terminals located adjacent to each other or in the vicinity, so that the wiring pattern from the vias can be easily arranged.

Further, as shown in FIG. 26, vias in the composite chip placement region 191 are connected to outer terminals (eg, HAD18, HAD14, HAD10, HAD6, HAD21, HDT12, HDT7, HDT4) arranged near the periphery of the composite chip placement region 191. , HDT0) and/or terminals arranged inside (eg, HAD17, HAD13, HAD9, HAD5, HAD22, HDT13, HDT8, HDT5, HDT1) overlap each other in the X-axis direction (and/or the Y-axis direction). It is desirable to arrange in a position where As a result, the vias can be arranged while avoiding the outer terminals and/or the terminals arranged inside thereof, so that the wiring pattern from the vias can be easily arranged. In other words, in the first wiring layer L1, if the vias are arranged to avoid the outer terminals and/or the terminals arranged inside thereof, when the wiring pattern is pulled out from the vias in a different wiring layer, the outer terminals and/or the inner side of the terminals can be easily connected. It is possible to draw out the wiring pattern linearly in the X-axis direction (and/or the Y-axis direction) without worrying about the terminals arranged in the direction.

Further, the outer terminals (eg, HAD18, HAD14, HAD10, HAD6, HAD21, HDT12, HDT7, HDT4, HDT0) arranged near the outer periphery of the composite chip arrangement area 191 shown in FIG. With respect to vias (eg V11 to V24) arranged to avoid terminals (eg HAD17, HAD13, HAD9, HAD5, HAD22, HDT13, HDT8, HDT5, HDT1), first specific vias (eg v18 to v24) and second specific vias (e.g., v11-v17) located inside the composite chip 104 relative to the first specific vias, avoiding the outer terminals and/or the terminals located inside them. As a result, they are arranged so as to overlap each other in the X-axis direction in the first wiring layer L1. In this case, for the second specific via arranged inside the composite chip 104 than the first specific via, for example, in a wiring layer different from the first wiring layer L1 as shown in FIG. The wiring pattern may be arranged so as to avoid one specific via. In this way, by using a plurality of wiring layers, the wires are arranged inside the composite chip placement region 191 so as to avoid the outer terminals arranged near the outer periphery of the composite chip placement region 191 and/or the terminals arranged inside thereof. A first specific via and a second specific via may be provided, and a wiring pattern drawn out from the second specific via may be provided so as to avoid the first specific via. As a result, the wiring pattern can be efficiently pulled out from inside the composite chip placement area 191 where there is relatively little wiring space to the outside of the composite chip placement area 191 . Further, here, specific terminals and specific vias are shown as examples based on FIGS. 26 and 31, but the configuration is not limited to this, and other terminals and vias may be configured in the same manner. For example, one edge side of the composite chip 104 is shown as an example in FIG. 26, but the other edge side may have the same configuration. In addition, when the first wiring layer L1 in the composite chip placement area 191 has a relatively large wiring space, the first specific via is arranged in the X-axis direction (and/or the Y-axis direction) in the first wiring layer L1. A second specific via may be configured to be placed to avoid.

As described above, the vias in the composite chip placement region 191 shown in FIG. 26 are arranged linearly in the Y-axis direction (and/or the X-axis direction). Even in different wiring layers, the vias in the composite chip placement area 191 are arranged linearly in the Y-axis direction (and/or the X-axis direction). Here, a first via (eg, v21), a second via (eg, v14) positioned inside the composite chip placement region 191 from the first via, and inside the composite chip placement region 191 from the second via The first via extends out of the composite chip placement region 191 by a wiring pattern drawn out linearly in the X-axis direction, and the second via extends to the first via The first wiring pattern drawn out linearly in the X-axis direction via the wiring pattern drawn out by the first distance in the direction avoiding the , and the first wiring pattern drawn out linearly in the direction in which the control ROM 105, which is the connection destination, is located The second wiring pattern advances outside the composite chip placement region 191, and the wiring pattern that the third via is pulled out by the first distance in a direction to avoid the first via and/or the second via (a wiring pattern that avoids the first via from the second via direction) and a wiring pattern drawn out linearly in the Y-axis direction (the wiring pattern length up to this point is the first distance in the direction avoiding the first via from the second via). The first wiring pattern is drawn out linearly in the X-axis direction and the second wiring pattern is drawn out linearly in the direction in which the control ROM 105, which is the connection destination, is located. The wiring pattern is configured to extend outside the composite chip placement area 191 . In this way, when the first via, the second via, and the third via are arranged toward the inside of the composite chip placement region 191 in this order, the outer vias are first placed in the composite chip placement region 191 . A wiring pattern may be provided to avoid this. As a result, the wiring space in the composite chip placement area 191 can be effectively utilized.

In the above example, the relationship between the first via, the second via, and the third via is shown by taking a specific via as an example, but the configuration is not limited to this, and the other vias shown in the figure can have the same configuration. desirable. In this way, by adopting the same configuration at a plurality of locations, it is possible to effectively utilize the wiring space in the composite chip placement area 191 more effectively than implementing at a single location. Also, in the above example, a wiring layer different from the first wiring layer L1 in the composite chip placement area 191 is used, but the present invention is not limited to this and may be implemented in the first wiring layer L1. may However, since a plurality of terminals of the composite chip 104 are arranged on the first wiring layer L1, it is assumed that the wiring space is relatively limited. is desirable.

In the example of FIG. 26, like the terminals of the composite chip 104 from HAD1 to HAD0 arranged linearly in the Y-axis direction, wiring patterns drawn out from the respective terminals are drawn out in different directions (for example, HAD1 and HAD0 are -XY direction, +XY direction for HAD8, HAD3, HAD15 and HAD20, and -X+Y direction for HAD11), vias connected to each terminal are arranged linearly in the Y-axis direction. In this way, the terminals of the composite chip 104 arranged in a straight line in the Y-axis direction (and/or the X-axis direction) and the vias connected by the respective wiring patterns are arranged in a straight line in the Y-axis direction (and/or the X-axis direction). Terminals of the composite chip 104 that are not arranged in a straight line in the Y-axis direction (and/or the X-axis direction) and vias connected by wiring patterns are arranged in the Y-axis direction. (and/or in the X-axis direction). Even with such a configuration, the terminal array and via array of the composite chip 104 can be arranged linearly in the Y-axis direction (and/or the X-axis direction). It is possible to achieve the same effect as

In the example of FIG. 26, from a plurality of terminals (eg, HDT6, HDT10, HDT15, HAD24) of the composite chip 104 arranged in a straight line in the Y-axis direction, wiring patterns are drawn out in substantially the same direction. Vias (eg, v17 to v14) are arranged linearly in the region 191 in the Y-axis direction. As shown in FIG. 31, the first wiring layer L1 is electrically connected to the fourth wiring layer L4 through these vias, and the wiring pattern is led out from the fourth wiring layer L4. In this way, wiring patterns may be drawn out in the same direction from each of the terminals of the composite chip 104 that have common conduction destinations from vias (here, the fourth wiring layer L4). Similarly, vias connected to each terminal may be arranged linearly in the Y-axis direction within the composite chip placement area 191 . In this case, as shown in FIG. 26, an address output terminal for outputting address information and a data input/output terminal for inputting/outputting data information may be configured as described above. The above-described configuration may be configured with only address output terminals for outputting information or only data input/output terminals for inputting/outputting data information. By configuring in this way, it becomes easy to check the arrangement of each terminal, the arrangement of vias, and the wiring pattern serving as a connection path. In addition, not only the terminals of the composite chip 104 that have the same conduction destination (here, the fourth wiring layer L4) from the via, but also the connection from the via to the connection destination (eg, the control ROM 105) through the wiring pattern. The terminals of the composite chip 104 having the same type may be configured as described above. In addition, the wiring route from the via to the connection destination (eg, control ROM 105) through the wiring pattern (which wiring layer is passed through, what wiring pattern is used for wiring, etc.) is substantially common. The terminals of the composite chip 104 may be configured as described above. By configuring in this way, it becomes easy to check the arrangement of each terminal, the arrangement of vias, and the wiring pattern serving as a connection path.

In the above description, the arrangement of vias v60 to v85 and v87 to v107 (specific inter-layer conduction portions) in the control ROM arrangement area 192 is approximated to the arrangement of the corresponding terminals (specific second terminals) on the control ROM 105 side. The word "approximation" is used in this example, but this "approximation" may mean that the arrangement of all the terminals and vias that are in the connection relationship are the same, or that the arrangement of all terminals and vias that are in the connection relationship Some terminals and vias may have the same arrangement. In addition, when there are a plurality of items in a connection relationship (for example, a control ROM terminal and a connector terminal for a predetermined via), the arrangement of one or both of the terminals may be the same. Also, when there are a plurality of connection destinations, there is no problem if they are the same electronic component, but if they are different electronic components, there is a high possibility that the arrangements of both terminals are different. In that case, it is practically impossible to have a via arrangement that completely matches the arrangement of both terminals. Therefore, in order to match the arrangement of both terminals as much as possible, the arrangement may be partially common. For example, a partial arrangement of the terminals of the first connection (partial arrangement of the terminals of the control ROM 105), a partial arrangement of the terminals of the second connection (partial arrangement of the terminals of the connector), and may correspond to a partial arrangement of the terminals of the first connection destination (arrangement of a part of the terminals of the control ROM), but the terminals of the second connection destination (partial arrangement of connector terminals) is not supported However, a second via array corresponding to a partial array of the terminals of the second connection destination (a partial array of the terminals of the connector) may be provided. It is also assumed that such an arrangement of vias has the aforementioned "approximation" relationship.

Regarding the assembly of boards, "assembly" may be a combination of a plurality of boards to complete one control board, or a state in which a harness is inserted into a connector for a single board so that it can conduct electricity. , and may be connected to another substrate via a harness. In addition, it is not limited to a plurality of substrates or a single substrate, and various electronic components required for operation may be attached to the substrate.

The contents of the above embodiments can be combined arbitrarily, and by combining them, the wiring efficiency can be increased more effectively, and a substrate configuration that is resistant to noise and fraud can be obtained.

In addition, all terminal arrangements, wiring patterns, installation positions of electronic components, etc. shown in the drawings were constructed by seeking optimum solutions. , miniaturization of the substrate and noise reduction are possible.

Further, the present invention can be similarly implemented in various pinball game machines such as an arrange ball machine and a mammoth game machine, as well as game machines other than pinball game machines such as slot machines.

98 liquid crystal control board (substrate)
104 composite chip (chip)
105 control ROM (ROM)
191 composite chip placement area (first placement area)
192 Control ROM placement area (second placement area)
v0~ Via (interlayer conduction part)
L1
~ L6 1st ~ 6th wiring layers

Claims (1)

A substrate having a plurality of wiring layers and an interlayer conductive portion in the plate thickness direction for connecting the plurality of wiring layers to each other,
A game machine in which a chip containing a CPU circuit, a ROM connected to the chip, and predetermined electronic components different from the chip and the ROM are arranged on the substrate,
providing a first placement region in which the chip is placed and a second placement region in which the ROM is placed in a first wiring layer of the plurality of wiring layers;
The chip has a plurality of first terminals capable of outputting and/or inputting predetermined information,
The ROM has a plurality of second terminals capable of inputting and/or outputting predetermined information,
The predetermined electronic component has a plurality of third terminals capable of inputting and/or outputting predetermined information,
The arrangement of the plurality of first terminals is different from the arrangement of the plurality of second terminals and the arrangement of the plurality of third terminals,
a group of first wiring paths for connecting the plurality of predetermined interlayer conduction portions arranged in the second arrangement region and the plurality of first terminals among the interlayer conduction portions; and the plurality of predetermined interlayer conduction portions. a second wiring path group that connects the plurality of second terminals, respectively; and a third wiring path group that connects the plurality of predetermined interlayer conduction portions and the plurality of third terminals, respectively;
approximating the arrangement of the plurality of predetermined interlayer conductive portions to the arrangement of the plurality of third terminals ;
The second wiring path group converts an arrangement corresponding to the plurality of predetermined interlayer conductive parts to an arrangement corresponding to the second terminal within the second arrangement area and connects to the second terminal.
A gaming machine characterized by:

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