JP7130017B2 - game machine - Google Patents

Description

The present invention relates to gaming machines such as pachinko machines and slot machines.

2. Description of the Related Art Most gaming machines such as pachinko machines are equipped with liquid crystal display means for displaying effect images and the like. The display of the liquid crystal display means is controlled based on an image data signal output from a VDP (Video Display Processor) circuit mounted on a control board and other control signals (Patent Document 1).

JP 2017-093632 A

In a conventional game machine, if even a part of the control signal related to liquid crystal control is lost due to some trouble, the liquid crystal display means displays an image that cannot be identified by the player, and the game cannot be continued normally. It was possible.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a gaming machine capable of minimizing adverse effects on game progress due to occurrence of troubles related to liquid crystal control.

According to the present invention, there is provided a gaming machine which includes display control means for controlling display of a liquid crystal display means, and which can display an advance notice image regarding occurrence of a predetermined event on the liquid crystal display means, wherein the display control means corresponds to odd-numbered pixels. The odd-numbered image data and the even-numbered image data corresponding to the even-numbered pixels adjacent to the odd-numbered pixels are output to the liquid crystal display means through different wiring paths to dynamically display the preview image. In this case, even if one of the odd-numbered image data and the even-numbered image data is missing, the preview image is configured to change for each frame, and when the preview image is dynamically displayed, the preview image is displayed dynamically. The image is configured to change by two dots or more in the direction in which the odd-numbered pixels and the even-numbered pixels are arranged for each frame.

According to the present invention, it is possible to minimize adverse effects on game progress due to troubles related to liquid crystal control.

1 is an overall front view of a pachinko machine according to a first embodiment of the present invention; FIG. It is an exploded perspective view of the pachinko machine. It is an exploded perspective view of the glass door of the pachinko machine. FIG. 2 is a plan view of a main portion showing operation effect means, a cross operation button, a volume adjustment button, a light amount adjustment button, etc. of the same pachinko machine; It is a front view of the game board of the pachinko machine. It is a front view of the game information display means of the pachinko machine. It is a rear view of the pachinko machine. It is an exploded perspective view of the performance board case and the performance control unit of the pachinko machine. It is a plan cross-sectional view of the performance board case and the performance control unit of the same pachinko machine. It is a block diagram showing the overall circuit configuration of the pachinko machine. It is an explanatory diagram regarding the specification of the liquid crystal display means in the same pachinko machine. FIG. 10 is an explanatory diagram relating to specifications of a liquid crystal control signal in the same pachinko machine; It is a block diagram which shows the structure of the liquid crystal display means in the same pachinko machine. It is a block diagram showing the overall configuration of a composite chip in the same pachinko machine. It is a block diagram showing the main configuration of a composite chip in the same pachinko machine. FIG. 4 is an explanatory diagram of an index space, an index table, a virtual drawing space, and a drawing area in the same pachinko machine; It is a block diagram describing the internal configuration of the data transfer circuit in the pachinko machine together with the related circuit configuration. It is a block diagram describing the internal configuration of the display circuit in the pachinko machine together with the related circuit configuration. It is explanatory drawing of the data valid signal ENAB in the same pachinko machine. It is a figure which shows the 1st wiring layer in the liquid crystal control board of the same pachinko machine. It is a figure which shows the 2nd wiring layer in the same liquid crystal control board. It is a figure which shows the 3rd wiring layer in the same liquid crystal control board. It is a figure which shows the 4th wiring layer in the same liquid crystal control board. It is a figure which shows the 5th wiring layer in the same liquid crystal control board. It is a figure which shows the 6th wiring layer in the same liquid crystal control board. FIG. 4 is a diagram showing terminal information of a composite chip arranged on the same liquid crystal control board; It is a figure which shows the terminal information of control ROM arrange|positioned at the same liquid crystal control board. 3 is a diagram of wiring paths P1 to P71 extracted from the first wiring layer of the liquid crystal control substrate; FIG. FIG. 3 is a diagram of wiring paths P1 to P71 extracted from a second wiring layer of the same liquid crystal control substrate; FIG. 3 is a diagram of wiring paths P1 to P71 extracted from a third wiring layer of the same liquid crystal control board; FIG. 10 is a diagram of wiring paths P1 to P71 extracted from a fourth wiring layer of the same liquid crystal control substrate; FIG. 10 is a diagram of wiring paths P1 to P71 extracted from a fifth wiring layer of the same liquid crystal control substrate; FIG. 10 is a diagram of wiring paths P1 to P71 extracted from a sixth wiring layer of the same liquid crystal control substrate; FIG. 29 is an enlarged view of a region E1a in FIG. 28; FIG. 29 is an enlarged view of a region E1b in FIG. 28; 29 is an enlarged view of a region E1c in FIG. 28; FIG. 31 is an enlarged view of a region E3a in FIG. 30; FIG. 31 is an enlarged view of a region E3b in FIG. 30; FIG. 31 is an enlarged view of a region E3c in FIG. 30; FIG. 32 is an enlarged view of a region E4 in FIG. 31; FIG. 34 is an enlarged view of a region E6a in FIG. 33; FIG. 34 is an enlarged view of a region E6b in FIG. 33; FIG. 34 is an enlarged view of a region E6c in FIG. 33; FIG. 34 is an enlarged view of a region E6d in FIG. 33; FIG. FIG. 3 is a diagram schematically showing wiring paths of wiring paths P1 to P8 on the liquid crystal control board of the pachinko machine according to the first embodiment of the present invention; 4 is a diagram schematically showing wiring paths P9 to P17 on the same liquid crystal control board; FIG. 4 is a diagram schematically showing wiring paths P18 to P26 on the same liquid crystal control board; FIG. 4 is a diagram schematically showing wiring paths P27 to P34 on the same liquid crystal control board; FIG. 4 is a diagram schematically showing wiring paths P35 to P42 on the same liquid crystal control board; FIG. 4 is a diagram schematically showing wiring paths P43 to P47 on the same liquid crystal control board; FIG. FIG. 4 is a diagram schematically showing wiring paths P48 to P51 on the same liquid crystal control board; 4 is a diagram schematically showing wiring paths P52 to P61 on the same liquid crystal control board; FIG. FIG. 4 is a diagram schematically showing wiring paths P62 to P71 on the same liquid crystal control board; It is a circuit diagram of a decoding circuit in the same liquid crystal control board. It is a circuit diagram of a reset circuit in the same liquid crystal control board. FIG. 4 is a diagram showing a silk print pattern on the first wiring layer side of the same liquid crystal control board; It is a diagram showing a first wiring layer in the liquid crystal interface substrate of the same pachinko machine. It is a figure which shows the 2nd, 5th wiring layer in the same liquid crystal interface board. FIG. 4 is a diagram showing a third wiring layer in the same liquid crystal interface substrate; It is a figure which shows the 4th wiring layer in the same liquid crystal interface board. It is a figure which shows the 6th wiring layer in the same liquid crystal interface board. FIG. 3 is a diagram showing only wiring paths P101 to P124 extracted from the first wiring layer in the liquid crystal interface substrate; FIG. 3 is a diagram of wiring paths P101 to P124 extracted from the second and fifth wiring layers of the liquid crystal interface substrate; FIG. 3 is a diagram of wiring paths P101 to P124 extracted from a third wiring layer of the same liquid crystal interface substrate; FIG. 10 is a diagram of wiring paths P101 to P124 extracted from the fourth wiring layer of the same liquid crystal interface substrate; FIG. 10 is a diagram of wiring paths P101 to P124 extracted from the sixth wiring layer of the same liquid crystal interface substrate; FIG. 63 is an enlarged view of a region E11a in FIG. 62; 63 is an enlarged view of a region E11b in FIG. 62; FIG. 63 is an enlarged view of a region E11c in FIG. 62; FIG. 67 is an enlarged view of a region E16a in FIG. 66; FIG. 67 is an enlarged view of a region E16b in FIG. 66; FIG. 67 is an enlarged view of a region E16c in FIG. 66; FIG. FIG. 4 is a diagram schematically showing wiring paths P101 to P110 in the liquid crystal interface board of the pachinko machine according to the first embodiment of the present invention; 4 is a diagram schematically showing wiring paths P111 to P120 on the same liquid crystal interface substrate; FIG. 4 is a diagram schematically showing wiring paths P121 to P124 on the same liquid crystal interface substrate; FIG. It is a circuit diagram near the liquid crystal IF third connector on the same liquid crystal interface board. It is a circuit diagram near the liquid crystal IF second connector on the same liquid crystal interface board. It is a circuit diagram of the main part in the liquid crystal interface board of the pachinko machine. It is a block diagram which shows schematic structure of the production|presentation control part of the same pachinko machine. It is a figure which shows the kind and big-hit reliability of the pending|holding alerting|reporting image in the same pachinko machine. It is explanatory drawing of the dynamic display at the time of the display start of the suspension notification image in the same pachinko machine, during display, and the display end. FIG. 10 is an explanatory diagram showing a display state of a hold notification image when either the odd numbered image data or the even numbered image data is missing in the same pachinko machine. FIG. 4 is a diagram showing the distribution of color information in pixel units when either odd image data or even image data is missing in the same pachinko machine, and (a) shows a plurality of types of color information distributed in the vertical direction. (b) shows the case of distribution in the lateral direction. It is explanatory drawing of the dynamic display at the time of a shift of the hold|hold alerting|reporting image in the same pachinko machine. It is a figure which shows the color distribution of the decorative pattern in the same pachinko machine. It is a figure which shows the dynamic display of the decoration pattern in the same pachinko machine. It is a figure which shows the operation guidance image of the same pachinko machine. It is a figure which shows the example of the rainbow background image used by the full-surface rainbow image production|presentation of the pachinko machine. It is a figure which shows the time change of the rainbow background image of the same pachinko machine. It is a figure which shows the specific example of win-lose branch button production|presentation NB1 of the same pachinko machine. It is a figure which shows the time change of the band production|presentation image in the same pachinko machine. It is a figure which shows the kind of the operation guidance image in the same pachinko machine. FIG. 10 is a diagram showing a temporal change near the boundary of the operation valid period notification image in the same pachinko machine (in the case where two dots are moved for each frame), (a) when there is no missing image data, and (b). indicates the case where either odd image data or even image data is missing. FIG. 10 is a diagram showing a change over time when the boundary of the operation effective period notification image moves by one dot for each frame, (a) showing the case where there is no missing image data, and (b) showing the odd image data and the even image. It shows the case where any of the data is missing. FIG. 10 is a diagram showing a case where color information changes in the vertical direction in partial rainbow image rendering of the same pachinko machine. FIG. 10 is a diagram showing a case where color information changes in the horizontal direction in the partial rainbow image effect of the same pachinko machine. It is a figure which shows the setting suggestion effect|action selection table of the same pachinko machine. It is a figure which shows the example of a screen display in the setting suggestion effect|action of the same pachinko machine. Explanatory diagram showing the color distribution in pixel units when moving by a predetermined number of dots per frame in a rainbow effect that changes in the horizontal direction with respect to the position and time of the same pachinko machine, in the normal state and when even/odd pixels are missing. be. It is a figure which shows the time change of the band production image in the pachinko machine which concerns on the 2nd Embodiment of this invention. (a) is a diagram showing an example in which a rainbow image is used as a star-shaped figure displayed during a ready-to-win effect, and (b) is a diagram showing an example in which a rainbow image is used as a ready-to-win title character.

Embodiments of the invention will be described in detail below with reference to the drawings. 1 to 99 illustrate a first embodiment in which the present invention is applied to a pachinko machine. 1 and 2, a gaming machine body 1 includes an outer frame 2 and a front frame 3 arranged in front of the outer frame 2. As shown in FIG. The front frame 3 is pivotally attached to the outer frame 2 so as to be openable and detachable via a vertical first hinge 4 arranged at one end in the left-right direction, for example, the left end. The outer frame 2 can be locked in the closed state by a locking means 5 provided on the opposite side, for example, the right end side.

The front frame 3 includes an inner frame 6 and a front door 7 arranged on the front side of the inner frame 6. - 特許庁The front door 7 is pivotally attached to the inner frame 6 via a vertical second hinge 8 disposed at one end in the left-right direction, for example, at the left end so as to be openable and detachable. can be locked in the closed state.

As shown in FIG. 2, the outer frame 2 is formed in a rectangular shape by a pair of left and right vertical frame members 2a and 2b and a pair of upper and lower horizontal frame members 2c and 2d. A front cover member 9 made of, for example, synthetic resin is attached to the front lower portion of the outer frame 2 so as to connect the front lower portions of the left and right vertical frame members 2a and 2b along the front edge of the lower horizontal frame member 2d. there is The front cover member 9 protrudes forward from the left and right vertical frame members 2a and 2b, and the inner frame 6 is arranged on the upper side thereof. In the outer frame 2, an outer frame upper hinge metal fitting 11 constituting the first hinge 4 is disposed, for example, at the upper left portion, and an outer frame lower hinge metal fitting 12 is disposed above the front cover member 9 at the lower left portion.

The inner frame 6 is made of synthetic resin, and has a rectangular frame portion 13 that can substantially contact the front edge side of the outer frame 2 on the upper side of the front cover member 9, and a game board provided on the upper side inside the frame portion 13. A mounting portion 14 and a lower mounting portion 15 provided on the lower side in the frame portion 13 are integrally provided, for example. A game board 16 is detachably attached to the game board mounting portion 14, for example, from the front side. In the inner frame 6, a main body frame upper hinge metal fitting 19 constituting the first hinge 4 and a main body frame upper hinge metal fitting 20 constituting the second hinge 8 are arranged, for example, at the upper left portion of the first and second hinges 4, 8. Main body frame lower hinge metal fittings 21 are arranged, for example, in the lower left part.

The front door 7 has a resin door base 22 formed in a rectangular shape corresponding to the front side of the inner frame 6 . The door base 22 is formed with window holes 24a of a glass window 24 corresponding to the front side of the game area 23 formed on the game board 16. For example, a plurality of windows (four here) are formed around the window holes 24a. Various effects means such as an upper speaker 25, a first frame movable effect means 26, a second frame movable effect means 27, and an air blowing means 28 are arranged.

On the upper front side of the door base 22, a side unit 30 is attached to at least a portion of the outer circumference of the window hole 24a, for example, an inverted L-shaped portion in front view corresponding to the right side from the upper side of the window hole 24a (FIG. 1). , Fig. 3). As shown in FIGS. 2 and 3, the side unit 30 operates a fixing screw 30a, a fixing lever 30b, etc. on the back side of the front frame 3 without using a special tool while the front frame 3 is open. By doing so, it can be easily attached and detached. On the front side of the side unit 30 are, as shown in FIG. 28 or the like is installed.

The first frame movable body 26a of the first frame movable effect means 26 is formed in an arbitrary three-dimensional shape (in this case, a shape with a butterfly motif), and can be slid substantially forward and backward by driving means (not shown). It is possible. The frame second movable body 27a of the frame second movable effect means 27 slides substantially in the front-rear direction by being driven by a driving means (not shown) and vibrates by a vibrating means (not shown) arranged in the grip portion 27b. , and the player can press the grip portion 27b. Further, the air blowing means 28 can blow air toward the player's hand at the timing when the player grips the grip portion 27b. Further, on the front side of the front door 7 including the side unit 30, a frame lamp 304 composed of a large number of LEDs 301a to 301d is arranged so as to substantially surround the glass window (display window) 24. As shown in FIG.

On the front side of the lower portion of the door base 22, an upper tray 33 for storing game balls put out from the putting out means 32 arranged on the rear side of the inner frame 6 and supplying them to the shooting means 17, and the upper tray 33 is full. A lower tray 34 for storing surplus balls, etc., and a firing handle 35 operated to operate the firing means 17 are arranged, and a lower decorative cover 36 that substantially covers the upper tray 33, the lower tray 34, etc. from the front side is attached. It is The lower decorative cover 36 is formed, for example, in a forward-facing bulging shape, and various operation means such as an operation presentation means 37, a cross operation button 38, a volume adjustment button 39, and a light amount adjustment button 40 are provided on the upper side thereof, for example. (Fig. 4). The operation presentation means 37 is used for advance notice presentation during symbol variation and other presentations, and is equipped with a vertically moving presentation button 41 that can be pressed by the player.

On the back side of the door base 22, as shown in FIG. 2, a glass unit 50 is detachably attached to substantially block the window hole 24a from the rear side, and the edges of the first and second hinges 4, 8 are provided with the glass unit 50. A vertical hinge end side reinforcing sheet metal 51a arranged along, a vertical opening/closing end side reinforcing sheet metal 51b arranged along the edge of the opening/closing end side, and left and right sides arranged under the window hole 24a. The direction lower reinforcing sheet metal 51c is detachably fixed by screws or the like. Further, on the door base 22, a glass door upper hinge metal fitting 52a and a glass door lower hinge metal fitting 52b constituting the second hinge 8 are disposed, for example, at the upper left portion and the lower left portion, respectively.

Further, for example, a ball feeding unit 53a, a lower tray guide unit 53b, and the like are mounted on the back side of the lower reinforcing sheet metal 51c. The ball feeding unit 53a is for supplying game balls in the upper tray 33 to the shooting means 17, and is arranged in front of the shooting means 17 arranged on the inner frame 6 side. By activating the ball feed solenoid 53c in synchronization with the shooting operation, the game balls in the upper tray 33 are supplied one by one onto the shooting rail 17a of the shooting means 17. As shown in FIG.

The shooting means 17 includes a shooting rail 17a which is arranged in an upward leftward sloping shape when viewed from the front, and a shooting ball stopper 17b which supports the game ball supplied onto the shooting rail 17a by the ball feeding unit 53a at a shooting standby position. , a striking hammer 17c arranged corresponding to a shooting standby position on the shooting rail 17a and capable of swinging around a drive shaft in the front-rear direction; When the shooting handle 35 is rotated, the shooting drive means 17d continuously drives the hammer 17c in the striking direction (clockwise) with a shooting intensity corresponding to the amount of operation.

The lower tray guide unit 53b guides surplus balls when the upper tray 33 is full and foul balls that have returned without reaching the game area 23 despite being shot by the shooting means 17 to the lower tray 34. For example, it is arranged adjacent to the ball feeding unit 53a on the side of the first and second hinges 4 and 8 thereof.

As shown in FIG. 5, the game board 16 has a base plate 55 made of plywood, polycarbonate, or the like. , and in the game area 23 inside the guide rail 56, in addition to unit parts such as the central display frame unit 57, the starting winning unit 58, the normal winning unit 59, etc., a large number of game nails (not shown) are arranged. Also, for example, a game information display means 60 is arranged at the outer lower part of the game area 23 .

As shown in FIG. 6, the game information display means 60 is provided with four LED groups composed of eight LEDs 70, and a total of 32 LEDs 70 are normal symbol display means 61 and normal reserved number display means 62. , 1st special symbol display means 63, 2nd special symbol display means 64, 1st special reserved number display means 65, 2nd special reserved number display means 66, fluctuation shortening notification means 67, right hitting notification means 68 and round number notification A predetermined number of them are assigned to the means 69 . That is, the eight LEDs 70 belonging to the first and second LED groups 60a and 60b constitute the first and second special symbol display means 63 and 64, respectively, and the eight LEDs 70 belonging to the third LED group 60c are two. Eight LEDs 70 belonging to the fourth LED group 60 d constitute the first special reserved number display means 65, the second special reserved number display means 66, the normal reserved number display means 62, and the fluctuation reduction notification means 67, respectively. , two constitute normal symbol display means 61, the other two constitute right-handed informing means 68, and the remaining four constitute round number informing means 69, respectively.

On the plurality of unit parts 57 to 59 of the game board 16, normal symbol starting means 71, first special symbol starting means 72, second special symbol starting means 73, big winning means 74, a plurality of normal winning means 75, etc. is provided. Further, on the rear side of the base plate 55, in addition to the liquid crystal display means (image display means) 76, board movement effect means 77 having a movable accessory 77a that can move on the front side of the liquid crystal display means 76 and the like are arranged. .

The movable accessory 77a is formed in a horizontally long rectangular box shape, and both left and right sides thereof are supported on the outside of the side edges of the liquid crystal display means 76 so as to be vertically movable. It is vertically movable between an origin position (see FIG. 5) on the upper side of the display means 76 and an operation position on the front side of the liquid crystal display means 76 . A movable accessory lamp 314 consisting of a plurality of LEDs 311 is arranged on the front side of the movable accessory 77a.

The central display frame unit 57 constitutes a display frame for the liquid crystal display means 76 and the movable accessory 77a. It is detachably attached from the front side to an attachment hole (not shown) formed in the front-rear direction penetrating shape. This central display frame unit 57, as shown in FIG. A decorative frame 82 arranged in a substantially gate shape in front view extending from both left and right sides to the upper side on the front side of the , and protruding forward on the inner peripheral side of the front mounting plate 81, and arranged between the left and right lower ends of the decorative frame 82 and a stage 83 to be performed. The game balls fired by the shooting means 17 and entering the upper part of the game area 23 are distributed to the left and right at the top of the decoration frame 82, and are distributed to the left flow path 84a on the left side of the central display frame unit 57 and the right flow path 84b on the right side. or flow down.

The central display frame unit 57 is provided with a warp entrance 85 through which game balls can flow in at least one of the left flow path 84a and the right flow path 84b, for example, the left flow path 84a. A game ball that flows into the warp entrance 85 while flowing down the left flow path 84a rolls freely in the left-right direction on the stage 83, and then moves to a central drop portion 86 provided corresponding to the center in the left-right direction of the game area 23. and the other portion to the front.

In addition, on the front side of the central display frame unit 57, board lamps 324 made up of a large number of LEDs 321a to 321c are arranged corresponding to at least a part of the periphery of the liquid crystal display means 76, for example, the left and right sides and the upper side. A part of the board lamp 324 may be arranged in the starting winning unit 58, the normal winning unit 59, and the like.

As shown in FIG. 5, the starting prize winning unit 58 is arranged below the central display frame unit 57 along the guide rail 56 and is detachably attached to the base plate 55 from the front side. As shown in FIG. 5, the normal winning unit 59 is arranged below the central display frame unit 57 and to the left of the starting winning unit 58 along the guide rail 56, and is detachably attached to the base plate 55 from the front side. ing.

The normal symbol starting means 71 is for starting variable display of normal symbols by the normal symbol display means 61, and is composed of a passage gate or the like through which a game ball can pass, and is a game ball detection switch for detecting passage of a game ball. (illustration omitted). As shown in FIG. 5, the normal symbol starting means 71 is provided, for example, on the front side of the front attachment plate 81 on the right side of the central display frame unit 57, so that game balls flowing down the right flow path 84b can pass through. ing.

The normal symbol display means 61 is for variably displaying normal symbols, and as shown in FIG. Based on the detection of the game ball by the 71, after the two LEDs 70 constituting the normal pattern emit light in the light emission pattern during normal fluctuation, the normal random number information acquired when the game ball is detected by the normal symbol starting means 71 If the included hit determination random value matches a predetermined hit determination value, the variation is stopped in a win mode, and in other cases, in a losing mode. In addition, the two LEDs 70 constituting the normal pattern can display one or more winning modes and one or more losing modes depending on the combination of their light emission modes (for example, lighting / extinguishing), and during normal fluctuation The light emission pattern is such that, for example, a plurality of specific types (here, two types) of light emission modes are switched every predetermined time (for example, 128 ms).

In addition, when the normal symbol starting means 71 detects the game ball during the normal holding period including during the symbol fluctuation of the normal symbol display means 61 and during the normal profit state, the normal random number information acquired thereby is predetermined. The set upper limit reserved number, for example, 4, is reserved and stored, and each time the normal reserved period ends, one is consumed and the normal pattern is varied. The stored number of normal random number information (normal reserved number) is notified to the player by the normal reserved number display means 62 or the like. The normal reserved number display means 62 is composed of a predetermined number (here, two) of LEDs 70 in the game information display means 60 as shown in FIG. By combining flashing/lighting out, it is possible to display 5 types of normal pending numbers from 0 to 4.

The first special symbol starting means 72 is for starting the symbol variation by the first special symbol display means 63, and is composed of a non-opening/closing type winning means having no opening/closing means, and detects a winning game ball. A detection switch (not shown) is provided. This first special symbol starting means 72 is provided in, for example, the starting winning unit 58 as shown in FIG. Since there is a winning route via the stage 83 from the warp entrance 85 on the side of the flow path 84a, the game ball flowing down the left flow path 84a has a higher probability than the game ball flowing down the right flow path 84b. It is possible to win a prize at In addition, when game balls win in the first special symbol starting means 72, a predetermined number of game balls are paid out as prize balls per one win.

The second special symbol starting means 73 is for starting the symbol variation by the second special symbol display means 64, and by operating the opening/closing part 88, the game ball can A game ball detection switch (not shown) that detects a game ball that has won a prize, and an opening/closing drive means such as an electromagnetic solenoid that opens/closes the opening/closing portion 88. When the normal profit state occurs due to the winning mode of the stopped symbol after the change of the normal symbol display means 61, the opening/closing part 88 changes from the closed state to the open state for a predetermined time. there is

This second special symbol starting means 73 is arranged on the front mounting plate 81 in the right part of the central display frame unit 57 and downstream of the normal symbol starting means 71 as shown in FIG. A game ball flowing down 84b can win a prize. The opening/closing part 88 can swing about, for example, a rotation axis in the left-right direction provided on the lower side. In the state, the front side of the front mounting plate 81 is tilted downward backward, and the game ball is made to win backward. When game balls win in the second special symbol starting means 73, a predetermined number of game balls are paid out as prize balls per winning.

The first special symbol display means (symbol display means) 63, as shown in FIG. On the condition that the game ball is detected, after the eight LEDs 70 constituting the first special symbol emit light in the special fluctuation light emission pattern, when the game ball is detected by the first special symbol starting means 72 (the symbol starting condition is If the big hit judgment random value included in the first special random number information acquired in the case of establishment) matches the predetermined big hit judgment value (when it becomes a big hit in the random number lottery), it is a big hit mode and similarly small. When it matches with the hit judgment value (when it becomes a small hit in a random number lottery), the variation is stopped in a small win mode, and in other cases, in a losing mode. A big win game is executed when the stopped symbol after the variation of the first special symbol display means 63 becomes a big win mode, and a small win game is executed when it becomes a small win mode (profit state generating means).

The second special symbol display means (symbol display means) 64, as shown in FIG. On the condition that the game ball is detected, after the eight LEDs 70 constituting the second special symbol emit light in the special fluctuation light emission pattern, when the game ball is detected by the second special symbol starting means 73 (the symbol starting condition is If the big hit determination random value included in the second special random number information acquired in the case of establishment) matches the predetermined big hit determination value (when the random number lottery results in a big hit), the big hit mode and the small win When it matches with the hit judgment value (when it becomes a small hit in a random number lottery), the variation is stopped in a small win mode, and in other cases, in a losing mode. A big win game is executed when the stopped symbol after the variation of the second special symbol display means 64 becomes a big win mode, and a small win game is executed when it becomes a small win mode (profit state generating means).

The first and second special symbol display means 63, 64 are one or more jackpot modes, one or more small win modes, one or more, depending on the combination of light emission modes (for example, lighting/extinguishing) of the eight LEDs 70. The deviation mode can be displayed, and the special fluctuating light emission pattern switches between a plurality of specific types (here, two types) of light emission modes at predetermined time intervals (for example, 128 ms).

Also, during the symbol variation of the first special symbol display means 63, during the symbol variation of the second special symbol display means 64, and during the special holding period including during the jackpot game, the first and second special symbol starting means 72, 73 are activated. When a sphere is detected, the first and second special random number information acquired thereby are retained and stored in the retention storage means up to a predetermined upper limit retention number, for example, 4 each. Then, when the reserved memory on the side of the second special pattern is 1 or more at the time when the special reserved period ends, one reserved memory of the second special pattern is digested to change the second special pattern, and the first special pattern is changed. When only the reserved memory on the side of the special design is 1 or more, one reserved memory of the first special design is digested to change the first special design. As described above, in this embodiment, both the first special symbol and the second special symbol are not fluctuating, and when both the first special symbol side and the second special symbol side have reserved memory, is to preferentially change the second special symbol.

In the case of this embodiment, the player hits to the left aiming at the first special symbol starting means 72 during the normal game state other than during the special game state described later, and during the special game state, the normal symbol starting means 71 and the second Since the player hits to the right aiming at the 2 special symbol starting means 73, the first special symbol mainly fluctuates during the normal game state, and the second special symbol mainly fluctuates during the special game state.

The numbers (first and second special reserved numbers) of the first and second special random number information reserved and stored in the reserved storage means are displayed on the first and second special reserved number display means 65 and 66, the liquid crystal display means 76 and the like. is notified to the player. Here, the first and second special reserved number display means 65 and 66 are composed of a predetermined number (here, two each) of LEDs 70 in the game information display means 60 as shown in FIG. For example, it is possible to display 5 kinds of first and second special holding numbers of 0 to 4 by combining lighting/blinking/lighting out.

In addition, there are two types of probability (jackpot probability) of hitting a jackpot (jackpot probability) in the jackpot determination (random number lottery) performed based on the game ball detection by the first and second special symbol starting means 72 and 73, ie, a low probability and a high probability. , It is set to a high probability during the variable probability state of the special game state described later, and to a low probability otherwise. In addition, in this embodiment, the set value can be set to any of a plurality of stages (here, 6 stages), and the jackpot probability (low probability and high probability) changes according to the set value (settings 1 to 6) . The big hit probability is higher, for example, as the set value is larger.

In addition, when the big hit determination result is a loss, one or a plurality of types of losses are selected, and when the big hit determination result is a small win, one or a plurality of types of small wins are selected. However, when the big hit determination result is a big hit, one or a plurality of types of big wins (for example, two types of variable probability big wins and non-variable probability big wins) are selected. Here, the probability variable big hit is a big hit that generates a probability variable state (first special game state) as a special game state after the end of the big hit game, and the non-variable probability big hit is a special game state after the end of the big win game, for example, a time saving state. The big hits that cause (second special game state) are distributed based on the big hit symbol random numbers and the like.

During the time saving state, for example, the variation times of the first and second special symbol display means 63, 64 are switched to a shortened variation time shorter than the normal variation time with respect to the first and second special symbols, and the probability of winning with respect to the normal symbols. is from normal probability to high probability, the fluctuation time is from normal fluctuation time to shortened fluctuation time, the opening and closing pattern of the second special symbol starting means 73 in the normal profit state is from the normal opening and closing pattern (for example, 0.2 seconds × 1 time open) It can be switched to a special opening/closing pattern (for example, opening 2 seconds x 3 times). The time saving state starts when the big win game ends, and ends when, for example, the first and second special symbols fluctuate a predetermined number of times (for example, 50 times) or when the next big win game occurs by then. Moreover, during the variable probability state, for example, in addition to switching similar to the time saving state, the probability of a big hit is switched from a low probability to a high probability. Incidentally, the variable probability state starts when the big hit game ends, and ends when the next big hit game occurs, for example.

The big winning means 74 is an opening/closing type winning means having an opening/closing plate 89 capable of switching between an open state in which game balls can win and a closed state in which game balls cannot win. provided with a game ball detection switch (not shown) for detecting a winning game ball, and an opening and closing driving means such as an electromagnetic solenoid for opening and closing the opening and closing plate 89, and the downstream side of the second special symbol starting means 73 And by being arranged on the upstream side of the first special symbol starting means 72, the game ball flowing down the right flowing path 84b can win with a higher probability than the game ball flowing down the left flowing path 84a. It has become. When the first and second special symbols of the first and second special symbol display means 63 and 64 stop in the big win mode (specific mode) after the variation, the big winning means 74 opens in a predetermined big win opening pattern. (big hit game), similarly, when it stops in the small win mode, it is released with a predetermined small win release pattern (small win game). When a game ball wins the big winning means 74, a predetermined number of game balls are paid out as prize balls per winning.

In parallel with the variable display of the first and second special symbols by the first and second special symbol display means 63 and 64, the liquid crystal display means 76 can variably display the decorative pattern 90. 2 It is possible to display various images such as the first and second hold notification images X1 to X4, Y1 to Y4 indicating the number of special holds, and the hold notice image Z during fluctuation.

Here, the decorative pattern 90 has a plurality of pattern rows (three in the horizontal direction in the example of FIG. 5) composed of a plurality of patterns such as numeral patterns, and each pattern constituting each pattern row is , and as shown in FIG. 5, it is composed of a combination of a pattern body 90a composed of numbers such as 1 to 8 and others, and a decoration part 90b such as a character attached to the pattern body 90a. It should be noted that the decorative pattern 90 can be arbitrarily changed in display mode, such as enlargement or reduction, change in display position, or erasure of the decorative portion 90b.

The decorative symbols 90, for example, start fluctuating by vertical scrolling, horizontal scrolling, etc. for each symbol row according to a predetermined fluctuation pattern substantially at the same time as the first and second special symbols start to fluctuate, and the stop symbols on a predetermined effective line start to fluctuate. For example, the first and second special symbols are finally stopped substantially at the same time as the fluctuation stop so that a predetermined mode is achieved. In the decorative pattern 90, for example, when all the stop patterns on the effective line are the same, the big win effect mode is used, and when the other patterns are the same, the small win effect mode or the losing effect mode is used, and the first and second special symbols are the big win mode. In this case, the decorative pattern 90 becomes a big hit production mode, and when the first and second special patterns become a small win mode, the decorative pattern 90 becomes a small win production mode, and the first and second special patterns become a losing mode. In that case, the decorative pattern 90 will be in a performance mode.

In addition, regarding the first and second suspension notification images X1 to X4, Y1 to Y4, and the variable suspension notification image Z, the first and second special symbol starting means 72 and 73 detect the game ball. , when the number of second special reservations increases, one additional first and second reservation notification images X1-, Y1-are displayed on the liquid crystal display means 76, and the first and second special symbol display means 63, 64 when the first and second special reserved numbers are reduced based on the start of new fluctuations of the first and second special symbols, for example, the suspended notification image Z during fluctuation is erased, and the first and second The hold notification images X1~, Y1~ are shifted one by one toward the front side of the queue (for example, the right side of the screen), and the first and second hold notification images X1, Y1 pushed out are moved to, for example, a predetermined position. It is moved to change to a new change pending notification image Z. FIG.

On the back side of the game board 16, as shown in FIG. 7, a back case 91 for supporting the liquid crystal display means 76 on the back side of the game board 16 is attached. A main board case 94 housing a main control board 93 constituting a part 92, a production interface board 96 constituting a production control part 95, a liquid crystal interface board 97, a liquid crystal control board 98 and a ROM board 99 are stored in a production board case. 100 and the like are detachably attached.

Here, details of how the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98 and the ROM board 99 are stored in the effect board case 100 will be described with reference to FIGS.

The effect interface board 96 and the liquid crystal interface board 97 are arranged so that their respective surfaces 96a and 97a face the rear side and are adjacent to each other in the left and right directions. The effect interface board 96 and the liquid crystal interface board 97 are arranged along the edge of the effect interface board 96 on the side of the liquid crystal interface board 97. The effect IF first and second connectors CN11 and CN12 The first and second liquid crystal IF connectors CN21 and CN22 arranged along the edge on the effect interface board 96 side are directly connected in the horizontal direction to be integrated with each other. Various electronic components are arranged on both front and back sides of the effect interface board 96. Various ICs such as the audio processor 101 and the digital amplifier 102, various connectors such as the liquid crystal IF first to third connectors CN21 to CN23, The audio ROM 103 and the like are arranged on the surface 96a side. Various electronic components are arranged on both sides of the liquid crystal interface board 97. In addition to liquid crystal IF first to third connectors CN21 to CN23, liquid crystal connection first and third connectors for connecting the liquid crystal display means 76 are provided. Various connectors such as the second connectors CN24 and CN25 are arranged on the surface 97a side.

The liquid crystal control board 98 is arranged behind the effect interface board 96 and the liquid crystal interface board 97 so that the front surface 98a faces rearward and the back surface 98b faces the surfaces 96a and 97a of the effect interface board 96 and the liquid crystal interface board 97. are placed. The liquid crystal control board 98 connects the liquid crystal control first connector CN31 provided on the back surface 98b side to the effect IF third connector CN13 on the effect interface board 96 side, and the liquid crystal control second connector CN32 also provided on the back surface 98b side. are directly connected to the third liquid crystal IF connector CN23 on the side of the liquid crystal interface board 97, the effect interface board 96 and the liquid crystal interface board 97 are integrated. Various electronic components are arranged on both front and back sides of the liquid crystal control board 98. The composite chip 104, the control ROM 105, the DRAM 106, the liquid crystal control third connector CN33, etc. are arranged on the front surface 98a side, and the rear surface 98b side. , liquid crystal control first and second connectors CN31, CN32, etc. are arranged.

The ROM board 99 is arranged adjacent to the liquid crystal control board 98 so that the front surface 99a faces backward and the rear surface 99b faces the display interface board 96 and the liquid crystal interface board 97, for example, the front surface 97a of the liquid crystal interface board 97. placed below it. The ROM board 99 directly connects the ROM first connector CN41 arranged at the upper edge on the surface 99a side to the liquid crystal control third connector CN33 arranged at the lower edge of the liquid crystal control board 98. It is integrated with the liquid crystal control board 98 . Various electronic components are arranged on both the front and back surfaces of the ROM board 99, but the CGROM 107, ROM first connector CN41, etc. are arranged on the surface 99a side.

As described above, the substrates 96 to 99 are connected to each other by directly connecting the connectors to each other. are opposed to each other with a predetermined gap therebetween and are connected and integrated. Therefore, when the substrates 96 to 99 are connected to each other, the rear surface 98b side of the liquid crystal control substrate 98 is hidden by the effect interface substrate 96 and the liquid crystal interface substrate 97 and cannot be viewed.

The effect board case 100 is made of a transparent synthetic resin, and is formed in a substantially box shape with a base body 111 covering the back sides of the boards 96-99 and a cover body 112 covering the front sides of the boards 96-99. When the boards 96 to 99 are stored in the presentation board case 100, the liquid crystal control board 98 and the ROM board 99 are first connected to each other by direct connectors, and then screwed to a predetermined position inside the cover body 112. fixed. At this time, the surfaces 98a and 99a of the liquid crystal control board 98 and the ROM board 99 are opposed to the inner surface side of the back wall 113 of the cover body 112 with a predetermined gap therebetween.

Next, the effect interface board 96 and the liquid crystal interface board 97 are connected to each other by direct connectors, and the liquid crystal control board 98 and the ROM board 99 are fitted into predetermined positions inside the cover body 112 from the rear side. At this time, the effect IF third connector CN13 on the effect interface board 96 side connects to the liquid crystal control first connector CN31 on the liquid crystal control board 98 side, and the liquid crystal IF third connector CN23 on the liquid crystal interface board 97 side connects to the liquid crystal on the liquid crystal control board 98 side. Each is coupled to a control second connector CN32.

Subsequently, the base body 111 is fitted to the cover body 112 from the back surfaces 96b and 97b of the presentation interface board 96 and the liquid crystal interface board 97. As shown in FIG. Further, by screwing to the screw base 115 on the side of the cover body 112 through the through holes 114 of the effect interface board 96 and the liquid crystal interface board 97 from the outside of the base body 111, the boards 96 to 99 are connected to the effect board. It is fixed at a predetermined position inside the case 100 . A presentation board case 100 storing boards 96 to 99 is detachably attached to the rear side of the back case 91 with the base body 111 directed to the front side and the cover body 112 directed to the rear side.

On the back side of the front frame 3, as shown in FIG. 7, a back cover 121 is detachably attached to cover the back side of the game board 16 in an openable and closable manner. However, the payout means 32 and the payout passage 124 are mounted on the left and right sides respectively, and when a game ball enters a winning opening of the big winning means 74 or the like, or a ball lending command is issued from an automatic ball lending machine (not shown). When there is, the game balls in the game ball tank 122 are put out by the putting out means 32 via the tank rail 123, and the game balls are guided to the upper tray 33 through the putting-out passage 124.例文帳に追加In addition, the back cover 121 is arranged so as to cover substantially the entire effect board case 100 and a part of the upper side of the main board case 94 from the rear side.

A board mounting base 125 is detachably mounted on the lower back side of the front frame 3. On the back side of the board mounting base 125, a power board case 127 in which a power board 126 is stored, and a payout firing control board. 128 is housed in a payout ejection board case 129, which is detachably mounted.

FIG. 10 is a block diagram showing the overall configuration of the control system of this pachinko machine. As shown in FIG. 10, the overall circuit configuration of this pachinko machine is composed of a board-side member 131 mounted on the game board 16 side and a frame-side member 132 mounted on the front frame 3 side.

First, the outline of the board-side member 131 will be described. The board-side member 131 includes a main control board 93 that constitutes the main control unit 92, an effect interface board 96 that constitutes the effect control unit 95, a liquid crystal interface board 97, a liquid crystal control board 98, a ROM board 99, and a game board relay board. 133, an LED connection board 134, a main control relay board 135, a power relay board 136, a frame LED relay board 137, and the like.

The main control board 93 performs overall game control, and includes a game ball detection switch provided in the normal symbol starting means 71 and the big winning means 74, etc., an opening and closing driving means provided in the big winning means 74, etc., a game Various sensors such as magnetism, radio waves, vibration, etc., and the game information display means 60, etc., arranged in each part of the board 16 are directly connected via a relay board such as the game board relay board 133 or directly without a relay board. It is Also, the main control board 93 is connected to the effect interface board 96 via the effect control harness 138, and is capable of transmitting the control command CMD and the strobe signal STB.

The main control relay board 135, the power relay board 136, and the frame LED relay board 137 are for connecting the board-side member 131 to the frame-side member 132. It is connected to the control board 128, and the effect interface board 96 is connected to the power supply board 126 via the power relay board 136, and to the frame LED connection board 139 via the frame LED relay board 137, respectively. On the main control relay board 135, the power relay board 136, and the frame LED relay board 137 on the game board 16 side, board-side first to third connectors CN1a to CN3a are arranged respectively corresponding to the rear side of the game board 16, In the game board mounting portion 14 (FIG. 2) on the inner frame 6 side, the frame side first to third connectors CN1b to CN3b are arranged so as to face the board side first to third connectors CN1a to CN3a, respectively. When the game board 16 is mounted on the game board mounting portion 14 of the inner frame 6 from the front side, the board side first to third connectors CN1a to CN3a are coupled to the frame side first to third connectors CN1b to CN3b, respectively. It has become so. In addition, the first frame-side connector CN1b is provided on one end side of the payout-emission control relay harness 141 connected to the payout-emission control board 128, and the second frame-side connector CN2b is the effect control power supply connected to the power supply board 126. The frame-side third connector CN3b is provided on one end side of the harness 142 and is provided on one end side of the frame-lower LED connection harness 143 connected to the frame-lower LED connection board 139 .

The effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98, and the ROM board 99, which constitute the effect control section 95, are integrated with each other by directly connecting the connectors without using a harness as already described. .

Further, the liquid crystal display means 76 is connected to the liquid crystal interface board 97 via liquid crystal connection first and second harnesses 144 and 145 from liquid crystal connection first and second connectors CN24 and CN25. An LED connection board 134 is connected to the effect interface board 96 via an LED connection harness 146 . In the LED connection board 134, in addition to various LED boards such as the LED board 312 constituting the movable accessory lamp 314 and the LED boards 322a to 322c constituting the board lamp 324, a motor used for driving control of the movable accessory 77a, A movable body drive means such as a solenoid, a position detection switch, and the like are connected.

Here, the specification of the liquid crystal display means 76 will be described with reference to FIG. 11 and the like. The liquid crystal display means 76 is a liquid crystal color display of 1280 horizontal pixels×1024 vertical pixels. , are received by a receiver RV (RVa+RVb) via separate LVDS (Low Voltage Differential Signaling) transmission lines. Therefore, in this embodiment, in accordance with this specification, the ODD signal (first signal) is transmitted via the first transmission line LVDS1 including the liquid crystal connection first connector CN24, the liquid crystal connection first harness 144, and the like. The EVEN signal (second signal) is transmitted via the second transmission line LVDS2 (bottom left of FIG. 10).

Further, in the liquid crystal display means 76, the operating clock CK that defines internal operations is specified to have a frequency in the range of 40 MHz to 70 MHz (typical value is 54 MHz). This operation clock CK corresponds to the dot clock DCK, but in the following description, for convenience, the frequency of the operation clock CK is assumed to be 54 MHz, which is a typical value. A configuration will be described in which the update time (frame rate) required to update the image of one frame is set to about 1/60 second at the operating clock CK of 54 MHz.

The liquid crystal display means 76, as its specifications, aligns two pixels adjacent to each other in the left-right direction of the display screen based on the ODD signal received from the first transmission line LVDS1 and the EVEN signal received from the second transmission line LVDS2. It is configured to be processed simultaneously with the operation clock CK. As a result, the pixel data of 1280 pixels corresponding to one line in the horizontal direction is updated with an operation time of 640/54 MHz=11.85 μs, and this operation is repeated for 1024 lines in the vertical direction, resulting in 1280×1024 pixels for one frame. The image representation of the pixels is updated. Note that the image is updated line by line in the non-interlaced manner, such as the 1st line, the 2nd line, . . . , the 1024th line.

However, as shown in FIG. 11, the specification of the liquid crystal display means 76 is to provide a waiting time (blank period) WTh for 204 clocks as a typical value in the horizontal direction and 42 lines as a typical value for the vertical direction. It is stipulated that a waiting time (blank period) WTv is provided. Therefore, the actual screen update cycle considering these waiting times WTh and WTv is (204+640)×(42+1024)/54MHz≈16.66ms in the calculation based on the typical values described above, so the frame rate is about 60Hz. becomes.

For the horizontal standby time WTh and the vertical standby time WTv, an allowable width is defined for each typical value, and in practice, values different from the typical values described above can be selected. However, since the frame rate is 1/60 seconds, it is necessary to accurately set the horizontal and vertical standby times WTh and WTv so that (WTh+640)×(WTv+1024)/54 MHz=1/60 seconds.

The liquid crystal display means 76 does not require the horizontal synchronizing signal HS and the vertical synchronizing signal VS, but requires the transmission of the H-level data valid signal ENAB when transmitting the ODD signal and the EVEN signal. That is, the data valid signal ENAB needs to be at the active level (H level) at the timing when a significant signal (ODD/EVEN signal) is transmitted to the first and second transmission lines LVDS1 and LVDS2.

Therefore, in the present embodiment, based on the specifications of the liquid crystal display means 76 described above, the liquid crystal control board (display control means) 98 and the liquid crystal display means 76 are connected by LVDS through a dual link transmission line with a dot clock (pixel clock) DCK of 54 MHz. are connected (Figs. 13 and 18). In addition, in the VDP circuit 172 (FIG. 14, etc.) mounted on the liquid crystal control board 98, a horizontal waiting time WTh and a vertical waiting time WTv that satisfy the specifications of the liquid crystal display means 76 are provided, and image data (ODD/EVEN signal) is output, the data valid signal ENAB is set to the active level (H level).

That is, as shown in FIG. 12(b), the data valid signal ENAB is configured to be at H level only during the horizontal display period THd in the horizontal synchronization period TH. Therefore, the data valid signal ENAB is always at L level during the vertical synchronization period TV except for the vertical display period TVd (FIG. 12(c)). Note that the horizontal waiting time WTh and the vertical waiting time WTv adopt values different from their respective typical values (WTh is 204, WTv is 42), but specific design values are based on FIG. will be described later.

In any case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal in each operation cycle of the dot clock DCK via the differential signal lines RA2 and RB2, as shown in FIG. 12(a). be. The data valid signal ENAB shown in FIGS. 12(b) and 12(c) is obtained by demodulating the DE signal, which is discrete data transmitted by LVDS, and the discrete DE signal is continuous on the time axis. In the differential signal lines RA2 and RB2, as shown in FIG. 12(a), the vertical synchronizing signal VS and the horizontal synchronizing signal HS are also repeatedly transmitted following the DE signal (data valid signal ENAB). The liquid crystal display means 76 of this embodiment does not utilize the synchronizing signals VS and HS, and internal operations relating to these synchronizing signals HS and VS are not executed.

That is, the horizontal line feed timing of the display line in the liquid crystal display means 76 of this embodiment is independent of the received horizontal synchronizing signal HS, and the operation after the falling timing of the data valid signal ENAB or the rising timing of the data valid signal ENAB. Based on the number of clocks CK (corresponding to dot clocks DCK) (640 in this embodiment), the optimum timing for the internal circuit of the liquid crystal display means 76 is defined (downward arrow in FIG. 12(b)).

This point is the same for the vertical line feed timing after displaying an image for one frame. The optimum timing for the internal circuit is specified (downward arrow in FIG. 12(c)) and is not affected by the received vertical synchronization signal VS. As described above, in this embodiment, since it is not necessary to transmit the horizontal synchronizing signal HS and the vertical synchronizing signal VS to the liquid crystal display means 76, the pulse widths PWh and PWv of the synchronizing signals HS and VS, the front porches FPh and FPv, and the back porch There is no need to optimally set BPh, BPv, etc., and the control burden on the VDP circuit 172 and the like is greatly reduced.

Further, as for the internal operation of the liquid crystal display means 76, horizontal line feed and vertical line feed operations are executed at optimum timing based on its own internal configuration, so that the fear of unnatural display operations is eliminated. Incidentally, in the case of display means that operates based on the horizontal synchronizing signal HS and the vertical synchronizing signal VS received from the outside, the pulse width of the synchronizing signals HS and VS, the front porch period before and after the synchronizing signals HS and VS, and the back porch If the period is inappropriate, normal display operation may be impaired.

By the way, in FIG. 12(a), the first transmission path LVDS1 using the differential signal lines RA0 to RA3 and RACLK transmits a signal corresponding to the odd-numbered pixels (ODD signal on the A side). A second transmission line LVDS2 using the motion signal lines RB0 to RB3 and RBCLK transmits signals corresponding to even-numbered pixels (B-side EVEN signal). Thus, in this embodiment, by transmitting the ODD signal and the EVEN signal through the dual-link transmission line, the frequency of the dot clock DCK can be substantially reduced to 1/2, and the noise resistance can be improved accordingly. can be improved and the transmission distance can also be increased.

On the other hand, the liquid crystal display means 76 has a built-in receiver RV for receiving the ODD signal and EVEN signal transmitted through the dual link transmission line, and converts the RGB signal from the two LVDS signals (ODD signal and EVEN signal). After restoration, an image of one frame (1280×1024 pixels) is displayed. Since each of the RGB signals consists of 8 bits, the liquid crystal display means 76 displays a full-color image with a gradation of 2 ⁸ ×2 ⁸ ×2 ⁸ .

FIG. 13 is a block diagram showing the internal configuration of the liquid crystal display means 76 together with the relevant parts of the VDP circuit 172. As shown in FIG. As illustrated, the ODD signal is transmitted to the LVDS-parallel converter RVa via the first transmission line LVDS1 (A side), and the EVEN signal is transmitted to the LVDS-parallel converter RVa via the second transmission line LVDS2 (B side). It is transmitted to the parallel converter RVb. The first transmission line LVDS1 has five differential signal lines RA0 to RA3 and RACLK, and the second transmission line LVDS2 has five differential signal lines RB0 to RB3 and RBCLK.

Image data R0 to R5 and G0 out of the 8-bit RGB data are extracted from the differential signal lines RA0/RB0, and image data G1 to G5 are extracted from the differential signal lines RA1/RB1. , B0 and B1 are extracted, and from the differential signal lines RA2/RB2, the image data B2 to B5, the DE signal (that is, the data valid signal ENAB), the VS signal and the HS signal are extracted, and the differential signal lines Similarly, image data G6, G7, B6, B7, R6 and R7 are extracted from RA3/RB3. As described above, the extracted VS and HS signals are not used.

Also, the dot clock DCK of the differential signal lines RACLK/RBCLK is supplied to the PLL circuit to generate an operation clock CK having the same frequency of 54 MHz as the dot clock DCK. This operating clock CK defines the internal operation of the liquid crystal controller LCD_CTL. The liquid crystal controller LCD_CTL controls image data corresponding to two RGB pixels (8 bits x 3 x 2) adjacent in the horizontal direction in the liquid crystal panel LCD. are collectively processed in synchronization with one operating clock CK.

Therefore, a pixel of 1280 (=640×2) dots in the horizontal direction will be processed in 11.85 μS (=640/54 MHz) of processing time corresponding to 640 operation clocks CK. Since the image data corresponding to one pixel is 1 byte long for each of RGB (gradation 2 ⁸ ×2 ⁸ ×2 ⁸ ), the image data of all pixels (1280 dots) constituting one line is is 3×1280 bytes long.

As shown in FIG. 13, the liquid crystal controller LCD_CTL has a source driver SDV that drives 1280 source signal lines with drive signals of 2 ⁸ (=256) gradations, and ON/OFF controls 1024 gate signal lines. It appropriately controls the gate driver GDV. Specifically, the liquid crystal controller LCD_CTL appropriately operates each unit based on the DE signal (data valid signal ENAB) extracted from the LVDS transmission line and the operation clock CK, thereby performing an image updating operation at a frame rate of 60 Hz. is realized.

Pixels of the liquid crystal panel LCD are each composed of basic pixels of RGB three colors, and the number of basic pixels corresponding to all pixels (1280 dots) for one line is 3×1280. It is configured by arranging 10 driver elements each having one output terminal. Image data DAT is sequentially supplied to these 10 driver elements from the liquid crystal controller LCD_CTL, and is appropriately transferred based on the start signal SP and the transfer clock DCLK. Then, in synchronization with the latch signal LT, analog-converted drive signals are supplied to 3840 source signal lines. As described above, the time required to update all pixels (1280 dots) of one line of the liquid crystal panel LCD is 11.85 μS (=640/54 MHz).

On the other hand, the liquid crystal controller LCD_CTL supplies the gate start signal GS and the gate clock signal GCLK to the gate driver GDV to update the gate signal lines to be driven. Here, the gate driver GDV is configured by arranging four driver elements having 256 output terminals.

The update timing of the gate signal line is defined based on the fall timing of the DE signal and the operating clock CK. (see FIG. 11). Also, based on the number of DE signals (1024), the gate signal line to be driven is reset to the initial state, the gate start signal GS is output at optimum timing, and the output of the gate clock signal GCLK is resumed. The vertical line feed cycle of the gate signal line is 42+1024 clocks in a typical value calculation, counted by the operation clock CK (see FIG. 11). However, as described above, in this embodiment, the liquid crystal display means 76 is operated with a design different from the typical value (see FIG. 19).

Next, returning to FIG. 10, the outline of the frame-side member 132 will be described. The frame-side member 132 is configured around a power supply board 126 and a payout firing control board 128 . The power supply board 126 receives AC 24V and outputs various DC voltages, and outputs DC 5V, DC 12V, and DC 35V to the payout launch control board 128, and DC 12V to the underframe LED connection board 139. In addition, the power supply relay board 136 DC5V, DC12V, and DC35V are output to the effect interface board 96 via. A backup board 147 is connected to the payout firing control board 128, and from the payout firing control board 128 to the main control board 93, in addition to DC5V, DC12V, and DC35V received from the power supply board 126, a backup power supply, a power failure Signals and the like are output via the main control relay board 135 .

In addition, the payout shooting control board 128 includes a shooting driving means 17d constituting the shooting means 17, an external terminal board 148 for outputting various information to an external host computer, etc., and a rental board for connecting an external game ball rental device. In addition to the device connection terminal plate 149, a frame relay board 150, a tray relay board 151, and the like are connected.

The frame relay board 150 relays the connection between the payout motor 32a, the payout counting switch 32b, the front door/inner frame open switch 152, etc. and the payout firing control board 128, which are arranged on the inner frame 6 side. Also, the tray relay board 151 relays the connection between the discharge connection board 153 on the front door 7 side, the clogged ball detection board 154, the frequency display board 155, etc. and the payout discharge control board 128. The firing connection board 153 is connected to the variable resistor 35a, the firing stop switch 35b, the touch sensor 35c, and the ball feeding solenoid 53c provided in the ball feeding unit 53a.

In addition to the lower speaker 18 on the inner frame 6 side, the frame lower LED connection board 139 is connected to the frame lower left LED connection board 156 on the front door 7 side. The lower left LED connection board 156 includes the LED boards 302a to 302d that make up the frame lamp 304, the handle LED board 158 that is arranged on the firing handle 35, the production button 41, and the production button LED to which the LED boards inside the production button 41 are connected. A connection board 159, a volume/light amount button board 160 to which the volume/light amount adjustment buttons 39 and 40 are connected, the upper speaker 25, a side unit relay board 161 to be connected to the side unit 30, and the like are connected.

Next, the circuit configurations of the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98 and the ROM board 99, which constitute the effect control section 95, will be described in detail with reference to FIGS.

As shown in FIG. 10, the effect interface board 96 reproduces audio signals based on instructions received from the CPU circuit 171 (FIG. 14) mounted on the composite chip 104 of the liquid crystal control board 98 in addition to various input/output buffers. an audio processor 101, an audio ROM 103 for storing compressed audio data or the like which is original data of an audio signal to be reproduced, a digital amplifier 102 for receiving an audio signal output from the audio processor 101, and the like. The audio processor 101 incorporates a WDT circuit that automatically resets the set value of the internal circuit to a default value when the internal circuit malfunctions, and an audio control register SRG. Based on the operation parameters received from the CPU circuit 171 , the audio ROM 103 is accessed to reproduce a necessary audio signal and output it to the digital amplifier 102 .

Various input/output buffers mounted on the effect interface board 96 include input buffers for receiving control commands CMD and strobe signals STB from the main control board 93 and transferring them to the composite chip 104 on the liquid crystal control board 98, frame LED An input buffer for receiving switch signals such as the effect button 41 via the relay board 137 and transferring them to the composite chip 104 of the liquid crystal control board 98, and a serial signal received from the liquid crystal control board 98 via the frame LED relay board 137 and an output buffer for transferring to a driver IC such as an LED board, and an LED connection board 134 for receiving a switch signal such as a position detection switch of a movable body and transferring it to the composite chip 104 of the liquid crystal control board 98 . There are an input buffer, an output buffer for transferring a serial signal received from the liquid crystal control board 98 to a driver IC such as an LED board via the LED connection board 134, and the like.

The liquid crystal control board 98 includes a composite chip (chip) 104 containing a CPU circuit 171, a VDP circuit 172, etc., a control ROM (ROM connected to the chip) 105 for storing a control program for the CPU circuit 171, and a large number of chips. A DRAM (Dynamic Random Access Memory) 106 etc. that can access the data at high speed is installed, and a ROM board 99 connected to the liquid crystal control board 98 stores a large amount of CG data necessary for control of the effect. CGROM 107 is mounted.

The control ROM 105 is located in the address space CS0 selected by the chip select signal CS0. The DRAM 106 is positioned in the address space CS5 selected by the chip select signal CS5.

FIG. 14 is a circuit block diagram showing the composite chip 104 mounted on the liquid crystal control board 98, including related circuit elements. As shown, the composite chip 104 includes a CPU circuit 171 that issues a display list DL at predetermined intervals, and a VDP circuit 172 that generates image data based on the issued display list DL and drives the liquid crystal display means 76. and are built-in. The CPU circuit 171 and the VDP circuit 172 are connected via a CPUIF circuit 173 that relays transmission/reception data between them.

The CPU circuit 171 frequency-multiplies (eg, 8-fold) the oscillation output (eg, 100/3 MHz) from the oscillator OSC1 received at the HCLKI terminal of the composite chip 104 to generate a CPU operating clock of about 266.7 MHz. Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby taking measures against EMI (Electromagnetic Interference) for preventing radio interference/electromagnetic interference.

On the other hand, the VDP circuit 172 frequency-multiplies the oscillation output (for example, 40 MHz) from the oscillator OSC2 received at the PLLREF terminal of the composite chip 104 as necessary, and converts it into the system clock of the VDP circuit 172 and the display for the display device. It is used as a clock (dot clock, etc.) and as a DDR clock for the external DRAM 106 . That is, the output of oscillator OSC2 functions as a reference clock for the entire VDP circuit 172. FIG.

Therefore, considering the importance of this reference clock, the oscillator OSC2 is operated at the same power supply voltage of 3.3 V as the VDP circuit 172, and the output enable terminal OE is at H level (=3.3 V). , a reference clock is oscillated, and when the power supply voltage of 3.3 V drops below a predetermined level, a non-maskable interrupt (NMI) is generated.

The composite chip 104 is also provided with an HBTSL terminal, and based on the logic level of this HBTSL terminal, a ROM for storing a boot program (initial setting program) to be executed after power-on (CPU reset) is specified. . As shown, in this embodiment, HBTSL is set to L, and zero address in the address space CS0 of the CPU circuit 171 is assigned to the control ROM 105. FIG.

The CPUIF circuit 173 is connected to a control ROM 105 for storing control programs and necessary control data in a non-volatile manner, and a work memory (RAM) 174 having a storage capacity of about 2M bytes. It is accessible from circuit 172 .

Control ROM 105 is located in address space CS0 selected by chip select signal CS0, and work memory 174 is located in address space CS6 selected by chip select signal CS6. In this work memory 174, a DL buffer BUF for temporarily storing a display list DL describing a series of instruction commands specifying one frame of the liquid crystal display means 76 is secured.

The CPU circuit 171 is a circuit having performance equivalent to that of a general-purpose one-chip microcomputer, and has an effect control CPU 181 that controls overall image effects based on the control program of the control ROM 105, and a storage capacity of about 16 kbytes. A built-in RAM 182 used as a work area for the CPU, a DMAC (Direct Memory Access Controller) 183 for realizing data transfer without going through the production control CPU 181, and a plurality of input ports Si and output ports So. An output port (SIO) 184, a parallel input/output port (PIO) 185 having a plurality of input ports Pi and output ports Po, a control register (REG) 186 in which setting values are set to control the operation of each of these parts, etc. It has

The parallel input/output port 185 is connected to an external device (effect interface board 96) via an input/output circuit 187 or the like. It receives a command CMD, an interrupt signal STB, and the like.

Next, the VDP circuit 172 will be described. Connected to the VDP circuit 172 are a CGROM 107 for storing compressed data that is a component of still images and moving images used for image effects, an external DRAM 106 having a storage capacity of about 4 Gbit, and a liquid crystal display means 76. there is In this embodiment, the DRAM 106 is composed of a DDR3 (Double-Data-Rate 3 SDRAM), and the CGROM 107 is composed of a flash SSD (solid state drive) made up of a NAND flash memory.

As shown in FIG. 14, the VDP circuit 172 includes a control register group 201 in which various operating parameters that define the operation of the VDP (Video Display Processor) can be set by the effect control CPU 181, and an image to be displayed on the liquid crystal display means 76. A built-in VRAM (video RAM) 202 of about 48 Mbytes used when generating data, a data transfer circuit 203 for executing data transmission/reception between each part inside the chip and data transmission/reception with the outside of the chip, and the built-in VRAM 202 are related to Source and An index table IDXTBL capable of specifying destination address information, a preloader 204 capable of executing a preload operation for READ access to the CGROM 107 prior to the drawing operation, and graphics for decoding (decoding/decompressing/decompressing) compressed data read from the CGROM 107. a video decoder (GDEC) 205; a rendering circuit 206 that generates image data for one frame of the liquid crystal display means 76 by appropriately combining still image data and moving image data after decoding (expanding); As a part, a geometry engine 207 that generates a stereoscopic image by appropriate coordinate transformation, and a plurality of systems that can read image data from the frame buffer FBa generated by the rendering circuit 206 and execute appropriate image processing in parallel, such as 3 systems (A/B/C) of display circuits 208A to 208C and an output selection unit 209 that appropriately selects the outputs of the 3 systems (A/B/C) of display circuits 208A to 208C, and the output selection unit 209 outputs an LVDS unit 210 for converting image data into an LVDS signal; an SMC unit 211 capable of serial data transmission/reception; a CPUIF unit 212 for relaying data transmission/reception with the CPUIF circuit 173; 213, a DRAMIF unit 214 for relaying data transmission/reception with the external DRAM 106, a VRAMIF unit 215 for relaying data transmission/reception with the built-in VRAM 202, and an audio circuit SND.

FIG. 15 shows the relationship between the CPUIF section 212, the CG bus IF section 213, the DRAMIF section 214 and the VRAMIF section 215, the control register group 201, the CGROM 107, the DRAM 106 and the built-in VRAM 202. FIG. As shown in the figure, the CG data acquired from the CGROM 107 is transferred to the preload area of the external DRAM 106 via the data transfer circuit 203 and the DRAM IF unit 214, for example, as preload data. Note that this preload operation is not essential, and the data transfer destination is not limited to the external DRAM 106, but may be the internal VRAM 202 as well. For example, when the preload operation is not executed, the CG data is transferred to the built-in VRAM 202 via the data transfer circuit 203 and VRAMIF section 215 .

By the way, the built-in VRAM 202 includes an area for decompressing compressed data read from the CGROM 107, a frame buffer area for storing image data specifying each ARGB information (32 bits=8×4) of W×H display pixels of the display device, and a Z-buffer area for storing depth information of each display pixel. In the ARGB information, A means 8-bit α-plane data, and RGB means 8-bit data of three primary colors.

Here, each area of the built-in VRAM 202 is indirectly accessed based on various instruction commands (textures, sprites, etc.) described in the display list DL by the effect control CPU 181. In the READ/WRITE access, Specifying the Destination address and Source address of the built-in VRAM 202 one by one is troublesome. Therefore, in this embodiment, in the initial processing after the CPU is reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as an index space) required for the drawing operation is secured, and an index number is assigned to each index space. This enables access based on index numbers.

Specifically, after resetting the CPU, the built-in VRAM 202 is roughly divided into three types of memory areas, and a necessary number of index spaces are secured in each memory area. By constructing an index table IDXTBL (see FIG. 16A) that stores index spaces and index numbers in association with each other, subsequent operations based on the index numbers are realized.

This index space needs to be (1) added after initial processing, and conversely (2) released. Therefore, when the addition/release effect control CPU 181 operates, a flag area FG that can determine whether or not it is the timing at which the addition/release processing can be performed, and whether or not the processing such as addition/release has actually been completed. are provided in the index table IDXTBL. The built-in VRAM 202 is roughly divided into three types of memory areas: two AAC areas (a1, a2), a page area (b), and an arbitrary area (c). , a2), (b) and (c), the index table IDXTBL is divided into three (FIG. 16(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are secured as the AAC area (a). It's okay to be alone. In the following description, the first and second AAC areas (a1, a2) may be collectively referred to as the AAC area (a).

In the case of this embodiment, the built-in VRAM 202 includes (a) an AAC area having an index space and its index number automatically assigned by internal processing and having a memory cache function, and (b) a two-dimensional space of, for example, 4096 bits×128 lines. The unit space can be divided into a page area in which an index space can be secured in the range of integral multiples thereof, and an arbitrary area in which (c) the top address (space top address) STx and the horizontal size Hx can be arbitrarily set. (See FIG. 16(b)). However, in order to facilitate the internal operation of the VDP circuit 172, the space start address STx of the index space arbitrarily set in the arbitrary area (c) has 0 in the lower 11 bits and has a predetermined number of bits (2048 bits=256 bytes). Must be in units.

Then, after resetting the CPU, the maximum value of the address space required for each and the area start address (lower 11 bits = 0) are defined, and the AAC area (a1), the second AAC area (a2), and the page area ( b) is secured, and the remaining memory area becomes an arbitrary area (c). In order to facilitate the internal operation of the VDP circuit 172, the maximum value of the address space of the AAC area is defined in units of 2048 bits, and the maximum value of the address space of the page area is an integral multiple of the unit space of 4096 bits×128 lines. be done.

Next, the necessary number of index spaces are set in each of the areas (a1, a2), (b), and (c) thus secured. When using the optional area (c), the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 256 bits in order to facilitate the internal operation of the VDP circuit 172. The vertical size is a fixed value (eg 2048 lines).

In any case, the first and second AAC areas (a1, a2) are automatically given an index space and an index number by the VDP circuit 172. Therefore, for example, the SETINDEX command, which is a texture setting command, can be used as the decoding destination. is specified in the AAC area (a), the TXLOAD (texture load) command that reads CG data from the CGROM 107 only needs to specify the source address of the CGROM 107 and the horizontal and vertical sizes after expansion (decoding). Become. Therefore, in the present embodiment, still images (textures) such as characters that temporarily appear during an announcement effect or the like and I-stream moving images are decoded to the AAC area (a).

This AAC area (a) is provided with a memory cache function. The decoded data cached in (a) can be utilized, and redundant READ accesses and decode processing can be suppressed. However, when the AAC area (a) is used up, the old data is automatically destroyed. Only specific textures that are used repeatedly are acquired in the second AAC area (a2).

Examples of repeatedly used textures include, for example, a character that appears repeatedly during a predetermined advance notice effect, and a background image when the background screen is composed of a still image. In such a case, the texture setting command SETINDEX command sets the decoding destination to the second AAC area (a2), and the TXLOAD command decodes the textures such as characters and background images to the second AAC area (a2). After that, the decoding result is protected by not using the second AAC area (a2).

Then, after specifying the decoding destination to the second AAC area (a2) with the SETINDEX command, executing the same TXLOAD command to reacquire the already acquired texture causes a cache hit for the already acquired texture. The time required for READ access to the CGROM 107 and decoding processing can be eliminated. Such a cache hit function is exhibited even in the preload data read ahead in the preload area, but the preload data that causes a cache hit in the preload area is compressed data before decoding, whereas the cache hit occurs in the AAC area. is the decompressed data after decoding.

By the way, the term “texture” generally refers to the texture of the surface of an object, the texture, etc. In this embodiment, the term “texture” refers to sprite image data that constitutes a still image, image data that constitutes one frame of a moving image, triangles, triangles, and so on. It is used as a concept including not only image data to be pasted onto drawing primitives such as rectangles, but also image data after decoding. When image data is copied inside the built-in VRAM 202 (hereinafter referred to as "move" for convenience), the texture setting command SETINDEX is used to set the source image data as a texture, and then the SPRITE command is issued. will be executed.

By executing the SPRITE command, the Source image data of the movement source is formally drawn in the virtual drawing space shown in FIG. 16(c). , and the index space that serves as the frame buffer can be set in advance using environment setting commands (SETDAVR, SETDAVF) and texture setting commands (SETINDEX). , the Source image data of the movement source is drawn in a predetermined index space (frame buffer) (see FIG. 16(c)).

In any case, in this embodiment, the built-in VRAM 202 is roughly divided into the AAC area (a1, a2), the page area (b), and the arbitrary area (c), and an appropriate number of index spaces can be secured for each area. , each index space is specified by an independent index number for each region (a), (b), and (c). The index number is, for example, 1 byte long, and the page area (b) (excluding the AAC area (a) automatically assigned by the internal circuit) and the arbitrary area (c) are controlled in the range of 0 to 255. The CPU 181 can freely assign index numbers.

Therefore, in this embodiment, as shown in FIG. 16(a), a pair of frame buffers FBa are secured in an arbitrary area (c) for the liquid crystal display means 76, and index numbers 255 and 254 are assigned to both of the double buffer structures. is given. That is, as a frame buffer FBa for the liquid crystal display means 76, an index space 255 and an index space 254 are secured which are toggled and used. Although not particularly limited, the index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of pixels in the horizontal direction of the liquid crystal display means 76 . Since each pixel is specified by 32-bit ARGB information, the horizontal size 1280 means 32×1280=40960 bits (a multiple of 256 bits).

The reason why the frame buffer FBa is secured in the arbitrary area (c) is that the arbitrary area (c) can be set to an arbitrary horizontal size as a multiple of 32 bytes (= 256 bits = 8 pixels). This is because if the number of horizontal pixels is matched with the number of horizontal pixels of the liquid crystal display means 76 as described above, the reserved area will not be wasted. On the other hand, in the page area (b), only horizontal/vertical sizes that are integral multiples of the unit space of 128 pixels×128 lines can be set. However, the vertical size of the two-dimensional index space secured in the arbitrary area (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area of horizontal size 1280×vertical size 1024 becomes an effective data area for the liquid crystal display means 76 .

Also, in this embodiment, when an additional index space (memory area) is secured in the arbitrary area (c) where the frame buffer FBa is secured, an index number starting from 0 is assigned. Although not limited in any way, in the present embodiment, as a work area for notice effect, in which a effect image composed of a character or other still image is made to appear in a part of the display screen in an appropriate rotational posture as necessary, An index space (0) is secured in an arbitrary area (c).

However, the use of a work area is not essential, and an index space as a work area may be secured in the page area (b) instead of the arbitrary area (c). If the page area (b) is used, it is possible to secure an index space with dimensions that are multiples of a square unit space of horizontal size 128 (=4096 bits)×vertical size 128, so it is suitable for handling small effect images.

By the way, in the present embodiment, the image effect is realized almost exclusively by moving images including the background image. In particular, during the variable effect, a large number (usually 10 or more) moving images are drawn simultaneously. Each of these moving images is stored in the CGROM 107 in a compressed state as a series of moving image frames. classified into Here, an I frame (Intra coded frame) means a frame in which an input image is directly compressed independently of other screens. On the other hand, a P-frame (Predictive coded frame) means a frame for which forward predictive coding is performed, and requires an I-frame or P-frame positioned in the past in terms of time.

Therefore, in the present embodiment, the IP stream moving image is developed in the page area (b) instead of the AAC area (a) where there is concern that the old data will be destroyed. That is, a large number of index spaces (IDX0 to IDXN) are secured in the page area (b) where index spaces of multiple dimensions of horizontal size 128 x vertical size 128 can be secured, and a series of video frames correspond to each video MVi. , the same index space IDXi is always used for decoding. That is, the moving picture MV1 is developed in the index space IDX1, the moving picture MV2 is developed in the index space IDX2, and similarly, the moving picture MVi is developed in the index space IDXi.

More specifically, the moving image MVi is specified in advance by the SETINDEX command that "the decoding destination of the IP stream moving image MVi is the index space (i) of the index number i in the page area (b)", A TXLOAD command is executed to acquire one moving image frame of the IP stream moving image MVi.

Then, one moving image frame (any of a series of moving image frames) on the CGROM 107 specified by the TXLOAD command is first acquired in the AAC area (a), and then automatically activated by the graphics decoder (GDEC) 205. One frame of the acquired moving image is decoded and developed in the index space (i) of the page area (b).

On the other hand, in this embodiment, I-stream moving pictures are handled in the same way as still pictures. Execute the TXLOAD command. As a result, the moving image frame is acquired in the first AAC area (a1), and then the automatically activated graphics decoder 205 develops decoded data in the first ACC area (a1). As explained above, the index space for the AAC area (a) is automatically generated, so there is no need to specify the index number. Note that the expansion volume required for the index space, that is, the horizontal size and vertical size of the decoded texture (video frame), can be determined by the TXLOAD command regardless of whether the expansion destination is the AAC area (a) or the page area (b). identified.

By the way, IP stream moving images MVi and I stream moving images MVj are generally composed of N moving image frames (I frames and P frames). Therefore, in the TXLOAD command, for example, the source address of the CGROM 107 in which the k-th (1≤k≤N) video frame is stored and the horizontal/vertical size after development are specified. Although not limited in any way, in this embodiment in which still images are hardly used, most of the 48 Mbyte address space (approximately 30 Mbytes) of the built-in VRAM 202 is allocated to the page area (b). In this embodiment, in which still images are hardly used, only the first AAC area (a1) is secured as the AAC area, and the second AAC area (a2) is not secured, and the cache hit function of the AAC area described above is used. do not use either.

It is also conceivable to provide a dedicated GDEC (graphics decoder) circuit in order to speed up the decoding process of compressed video data. If a dedicated GDEC circuit is incorporated in the VDP circuit 172, it is sufficient to instruct the GDEC circuit of the head address of the compressed moving image data in the decoding process of the compressed moving image data composed of N compressed moving image frames. It is no longer necessary to specify the start address for each of the N compressed video frames.

However, incorporating a plurality of such dedicated GDEC circuits for each compression algorithm further complicates the internal configuration of the VDP circuit 172 . Therefore, in this embodiment, software GDEC is used, and decoding processing is realized by software processing corresponding to each compression algorithm for data such as IP stream moving images, I stream moving images, still images, and other α values. The processing time difference between hardware processing and software processing does not matter much, and the processing time that matters is the access (READ) time from the CGROM 107 .

Returning to FIG. 14, the description continues. The data transfer circuit 203 is a circuit that performs a data transfer operation between a resource (storage medium) inside the VDP circuit and an external storage medium as a transfer source port or a transfer destination port in a DMA (Direct Memory Access) manner. is. FIG. 17 is a block diagram showing the internal configuration of this data transfer circuit 203 together with related circuit configurations.

As shown in FIG. 17, the data transfer circuit 203 is configured to transmit/receive data to/from the CGROM 107, DRAM 106 and built-in VRAM 202 via an integrated connection bus ICM having a router function. The CGROM 107 and DRAM 106 are accessed via the CG bus IF section 213 and the DMAM IF section 214 .

On the other hand, the CPU circuit 171 issues the display list DL to the rendering circuit 206 and the preloader 204 via the transfer port register TR_PORT incorporated in the data transfer circuit 203 . Note that the CPU circuit 171 and the data transfer circuit 203 are bidirectionally connected, but when the display list DL is issued, the transfer port register TR_PORT functions as a data write port that receives one unit of data forming the display list DL. do. Note that the write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus control unit 203d.

As shown, the effect control CPU 181 can WRITE access the transfer port register TR_PORT via the CPUIF unit 212, and when the DMAC circuit 183 is utilized, the DMAC circuit 183 directly WRITE accesses the transfer port register TR_PORT. will do. A series of instruction commands written in the transfer port register TR_PORT (that is, a series of instruction commands forming the display list DL) are processed in 32-bit units by a CPU bus control system having a built-in FIFO buffer with a FIFO structure (32 bits×130 stages). It is configured to be automatically stored in the section 203d.

In addition, this data transfer circuit 203 executes data transmission/reception operations on the transmission paths of three channels ChA to ChC, and has a FIFO buffer of FIFO structure (64 bits×N stages) ChA control circuit 203a (N=130 stages) ), a ChB control circuit 203b (N=1026 stages), and a ChC control circuit 203c (N=130 stages).

Then, the instruction command string (display list DL) accumulated in the CPU bus control unit 203d is transferred to the drawing circuit 206 or the preloader 204 based on the set value to the data transfer register RGij (a kind of the various control registers 201) by the effect control CPU 181. transferred to As indicated by arrows, the display list DL is transferred from the CPU bus control unit 203d to the drawing circuit 206 via the FIFO buffer of the ChB control circuit 203b, and transferred to the preloader 204 via the FIFO buffer of the ChC control circuit 203c. is configured as follows.

In this embodiment, the ChB control circuit 203b and the ChC control circuit 203c are specialized for the transfer operation of the display list DL. Each of them is transferred to the drawing circuit 206 or the display list analyzer of the preloader 204 as part of the display list DL via the FIFO buffer of the ChC control circuit 203c.

The drawing circuit 206 then starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 204 performs necessary preload operations based on the transferred display list DL. By the preload operation, the CG data of the CGROM 107 is read ahead into the preload area secured in the DRAM 106, and the display list DL (hereinafter referred to as the rewrite list DL') in which the source address of the texture is changed in relation to the TXLOAD command etc. is secured in the DRAM 106. DL buffer area BUF'.

On the other hand, the ChA control circuit 203a and the connection bus access arbitration circuit 203e function for data transfer between storage media such as the CGROM 107, the DRAM 106, and the built-in VRAM 202. FIG. In addition, the IDXTBL access arbitration circuit 203f functions when accessing the built-in VRAM 202 that requires the address information of the index table IDXTBL. Specifically, the ChA control circuit 203a, for example, (a) transfers the compressed data of the CGROM 107 to the internal VRAM 202, (b) preloads (reads ahead) the compressed data of the CGROM 107 and transfers it to the external DRAM 106, or , (c) functions when prefetch data in the preload area is transferred to the built-in VRAM 202 .

Here, the ChA control circuit 203a is configured to be able to operate in parallel with the ChB control circuit 203b and the ChC control circuit 203c. It can be executed in parallel with the transfer operation of the rewrite list DL'. Also, the ChB control circuit 203b and the ChC control circuit 203c can be executed simultaneously. However, since there is only one transfer port register TR_PORT, at the timing when one of the transfer port registers TR_PORT is used, the other (203c/203b) cannot access the transfer port register TR_PORT. Can not.

During operation of the ChA control circuit 203a, the connection bus access arbitration circuit 203e arbitrates data transmission with each storage element (CGROM 107, DRAM 106) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 203f arbitrates data communication with the built-in VRAM 202 by controlling the ChA control circuit 203a based on the index table IDXTBL. In the case of this embodiment in which the preloader 204 functions, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 106 is sent to the drawing circuit 206 via the connection bus access arbitration circuit 203e and the ChB control circuit 203b. transferred.

As described above, the data transfer circuit 203 of the present embodiment has a data transfer source arbitrarily selected from various storage resources and a data transfer destination arbitrarily selected from various storage resources. It provides high-speed data transfer between Note that the storage resources on which the data transfer circuit 203 functions include not only the built-in VRAM 202 but also external devices via the CPUIF section 212, the CG bus IF section 213, and the DRAMIF section 214. FIG.

Like the amount of data to be acquired from the CGROM 107 at one time (memory sequential READ), the amount of data transferred to and from an external device in which the ChA control circuit 203a functions is determined by the display in which the ChB control circuit 203b and the ChC control circuit 203c function. Compared to the case of the list DL, it is enormous, and the amount of data transfer is greatly different from each other.

Here, it is conceivable that the unit data amount and the total transfer data amount can be finely set for these various data transfers. be. Therefore, in this embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total transfer data amount is limited to be an integral multiple of the minimum data amount DTmin, thereby achieving high-speed and smooth data transfer operations. is doing. Although not particularly limited, in the data transfer circuit 203 of this embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total transfer data amount is limited to integral multiples of this.

Therefore, the instruction command string of the display list DL accumulated in the FIFO buffer of the CPU bus control unit 203d for each 32 bits is transferred to the ChB control circuit 203b and the ChC control circuit 203b at the timing when the total amount reaches the minimum data amount Dmin. , is accumulated in each FIFO buffer.

The display list DL consists of a series of instruction commands. In this embodiment, the display list DL has a command length of 32 bits integer N times ( (N>0)). Therefore, the drawing circuit 206 and the preloader 204 that receive the display list DL instruction command via the data transfer circuit 203 can quickly and smoothly start command analysis processing (DL analyze). It should be noted that the command length of 32-bit integer N times does not necessarily mean that all of them are significant bits, but that it is 32-bit integer N times including non-significant bits (Don't care bits).

Next, preloader 204 will be described. The preloader 204 is a circuit that interprets the display list DL transferred from the data transfer circuit 203 (ChC control circuit 203b) and transfers the CG data on the CGROM 107 referenced by the TXLOAD command to the preload area of the DRAM 106 in advance. be. The preloader 204 also stores the rewrite list DL' in which the reference destination of the CG data is rewritten to the address after the transfer in the DL buffer BUF' of the DRAM 106 in relation to this TXLOAD command. Note that the DL buffer BUF' and the preload area are secured in advance during the initial processing after resetting the CPU.

The rewrite list DL' is sent to the display list analyzer (DL Analyzer) of the drawing circuit 206 via the connection bus access arbitration circuit 203e and the ChB control circuit 203b of the data transfer circuit 203 when the drawing operation of the drawing circuit 206 is started. transferred. The drawing circuit 206 then executes the drawing operation based on the rewrite list DL'. Therefore, based on the TCLOAD command or the like, the CG data that should originally be obtained from the CGROM 107 is obtained from the preload area of the DRAM 106 as preload data preloaded in the preload area. In this case, the preload data can be used repeatedly as long as it is not overwritten, and the preload data hit in the preload area is reused repeatedly.

In this embodiment, since the preload area is set in the external DRAM 106 having a sufficient storage capacity, the above cache hit function works effectively. Also, since the external DRAM 106 has a large storage capacity, it is possible to preload multiple frames of CG data at once, for example. That is, regarding the operation period of the preloader 204, the operation period of a series of preload operations including the read-ahead operation of CG data can be appropriately set within the range of integral multiples of the operation period δ during the intermittent operation of the VDP circuit 172. Multiple preloads are implemented.

However, in the following description, for the sake of convenience, a configuration without multiple preloads will be described, so the preloader 204 of this embodiment completes the preload operation for one frame during one operation period (δ). In this embodiment, the intermittent operation period δ of the VDP circuit 172 is 1/30 second, which is twice the period of the vertical synchronization signal of the liquid crystal display means 76 .

Next, the rendering circuit 206 sequentially analyzes the instruction command strings of the display list DL and the rewrite list DL' transferred via the data transfer circuit 203, and cooperates with the graphics decoder 205, the geometry engine 207, and the like. , and draws an image for one frame on the liquid crystal display means 76 in a frame buffer formed in the VRAM 202 .

As described above, when the preloader 204 is to function, the reference destination of the CG data of the rewrite list DL' is not the CGROM 107 but the preload area set in the DRAM 106. FIG. Therefore, sequential access to CG data that occurs during execution of drawing by the drawing circuit 206 can be executed quickly, and high-resolution moving images with rapid motion can be drawn without problems. That is, according to the present embodiment, it is possible to use an inexpensive SATA module as the CGROM 107 and execute complex and advanced image effects.

By the way, regardless of whether the preloader 204 is activated or not, the rendering circuit 206 cannot detect data garbled during the transfer of the display list DL and the rewrite list DL'. In addition, it is possible that the drawing circuit 206 freezes due to noise or the like, and the READ/WRITE access to the built-in VRAM 202 stops abnormally. Therefore, in this embodiment, when the drawing circuit 206 detects an irrational instruction command (analyze-disabled bit arrangement) or when there is no READ/WRITE access to the built-in VRAM 202 for a certain period of time, a drawing abnormal interrupt is generated. (drawing error interrupt is enabled).

Next, as described with reference to FIG. 16, the frame buffer FB secured in the arbitrary area (c) of the VRAM 202 is a double buffer divided into a drawing area and a readout area. to use. In addition, in this embodiment, one liquid crystal display means 76 is connected, so as shown in FIG. 16, one section of frame buffer FBa is secured. Therefore, the drawing circuit 206 draws image data for one frame in the drawing area (writing area) of the frame buffer FBa for the liquid crystal display means 76 .

The display circuits 208A to 208C are circuits that read the image data in the frame buffers FBa to FBc, perform final image processing, and output the data (see FIG. 18). The final image processing includes, for example, scaler scaling processing for enlarging/reducing the image, subtle color correction processing, and dithering processing for minimizing the quantization error of the entire image. Digital RGB signals (total of 24 bits) that have undergone these image processes are normally output together with the horizontal synchronizing signal HS and the vertical synchronizing signal VS.

As shown in FIG. 18, in this embodiment, three systems of display circuits A/B/C that execute the above operations in parallel are provided. The image data of FBa/FBb/FBc are read out and the final image processing described above is executed. However, since there is only one display device in this embodiment, the frame buffers FBb and FBc are not secured, and the display circuits 208B and 208C do not function.

Here, when confirming the specifications of the liquid crystal display means 76, the liquid crystal display means 76 transmits odd-numbered pixels (ODD) and even-numbered pixels (EVEN) adjacent in the horizontal direction through separate LVDS (Low Voltage Differential Signaling) transmission lines. It must be received by the receiver RV (RVa, RVb). Further, the frequency of the dot clock DCK of the liquid crystal display means 76 must be about 40 to 70 MHz (typical value is 54 MHz). It is necessary to set the vertical waiting time WTh/WTv. Furthermore, at the timing of outputting the image data (ODD/EVEN signal) to the liquid crystal display means 76, it is necessary to output the active level data enable signal ENAB.

Therefore, the display circuit 208A needs to output a signal that satisfies all the above specifications. 19(a) to 19(e) illustrate various signals output from the display circuit 208A. First, it is necessary to determine the frequency of the dot clock DCK. In this embodiment, the liquid crystal display means 76 is operated with the operation clock CK having a typical value of 54 MHz. dot clock DCK is 108 MHz (=54×2).

In a display panel LCD of 1280 dots wide by 1024 lines long (see FIG. 19(f)), two pixels adjacent to each other on the left and right are processed at once in synchronization with the operating clock CK of 54 MHz, so the clock frequency is substantially 108 MHz. This is because it is equivalent to operating with the dot clock DCK of .

Various operating parameters that define the operation of the display circuit 208A are defined based on the dot clock DCK having a frequency of 108 MHz. First, it is necessary to set the horizontal/vertical standby time WTh/WTv so that (WTh+640)×(WTv+1024)/54 MHz≈1/60 second. , (WTh+1280)×(WTv+1024)/108 MHz≈1/60 second.

Moreover, it is necessary to consider the permissible range of the specifications of the liquid crystal display means 76 for the waiting times WTh/WTv in the horizontal/vertical directions. Therefore, in the present embodiment, the horizontal waiting time WTh is counted by the dot clock DCK of 108 MHz and is set to 382 clocks, and the vertical waiting time WTv is set to 59 lines. Therefore, the time required to update the image of one frame is (382+1280)×(59+1024)/108 MHz=16.666 mS, and the frame rate is 1/60 second.

Corresponding to this setting, in the image updating operation of each line, the data valid signal ENAB is at L level during the standby time WTh (=382/108 MHz) corresponding to 382 clocks, and thereafter, in the active interval corresponding to 1280 clocks. (=1280/108 MHz) becomes active (H) level (FIG. 19(c)). As shown in FIGS. 19(d) and 19(e), during the active period of the data valid signal ENAB, the image updating operation is completed in a predetermined time (11.85 μS=1280/108 MHz) for pixels of 1280 dots per line. The image data is output so as to That is, 1280 pixel data are output in synchronization with 1280 dot clocks DCK. Since a full-color image with a gradation of 2 ⁸ ×2 ⁸ ×2 ⁸ is displayed on the liquid crystal display means 76, the pixel data of one pixel has a 3×8 bit length.

By the way, in this embodiment, the liquid crystal display means 76 outputs the vertical synchronizing signal VS and the horizontal synchronizing signal HS, although they are not required. The vertical synchronizing signal VS is output within the vertical standby time WTv, and the horizontal synchronizing signal HS is output within the horizontal standby time WTh. Note that FIGS. 19A and 19B show respective operating cycles for convenience of understanding. Also, in FIG. 19(f), the upper left and lower right vertices of the rectangular frame specified by TH×TV (=1083×1662 clocks) are marked with circles to indicate “start of display operation” and “start of display operation”, respectively. "end of", but this ◯ sign means "start of V-blank" which starts every 1/60th of a second. Since the 1083×1662 clock that defines the display operation coincides with 1/60 second, the elapsed time from "start of display operation" to "end of display operation" is 1/60 second.

Returning to FIG. 18, the output selection unit 209 of the present embodiment divides the output signal of the display circuit 208A into dual links that divide the 108 MHz dot clock DCK by two, and divides the LVDS unit 210a and the dual links into dual links. It is transmitted to the LVDS section 210b (see FIGS. 18 and 13). Each of the LVDS sections 210a and 210b converts the image data (24-bit digital RGB signals in total) into first and second LVDS signals, and adds a pair of clock signals (54 MHz=108/2) for transmission to the first and second LVDS signals. All five pairs of differential signals LVDS1 and LVDS2 are output to the liquid crystal display means 76 via two paths (see FIGS. 18 and 12).

As described above, in the liquid crystal display means 76, the ODD signal for one pixel and the EVEN signal for one adjacent pixel are processed at the same timing. 208A matches the 108 MHz dot clock DCK output.

By the way, in the case of this embodiment, the display circuits 208A to 208C are provided with underrun counters URCNTa to URCNTc for counting underrun abnormalities in which the generation of display data is not in time for the display timing (see FIG. 18). . The counter values of the underrun counters URCNTa to URCNTc are automatically added for each VBLANK when an underrun abnormality occurs.

Next, an SMC (Serial Management Controller) unit 211 is a composite controller containing an LED controller and a Motor controller. Then, it outputs an LED drive signal and a motor drive signal in synchronization with the clock signal to the LED/Motor driver (driver IC with a built-in shift register) mounted on the external board, while outputting a latch pulse at an appropriate timing. configured as possible.

Regarding the internal circuit of the VDP circuit 172 and its operation, the contents of the operation to be executed by the internal circuit are defined by the operation parameters (set values) set in the control register group 201 by the effect control CPU 181, and the execution state of the VDP circuit 172 can be specified by reading the operation status value of the control register group 201 . The control register group 201 means a large number of VDP registers RGij mapped in an address space (0 to FFFFFH) of about 1 Mbyte on the memory map of the effect control CPU 181. WRITE (setting) of operation parameters and READ operation of operation status values are executed via (see FIG. 15).

As shown in FIG. 15, the control register group 201 (VDP register RGij) includes a "system control register" in which initial setting values related to system operations such as interrupt operations are written, and the built-in VRAM 202 includes an AAC area (a) and a page area ( "Index table register" for determining b) and constructing or changing the index table IDXTBL, setting values regarding data transfer processing by the data transfer circuit 203 between the effect control CPU 181 and the internal circuit of the VDP circuit 172, etc. A "data transfer register" to be written, a "GDEC register" for specifying the execution status of the graphics decoder 205, a "drawing register" to which instruction commands and setting values relating to the drawing circuit 206 are written, and a "drawing register" for the operation of the preloader 204. A "preloader register" in which setting values are written, a "display register" in which setting values relating to the operation of the display circuit 208 are written, and an "LED control register" in which setting values relating to the LED controller (SMC unit 211) are written. , a "motor control register" in which setting values relating to the Motor controller (SMC unit 211) are written, and a "voice control register SRG" in which setting values relating to the audio circuit SND are written. However, in this embodiment, the audio circuit SND is not utilized.

In any case, the effect control CPU 181 controls the internal operation of the VDP circuit 172 by writing an appropriate set value to a predetermined VDP register RGij. Specifically, the effect control CPU 181 realizes a predetermined image effect based on a display list DL updated at appropriate time intervals and a set value in a predetermined VDP register RGij. In this embodiment, since the effect control CPU 181 is in charge of lamp effects and motor effects, the VDP register RGij also includes an LED control register and a motor control register.

Next, details such as wiring patterns of the liquid crystal control board 98 and the liquid crystal interface board 97 that constitute the effect control section 95 will be described. First, the liquid crystal control board 98 will be explained.

The liquid crystal control board 98 has a plurality of wiring layers on a board body 190 (see FIG. 8). 1st to 6th wiring layers La1 to La6 (FIGS. 20 to 25) consisting of 6 wiring layers La6 and 2nd to 5th wiring layers La2 to La5 arranged therebetween. there is The second wiring layer La2 (FIG. 21) is a solid wiring layer connected to the ground, and the fifth wiring layer La5 (FIG. 24) is a solid wiring layer connected to the power supply. In addition, a large number of vias (interlayer conduction portions) are provided in the substrate body 190 of the liquid crystal control substrate 98 in the board thickness direction, and a plurality of wiring layers La1 to La6 are connected to each other through these vias (interlayer conduction portions). Conducted. The vias used in this embodiment are plated through-hole type vias that penetrate from the front surface (first surface) 98a of the substrate body 190 to the rear surface (second surface) 98b.

20 to 25, the horizontal direction is the X direction, and the vertical direction is the Y direction. +X/−X directions (sides) are the rightward/leftward directions, and +Y/−Y direction (sides) are the upward/downward directions. The diagonal directions are also expressed as diagonal +XY direction and diagonal -XY direction. 7 and 8, when the liquid crystal control board 98 is attached to the main body 1 of the game machine, the +X direction of the liquid crystal control board 98 faces upward, and the +Y direction of the liquid crystal control board 98 faces rightward toward the main body 1 of the game machine. (facing left when viewed from the back).

As shown in FIG. 20, in the first wiring layer (A wiring layer) La1 on the side of the surface 98a, a composite chip placement area (first placement area) 191 in which a composite chip (first electronic component) 104 is placed, A control ROM placement area (second placement area) 192 in which the control ROM (second electronic component, specific electronic component) 105 is placed is provided. The composite chip arrangement area 191 has a substantially square shape corresponding to the shape of the composite chip 104 and is arranged near the central portion of the surface 98 a of the liquid crystal control substrate 98 . In the composite chip arrangement area 191, dot-shaped terminal connection portions corresponding to respective terminals of the composite chip 104 are arranged in a matrix at approximately equal intervals. The composite chip 104 has a total of 1020 terminals arranged in 32 rows and 32 columns (4 corners are missing) on the bottom side, and each terminal is connected to a corresponding terminal connection portion. It is attached to the composite chip placement area 191 in this state.

The control ROM placement area 192 has a substantially rectangular shape elongated in the Y direction corresponding to the shape of the ROM socket 193 (see FIG. 8) in which the control ROM 105 is mounted. It is about the same as The control ROM arrangement area 192 is arranged in the vicinity of the +X side with respect to the composite chip arrangement area 191, and the first and second edges 192a which are the long sides of the control ROM arrangement area 192 on the -X side and the +X side. , 192b is the first edge 191a among the first to fourth edges 191a to 191d on the +X side, −Y side, −X side, and +Y side of the composite chip placement area 191. , and are offset in the -Y direction and opposed to each other at a predetermined distance.

In the control ROM arrangement area 192, a plurality of (here, 35 each) terminal connection portions (ROM terminal connection portions) are arranged along both long sides, that is, along the first and second edges 192a and 192b. ing. A ROM socket 193 for detachably supporting the control ROM 105 is fixed in the control ROM arrangement area 192, and the control ROM 105 is detachably mounted in the ROM socket 193 (FIG. 8). The control ROM 105 has a plurality of terminals (here, 35 terminals each) arranged along both ends thereof, and each terminal is connected to each terminal connection part of the control ROM arrangement area 192 via the ROM socket 193 . It is connected.

As shown in FIG. 8, the ROM socket 193 detachably holds a substantially rectangular bottom wall 193a corresponding to the control ROM arrangement area 192 and both edges of the control ROM 105 mounted on the bottom wall 193a. The bottom wall 193a is fixed to the surface 98a of the liquid crystal control board 98 so as to cover substantially the entire control ROM arrangement area 192. As shown in FIG. Therefore, the wiring patterns (such as vias) in the control ROM arrangement area 192 in the first wiring layer La1 are shielded by the bottom wall (shielding wall) 193a of the ROM socket 193 even when the control ROM 105 is removed from the ROM socket 193. It cannot be visually recognized from the outside. This makes it possible to increase the preventiveness against fraudulent acts such as unauthorized modification of the wiring pattern connecting the composite chip 104 and the control ROM 105 . By drawing wiring patterns in the control ROM arrangement area 192, wiring space can be secured in other areas.

Further, as shown in FIG. 25, the sixth wiring layer (B wiring layer) La6 on the back surface 98b side has a first connector arrangement area 194 in which the liquid crystal control first connector CN31 is arranged and a liquid crystal control second connector CN32. A second connector placement area 195 is provided. The first connector arrangement area 194 has a substantially rectangular shape elongated in the X direction, and is arranged near the edge on the +Y side of the rear surface 98 b of the liquid crystal control board 98 . In the first connector arrangement area 194, a plurality of (here, 70 pieces each) terminal connection portions corresponding to the respective terminals of the liquid crystal control first connector CN31 are arranged along a pair of long sides. The second connector arrangement area 195 has a substantially rectangular shape elongated in the X direction, and is arranged in the vicinity of the −Y side edge of the rear surface 98 b of the liquid crystal control board 98 . In the second connector arrangement area 195, a plurality of (here, 50 pieces each) terminal connection portions corresponding to the respective terminals of the liquid crystal control second connector CN32 are arranged along a pair of long sides.

Among all the terminals of the composite chip 104 , the terminals connected to the control ROM 105 are arranged intensively in the vicinity of the first edge 191 a on the control ROM 105 side in the composite chip placement area 191 . FIG. 26 shows the types (terminal information) of some terminals in the vicinity of the first edge 191a and in the vicinity of the second edge 192b among all the terminals of the composite chip 104. FIG. The arrangement of each terminal in FIG. 26 matches the arrangement of the terminal connection portions in the composite chip arrangement area 191 in FIG.

In FIG. 26A, HAD0 to HAD25 are address output terminals for outputting address information, HDT0 to HDT15 are data input/output terminals for inputting/outputting data information, and HCS0 is a chip for outputting a chip select signal. A select output terminal, HRD a read strobe output terminal for outputting a read strobe signal, and HRESET a system reset terminal for inputting a system reset signal.

In FIG. 26B, RA0+ and RA0- are data output terminals corresponding to the differential signal line RA0 on the side of the first transmission line LVDS1, and RA1+ and RA1- are the differential signal lines on the side of the first transmission line LVDS1. Data output terminals corresponding to RA1, RA2+ and RA2- are data output terminals corresponding to the differential signal line RA2 on the side of the first transmission line LVDS1, and RA3+ and RA3- are the differential signal lines on the side of the first transmission line LVDS1. Data output terminals corresponding to RA3, RACLK+ and RACLK- are clock output terminals corresponding to the differential signal line RACLK on the side of the first transmission line LVDS1, and RB0+ and RB0- are the differential signal lines on the side of the second transmission line LVDS2. Data output terminals corresponding to RB0, RB1+, RB1- are data output terminals corresponding to the differential signal line RB1 on the side of the second transmission line LVDS2, and RB2+, RB2- are differential signal lines on the side of the second transmission line LVDS2. Data output terminals RB3+ and RB3- corresponding to RB2 are data output terminals corresponding to the differential signal line RB3 on the side of the second transmission line LVDS2, and RBCLK+ and RBCLK- are the differential signal lines on the side of the second transmission line LVDS2. A clock output terminal corresponding to RBCLK.

In the following description, the terminal symbols HAD0 to HAD25, HDT0 to HDT15, RA1+, RA1-, RBCLK+, RBCLK-, etc. of the corresponding terminals of the composite chip 104 are used as they are for the terminal connection portions in the composite chip placement area 191. do. For example, the terminal connection portion HRD indicates the terminal connection portion corresponding to the read strobe output terminal HRD.

FIG. 27 also shows the type (terminal information) of each terminal of the control ROM 105 . 27, A0 to A24 are address input terminals for inputting address information, Q0 to Q15 are data input/output terminals for inputting/outputting data information, and address output terminals of the composite chip 104, respectively. , are connected to the data input/output terminals. CE# is a chip select input terminal for inputting a chip select signal and is connected to the chip select output terminal of the composite chip 104 . WE# is a writable input terminal, and by connecting it to the power supply and keeping it at H level, it is possible to switch the mode according to the value (H/L) of the OE# terminal. OE# is an output enable input terminal and is connected to the read strobe output terminal of the composite chip 104 .

RESET# is a reset terminal, which is connected to a power supply voltage monitoring integrated circuit (reset IC) together with a system reset input terminal HRESET of the composite chip 104 . WP#/ACC is a write prohibition/program input terminal, and by connecting it to the ground (L level) or power supply (H level), it is possible to switch between write prohibition/permission and program execution prohibition/permission. there is In this embodiment, the WP#/ACC terminal is connected to the power supply and set to H level. BYTE# is an 8/16-bit mode selection terminal, and by connecting it to the ground (L level) or power supply (H level), it is possible to select either the 8-bit communication mode or the 16-bit communication mode.

In the following description, for the terminal connection portions corresponding to the control ROM arrangement area 192, the symbols A0 to A24, Q0 to Q15, CE#, etc. of the corresponding terminals of the control ROM 105 are used as they are. For example, the terminal connection portion RESET# indicates the terminal connection portion corresponding to the reset terminal RESET#.

Plural types of wiring paths P1 connecting the composite chip 104, the control ROM 105, the liquid crystal control first connector CN31, the liquid crystal control second connector CN32, etc. among the many wiring paths provided on the liquid crystal control board 98 are described below. Focusing on P71, the details thereof will be described with reference to the drawings. 28 to 33 show only the portions forming the wiring paths P1 to P71 from the wiring patterns of the first to sixth wiring layers La1 to La6 shown in FIGS. 20 to 25, respectively. , and FIGS. 34 to 44 are partially enlarged views thereof. 45 to 53 schematically show the wiring routes of the wiring paths P1 to P71. 45 to 50, vias displayed in gray (for example, via v86 in wiring path P1 in FIG. 45) indicate vias (specific inter-layer conductive portions) arranged in control ROM arrangement area 192, and are indicated by thick lines. (for example, wiring path cp13 in wiring path P2 in FIG. 45) indicated by .

First, wiring paths P1 to P26 connected to address output terminals HAD0 to HAD25 of composite chip 104 will be described. In this embodiment, among the address output terminals HAD0 to HAD25, HAD1 to HAD25 are connected to the address input terminals A0 to A24 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31. On the other hand, the address output terminal HAD0 is connected to the liquid crystal control first connector CN31, but is not connected to the terminal on the control ROM 105 side.

Comparing the arrangement of the address output terminals HAD1 to HAD25 of the composite chip 104 (FIG. 26A) with the arrangement of the corresponding address input terminals A0 to A24 of the control ROM 105 (FIG. 27) clearly shows that are different. That is, the address output terminals HAD1 to HAD25 of the composite chip 104 are arranged in six rows as shown in FIG. On the other hand, the address input terminals A0 to A24 of the control ROM 105 are arranged in two columns as shown in FIG. 27, and the arrangement order in each column is not regular. In addition, the arrangement positions of the composite chip 104 and the control ROM 105 and the number of wiring patterns are related to each other, so that the routing of the wiring patterns becomes very complicated. Therefore, it is very important to optimize the routing of the wiring pattern that connects the composite chip 104 and the control ROM 105. This makes it possible to shorten the length of the wiring pattern, thereby reducing noise and slimming down the entire board. It leads to plan. The same applies not only to the relationship between the composite chip 104 and the control ROM 105, but also to the relationship between the composite chip 104 and electronic components such as various connectors. In particular, the wiring pattern connected to a plurality of electronic components such as the composite chip 104 such as HAD1 to HAD25 and HDT1 to HDT25, the control ROM 105, and various connectors poses a great deal of the above-mentioned problems, so the effect of optimization is great. become a thing.

Among the wiring paths P1 to P26, in the wiring path P1 (FIG. 45), as shown in FIG. It is connected to the via v0 arranged in the vicinity in the diagonal -XY direction. The via v0 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD0) arranged around it. As shown in FIG. 37, this via v0 is connected to a via v41 by a wiring path cp1 provided in the third wiring layer La3. This via v41 is arranged between the composite chip placement area 191 and the control ROM placement area 192 . As shown in FIG. 40, the via v41 is connected to a via v86 arranged in the control ROM arrangement region 192 by a wiring path cp2 provided in the fourth wiring layer La4. Thus, the wiring path drawn out from the terminal connection portion HAD0 in the first wiring layer La1 is connected to the via v86 in the control ROM placement area 192 via the two wiring layers La3 and La4.

The wiring path extending from the terminal connection portion HAD0 to the via v86 branches into two at the via v86. As shown in FIGS. 37 and 38, the first branch path extends from the via v86 through the via v205 constituting the test point TP28 to the first connector placement region 194 by the wiring path cp3 provided in the third wiring layer La3. 42, is connected to the terminal connection portion had0 from inside the first connector placement region 194 by a wiring path cp4 provided in the sixth wiring layer La6, as shown in FIG. . Also, as shown in FIG. 41, the second branch path is connected from the via v86 to the terminating resistor RA16 by the wiring path cp5 provided in the sixth wiring layer La6. The termination resistor RA16 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

In the wiring path P2 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD1 provided in the composite chip placement region 191 of the first wiring layer La1 is connected to the vicinity of the diagonal -XY direction by the wiring path cp11. is connected to the via v5 located in the . The via v5 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD1) arranged around it. As shown in FIG. 40, this via v5 is connected to a via v85 arranged in the control ROM arrangement region 192 by a wiring path cp12 provided in the fourth wiring layer La4. In this way, unlike the wiring path drawn from the terminal connection portion HAD0, the wiring path drawn from the terminal connection portion HAD1 does not pass through the third wiring layer La3, but passes through the fourth wiring layer La4. It is connected to via v85 in region 192 .

The wiring path extending from the terminal connection portion HAD1 to the via v85 branches into four at the via v85. As shown in FIG. 35, the first branch path is connected from the via v85 to the terminal connection portion A0 of the control ROM 105 from inside the control ROM placement area 192 by the wiring path cp13 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v85 to the terminating resistor RA16 by the wiring path cp14 provided in the sixth wiring layer La6.

As shown in FIGS. 37 and 38, the third branch path is connected from the via v85 to the via v145 in the first connector placement area 194 by the wiring path cp15 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp16 provided in the sixth wiring layer La6 is connected to the terminal connection part had1 from inside the first connector arrangement area 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v85 to the via v182 by the wiring path cp17 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp18 provided in the sixth wiring layer La6 is connected to a decoder IC12 forming a decoding circuit.

Although partially omitted in the wiring diagrams such as FIG. 43, the decoding circuit including the decoders IC12 to IC14 is configured as shown in FIG. As shown in FIG. 54, the decoders IC13 and IC14 are connected to the liquid crystal display means 76 and the like via the liquid crystal IF third connector CN23 and the like. Data information is entered. Since the decoders IC13 and IC14 output data information to the liquid crystal display means 76 and the like based on the clock synchronized with the CPU input from the decoder IC12, the CPU does not need to transmit fixed data information each time. This eliminates the need to output the same data information from the CPU every predetermined time, and the CPU only needs to transmit new data information when the content of the data information is changed, thus simplifying the control program. become possible.

In the wiring path P3 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD2 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp21. It is connected to the placed via v4. The via v4 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD2) arranged around it. As shown in FIG. 40, the via v4 is connected to a via v84 arranged in the control ROM arrangement area 192 by a wiring path cp22 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD2 to the via v84 branches into four at the via v84. As shown in FIG. 35, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v84 to the terminal connection portion A1 of the control ROM 105 by the wiring path cp23 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v84 to the terminating resistor RA16 by the wiring path cp24 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v84 to the via v144 in the first connector placement area 194 by the wiring path cp25 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp26 provided in the sixth wiring layer La6 is connected to the terminal connection part had2 from inside the first connector arrangement area 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v84 to the via v184 by the wiring path cp27 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp28 provided in the sixth wiring layer La6 is connected to the decoder IC12 constituting the decoding circuit.

In the wiring path P4 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD3 provided in the composite chip placement region 191 of the first wiring layer La1 is obliquely adjacent to the +XY direction by the wiring path cp31. It is connected to the placed via v13. The via v13 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD3) arranged around it. As shown in FIG. 40, the via v13 is connected to a via v83 arranged in the control ROM arrangement region 192 by a wiring path cp32 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD3 to the via v83 branches into four at the via v83. As shown in FIG. 35, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v83 to the terminal connection portion A2 of the control ROM 105 by the wiring path cp33 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v83 to the terminating resistor RA16 by a wiring path cp34 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v83 to the via v143 in the first connector placement area 194 by the wiring path cp35 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp36 provided in the sixth wiring layer La6 is connected to the terminal connection part had3 from inside the first connector arrangement area 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v83 to the via v181 by the wiring path cp37 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp38 provided in the sixth wiring layer La6 is connected to the decoder IC12 constituting the decoding circuit.

In the wiring path P5 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD4 provided in the composite chip arrangement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp41. It is connected to the placed via v20. The via v20 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD4) arranged around it. As shown in FIG. 40, the via v20 is connected to a via v82 arranged in the control ROM arrangement region 192 by a wiring path cp42 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD4 to the via v82 branches into three at the via v82. As shown in FIG. 35, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v82 to the terminal connection portion A3 of the control ROM 105 by the wiring path cp43 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v82 to the terminating resistor RA15 by a wiring path cp44 provided in the sixth wiring layer La6. The terminating resistor RA15 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

As shown in FIGS. 37 and 38, the third branch path is connected from the via v82 to the via v142 in the first connector placement area 194 by the wiring path cp45 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp46 provided in the sixth wiring layer La6 is connected to the terminal connection part had4 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P6 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD5 provided in the composite chip placement area 191 of the first wiring layer La1 is arranged outside the composite chip placement area 191 by the wiring path cp51. Specifically, it is connected to the via v34 arranged between the composite chip placement area 191 and the control ROM placement area 192 . Note that the terminal connection portion HAD5 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . As shown in FIG. 40, the via v34 is connected to the via v81 arranged in the control ROM arrangement region 192 by a wiring path cp52 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD5 to the via v81 branches into three at the via v81. As shown in FIG. 35, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v81 to the terminal connection portion A4 of the control ROM 105 by the wiring path cp53 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v81 to the terminating resistor RA15 by a wiring path cp54 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v81 to the via v141 in the first connector placement area 194 by the wiring path cp55 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp56 provided in the sixth wiring layer La6 is connected to the terminal connection part had5 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P7 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD6 provided in the composite chip placement area 191 of the first wiring layer La1 is arranged outside the composite chip placement area 191 by the wiring path cp61. Specifically, it is connected to the via v39 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection portion HAD6 is arranged on the outermost side of the composite chip arrangement area 191 . As shown in FIG. 40, the via v39 is connected to the via v80 arranged in the control ROM arrangement area 192 by a wiring path cp62 provided in the fourth wiring layer La4.

A wiring path extending from the terminal connection portion HAD6 to the via v80 branches into three at the via v80. As shown in FIG. 35, the first branch path is connected from the via v80 to the terminal connection portion A5 of the control ROM 105 from inside the control ROM placement area 192 by the wiring path cp63 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v80 to the terminating resistor RA15 by a wiring path cp64 provided in the sixth wiring layer La6.

As shown in FIGS. 37 and 38, the third branch path is connected from the via v80 to the via v140 in the first connector placement area 194 by the wiring path cp65 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp66 provided in the sixth wiring layer La6 is connected to the terminal connection part had6 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P8 (FIG. 45), as shown in FIG. 34, the terminal connection portion HAD7 provided in the composite chip placement region 191 of the first wiring layer La1 is obliquely adjacent to the +XY direction by the wiring path cp71. It is connected to the placed via v3. The via v3 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD7) arranged around it. As shown in FIG. 40, the via v3 is connected to a via v79 arranged in the control ROM arrangement area 192 by a wiring path cp72 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD7 to the via v79 branches into three at the via v79. As shown in FIG. 35, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v79 to the terminal connection portion A6 of the control ROM 105 by the wiring path cp73 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v79 to the terminating resistor RA15 by a wiring path cp74 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v79 to the via v139 in the first connector placement area 194 by the wiring path cp75 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp76 provided in the sixth wiring layer La6 is connected to the terminal connection part had7 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P9 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD8 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the +XY direction diagonally by the wiring path cp81. It is connected to the placed via v12. The via v12 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD8) arranged around it. As shown in FIG. 40, this via v12 is connected to a via v78 arranged in the control ROM arrangement region 192 by a wiring path cp82 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD8 to the via v78 branches into three at the via v78. As shown in FIG. 35, the first branch path is connected from the via v78 to the terminal connection portion A7 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp83 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v78 to the terminating resistor RA13 by a wiring path cp84 provided in the sixth wiring layer La6. The termination resistor RA13 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

As shown in FIGS. 37 and 38, the third branch path is connected from the via v78 to the via v138 in the first connector placement area 194 by the wiring path cp85 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp86 provided in the sixth wiring layer La6 is connected to the terminal connection part had8 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P10 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD9 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the outside of the composite chip placement area 191 by the wiring path cp91. Specifically, it is connected to the via v33 arranged between the composite chip placement area 191 and the control ROM placement area 192 . The terminal connection portion HAD9 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 40, the via v33 is connected to a via v77 arranged in the control ROM arrangement area 192 by a wiring path cp92 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD9 to the via v77 is branched into three at the via v77. As shown in FIG. 35, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v77 to the terminal connection portion A8 of the control ROM 105 by the wiring path cp93 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v77 to the terminating resistor RA13 by a wiring path cp94 provided in the sixth wiring layer La6.

As shown in FIGS. 37 and 38, the third branch path is connected from the via v77 to the via v137 in the first connector placement area 194 by the wiring path cp95 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp96 provided in the sixth wiring layer La6 is connected to the terminal connection part had9 from inside the first connector arrangement region 194. As shown in FIG.

In the wiring path P11 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD10 provided in the composite chip placement area 191 of the first wiring layer La1 is arranged outside the composite chip placement area 191 by the wiring path cp101. Specifically, it is connected to the via v38 arranged between the composite chip placement area 191 and the control ROM placement area 192 . The terminal connection portion HAD10 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 40, the via v38 is connected to the via v76 arranged in the control ROM arrangement region 192 by a wiring path cp102 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD10 to the via v76 branches into three at the via v76. As shown in FIG. 35, the first branch path is connected from the via v76 to the terminal connection portion A9 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp103 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v76 to the terminating resistor RA13 by the wiring path cp104 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v76 to the via v136 in the first connector placement area 194 by the wiring path cp105 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp106 provided in the sixth wiring layer La6 is connected to the terminal connection part had10 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P12 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD11 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal -X+Y direction by the wiring path cp111. is connected to the via v2 connected to the The via v2 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD11) arranged around it. As shown in FIG. 40, the via v2 is connected to a via v75 arranged in the control ROM arrangement region 192 by a wiring path cp112 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD11 to the via v75 branches into three at the via v75. As shown in FIG. 35, the first branch path is connected from the via v75 to the terminal connection portion A10 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp113 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v75 to the terminating resistor RA13 by the wiring path cp114 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v75 to the via v135 in the first connector placement area 194 by the wiring path cp115 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp116 provided in the sixth wiring layer La6 is connected to the terminal connection part had11 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P13 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD12 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp121. It is connected to the placed via v19. The via v19 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD12) arranged around it. As shown in FIG. 40, this via v19 is connected to a via v74 arranged in the control ROM arrangement region 192 by a wiring path cp122 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD12 to the via v74 branches into three at the via v74. As shown in FIG. 35, the first branch path is connected from the via v74 to the terminal connection portion A11 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp123 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v74 to the terminating resistor RA11 by the wiring path cp124 provided in the sixth wiring layer La6. The termination resistor RA11 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

37 and 38, the third branch path is connected from the via v74 to the via v134 in the first connector placement area 194 by the wiring path cp125 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp126 provided in the sixth wiring layer La6 is connected to the terminal connection part had12 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P14 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD13 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the outside of the composite chip placement area 191 by the wiring path cp131. Specifically, it is connected to the via v49 arranged on the +Y side of the control ROM arrangement area 192 . The terminal connection portion HAD13 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. The via v49 is connected to the via v73 arranged in the control ROM arrangement region 192 by a wiring path cp132 provided in the fourth wiring layer La4, as shown in FIG.

The wiring path extending from the terminal connection portion HAD13 to the via v73 branches into two at the via v73. As shown in FIG. 41, the first branch path is connected from the via v73 to the terminating resistor RA11 by a wiring path cp133 provided in the sixth wiring layer La6.

Also, as shown in FIG. 37, the second branch path is connected from the via v73 to the via v107 arranged in the control ROM placement area 192 by the wiring path cp134 provided in the third wiring layer La3. , where it branches further into two. As shown in FIG. 35, the first branch path 2a is connected to the terminal connection portion A12 of the control ROM 105 from the via v107 by the wiring path cp135 provided in the first wiring layer La1. 192 is connected from the inside. As shown in FIGS. 37 and 38, the second 2b branch path is connected from the via v107 to the via v133 in the first connector placement area 194 by the wiring path cp136 provided in the third wiring layer La3. Further, as shown in FIG. 42, a wiring path cp137 provided in the sixth wiring layer La6 is connected to the terminal connection part had13 from inside the first connector arrangement area 194. FIG.

In the wiring path P15 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD14 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the outside of the composite chip placement area 191 by the wiring path cp141. Specifically, it is connected to the via v50 arranged on the +Y side of the control ROM arrangement area 192 . The terminal connection portion HAD14 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 40, the via v50 is connected to a via v72 arranged in the control ROM arrangement region 192 by a wiring path cp142 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD14 to the via v72 branches into two at the via v72. As shown in FIG. 41, the first branch path is connected from the via v72 to the terminating resistor RA11 by a wiring path cp143 provided in the sixth wiring layer La6.

Also, as shown in FIG. 37, the second branch path is connected from the via v72 to the via v106 arranged in the control ROM arrangement area 192 by the wiring path cp144 provided in the third wiring layer La3. , where it branches further into two. As shown in FIG. 35, the first branch path 2a is connected to the terminal connection portion A13 of the control ROM 105 from the via v106 by the wiring path cp145 provided in the first wiring layer La1. 192 is connected from the inside. As shown in FIGS. 37 and 38, the second 2b branch path is connected from the via v106 to the via v132 in the first connector placement area 194 by the wiring path cp146 provided in the third wiring layer La3. Further, as shown in FIG. 42, a wiring path cp147 provided in the sixth wiring layer La6 is connected to the terminal connection part had14 from inside the first connector arrangement area 194. FIG.

In the wiring path P16 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD15 provided in the composite chip placement region 191 of the first wiring layer La1 is obliquely adjacent to the +XY direction by the wiring path cp151. It is connected to the placed via v11. The via v11 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD15) arranged around it. As shown in FIG. 40, this via v11 is connected to a via v71 arranged in the control ROM arrangement region 192 by a wiring path cp152 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD15 to the via v71 branches into two at the via v71. As shown in FIG. 41, the first branch path is connected from the via v71 to the terminating resistor RA11 by a wiring path cp153 provided in the sixth wiring layer La6.

Also, as shown in FIG. 37, the second branch path is connected from the via v71 to the via v105 arranged in the control ROM arrangement area 192 by the wiring path cp154 provided in the third wiring layer La3. , where it branches further into two. As shown in FIG. 35, the first branch path 2a is connected to the terminal connection portion A14 of the control ROM 105 from the via v105 by the wiring path cp155 provided in the first wiring layer La1. 192 is connected from the inside. As shown in FIGS. 37 and 38, the second 2b branch path extends from the via v105 to the via v131 in the first connector placement area 194 by the wiring path cp156 provided in the third wiring layer La3. Further, as shown in FIG. 42, a wiring path cp157 provided in the sixth wiring layer La6 is connected to the terminal connection part had15 from inside the first connector arrangement area 194. FIG.

In the wiring path P17 (FIG. 46), as shown in FIG. 34, the terminal connection portion HAD16 provided in the composite chip placement region 191 of the first wiring layer La1 is obliquely adjacent to the +XY direction by the wiring path cp161. It is connected to the placed via v18. The via v18 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD16) arranged around it. As shown in FIG. 40, the via v18 is connected to a via v70 arranged in the control ROM arrangement region 192 by a wiring path cp162 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD16 to the via v70 branches into two at the via v70. As shown in FIG. 41, the first branch path is connected from the via v70 to the terminating resistor RA10 by a wiring path cp163 provided in the sixth wiring layer La6. The terminating resistor RA10 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (not shown in the wiring diagram).

Also, as shown in FIG. 37, the second branch path is connected from the via v70 to the via v104 arranged in the control ROM arrangement area 192 by the wiring path cp164 provided in the third wiring layer La3. , where it branches further into two. As shown in FIG. 35, the first branch path 2a is connected to the terminal connection portion A15 of the control ROM 105 from the via v104 by the wiring path cp165 provided in the first wiring layer La1. 192 from outside. As shown in FIGS. 37 and 38, the second 2b branch path is connected from the via v104 to the via v130 in the first connector placement area 194 by the wiring path cp166 provided in the third wiring layer La3. Further, as shown in FIG. 42, a wiring path cp167 provided in the sixth wiring layer La6 is connected to the terminal connection part had16 from inside the first connector arrangement area 194. FIG.

In the wiring path P18 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD17 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the outside of the composite chip placement area 191 by the wiring path cp171. Specifically, it is connected to the via v51 arranged on the +Y side of the control ROM arrangement area 192 . The terminal connection portion HAD17 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 40, the via v51 is connected to a via v69 arranged in the control ROM arrangement area 192 by a wiring path cp172 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD17 to the via v69 branches into two at the via v69. As shown in FIG. 41, the first branch path is connected from the via v69 to the terminating resistor RA10 by a wiring path cp173 provided in the sixth wiring layer La6.

Also, as shown in FIG. 37, the second branch path is connected from the via v69 to the via v103 arranged in the control ROM placement area 192 by the wiring path cp174 provided in the third wiring layer La3. , where it branches further into two. As shown in FIG. 35, the first branch path 2a is connected to the terminal connection portion A16 of the control ROM 105 from the via v103 by the wiring path cp175 provided in the first wiring layer La1. 192 from outside. As shown in FIGS. 37 and 38, the second branch path 2b is connected from the via v103 to the via v129 in the first connector placement area 194 by the wiring path cp176 provided in the third wiring layer La3. Further, as shown in FIG. 42, a wiring path cp177 provided in the sixth wiring layer La6 is connected to the terminal connection part had17 from inside the first connector arrangement area 194. FIG.

In the wiring path P19 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD18 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the outside of the composite chip placement area 191 by the wiring path cp181. Specifically, it is connected to the via v52 arranged on the +Y side of the control ROM arrangement area 192 . It should be noted that the terminal connection portion HAD18 is arranged on the outermost side of the composite chip arrangement area 191 . As shown in FIG. 40, the via v52 is connected to the via v68 arranged in the control ROM arrangement region 192 by a wiring path cp182 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD18 to the via v68 branches into three at the via v68. As shown in FIG. 35, the first branch path is connected from the via v68 to the terminal connection portion A17 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp183 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v68 to the terminating resistor RA10 by the wiring path cp184 provided in the sixth wiring layer La6.

As shown in FIGS. 37 and 38, the third branch path is connected from the via v68 to the via v128 in the first connector placement area 194 by the wiring path cp185 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp186 provided in the sixth wiring layer La6 is connected to the terminal connection part had18 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P20 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD19 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp191. It is connected to the placed via v1. The via v1 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD19) arranged around it. As shown in FIG. 40, the via v1 is connected to a via v67 arranged in the control ROM arrangement region 192 by a wiring path cp192 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD19 to the via v67 branches into three at the via v67. As shown in FIG. 35, the first branch path is connected from the via v67 to the terminal connection portion A18 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp193 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v67 to the terminating resistor RA10 by a wiring path cp194 provided in the sixth wiring layer La6.

Also, as shown in FIGS. 37 and 38, the third branch path is connected from the via v67 to the via v127 in the first connector placement area 194 by the wiring path cp195 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp196 provided in the sixth wiring layer La6 is connected to the terminal connection part had19 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P21 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD20 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp201. It is connected to the placed via v10. The via v10 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD20) arranged around it. As shown in FIG. 40, this via v10 is connected to a via v66 arranged in the control ROM arrangement region 192 by a wiring path cp202 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD20 to the via v66 branches into three at the via v66. As shown in FIG. 35, the first branch path is connected from the via v66 to the terminal connection portion A19 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp203 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v66 to the terminating resistor RA9 by a wiring path cp204 provided in the sixth wiring layer La6. The termination resistor RA9 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

37 and 38, the third branch path is connected from the via v66 to the via v126 in the first connector placement area 194 by the wiring path cp205 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp206 provided in the sixth wiring layer La6 is connected to the terminal connection part had20 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P22 (FIG. 47), as shown in FIGS. 34 and 35, the terminal connection portion HAD21 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the composite chip placement area 191 by the wiring path cp211. is connected to the via v54 arranged on the outside of the control ROM arrangement area 192, specifically on the +Y side of the control ROM arrangement area 192. As shown in FIG. The terminal connection portion HAD21 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 40, the via v54 is connected to the via v65 arranged in the control ROM arrangement area 192 by a wiring path cp212 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD21 to the via v65 branches into three at the via v65. As shown in FIG. 35, the first branch path is connected from the via v65 to the terminal connection portion A20 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp213 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v65 to the terminating resistor RA9 by the wiring path cp214 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v65 to the via v125 in the first connector placement area 194 by the wiring path cp215 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp216 provided in the sixth wiring layer La6 is connected to the terminal connection part had21 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P23 (FIG. 47), as shown in FIGS. 34 and 35, the terminal connection portion HAD22 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the composite chip placement area 191 by the wiring path cp221. is connected to the via v53 arranged on the outside of the control ROM arrangement area 192, specifically on the +Y side of the control ROM arrangement area 192. As shown in FIG. The terminal connection portion HAD22 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. As shown in FIG. 40, the via v53 is connected to the via v64 arranged in the control ROM arrangement area 192 by a wiring path cp222 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HAD22 to the via v64 branches into three at the via v64. As shown in FIG. 35, the first branch path is connected from the via v64 to the terminal connection portion A21 of the control ROM 105 from inside the control ROM placement area 192 by the wiring path cp223 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v64 to the terminating resistor RA9 by a wiring path cp224 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v64 to the via v124 in the first connector placement area 194 by the wiring path cp225 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp226 provided in the sixth wiring layer La6 is connected to the terminal connection part had22 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P24 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD23 provided in the composite chip arrangement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp231. is connected to the via v21. The via v21 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD23) arranged around it. As shown in FIG. 40, the via v21 is formed outside the composite chip placement region 191, specifically, between the composite chip placement region 191 and the control ROM placement region 192 by the wiring path cp232 provided in the fourth wiring layer La4. is connected to the via v36 arranged between the It is connected.

The wiring path extending from the terminal connection portion HAD23 to the via v63 branches into three at the via v63. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 to the terminal connection portion A22 of the control ROM 105 from the via v63 by the wiring path cp234 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v63 to the terminating resistor RA9 by the wiring path cp235 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v63 to the via v123 in the first connector placement area 194 by the wiring path cp236 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp237 provided in the sixth wiring layer La6 is connected to the terminal connection part had23 from inside the first connector arrangement area 194. As shown in FIG.

In the wiring path P25 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD24 provided in the composite chip arrangement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp241. is connected to via v14. The via v14 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD24) arranged around it. As shown in FIG. 40, the via v14 is formed outside the composite chip placement region 191, specifically, between the composite chip placement region 191 and the control ROM placement region 192 by the wiring path cp242 provided in the fourth wiring layer La4. is connected to the via v35 arranged between the It is connected.

The wiring path extending from the terminal connection portion HAD24 to the via v62 branches into four at the via v62. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 to the terminal connection portion A23 of the control ROM 105 from the via v62 by the wiring path cp244 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v62 to the terminating resistor R45 by the wiring path cp245 provided in the sixth wiring layer La6. The terminating resistor R45 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (not shown in the wiring diagram).

37 and 38, the third branch path is connected from the via v62 to the via v122 in the first connector placement area 194 by the wiring path cp246 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp247 provided in the sixth wiring layer La6 is connected to the terminal connection part had24 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v62 to the via v183 by the wiring path cp248 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp249 provided in the sixth wiring layer La6 is connected to the decoder IC12 constituting the decoding circuit.

In the wiring path P26 (FIG. 47), as shown in FIG. 34, the terminal connection portion HAD25 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp251. is connected to via v6. The via v6 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD25) arranged around it. As shown in FIG. 40, the via v6 is formed outside the composite chip placement region 191, specifically, between the composite chip placement region 191 and the control ROM placement region 192 by the wiring path cp252 provided in the fourth wiring layer La4. is connected to the via v40 arranged between It is connected.

The wiring path extending from the terminal connection portion HAD25 to the via v61 branches into three at the via v61. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v61 to the terminal connection portion A24 of the control ROM 105 by the wiring path cp254 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v61 to the terminating resistor R44 by the wiring path cp255 provided in the sixth wiring layer La6. The terminating resistor R44 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

37 and 38, the third branch path is connected from the via v61 to the via v121 in the first connector placement area 194 by the wiring path cp256 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp257 provided in the sixth wiring layer La6 is connected to the terminal connection part had25 from inside the first connector arrangement area 194. As shown in FIG.

Next, the wiring paths P27 to P42 connected to the data input/output terminals HDT0 to HDT15 of the composite chip 104 will be described. The data input/output terminals HDT0 to HDT15 are connected to the data input/output terminals Q0 to Q15 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31.

Comparing the arrangement of the data input/output terminals HDT0 to HDT15 of the composite chip 104 (FIG. 26(a)) with the corresponding arrangement of the data input/output terminals Q0 to Q15 of the control ROM 105 (FIG. 27), the two are Clearly different. That is, the data input/output terminals HDT0 to HDT15 of the composite chip 104 are arranged in four rows as shown in FIG. 26(a). On the other hand, the data input/output terminals Q0 to Q15 of the control ROM 105 are arranged in two columns as shown in FIG. 27, and the arrangement order in each column is not regular. In addition, the arrangement positions of the composite chip 104 and the control ROM 105 and the number of wiring patterns are related, so that the routing of the wiring patterns becomes very complicated. Therefore, it is very important to optimize the routing of the wiring pattern that connects the composite chip 104 and the control ROM 105. This makes it possible to shorten the length of the wiring pattern, thereby reducing noise and slimming down the entire board. It leads to plan. The same applies not only to the relationship between the composite chip 104 and the control ROM 105, but also to the relationship between the composite chip 104 and electronic components such as various connectors. In particular, the wiring pattern connected to a plurality of electronic components such as the composite chip 104 such as HAD1 to HAD25 and HDT1 to HDT25, the control ROM 105, and various connectors poses the above-mentioned problems, and the effect of optimization is great. become a thing.

Among the wiring paths P27 to P42, in the wiring path P27 (FIG. 48), as shown in FIG. It is connected to a via v32 arranged outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. FIG. Terminal connection portion HDT0 is arranged on the outermost side of composite chip arrangement region 191 . As shown in FIG. 40, the via v32 is connected to the via v102 arranged in the control ROM arrangement region 192 by a wiring path cp302 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT0 to the via v102 branches into four at the via v102. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v102 to the terminal connection portion Q0 of the control ROM 105 by the wiring path cp303 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v102 to the terminating resistor RA34 by the wiring path cp304 provided in the sixth wiring layer La6. The termination resistor RA34 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

As shown in FIGS. 37 and 38, the third branch path is connected from the via v102 to the via v162 in the first connector placement area 194 by the wiring path cp305 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp306 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt0 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v102 to the via v197 by the wiring path cp307 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp308 provided in the sixth wiring layer La6 is connected to the decoder IC13 forming a decoding circuit.

In the wiring path P28 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT1 provided in the composite chip placement area 191 of the first wiring layer La1 is arranged outside the composite chip placement area 191 by the wiring path cp311. Specifically, it is connected to the via v31 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection portion HDT1 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . The via v31 is connected to the via v101 arranged in the control ROM arrangement region 192 by a wiring path cp312 provided in the fourth wiring layer La4, as shown in FIG.

The wiring path extending from the terminal connection portion HDT1 to the via v101 branches into four at the via v101. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v101 to the terminal connection portion Q1 of the control ROM 105 by the wiring path cp313 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v101 to the terminating resistor RA34 by the wiring path cp314 provided in the sixth wiring layer La6.

As shown in FIGS. 37 and 38, the third branch path is connected from the via v101 to the via v161 in the first connector placement area 194 by the wiring path cp315 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp316 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt1 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v101 to the via v198 by the wiring path cp317 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp318 provided in the sixth wiring layer La6 is connected to the decoder IC13 forming a decoding circuit.

In the wiring path P29 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT2 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp321. is connected to via v24. The via v24 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT2) arranged around it. As shown in FIG. 40, the via v24 is connected to the via v100 arranged in the control ROM arrangement region 192 by a wiring path cp322 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT2 to the via v100 branches into four at the via v100. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v100 to the terminal connection portion Q2 of the control ROM 105 by the wiring path cp323 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v100 to the terminating resistor RA34 by the wiring path cp324 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v100 to the via v160 in the first connector placement area 194 by the wiring path cp325 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp326 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt2 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v100 to the via v199 by the wiring path cp327 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp328 provided in the sixth wiring layer La6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P30 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT3 provided in the composite chip placement region 191 of the first wiring layer La1 is connected to the vicinity of the diagonal -XY direction by the wiring path cp331. is connected to the via v8 located in the . The via v8 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT3) arranged around it. As shown in FIG. 40, the via v8 is connected to a via v99 arranged in the control ROM arrangement region 192 by a wiring path cp332 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT3 to the via v99 branches into four at the via v99. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v99 to the terminal connection portion Q3 of the control ROM 105 by the wiring path cp333 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v99 to the terminating resistor RA34 by the wiring path cp334 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v99 to the via v159 in the first connector placement area 194 by the wiring path cp335 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp336 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt3 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v99 to the via v200 by the wiring path cp337 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp338 provided in the sixth wiring layer La6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P31 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT4 provided in the composite chip placement area 191 of the first wiring layer La1 is arranged outside the composite chip placement area 191 by the wiring path cp341. Specifically, it is connected to the via v37 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection part HDT4 is arranged on the outermost side of the composite chip arrangement area 191 . The via v37 is connected to a via v98 arranged in the control ROM arrangement region 192 by a wiring path cp342 provided in the fourth wiring layer La4, as shown in FIG.

The wiring path extending from the terminal connection portion HDT4 to the via v98 branches into four at the via v98. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 to the terminal connection portion Q4 of the control ROM 105 from the via v98 by the wiring path cp343 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v98 to the terminating resistor RA32 by the wiring path cp344 provided in the sixth wiring layer La6. The termination resistor RA32 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 via a predetermined via (not shown in the wiring diagram).

As shown in FIGS. 37 and 38, the third branch path is connected from the via v98 to the via v158 in the first connector placement area 194 by the wiring path cp345 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp346 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt4 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v98 to the via v189 by the wiring path cp347 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp348 provided in the sixth wiring layer La6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P32 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT5 provided in the composite chip placement area 191 of the first wiring layer La1 is arranged outside the composite chip placement area 191 by the wiring path cp351. Specifically, it is connected to the via v46 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection portion HDT5 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . The via v46 is connected to the via v97 arranged in the control ROM arrangement region 192 by a wiring path cp352 provided in the fourth wiring layer La4, as shown in FIG.

The wiring path extending from the terminal connection portion HDT5 to the via v97 branches into four at the via v97. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 to the terminal connection portion Q5 of the control ROM 105 from the via v97 by the wiring path cp353 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v97 to the terminating resistor RA32 by the wiring path cp354 provided in the sixth wiring layer La6.

As shown in FIGS. 37 and 38, the third branch path is connected from the via v97 to the via v157 in the first connector placement area 194 by the wiring path cp355 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp356 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt5 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v97 to the via v190 by the wiring path cp357 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp358 provided in the sixth wiring layer La6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P33 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT6 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp361. is connected to via v17. The via v17 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT6) arranged around it. As shown in FIG. 40, this via v17 is connected to a via v96 arranged in the control ROM arrangement region 192 by a wiring path cp362 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT6 to the via v96 branches into four at the via v96. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v96 to the terminal connection portion Q6 of the control ROM 105 by the wiring path cp363 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v96 to the terminating resistor RA32 by the wiring path cp364 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v96 to the via v156 in the first connector placement area 194 by the wiring path cp365 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp366 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt6 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v96 to the via v195 by the wiring path cp367 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp368 provided in the sixth wiring layer La6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P34 (FIG. 48), as shown in FIG. 34, the terminal connection portion HDT7 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the outside of the composite chip placement area 191 by the wiring path cp371. Specifically, it is connected to the via v45 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection part HDT7 is arranged on the outermost side of the composite chip arrangement area 191 . The via v45 is connected to a via v95 arranged in the control ROM arrangement region 192 by a wiring path cp372 provided in the fourth wiring layer La4, as shown in FIG.

The wiring path extending from the terminal connection portion HDT7 to the via v95 branches into four at the via v95. As shown in FIG. 35, the first branch path is connected from the outside of the control ROM arrangement area 192 from the via v95 to the terminal connection portion Q7 of the control ROM 105 by the wiring path cp373 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v95 to the terminating resistor RA32 by the wiring path cp374 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v95 to the via v155 in the first connector placement area 194 by the wiring path cp375 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp376 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt7 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v95 to the via v196 by the wiring path cp377 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp378 provided in the sixth wiring layer La6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P35 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT8 provided in the composite chip placement area 191 of the first wiring layer La1 is arranged outside the composite chip placement area 191 by the wiring path cp381. Specifically, it is connected to the via v44 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection portion HDT8 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . As shown in FIG. 40, the via v44 is connected to a via v94 arranged in the control ROM arrangement region 192 by a wiring path cp382 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT8 to the via v94 branches into four at the via v94. As shown in FIG. 35, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v94 to the terminal connection portion Q8 of the control ROM 105 by the wiring path cp383 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v94 to the terminating resistor RA30 by the wiring path cp384 provided in the sixth wiring layer La6. The termination resistor RA30 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

As shown in FIGS. 37 and 38, the third branch path is connected from the via v94 to the via v154 in the first connector placement area 194 by the wiring path cp385 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp386 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt8 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v94 to the via v191 by the wiring path cp387 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp388 provided in the sixth wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P36 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT9 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp391. is connected to the via v23. The via v23 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT9) arranged around it. As shown in FIG. 40, this via v23 is connected to a via v93 arranged in the control ROM arrangement region 192 by a wiring path cp392 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT9 to the via v93 branches into four at the via v93. As shown in FIG. 35, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v93 to the terminal connection portion Q9 of the control ROM 105 by the wiring path cp393 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v93 to the terminating resistor RA30 by a wiring path cp394 provided in the sixth wiring layer La6.

As shown in FIGS. 37 and 38, the third branch path is connected from the via v93 to the via v153 in the first connector placement area 194 by the wiring path cp395 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp396 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt9 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v93 to the via v192 by the wiring path cp397 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp398 provided in the sixth wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P37 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT10 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity in the diagonal +X+Y direction by the wiring path cp401. is connected to via v16. The via v16 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT10) arranged around it. This via v16 is connected to a via v92 arranged in the control ROM arrangement region 192 by a wiring path cp402 provided in the fourth wiring layer La4, as shown in FIG.

The wiring path extending from the terminal connection portion HDT10 to the via v92 branches into four at the via v92. As shown in FIG. 35, the first branch path is connected from the via v92 to the terminal connection portion Q10 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp403 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v92 to the terminating resistor RA30 by a wiring path cp404 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v92 to the via v152 in the first connector placement area 194 by the wiring path cp405 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp406 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt10 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v92 to the via v193 by the wiring path cp407 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp408 provided in the sixth wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P38 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT11 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp411. is connected to via v7. The via v7 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT11) arranged around it. As shown in FIG. 40, this via v7 is connected to a via v91 arranged in the control ROM arrangement region 192 by a wiring path cp412 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT11 to the via v91 branches into four at the via v91. As shown in FIG. 35, the first branch path is connected from the via v91 to the terminal connection portion Q11 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp413 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v91 to the terminating resistor RA30 by a wiring path cp414 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v91 to the via v151 in the first connector placement area 194 by the wiring path cp415 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp416 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt11 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v91 to the via v194 by the wiring path cp417 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp418 provided in the sixth wiring layer La6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P39 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT12 provided in the composite chip placement area 191 of the first wiring layer La1 is arranged outside the composite chip placement area 191 by the wiring path cp421. Specifically, it is connected to the via v43 arranged between the composite chip placement area 191 and the control ROM placement area 192 . The terminal connection portion HDT12 is arranged on the outermost side of the composite chip arrangement area 191 . As shown in FIG. 40, the via v43 is connected to a via v90 arranged in the control ROM arrangement region 192 by a wiring path cp422 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT12 to the via v90 branches into four at the via v90. As shown in FIG. 35, the first branch path is connected from the via v90 to the terminal connection portion Q12 of the control ROM 105 from inside the control ROM arrangement area 192 by the wiring path cp423 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v90 to the terminating resistor RA17 by a wiring path cp424 provided in the sixth wiring layer La6. The termination resistor RA17 has the other end connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

Also, as shown in FIGS. 37 and 38, the third branch path is connected from the via v90 to the via v150 in the first connector placement area 194 by the wiring path cp425 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp426 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt12 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v90 to the via v185 by the wiring path cp427 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp428 provided in the sixth wiring layer La6 is connected to the decoder IC14 constituting the decoding circuit.

In the wiring path P40 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT13 provided in the composite chip placement area 191 of the first wiring layer La1 is arranged outside the composite chip placement area 191 by the wiring path cp431. Specifically, it is connected to the via v42 arranged between the composite chip placement area 191 and the control ROM placement area 192 . It should be noted that the terminal connection portion HDT13 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191 . The via v42 is connected to the via v89 arranged in the control ROM arrangement region 192 by a wiring path cp432 provided in the fourth wiring layer La4, as shown in FIG.

The wiring path extending from the terminal connection portion HDT13 to the via v89 branches into four at the via v89. As shown in FIG. 35, the first branch path is connected from the inside of the control ROM arrangement area 192 from the via v89 to the terminal connection portion Q13 of the control ROM 105 by the wiring path cp433 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v89 to the terminating resistor RA17 by a wiring path cp434 provided in the sixth wiring layer La6.

As shown in FIGS. 37 and 38, the third branch path is connected from the via v89 to the via v149 in the first connector placement area 194 by the wiring path cp435 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp436 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt13 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v89 to the via v186 by the wiring path cp437 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp438 provided in the sixth wiring layer La6 is connected to the decoder IC14 constituting the decoding circuit.

In the wiring path P41 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT14 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +X+Y direction by the wiring path cp441. is connected to the via v22. The via v22 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT14) arranged around it. As shown in FIG. 40, this via v22 is connected to a via v88 arranged in the control ROM arrangement region 192 by a wiring path cp442 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT14 to the via v88 is branched into four at the via v88. As shown in FIG. 35, the first branch path is connected from the via v88 to the terminal connection portion Q14 of the control ROM 105 from inside the control ROM placement area 192 by the wiring path cp443 provided in the first wiring layer La1. It is Also, as shown in FIG. 41, the second branch path is connected from the via v88 to the terminating resistor RA17 by a wiring path cp444 provided in the sixth wiring layer La6.

As shown in FIGS. 37 and 38, the third branch path is connected from the via v88 to the via v148 in the first connector placement area 194 by the wiring path cp445 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp446 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt14 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v88 to the via v187 by the wiring path cp447 provided in the third wiring layer La3, and further, as shown in FIG. A wiring path cp448 provided in the sixth wiring layer La6 is connected to the decoder IC14 constituting the decoding circuit.

In the wiring path P42 (FIG. 49), as shown in FIG. 34, the terminal connection portion HDT15 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity in the diagonal +X+Y direction by the wiring path cp451. is connected to via v15. The via v15 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT15) arranged around it. As shown in FIG. 40, the via v15 is connected to a via v87 arranged in the control ROM arrangement area 192 by a wiring path cp452 provided in the fourth wiring layer La4.

The wiring path extending from the terminal connection portion HDT15 to the via v87 branches into four at the via v87. As shown in FIG. 35, the first branch path is connected to the control ROM arrangement area 192 from the via v87 to the terminal connection portion Q15/A-1 of the control ROM 105 by the wiring path cp453 provided in the first wiring layer La1. connected from the inside. Also, as shown in FIG. 41, the second branch path is connected from the via v87 to the terminating resistor RA17 by a wiring path cp454 provided in the sixth wiring layer La6.

37 and 38, the third branch path is connected from the via v87 to the via v147 in the first connector placement region 194 by the wiring path cp455 provided in the third wiring layer La3. As shown in FIG. 42, the wiring path cp456 provided in the sixth wiring layer La6 is connected to the terminal connection portion hdt15 from inside the first connector arrangement region 194. As shown in FIG. 37 and 39, the fourth branch path is connected from the via v87 to the via v188 by the wiring path cp457 provided in the third wiring layer La3, and further, as shown in FIG. It is connected to the decoder IC 14 by a wiring path cp458 provided in the sixth wiring layer La6.

Next, wiring paths P43 to P45 connected to the chip select output terminal HCS0, the read strobe output terminal HRD, and the system reset terminal HRESET of the composite chip 104 will be described.

In the wiring path P43 (FIG. 50), as shown in FIG. 34, the terminal connection portion HCS0 provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal -X+Y direction by the wiring path cp501. is connected to the via v9 connected to it, and is branched into two here. The via v9 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HCS0) arranged around it. As shown in FIG. 33, the first branch path in the via v9 is connected to the via v60 arranged in the control ROM placement area 192 by the wiring path cp502 provided in the sixth wiring layer La6. 2, the wiring path cp503 provided in the first wiring layer La1 is connected to the terminal connection portion CE# from inside the control ROM arrangement region 192. As shown in FIG.

Also, as shown in FIG. 31, the second branched path in the via v9 is connected to the via v173 by a wiring path cp504 provided in the fourth wiring layer La4, where it is further branched into two. As shown in FIG. 33, the 2a-th branch path in the via v173 is connected to the via v201 by a wiring path cp505 provided in the sixth wiring layer La6. This via v201 forms a test point TP33. As shown in FIG. 28, the 2b branch path of the via v173 is connected to DC 3.3V (fifth wiring layer La5) through a resistor RA12 by a wiring path cp506 provided in the first wiring layer La1. there is

In the wiring path P44 (FIG. 50), as shown in FIG. 28, the terminal connection portion HRD provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp511. It is connected to the arranged via v25 and branches into two here. The via v25 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HRD) arranged around it. As shown in FIG. 33, the first branched path in the via v25 is connected to the outside of the composite chip placement area 191, specifically, the composite chip placement area 191 and controlled by the wiring path cp512 provided in the sixth wiring layer La6. 35, the wiring path cp513 provided in the first wiring layer La1 is connected to the via v47 arranged between the ROM arrangement region 192 and the control ROM arrangement with respect to the terminal connection portion OE#. It is connected from outside the area 192 .

Also, as shown in FIG. 30, the second branch path in the via v25 is connected to the via v172 by the wiring path cp514 provided in the third wiring layer La3, and is further branched into two. As shown in FIG. 30, the 2a branch path of the via v172 is connected to the via v171 arranged near the outside of the first connector placement region 194 by a wiring path cp515 provided in the third wiring layer La3. Further, as shown in FIG. 33, the wiring path cp516 provided in the sixth wiring layer La6 is connected to the terminal connection portion hrd from the outside of the first connector arrangement region 194. As shown in FIG. Also, as shown in FIG. 28, the 2b branch path in the via v172 is connected to DC 3.3 V (fifth wiring layer La5) through a resistor RA8 by a wiring path cp517 provided in the first wiring layer La1. there is

In the wiring path P45 (FIG. 50), as shown in FIG. 28, the terminal connection portion HRESET provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the outside of the composite chip placement area 191 ( +X side). The terminal connection portion HRESET is arranged on the outermost side of the composite chip arrangement area 191 . The via v26 is connected to the via v202 by a wiring path cp522 provided in the fourth wiring layer La4, as shown in FIG. 31, and further to a wiring path cp523 provided in the sixth wiring layer La6, as shown in FIG. is connected to via v174 by , where it branches into two.

As shown in FIG. 33, the first branch path in the via v174 is connected to the via v108 arranged near the outside (+X side) of the control ROM arrangement area 192 by the wiring path cp524 provided in the sixth wiring layer La6. Further, as shown in FIG. 35, a wiring path cp525 provided in the first wiring layer La1 is connected to the terminal connection portion RESET# from inside the control ROM arrangement area 192. FIG. As shown in FIG. 33, the wiring line cp524 of the sixth wiring layer La6 is connected to DC 3.3V (fifth wiring layer La5) via a resistor R40, and is grounded (second wiring layer) via a capacitor C151. La2).

Also, as shown in FIG. 28, the second branch path in the via v174 is connected to the via v204 by a wiring path cp526 provided in the first wiring layer La1. This via v204 constitutes the test point TP17. The via v204 is connected to the reset circuit on the sixth wiring layer La6 side. That is, as shown in FIG. 33, the via v204 is connected to the resistor built-in transistor T1 by a wiring path cp527 provided in the sixth wiring layer La6, further connected to the logic integrated circuit IC7 by a wiring path cp528, and further connected to the logic integrated circuit IC7 by a wiring path cp529. , is connected to the WDT built-in reset integrated circuit (reset IC) IC10 via a via v203 forming the test point TP23. The wiring path cp528 is connected to DC 3.3 V (fifth wiring layer La5) through a resistor R19, the wiring path cp529 is connected to the ground (second wiring layer La2) through a capacitor C40, and the resistor R26 is connected. are connected to DC 3.3 V (fifth wiring layer La5) via the respective wiring layers.

The reset circuit on the sixth wiring layer La6 side is constructed as shown in FIG. A system reset signal can be input to the logic integrated circuit IC7 via the liquid crystal control first connector CN31, and a reset signal can be input from the WDT built-in reset integrated circuit (reset IC) IC10. When a signal is input, a reset signal is transmitted to the composite chip 104 and the control ROM 105 via the resistor built-in transistor T1 for noise countermeasures. For example, a data output terminal ASIBLDTB for LED of the composite chip 104 is connected to the WDT built-in reset integrated circuit (reset IC) IC10 for resetting the WDT.

Here, the test point TP23 is for checking when the reset integrated circuit IC10 operates, and as shown in FIG. Therefore, the display of "TP23", which is the identification information indicating the test point TP23, is placed by silk printing on the sixth wiring layer La6 side where the wiring path cp421 is provided, that is, on the back surface 98b side. is normal. On the other hand, the check operation by the test point TP23 must be performed with the board assembled (see FIGS. 8 and 9) or with the board assembled (installed) in the game machine main body. The rear surface 98b of 98 cannot be touched by a tester because it is shaded by the presentation interface board 96 and the liquid crystal interface board 97 facing each other. Therefore, in this embodiment, as shown in FIG. 56, the display of "TP23", which is the identification information indicating the test point TP23, is displayed on the wiring path cp421 side where the test point TP23 is arranged, that is, not on the back surface 98b side but on the front surface. It is arranged on the 98a side. Since the test point TP23 is configured by the via v203 penetrating the substrate body 190, it is possible to apply the tester from the surface 98a side of the substrate body 190 as well.

The test point TP17 is provided in the via v204 that connects the wiring path cp418 on the first wiring layer La1 side and the wiring path cp419 on the sixth wiring layer La6 side. The display of "TP17" is also arranged on the surface 98a side like the test point TP23.

The same applies to the other test points TP28 and TP33 described above. That is, the test point TP28 is provided on the wiring path cp3 of the third wiring layer La3, but the display of "TP28", which is the identification information indicating the test point TP28, is arranged on the surface 98a side. Also, the test point TP33 is provided on the wiring path cp505 of the sixth wiring layer La6, but the display of "TP33", which is the identification information indicating this test point TP33, is arranged on the surface 98a side.

Next, wiring paths P46 and P47 connected to the 8/16-bit mode selection terminal BYTE#, writable input terminal WE#, and write inhibit/program input terminal WP#/ACC of the control ROM 105 will be described. These wiring paths P46 and P47 are not connected to the composite chip 104. FIG.

In the wiring path P46 (FIG. 50), as shown in FIG. 35, the terminal connection portion BYTE# provided in the control ROM arrangement area 192 of the first wiring layer La1 is connected to the via v48 by the wiring path cp531. The via v48 is arranged in the vicinity of the terminal connection portion BYTE# on the outside (-X side) of the control ROM arrangement area 192, and as shown in FIG. It is connected. Thus, in this embodiment, the 16-bit communication mode is selected by connecting the 8/16-bit mode selection terminal BYTE# of the control ROM 105 to the power supply (H level).

In the wiring path P47 (FIG. 50), as shown in FIG. 35, the terminal connection portion WE# (first predetermined terminal) provided in the control ROM arrangement region 192 of the first wiring layer La1 is connected to the via v111 by the wiring path cp541. is connected with This via v111 (first predetermined inter-layer conductive portion) is arranged near the terminal connection portion WE# on the outside (+X side) of the control ROM arrangement area 192, and as shown in FIG. is connected to DC 3.3V through As described above, in this embodiment, the writable input terminal WE# of the control ROM 105 is connected to the power supply (H level), so that when it is at H level (when not reading), it is in the output disabled mode, and when it is at L level (when it is reading). ), the mode can be switched according to the value (H/L) of the output enable input terminal OE#. Output enable input terminal OE# is connected to read strobe output terminal HRD of composite chip 104 as described above.

In the wiring path P47, as shown in FIG. 35, the terminal connection portion WP#/ACC (second predetermined terminal) provided in the control ROM arrangement area 192 of the first wiring layer La1 is connected to the via v112 by the wiring path cp542. It is connected. The via v112 is arranged near the terminal connection portion WP#/ACC outside the control ROM arrangement area 192 (on the +X side). As shown in FIG. 33, the via v112 (second predetermined inter-layer conductive portion) is connected to the via v111 through a resistor R43 by a wiring path cp543 provided in the sixth wiring layer La6. This via v111 is connected to DC 3.3V through the fifth wiring layer La5 as described above. As described above, in this embodiment, the write inhibit/program input terminal WP#/ACC of the control ROM (specific electronic component) 105 is connected to the power supply (H level), so that it is set to be writable and program executable. ing. Also, by connecting to the power supply via a resistor R43, an input exceeding the H level is eliminated and the H level is stably maintained.

For example, depending on the type of control ROM, when there is an input exceeding the H level, if a mode setting different from write prohibition/permission and program execution prohibition/permission is performed, Even if the input exceeds the H level due to noise, etc., the control ROM is set to a mode different from prohibition/permission of writing and prohibition/permission of program execution by configuring to be stably at H level. It is possible to prevent this from happening.

Next, by connecting the decoder IC 13 and the liquid crystal control second connector CN32, wiring for transmitting the power supply control signals PS1 and PS2, the backlight ON/OFF control signal XSTABY1, and the PWM signal VBR1 for backlight dimming, respectively. The roads P48-P51 will be explained. The connections between the data input/output terminals HDT0 to HDT7 of the composite chip 104 and the decoder IC13 are already described as the wiring paths P27 to P34 (FIG. 48). In the liquid crystal control second connector CN32, a large number of terminals are arranged in two rows along the longitudinal direction (X direction). They are arranged along the second edge 195b on the −Y side.

A wiring path P48 (FIG. 51) transmits the power supply control signal PS1, and as shown in FIG. It is As shown in FIG. 30, the via v211 is connected to the via v212 through a wiring path cp552 arranged in the third wiring layer La3. As shown in FIG. 44, the via v212 is connected to the terminal connection portion ps1 of the liquid crystal control second connector CN32 via the wiring path cp553 arranged in the sixth wiring layer La6, and the second connector arrangement region 195 is connected to the second connector arrangement region 195. It is connected from the outside (-Y side).

A wiring path P49 (FIG. 51) transmits a power supply control signal PS2, and as shown in FIG. It is As shown in FIG. 30, the via v221 is connected to the via v222 through a wiring path cp562 arranged in the third wiring layer La3. As shown in FIG. 44, the via v222 is connected to the terminal connection portion ps2 of the liquid crystal control second connector CN32 via the wiring path cp563 arranged in the sixth wiring layer La6, and the second connector arrangement region 195 is connected to the second connector arrangement region 195. It is connected from the outside (-Y side).

A wiring path (B wiring path) P50 (FIG. 51) is for transmitting the backlight ON/OFF control signal XSTABY1, and as shown in FIG. pulled out to the side and connected to the via v231. As shown in FIG. 30, the via v231 is connected to the via v232 through a wiring path cp572 arranged in the third wiring layer La3. As shown in FIG. 44, the via v232 is connected to the terminal connection portion xstaby1 of the liquid crystal control second connector CN32 via the wiring path cp573 arranged in the sixth wiring layer La6, and the second connector arrangement region 195 is connected to the second connector arrangement region 195. It is connected from the outside (-Y side).

A wiring path (B wiring path) P51 (FIG. 51) is for transmitting the backlight dimming PWM signal VBR1, and as shown in FIG. pulled out to the side and connected to the via v241. As shown in FIG. 30, the via v241 is connected to the via v242 through a wiring path cp582 arranged in the third wiring layer La3. As shown in FIG. 44, the via v242 is connected to the terminal connection portion vbr1 of the liquid crystal control second connector CN32 via the wiring path cp583 arranged in the sixth wiring layer La6, and the second connector arrangement region 195 is connected to the second connector arrangement region 195. It is connected from the outside (-Y side).

Subsequently, the data output terminals RA0+, RA0-, RA1+, RA1-, RA2+, RA2-, RA3+, RA3-, RACLK+, RACLK- (hereinafter referred to as ODD side data output terminal group) of the composite chip 104 and the liquid crystal control terminal 2 wiring paths (first wiring path, A wiring path) P52 to P61 connecting with 2 connectors CN32, data output terminals RB0+, RB0-, RB1+, RB1-, RB2+, RB2-, RB3+, RB3-, RBCLK+, RBCLK - (hereinafter referred to as EVEN data output terminal group) and the liquid crystal control second connector CN32. The wiring lines P52 to P61 constitute a first transmission line LVDS1 for transmitting ODD signals, and the wiring lines P62 to P71 constitute a second transmission line LVDS2 for transmitting EVEN signals.

The group of ODD-side data output terminals (first chip terminals) of the composite chip 104 are arranged in two rows along the second edge 191b of the composite chip placement area 191, as shown in FIGS. arrayed. That is, the data output terminals RA0−, RA1−, RA2−, RACLK−, RA3− are arranged in that order in the −X direction on the outermost side of the composite chip placement area 191, and the data output terminals are arranged inside them. RA0+, RA1+, RA2+, RACLK+ and RA3+ are arranged in that order in the -X direction.

Also, the EVEN side data output terminal group (second chip terminal) of the composite chip 104 is located inside the composite chip arrangement area 191 with respect to the ODD side data output terminal group, as shown in FIGS. are arranged in two rows. That is, data output terminals RB0-, RB1-, RB2-, RBCLK-, RB3- are arranged in that order in the -X direction inside the group of ODD-side data output terminals, with the GND terminal row interposed therebetween. Inside, data output terminals RB0+, RB1+, RB2+, RBCLK+, RB3+ are arranged in that order in the -X direction.

Further, the second connector arrangement area 195 in which the liquid crystal control second connector CN32 is arranged is located on the side of the second edge 191b of the composite chip arrangement area 191, as shown in FIGS. arranged in an elongated shape parallel to the In the liquid crystal control second connector CN32, a large number of terminals are arranged in two rows along the longitudinal direction (X direction), and as shown in FIG. , ra0+, ra1−, ra1+, ra2−, ra2+, raclk−, raclk+, ra3−, ra3+ are arranged in the −X direction along the first edge 195a on the −Y side of the second connector arrangement region 195, Connector terminals rb0−, rb0+, rb1−, rb1+, rb2−, rb2+, rbclk−, rbclk+, rb3−, rb3+ corresponding to the EVEN data output terminal group are located on the second edge on the +Y side of the second connector arrangement area 195. They are arranged in the -X direction along the portion 195b.

First, wiring lines (first wiring lines) P52 to P61 (FIG. 52) forming the first transmission line LVDS1 will be described. In the wiring path P52 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA0− provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 by the wiring path cp601. It is connected to a via (specific inter-layer conductive portion) v251 arranged (near the connector). As shown in FIG. 44, the via v251 is connected to the terminal connection portion ra0− from inside the second connector placement region 195 by the wiring path cp602 of the sixth wiring layer La6.

In the wiring path P53 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA0+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 ( It is connected to a via (specific inter-layer conductive portion) v252 arranged in the vicinity of the connector). The wiring path cp603 is drawn out of the composite chip placement area 191 through between the terminal connection portion RA0- and the adjacent terminal connection portion RA1-. That is, the two wiring paths cp601 and cp603 forming the actuation signal line RA0 are arranged side by side in parallel. As shown in FIG. 44, the via v252 is connected to the terminal connection portion ra0+ from inside the second connector placement region 195 by the wiring path cp604 of the sixth wiring layer La6.

In the wiring path P54 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA1− provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 by the wiring path cp605. It is connected to a via (specific inter-layer conductive portion) v253 arranged (near the connector). As shown in FIG. 44, the via v253 is connected to the terminal connection portion ra1- from inside the second connector placement region 195 by the wiring path cp606 of the sixth wiring layer La6.

In the wiring path P55 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA1+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 ( It is connected to a via (specific inter-layer conductive portion) v254 arranged in the vicinity of the connector). The wiring path cp607 is led out of the composite chip placement area 191 through between the terminal connection portion RA1- and the adjacent terminal connection portion RA2-. That is, the two wiring paths cp605 and cp607 forming the actuation signal line RA1 are arranged side by side in parallel. As shown in FIG. 44, the via v254 is connected to the terminal connection portion ra1+ from inside the second connector placement region 195 by the wiring path cp608 of the sixth wiring layer La6.

In the wiring path P56 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA2− provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 by the wiring path cp609. It is connected to a via (specific inter-layer conductive portion) v255 arranged (near the connector). As shown in FIG. 44, the via v255 is connected to the terminal connection portion ra2− from inside the second connector placement region 195 by the wiring path cp610 of the sixth wiring layer La6.

In the wiring path P57 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA2+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 ( It is connected to a via (specific inter-layer conductive portion) v256 arranged in the vicinity of the connector). The wiring path cp611 is led out to the outside of the composite chip placement area 191 through between the terminal connection portion RA2- and the adjacent terminal connection portion RACLK-. That is, the two wiring paths cp609 and cp611 forming the actuation signal line RA2 are arranged side by side in parallel. As shown in FIG. 44, the via v256 is connected to the terminal connection portion ra2+ from inside the second connector placement region 195 by the wiring path cp612 of the sixth wiring layer La6.

In the wiring path P58 (FIG. 52), as shown in FIG. 36, the terminal connection portion RACLK− provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 by the wiring path cp613. It is connected to a via (specific inter-layer conductive portion) v257 arranged (near the connector). As shown in FIG. 44, the via v257 is connected to the terminal connection portion raclk- from inside the second connector placement region 195 by the wiring path cp614 of the sixth wiring layer La6.

In the wiring path P59 (FIG. 52), as shown in FIG. 36, the terminal connection portion RACLK+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 ( It is connected to a via (specific inter-layer conductive portion) v258 arranged in the vicinity of the connector). The wiring path cp615 is drawn out of the composite chip placement area 191 through between the terminal connection portion RACLK- and the adjacent terminal connection portion RA3-. That is, the two wiring paths cp613 and cp615 forming the actuation signal line RACLK are arranged side by side in parallel. As shown in FIG. 44, the via v258 is connected to the terminal connection portion raclk+ from inside the second connector placement region 195 by the wiring path cp616 of the sixth wiring layer La6.

In the wiring path P60 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA3− provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 by the wiring path cp617. It is connected to a via (specific inter-layer conductive portion) v259 arranged (near the connector). As shown in FIG. 44, the via v259 is connected to the terminal connection portion ra3− from inside the second connector placement region 195 by the wiring path cp618 of the sixth wiring layer La6.

In the wiring path P61 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA3+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the second connector placement area 195 ( It is connected to a via (specific inter-layer conductive portion) v260 arranged in the vicinity of the connector). Note that the wiring path cp619 is led out to the outside of the composite chip placement area 191 via the -X side of the terminal connection portion RA3-. That is, the two wiring paths cp617 and cp619 forming the actuation signal line RA3 are arranged side by side in parallel. As shown in FIG. 44, the via v260 is connected to the terminal connection portion ra3+ from inside the second connector placement region 195 by the wiring path cp620 of the sixth wiring layer La6.

In the first wiring layer La1, as shown in FIG. 36, between the wiring paths cp601 and cp603 forming the operating signal line RA0 and the wiring paths cp605 and cp607 forming the operating signal line RA1, the operating signal line RA1 is provided. and the wiring paths cp609 and cp611 forming the actuation signal line RA2, the wiring paths cp609 and cp611 forming the actuation signal line RA2 and the wiring paths cp613 and cp615 forming the actuation signal line RACLK. , and between the wiring paths cp613 and cp615 forming the actuation signal line RACLK and the wiring paths cp617 and cp619 forming the actuation signal line RA3, respectively, ground wiring paths gp1 to gp4 are arranged. The ground wiring paths gp1 to gp4 are formed in an elongated shape with a substantially constant width.

Next, wiring lines (second wiring lines) P62 to P71 (FIG. 53) forming the second transmission line LVDS2 will be described. In the wiring path P62 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB0− provided in the composite chip placement region 191 of the first wiring layer La1 is connected to the vicinity of the diagonal +XY direction by the wiring path cp621. is connected to a via v261 located in the . The via v261 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB0−) arranged around it. As shown in FIG. 44, the via v261 is connected to the terminal connection portion rb0− from the outside of the second connector placement region 195 by the wiring path cp622 of the sixth wiring layer La6.

In the wiring path P63 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB0+ provided in the composite chip arrangement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp623. It is connected to the placed via v262. The via v262 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB0+) arranged around it. As shown in FIG. 44, the via v262 is connected to the terminal connection portion rb0+ from outside the second connector placement region 195 by the wiring path cp624 of the sixth wiring layer La6. Note that the wiring path cp624 is led out to the outside of the composite chip placement area 191 via the +X side of the via v261. That is, the two wiring paths cp622 and cp624 forming the actuation signal line RB0 are arranged side by side in parallel.

In the wiring path P64 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB1− provided in the composite chip arrangement region 191 of the first wiring layer La1 is connected to the vicinity of the diagonal +XY direction by the wiring path cp625. is connected to a via v263 located in the . The via v263 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB1−) arranged around it. As shown in FIG. 44, the via v263 is connected to the terminal connection portion rb1- from the outside of the second connector arrangement region 195 by the wiring path cp626 of the sixth wiring layer La6.

In the wiring path P65 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB1+ provided in the composite chip arrangement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp627. It is connected to the placed via v264. The via v264 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB1+) arranged around it. As shown in FIG. 44, the via v264 is connected to the terminal connection portion rb1+ from outside the second connector placement region 195 by the wiring path cp628 of the sixth wiring layer La6. Note that the wiring path cp628 is led out to the outside of the composite chip placement area 191 through the via v263 and the adjacent via v261. That is, the two wiring paths cp626 and cp628 forming the actuation signal line RB1 are arranged side by side in parallel.

In the wiring path P66 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB2− provided in the composite chip placement region 191 of the first wiring layer La1 is connected to the vicinity of the diagonal +XY direction by the wiring path cp629. is connected to via v265 located in The via v265 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB2−) arranged around it. As shown in FIG. 44, the via v265 is connected to the terminal connection portion rb2− from the outside of the second connector placement region 195 by the wiring path cp630 of the sixth wiring layer La6.

In the wiring path P67 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB2+ provided in the composite chip arrangement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp631. It is connected to a placed via v266. The via v266 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB2+) arranged around it. As shown in FIG. 44, the via v266 is connected to the terminal connection portion rb2+ from outside the second connector placement region 195 by the wiring path cp632 of the sixth wiring layer La6. The wiring path cp632 is drawn out of the composite chip placement area 191 through the via v265 and the adjacent via v263. That is, the two wiring paths cp630 and cp632 forming the actuation signal line RB2 are arranged side by side in parallel.

In the wiring path P68 (FIG. 53), as shown in FIG. 36, the terminal connection portion RBCLK− provided in the composite chip placement region 191 of the first wiring layer La1 is connected to the vicinity of the diagonal +XY direction by the wiring path cp633. is connected to the via v267 located in the . The via v267 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RBCLK−) arranged around it. As shown in FIG. 44, the via v267 is connected to the terminal connection portion rbclk- from outside the second connector placement region 195 by the wiring path cp634 of the sixth wiring layer La6.

In the wiring path P69 (FIG. 53), as shown in FIG. 36, the terminal connection portion RBCLK+ provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp635. It is connected to the placed via v268. The via v268 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RBCLK+) arranged around it. As shown in FIG. 44, the via v268 is connected to the terminal connection portion rbclk+ from outside the second connector placement region 195 by the wiring path cp636 of the sixth wiring layer La6. The wiring path cp636 is led out to the outside of the composite chip placement area 191 through the via v267 and the adjacent via v265. That is, the two wiring paths cp634 and cp636 forming the actuation signal line RBCLK are arranged side by side in parallel.

In the wiring path P70 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB3− provided in the composite chip placement region 191 of the first wiring layer La1 is connected to the vicinity of the diagonal +XY direction by the wiring path cp637. is connected to via v269 located in The via v269 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB3−) arranged around it. As shown in FIG. 44, the via v269 is connected to the terminal connection portion rb3- from outside the second connector arrangement region 195 by the wiring path cp638 of the sixth wiring layer La6.

In the wiring path P71 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB3+ provided in the composite chip placement region 191 of the first wiring layer La1 is arranged in the vicinity of the diagonal +XY direction by the wiring path cp639. It is connected to the placed via v270. The via v270 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion RB3+) arranged around it. As shown in FIG. 44, the via v270 is connected to the terminal connection portion rb3+ from outside the second connector placement region 195 by the wiring path cp640 of the sixth wiring layer La6. The wiring path cp640 is led out to the outside of the composite chip placement area 191 through the via v269 and the adjacent via v267. That is, the two wiring paths cp638 and cp640 forming the actuation signal line RB3 are arranged side by side in parallel.

Note that, as shown in FIG. 44, the sixth wiring layer La6 includes the operating signal line RB1 between the wiring paths cp622 and cp624 forming the operating signal line RB0 and the wiring paths cp626 and cp628 forming the operating signal line RB1. and the wiring paths cp630 and cp632 forming the actuation signal line RB2, the wiring paths cp630 and cp632 forming the actuation signal line RB2 and the wiring paths cp634 and cp636 forming the actuation signal line RBCLK. , and between the wiring paths cp634, cp636 constituting the operating signal line RBCLK and the wiring paths cp638, cp640 constituting the operating signal line RB3, ground wiring paths gp11 to gp14 are arranged, respectively. The ground wiring paths gp11 to gp14 are formed in an elongated shape with a substantially constant width.

As described above, in the wiring patterns shown in FIGS. 36 and 44, the ground wiring paths gp1 to gp4 and gp11 to gp14 are arranged between a plurality of wiring path pairs (five sets each) constituting the operating signal lines. This is to reduce noise to wiring paths cp601, cp622, etc. around these ground wiring paths gp1-gp4, gp11-gp14. As shown in FIGS. 36 and 44, the ground wiring paths gp1 to gp4 and gp11 to gp14 are preferably wider than the surrounding wiring paths cp601 and cp622. This is because the surrounding wiring paths cp601, cp622, etc. are wiring paths for transmitting image data, so that they are designed to be more noise-resistant so that the pattern images on the screen do not become difficult to see due to noise. .

The ground wiring paths gp1 to gp4 on the first wiring layer La1 side and the ground wiring paths gp11 to gp14 on the sixth wiring layer La6 side are, as shown in FIGS. are connected to each other via , which makes it possible to further reduce noise.

Further, as shown in FIGS. 36 and 44, the ground wiring paths gp1 to gp4 on the first wiring layer La1 side and the ground wiring paths gp11 to gp14 on the sixth wiring layer La6 side are different from each other according to the surrounding wiring patterns. Although it has a shape, it is configured to partially pass through mutually corresponding locations (regions), and is connected via through holes (vias) at the corresponding locations (here, multiple locations). While adopting a shape that corresponds to the surrounding wiring pattern, it is possible to make the wiring pattern more noise-resistant and efficient.

To summarize the configuration of the wiring paths P1 to P71 described above, among the wiring paths P2 to P45 connecting the composite chip 104 and the control ROM 105, the wiring paths P2 to P43 and P45 (specific wiring paths) are shown in FIG. , as shown in FIGS. 45 to 50, vias v60 to v108 (specific inter-layer conductive portions; vias indicated in gray in FIGS. 45 to 50) arranged in the control ROM arrangement area (second arrangement area) 192 are Further, wiring paths P2 to P16, P19 to P23, P35 to P43, and P45 (first specific wiring paths) among them are connected to terminal connections on the control ROM 105 side. The parts A0 to A14, A17 to A21, Q8 to Q15, CE#, and RESET# are connected from the inside of the control ROM arrangement area 192 (wiring lines indicated by thick lines in FIGS. 45 to 50). Thus, the wiring path connecting the composite chip 104 and the control ROM 105 is arranged so as to pass through the control ROM arrangement area 192 which has a relatively large space, and the terminals of the control ROM 105 are connected as much as possible. By connecting from the inside of the control ROM arrangement area 192, the wiring patterns on the substrate can be arranged more efficiently, and the limited space can be used more effectively.

Wiring connecting vias v60 to v108 (specific inter-layer conductive portions) arranged in the control ROM arrangement area (second arrangement area) 192 to terminal connection parts on the control ROM 105 side from outside the control ROM arrangement area 192 The wiring paths cp165, cp175, cp234, cp244, cp254, cp343, cp353, cp363, cp373, cp303, cp313, cp323, and cp333 have the length of the control ROM placement area 192 as shown in FIG. It is arranged so as to cross sides 192a and 192b on the outside of each terminal connection portion. By configuring in this way, the wiring length can be shortened compared to the case of wiring avoiding the control ROM arrangement area 192, so that the wiring efficiency can be improved and noise can be reduced. In addition, since the control ROM 105 is actually located in the range indicated by the control ROM arrangement area 192, the wiring pattern cannot be visually observed, and therefore unauthorized access to the wiring pattern can be prevented. It is possible.

Also, a wiring path connected in the first wiring layer La1 to the vias v60 to v108 (specific inter-layer conductive portions) arranged in the control ROM placement area (second placement area) 192, specifically, the wiring path cp233. , cp243 and cp253 are also arranged so as to cross the long side 192a of the control ROM arrangement area 192 outside the respective terminal connection portions, as shown in FIG. By adopting such a configuration at a plurality of locations together with the configuration in the preceding paragraph, the effect described in the preceding paragraph becomes more effective.

A ROM socket 193 (FIG. 8) is fixed to the control ROM arrangement area 192, and the bottom wall (shielding wall corresponding to the specific inter-layer conduction part) 193a of the ROM socket 193 shields the control ROM arrangement area 192. Even when the control ROM 105 is removed from the ROM socket 193, the wiring pattern in the control ROM arrangement area 192 including the vias v60 to v108 (specific inter-layer conduction portions) cannot be visually recognized from the outside and cannot be accessed.

The vias v60 to v108 (specific inter-layer conductive portions) in the control ROM arrangement area 192 penetrate from the front surface (first surface) 98a to the rear surface (second surface) 98b of the substrate body 190, thereby enhancing the heat radiation effect. Also, the vias v60 to v108 (specific interlayer conductive portions) in the control ROM arrangement area 192 are connected to predetermined electronic components such as ICs, resistors, capacitors, connectors, etc. on the back surface 98b side, that is, on the sixth wiring layer La6 side. .

As for the wiring paths P2 to P45 connecting the composite chip 104 and the control ROM 105, the first wiring portion connecting the composite chip 104 and a predetermined via (predetermined inter-layer conductive portion) is connected to the predetermined via and the control ROM 105. and a third wiring portion for connecting predetermined vias to other electronic components such as the liquid crystal control first connector CN31. Then, the second wiring portion is formed in a first predetermined wiring layer such as the first wiring layer La1, and the third wiring portion is formed in a second predetermined wiring layer such as a third wiring layer La3 and a sixth wiring layer La6 which are different from the first predetermined wiring layer. They are arranged in wiring layers, respectively.

Among the wiring paths P2 to P45, for the wiring paths P2 to P42 for transmitting address/data information, predetermined vias (predetermined inter-layer conductive portions) serving as branch points are located in the control ROM layout area (second layout area). ) 192 (vias indicated in gray in FIGS. 45 to 50), the second wiring portion is the first wiring layer La1, and at least a part of the first wiring portion are provided in the fourth wiring layer La4 (an example of a predetermined wiring layer different from the first wiring layer), and the third wiring portion is provided in the first wiring layer La1 (first predetermined wiring layer). This makes it possible to improve the preventiveness against fraudulent acts such as unauthorized modification of wiring patterns and vias for transmitting address/data information. By drawing wiring patterns in the control ROM arrangement area 192, wiring space can be secured in other areas. In addition, particularly at branch points, wiring patterns tend to be densely packed over multiple layers of the substrate, so a sufficient wiring space is required at the branch point. It is effective to place the branch point in the control ROM placement area 192 with the .

In addition, among the vias v60 to v107 (specific inter-layer conductive portions) in the control ROM arrangement area 192, the vias v61 to v85 and v103 forming part of the wiring paths P2 to P26 (address wiring) for transmitting address information. ∼ v107 (first specific interlayer conduction portion) and vias v87 to v102 (second specific interlayer conduction portion) forming part of wiring paths P27 to P42 (data wiring) for transmitting data information are controlled. They are arranged in the Y direction (first direction), which is the arrangement direction of the terminals in the ROM 105 .

Address output terminals HAD1 to HAD25 and data input/output terminals HDT0 to HDT15 (first terminal) on the composite chip 104 side, and corresponding address input terminals A0 to A24 and data input/output terminals Q0 to Q15 on the control ROM 105 side. The wiring paths P2 to P42 connecting them have vias v60 to v85 and v87 to v107 (specific inter-layer conductive portions) in the control ROM arrangement area 192, The arrangement of vias v60 to v85 and v87 to v107 (specific inter-layer conduction portions) in the control ROM arrangement area 192 is approximated to the arrangement of corresponding terminals (specific second terminals) on the control ROM 105 side. As a result, it is possible to arrange the wiring patterns that connect the specific interlayer conductive portions and the terminals of the control ROM, and for example, there is no need to arrange the patterns so that the positional relationship between a plurality of wiring patterns changes (twists). Therefore, the connection method is easier, and the space in the control ROM arrangement area 192 can be used more effectively. In this way, when the terminal arrangement of the composite chip 104 and the terminal arrangement of the control ROM 105 are different, a wiring pattern with a relatively short wiring distance from the specific inter-layer conductive portion in the arrangement area of the control ROM 105 to the terminals of the control ROM 105 can be used. Rather than devising the routing of the specific interlayer conductive portion, by devising the routing of a wiring pattern having a relatively long wiring distance from the composite chip 104 to the specific interlayer conductive portion, the arrangement of the specific interlayer conductive portion is approximated to the terminal arrangement of the control ROM 105. is more effective in terms of wiring efficiency.

Specifically, as shown in FIG. 35, for example, address input terminals A0 to A6 and corresponding vias v85 to v79, address input terminals A17 to A20 and corresponding vias v68 to v64, and data input/output terminals Q12 to Q15. and vias v90 to v87 corresponding thereto are arranged in substantially the same order in the Y direction. , data input/output terminals Q0 to Q3 and corresponding vias v102 to v99, data input/output terminals Q8 to Q11 and corresponding vias v94 to v91, data input/output terminals Q4 to Q7 and corresponding vias v98 to v95 , are arranged in substantially reversed order in the Y direction. In this way, rather than considering only the terminal arrangement of the control ROM 105 and devising the arrangement of the specific interlayer conductive portions, the terminal arrangement on the side of the composite chip 104 and the terminal arrangement on the liquid crystal control first connector CN31 side, which are also connected in the same manner, are not devised. Considering the above, the specific inter-layer conductive portions may be arranged. Although this partly complicates the connection relationship with the control ROM 105, the connection between the composite chip 104 and the liquid crystal control first connector CN31 side located farther than the terminals of the control ROM 105 is based on the specified inter-layer conduction portion. Since the connection relationship with the terminals is simplified, it is possible to improve the wiring efficiency of the entire board. That is, in the control ROM arrangement area 192, the wiring efficiency of the entire substrate can be improved by devising the arrangement of the specific inter-layer conductive portions as necessary. Also, the wiring efficiency of the entire substrate can be improved not only within the control ROM placement area 192, but also by devising the arrangement of vias serving as branch points as described above.

Address output terminals HAD1 to HAD25 and data input/output terminals HDT0 to HDT15 (first terminals) on the composite chip 104 side correspond to address input terminals A0 to A24 and data input/output terminals Q0 to Q15 on the control ROM 105 side. (the second terminal), but also the terminals had1 to had25 and hdt0 to hdt15 (the third terminal) of the liquid crystal control first connector CN31 are arranged differently. ) are made to match (approximately) the arrangement of the terminals had1 to had25 and hdt0 to hdt15 (third terminals) of the liquid crystal control first connector CN31. That is, as shown in FIGS. 37, 38, and 42, the vias v61 to v85 and v87 to v102 (specific inter-layer conductive portions) are arranged in the Y direction so that the corresponding terminals had1 to Since it matches the arrangement of had25 and hdt0 to hdt15 in the X direction, the wiring path group (third wiring path group) connecting them can be arranged in parallel without twisting. It should be noted that, as a result, a wiring path group ( The second wiring path group) has a complicated wiring pattern including twists, but this can be easily realized by arranging it in the control ROM arrangement area 192 which has a relatively large space.

Of the wiring paths P2 to P42 for transmitting address/data information, wiring paths P2 to P13 and P19 to P42 are vias v61 to v68, v74 to v85, and v87 to v102 ( The wiring paths P14 to P18 are branched to the control ROM 105 side and the liquid crystal control first connector CN31 side at the specific inter-layer conduction portion). Vias v103 to v107 are separately provided in the control ROM arrangement area 192 on the wiring path connecting the vias v69 to v73 and the liquid crystal control first connector CN31 without branching, and the vias v103 to v107 branch to the control ROM 105 side. ing. With this configuration, the wiring to the liquid crystal control first connector CN31 is arranged in parallel without being twisted in harmony with other wiring paths, and the wiring to the control ROM 105 is also prevented from interfering with other wiring paths. It is possible to efficiently arrange while avoiding.

Further, specific one end terminals A0 to A7, A17, A18, A20, A21, Q0 to Q3, Q8 to Q11 included in one end terminals arranged on one end side of the control ROM (second electronic component) 105 and The corresponding first specific terminals HAD0 to HAD7, HAD17, HAD18, HAD20, HAD21, HDT0 to HDT3, HDT8 to HDT11 on the side of the corresponding composite chip (first electronic component) 104 are connected to vias v65 to v68, v78 to v85, v91 to v94. , v99 to v102 (first interlayer conductive portions), a plurality of one end side wiring paths P2 to P9, P19, P20, P22, P23, P27 to P30, P35 to P38, a control ROM (second electronic Specific other-end terminals A8-A16, A19, A22-A24, Q4-Q7, Q12-Q15 included in the other-end terminals arranged on the other-end side of component) 105 and their corresponding composite chips (first The second specific terminals HAD8 to HAD16, HAD19, HAD22 to HAD24, HDT4 to HDT7, HDT12 to HDT15 on the electronic component) 104 side are connected to vias v61 to v63, v66, v74 to v77, v87 to v90, v95 to v98 (second a plurality of other end side wiring paths P10 to P18, P21, P24 to P26, P31 to P34, P39 to P42, which are connected to each other via a first interlayer conduction portion and a second interlayer conduction portion; are arranged close to each other so as to have different arrangements from those of the first specific terminal and second specific terminal and correspond to the specific one-end terminal and the specific other-end terminal, respectively.

In addition, internal connection wiring portions connected from the inside of the control ROM arrangement area 192 and external connection wiring portions connected from the outside are alternately arranged with respect to the plurality of ROM terminal connection portions arranged in a row. That is, as shown in FIG. 35, for the terminal connection portions Q0, Q8, Q1, Q9, Q2, Q10, Q3, Q11 of the control ROM arrangement area 192, external connection wiring portions cp303, cp313, cp323, cp333 and internal wiring portions are provided. The connection wiring portions cp383, cp393, cp403, and cp413 are alternately connected. Moreover, the vias v102 to v99 on the other end side of the external connection wiring portions cp303, cp313, cp323, and cp333 are arranged close to each other, and the vias v94 to v91 on the other end side of the internal connection wiring portions cp383, cp393, cp403, and cp413. are also arranged close to each other. Similarly, for the terminal connection portions Q15/A-1, Q7, Q14, Q6, Q13, Q5, Q12, and Q4 of the control ROM arrangement area 192, the internal connection wiring portions cp453, cp443, cp433, and cp423 are externally connected. The wiring portions cp373, cp363, cp353 and cp343 are alternately connected. Moreover, the vias v87 to v90 on the other end side of the internal connection wiring portions cp453, cp443, cp433, and cp423 are arranged close to each other, and the vias v95 to v98 on the other end side of the external connection wiring portions cp373, cp363, cp353, and cp343. are also arranged close to each other. In this way, by arranging and grouping the internal connection wiring portion and the external connection wiring portion in proximity to each other instead of the terminal arrangement of the control ROM 105, the routing of the wiring pattern can be simplified and the wiring efficiency can be improved. .

The first wiring paths P2 to P42 for transmitting address information or data information and the second wiring path P43 for transmitting chip select information are in different wiring layers. The layer La4 and the second wiring path P43 are connected to vias v61 to v85, v87 to v101 and v60 (specific inter-layer conductive portions) in the control ROM arrangement area 192 from the composite chip 104 side in the sixth wiring layer La6. In this way, by wiring the chip select signal, which is important in data transmission, using a wiring layer different from the wiring pattern for transmitting address information or data information, transmission of the wiring pattern for transmitting address information or data information can be achieved. It is possible to make it difficult for noise to get on the chip select signal, and it is possible to have a configuration that is resistant to noise. Further, by making the pattern of the wiring path for the chip select signal different from that of other wiring paths, it becomes relatively easy to specify the wiring of the chip select signal, and it is possible to check whether the wiring pattern is short-circuited. It is possible to relatively easily perform checks and energization checks.

Further, in the wiring path P45 constituting the reset circuit, the wiring paths cp418 to cp421 (reset first wiring paths) connecting the reset integrated circuit (reset IC) IC10 and the via v174 (predetermined interlayer conduction portion), and the via v174 Wiring paths cp413 to cp415 (reset second wiring path) connecting (predetermined interlayer conductive portion) and reset terminal HRESET of composite chip 104, via v174 (predetermined interlayer conductive portion) and reset terminal RESET# of control ROM 105 are connected. Wiring paths cp416 and cp417 (third reset wiring paths) are provided for connection, and a test point TP17 (first reset wiring path) penetrating the liquid crystal control board 98 in the board thickness direction is provided on the wiring paths cp418 to cp421 (first reset wiring path). test point) and test point TP23 (second test point), identification information "TP17" and "TP23" indicating these test points TP17 and TP23, liquid crystal control board 98 to another effect interface board 96, liquid crystal interface It is shown on the surface (first surface) 98a on the opposite side to the substrates 96 and 97 when assembled together with the substrate 97 and the like. The reset integrated circuit (reset IC) IC10 is arranged on the rear surface (second surface) 98b side. As a result, when the board is assembled (see FIGS. 8 and 9) or when the board is assembled (installed) in the game machine main body, the part of the wiring path where the test points TP17 and TP23 are arranged cannot be visually recognized. In spite of this, it is possible to easily perform checking work using the test points TP17 and TP23 based on the identification information displayed on the visible surface 98a side.

The wiring paths cp418 to cp421 (reset first wiring path) are arranged on the front surface (first surface) 98a side and the wiring path cp418 (first wiring path) on the rear surface (second surface) 98b side. Wiring paths cp420 and cp421 (second wiring paths) and a via v204 (reset first interlayer conduction portion) connecting them are provided, and a test point TP17 (first test point) is arranged in the via v204 to perform a test. Point TP23 (second test point) is placed on wiring path cp421 (second wiring path).

The control ROM (specific electronic component) 105 operates in an operation mode corresponding to the voltage level of the write inhibit/program input terminal WP#/ACC (second predetermined terminal), and the writable input terminal WE# (first A predetermined terminal) is connected to the power supply wiring path of the fifth wiring layer La5 via a via v111 (first predetermined interlayer conductive portion), and a write inhibit/program input terminal WP#/ACC (second predetermined terminal) is connected to a resistor It is connected to via v111 (first predetermined inter-layer conductive portion) through R43. A control ROM (specific electronic component) 105 is arranged on the surface (first surface) 98a of the liquid crystal control board 98, and a resistor R43 is arranged on the back surface (second surface) 98b. A write inhibit/program input terminal WP#/ACC (second predetermined terminal) and a resistor R43 are connected via the . Thus, the via for connecting WP#/ACC (second predetermined terminal) to the power supply wiring path via resistor R43 is commonly used as the via for connecting WE# (first predetermined terminal) to the power supply wiring path. , the number of vias can be reduced compared to connecting via individual vias.

A plurality of terminals are arranged in a matrix on the bottom surface of the composite chip 104. Out of the plurality of terminals, the outer terminals arranged near the outer periphery of the composite chip arrangement area (first arrangement area) 191, For example, the terminals HDT0, HDT1, HDT4, HDT5, etc. arranged in the second row on the outermost peripheral side and inside thereof are connected to the control ROM 105 by the first wiring paths P27, P28, P31, P32, etc., and are arranged inside the outer terminals. Arranged inner terminals such as terminals HDT2, HDT3, HDT6, etc. are connected to the control ROM 105 by second wiring paths P29, P30, P33, etc., and first wiring paths P27, P28, P31, P32, etc. are connected to the composite chip layout area. Vias v32, v31, v37, v46, etc. (first inter-layer conductive portions) arranged outside 191 and external terminals HDT0, HDT1, HDT4, HDT5, etc. are connected in a first wiring layer La1, and a second wiring path P29 is connected. , P30, P33, etc. connect the vias v24, v8, v17, etc. (second interlayer conductive portions) arranged inside the composite chip placement area 191 and the inner terminals HDT2, HDT3, HDT6, etc., on the first wiring layer La1. is doing. Further, the distances from the inner terminals HDT2, HDT3, HDT6, etc. to the vias v24, v8, v17, etc. (second interlayer conductive portions) are set to the distances from the outer terminals HDT0, HDT1, HDT4, HDT5, etc. It is shorter than the distance to (the first interlayer conductive portion).

Thus, in the composite chip 104 having a plurality of terminals arranged in a matrix, the outer terminals arranged in the vicinity of the outer periphery of the arrangement area of the composite chip 104 are connected to the vias arranged outside the composite chip 104. Therefore, a wiring space is generated near the outer periphery of the composite chip 104, and the wiring pattern of the inner terminal of the composite chip 104 can be easily routed to the outside of the composite chip, so that the wiring efficiency can be improved. As for the wiring space described above, since a wiring space in the vicinity of the outer periphery of the composite chip is generated in a plurality of wiring layers of the substrate, even if any wiring layer among the plurality of wiring layers is used, the wiring space may extend to the outside of the composite chip. It goes without saying that it becomes easy to wire the wiring pattern.

Wiring paths (first wiring paths) P52 to P61 for transmitting ODD signals (first signals) corresponding to odd-numbered pixels are connected to the first wiring layer (A wiring layer) La1 among the plurality of wiring layers La1 to La6. of the plurality of wiring layers La1 to La6 that transmit EVEN signals (second signals) corresponding to even-numbered pixels. They are arranged so that the ratio is the highest.

That is, the ODD side data output terminal group (first chip terminal) to which the wiring paths (first wiring paths) P52 to P61 are connected is the EVEN side data output terminals to which the wiring paths (second wiring paths) P62 to P71 are connected. The terminal group (second chip terminal) is arranged on the outer peripheral side of the composite chip 104, and the liquid crystal control second connector CN32 is arranged on the sixth wiring layer (B wiring layer) Lb6 side opposite to the composite chip 104. there is Wiring paths (first wiring paths) P52 to P61 connected to the group of ODD-side data output terminals (first chip terminals) are vias (specific inter-layer conductive portions) arranged near the liquid crystal control second connector CN32. ) v251 to v260 to the liquid crystal control second connector CN32, and the EVEN data output terminal group (second chip terminal) connected to the EVEN data output terminal group (second chip terminal) is connected to the EVEN data It is connected to the liquid crystal control second connector CN32 via vias (unspecified inter-layer conductive portions) v261 to v270 arranged near the output terminal group. With such a configuration, wiring paths (first wiring paths) P52 to P61 for transmitting the ODD signal (first signal) and wiring paths (second wiring paths) P62 to P7 for transmitting the EVEN signal (second signal) are provided. At the same time, it is possible to reduce the possibility of failure due to disconnection or noise, and disperse the risk.

A liquid crystal control second connector CN32 is arranged on the second edge (first side) 191b side of the composite chip 104, and a wiring path (A wiring path) P52 capable of transmitting an image data signal to the liquid crystal display means 76. . . . P71 are wiring paths ( B wiring paths P50 and P51 are led out from the first edge (second side) 191a side of the composite chip 104 and connected to the second connector terminals of the liquid crystal control second connector CN32. As a result, while shortening the wiring length of the wiring path (A wiring path) P52 to P71, the wiring path (A wiring path) P52 to P71 and the wiring path (B wiring path) P50, P51 are separated for efficient operation. Wiring is possible.

Next, the details of the wiring pattern and the like of the liquid crystal interface substrate 97 will be described. The liquid crystal interface substrate 97 has a plurality of wiring layers on the substrate body 220 (see FIG. 8), specifically, a first wiring layer Lb1 on the front surface (first surface) 97a side and a second wiring layer Lb1 on the back surface (second surface) 97b side. 6 wiring layers Lb6 and 2nd to 5th wiring layers Lb2 to Lb5 arranged therebetween, 6 layers in total of 1st to 6th wiring layers Lb1 to Lb6 (FIGS. 57 to 61). there is The second and fifth wiring layers Lb2 and Lb5 (FIG. 58) are solid wiring layers connected to the ground, and the fourth wiring layer Lb4 (FIG. 60) is a solid wiring layer connected to the power supply. Further, the substrate body 220 of the liquid crystal interface substrate 97 is provided with a large number of through-hole type vias (interlayer conductive portions) similarly to the liquid crystal control substrate 98, and the plurality of wiring layers Lb1 to Lb6 are provided with these vias (interlayer conductive portion).

In the following description, the directions and orientations of the wiring layers Lb1 to Lb6 in the plane are based on the XY coordinate system (see FIG. 8) common to the liquid crystal control board 98, and the vertical directions in FIGS. is the X direction, the horizontal direction is the Y direction, the upward/downward direction is the +X/−X direction (side), and the left/right direction is the +Y/−Y direction (side).

As shown in FIG. 57, the first wiring layer Lb1 of the liquid crystal interface board 97 includes liquid crystal IF first to third connector arrangement areas 221 to 223 in which liquid crystal IF first to third connectors CN21 to CN23 are arranged, Liquid crystal connection first and second connector placement regions 224 and 225 are provided in which the liquid crystal connection first and second connectors CN24 and CN25 are arranged.

The liquid crystal IF first connector arrangement region 221 is elongated in the X direction and arranged on the +X side in the vicinity of the +Y side edge of the first wiring layer Lb1. The liquid crystal IF second connector arrangement area 222 is elongated in the X direction and arranged on the -X side in the vicinity of the +Y side edge of the first wiring layer Lb1. The liquid crystal IF third connector arrangement area 223 is elongated in the X direction and is arranged slightly on the +X and -Y sides of the central portion of the first wiring layer Lb1. The liquid crystal connection first and second connectors CN24 and CN25 are both long and slender in the Y direction. They are arranged adjacent to each other so as to form the connecting second connector CN25.

Among the many wiring paths provided on the liquid crystal interface board 97, a plurality of wiring paths P101 to P124 connected to the liquid crystal display means 76 via the liquid crystal connection first and second connectors CN24 and CN25 will be focused on. The details will be described with reference to the drawings. 62 to 66 show only the portions forming the wiring paths P101 to P124, respectively, extracted from the wiring patterns of the first to sixth wiring layers Lb1 to Lb6 shown in FIGS. 57 to 61. , and FIGS. 67 to 72 are partially enlarged views thereof. 73 to 75 schematically show wiring routes of the wiring paths P101 to P124, and FIGS. 76 to 78 show circuit diagrams corresponding to the wiring paths P101 to P124.

First, the wiring lines P101 to P110 forming the first transmission line LVDS1 for transmitting the ODD signal will be described. The wiring paths P101 to P110 are the ODD side terminals ra0−, ra0+, ra1−, ra1+, ra2−, ra2+, raclk−, raclk+, ra3−, ra3+ in the liquid crystal IF third connector CN23, and the liquid crystal connection first connector. It is arranged to connect ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ in CN24.

The liquid crystal IF third connector CN23 is arranged in an elongated shape in the X direction as shown in FIG. The terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, and ra3+ are arranged in that order in the -X direction along the long side on the -Y side. The terminals ra0− and ra0+, ra1− and ra1+, ra2− and ra2+, raclk− and raclk+, and ra3− and ra3+ are arranged side by side. A predetermined number (here, one each) of GND terminals are arranged between them (not shown in FIG. 67).

The liquid crystal connection first connector CN24 is elongated in the Y direction as shown in FIG. are arranged, and as shown in FIG. 69, the ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ are arranged in that order in the +Y direction. arrayed.

In the wiring paths P101 to P110 (FIG. 73), as shown in FIG. 67, in the first wiring layer Lb1, terminal connection portions ra0−, ra0+, ra1−, ra1+, ra2− on the side of the liquid crystal IF third connector arrangement region 223 are connected. , ra2+, raclk-, raclk+, ra3-, and ra3+, wiring paths cp701 to cp710 are led out in the -Y direction, respectively. These wiring paths cp701 to cp710 change direction to the liquid crystal connection first connector CN24 side (-X side), and then pass through test points TP101 to TP110 as shown in FIGS. They are connected to the terminal connection portions ra0−, ra0+, ra1−, ra1+, ra2−, ra2+, raclk−, raclk+, ra3−, ra3+ on the first connector CN24 side.

In this manner, in the wiring paths P101 to P110, the terminal arrangement on the liquid crystal IF third connector CN23 side and the terminal arrangement on the liquid crystal connection first connector CN24 side match each other while facing each other. It is possible to arrange only the first wiring layer Lb1 without twisting without switching.

The wiring paths cp701 and cp702, the wiring paths cp703 and cp704, the wiring paths cp705 and cp706, the wiring paths cp707 and cp708, and the wiring paths cp709 and cp710 are arranged in parallel while maintaining substantially constant intervals. A ground pattern is arranged between each of the wiring paths. In addition, the five sets of wiring paths have meandering portions of different lengths, respectively, in order to make the wiring lengths uniform. Since the diameter of the test points TP101 to TP110 is larger than the minimum spacing between the wiring paths, the test points TP101 to TP110 are arranged with their axes shifted from the wiring paths cp701 to cp710 to increase the spacing. Adjacent pairs of test points, that is, a total of five pairs of test points, are alternately displaced in the X direction to avoid mutual interference.

The wiring paths P101 to P110 are branched from the wiring paths cp701 to cp710 at the test points TP101 to TP110, and are connected to the ground (second wiring layer Lb2) via protective diodes arranged on the sixth wiring layer Lb6 side. there is That is, the wiring paths P101 and P102 are connected to the protection diode D103, the wiring paths P103 and P104 are connected to the protection diode D105, the wiring paths P105 and P106 are connected to the protection diode D102, the wiring paths P107 and P108 are connected to the protection diode D104, and the wiring paths P109 and P109 are connected to the protection diode D105. P110 are each connected to a protection diode D101.

Next, wiring lines P111 to P120 forming the second transmission line LVDS2 for transmitting the EVEN signal will be described. The wiring paths P111 to P120 are connected to EVEN-side terminals rb0−, rb0+, rb1−, rb1+, rb2−, rb2+, rbclk−, rbclk+, rb3−, rb3+ in the liquid crystal IF third connector CN23, and the liquid crystal connection first connector. It is arranged to connect the EVEN side terminals rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ in CN24.

The arrangement of the EVEN-side terminals in the liquid crystal IF third connector CN23 is opposite to the arrangement of the ODD-side terminals in +/−. That is, as shown in FIG. 67, the EVEN-side terminals in the liquid crystal IF third connector CN23 are arranged along the long side on the +Y side with rb0+, rb0-, rb1+, rb1-, rb2+, rb2-, rbclk+, rbclk-, rb3+. , rb3- in the -X direction. The terminals rb0+ and rb0−, rb1+ and rb1−, rb2+ and rb2−, rbclk+ and rbclk−, and rb3+ and rb3− are arranged side by side. A predetermined number (here, one each) of GND terminals are arranged between them (not shown in FIG. 67).

On the other hand, the arrangement of the EVEN-side terminals in the liquid crystal connection first connector CN24 is common to the arrangement of the ODD-side terminals. That is, as shown in FIG. 69, the EVEN-side terminals of the liquid crystal IF third connector CN23 are connected to the +Y side of the ODD-side terminals by rb0−, rb0+, rb1−, rb1+, rb2−, rb2+, rbclk−, rbclk+, rb3 They are arranged in the +Y direction in the order of -, rb3+.

Comparing the EVEN terminal on the third liquid crystal IF connector CN23 side (FIG. 67) and the EVEN terminal on the liquid crystal connection first connector CN24 side (FIG. 69) facing each other, the arrangement of both is rb0, The five sets of terminal pairs rb1, rb2, rbclk, and rb3 are arranged in the opposite order. Therefore, the wiring paths that connect them are twisted with each other, so unlike the wiring paths on the ODD side, it is necessary to wire across a plurality of wiring layers.

In the wiring paths P111 to P120 (FIG. 74), as shown in FIG. 67, in the first wiring layer Lb1, the terminal connection portions rb0−, rb0+, rb1−, rb1+, rb2− on the side of the liquid crystal IF third connector arrangement region 223 are connected. , rb2+, rbclk-, rbclk+, rb3- and rb3+, wiring paths cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp732, cp735 and cp738 are led out in the +Y direction, respectively. These wiring paths cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738 change direction to the liquid crystal connection first connector CN24 side (-X side), and then vias v301 to v310.

The wiring paths cp711 and cp714, the wiring paths cp717 and cp720, the wiring paths cp723 and cp726, the wiring paths cp729 and cp732, and the wiring paths cp735 and cp738 are arranged in parallel while maintaining substantially constant intervals. Ground patterns are arranged between the paths, respectively.

Here, v301 to v310 correspond to five sets of terminal pairs rb0, rb1, rb2, rbclk, and rb3, and are arranged two by two so as to be adjacent to each other in the X direction. , cp714 are located on the most −X side, and vias v309 and v310 corresponding to the most −Y side wiring paths cp735 and cp738 are located on the most +Y side. are staggered.

Regarding vias v303 to v310 corresponding to wiring paths cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738, vias v303, v305, v307, and v309 on the - signal side The wiring paths cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738 are connected from the -Y side while they are arranged on the -X side with respect to v306, v308, and v310. , the vias v301 and v302 corresponding to the wiring paths cp711 and cp714 are arranged such that the via v301 on the -signal side is on the +X side with respect to the via v302 on the +signal side, and the wiring paths cp711 and cp714 are arranged on the +X side with respect to the via v302 on the +signal side. It is connected from the +Y side.

Further, v301 to v310 are connected to wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, cp739 on the sixth wiring layer Lb6 side, as shown in FIG. Among these wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739, the wiring paths cp712 and cp715 corresponding to the vias v301 and v302 closest to the -X side are the most -Y side and the most +X side. Wiring paths cp736 and cp739 corresponding to the vias v309 and v310 of the wiring lines cp736 and cp739 are connected to the test points TP111 to TP120 after changing the direction toward the liquid crystal connection first connector CN24 side (-X side) so that the wiring paths cp736 and cp739 corresponding to the vias v309 and v310 are closest to the +Y side. ing. As a result, the wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 on the sixth wiring layer Lb6 side are arranged in the same order as the wiring paths cp711, cp714, and cp717 on the first wiring layer Lb1 side. , cp720, cp723, cp726, cp729, cp732, cp735, and cp738 are changed to match the arrangement of the EVEN-side terminals in the liquid crystal connection first connector CN24.

Note that cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 are drawn out in the +Y direction with respect to vias v303 to v310, whereas cp712 and cp715 are drawn out with respect to vias v301 and v302. Therefore, there is no change in the arrangement of the +/− wiring paths between the first wiring layer Lb1 side and the sixth wiring layer Lb6 side.

Since test points TP111 to TP120 have a diameter larger than the minimum interval of each wiring path, each wiring path cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733 is similar to test points TP101 to TP110. , cp736, and cp739, and are spaced apart from each other. Adjacent pairs of test points, that is, a total of five pairs of test points, are alternately displaced in the X direction to avoid mutual interference.

Further, as shown in FIG. 69, the test points TP111 to TP120 are connected to the liquid crystal connection via wiring paths cp713, cp716, cp719, cp722, cp725, cp728, cp731, cp734, cp737, cp740 on the first wiring layer Lb1 side. It is connected to terminal connection portions rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ on the side of one connector CN24.

Wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 on the sixth wiring layer Lb6 side extend from test points TP111 to TP120 to protection diodes D110, D111, D112, D108, and D109, respectively. , to the ground (second wiring layer Lb2). That is, as shown in FIG. 70, the wiring paths cp712 and cp715 are connected to the protection diode D110, the wiring paths cp718 and cp721 are connected to the protection diode D111, the wiring paths cp724 and cp727 are connected to the protection diode D112, and the wiring paths cp730 and cp733 are connected to the protection diode D112. D108 and wiring paths cp736 and cp739 are connected to a protective diode D109, respectively.

As described above, in the wiring paths P101 to P120 of this embodiment, the wiring patterns before reaching the test points TP101 to TP120 (on the upstream side, that is, on the liquid crystal IF third connector CN23 side) are shown in FIGS. The wiring length of each wiring path is made substantially equal by meandering as shown in FIG. This makes it possible to equally measure the transmission speed of each of the test points TP101 to TP120 during the test. Of course, as shown in FIG. 69, it is desirable to make the wiring lengths of the respective wiring paths substantially equal in the wiring pattern after passing the test points TP101 to TP120 (on the downstream side, that is, on the liquid crystal connection first connector CN24 side). . This is to equalize the transmission speed of image data in each wiring path. Moreover, it is desirable to provide these test points TP101 to TP120 before (on the upstream side of) the electronic parts such as diodes in that it is possible to check whether or not the noise source is in the electronic parts such as diodes.

Next, the wiring path P121 for transmitting the backlight ON/OFF control signal XSTABY1 from the liquid crystal IF third connector CN23 to the liquid crystal connection second connector CN25 will be described. The backlight of the liquid crystal display means 76 is composed of light emitting diodes (LEDs) arranged vertically and horizontally, and a driving driver for outputting a driving signal and synchronously lighting and driving the light emitting diodes. The CPU (built-in CPU circuit 171) outputs a backlight ON/OFF control signal XSTABY1 to the drive driver, thereby controlling the internal operation of the drive driver.

In the wiring path P121 (FIG. 75), as shown in FIG. 67, in the first wiring layer Lb1, the wiring path cp801 extends from the terminal connection portion xstaby1 on the liquid crystal IF third connector arrangement area 223 (liquid crystal IF third connector CN23) side. - pulled out in the Y direction and connected to via v311; As shown in FIG. 71, the via v311 is connected to the ground via the resistor RA113 in the sixth wiring layer Lb6, and is also connected to the via v312 by the wiring path cp802. Logic integrated circuit IC101, test point TP121, resistor built-in transistor Q102, resistor R106, transistor Q104, resistor R105, and test point TP122 are arranged. A via v331 is arranged on the wiring path connecting the transistor Q104 and the resistor R105. This via v331 is connected to a wiring path P123 for DC12V supply, which will be described later.

As shown in FIG. 64, the via v312 is connected to the via v313 through the wiring path cp803 on the third wiring layer Lb3 side, and further, as shown in FIG. is connected to the terminal connection portion xstaby1 on the liquid crystal connection second connector arrangement area 225 (liquid crystal connection second connector CN25) side.

Next, the wiring path P122 for transmitting the backlight dimming PWM signal VBR1 from the liquid crystal IF third connector CN23 to the liquid crystal connection second connector CN25 will be described. The liquid crystal control CPU outputs the backlight dimming PWM signal VBR1 to the drive driver whose internal operation is enabled by the above-described backlight ON/OFF control signal XSTABY1, so that the drive driver operates. is configured to drive the light-emitting diode to light up.

In the wiring path P122 (FIG. 75), as shown in FIG. 67, in the first wiring layer Lb1, the wiring path cp811 extends from the terminal connection portion vbr1 on the liquid crystal IF third connector arrangement area 223 (liquid crystal IF third connector CN23) side. - pulled out in the Y direction and connected to via v314; As shown in FIG. 71, the via v314 is connected to the ground via the resistor RA113 in the sixth wiring layer Lb6, and is also connected to the via v315 via the wiring path cp812. Logic integrated circuit IC101, test point TP123, resistor built-in transistor Q101, resistor R104, transistor Q103, resistor R111, and test point TP124 are arranged. A via v332 is arranged on the wiring path connecting the transistor Q103 and the resistor R111. The via v332 is connected to a wiring path P123 for DC12V supply, which will be described later.

The via v315 is connected to the via v316 through a wiring path cp813 on the third wiring layer Lb3 side as shown in FIG. to the terminal connection portion xstaby1 on the liquid crystal connection second connector arrangement area 225 (liquid crystal connection second connector CN25) side.

Next, a wiring path P123 for supplying DC 12V from the second liquid crystal IF connector CN22 to the second liquid crystal connection connector CN25 and the like based on the power supply control signal PS1 from the third liquid crystal IF connector CN23 will be described. 12 V power is supplied to the backlight power source of the liquid crystal display means 76 based on the power control signal PS1.

In the wiring path P123 (FIG. 75), as shown in FIG. 67, in the first wiring layer Lb1, the wiring path cp821 extends from the terminal connection portion ps1 on the liquid crystal IF third connector arrangement area 223 (liquid crystal IF third connector CN23) side. - pulled out in the Y direction and connected to via v317; As shown in FIG. 71, in the sixth wiring layer Lb6, the via v317 is connected to the ground via the resistor RA113 and is also connected to the via v318 via a wiring path cp822. A logic integrated circuit IC101, a resistor built-in transistor Q107, and a resistor R109 are arranged.

The via v318 is connected to the resistor R103 and the transistor Q106 via the cp823 in the first wiring layer Lb1, as shown in FIG.

In the wiring path P123 (FIG. 75), as shown in FIG. 68, in the first wiring layer Lb1, one or a plurality (here, eight connectors) on the side of the liquid crystal IF second connector arrangement region 222 (liquid crystal IF second connector CN22). ) from the terminal connection portion dc12v to the -Y side, and is connected to one or a plurality of (here, six) vias v321. The solid wiring path cp824 is connected to the ground via capacitors C107, C110 and C114.

As shown in FIG. 65, the via v321 is connected to one or a plurality of (here, six) vias v322 via a solid wiring path cp825 of the fourth wiring layer Lb4, and further, as shown in FIG. It is connected to the resistor R103 and the transistor Q106 via the wiring path cp826 on the one wiring layer Lb1 side.

Further, as shown in FIG. 68, the transistor Q106 is connected to one or more (five here) vias v341 and one or more (one here) vias v332 via a solid wiring path cp827. As already described, the via v332 is connected to the transistor Q103 and the resistor R111 on the wiring path P122 side in the sixth wiring layer Lb6.

Also, as shown in FIG. 65, the via v341 includes one or a plurality (here, one) via v331 and one or a plurality (here, five) via v331 through the solid wiring path cp828 of the fourth wiring layer Lb4. v342 and via v332. As already described, the via v331 is connected to the transistor Q104 and the resistor R105 on the wiring path P121 side in the sixth wiring layer Lb6.

As shown in FIG. 72, via v342 is connected to capacitors C112 and C104, resistor R112, diode D106, and test points TP125 and TP126 through solid wiring path cp829 in sixth wiring layer Lb6. are connected to a plurality of (here, four) terminal connection portions dc12v on the side of the liquid crystal connection second connector arrangement region 225 (liquid crystal connection second connector CN25) via the solid wiring path cp830 in the first wiring layer Lb1. there is

Next, the wiring path P124 for supplying DC 5V from the liquid crystal IF second connector CN22 to the liquid crystal connection first connector CN24 based on the power supply control signal PS2 from the liquid crystal IF third connector CN23 will be described. A 5V power supply is supplied to the display control section of the liquid crystal display means 76 based on the power supply control signal PS2.

In the wiring path P124 (FIG. 75), as shown in FIG. 67, in the first wiring layer Lb1, the wiring path cp831 extends from the terminal connection portion ps2 on the liquid crystal IF third connector arrangement area 223 (liquid crystal IF third connector CN23) side. - pulled out in the Y direction and connected to via v351; As shown in FIG. 71, in the sixth wiring layer Lb6, the via v351 is connected to the ground through the resistor RA113 and is also connected to the via v352 by the wiring path cp832. A logic integrated circuit IC101, a resistor built-in transistor Q105, and a resistor R107 are arranged.

The via v352 is connected to the resistor R108 through the wiring path cp833 in the first wiring layer Lb1, as shown in FIG. Also, the resistor R108 is connected to the transistor Q108 via the wiring path cp834.

Further, in the wiring path P124 (FIG. 75), as shown in FIG. 68, in the first wiring layer Lb1, a plurality (eight in this case) of the liquid crystal IF second connector arrangement region 222 (liquid crystal IF second connector CN22) side. A solid wiring path cp835 is drawn out from the terminal connection portion dc5v to the -Y side and connected to one or a plurality of (here, four) vias v353. The solid wiring path cp835 is grounded via capacitors C108 and C109.

Then, as shown in FIG. 65, the via v353 is connected to one or more (here, three) vias v354 through the solid wiring path cp836 of the fourth wiring layer Lb4, and further, as shown in FIG. It is connected to the resistor R108 and the transistor Q108 via the wiring path cp837 on the first wiring layer Lb1 side.

Furthermore, as shown in FIG. 68, the transistor Q108 is connected to one or a plurality of (here, four) vias v355 via a solid wiring path cp838 on the first wiring layer Lb1 side. As shown in FIG. 65, this via v355 is connected to a plurality of (here, four) vias v356 via a solid wiring path cp839 of the fourth wiring layer Lb4.

The via v356 is connected to the solid wiring path cp840 in the sixth wiring layer Lb6, as shown in FIG. Capacitors C113, C105, resistor R110, diode D107, test points TP127, TP128 are connected to solid wiring path cp840, and it is also connected to one or more (here, four) vias v357. As shown in FIG. 69, the vias v357 are formed in a plurality (four in this case) of the liquid crystal connection first connector arrangement area 224 (liquid crystal connection first connector CN24) through the solid wiring path cp841 in the first wiring layer Lb1. It is connected to the terminal connection portion dc5v.

As described above, in this embodiment, the power supply to the liquid crystal display means is controlled by software using the power control signals PS1 and PS2. The power supply to the liquid crystal display means may be controlled. In this case, the 12V power supply and the 5V power supply are respectively supplied to the backlight power supply unit and the display control unit when the game machine is powered on.

Here, processing by the liquid crystal control CPU when power is turned on will be described. As a process when the power is turned on, the liquid crystal control CPU supplies power to the liquid crystal display means by the power control signals PS1 and PS2, and then sends the backlight ON/OFF control signal XSTABY1 and the backlight dimming PWM signal to the drive driver. It is configured to perform the following processing before outputting the signal VBR1.

First, the internal VRAM is initialized and the refresh period is set. By performing refresh processing based on the predetermined period set here, loss of charge in the memory is prevented. Therefore, even if there is a memory cell that has not been accessed for a long time in the VRAM, there is no possibility that the data will be lost.

Subsequently, the initialization of the display circuit and the initial setting of the display clock that defines the operation of the display circuit are performed by setting a predetermined register. Then, an initial setting for the LVDS output is performed by setting a predetermined register. Further, the LVDS output of the image data is performed from the designated display circuit by setting a predetermined register. At this time, the image data to be output is set so as to output random data (data of all 0) by register setting. As a result, it is possible to prevent the display of unnatural image data such as broken image data on the liquid crystal display means side, and it is possible to confirm that the LVDS output processing itself operates normally. Also, although the image data is set to be output here, the backlight ON/OFF control signal XSTABY1 and the backlight dimming PWM signal VBR1 have not yet been output to the drive driver at this timing. In practice, an image based on random data (data of all 0's) is never displayed on the liquid crystal display means side. By doing so, it is configured so that (in terms of display) meaningless image data cannot be visually recognized.

Here, it was set to output random data (data of all 0) by setting the register, but as described above, it is difficult to see the image data actually output at this timing, so random data is specified. Alternatively, only the image data (unspecified uncertain data) may be output. In this case, the number of register setting processes can be reduced, so that the number of processes to be performed when the power is turned on can be reduced, and the time until the liquid crystal display means actually turns on can be shortened as much as possible.

In addition, since the dual-link transmission system is adopted in this embodiment, the LVDS output setting for the ODD signal and the LVDS output setting for the EVEN signal are performed for each register. At this time, a common setting value is set for each parameter to be set.

Subsequently, a predetermined register is referenced to confirm whether the clock operation of the display clock that has been initialized is in a stable state. At that time, it waits while clearing the watchdog timer for resetting the liquid crystal control CPU until the value of the register becomes a value indicating a stable state.

Subsequently, a predetermined register is referenced to confirm whether the initialization of the display circuit that has been initialized has been completed. At this time, it waits while clearing the watchdog timer for resetting the liquid crystal control CPU until the value of the register becomes a value indicating the completion of initialization.

Subsequently, a predetermined register is referenced to confirm whether the initialization of the LVDS output that has been initialized has been completed. At this time, it waits while clearing the watchdog timer for resetting the liquid crystal control CPU until the value of the register becomes a value indicating the completion of initialization.

Subsequently, definitions of an AAC area, a page area, and an arbitrary area are set for the built-in VRAM (at that time, each frame buffer is secured in the arbitrary area). Further, setting of the number of display lines and the number of horizontal pixels for the liquid crystal display means to be used, setting of the horizontal synchronization cycle, horizontal standby time, setting of the number of vertical synchronization lines and vertical standby time, setting of the pulse width of the horizontal synchronization signal HS and the number of cycles from the start of V blank, the pulse width of the vertical synchronization signal VS and the number of cycles from the start of V blank, the setting of V blank interrupt permission, the setting of the vertical and horizontal display start positions for each frame buffer, Set the display area, etc.

Subsequently, a predetermined register is referenced to confirm whether the initialization of the built-in VRAM, which has been initialized, has been completed. At this time, it waits while clearing the watchdog timer for resetting the liquid crystal control CPU until the value of the register becomes a value indicating the completion of initialization.

Finally, by setting a predetermined register, the display circuit accesses the built-in VRAM and performs the setting for permitting the operation of generating image data, and the setting for permitting the LVDS output operation.

After these processes are completed, the backlight ON/OFF control signal XSTABY1 is output to the driver, and after waiting for a predetermined time (approximately 300 ms), the backlight dimming PWM signal VBR1 is output. , to complete the lighting control of the liquid crystal display means.

In this manner, after power is supplied to the liquid crystal display means by the power control signals PS1 and PS2, and before the actual lighting control is started, various settings relating to the display circuit, the output circuit, and image data generation can be performed. , there is no risk of accidentally outputting inappropriate data on the screen when setting. In addition, since the lighting of the backlight of the liquid crystal display means is started after all these settings are completed, it is possible to configure so that all the settings related to the display are already completed when the liquid crystal display means is turned on. . Therefore, it is possible to configure so that the image data can be output immediately after the liquid crystal display means is turned on.

In this embodiment, before outputting the backlight ON/OFF control signal XSTABY1 and the backlight dimming PWM signal VBR1 to the drive driver, various setting processes are performed. After outputting the light ON/OFF control signal XSTABY1, it may be performed before outputting the backlight dimming PWM signal VBR1.

Next, a specific example of the effect executed by the effect control section 95 will be described. FIG. 79 conceptually shows a configuration relating to the effect control realized by the effect control section 95. As shown in FIG.

The special reserved number display control means 95a controls the display of the first and second special reserved numbers on the liquid crystal display means 76, and corresponds to the increase/decrease of the first and second special reserved numbers. 1st suspension notification images X1 to X4 for the number (maximum 4), 2nd suspension notification images Y1 to Y4 for the number of the 2nd special suspension (maximum 4), and the 1st and 2nd special symbols during fluctuation is displayed on the liquid crystal display means 76.

Based on the fact that the first and second special symbol starting means 72 and 73 detect the game ball, when receiving a hold addition command relating to the first and second special hold numbers from the main control board 93, the special hold number The display control means 95a additionally displays one of the first and second suspension notification images X1~, Y1~ at the end of the queue. Also, based on the start of the variation of the first and second special symbols by the first and second special symbol display means 63 and 64, the main control board 93 issues a reserve subtraction command regarding the first and second special reserve numbers. When received, the special pending number display control means 95a shifts the first and second pending notification images X1 ~, Y1 ~ toward the front side of the queue one by one, and pushes out the top number 1, the second suspension notification images X1 and Y1 are moved to a predetermined position, for example, and changed to a suspension notification image Z during fluctuation. In the present embodiment, the display color (display mode) of the first and second hold notification images X1-, Y1-, and the variable hold notification image Z is set to, for example, "○ (white circle)" by default, and the hold change described later When the notice is executed, it is changed according to the scenario selected by the look-ahead notice effect control means 95b.

The pre-reading notice effect control means 95b controls the pre-reading notice effect, and based on the result of the pre-reading determination by the main control board 93, the stop pattern after the fluctuation of the first and second special symbols becomes a big win mode and the big win game is played. It is configured to be able to execute a pre-reading forewarning effect that forewarns whether or not will occur. In addition, in the main control board 93, the first and second special random number information acquired when the first and second special symbol starting means 72 and 73 detect the game ball are provided before the symbol variation. At a predetermined timing, for example, when acquiring the first and second special random number information, look-ahead judgment to determine whether the big hit judgment random number contained in the first and second special random number information matches the big hit judgment value Processing is executable. The prefetch determination result is transmitted from the main control board 93 by, for example, a pending addition command.

The look-ahead notice effect includes "continuous notice", "suspended change notice", and the like. "Continuous notice" is based on the result of the pre-reading determination, for example, in the same mode in multiple symbol variations (in the pre-reading zone) up to the symbol variation (target variation) corresponding to the special random number information that is the target of the pre-reading determination It carries out the performance.

Further, the "suspension change notice" is to display the first and second suspension notification images X1-X4, Y1-Y4 and the variable suspension notification image Z in a predetermined display mode based on the result of pre-read determination. In this embodiment, as shown in FIG. 80, as the display mode of the suspension notification image, three types other than the default "○ (white circle)" are prepared. When winning, for example, when the first and second suspension notification images are newly additionally displayed, or at a predetermined timing after that, the suspension notification image is displayed in a display mode such as the winning "elephant". The display mode of the pending notification image is selected in accordance with the degree of reliability of the big win based on the prefetch determination, and as shown in FIG. set to be high. Further, for example, a display mode such as "Rainbow" in which the reliability of the big hit is set to 100% may be provided. It should be noted that, if prefetching is prohibited or if the pending change notice is not won, the pending notification image is displayed as "○ (white circle)".

Further, the hold notification image of the present embodiment performs an operation (dynamic display) that mainly changes in the vertical direction at the start of display, during display, and at the end of display. FIGS. 81(a) to 81(c) show an example of operations at the start of display, during display, and at the end of display of the holding notification image of "elephant". It should be noted that the same applies to other hold notification images of "Lion" and "Giraffe". As shown in FIG. 81(a), when the hold notification image is newly displayed (at the start of display), the hold notification image is bounced once in the vertical direction immediately after it is displayed. That is, the suspension notification image at the start of display is moved vertically.

Further, as shown in FIG. 81(b), during the display of the hold notification image (after the start of display and before the end of display), the hold notification image is displayed as if it is three-dimensionally rotating around the horizontal axis. be. At this time, what is actually performed on the two-dimensional screen is a vertical deformation operation. The operation of the hold notification image being displayed is repeatedly performed, but it may be performed continuously or intermittently.

Further, as shown in FIG. 81(c), when the display of the hold notification image ends (at the end of display), the hold notification image is displayed downward (or upward) so as to be sequentially erased. That is, the suspension notification image at the end of display is deformed in the vertical direction.

In addition, as shown in FIG. 80, the reservation notification image of the present embodiment is configured such that more types of color information are distributed in the vertical direction than in the horizontal direction. are increasing. For example, in the reservation notification image of "elephant", the display color of the background portion of the character changes in three levels in the vertical direction, but the display color does not change in the horizontal direction. As a result, the number of types of color information used on each pixel line in the vertical direction is greater than the number of types of color information used on each pixel line in the horizontal direction. are relatively high.

By the way, as already explained, in the pachinko machine of the present embodiment, the liquid crystal control board (display control means) 98 for controlling the display of the liquid crystal display means 76 provides the liquid crystal display means 76 with odd-numbered pixels in the horizontal direction. It is configured to output odd-numbered image data and even-numbered image data corresponding to even-numbered pixels in the horizontal direction in parallel via different wiring paths, that is, a first transmission path LVDS1 and a second transmission path LVDS2. there is Therefore, even if one of the first and second transmission lines LDVS1 and LVDS2 is disabled due to disconnection or the like, as long as the other transmission line is alive, only one of the odd image data and the even image data can be transmitted. It is possible to continue the display of the liquid crystal display means 76 at . However, in this case, the screen of the liquid crystal display means 76 is in a state in which every single vertical pixel line is missing, so the player may not be able to fully recognize the displayed content when compared with the normal display state. .

In this regard, the hold notification image of the present embodiment is configured to perform an action mainly for vertical change at the start of display, during display, and at the end of display. Even if any of the even-numbered image data is missing, the dynamic display (movement, deformation, etc.) of the hold notification image is continuously displayed as shown in FIGS. The dynamic display of the hold notification image can be recognized by the player in the same manner as during normal display.

In addition, since the hold notification image of the present embodiment is configured such that more types of color information are distributed in the vertical direction than in the horizontal direction, even-numbered image data or odd-numbered image data may be missing. However, as shown in FIG. 83(a), the color change is along the normally displayed vertical pixel line, and the player can clearly recognize the color change pixel by pixel, thereby displaying the hold notification image. can be identified in the same manner as during normal display. Incidentally, when the types of color information are distributed in the horizontal direction, if either the odd-numbered image data or the even-numbered image data is missing, the color change position becomes ambiguous as shown in FIG. There is a possibility that the image cannot be identified as it is during normal display.

It should be noted that the operation of the hold notification image does not have to be performed at the start of display, during display, and at the end of display, and may not be performed for any of them. Further, the action of the hold notification image may be mainly a change in the up-down direction, and may be accompanied by a change in the left-right direction. Further, the dynamic display mainly based on the change in the vertical direction of the hold notification image is not limited to the one shown in FIG. ) may be displayed.

Further, when shifting the suspension notification image at the start of a new pattern variation, as shown in FIG. bound motion). As a result, even if either the odd-numbered image data or the even-numbered image data is missing, the shift operation of the hold notification image is performed along the continuously displayed (without missing) vertical pixel lines. , the player can more clearly and easily recognize the shift operation of the hold notification image. Instead of or in addition to the movement in the vertical direction, deformation in the vertical direction may be accompanied.

Returning to FIG. 79, the description continues. The symbol variation effect control means 95c controls the display of the decorative symbol 90 and the accompanying voice output, lamp light emission, etc. When the fluctuation pattern command is received from the main control board 93 at the start of the fluctuation, the fluctuation pattern scenario corresponding to the specified fluctuation pattern, various scenarios such as the notice effect scenario selected by the normal notice effect control means 95d described later Based on the variation of the decorative pattern 90 and the accompanying voice output, lamp emission, etc. are started, and when the variation stop command is received from the main control board 93 at the end of the variation of the first and second special symbols, the stop design A stop pattern selected based on the command and the variation pattern command is used to stop the variation of the decorative pattern 90, and to stop the accompanying voice output, lamp emission, and the like.

As shown in FIG. 85(a), the decorative pattern 90 is designed such that the pattern body 90a is displayed in any one of a plurality of colors, for example, odd-numbered patterns are displayed in red and even-numbered patterns in blue. Strictly speaking, however, the color of the pattern body portion 90a is not a single color, but a variety of similar colors are used to express a three-dimensional effect. In this embodiment, a vertical gradation is formed as shown in FIG. 85(a) so that more types of color information are distributed in the vertical direction than in the horizontal direction in the design body portion 90a. As a result, even if either the odd-numbered image data or the even-numbered image data is missing, as shown in FIG. It follows the pixel line, and the player can clearly recognize the color change in pixel units, so that the color information of the decorative pattern 90 can be identified in the same manner as during normal display. In the decorative pattern 90, it is sufficient that more kinds of color information are distributed in the vertical direction than in the horizontal direction, and the gradation is not necessarily required.

In addition, as shown in FIG. 86, the decorative pattern 90 is a dynamic display accompanied by a change in the vertical direction (here, expansion and contraction deformation in the vertical direction) at the start of fluctuation, at the stop of fluctuation, at the establishment of reach, and in a specific mode ( Jackpot production mode) It is designed to be executed at a predetermined timing such as when establishment. In this way, even if either the odd image data or the even image data is missing, the dynamic display shown in FIG. As in the case of the notification image, the dynamic display is along vertical pixel lines that are continuously displayed (with no gaps), and the player can distinguish between the dynamic display of the decoration pattern 90 and the normal display. It is possible to identify them in the same way.

Regarding the decorative pattern 90, the dynamic display accompanied by the change in the vertical direction is not limited to deformation such as enlargement and reduction, and may be moved, rotated, or the like. In addition, since the pattern variation is also included in the dynamic display, if one of the odd image data and the even image data is missing, the vertical direction of the pattern variation (scrolling direction) is better than the horizontal direction. desirable. Also, when performing dynamic display involving changes in the horizontal direction instead of the vertical direction, it is desirable to move (change) two dots or more per frame. As a result, even when either the odd image data or the even image data is missing, the decorative pattern 90 always changes in the horizontal direction for each frame, so that the player can display the dynamic display of the decorative pattern 90 normally. It becomes possible to identify it in the same way as time.

Returning to FIG. 79, the description continues. The normal notice effect control means 95d controls the normal notice effect. The normal notice effect informs the possibility of occurrence of a predetermined event (for example, the reliability of the big hit) during the pattern change based on the result of the big hit determination by the big hit determination process on the main control board 93 side. SU notice,” “timer notice,” “pseudo continuous effect,” “button effect,” “word notice,” “information notice,” “rainbow effect,” and the like.

Among them, for example, "button effect" (operation effect) is a effect that requires the player to operate the effect button (predetermined operation means) 41, and the effect is produced during the operation valid period during which the operation by the effect button 41 is valid. When the operation of the button 41 satisfies a predetermined operation condition, a predetermined post-operation effect is executed to notify the reliability of the big hit or the like. Of course, the operation target in the operation presentation may be anything that can be operated by the player, such as an operation lever or a touch panel. During the effective period of operation, an LED (not shown) provided in the effect button 41 emits light, and an operation guide image 231 for prompting the player to operate the effect button 41 is displayed on the liquid crystal display means 76 . As shown in FIG. 87, the operation guide image 231 includes a button image (operation target image) 232 indicating the effect button (predetermined operation means) 41 to be operated, and an operation indicating an operation mode for the effect button 41 to be operated. It has a mode notification image 233 and an operation effective period notification image 234 indicating the progress of the operation effective period.

The operation effective period notification image 234 is formed in an elongated shape elongated in the left-right direction, and has an elapsed display portion 234a on one side (here, left side) in the longitudinal direction and a non-elapsed display portion on the other side (here, right side) in the longitudinal direction. A boundary 234c with 234b moves laterally (to the right in this case) as time passes during the effective period of operation, thereby notifying the progress of the effective period of operation. That is, at the start of the effective period of operation, the boundary 234c is located on the left end side so that the length ratio of the elapsed display section 234a and the non-elapsed display section 234b is 0:10, and as time passes during the effective period of operation, After the boundary 234c moves rightward at a constant speed, the boundary 234c reaches the right end when the valid operation period expires, and the length ratio between the elapsed display portion 234a and the non-elapsed display portion 234b becomes 10:0. controlled.

As for this button effect (operation effect), for example, when the effect button 41 is operated once, it is determined that a predetermined operation condition is satisfied due to a difference in the operation mode required of the player. 41 is continuously pressed (operated) a plurality of times, it is determined that a predetermined operation condition is satisfied; A “long-press button effect” or the like for determining that the condition is satisfied is conceivable. The operation mode notification image 233 is composed of character information such as "PUSH" for the one-hit button effect, "continuous hit" for the repeated button effect, and "long press" for the long-press button effect. Of course, when the type of button effect is limited to one-hit button effect, only one type of operation mode notification image 233 may be used, and the operation mode notification image 233 may not be displayed. Further, the operation mode notification image 233 is integrated with the button image (operation target image) 232 as shown in FIG. Alternatively, it may be displayed separately from the button image (operation target image) 232 .

In addition, the "rainbow effect" informs the player of the determination of the award of a privilege (for example, determination of winning regarding the result of a winning lottery as to whether or not to execute a jackpot game (big hit determination)). A rainbow image effect for displaying an image (gradation image), and a rainbow light emission for causing light emitters arranged in predetermined parts including the front frame 3, such as the frame lamp 304, the board lamp 324, and the movable accessory lamp 314, to emit light in a rainbow light emission pattern. There is a production. Of course, the rainbow image effect and the rainbow light emission effect can be executed in parallel with each other, and either one of them can be executed independently.

In the rainbow image effect, a full-screen image (for example, a background image) displayed on substantially the entire surface of the liquid crystal display means 76 is displayed in rainbow colors, and characters, graphics, and characters displayed on a portion of the screen of the liquid crystal display means 76 are displayed. , etc., may be displayed in rainbow colors. Since color display is not possible in the patent drawings, the rainbow image is simply expressed in black and white gradation in the drawings of the present application.

Rainbow images are those whose colors change in the circumferential direction around a predetermined point on the screen (Fig. 88(a)), those whose colors change in the radial direction around a predetermined point on the screen (Fig. 88(b)), It is conceivable that the color changes in any direction such as vertical direction and horizontal direction (FIGS. 88(c) and (d)). Also, instead of the smooth gradation shown in FIGS. 88(a) to (c), a gradation in which the color changes stepwise as shown in FIG. 88(d) may be employed.

Further, the rainbow images exemplified in FIGS. 88(a) to (d) change the display color continuously or stepwise with respect to position, and also continuously (or stepwise) with respect to time. display color may be changed. That is, as shown in FIG. 89, all the pixels forming the rainbow background image may be controlled so that the display colors return to the original display colors in a predetermined time period (for example, 3 seconds). This causes the rainbow colors to flow clockwise or counterclockwise in the case of Figure 88(a), and the rainbow colors to flow radially outward or inward in the case of Figure 88(b). In the case of FIG. 88(c), the rainbow colors are displayed so as to flow upward or downward, and in the case of FIG. 88(d), the rainbow colors are displayed so as to flow leftward or rightward.

Each of the various normal notice effects described above can be executed independently, or can be executed by combining a plurality of types of effects. Hereinafter, a specific example of "hit-lose branch button effect" in which the rainbow effect is combined with the button effect will be described as the win-lose branch effect at the end of the ready-to-win effect.

In the win-lose branch button effect shown in FIG. 90, first, the button pushing effect is executed. The button push effect is a show that arouses the player's expectation by notifying that the button operation will be possible soon, and a button push image 242 is displayed on the liquid crystal display means 76. - 特許庁The button effect image 242 includes a band effect image 242a arranged in a predetermined direction (here, left and right direction) at a predetermined position (here, the top) on the screen, and a character image (band effect-related image) related to the band effect image 242a. ) 242b.

As shown in FIG. 91, the band effect image 242a includes a character information image (information image) 235 composed of a character string (display information) and a character information image 235 overlapping at least part of the character information image 235. An information decoration image 236 arranged in a substantially band-like area along the information image 235 .

The character information image 235 includes first character information (first display information) 235a composed of a character string "if you make a character laugh" and "big win!" which is more important to the player than the first character information 235a. '' (second display information) 235b. The first character information 235a is displayed so as to fit within the width (vertical width) of the information decoration image 236, while the second character information 235b is displayed on at least one side (here, the upper side) of the information decoration image 236. It is displayed as if it sticks out. With such a configuration, the character information image 235 can be sharpened according to its importance, and the width of the information decoration image 236 for emphasizing and conspicuous the character information image 235 can be minimized to improve the visibility of the background. can be sufficiently ensured.

Also, the second character information 235b is displayed in a color that is more visible with respect to the information decoration image 236 than the first character information 235a. That is, for example, the information decoration image 236 is displayed in light blue, the second character information 235b is displayed in red which is the opposite color, and the first character information 235a is displayed in yellow, for example. The display colors of the character information image 235 and the information ornamentation image 236 may be a single color or a plurality of colors. Assuming that either the odd-numbered image data or the even-numbered image data is missing, it is desirable to arrange so that more types of color information are distributed in the vertical direction than in the horizontal direction.

Further, as shown in FIGS. 91(a) to 91(f), the character information image 235 performs a moving operation (first dynamic display) in a predetermined direction (to the left in this case) along the information decoration image 236. Furthermore, for the second character information 235b of the character information image 235, an action of jumping upward character by character (second dynamic display different from the first dynamic display) is performed.

Note that the second dynamic display is not limited to an upward jumping motion, but is a two-dimensional rotating motion (for example, a rotating motion around an axis perpendicular to the screen), a three-dimensional rotating motion (for example, a vertical or horizontal direction around an axis). It can be any kind of action, such as an action that looks as if it is rotating), a deformation action such as enlargement/reduction, or the like. As for the second dynamic display, if one of the odd-numbered image data and the even-numbered image data is assumed to be missing, it is desirable that the second dynamic display accompanies a change in the vertical direction.

A character image 242b with a straight face related to the band effect image 242a is displayed, for example, substantially in the center of the liquid crystal display means 76 separately from the band effect image 242a, as shown in FIG. The character image 242b may be displayed in front of the information decoration image 236 as one of the information images forming the band effect image 242a. In this way, the display information that constitutes the information image is not limited to character information, and may be symbols, patterns, and the like.

Further, while the button-flashing images 242 are being displayed, the left and right decorative patterns 90 already stopped in the ready-to-win mode are reduced and displayed on the periphery of the screen. It is assumed that the mini-symbol 240 corresponding to the decorative pattern 90 is always displayed on the liquid crystal display means 76 while the decorative pattern 90 is changing.

Following the button-flicking effect, an operation guide image 231 for prompting the player to operate the effect button 41 is displayed on the liquid crystal display means 76, and an operation effective period with a predetermined time as the upper limit is started. Note that the button effect is a one-hit button effect in which a result effect is executed when the effect button 41 is operated once. Therefore, the operation mode notification image 233 forming the operation guidance image 231 becomes an operation mode notification image 233a including characters such as "PUSH" corresponding to the one-hit button effect.

In addition, in this embodiment, a plurality of types of operation guide images are prepared, and the reliability of big wins differs from one to another. For example, in the first operation guide image 231a shown in FIG. 92(a), the inside of the button image 232a (excluding the operation mode notification image 233) is displayed in a single color, whereas the first operation guide image 231a shown in FIG. In the 2-operation guide image 231b, the inside of the button image 232a (excluding the operation mode notification image 233) is divided into a plurality of vertical regions and displayed in different colors, and the reliability of the latter is higher than that of the former. It's becoming

In this way, the image data corresponding to the button image 232b of the second operation guidance image 231b with higher reliability is configured such that more types of color information are distributed in the vertical direction than in the horizontal direction. Even if either the image data or the even image data is missing, the color change is along the vertical pixel line that is continuously displayed (without missing) (see FIG. 83), A player or the like can clearly recognize the color change on a pixel-by-pixel basis, and thus can clearly identify the second operation guide image 231b.

Further, in the present embodiment, regarding the operation effective period notification image 234 that constitutes the operation guide image 231, the boundary 234c between the elapsed display portion 234a and the non-elapsed display portion 234b moves horizontally by two dots or more for each frame. is configured to FIG. 93(a) shows how the boundary 234c moves rightward by two dots for each frame. In this case, even if either the odd-numbered image data or the even-numbered image data is missing, as shown in FIG. It is possible to accurately recognize the elapse of the valid period of operation in the same manner as in the case of normal display without omission. As shown in FIG. 94(a), when the movement of the boundary 234c for each frame is set to less than 2 dots, if either the odd image data or the even image data is missing, As shown, it may appear that the boundary 234c does not move even after one frame, and the appearance of the boundary 234c is clearly different from that during normal display.

When the player presses the effect button 41 during the effective period of operation, the effective period of operation ends at that point, and the rainbow effect, which means that the big win is confirmed, is started (FIG. 90). In this rainbow effect, a rainbow image effect and a rainbow light emitting effect are executed in parallel. In this rainbow image effect, the background image of the liquid crystal display means 76 becomes a rainbow background image 243, and in front of the rainbow background image 243, a smiling character image 244 and the like are displayed. In the example of FIG. 90, the rainbow background image 243 is displayed in rainbow colors whose colors change in the circumferential direction around a predetermined point on the screen (here, the center point of the screen), and the color distribution of the rainbow colors is It changes clockwise as time passes. The character image 244 is superimposed on the front side of the rainbow background image 243 so as to hide the center point (predetermined point) of the rainbow background image 243 . Also, in the rainbow light emission effect, the movable accessory lamp 314, the board lamp 324, and the frame lamp 304 each emit light in a rainbow light emission pattern (not shown).

Following the above rainbow effect, the post-success effect is executed. The post-success effect of this embodiment is composed of a first post-success effect in the first half and a second post-success effect in the latter half. The first post-success effect is a symbol matching effect in which the decorative symbols 90 are stopped in a jackpot effect mode such as "7.7.7". In the first post-success effect, neither the rainbow image effect nor the rainbow light emission effect is executed in order to draw the player's attention to the pattern matching effect. That is, the background image of the liquid crystal display means 76 is switched from the rainbow background image 243 to the normal background or the background image 245 along with the effect of the SP reach. displayed in the color of Also, the movable accessory lamp 314, the board lamp 324, and the frame lamp 304 emit light in a normal light emission pattern other than the rainbow light emission pattern corresponding to the image on the liquid crystal display means .

The second post-success effect performed following the first post-success effect is a blessing effect for congratulating establishment of the big win effect mode. In this second post-success effect, only the rainbow light emission effect is executed out of the rainbow image effect and the rainbow light emission effect. That is, on the liquid crystal display means 76, the congratulatory image 246 and the like are displayed in addition to the image of the decorative pattern 90 and the like during the first post-success effect. The congratulatory image 246 is composed of a character image and the like, such as "congratulations," which congratulates the player on the fact that the game has become a big hit, and is displayed in a normal color other than the rainbow color. On the other hand, the movable accessory lamp 314, the board lamp 324, and the frame lamp 304 emit light in the rainbow light emission pattern again.

Incidentally, in this second post-success effect, both the rainbow image effect and the rainbow light emission effect may be executed. As an example of the rainbow image effect in this case, at least part of the congratulatory image 246, for example, only the characters "congratulations" may be rendered rainbow. FIGS. 95 and 96(a) show an example in which the inside of the characters "congratulations" in the blessing image 246 is displayed in rainbow colors in the second composite execution mode. In the example of FIG. 95, the color information changes continuously (or stepwise) in the vertical direction (the color information changes continuously or stepwise with respect to the position). is designed so that the display color does not change. In this way, by setting the direction in which the color information in the rainbow image (gradation image) changes in the vertical direction, even if either the odd-numbered image data or the even-numbered image data is missing, the rainbow color changes normally. It follows the displayed vertical pixel line, and the player can clearly recognize the color change in pixel units, so that the rainbow image can be reliably identified as in the case of normal display. This effect is particularly useful when a narrow area such as the inside of a character is to be rainbowed as shown in FIG.

In the example of FIG. 96(a), the color information changes continuously (or stepwise) in the horizontal direction (color information changes continuously or stepwise with respect to the position), The display color does not change with time. Also, in this case, as shown in FIG. 96(b), the inside of the character "Congratulations" has substantially common color information for each pair of pixel lines adjacent to the left and right, that is, a plurality of types of odd image data set. , and a plurality of types of color information set for the even-numbered image data on the right thereof are substantially common. As a result, even if either the odd image data or the even image data is missing, the player can clearly identify the rainbow image.

Next, the big hit effect control means 95e (FIG. 79) will be described. The big-hit production control means 95e controls the production during the big-hit game performed during the big-hit game. An image is displayed on the liquid crystal display means 76, and accompanying voice output, lamp light emission, movable body drive, etc. are executed.

In this embodiment, it is possible to execute a setting suggesting effect that suggests a set value (any of settings 1 to 6) relating to the probability of a big win during the interval for ending the big win. In this setting suggesting effect, the set value is suggested by the display color of a predetermined image (here, a character image of "probability change mode entry") displayed on the liquid crystal display means 76 during the jackpot end interval. Here, five colors of black, blue, yellow, red, and rainbow are prepared as the display color of "probability change mode entry", and one of these five colors is selected by lottery based on the setting suggestion effect selection table shown in FIG. selected. Selection processing regarding whether or not to execute this setting suggestion effect and the type (character color) in the case of execution is performed at an arbitrary timing such as the start of the big win game, the start of the big win end interval, or the like. In addition, in this setting suggestion effect, it is necessary to display the characters "entering the probability mode", so it is only executed in the case of a probability fluctuation jackpot, but at the start of the jackpot end interval at the time of the non-probability fluctuation jackpot, "time saving A setting suggestion effect may be performed by displaying characters such as "enter mode".

In the setting suggestion effect selection table shown in FIG. 97, distribution ratios are set for five colors of black, blue, yellow, red, and rainbow for each of settings 1-6. As is clear from this setting suggestion effect selection table (Fig. 97), in the setting suggestion effect, black has all possibilities of settings 1 to 6, but settings 1 to 3 (low settings) are highly likely. , blue indicates not setting 1 (lowest setting), yellow indicates any setting 4-6 (not low setting), red indicates any setting 5 or 6 (high setting), and the rainbow color (rainbow effect) suggests setting 6 (highest setting).

In this way, the rainbow effect (rainbow color effect) in which the characters of this "probability change mode entry" are rainbow colors is to inform the player that the setting 6 is advantageous, and appears during the above-described pattern variation. Unlike the rainbow effect, it does not announce the confirmation of the big hit, but it is common in that it announces the confirmation of a state advantageous to the player.

When the setting suggestion effect is performed during the jackpot end interval, the operation effective period with the predetermined time as the upper limit is started in a state where the characters (for example, black) of "probability change mode entry" are displayed on the liquid crystal display means 76. (Fig. 98(a)). During the effective period of operation, an operation guide image 231 for prompting the player to operate the effect button 41 is displayed on the liquid crystal display means 76 so as not to overlap with the characters "enter the variable probability mode", for example. Then, when the effect button 41 is operated during the operation valid period, the operation valid period ends at that time, and the characters "entering the probability variable mode" displayed on the liquid crystal display means 76 are displayed according to the set value. Change to selected display color (no change if black is selected). In the case of FIG. 98, since the characters of "probability change mode entry" have changed from black (FIG. 98(a)) to rainbow color (FIG. 98(d)), the player is advised that the setting value at that time is the highest setting. It can be seen that the setting is 6.

In addition, as for the color change (here, black → rainbow) of the characters of this "probable variable mode entry", as shown in Figs. It is progressing. As a result, even if either the odd image data or the even image data is missing, the player can clearly identify the color change of the characters "entering the variable probability mode". It should be noted that the color change of the characters of this "probability change mode entry" may be configured to progress in the left and right direction. In that case, it is desirable to change the color information in the horizontal direction by two dots or more for each frame. As a result, the player can clearly identify the color change of the characters "enter the variable probability mode" even if either the odd image data or the even image data is missing.

In addition, if the operation effective period expires without the production button 41 being operated, the character color of "entering the probability change mode" may be changed at that time, or the color change regardless of the selected color type may not be performed, or when the operation valid period expires, the display of the characters "probability change mode entry" may be terminated.

In addition, in the example of FIG. 98(d), the characters "entering the variable mode" have a rainbow color gradation, and the gradation image is stepwise (or continuous) in the left and right direction (relative to the position). Not only is the color information changing, but the color information is also changing stepwise (or continuously) over time. As for the change of the color information with respect to the time, as shown in FIG. 99(a), the color information moves rightward by two dots per frame. Both the odd-numbered image data and the even-numbered image data corresponding to the gradation image change from pre-change color information to post-change color information. As a result, the width of each color is the same between when the odd-numbered image data is missing and when the even-numbered image data is missing. Even if either the image data or the even-numbered image data is missing, the player can clearly identify the color change of the gradation image.

FIG. 99(b) shows the case where each color information is moved rightward by 1 dot for each frame, and FIG. 99(c) shows the case where each color information is moved rightward by 3 dots for each frame. FIG. 99(d) shows a case where each color information is moved rightward by 4 dots for each frame. In the case of FIG. 99(b) (moving by 1 dot), when the odd image data is missing as indicated by ◯, the color change cannot be expressed accurately. movement), there is a difference between the case where the odd numbered image data is missing and the case where the even numbered image data is missing in the portion indicated by the circle.

On the other hand, in the case of FIG. 99(d) (moving by 4 dots), similar to the case of FIG. The width of each color is common, and it is possible to express almost the same gradation as in the normal state (when there is no dropout). That is, for a gradation image in which color information changes with respect to position and time, it is possible to move even-numbered dots of two dots or more in the horizontal direction (the direction in which odd-numbered pixels and even-numbered pixels are arranged) for each frame. desirable.

In this way, when the preview image is displayed dynamically, either the odd image data or the even image data is missing by changing two dots or more in the left-right direction (direction in which the odd-numbered pixels and the even-numbered pixels are arranged) for each frame. Even in this case, it is desirable that the preview image is changed for each frame, but it may be configured to be changed in the vertical direction, for example. In this case, regardless of the magnitude of the change for each frame, even if either the odd image data or the even image data is missing, the preview image can be configured to change for each frame. is. In addition, the dynamic display in this case includes not only temporal changes in gradation, but also movement of the preview image in a predetermined direction.

FIG. 100 illustrates the second embodiment of the present invention, in which the first embodiment is partially modified to provide the first dynamic display for the first display information and the second display information in the band effect image. is executed, and a second dynamic display different from the first dynamic display is sequentially executed with respect to the first display information and the second display information.

The band effect image 242a of this embodiment differs from that of the first embodiment in that, in the first embodiment, as shown in FIG. Only the dynamic display (leftward moving motion) is performed, and the second character information (second display information) 235b is subjected to the first dynamic display (leftward moving motion) and the second motion display (upward moving motion). 100, in this embodiment, the second action display (upward jump action) is performed by first character information (first display information) 235a and second character information ( The only difference is that the second display information) 235b is sequentially executed.

100(a) to 100(g), the band effect image 242a of the present embodiment is moved in a predetermined direction (to the left in this case) along the information decoration image 236 with respect to the character information image 235. An action (first dynamic display) is performed, and an action of jumping upward (the first dynamic display is A different second dynamic display) is performed. In the example of FIG. 100, the second dynamic display of the first character information 235a is performed for all characters at once, while the second dynamic display of the second character information 235b is performed sequentially character by character. It's like Of course, the second dynamic display of the first character information 235a may be performed one character at a time, or the second dynamic display of the second character information 235b may be performed for all characters at once. good too.

Note that the second dynamic display is not limited to an upward jumping motion, but is a two-dimensional rotating motion (for example, a rotating motion around an axis perpendicular to the screen), a three-dimensional rotating motion (for example, a vertical or horizontal direction around an axis). It can be any kind of action, such as an action that looks as if it is rotating), a deformation action such as enlargement/reduction, or the like. As for the second dynamic display, if one of the odd-numbered image data and the even-numbered image data is assumed to be missing, it is desirable that the second dynamic display accompanies a change in the vertical direction. Also, the second dynamic display for the first character information 235a and the second dynamic display for the second character information 235b may be different.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the liquid crystal control board 98 of the embodiment, an example is shown in which the composite chip 104 and the liquid crystal control second connector CN32 are arranged in different wiring layers. wiring layer). In this case, out of the group of ODD-side data output terminals (first chip terminals) and the group of EVEN-side data output terminals (second chip terminals), the first chip terminals drawn out from the first chip terminals arranged on the outer peripheral side of the composite chip 104 One wiring path is connected to the liquid crystal control second connector CN32 on the A wiring layer side without an inter-layer conduction portion, and the second wiring path connected to the other second chip terminal is connected to the second chip terminal. Once moved to the B wiring layer side through vias (non-specific inter-layer conduction parts) arranged in the vicinity, and then through vias (specific inter-layer conduction parts) arranged in the vicinity of the liquid crystal control second connector CN32, A wiring layer It may be configured to return to the side and connect to the liquid crystal control second connector CN32. As a result, even when the liquid crystal control second connector CN32 is arranged in the same wiring layer (A wiring layer) as the composite chip 104, the first wiring path is arranged so that the wiring ratio to the A wiring layer is the highest, It is possible to arrange the second wiring path so that the ratio of wiring to the B wiring layer is the highest.

In this way, when the first chip terminals are arranged closer to the outer circumference of the chip than the second chip terminals, the first wiring path connected to the first chip terminals is replaced with the first wiring path where the chip is arranged. Place the second wiring path connected to the second chip terminal so that the wiring ratio to the layer is the highest, and arrange the second wiring path connected to the second chip terminal so that the wiring ratio to the B wiring layer, which is different from the A wiring layer, is the highest is desirable.

In the embodiment, an example has been shown in which the suspension notification image is dynamically displayed with changes in the vertical direction, but this dynamic display is not limited to movement and deformation. Together with or instead of them, a color change in the vertical direction (for example, the color distribution moves in the vertical direction over time) may be performed.

In addition, for example, when the display mode changes after the start of display of the hold notification image (for example, from ○ to elephant, from elephant to lion, etc.), color information is displayed at least in the vertical direction, such as gradually switching colors downward from the upper side. Change is desirable. This is the same when changing the display mode of other preview images.

When displaying an operation target image such as the button image 232, the operation target image may be dynamically displayed. In this case, the dynamic display may be a movement or a transformation that indicates how the image to be operated is manipulated. desirable.

In the embodiment, the band effect image is displayed in the button effect, but the band effect image can be displayed in all kinds of effects. For example, in the setting suggestive effects shown in FIGS. 97 and 98, a band effect image may be displayed in which the characters "entering the variable probability mode" are used as the information image.

The information image forming the band effect image is not limited to character information, and may be a symbol, a pattern, or the like, or may be a mixture of them. Further, the information decoration image that constitutes the band effect image may be arranged along the information image. Alternatively, it may have a curved shape or polygonal line shape. In addition, they may be arranged not only in the horizontal direction but also in the vertical direction or in an oblique direction such as upward to the right or downward to the right, or they may be arranged in a plurality of rows.

In the embodiment, an example in which the character information image 235 moves to the left as the first dynamic display has been shown, but the first dynamic display is not limited to this, and can be reciprocated in the left-right direction or the like, left-right direction or the like. It may be enlarged/reduced or otherwise modified. In addition, the second dynamic display may be different from the first dynamic display, and may be two-dimensional rotation (for example, rotation around an axis perpendicular to the screen), three-dimensional rotation (for example, vertical or horizontal). Any action such as an action that appears to rotate about an axis of a direction), a deformation action such as enlargement/reduction, etc. may be used. Assuming that either the odd-numbered image data or the even-numbered image data is missing, it is desirable that the first and second dynamic displays involve changes in the vertical direction. For this purpose, it is desirable to change by 2 dots or more per frame.

In the embodiment, as an example of the first rainbow color image effect performed before the win-lose branch effect of whether or not to give the privilege, the example of displaying the characters "Congratulations" in rainbow color was shown. The rainbow image in the rainbow image effect is not limited to this, and any partial image such as a character, a figure, or a character can be used as the rainbow image. FIG. 101(a) shows an example in which a rainbow image is used for the star-shaped figure 261 displayed during the ready-to-win production, and FIG. Examples are given respectively.

In FIG. 101, the color information of the star-shaped figure 261 and reach title character 262 changes in the horizontal direction. It is desirable that the direction of change is the vertical direction. Also, when the direction of change of color information is set to the horizontal direction, it is desirable that the color information be substantially common to each pair of pixel lines adjacent to the left and right (see FIG. 96(b)).

The rainbow image production described above displays a rainbow image that covers the seven colors of red, orange, yellow, green, blue, indigo, and purple. A gradation image production may be used.

It is desirable not to perform the rainbow effect in the look-ahead advance notice effect. This is because the player misunderstands that the change will be a big hit if the rainbow effect is performed with the change before the target change that is the object of the look-ahead determination. However, if the target of the rainbow effect is a clear pre-reading notice effect, the rainbow effect may be performed. For example, it is possible to execute a rainbow effect in which the pending image corresponding to the target change is a rainbow image in the pending change effect.

In the embodiment, for the wiring paths P2 to P42 for transmitting address information/data information between the composite chip 104 and the control ROM 105, specific inter-layer conductive portions arranged in the control ROM arrangement area (second arrangement area) 192 However, at least some of the wiring paths P2 to P42 may not have the specific inter-layer conductive portion.

In the embodiment, the vias v61 to v85 and v87 to v102 (specific inter-layer conduction portions) in the wiring paths P2 to P42 are arranged in the Y direction so that the corresponding terminals had1 to had25 and hdt0 to the terminals of the liquid crystal control first connector CN31 The Y-direction arrangement of the vias v61 to v85 and v87 to v102 (specific inter-layer conductive portions) may be made to match (or approximate) the terminal arrangement of the control ROM105.

In the embodiment, regardless of whether the test points to be checked exist on the front or back of the board, the test points that need to be checked while the board is assembled are placed on the outer surface of the board when the board is assembled. Although configured to display test point identification information, such test point identification information may be displayed on both sides of the board.

In the embodiment, among the terminals of the composite chip 104, the terminals (outer terminals) arranged in the second row on the outermost side and the inner side of the composite chip arrangement area (first arrangement area) 191 are formed in the first wiring layer. La1 is connected to the inter-layer conductive portion arranged outside the composite chip placement region 191, and the inner terminal (inner terminal) is arranged inside the composite chip placement region 191 in the first wiring layer La1. Although it is configured to be connected to the interlayer conductive portion, only the terminals on the outermost side in the composite chip placement area 191 may be used as outer terminals, or the terminals in the third row from the outermost side may be used as outer terminals.

Further, in the embodiment, only the wiring related to the terminal on the one edge side of the composite chip 104 was specifically illustrated, but the configuration is not limited to this, and the other edge side of the composite chip 104 has the same configuration or embodiment. may be configured to have the contents described in . Thus, by adopting the configuration described in this embodiment also on each edge side of the composite chip 104, it is possible to further increase the wiring efficiency. For example, a configuration as shown in FIG. 20 is given as an example.

In the embodiment, an example in which the first to sixth wiring layers La1 to La6 are provided on the liquid crystal control substrate 98 is shown, but the number of wiring layers may be smaller or larger than this. When the number of wiring layers is reduced, the solid wiring layer for ground connection and the solid wiring layer for power supply connection may be omitted.

The connection between the terminals of the composite chip 104 and the vias in the composite chip placement area 191 may be designed such that the distances between the terminals and the vias are substantially the same. As a result, the distances between the plurality of terminals and the vias are substantially equal, so that noise is less likely to enter and the vias can be arranged in a more appropriate state.

In addition, with regard to the directions in which wirings are drawn out from the terminals of the composite chip 104 toward the vias, it is desirable that vertically and horizontally adjacent terminals have the same wiring drawing direction (via arrangement direction). In addition, when these terminals are treated as a group, it is desirable that the direction of drawing out the wiring (the direction of arranging the vias) is different from that described above for another group of terminals. By setting the wiring lead-out direction (via arrangement direction) for each terminal group in this way, it becomes easy to check and recognize the information of each terminal by the wiring pattern, so that inspection and checking after completion is facilitated. Become. Also, by grouping the terminals for transmitting address information or grouping the terminals for transmitting data information, the above effects can be further exhibited. Further, with respect to terminals for individual signals such as chip select signals, confirmation and recognition may be facilitated by providing vias in a wiring lead-out direction different from that of the aforementioned group. In addition, by providing vias in a common wiring lead-out direction for terminals for chip select signals as well, important terminals and signal lines for chip select signals are made difficult to identify, and a configuration that is strong against fraudulent acts may be provided.

As shown in FIG. 34, a wiring pattern may be provided that reaches into or near the control ROM placement region 192 without vias, such as the wiring path cp221 connected to the HAD22 terminal of the composite chip 104 . By wiring in this manner, the number of vias around the composite chip 104 can be reduced, so that the corresponding space can be used as a location for installing other wirings and vias. Further, although the wiring path cp221 is connected to the via v53, it may be configured to be connected to the terminal of the control ROM 105 without via the via.

As shown in FIG. 35, wiring patterns of special terminals such as OE#, WE#, BYTE#, WP#ACC, CE#, and RESET# among the terminals of the control ROM 105 transmit address information and data information. The connection distance from the via may be set shorter than the wiring pattern. As a result, it is possible to easily distinguish the types of wiring patterns during board assembly, inspection, and the like. Conversely, by setting a long connection distance, it may be configured such that the types of wiring patterns can be easily distinguished. Also, since it is a terminal connection pattern for controlling the operation of the control ROM 105, it is desirable to use a relatively short wiring pattern in consideration of noise and the like.

As shown in FIG. 35, in the control ROM placement area 192, by displacing the first via array group (v61 to v85, etc.) and the second via array group (v87 to v102, etc.) in the X-axis direction, It is possible to make it easier to pull out wiring patterns in the Y-axis direction from each array group. If the first via array group and the second via array group are arranged in the Y-axis direction without being shifted in the X-axis direction, they will not fit in the control ROM arrangement area 192 and protrude. By arranging them so as to overlap in the Y-axis direction, the first via array group and the second via array group can be accommodated in the control ROM arrangement area 192, and the wiring space in the control ROM arrangement area 192 can be further reduced. Effective utilization is possible.

Even if the first via array group and the second via array group are shifted in the Y-axis direction and arranged so as to overlap in the X-axis direction, if they fit within the control ROM placement area 192, they are shifted in the Y-axis direction. may be arranged so as to overlap in the X-axis direction. In this case, it becomes difficult to pull out the wiring patterns in the Y-axis direction from each array group, but at least in the X-axis direction, there is no restriction. Also, for example, when the first via array group or the second via array group is the branch point, after considering the arrangement of the connection terminals at the branch destinations, they are arranged so as to be shifted in the Y-axis direction and overlapped in the X-axis direction. It may be so arranged if it results in a more efficient arrangement. Similarly, they may be arranged so as to be shifted in the X-axis direction and overlapped in the Y-axis direction. Depending on the shape of the control ROM layout area 192 and how the wiring pattern is routed, there may be a case where a more suitable layout relationship is obtained.

As shown in FIG. 28, the physical connection distance can be reduced by determining the layout relationship between the composite chip 104 and the control ROM 105 according to the position of the terminal arrangement of the composite chip 104 that is connected to the terminals of the control ROM 105. It may be configured to be closer. This is not limited to the control ROM 105 in particular, but is based on the position of each terminal of the composite chip 104. By determining the arrangement position, the arrangement direction, the distance, etc. of the electronic parts connected to these terminals, the wiring efficiency is increased. be able to. Of course, only specific electronic components, such as the control ROM 105, may be placed in the above-described arrangement relationship, thereby partially improving the wiring efficiency. By doing so, the wiring efficiency of the entire substrate can be improved.

In addition, regarding wiring that needs to connect composite chip 104 and a plurality of electronic components, such as a wiring pattern for transmitting address information and data information, a first electronic component (eg, control wiring) that is close to composite chip 104 (ROM 105) and a second electronic component farther away (e.g. liquid crystal control first connector CN31). may be increased. Further, it goes without saying that wiring efficiency can be further improved by providing both the first electronic component and the farther second electronic component on the side where the connection terminals of the composite chip are located. Moreover, wiring efficiency may be improved by providing the far second electronic component of the first electronic component and the second electronic component on the side where the connection terminal of the composite chip 104 is located. In this case, the first electronic component is placed on a side different from the side on which the connection terminals of the composite chip are located. If the wiring efficiency of the pattern is taken into consideration, this may be more effective. Also, the first electronic component is not limited to the control ROM, and may be a connector, a (termination) resistor, or the like. Similarly, the second electronic component is not limited to a connector, and may be a control ROM or (terminating) resistor.

As shown in FIG. 27, the terminals of the control ROM 105 include terminals (NC terminals, etc.) that are not connected to the terminals of the composite chip 104. In FIG. A via for connecting a wiring pattern connected to a terminal other than the NC terminal is provided in a location (region) shifted in the X-axis direction from the location where the NC terminal of the control ROM 105 is located in the ROM arrangement region 192 (FIG. 35). corresponds to v80 to v85) may be provided. The reason for this configuration is that there is no need to consider the wiring patterns and via layouts connected to the NC terminals, etc., so there is a tendency for wiring spaces to occur relatively easily around them, so that area is utilized. This is because vias can be placed by In addition, since there is enough space around the NC terminals and the like, there is an advantage that the wiring pattern can be easily pulled out from the via in the Y-axis direction or the X-axis direction. Moreover, the above effects can be obtained by applying the same configuration not only to the NC terminal but also to the VCC terminal and the GND terminal.

As shown in FIG. 40, vias (eg, v49 to v54) for connecting wiring patterns for connecting the terminals of the composite chip 104 and the terminals of the control ROM 105 are formed near or around the outside of the control ROM placement area 192. A wiring pattern is routed in the control ROM placement area 192 through the via, so that the via can be visually recognized from the outside of the substrate without being shielded by the control ROM 105 or the like. Compared to a wiring pattern in which vias are not provided in the vicinity of the outside of the area 192 or around it, confirmation and inspection of the wiring pattern connecting the terminals of the composite chip 104 and the terminals of the control ROM 105 are facilitated. Wiring efficiency can be improved by arranging vias near the outside.

As shown in FIGS. 35 and 37, the vias v69 to v73 are arranged in the control ROM placement area 192 together with other vias. The wiring pattern is drawn out to the control ROM arrangement area 192 via the . In this way, the wiring pattern that connects the vias (v69 to v73) arranged together with the other specific interlayer conductive portions and the terminals of the control ROM 105 is arranged in the control ROM placement region 192 via another via (v103 to v107). can be arranged to increase the wiring efficiency. Even in this case, since the vias v69 to v73 are arranged in the same manner as the other vias, it is possible to relatively easily perform inspections such as confirmation of the connection relationship and checking of energization.

Although the VDP+CPU composite chip 104 is exemplified in the embodiment, a CPU chip without the VDP function may be used. Also, the control ROM is not limited to a storage medium for storing control programs for the CPU, and may be a ROM for storing audio data and image data.

Vias located in the composite chip placement area 191 and the control ROM placement area 192 may be used as test points for continuity check. In this case, it is desirable to display test points (identification information display) by silk printing near or around the vias located in the composite chip placement area 191 and the control ROM placement area 192 . As a result, continuity check of the composite chip 104 and the control ROM 105 can be easily performed, and the composite chip placement area 191 and the control ROM placement area 192 can be used to place silk-printed notations of test points.

As shown in FIG. 55, by connecting the SRESET signal and the WTDOG signal to a common logic integrated circuit IC7, it is possible to appropriately perform reset processing when a reset signal is input due to any reset factor. It's becoming Further, the output information (reset signal) from the logic integrated circuit IC7 is output not only to the composite chip 104 and/or the control ROM 105, but also to the decoders IC13 and IC14 shown in FIG. IO-RST), it is possible to reset the liquid crystal display means 76. FIG. As a result, reset operations can be realized synchronously or at approximately the same timing by hardware such as different electronic components.

Also, in order to reset an external ROM such as a CGROM or an audio ROM, a reset signal may be separately output to the composite chip 104 (output from the DDR-RST in FIG. 55). In this manner, even when the output target is the same composite chip 104, a different reset signal may be output for each reset target. Accordingly, a circuit configuration can be provided in which reset processing can be performed according to the reset target and reset purpose. Further, as shown in FIG. 55, the IO-RST signal and the DDR-RST signal are also signals output from the logic integrated circuit IC7. This is a signal that is triggered by being input to the integrated circuit IC7.

In addition, although the common logic integrated circuit IC7 is used in the embodiment, the present invention is not limited to this, and a plurality of logic integrated circuits may be provided. In this case, different logic integrated circuits may be used for the CPU-RST signal, the IO-RST signal, and the DDR-RST signal, or different logic integrated circuits may be used for the CPU-RST signal, the IO-RST signal, and the DDR-RST signal. It may be configured to use a logic integrated circuit. When a plurality of logic integrated circuits are used in this way, although it is costly, it is possible to prevent a reset signal from being output to all hardware due to a problem. Even in this case, different logic integrated circuits are configured to receive a common SRESET signal and/or WTDOG signal.

As shown in FIG. 27, the terminals of the control ROM 105 include terminals (NC, etc.) that are not connected to the terminals of the composite chip 104. In FIG. A location (region) shifted in the X-axis direction with respect to the location where the NC terminal of the control ROM is located in the region 192, and a location (region) shifted in the X-axis direction with respect to the location where terminals other than the NC terminal are located. , the number of vias arranged in the control ROM arrangement area 192 may be varied. In this way, the space in the control ROM arrangement area 192 may be effectively utilized by varying the number of vias arranged for each corresponding location (area). In addition, of course, the wiring pattern pulled out from the via is connected to the terminals other than the NC terminal, so there is an advantage that the connection distance is shortened when arranging them close to each other. When a wiring pattern drawn from a via drawn out from a position (region) shifted in the X-axis direction with respect to the position where the X-axis is to be connected is connected, the connection distance becomes long, but the wiring space has a relatively large margin. , there is an advantage that routing becomes easy.

Among the vias in the control ROM arrangement area 192, vias that are not directly connected to the terminals of the control ROM (for example, a plurality of vias located between v68 and v74 in FIG. 35) are as shown in FIG. Alternatively, it may be provided at a location (region) shifted in the X-axis direction with respect to locations where terminals other than the NC terminals are located. This is because the wiring pattern is not drawn out from these vias on the first wiring layer La1, so that there is little possibility that the wiring space in the control ROM arrangement region 192 will be obstructed. Conversely, it may be provided in a location (area) shifted in the X-axis direction with respect to the location where the NC terminal of the control ROM 105 is located in the control ROM layout area 192 . In this case, a wiring space can be provided by a location (region) shifted in the X-axis direction with respect to locations where terminals other than the NC terminals are located. In any case, in the embodiment, the via arrangement as shown in FIG. 35 is constructed in consideration of the above-mentioned merits and also considering the connection relationship with electronic parts (eg, connectors) other than the control ROM. ing.

In the example of FIG. 35, vias for conducting wiring patterns for transmitting address information are arranged in a predetermined array, and vias for conducting wiring patterns for transmitting data information are arranged in a predetermined array. Although the via arrays are arranged in groups, the vias are not limited to this, and the vias that conduct the wiring patterns for transmitting the address information and the vias that conduct the wiring patterns for transmitting the data information are arranged in a predetermined arrangement. They may be arranged so as to form one via group. In this case, the vias for conducting the wiring patterns that transmit different information can be densely arranged, so that the installation range of the vias can be made relatively small. Further, like vias v87 to v90 shown in FIG. 35, some vias may be arranged as small groups in the array of vias that conduct wiring patterns for transmitting data information. A via for conducting a wiring pattern for transmitting address information may also have a similar configuration.

In the example of FIG. 35, vias for conducting wiring patterns for transmitting address information and vias for conducting wiring patterns for transmitting data information are arranged in a predetermined arrangement in the control ROM arrangement area 192, respectively. , the vias may be arranged in a predetermined arrangement outside the control ROM arrangement area 192 . In this case, the control ROM arrangement area 192 cannot be utilized, but since the wiring pattern is connected from the outside of the control ROM arrangement area 192 to the terminals of the control ROM 105, check the connection status for each terminal of the control ROM. It has the advantage of being easier. However, since the necessary wiring space is relatively large compared to the case of using the control ROM placement area 192, it is desirable to employ such a configuration when there is a relatively large margin of space.

As shown in FIG. 35, the wiring patterns of special terminals such as OE#, WE#, BYTE#, WP#/ACC among the terminals of the control ROM 105 are arranged from the outside of the control ROM arrangement area 192 to the terminals. , the connection status may be easily checked. Also, CE# and RESET# may be configured in the same manner. However, in the embodiment, CE#, which is a chip select input terminal for inputting a chip select signal, and RESET#, which is a reset terminal for inputting a reset signal, are likely to be subject to problems and failures. A wiring pattern is connected to each terminal from within the control ROM placement area 192 so that the pattern is not tampered with.

As shown in FIG. 34, with respect to the terminals of the composite chip 104 and the vias in the composite chip placement area 191, the composite chip terminals are arranged in a straight line in the Y-axis direction (and/or the X-axis direction). By arranging the vias in the arrangement region 191 in a straight line in the Y-axis direction (and/or the X-axis direction), it is possible to easily confirm the arrangement of each terminal and the arrangement of the vias, and at the same time, the space is reduced. Vias can be arranged in an aligned manner within the composite chip placement area 191, which has relatively little margin.

Also, as shown in FIG. 34, terminals of the composite chip 104 linearly aligned in the Y-axis direction (and/or X-axis direction) and vias linearly aligned in the Y-axis direction (and/or X-axis direction) are preferably arranged so as not to overlap each other in the Y-axis direction (and/or the X-axis direction). By configuring in this way, the vias can be arranged, for example, avoiding the terminals located adjacent to each other or in the vicinity, so that the wiring pattern from the vias can be easily arranged.

Further, as shown in FIG. 34, the vias in the composite chip placement region 191 are connected to outer terminals (eg, HAD18, HAD14, HAD10, HAD6, HAD21, HDT12, HDT7, HDT4) arranged near the periphery of the composite chip placement region 191. , HDT0) and/or terminals arranged inside (eg, HAD17, HAD13, HAD9, HAD5, HAD22, HDT13, HDT8, HDT5, HDT1) overlap each other in the X-axis direction (and/or the Y-axis direction). It is desirable to arrange in a position where As a result, the vias can be arranged while avoiding the outer terminals and/or the terminals arranged inside thereof, so that the wiring pattern from the vias can be easily arranged. That is, in the first wiring layer La1, if the vias are arranged so as to avoid the outer terminals and/or the terminals arranged inside thereof, when the wiring pattern is pulled out from the vias in a different wiring layer, the outer terminals and/or the inner sides of the outer terminals can be arranged. It is possible to draw out the wiring pattern linearly in the X-axis direction (and/or the Y-axis direction) without worrying about the terminals arranged in the direction.

Also, the outer terminals (eg, HAD18, HAD14, HAD10, HAD6, HAD21, HDT12, HDT7, HDT4, HDT0) arranged near the outer periphery of the composite chip arrangement area 191 shown in FIG. With respect to vias (eg V11 to V24) arranged to avoid terminals (eg HAD17, HAD13, HAD9, HAD5, HAD22, HDT13, HDT8, HDT5, HDT1), first specific vias (eg v18 to v24) and second specific vias (e.g., v11-v17) located inside the composite chip 104 relative to the first specific vias, avoiding the outer terminals and/or the terminals located inside them. As a result, they are arranged so as to overlap each other in the X-axis direction in the first wiring layer La1. In this case, for the second specific via arranged inside the composite chip 104 than the first specific via, for example, in a wiring layer different from the first wiring layer La1 as shown in FIG. The wiring pattern may be arranged so as to avoid one specific via. In this way, by using a plurality of wiring layers, the wires are arranged inside the composite chip placement region 191 so as to avoid the outer terminals arranged near the outer periphery of the composite chip placement region 191 and/or the terminals arranged inside thereof. A first specific via and a second specific via may be provided, and a wiring pattern drawn out from the second specific via may be provided so as to avoid the first specific via. As a result, the wiring pattern can be efficiently pulled out from inside the composite chip placement area 191 where there is relatively little wiring space to the outside of the composite chip placement area 191 . Further, here, specific terminals and specific vias are shown as examples based on FIGS. 34 and 40, but the configuration is not limited to this, and other terminals and vias may be configured in the same manner. For example, one edge side of the composite chip 104 is shown as an example in FIG. 34, but the other edge side may have the same configuration. In addition, when the first wiring layer La1 in the composite chip placement area 191 has a relatively large wiring space, the first specific via is arranged in the X-axis direction (and/or the Y-axis direction) in the first wiring layer La1. A second specific via may be configured to be placed to avoid.

As described above, the vias in the composite chip placement region 191 shown in FIG. 34 are arranged linearly in the Y-axis direction (and/or the X-axis direction). Even in different wiring layers, the vias in the composite chip placement area 191 are arranged linearly in the Y-axis direction (and/or the X-axis direction). Here, a first via (eg, v21), a second via (eg, v14) positioned inside the composite chip placement region 191 from the first via, and inside the composite chip placement region 191 from the second via The first via extends out of the composite chip placement region 191 by a wiring pattern drawn out linearly in the X-axis direction, and the second via extends to the first via The first wiring pattern drawn out linearly in the X-axis direction via the wiring pattern drawn out by the first distance in the direction avoiding the , and the first wiring pattern drawn out linearly in the direction in which the control ROM 105, which is the connection destination, is located The second wiring pattern advances outside the composite chip placement region 191, and the wiring pattern that the third via is pulled out by the first distance in a direction to avoid the first via and/or the second via (a wiring pattern that avoids the first via from the second via direction) and a wiring pattern drawn out linearly in the Y-axis direction (the wiring pattern length up to this point is the first distance in the direction avoiding the first via from the second via). The first wiring pattern is drawn out linearly in the X-axis direction and the second wiring pattern is drawn out linearly in the direction in which the control ROM 105, which is the connection destination, is located. The wiring pattern is configured to extend outside the composite chip placement area 191 . In this way, when the first via, the second via, and the third via are arranged toward the inside of the composite chip placement region 191 in this order, the outer vias are first placed in the composite chip placement region 191 . A wiring pattern may be provided to avoid this. As a result, the wiring space in the composite chip placement area 191 can be effectively utilized.

In the above example, the relationship between the first via, the second via, and the third via is shown by taking a specific via as an example, but the configuration is not limited to this, and the other vias shown in the figure can have the same configuration. desirable. In this way, by adopting the same configuration at a plurality of locations, it is possible to effectively utilize the wiring space in the composite chip placement area 191 more effectively than implementing at a single location. In the above example, a wiring layer different from the first wiring layer La1 in the composite chip placement area 191 is used. may However, since a plurality of terminals of the composite chip 104 are arranged in the first wiring layer La1, it is assumed that the wiring space is relatively limited. is desirable.

In the example of FIG. 34, like the terminals of the composite chip 104 from HAD1 to HAD0 arranged linearly in the Y-axis direction, wiring patterns drawn out from the respective terminals are drawn out in different directions (for example, HAD1 and HAD0 are -XY direction, +XY direction for HAD8, HAD3, HAD15 and HAD20, and -X+Y direction for HAD11), vias connected to each terminal are arranged linearly in the Y-axis direction. In this way, the terminals of the composite chip 104 arranged in a straight line in the Y-axis direction (and/or the X-axis direction) and the vias connected by the respective wiring patterns are arranged in a straight line in the Y-axis direction (and/or the X-axis direction). Terminals of the composite chip 104 that are not arranged in a straight line in the Y-axis direction (and/or the X-axis direction) and vias connected by wiring patterns are arranged in the Y-axis direction. (and/or in the X-axis direction). Even with such a configuration, the terminal array and via array of the composite chip 104 can be arranged linearly in the Y-axis direction (and/or the X-axis direction). It is possible to achieve the same effect as

In the example of FIG. 34, from a plurality of terminals (eg, HDT6, HDT10, HDT15, and HAD24) of the composite chip 104 arranged in a straight line in the Y-axis direction, wiring patterns are drawn out in substantially the same direction, and the composite chip layout is shown in FIG. Vias (eg, v17 to v14) are arranged linearly in the region 191 in the Y-axis direction. As shown in FIG. 40, the first wiring layer La1 is electrically connected to the fourth wiring layer La4 through these vias, and the wiring pattern is led out from the fourth wiring layer La4. In this way, with respect to the terminals of the composite chip 104 that have common conduction destinations from vias (here, the fourth wiring layer La4), wiring patterns may be drawn out in the same direction from each terminal. Similarly, vias connected to each terminal may be arranged linearly in the Y-axis direction within the composite chip placement area 191 . In this case, as shown in FIG. 34, an address output terminal for outputting address information and a data input/output terminal for inputting/outputting data information may be configured as described above. The above-described configuration may be configured with only address output terminals for outputting information or only data input/output terminals for inputting/outputting data information. By configuring in this way, it becomes easy to check the arrangement of each terminal, the arrangement of vias, and the wiring pattern serving as a connection path. In addition, not only the terminals of the composite chip 104 having the same conduction destination (here, the fourth wiring layer La4) from the via, but also the connection from the via to the connection destination (eg, the control ROM 105) through the wiring pattern. The terminals of the composite chip 104 having the same type may be configured as described above. In addition, the wiring route from the via to the connection destination (eg, control ROM 105) through the wiring pattern (which wiring layer is passed through, what wiring pattern is used for wiring, etc.) is substantially common. The terminals of the composite chip 104 may be configured as described above. By configuring in this way, it becomes easy to check the arrangement of each terminal, the arrangement of vias, and the wiring pattern serving as a connection path.

In the above description, the arrangement of vias v60 to v85 and v87 to v107 (specific inter-layer conduction portions) in the control ROM arrangement area 192 is approximated to the arrangement of the corresponding terminals (specific second terminals) on the control ROM 105 side. The word "approximation" is used in this example, but this "approximation" may mean that the arrangement of all the terminals and vias that are in the connection relationship are the same, or that the arrangement of all terminals and vias that are in the connection relationship Some terminals and vias may have the same arrangement. In addition, when there are a plurality of items in a connection relationship (for example, a control ROM terminal and a connector terminal for a predetermined via), the arrangement of one or both of the terminals may be the same. Also, when there are a plurality of connection destinations, there is no problem if they are the same electronic component, but if they are different electronic components, there is a high possibility that the arrangements of both terminals are different. In that case, it is practically impossible to have a via arrangement that completely matches the arrangement of both terminals. Therefore, in order to match the arrangement of both terminals as much as possible, the arrangement may be partially common. For example, a partial arrangement of the terminals of the first connection (partial arrangement of the terminals of the control ROM 105), a partial arrangement of the terminals of the second connection (partial arrangement of the terminals of the connector), and may correspond to a partial arrangement of the terminals of the first connection destination (arrangement of a part of the terminals of the control ROM), but the terminals of the second connection destination (partial arrangement of connector terminals) is not supported However, a second via array corresponding to a partial array of the terminals of the second connection destination (a partial array of the terminals of the connector) may be provided. It is also assumed that such an arrangement of vias has the aforementioned "approximation" relationship.

Regarding the assembly of boards, "assembly" may be a combination of a plurality of boards to complete one control board, or a state in which a harness is inserted into a connector for one board so that it can conduct electricity. , and may be connected to another substrate via a harness. In addition, it is not limited to a plurality of substrates or a single substrate, and various electronic components required for operation may be attached to the substrate.

The contents of the above embodiments can be combined arbitrarily, and by combining them, the wiring efficiency can be increased more effectively, and a substrate configuration that is resistant to noise and fraud can be obtained.

In addition, all terminal arrangements, wiring patterns, installation positions of electronic components, etc. shown in the drawings were constructed by seeking optimum solutions. , miniaturization of the substrate and noise reduction are possible.

Further, the present invention can be similarly implemented in various pinball game machines such as an arrange ball machine and a mammoth game machine, as well as game machines other than pinball game machines such as slot machines.

76 liquid crystal display means 98 liquid crystal control board (display control means)

Claims (1)

A display control means for performing display control of the liquid crystal display means,
In a gaming machine capable of displaying an advance notice image regarding occurrence of a predetermined event on the liquid crystal display means,
The display control means outputs odd-numbered image data corresponding to odd-numbered pixels and even-numbered image data corresponding to even-numbered pixels adjacent to the odd-numbered pixels to the liquid crystal display means through different wiring paths. compose and
When dynamically displaying the preview image, the preview image is configured to change for each frame even if either the odd image data or the even image data is missing,
A gaming machine characterized in that, when the preview image is dynamically displayed, the preview image changes by two dots or more in the direction in which the odd-numbered pixels and the even-numbered pixels are arranged for each frame.

Images