JP2022024947A - Nitride-based high-electron mobility transistor, and method for manufacturing the same - Google Patents

Abstract

To provide a PEC etching technique which is to be used for manufacturing a nitride-based high-electron mobility transistor.SOLUTION: A method for manufacturing a nitride-based high-electron mobility transistor comprises the steps of: providing a conductive member on a substrate outside a device region in plan view; forming, on the substrate, a mask having an opening in at least one of a source recess etching region and a drain recess etching region; exposing the substrate to light in a state in which the substrate having the conductive member provided thereon and the mask formed thereon is put in contact with an etchant containing an oxidizing agent capable of receiving an electron, thereby performing a photoelectrochemical etching process to form at least one of a source recess and a drain recess; and forming a device isolation structure.SELECTED DRAWING: Figure 3

Description

The present invention relates to a method for manufacturing a nitride-based high electron mobility transistor and a nitride-based high electron mobility transistor.

Group III nitrides such as gallium nitride (GaN) are used as materials for manufacturing semiconductor devices such as light emitting devices and transistors.

Photoelectrochemical (PEC) etching has been proposed as an etching technique for forming various structures on Group III nitrides such as GaN (see, for example, Non-Patent Document 1). PEC etching is wet etching with less damage than general dry etching, and damage such as neutral particle beam etching (see, for example, Non-Patent Document 2) and atomic layer etching (see, for example, Non-Patent Document 3). It is preferable in that the apparatus is simpler than the special dry etching with less.

K. Miwa, Appl. Phys. Express 13, 026508 (2020). S. Samukawa, JJAP, 45 (2006) 2395. T. Ohba, Jpn. J. Appl. Phys. 56, 06HB06 (2017).

One object of the present invention is to provide a PEC etching technique used for manufacturing a nitride-based high electron mobility transistor.

According to one aspect of the invention
A method for manufacturing a nitride-based high electron mobility transistor.
A step of providing a conductive member on a nitride semiconductor crystal substrate outside the element region of the high electron mobility transistor in a plan view.
On the nitride semiconductor crystal substrate, a source recess etched region in which a source recess, which is a recess in which the source electrode of the high electron mobility transistor is arranged, is formed, and a drain electrode of the high electron mobility transistor are arranged. A step of forming a mask having an opening in at least one of the drain recess etched regions in which the drain recess, which is the recess, is formed, and
The nitride semiconductor crystal substrate is irradiated with light in a state where the nitride semiconductor crystal substrate on which the conductive member is provided and the mask is formed is in contact with an etching solution containing an oxidizing agent that receives electrons. In the step of performing photoelectrochemical etching to form at least one of the source recess and the drain recess.
The step of forming the element separation structure of the high electron mobility transistor and
A method for manufacturing a nitride-based high electron mobility transistor having the above is provided.

According to another aspect of the invention.
Nitride-based high electron mobility transistor
A Group III nitride layer having at least a channel layer, a barrier layer arranged on the channel layer, and a cap layer arranged on the barrier layer.
Source electrode, gate electrode, and drain electrode,
Element separation structure and
Equipped with
At least, plasma damage is not introduced into the Group III nitride layer located directly below the source electrode and the drain electrode.
Nitride-based high electron mobility transistors are provided.

PEC etching techniques used in the manufacture of nitride-based high electron mobility transistors are provided.

FIG. 1A is a schematic cross-sectional view illustrating HEMT according to an embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view illustrating a PEC etching apparatus. 2 (a) to 2 (c) are schematic cross-sectional views illustrating the manufacturing process of the HEMT according to the present embodiment. 3 (a) to 3 (c) are schematic cross-sectional views illustrating the manufacturing process of the HEMT according to the present embodiment. 4 (a) to 4 (c) are schematic cross-sectional views illustrating the manufacturing process of the HEMT according to the present embodiment. 5 (a) to 5 (c) are schematic cross-sectional views illustrating the manufacturing process of the HEMT according to the present embodiment. 6 (a) and 6 (b) are schematic plan views illustrating the manufacturing process of the HEMT according to the present embodiment. 7 (a) and 7 (b) are schematic plan views illustrating the manufacturing process of the HEMT according to the present embodiment. 8 (a) and 8 (b) are schematic cross-sectional views schematically showing the mechanism of PEC etching forming a gate recess. FIG. 9A is a schematic plan view showing a planar arrangement example of the element separation structure according to the first modification, and FIG. 9B is a planar arrangement of the element separation structure 160 according to the second modification. It is a schematic plan view which shows an example. 10 (a) and 10 (b) are schematic cross-sectional views illustrating the manufacturing process of the HEMT according to the second modification. FIG. 11 is a schematic plan view showing a planar arrangement example of the cathode pad according to the third modification. FIG. 12 is a schematic cross-sectional view illustrating HEMT according to the fourth modification. FIG. 13 is a schematic cross-sectional view illustrating the process of another embodiment in which the element separation structure is formed by PEC etching. FIG. 14 is a schematic plan view illustrating another embodiment in which a part of the cathode pad overlaps with the element region. 15 (a) and 15 (b) are schematic cross-sectional views illustrating the manufacturing process of the HEMT according to another embodiment in which the cathode pad (cathode portion) is composed of a group III nitride, respectively, and the said object. It is a schematic cross-sectional view which illustrates HEMT. FIG. 16 is a schematic cross-sectional view illustrating HEMT according to still another embodiment in which the cathode pad (cathode portion) is composed of Group III nitride.

In a high electron mobility transistor (nitride-based high electron mobility transistor) using a group III nitride, a technique of forming a cap layer on a barrier layer is used. The barrier layer is made of, for example, aluminum gallium nitride (AlGaN), and the cap layer is made of, for example, GaN. Hereinafter, the nitride-based high electron mobility transistor is also simply referred to as HEMT.

In the prior art, the HEMT source and drain electrodes are formed on the cap layer, which makes it impossible to reduce the contact resistance of the source and drain electrodes.

It is conceivable to reduce the contact resistance of the source electrode and the drain electrode by removing the cap layer. However, the conventional technique for etching the cap layer is dry etching, and the contact resistance cannot be reduced even if the cap layer is removed due to the etching damage caused by the dry etching.

Photoelectrochemical (PEC) etching has been proposed as a new technique for etching Group III nitrides such as GaN while suppressing etching damage. As a technique for PEC etching according to HEMT, the inventor of the present application has previously proposed a technique for forming a gate recess by PEC etching by using a source electrode or a drain electrode as a cathode pad (Japanese Patent Application No. 2019-). 140027). The cathode pad is a conductive member used for advancing electrodeless PEC etching, as will be described in detail later.

In the gate recess forming technique, the cap layer interposed under the source electrode or the drain electrode could not be removed by PEC etching. The source electrode and the drain electrode were formed on the cap layer, and the contact resistance caused by the cap layer of the source electrode and the drain electrode could not be reduced.

By using PEC etching, etching damage can be suppressed and the cap layer can be removed. However, it is not known how to perform PEC etching to remove the cap layer interposed under the source electrode or the drain electrode. The inventor of the present application proposes such a technique in the following embodiments.

<Embodiment>
A nitride-based high electron mobility transistor (HEMT) 150 according to an embodiment of the present invention will be described. FIG. 1A is a schematic cross-sectional view illustrating HEMT150, and shows one HEMT element. The HEMT 150 includes a laminate 10, a source electrode 151, a gate electrode 152, a drain electrode 153, an element separation structure 160, and an insulating film 170.

The laminate (nitride semiconductor crystal substrate) 10 has a substrate (base substrate) 11 and a group III nitride layer 12 (hereinafter, also referred to as epi layer 12) formed on the substrate 11. The substrate 11 is a crystal substrate that serves as a base for epitaxially growing the epi layer 12, and as the substrate 11, for example, a semi-insulating substrate is used. Here, the “semi-insulating property” means, for example, a state in which the specific resistance is ¹⁰⁵ Ωcm or more. As the semi-insulating substrate, for example, a semi-insulating silicon carbide (SiC) substrate is used, and for example, a semi-insulating gallium nitride (GaN) substrate is used. The semi-insulating GaN substrate is, for example, a (Fe) -doped or manganese (Mn) -doped GaN substrate.

When a SiC substrate is used for the substrate 11, the epi layer 12 is composed of, for example, a nucleation layer 12a made of aluminum nitride (AlN), a channel layer 12b made of GaN, and aluminum gallium nitride (AlGaN). A laminated structure of the barrier layer 12c and the cap layer 12d made of GaN is used.

In the laminated structure of the channel layer 12b and the barrier layer 12c, a two-dimensional electron gas (2DEG) serving as a channel of HEMT150 is formed in the vicinity of the upper surface of the channel layer 12b. In addition to GaN, AlGaN may be used as the material for the channel layer 12b. As the AlGaN used for the channel layer 12b, one having a lower Al composition (smaller bandgap) than the AlGaN used for the barrier layer 12c is used.

The substrate 11 is not limited to the SiC substrate, and other substrates (sapphire substrate, silicon (Si) substrate, (semi-insulating) GaN substrate, etc.) may be used. The laminated structure of the epi layer 12 may be appropriately selected depending on the type of the substrate 11, the characteristics of the HEMT 150 to be obtained, and the like. For example, in the epi layer 12 when a GaN substrate is used for the substrate 11, the nucleation layer 12a may be omitted.

The upper surface of the epi layer 12 is composed of the c-plane of the group III nitride constituting the epi layer 12. Here, "consisting of the c-plane" means that the crystal plane having the lowest index closest to the upper surface is the c-plane of the Group III nitride crystal constituting the epi layer 12. The group III nitride constituting the epi layer 12 has dislocations (through dislocations), and dislocations are distributed at a predetermined density on the upper surface thereof.

The laminate 10 may have a passivation insulating film 13 (hereinafter, also referred to as an insulating film 13) arranged on the epi layer 12. The insulating film 13 is made of, for example, silicon nitride.

Of the epi layer 12, the portion below the channel layer 12b is referred to as the epi lower layer 12L, and the portion above the channel layer 12b is referred to as the epi upper layer 12U. The epi lower layer 12L contains a channel layer 12b on which 2DEG is formed. The epi upper layer 12U includes a barrier layer 12c formed on the channel layer 12b and a cap layer 12d formed on the barrier layer 12c. The barrier layer 12c is composed of a group III nitride having a bandgap larger than that of the group III nitride constituting the channel layer 12b, and 2DEG is generated in the channel layer 12b. The cap layer 12d is composed of a group III nitride having a smaller bandgap than the group III nitride constituting the barrier layer 12c.

In the HEMT 150 of the present embodiment, the gate electrode 152 is arranged in the gate recess 110G, the source electrode 151 is arranged in the source recess 110S, and the drain electrode 153 is arranged in the drain recess 110D. The gate recess 110G, the source recess 110S, and the drain recess 110D are recesses (structures formed by etching the epi upper layer 12U) formed in the epi upper layer 12U, respectively. Hereinafter, the source recess 110S and the drain recess 110D may be collectively referred to as an ohmic recess 110SD (to represent at least one of the source recess 110S and the drain recess 110D without particular distinction).

The gate recess 110G is a recess formed in the epi upper layer 12U by etching the cap layer 12d and a part of the barrier layer 12c, and the barrier layer 12c is exposed at the bottom of the gate recess 110G. The thickness of the barrier layer 12c below the gate recess 110G (thickness from the upper surface of the channel layer 12b to the bottom of the gate recess 110G) is set to a predetermined thickness so that the threshold gate voltage of the HEMT 150 becomes a predetermined value. good.

The ohmic recess 110SD is a recess formed in the epi upper layer 12U by etching the cap layer 12d (only), and the barrier layer 12c is exposed at the bottom of the ohmic recess 110SD. Ohmic recess 110SD is shallower than gate recess 110G. By arranging the source electrode 151 and the drain electrode 153 in the ohmic recess 110SD, respectively, the contact resistance of the source electrode 151 and the drain electrode 153 can be reduced. It is considered that this is because the source electrode 151 and the drain electrode 153 come into direct contact with the barrier layer 12c, and the lifting of the band caused by the cap layer 12d is suppressed.

The gate electrode 152 is formed, for example, by a Ni / Au layer in which a gold (Au) layer is laminated on a nickel (Ni) layer. In each of the source electrode 151 and the drain electrode 153, for example, an aluminum (Al) layer was laminated on a titanium (Ti) layer, a Ti layer was laminated on the Al layer, and an Au layer was further laminated on the Ti layer. It is formed by a Ti / Al / Ti / Au layer.

The element separation structure 160 is a structure that divides the cap layer 12d and 2DEG between adjacent HEMT elements, and electrically separates the adjacent HEMT elements with the element separation structure 160 interposed therebetween. As the element separation structure 160, the element separation groove is exemplified in this embodiment, but the element separation structure 160 may be formed by ion implantation instead of forming the groove. The element separation structure 160, which is an element separation groove, is formed so that its bottom reaches a depth in the middle of the channel layer 12b.

The element separation structure 160 defines an element region 180 that functions as a HEMT element. In a plan view, the internal region of the closed edge (HEMT element side, that is, the inner edge) surrounding the HEMT element of the element separation structure 160 becomes the element region 180 (see FIG. 7A).

The insulating film 170 has an opening on the upper surface of the source electrode 151 and the drain electrode 153, covers the element separation structure 160, and extends to the outside of the element separation structure 160. The insulating film 170 of the present embodiment is provided as a gate insulating film, and is interposed between the gate recess 110G and the gate electrode 152. The insulating film 170 is made of, for example, aluminum oxide.

In this embodiment, the ohmic recess 110SD is formed by etching the epi upper layer 12U by photoelectrochemical (PEC) etching. In this embodiment, the gate recess 110G is also formed by etching the epi upper layer 12U by PEC etching. In the manufacturing process of HEMT150, an intermediate structure that is subjected to various treatments until the HEMT150 is completed is referred to as a treatment target 100.

FIG. 1B is a schematic cross-sectional view illustrating the PEC etching apparatus 200. The PEC etching apparatus 200 has a container 210 for accommodating the object to be processed 100 and the etching solution 201, and a light source 220 for emitting light 221.

The object 100 to be processed in PEC etching includes a laminate 10 (at least epi lower layer 12L and epi upper layer 12U), a cathode pad 30, and a mask 50. The laminate 10 (more specifically, the epi upper layer 12U) has a region 21 to be etched that is etched by PEC etching. The etched region 21 is defined by the mask 50. The object 100 to be processed in PEC etching is more specifically exemplified in FIGS. 2 (c) and 3 (b).

In PEC etching, the object to be processed 100 is immersed in the etching solution 201, and the region 21 to be etched is irradiated with light 221 through the etching solution 201 in a state where the region 21 to be etched and the cathode pad 30 are in contact with the etching solution 201. (PEC etching is performed by irradiating the laminate 10 with light 221 in a state where the laminate 10 on which the cathode pad 30 is provided and the mask 50 is formed is in contact with the etching solution 201. Will be).

The mechanism of PEC etching will be described, and the etching solution 201, the cathode pad 30, and the like will be described in more detail. Gallium nitride (GaN) will be described as an example of a group III nitride that is PEC-etched.

The PEC etching is wet etching, and is performed in a state where the object 100 to be processed is immersed in the etching solution 201. The etching solution 201 contains oxygen used to generate an oxide of a Group III element contained in the Group III nitride constituting the region 21 to be etched, and further contains an oxidizing agent that receives electrons, and is alkaline or acidic. Etching solution 201 is used.

Peroxodisulfate ion ( _{S2O 8-2-} ) is preferably used as the oxidizing agent, and as the etching solution 201, (at least) a salt of ^{peroxodisulfate} ion _{( S2O} ^8-2- ) is watered at a predetermined concentration. An aqueous solution dissolved in is used. More specifically, the oxidizing agent is such that a sulfate ion radical (SO ^{4- *} ) generated from _{S2O 8 2-} receives an electron and changes ^into a sulfate ion (SO _4-2- ). Function.

Examples of the salt of S ₂ O ₈ ^2- used in the etching solution 201 include ammonium peroxodisulfate (NH ₄ ) ₂ S ₂ O ₈ and potassium peroxodisulfate (K ₂ S ₂ O ₈ ) and sodium peroxodisulfate (Na). ₂ S ₂ O ₈ ) and the like. From the viewpoint of suppressing the residual alkali metal elements caused by the etching solution 201, it is preferable to use ₂ S ₂ O ₈ containing no alkali metal (NH ₄ ).

In addition, all of these aqueous solutions of S ₂ O ₈₂ ^- salt are acidic. For example, an alkaline etching solution 201 can be obtained by mixing an alkaline aqueous solution such as a KOH aqueous solution with an aqueous solution of these _S2O ^82- _salts at an appropriate concentration.

The reaction in PEC etching of this embodiment can be summarized as in (Chemical formula 1).

The reaction for producing SO _4- ^* from S ₂ O ₈ ^2- contained in the etching solution is shown by (Chemical formula 2). That is, SO _4- ^* can be produced by at least one of heating S ₂ O ₈ ² and irradiating S ₂ O ₈ ² with light.

As shown in (Chemical Formula 1), the group III nitride has light 221 having a wavelength or less corresponding to the band gap of the group III nitride (in this example, ultraviolet light 221 having a wavelength of 365 nm or less corresponding to the band gap of GaN). Is irradiated to generate holes (h ⁺ ) and electrons (e ⁻ ) in the group III nitride. Due to the formation of holes, Group III nitride (GaN in this example) is decomposed into Group III elemental cations (Ga ³⁺ in this example) and nitrogen gas ( _N2 gas), and Group III elemental cations are decomposed into water (N2 gas). By combining with oxygen contained in H ₂ O), an oxide of a Group III element (Ga ₂ O ₃ in this example) is produced. The group III nitride is etched by dissolving the oxide of the group III element in the alkaline or acidic etching solution 201. The electrons generated in the Group III nitride are consumed by ^{combining with SO 4-} _* ^to form SO _4-2- . As the PEC etching progresses, the hydrogen ion (H ⁺ ) concentration increases, which causes the pH of the etching solution 201 to decrease.

PEC etching can be performed regardless of whether the etching solution 201 is alkaline or acidic, but since the resist mask has low resistance to alkali, when a resist mask is used, the etching solution 201 which is acidic (from the start of PEC etching) is used. It is preferable to use it.

Further, as described in another embodiment described later, it is acidic (from the start of PEC etching) from the viewpoint of self-stopping PEC etching by reducing 2DEG (suppressing the occurrence of excessively deep PEC etching). It is preferable to use the etching solution 201.

The cathode pad 30 is a conductive member made of a conductive material such as metal, and is a conductive member of an object 100 to be processed, which is electrically connected to an etched region 21 via at least one of a cap layer 12d and 2DEG. It is provided so as to be in contact with at least a part of the surface of the sex region (see FIG. 8 (a)). Further, the cathode pad 30 is provided so that at least a part of the cathode pad 30, for example, the upper surface thereof comes into contact with the etching solution 201 during PEC etching. The cathode pad 30 is made of, for example, titanium (Ti).

In the region 21 to be etched by PEC etching, a hole is generated by light irradiation, so that an oxide of a group III element is generated. That is, the etched region 21 functions as an anode in which holes are consumed. By irradiating the region 21 to be etched with light, the electrons generated in pairs with the holes can flow to the cathode pad 30 via at least one of the cap layer 12d and 2DEG. The surface of the cathode pad 30 in contact with the etching solution 201 functions as a cathode consumed by the emission of the electrons into the etching solution 201. By making the cathode pad 30 function as a cathode in this way, PEC etching can proceed.

In the PEC etching according to the present embodiment, the group III nitride is produced by S2 O _{8 2- (more specifically, SO 4- * produced from S 2 O 8} ^2- ₎ ^{contained in} _{the etching solution} 201 as an oxidizing agent. PEC etching can be advanced by consuming the electrons generated together with the holes by irradiating the light with the light. That is, PEC etching can be performed in such a manner that electrons are directly emitted from the object 100 to be processed into the etching solution 201 (without going through external wiring).

On the other hand, as a PEC etching technique that does not use such an oxidizing agent, a cathode in which electrons generated in a group III nitride are immersed in the etching solution via a wiring extending outside the etching solution. There is a form of PEC etching in which the electrode is discharged into the etching solution. In contrast to the electrodeed PEC etching using such a cathode electrode, the PEC etching according to the present embodiment is a non-electrode (contactless) PEC etching that does not require such a cathode electrode.

PEC etching can also be performed on group III nitrides other than the exemplified GaN. The group III element contained in the group III nitride may be at least one of aluminum (Al), gallium (Ga) and indium (In). The concept of PEC etching for the Al component or In component in the Group III nitride is the same as the concept described with reference to (Chemical formula 1) for the Ga component. That is, PEC etching is performed by forming holes by irradiating the Group III nitride with light to generate an oxide of Al or an oxide of In, and dissolving these oxides in an alkaline or acidic etching solution. It can be performed. The wavelength of the light 221 to be irradiated may be appropriately changed depending on the composition of the group III nitride to be etched. Based on the PEC etching of GaN, when Al is contained, light 221 having a shorter wavelength may be used, and when In is contained, light 221 having a longer wavelength can also be used. That is, depending on the composition of the group III nitride to be etched, light 221 having a wavelength such that the group III nitride is PEC-etched can be appropriately selected and used.

Next, a method for manufacturing HEMT150 according to the present embodiment will be described. The manufacturing method of the present embodiment includes a step of providing a cathode pad 30 outside the element region 180 of the HEMT 150 in a plan view on the laminated body 10 (see FIGS. 2 (b) and 6 (a)) and the laminated body. A step of forming a mask 50 having an opening in the etched region 21SD on which the ohmic recess 110SD is formed (see FIG. 3B) and a step of forming the ohmic recess 110SD by PEC etching (FIG. 3 (c)). ) And a step of forming the element separation structure 160 (see FIG. 4B).

A plurality of HEMT elements are periodically arranged side by side in at least one direction in the gate length direction and the gate width direction on the wafer of the laminate 10 on which the HEMT 150 is formed. Correspondingly, a plurality of cathode pads 30 may be periodically arranged side by side in at least one direction in the gate length direction and the gate width direction.

2 (a) to 5 (c) are schematic cross-sectional views illustrating the manufacturing process of HEMT150 according to the present embodiment. In order to avoid the complexity of the figure, in FIGS. 2 (a) to 5 (c), the portion of the laminated body 10 over the channel layer 12b is shown. In the cross-sectional views of FIGS. 2 (a) to 5 (c), one HEMT element is shown.

6 (a) to 7 (b) are schematic plan views illustrating the manufacturing process of HEMT150 according to the present embodiment. In the plan view of FIGS. 6A to 7B, two HEMT elements arranged in the gate length direction are shown.

See FIG. 2 (a). A wafer of the laminated body 10 is prepared. The laminate 10 has regions 21G, 21SD, 21IS and 21CP to be etched. The region to be etched 21G is a region to be etched to form a gate recess 110G, which is a recess in which the gate electrode 152 is arranged. The region to be etched 21SD is a region to be etched to form an ohmic recess 110SD, which is a recess in which the source electrode 151 or the drain electrode 153 is arranged. The region 21IS to be etched is a region to be etched in order to form the element separation structure 160 which is an element separation groove. The region to be etched 21CP is a region to be etched to form a recess 110CP in which the cathode pad 30 is arranged. Hereinafter, each of the etched regions 21G to 21CP is also simply referred to as a region 21G to 21CP.

See FIG. 2 (b). Photolithography and etching form recesses in the regions 21G, 21SD, 21IS, and 21CP of the insulating film 13 where the cap layer 12d is exposed at the bottom. For the etching of the insulating film 13, for example, wet etching with a buffered hydrofluoric acid aqueous solution, an aqueous hydrofluoric acid solution or the like is used, and for example, low damage dry etching by atomic layer etching, neutral particle beam etching or the like is used.

Further, by photolithography and etching, a recess 110CP in which the barrier layer 12c is exposed is formed in the region 21CP of the cap layer 12d. For the etching of the cap layer 12d forming the concave portion 110CP, for example, low damage dry etching by atomic layer etching, neutral particle beam etching, or the like is used.

After forming the recess 110CP, for example, a Ti film is deposited on the entire upper surface of the object to be treated 100, and the unnecessary Ti film on the outside of the recess 110CP is removed by lift-off to form the cathode pad 30.

Since the cap layer 12d is usually doped in an n-type (has n-type conductivity), the cathode pad 30 may be formed on the cap layer 12d. By forming the cap layer 12d in the recess 110CP from which the cap layer 12d has been removed, that is, directly above the barrier layer 12c, the contact resistance of the cathode pad 30 can be reduced. On the other hand, by forming the cathode pad 30 on the cap layer 12d, it is possible to omit the photolithography and etching steps for removing the cap layer 12d of the recess 110CP.

The cathode pad 30 formed on the cap layer 12d or the barrier layer 12c and the region 21 to be etched using the cathode pad 30 are electrically connected to each other via at least one of the cap layer 12d and 2DEG. Be connected. The conductivity of 2DEG is higher than that of the cap layer 12d.

See FIG. 2 (c). For example, a silicon oxide film is deposited on the entire upper surface of the object to be treated 100. By photolithography and etching, the portion of the silicon oxide film placed on the region 21G and the upper surface of the cathode pad 30 is removed to form the hard mask 51 placed above the cap layer 12d. .. For example, a buffered hydrofluoric acid aqueous solution is used for etching the silicon oxide film. In the present specification, the hard mask means a mask made of an inorganic material or a metal material (as opposed to a resist mask made of an organic material).

See FIG. 3 (a). The gate recess 110G is formed by etching the cap layer 12d and the barrier layer 12c of the region 21G by PEC etching using the hard mask 51 (and the insulating film 13 or the like interposed below the hard mask 51) as the mask 50.

8 (a) and 8 (b) are schematic cross-sectional views schematically showing the mechanism of PEC etching forming the gate recess 110G. FIG. 8A shows a situation in which PEC etching is in progress, and FIG. 8B shows a situation in which PEC etching is stopped.

As described above, the electrons generated by irradiating the region 21G to be etched with light flow to the cathode pad 30 via at least one of the cap layer 12d and 2DEG, and are discharged from the surface of the cathode pad 30 to the etching solution 201. As a result, PEC etching proceeds. FIG. 8A shows a schematic flow of electrons indicated by an arrow 35.

When the barrier layer 12c becomes thin as the PEC etching progresses and the 2DEG below the gate recess 110G decreases, the PEC etching becomes difficult to proceed, and eventually, as shown in FIG. 8B, it is predetermined below the gate recess 110G. PEC etching automatically stops (self-stop) with the thick barrier layer 12c remaining. The predetermined thickness can be adjusted by, for example, the intensity of the light 221 and can be set so that the threshold gate voltage of the HEMT 150 becomes a predetermined value.

See FIG. 3 (b). A resist mask 52 (mask 50) having an opening is formed on the region 21SD and the upper surface of the cathode pad 30. By etching the hard mask 51 on the region 21SD using the resist mask 52 as a mask, the cap layer 12d of the region 21SD is exposed.

See FIG. 3 (c). The ohmic recess 110SD is formed by etching the cap layer 12d of the region 21SD by PEC etching using the resist mask 52 (and the hard mask 51 and the insulating film 13 interposed below the resist mask 52) as the mask 50. .. After that, the resist mask 52 is removed.

See FIG. 4 (a). A resist mask 53 having an opening is formed on the region 21IS. The resist mask 53 is filled in the gate recess 110G and the ohmic recess 110SD and covers the entire upper surface of the cathode pad 30.

See FIG. 4 (b). The element is formed by etching the cap layer 12d, the barrier layer 12c, and the channel layer 12b of the region 21IS using the resist mask 53 (and the hard mask 51 and the insulating film 13 that are interposed below the resist mask 53) as the mask 50. The element separation structure 160, which is a separation groove, is formed. For etching to form the device separation structure 160, for example, dry etching such as inductively coupled plasma reactive ion etching is used. The device separation structure 160 may be formed by ion implantation into the epi layer 12 instead of etching the epi layer 12.

See FIG. 4 (c). The resist mask 53 and the hard mask 51 are removed. Further, for example, the object to be treated 100 is washed with a mixed aqueous solution (hydrochloric acid excess water) of hydrochloric acid (HCl) and hydrogen peroxide (H ₂ O ₂ ). For example, the cathode pad 30 can be removed by washing with hydrogen peroxide.

As described above, dislocations are distributed at a predetermined density on the upper surface of the epi layer 12. Since the lifetime of holes is short in dislocations, PEC etching is unlikely to occur. Therefore, on the bottom of the gate recess 110G and the ohmic recess 110SD formed by the PEC etching, a convex portion is likely to be formed as an undissolved portion of the PEC etching at the position corresponding to the dislocation.

According to the findings obtained by the inventor of the present application, it is also possible to etch the convex portion, that is, to improve the flatness of the bottoms of the gate recess 110G and the ohmic recess 110SD, for example, by washing with hydrochloric acid hydrogen peroxide. As described above, in the present embodiment, the cleaning treatment performed after the formation of the element separation structure 160 also serves as a removal treatment of the cathode pad 30 and a flattening treatment of the bottoms of the gate recess 110G and the ohmic recess 110SD.

Such cleaning treatment includes hydrochloric acid (HCl) aqueous solution, mixed aqueous solution (Piranha solution) of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ), and tetramethylammonium hydroxide. (TMAH) aqueous solution, hydrogen fluoride aqueous solution (fluoric acid), potassium hydroxide (KOH) aqueous solution and the like may be used.

See FIG. 5 (a). The source electrode 151 and the drain electrode 153 are formed by lift-off using a resist mask having an opening on the ohmic recess 110SD. The source electrode 151 and the drain electrode 153 are formed of, for example, a Ti / Al / Ti / Au layer.

See FIG. 5 (b). For example, an aluminum oxide film is deposited on the entire upper surface of the object to be treated 100. The insulating film 170 is formed by removing the portions of the aluminum oxide film arranged on the upper surfaces of the source electrode 151 and the drain electrode 153 by photolithography and etching. For example, a buffered hydrofluoric acid aqueous solution is used for etching the silicon oxide film.

See FIG. 5 (c). The gate electrode 152 is formed by lift-off using a resist mask having an opening on the gate recess 110G. The gate electrode 152 is formed of, for example, a Ni / Au layer. The gate electrode 152 is formed on the gate recess 110G via an insulating film 170 which is a gate insulating film. As described above, HEMT150 is manufactured.

FIG. 6A is a schematic plan view corresponding to FIG. 2B, and shows an example of a planar arrangement of the cathode pad 30. As shown in FIGS. 2 (b) and 6 (a), the cathode pad 30 is provided outside the element region 180 of the HEMT 150 (in plan view) on the laminate 10.

FIG. 6B is a schematic plan view corresponding to FIG. 3C, and shows a planar arrangement example of the gate recess 110G and the ohmic recess 110SD.

In this embodiment, the cathode pad 30 is provided outside the element region 180. By using the cathode pad 30 provided in this way, it is possible to form the ohmic recess 110SD by PEC etching. Further, by providing the cathode pad 30 outside the element region 180, the degree of freedom in the shape, arrangement, etc. of the cathode pad 30 is increased. It should be noted that such a cathode pad 30 can also be used for forming the gate recess 110G by PEC etching.

In this example, more specifically, the cathode pad 30 is arranged between the HEMT elements adjacent to each other in the gate length direction (paper surface left / right direction). For example, as shown in FIG. 6B, a cathode pad 32 has a drain recess 111D of the first HEMT element on the left side of the paper surface and a second HEMT element (right side of the paper surface) adjacent to the first HEMT element. It is arranged between the source recess 112S and the HEMT element).

As a result, for example, the cathode pad 30 can be provided at uniform positions from the drain recess 111D of the first HEMT element and the source recess 112S of the second HEMT element, so that the PEC etching conditions for forming both recesses can be provided. It becomes easy to increase the uniformity.

Further, in this example, the cathode pad 30 has a shape extending in the gate width direction (paper surface vertical direction), that is, a shape extending in a direction parallel to the length direction of the Ohmic Recess 110SD.

This facilitates, for example, increasing the uniformity of PEC etching conditions in the length direction of the ohmic recess 110SD.

In this embodiment, an embodiment in which an ohmic recess 110SD is formed after forming a gate recess 110G is exemplified. By forming the gate recess 110G, the cap layer 12d of the portion of the gate recess 110G is removed, and the 2DE below the gate recess 110G is reduced.

Due to this, it becomes difficult for the source recess 110S and the drain recess 110D of the same HEMT element to conduct with the same cathode pad 30. For example, as shown in FIG. 6B, the cathode pad 31 arranged on the source recess 111S side of the first HEMT element and the drain recess 111D arranged on the opposite side of the gate recess 111G from the cathode pad 31 , It becomes difficult to conduct.

However, the drain recess 111D of the first HEMT element can easily conduct with the cathode pad 32 arranged on the same side as the drain recess 111D with respect to the gate recess 111G. Similarly, the source recess 112S of the second HEMT element can easily conduct with the cathode pad 32 arranged on the same side as the source recess 112S with respect to the gate recess 112G.

As described above, in this example, the cathode pads 30 arranged between the HEMT elements adjacent to each other in the gate length direction are shared in the PEC etching for forming the ohmic recess 110SD of these HEMT elements, thereby forming the ohmic recess 110SD. Can be done well. Thereby, for example, the uniformity of the PEC etching conditions in the HEMT elements adjacent to each other in the gate length direction can be enhanced, or the ohmic recess 110SD can be easily formed after the gate recess 110G is formed.

FIG. 7A is a schematic plan view corresponding to FIG. 4B, and shows an example of a planar arrangement of the element separation structure 160. The element separation structure 160 defines an element region 180 that functions as a HEMT element. In a plan view, the internal region of the closed edge (the HEMT element side, that is, the inner edge shown by the thick broken line) surrounding the HEMT element of the element separation structure 160 is the element region 180.

In this embodiment, an embodiment in which the element separation structure 160 is formed with the cathode pad 30 provided is exemplified. The cathode pad 30 functions as at least a part of the mask 50 (when performing dry etching, ion implantation, etc.) when forming the element separation structure 160. Therefore, in this example, the element separation structure 160 is formed so as not to overlap with the arrangement region of the cathode pad 30 (in a plan view).

In the embodiment in which the element separation structure 160 is formed with the cathode pad 30 provided, dry etching for forming the element separation structure 160 with a mask (resist mask 53) covering the cathode pad 30 so as not to be exposed is formed. (See FIG. 4 (b)). As a result, it is possible to suppress etching of the cathode pad 30 by the dry etching, and it is possible to suppress unnecessary contamination caused by the material (for example, a metal such as Ti) constituting the cathode pad 30.

In the element separation structure 160, the 2DEG is divided, and the conduction by the cap layer 12d is also lost. Therefore, after the element separation structure 160 is formed, the ohmic recess 110SD (or gate recess 110G) arranged in the element region 180 is subjected to PEC by using the cathode pad 30 provided outside the element region 180. It cannot be formed by etching.

Therefore, in the present embodiment, the ohmic recess 110SD (and the gate recess 110G) is formed by PEC etching using the cathode pad 30 provided outside the device region 180, and then the device separation structure 160 is formed.

FIG. 7B is a schematic plan view corresponding to FIG. 5C, and shows a planar arrangement example of the source electrode 151, the gate electrode 152, and the drain electrode 153. The width of the gate electrode 152 defines the gate length _Lg of the HEMT element. The source electrode 151, the gate electrode 152, and the drain electrode 153 are arranged in the gate length direction. The direction orthogonal to the gate length direction is the gate width direction, and the gate width _Wg is defined by the length of the element region 180 in the gate width direction. The source electrodes 151, the gate electrodes 152, and the drain electrodes 153 may be electrically connected to each other between adjacent HEMT elements, if necessary.

In the present embodiment, the etching for forming the gate recess 110G and the etching for forming the ohmic recess 110SD are both performed by PEC etching. Hereinafter, the PEC etching for forming the gate recess 110G is also referred to as a PEC etching for the gate recess 110G, and the PEC etching for forming the ohmic recess 110SD is also referred to as a PEC etching for the ohmic recess 110SD.

The light source 220 may be switched (the wavelength characteristic of the light 221 may be changed) for each of the PEC etching of the gate recess 110G and the PEC etching of the ohmic recess 110SD, but from the viewpoint of simplifying the structure of the PEC etching apparatus 200. It is preferable to use the same light source 220 (light 221 having the same wavelength characteristics) for both PEC etchings.

In the example where the cap layer 12d is made of GaN and the barrier layer 12c is made of AlGaN, the barrier layer 12c (AlGaN) is also PEC-etched with short-wavelength light 221 capable of PEC-etching. Can be done.

The PEC etching of the gate recess 110G can be stopped by self-stop as described above. On the other hand, when the PEC etching of the ohmic recess 110SD is performed using such a short wavelength light 221, the etching proceeds deeply until it stops by itself unless any time limit is set. Therefore, the PEC etching of the ohmic recess 110SD is stopped by time control. Thereby, both PEC etchings can be performed using the same light source 220.

In the PEC etching of the ohmic recess 110SD, the cap layer 12d can be PEC-etched, but the barrier layer 12c cannot be PEC-etched. Etching may be stopped.

The time required for PEC etching of the gate recess 110G is longer than the time required for PEC etching of the ohmic recess 110SD, which is shallower than the PEC etching of the gate recess 110G. In the present embodiment, the PEC etching of the gate recess 110G, which takes a long time, is performed using the hard mask 51. The PEC etching of the gate recess 110G may be performed using a resist mask (only), but in order to further improve the resistance of the mask to the etching solution 201 and further improve the patterning accuracy, the PEC etching of the gate recess 110G is hard. It is preferable to use the mask 51.

In this embodiment, the PEC etching of the gate recess 110G is followed by the PEC etching of the ohmic recess 110SD. During PEC etching of the gate recess 110G, the cap layer 12d of the region 21SD corresponding to the ohmic recess 110SD is in a state of being protected by the hard mask 51 (see FIG. 3A). Thereby, unnecessary etching in the cap layer 12d of the region 21SD can be further suppressed as compared with the state where the cap layer 12d is protected by the resist mask (only).

The PEC etching of the ohmic recess 110SD is performed using the hard mask 51 having an opening formed on the region 21SD and the resist mask 52, and the gate recess 110G is preferably filled with the resist mask 52, preferably at least. The resist mask 52 is applied with the side surface of the gate recess 110G made of Group III nitride covered (see FIG. 3C). By protecting the side surface of the gate recess 110G with the resist mask 52, it is possible to suppress unnecessary side etching of the side surface in the PEC etching of the ohmic recess 110SD. In this example, when the PEC etching of the ohmic recess 110SD is performed, the gate recess 110G is protected only by the resist mask, but since the PEC etching of the ohmic recess 110SD is short, the problem is unlikely to occur.

Either the PEC etching of the gate recess 110G or the PEC etching of the ohmic recess 110SD may be performed first, if necessary. Further, the PEC etching of the gate recess 110G and the PEC etching of the ohmic recess 110SD may be performed using a resist mask or a hard mask, respectively, as necessary.

The HEMT 150 according to the present embodiment has the following features, for example, reflecting the above-mentioned manufacturing method.

In the manufacturing method according to the present embodiment, the source recess 110S and the drain recess 110D (and further the gate recess 110G) can be formed by PEC etching. Therefore, the plasma damage introduced when the source recess and the drain recess are formed by the conventional dry etching is not introduced into the HEMT 150 of the present embodiment. That is, in the HEMT 150 of the present embodiment, at least for the group III nitride layer located directly under the source electrode and the drain electrode (more preferably, also for the group III nitride layer located directly under the gate electrode), the plasma No damage has been introduced.

In the manufacturing method according to the present embodiment, the source recess 110S and the drain recess 110D (and further the gate recess 110G) are formed by PEC etching using a cathode pad 30 provided outside the element separation structure 160. In the arrangement region of the cathode pad 30, the cap layer 12d is removed to form the recess 110CP.

Reflecting this, as shown in FIG. 5C, the insulating film 170 of the HEMT 150 is outside the element separation structure 160 with respect to the region where the source electrode 151, the gate electrode 152, and the drain electrode 153 are arranged. In, a portion 171 provided on the barrier layer 12c via the cap layer 12d and a portion 172 provided directly above the barrier layer 12c may be provided.

<First modification>
A first modification will be described. FIG. 9A is a schematic plan view showing a planar arrangement example of the element separation structure 160 according to the first modification. As shown in FIG. 9A, at least one end of the etched region 21SD on which the ohmic recess 110SD is formed in the gate width direction and the gate length direction and the element separation structure 160 are (in a plan view). The element separation structure 160 may be formed so as to have an overlap. That is, the element separation structure 160 may be formed so as to have an overlap (in a plan view) with a part of the etched region 21SD on which the ohmic recess 110SD is formed.

This makes it possible to more ensure that the ohmic recess 110SD is arranged without a gap to the end of the element region 180 in the gate width direction or the gate length direction. That is, the region 21SD to be etched may be defined so as to be slightly wider than the effective recess portion that is arranged in the element region 180 and actually functions as the ohmic recess 110SD.

<Second modification>
A second modification will be described. FIG. 9B is a schematic plan view showing a planar arrangement example of the element separation structure 160 according to the second modification. In the above-described embodiment, an embodiment in which the element separation structure 160 is formed so as not to overlap with the arrangement region of the cathode pad 30 (in a plan view) has been exemplified. As shown in FIG. 9B, the element separation structure 160 may be formed so as to have an overlap (in a plan view) with the arrangement region of the cathode pad 30.

10 (a) and 10 (b) are schematic cross-sectional views illustrating the manufacturing process of HEMT150 according to the second modification. In this modification, as shown in FIG. 10A, the cathode pad 30 is removed after the ohmic recess 110SD (and the gate recess 110G) is formed and before the element separation structure 160 is formed. The cathode pad 30 is removed, for example, by hydrochloric acid hydrogen peroxide.

After the cathode pad 30 is removed, the element separation structure 160 is formed in a region overlapping the arrangement region of the cathode pad 30 as shown in FIG. 10 (b). Since the cathode pad 30 is removed, the element separation structure 160 can be formed also in the arrangement region of the cathode pad 30.

In the structure in which the arrangement region of the cathode pad 30 and the element separation structure 160 do not overlap each other as in the above-described embodiment, that is, the arrangement region of the cathode pad 30 is provided outside the element separation structure 160, the cathode is used. The arrangement area of the pad 30 cannot be effectively used as, for example, the element separation structure 160. In this modification, by forming the element separation structure 160 after removing the cathode pad 30, the arrangement region of the cathode pad 30 can be effectively utilized.

<Third modification example>
A third modification will be described. FIG. 11 is a schematic plan view showing a planar arrangement example of the cathode pad 30 according to the third modification. In the above-described embodiment, the embodiment in which the cathode pad 30 is arranged between the HEMT elements adjacent to each other in the gate length direction is exemplified.

As shown in FIG. 11, the cathode pad 30 may be arranged between the HEMT elements adjacent to each other in the gate width direction. The cathode pad 30 has, for example, a shape extending in the gate length direction, that is, a shape extending in a direction orthogonal to the length direction of the ohmic recess 110SD. The cathode pad 30 of this modification can improve the uniformity of PEC etching conditions in the HEMT element adjacent to each other in the gate width direction, for example.

<Fourth modification>
A fourth modification will be described. FIG. 12 is a schematic cross-sectional view illustrating HEMT 150 according to the fourth modification. In the above embodiment (see FIG. 1), an embodiment in which the gate recess 110G is formed by PEC etching together with the ohmic recess 110SD is exemplified. The fourth modification illustrates an embodiment in which the gate recess 110G is not formed.

As shown in FIG. 12, the HEMT 150 according to this modification has an ohmic recess 110SD but no gate recess. The gate electrode 152 is formed on, for example, the cap layer 12d. Further, in this modification, the gate insulating film does not intervene below the gate electrode 152.

For example, even in the HEMT 150 in such an embodiment, the ohmic recess 110SD can be formed by PEC etching using the cathode pad 30 provided outside the element region 180 in the same manner as in the above-described embodiment.

<Other embodiments>
The embodiments and modifications of the present invention have been specifically described above. However, the present invention is not limited to the above-described embodiments and modifications, and various changes, improvements, combinations, and the like can be made without departing from the gist thereof. The above-described embodiment and various modifications, as well as other embodiments described below, may be used in combination as appropriate.

In the above-described embodiment, dry etching is exemplified as the etching for forming the element separation structure 160 which is the element separation groove, but PEC etching which is wet etching may be used as the etching.

The inventor of the present application has found that it is preferable to make the etching solution 201 acidic in order to self-stop PEC etching by reducing 2DE, that is, to stop PEC etching at a depth in the middle of the barrier layer 12c. It has gained. In other words, by making the etching solution 201 alkaline, the mechanism is unknown, but it was found that (high-speed) PEC etching that penetrates the barrier layer 12c and reaches the depth in the middle of the channel layer 12b is likely to occur. ing.

Based on these findings, it is preferable to use an acidic etching solution 201 (from the start of PEC etching) for the PEC etching forming the gate recess 110G and the ohmic recess 110SD. Further, by using the alkaline etching solution 201, it is possible to form the element separation structure 160, which is an element separation groove, by PEC etching.

FIG. 13 is a schematic cross-sectional view illustrating a step of forming the element separation structure 160 by PEC etching (corresponding to FIG. 4 (b) described above). In the example shown in FIG. 13, a mask 53a that exposes at least a part of the cathode pad 30 is formed in order to perform PEC etching. In this step, the element separation structure 160 is formed by performing PEC etching at a depth at which the channel layer 12b is exposed on the bottom using an alkaline etching solution 201. On the other hand, in the steps shown in FIGS. 3 (a) and 3 (c), PEC etching is performed at a depth at which the barrier layer 12c is exposed on the bottom, preferably using an acidic etching solution 201. The gate recess 110G and the ohmic recess 110SD are formed.

In the above-described embodiment, the cathode pad 30 provided outside the element region 180 has been described, but a part of the cathode pad 30 may have an overlap (in a plan view) with the element region 180.

FIG. 14 is a schematic plan view illustrating an embodiment in which a part of the cathode pad 30 overlaps with the element region 180. In the example shown in FIG. 14, two HEMT elements are arranged side by side in the gate length direction, and these two HEMT elements are formed in a common element region 180. That is, these two HEMT elements are surrounded by a common element separation structure 160.

In this example, the cathode pad 33 arranged on the left side of the HEMT element on the left side of the paper is provided outside the element region 180, and the cathode pad 34 arranged between the two HEMT elements is the element region 180. It has an overlap.

In the above-described embodiment, an embodiment in which a conductive member different from the laminate (nitride semiconductor crystal substrate) 10 is used as the cathode pad (conductive member functioning as a cathode for electrodeless PEC etching) 30 has been exemplified. As described below, a conductive member (conductive region) made of Group III nitride as a part of the laminate 10 may be used as the cathode pad 30.

It should be noted that the cathode pad 30 comprehensively includes a mode in which a conductive member separate from the laminated body 10 is used and a mode in which a conductive member composed of a Group III nitride is used as a part of the laminated body 10. In the case of capturing, the expression of the cathode portion 30 may be used instead of the expression of the cathode pad 30.

15 (a) and 15 (b) are schematic cross-sectional views illustrating an embodiment in which the cathode portion 30 is formed by ion-implanting an n-type impurity into the epi layer 12.

FIG. 15 (a) corresponds to FIG. 2 (b) of the above-described embodiment, and illustrates a step of forming the cathode portion 30. In FIG. 15A, the region to be the cathode portion 30 is shown by a thick line. In this example, the region where the cathode portion 30 is arranged in a plan view is referred to as a region 21CP.

The cathode portion 30 is formed by ion-implanting an n-type impurity such as Si into the epi layer 12 in a state where a mask having an opening is formed in the region 21CP. For example, ion implantation is performed so that the cathode portion 30 having an n-type impurity concentration of 1 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less and a depth (thickness) of 100 nm or more and 200 nm or less is formed. conduct. For example, in the region 21CP, the cathode portion 30 is formed by ion-implanting an n-type impurity into the total thickness of the cap layer 12d, the total thickness of the barrier layer 12c, and the upper part of the channel layer 12b.

The cathode portion 30 is formed to a depth reaching the upper part of the channel layer 12b, so that it reaches 2DEG, and the etched region 21 etched by PEC etching and the cathode portion 30 are the cap layer 12d and It is electrically connected via at least one of the 2DEGs. In this example, since the cathode portion 30 is directly connected to the 2DEG, electrons can be emitted from the cathode portion 30 more effectively.

In this example, the etched region 21 and the cathode portion 30 are both composed of Group III nitride. Further, when the light 221 is irradiated to the etched region 21, the light 221 is also irradiated to the cathode portion 30. However, the group III nitride constituting the cathode portion 30 has an n-type impurity concentration higher than that of the region 21 to be etched (preferably, for example, 10 times or more higher). As a result, in the cathode portion 30 having a higher electron concentration than the region 21 to be etched, the anodizing reaction can be suppressed by consuming the photoexcited holes in a short time, so that the cathode portion 30 can be PEC-etched. It is suppressed and can function as a cathode for PEC etching. This also applies to the embodiment in which the cathode portion 30 is formed by regrowth described later.

The region 21 to be etched by PEC etching is a cap layer 12d or a barrier layer 12c, and can be said to be a portion of the epi layer 12 above the lower surface of the barrier layer 12c. Typically, n-type impurities are not added to the barrier layer 12c, and n-type impurities are added to the cap layer 12d. The cathode portion 30 has an n-type impurity concentration higher than that of the cap layer 12d, that is, an n-type impurity concentration higher than the highest n-type impurity concentration of the region 21 to be etched (preferably 10 times or more higher). N-type impurities are added so as to be.

The step after forming the cathode portion 30 is the same as that of the above-described embodiment. When the PEC etching of the region 21 to be etched is performed, the cathode portion 30 is brought into contact with the etching solution 201, so that the cathode portion 30 functions as a cathode for PEC etching. The cathode portion 30 may not be removed (the group III nitride layer constituting the cathode portion 30) and may remain after the formation of the element separation region 160. The cathode portion 30 may be removed by etching at the time of forming the element separation region 160 which is an element separation groove. The cathode portion 30 may be implanted with ions for element separation when the element separation region 160 is formed by ion implantation.

FIG. 15B corresponds to FIG. 1A of the above-described embodiment and schematically shows HEMT150 of this example. The epi layer 12 of the HEMT 150 of this example may have a cathode portion 30 having a depth reaching the upper part of the channel layer 12b outside the element region 180 in a plan view, reflecting the above-mentioned manufacturing method. The cathode portion 30 has an n-type impurity concentration higher than the (highest) n-type impurity concentration in the portion above the lower surface of the barrier layer 12c in the epi layer 12 in the element region 180 in a plan view.

FIG. 16 is a schematic cross-sectional view illustrating an embodiment in which a cathode portion 30 is formed by regrowth of a Group III nitride layer to which an n-type impurity is added. This example may be regarded as an embodiment in which, for example, the cathode portion 30 made of Ti in the above-described embodiment is made of a Group III nitride having a high n-type impurity concentration instead of Ti.

A method of forming the cathode portion 30 of this example will be described with reference to FIG. 2 (b). In a state where a mask having an opening is formed in the region 21CP, the cathode portion 30 is formed by regrowth of GaN to which an n-type impurity such as Si is added above the barrier layer 12c. As a method of regrowth, sputtering, pulsed laser deposition (PLD), organometallic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like may be appropriately used. For example, a cathode portion 30 having an n-type impurity concentration of 1 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less and a thickness of about 50 nm is grown. The cathode portion 30 may be provided on the cap layer 12d in the same manner as described in the embodiment in which the cathode portion 30 is made of Ti.

The process after forming the cathode pad 30 is the same as that of the above-described embodiment. Also in this example, the cathode portion 30 may not be removed and may remain after the formation of the element separation region 160.

FIG. 16 corresponds to FIG. 1 (a) of the above-described embodiment and schematically shows HEMT 150 of this example. The epi layer 12 of the HEMT 150 of this example is a cathode portion 30 grown above the barrier layer 12c (or above the cap layer 12d) outside the element region 180 in a plan view, reflecting the above-mentioned manufacturing method. May have. The cathode portion 30 has an n-type impurity concentration higher than the n-type impurity concentration in the portion above the lower surface of the barrier layer 12c in the epi layer 12 in the element region 180 in a plan view.

<Preferable Aspect of the Present Invention>
Hereinafter, preferred embodiments of the present invention will be described.

(Appendix 1)
A method for manufacturing a nitride-based high electron mobility transistor.
A step of providing a conductive member on a nitride semiconductor crystal substrate outside the element region of the high electron mobility transistor in a plan view.
On the nitride semiconductor crystal substrate, a source recess etched region in which a source recess, which is a recess in which the source electrode of the high electron mobility transistor is arranged, is formed, and a drain electrode of the high electron mobility transistor are arranged. A step of forming a mask having an opening (and an opening that exposes the conductive member) in at least one of the drain recess etched regions in which the drain recess, which is a recess, is formed.
The nitride semiconductor crystal substrate is irradiated with light in a state where the nitride semiconductor crystal substrate on which the conductive member is provided and the mask is formed is in contact with an etching solution containing an oxidizing agent that receives electrons. In the step of performing photoelectrochemical etching to form at least one of the source recess and the drain recess.
The step of forming the element separation structure (defining the element region) of the high electron mobility transistor (after the photoelectrochemical etching) and
A method for manufacturing a nitride-based high electron mobility transistor having the above.

(Appendix 2)
The method for manufacturing a nitride-based high electron mobility transistor according to Appendix 1, wherein each step is performed in the order described in Appendix 1.

(Appendix 3)
The nitride semiconductor crystal substrate is composed of a channel layer on which at least two-dimensional electron gas is formed, a barrier layer formed on the channel layer, and a group III nitride constituting the barrier layer. Also includes a cap layer, which is composed of a group III nitride having a small bandgap and is formed on the barrier layer.
The method for manufacturing a nitride-based high electron mobility transistor according to Appendix 1 or 2, wherein the cap layer (only) is removed in the photoelectrochemical etching.

(Appendix 4)
The nitride according to Appendix 3, wherein the conductive member is electrically connected to the source recess etched region or the drain recess etched region via at least one of the cap layer and the two-dimensional electron gas. A method for manufacturing a system high electron mobility transistor.

(Appendix 5)
In the step of forming the element separation structure, the element separation structure is formed so as to have an overlap in a plan view with at least one part of the source recess etched region and the drain recess etched region. The method for manufacturing a nitride-based high electron mobility transistor according to any one of the above.

(Appendix 6)
In the step of forming the element separation structure, the element separation structure is formed by any one of ion injection, dry etching, and photoelectrochemical etching, according to any one of Supplementary note 1 to 5. A method for manufacturing a nitride-based high electron mobility transistor.

(Appendix 7)
The nitride according to any one of Supplementary note 1 to 6, wherein in the step of forming the element separation structure, the element separation structure is formed so as not to overlap with the arrangement region of the conductive member in a plan view. A method for manufacturing a system high electron mobility transistor.

(Appendix 8)
In the step of forming the device separation structure, the nitride-based high electron mobility transistor according to Appendix 7, wherein the device separation structure is formed by ion implantation using the conductive member as at least a part of a mask. Production method.

(Appendix 9)
In the step of forming the element separation structure, the element separation structure is formed by dry etching at least in a state where a mask covering the source recess or the drain recess and the conductive member so as not to be exposed is formed. The method for manufacturing a nitride-based high electron mobility transistor according to Appendix 7.

(Appendix 10)
The nitride system according to Appendix 7, wherein in the step of forming the element separation structure, the element separation structure is formed by photoelectrochemical etching in a state where a mask that exposes at least a part of the conductive member is formed. A method for manufacturing a high electron mobility transistor.

(Appendix 11)
Photoelectrochemical etching in the step of forming at least one of the source recess and the drain recess is performed using an acidic etching solution.
The method for manufacturing a nitride-based high electron mobility transistor according to Appendix 10, wherein the photoelectrochemical etching in the step of forming the device separation structure is performed using an alkaline etching solution.
Preferably, the photoelectrochemical etching in the step of forming the gate recess in Appendix 17 is performed using an acidic etching solution.

(Appendix 12)
The nitride system according to any one of Supplementary note 1 to 6, wherein in the step of forming the element separation structure, the element separation structure is formed so as to have an overlap with the arrangement region of the conductive member in a plan view. A method for manufacturing a high electron mobility transistor.

(Appendix 13)
The method for manufacturing a nitride-based high electron mobility transistor according to Appendix 12, wherein the step of forming the element separation structure is performed after removing the conductive member.

(Appendix 14)
In the method for manufacturing a nitride-based high electron mobility transistor, a plurality of high electron mobility transistors arranged in at least one direction in the gate length direction and the gate width direction are manufactured on the nitride semiconductor crystal substrate.
The conductive member is arranged at least one of the high electron mobility transistor elements adjacent to each other in the gate length direction and the high electron mobility transistor elements adjacent to each other in the gate width direction. The method for manufacturing a nitride-based high electron mobility transistor according to any one of Supplementary note 1 to 13.
A plurality of conductive members may be arranged side by side in at least one direction in the gate length direction and the gate width direction.

(Appendix 15)
The nitride-based high electron mobility according to Appendix 14, wherein the conductive member arranged between the high electron mobility transistor elements adjacent to each other in the gate length direction has a shape extending in the gate width direction. Transistor manufacturing method.

(Appendix 16)
The nitride-based high electron according to Appendix 14 or 15, wherein the conductive member arranged between the high electron mobility transistor elements adjacent to each other in the gate width direction has a shape extending in the gate length direction. Manufacturing method of mobility transistor.

(Appendix 17)
On the nitride semiconductor crystal substrate, there is an opening in the gate recess etched region where a gate recess, which is a recess in which the gate electrode of the high electron mobility transistor is arranged, is formed (and an opening for exposing the conductive member). ) The process of forming other masks and
The nitride semiconductor crystal substrate is irradiated with light in a state where the nitride semiconductor crystal substrate on which the conductive member is provided and the other mask is formed is in contact with an etching solution containing an oxidizing agent that receives electrons. By doing so, another photoelectrochemical etching is performed to form the gate recess.
The step of forming the element separation structure (after the photoelectrochemical etching and the other photoelectrochemical etching) and
The method for manufacturing a nitride-based high electron mobility transistor according to any one of Supplementary note 1 to 16, further comprising.

(Appendix 18)
The nitride semiconductor crystal substrate is composed of a channel layer on which at least two-dimensional electron gas is formed, a barrier layer formed on the channel layer, and a group III nitride constituting the barrier layer. Also includes a cap layer, which is composed of a group III nitride having a small bandgap and is formed on the barrier layer.
In the photoelectrochemical etching, the cap layer (only) is removed.
The method for manufacturing a nitride-based high electron mobility transistor according to Appendix 17, wherein the cap layer and a part of the barrier layer are removed in the other photoelectrochemical etching.

(Appendix 19)
In the photoelectrochemical etching and the other photoelectrochemical etching, light irradiation is performed using the same light source (light having the same wavelength characteristics).
The method for manufacturing a nitride-based high electron mobility transistor according to Supplementary note 17 or 18, wherein the photoelectrochemical etching is stopped by time control, and the other photoelectrochemical etching is stopped by self-stop.

(Appendix 20)
The other photoelectrochemical etching is performed before the photoelectrochemical etching.
The nitride-based high electron mobility according to any one of Supplementary note 17 to 19, wherein in the other photoelectrochemical etching, the other mask is formed by using a hard mask made of an inorganic material or a metallic material. Manufacturing method of degree transistor.

(Appendix 21)
The method for manufacturing a nitride-based high electron mobility transistor according to any one of Supplementary note 17 to 20, wherein the mask is formed by using a resist mask in the photoelectrochemical etching.

(Appendix 22)
A method for manufacturing a nitride-based high electron mobility transistor.
A step of providing a conductive member on a nitride semiconductor crystal substrate outside the element region of the high electron mobility transistor in a plan view.
On the nitride semiconductor crystal substrate, there is an opening in the gate recess etched region where a gate recess, which is a recess in which the gate electrode of the high electron mobility transistor is arranged, is formed (and an opening for exposing the conductive member). ) The process of forming the mask and
The nitride semiconductor crystal substrate is irradiated with light in a state where the nitride semiconductor crystal substrate on which the conductive member is provided and the mask is formed is in contact with an etching solution containing an oxidizing agent that receives electrons. In the process of forming the gate recess by performing photoelectrochemical etching,
The step of forming the element separation structure (defining the element region) of the high electron mobility transistor (after the photoelectrochemical etching) and
A method for manufacturing a nitride-based high electron mobility transistor having the above.

(Appendix 23)
Nitride-based high electron mobility transistor
A Group III nitride layer having at least a channel layer, a barrier layer arranged on the channel layer, and a cap layer arranged on the barrier layer.
Source electrode, gate electrode, and drain electrode,
Element separation structure and
Equipped with
At least, plasma damage is not introduced into the Group III nitride layer located directly below the source electrode and the drain electrode (preferably further directly below the gate electrode).
Nitride-based high electron mobility transistor.

(Appendix 24)
Nitride-based high electron mobility transistor
A group III nitride layer having a channel layer, a barrier layer arranged on the channel layer, and a cap layer arranged on the barrier layer.
Source electrode, gate electrode, and drain electrode,
Element separation structure and
With an insulating film
Equipped with
The insulating film is
It covers the element separation structure and is provided extending to the outside of the element separation structure with respect to the region where the source electrode, the gate electrode, and the drain electrode are arranged, and outside the element separation structure. It has a portion provided on the barrier layer via the cap layer and a portion provided directly above the barrier layer.
Nitride-based high electron mobility transistor.

(Appendix 25)
A region to be etched made of a group III nitride and a cathode portion made of a group III nitride having a higher n-type impurity concentration than the region to be etched and electrically connected to the region to be etched. The process of preparing the object to be prepared and
The region to be etched (and the cathode portion) is etched by irradiating the region to be etched (and the cathode portion) with light in a state where the region to be etched and the cathode portion are in contact with an etching solution containing an oxidizing agent that receives electrons. Process and
A method for manufacturing a structure having a structure.

(Appendix 26)
Nitride-based high electron mobility transistor
A Group III nitride layer having at least a channel layer and a barrier layer disposed on the channel layer (preferably further having a cap layer disposed on the barrier layer).
Source electrode, gate electrode, and drain electrode,
Element separation structure and
Equipped with
The group III nitride layer has a cathode portion having a depth reaching the upper part of the channel layer outside the element region of the high electron mobility transistor in a plan view.
The cathode portion has an n-type impurity concentration higher than the n-type impurity concentration in the portion above the lower surface of the barrier layer in the group III nitride layer in the element region of the high electron mobility transistor in a plan view. Have,
Nitride-based high electron mobility transistor.

(Appendix 27)
Nitride-based high electron mobility transistor
A Group III nitride layer having at least a channel layer and a barrier layer disposed on the channel layer (preferably further having a cap layer disposed on the barrier layer).
Source electrode, gate electrode, and drain electrode,
Element separation structure and
Equipped with
The group III nitride layer has a cathode portion grown above the barrier layer outside the element region of the high electron mobility transistor in a plan view.
The cathode portion has an n-type impurity concentration higher than the n-type impurity concentration in the portion above the lower surface of the barrier layer in the group III nitride layer in the element region of the high electron mobility transistor in a plan view. Have,
Nitride-based high electron mobility transistor.

10 ... Laminate, 11 ... Substrate, 12 ... Group III nitride layer (epi layer), 12a ... Nucleation layer, 12b ... Channel layer, 12c ... Barrier layer, 12d ... Cap layer, 13 ... Insulating film, 21 ... Covered Etching region, 30 ... cathode pad, 50 ... mask, 51 ... hard mask, 52 ... resist mask, 53 ... resist mask, 100 ... object to be processed, 110S ... source recess, 110D ... drain recess, 110SD ... ohmic recess, 110G ... gate recess , 150 ... Nitride-based high electron mobility transistor, 151 ... Source electrode, 152 ... Gate electrode, 153 ... Drain electrode, 160 ... Element separation structure, 170 ... Insulating film, 171 ... (Insulating film 170) portion, 172 ... Part (of insulating film 170), 180 ... element region, 200 ... PEC etching device, 201 ... etching solution, 210 ... container, 220 ... light source, 221 ... light

Claims (24)

A method for manufacturing a nitride-based high electron mobility transistor.
A step of providing a conductive member on a nitride semiconductor crystal substrate outside the element region of the high electron mobility transistor in a plan view.
On the nitride semiconductor crystal substrate, a source recess etched region in which a source recess, which is a recess in which the source electrode of the high electron mobility transistor is arranged, is formed, and a drain electrode of the high electron mobility transistor are arranged. A step of forming a mask having an opening in at least one of the drain recess etched regions in which the drain recess, which is the recess, is formed, and
The nitride semiconductor crystal substrate is irradiated with light in a state where the nitride semiconductor crystal substrate on which the conductive member is provided and the mask is formed is in contact with an etching solution containing an oxidizing agent that receives electrons. In the step of performing photoelectrochemical etching to form at least one of the source recess and the drain recess.
The step of forming the element separation structure of the high electron mobility transistor and
A method for manufacturing a nitride-based high electron mobility transistor having the above. The method for manufacturing a nitride-based high electron mobility transistor according to claim 1, wherein each step is performed in the order according to claim 1. The nitride semiconductor crystal substrate is composed of a channel layer on which at least two-dimensional electron gas is formed, a barrier layer formed on the channel layer, and a group III nitride constituting the barrier layer. Also includes a cap layer, which is composed of a group III nitride having a small bandgap and is formed on the barrier layer.
The method for manufacturing a nitride-based high electron mobility transistor according to claim 1 or 2, wherein the cap layer is removed in the photoelectrochemical etching. The nitride according to claim 3, wherein the conductive member is electrically connected to the source recess etched region or the drain recess etched region via at least one of the cap layer and the two-dimensional electron gas. A method for manufacturing a physical high electron mobility transistor. In the step of forming the element separation structure, the element separation structure is formed so as to have an overlap in a plan view with at least one part of the source recess etched region and the drain recess etched region. 4. The method for manufacturing a nitride-based high electron mobility transistor according to any one of 4. The step of forming the element separation structure according to any one of claims 1 to 5, wherein the element separation structure is formed by any one of ion injection, dry etching, and photoelectrochemical etching. The method for manufacturing a nitride-based high electron mobility transistor according to the above method. The nitride according to any one of claims 1 to 6, wherein in the step of forming the element separation structure, the element separation structure is formed so as not to overlap with the arrangement region of the conductive member in a plan view. Manufacturing method of physical high electron mobility transistor. The nitride-based high electron mobility transistor according to claim 7, wherein in the step of forming the device separation structure, the device separation structure is formed by ion implantation using the conductive member as at least a part of a mask. Manufacturing method. In the step of forming the element separation structure, the element separation structure is formed by dry etching at least in a state where a mask covering the source recess or the drain recess and the conductive member so as not to be exposed is formed. The method for manufacturing a nitride-based high electron mobility transistor according to claim 7. The nitride according to claim 7, wherein in the step of forming the element separation structure, the element separation structure is formed by photoelectrochemical etching in a state where a mask that exposes at least a part of the conductive member is formed. A method for manufacturing a system high electron mobility transistor. Photoelectrochemical etching in the step of forming at least one of the source recess and the drain recess is performed using an acidic etching solution.
The method for manufacturing a nitride-based high electron mobility transistor according to claim 10, wherein the photoelectrochemical etching in the step of forming the device separation structure is performed using an alkaline etching solution. The nitride according to any one of claims 1 to 6, wherein in the step of forming the element separation structure, the element separation structure is formed so as to have an overlap with the arrangement region of the conductive member in a plan view. A method for manufacturing a system high electron mobility transistor. The method for manufacturing a nitride-based high electron mobility transistor according to claim 12, wherein the step of forming the element separation structure is performed after removing the conductive member. In the method for manufacturing a nitride-based high electron mobility transistor, a plurality of high electron mobility transistors arranged in at least one direction in the gate length direction and the gate width direction are manufactured on the nitride semiconductor crystal substrate.
The conductive member is arranged at least one of the high electron mobility transistor elements adjacent to each other in the gate length direction and the high electron mobility transistor elements adjacent to each other in the gate width direction. The method for manufacturing a nitride-based high electron mobility transistor according to any one of claims 1 to 13. The nitride-based high electron mobility according to claim 14, wherein the conductive member arranged between the high electron mobility transistor elements adjacent to each other in the gate length direction has a shape extending in the gate width direction. Manufacturing method of degree transistor. The nitride-based height according to claim 14 or 15, wherein the conductive member arranged between the high electron mobility transistor elements adjacent to each other in the gate width direction has a shape extending in the gate length direction. Manufacturing method of electron mobility transistor. A step of forming another mask having an opening in the gate recess etched region where a gate recess, which is a recess in which the gate electrode of the high electron mobility transistor is arranged, is formed on the nitride semiconductor crystal substrate.
The nitride semiconductor crystal substrate is irradiated with light in a state where the nitride semiconductor crystal substrate on which the conductive member is provided and the other mask is formed is in contact with an etching solution containing an oxidizing agent that receives electrons. By doing so, another photoelectrochemical etching is performed to form the gate recess.
The process of forming the element separation structure and
The method for manufacturing a nitride-based high electron mobility transistor according to any one of claims 1 to 16, further comprising. The nitride semiconductor crystal substrate is composed of a channel layer on which at least two-dimensional electron gas is formed, a barrier layer formed on the channel layer, and a group III nitride constituting the barrier layer. Also includes a cap layer, which is composed of a group III nitride having a small bandgap and is formed on the barrier layer.
In the photoelectrochemical etching, the cap layer is removed.
The method for manufacturing a nitride-based high electron mobility transistor according to claim 17, wherein in the other photoelectrochemical etching, the cap layer and a part of the barrier layer are removed. In the photoelectrochemical etching and the other photoelectrochemical etching, light irradiation is performed using the same light source.
The method for manufacturing a nitride-based high electron mobility transistor according to claim 17 or 18, wherein the photoelectrochemical etching is stopped by time control, and the other photoelectrochemical etching is stopped by self-stop. The other photoelectrochemical etchings are performed prior to the photoelectrochemical etchings.
The nitride-based high electron according to any one of claims 17 to 19, wherein in the other photoelectrochemical etching, the other mask is formed by using a hard mask made of an inorganic material or a metallic material. Manufacturing method of mobility transistor. The method for manufacturing a nitride-based high electron mobility transistor according to any one of claims 17 to 20, wherein in the photoelectrochemical etching, the mask is formed by using a resist mask. A method for manufacturing a nitride-based high electron mobility transistor.
A step of providing a conductive member on a nitride semiconductor crystal substrate outside the element region of the high electron mobility transistor in a plan view.
A step of forming a mask having an opening in the gate recess etched region where a gate recess, which is a recess in which the gate electrode of the high electron mobility transistor is arranged, is formed on the nitride semiconductor crystal substrate.
The nitride semiconductor crystal substrate is irradiated with light in a state where the nitride semiconductor crystal substrate on which the conductive member is provided and the mask is formed is in contact with an etching solution containing an oxidizing agent that receives electrons. In the process of forming the gate recess by performing photoelectrochemical etching,
The step of forming the element separation structure of the high electron mobility transistor and
A method for manufacturing a nitride-based high electron mobility transistor having the above. Nitride-based high electron mobility transistor
A Group III nitride layer having at least a channel layer, a barrier layer arranged on the channel layer, and a cap layer arranged on the barrier layer.
Source electrode, gate electrode, and drain electrode,
Element separation structure and
Equipped with
At least, plasma damage is not introduced into the Group III nitride layer located directly below the source electrode and the drain electrode.
Nitride-based high electron mobility transistor. Nitride-based high electron mobility transistor
A group III nitride layer having a channel layer, a barrier layer arranged on the channel layer, and a cap layer arranged on the barrier layer.
Source electrode, gate electrode, and drain electrode,
Element separation structure and
With an insulating film
Equipped with
The insulating film is
It covers the element separation structure and is provided extending to the outside of the element separation structure with respect to the region where the source electrode, the gate electrode, and the drain electrode are arranged, and outside the element separation structure. It has a portion provided on the barrier layer via the cap layer and a portion provided directly above the barrier layer.
Nitride-based high electron mobility transistor.

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