JP2022014805A - Power converter - Google Patents

Abstract

To provide a power converter with high efficiency at a low cost.SOLUTION: A power converter (3) has a power conversion unit (30) that includes multiple parallel switching elements (S1) are connected in series (S1-S8) in which at least one switching element (S1a-S1b) are connected in parallel. In each of the switching elements (S1a-S1b), diodes (D1a-D1b) are formed or connected in anti-parallel. In the multiple parallel switching elements (S1-S8), a parallel switching element (S1) with several parallels is fewer than that of other parallel switching elements is included.SELECTED DRAWING: Figure 16

Description

The present disclosure relates to a power conversion device that converts a voltage of electric power.

A DC / DC converter and an inverter are used in a power conditioner connected to a storage battery, a solar cell, a fuel cell, or the like. Highly efficient power conversion and compact design are desired for DC / DC converters and inverters. As a DC / DC converter to realize this, a flying capacitor circuit (four switching elements connected in series and a flying capacitor connected in parallel to the second switching element and the third switching element is configured after the reactor. A multi-level power conversion device has been proposed in which the voltage at the connection point between the reactor and the flying capacitor circuit is divided into three levels (see, for example, Patent Document 1).

The multi-level power converter can reduce the voltage applied to each switching element, thereby reducing the switching loss and realizing highly efficient power conversion. In the multi-level power conversion device using the flying capacitor circuit, the voltage applied to each switching element constituting the flying capacitor circuit can be reduced to 1/2 times the DC bus voltage by increasing the level to three. ..

As a result, it is possible to configure a switching element with a relatively low withstand voltage (for example, 300V) without using a switching element with a relatively high withstand voltage (for example, 600V) used in the full bridge portion of the inverter. Become. A switching element with a low withstand voltage is cheaper than a switching element with a high withstand voltage, and has less conduction loss and switching loss during power conversion, which contributes to further improvement in efficiency.

Japanese Unexamined Patent Publication No. 2013-192383

In a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) generally used as an inexpensive switching element, a parasitic diode is used as a freewheeling diode. Parasitic diodes have a large recovery loss and are a factor in increasing switching loss.

The present disclosure has been made in view of these circumstances, and an object thereof is to provide a low-cost and highly efficient power conversion device.

In order to solve the above problems, the power conversion device of one aspect of the present disclosure is a power conversion device in which a parallel switching element in which at least one switching element is connected in parallel has a power conversion unit in which a plurality of parallel switching elements are connected in series. Therefore, diodes are formed or connected in antiparallel to each switching element, and among the plurality of parallel switching elements, a parallel switching element having a smaller number of parallels than other parallel switching elements is included.

According to the present disclosure, it is possible to realize a low-cost and highly efficient power conversion device.

It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Embodiment 1. FIG. It is a figure which summarized the switching pattern of the 1st switching element-8th switching element of the DC / DC conversion apparatus which concerns on Embodiment 1. FIG. 3 (a)-(d) is a circuit diagram showing a current path of each switching pattern at the time of boosting operation. 4 (a)-(d) is a circuit diagram showing a current path of each switching pattern at the time of step-down operation. It is a timing chart which shows an example of the switching pattern of the 1st switching element-the 8th switching element when the step-up ratio is 2 times or more. It is a timing chart which shows an example of the switching pattern of the 1st switching element-8th switching element when the step-up ratio is less than 2 times. 7 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is twice or more (No. 1). 8 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is twice or more (No. 2). 9 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is 2 times or more (No. 1). 10 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is twice or more (No. 2). 11 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is less than 2 times (No. 1). 12 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is less than 2 times (No. 2). 13 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is less than 2 times (No. 1). 14 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is less than 2 times (No. 2). It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on the comparative example of Embodiment 1. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 1 of Embodiment 1. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 2 of Embodiment 1. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on the modification of Example 1 of Embodiment 1. FIG. 19 (a)-(c) are diagrams showing a configuration example of a flying capacitor circuit. It is a figure which shows the flying capacitor circuit of N (N is a natural number) stage. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 1 of Embodiment 2. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 2 of Embodiment 2. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 1 of Embodiment 3. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 2 of Embodiment 3. FIG.

FIG. 1 is a diagram for explaining the configuration of the DC / DC converter 3 according to the first embodiment. The DC / DC converter 3 according to the first embodiment is a bidirectional buck-boost DC / DC converter. The DC / DC converter 3 can boost the DC power supplied from the second DC power supply 2 and supply it to the first DC power supply 1. Further, the DC / DC converter 3 can step down the DC power supplied from the first DC power supply 1 and supply it to the second DC power supply 2. In the present specification, it is assumed that the second DC power supply 2 is a power supply having a lower voltage than the first DC power supply 1.

The second DC power supply 2 corresponds to, for example, a storage battery, an electric double layer capacitor, or the like. The first DC power supply 1 corresponds to, for example, a DC bus to which a bidirectional DC / AC inverter is connected. The AC side of the bidirectional DC / AC inverter is connected to the commercial power system and the AC load in the application of the power storage system. For electric vehicle applications, it is connected to a motor (with regenerative function). In the application of the power storage system, a DC / DC converter for a solar cell or a DC / DC converter for another storage battery may be further connected to the DC bus.

The DC / DC converter 3 includes a DC / DC converter 30 and a control unit 40. The DC / DC converter 30 includes an input capacitor C5, a reactor L1, a first flying capacitor circuit 31, a second flying capacitor circuit 32, a first dividing capacitor C3, a second dividing capacitor C4, and an output capacitor C6.

The input capacitor C5 is connected in parallel with the second DC power supply 2. The output capacitor C6 is connected in parallel with the first DC power supply 1. The first partitioning capacitor C3 and the second partitioning capacitor C4 are connected in series between the positive side bus and the negative side bus of the first DC power supply 1. The first dividing capacitor C3 and the second dividing capacitor C4 act as a snubber capacitor for dividing the voltage E of the first DC power supply 1 into 1/2 and suppressing the surge voltage generated in the DC / DC converter 30. Has the effect of. In the present specification, the configuration before the input capacitor C5 is referred to as a low-voltage DC unit, and the configuration after the first division capacitor C3 and the second division capacitor C4 is referred to as a high-voltage DC unit.

The first flying capacitor circuit 31 and the second flying capacitor circuit 32 are connected in series with the high-voltage side DC unit in parallel. The reactor L1 is connected between the positive terminal of the low voltage side DC portion and the midpoint of the first flying capacitor circuit 31. The negative terminal of the low voltage side DC portion and the midpoint of the second flying capacitor circuit 32 are connected. The connection point between the first flying capacitor circuit 31 and the second flying capacitor circuit 32 is connected to the intermediate potential point M (the voltage dividing point of the first divided capacitor C3 and the second divided capacitor C4) of the DC portion on the high voltage side. To.

The first division capacitor C3 and the second division capacitor C4 can be omitted. In that case, the connection point between the first flying capacitor circuit 31 and the second flying capacitor circuit 32 is not necessarily in the middle of the high-voltage side DC portion. It does not need to be connected to the potential point M.

The first flying capacitor circuit 31 includes a first switching element S1, a second switching element S2, a third switching element S3, a fourth switching element S4, and a first flying capacitor C1. The first switching element S1, the second switching element S2, the third switching element S3, and the fourth switching element S4 are connected in series and are connected between the positive bus of the high voltage direct current section and the intermediate potential point M. The first flying capacitor C1 is connected between the connection point between the first switching element S1 and the second switching element S2 and the connection point between the third switching element S3 and the fourth switching element S4, and is connected to the first switching element. S1-Charged and discharged by the fourth switching element S4.

At the midpoint of the first flying capacitor circuit 31, the voltage E [V] of the first DC power supply 1 applied to the upper terminal of the first switching element S1 and the voltage E [V] applied to the lower terminal of the fourth switching element S4. Potentials in the range between 1 / 2E [V] are generated. The first flying capacitor C1 is initially charged (precharged) so as to have a voltage of 1 / 4E [V], and charging / discharging is repeated centering on the voltage of 1 / 4E [V]. Therefore, at the midpoint of the first flying capacitor circuit 31, three levels of potentials of E [V], 3/4 E [V], and 1 / 2E [V] are generally generated.

The second flying capacitor circuit 32 includes a fifth switching element S5, a sixth switching element S6, a seventh switching element S7, an eighth switching element S8, and a second flying capacitor C2. The fifth switching element S5, the sixth switching element S6, the seventh switching element S7, and the eighth switching element S8 are connected in series and are connected between the intermediate potential point M of the high voltage direct current section and the negative bus. The second flying capacitor C2 is connected between the connection point between the fifth switching element S5 and the sixth switching element S6 and the connection point between the seventh switching element S7 and the eighth switching element S8, and is connected to the fifth switching element. S5-charged and discharged by the eighth switching element S8.

At the midpoint of the second flying capacitor circuit 32, 1 / 2E [V] applied to the upper terminal of the fifth switching element S5 and 0 [V] applied to the lower terminal of the eighth switching element S8. Potentials in the range between are generated. The second flying capacitor C2 is initially charged (precharged) so as to have a voltage of 1 / 4E [V], and charging / discharging is repeated centering on the voltage of 1 / 4E [V]. Therefore, at the midpoint of the second flying capacitor circuit 32, three levels of potentials of 1 / 2E [V], 1 / 4E [V], and 0 [V] are generally generated.

A first diode D1 to an eighth diode D8 are formed / connected in antiparallel to each of the first switching element S1 to the eighth switching element S8.

For the first switching element S1-8th switching element S8, it is preferable to use a switching element having a withstand voltage lower than the voltage of the first DC power supply 1 and the second DC power supply 2. Hereinafter, in the present embodiment, an example in which an N-channel MOSFET with a withstand voltage of 150 V is used for the first switching element S1 to the eighth switching element S8 is assumed. In the N-channel MOSFET, a parasitic diode is formed from the source to the drain.

Although not shown in FIG. 1, a voltage sensor that detects the voltage of the low voltage DC portion, a current sensor that detects the current flowing through the reactor L1, a voltage sensor that detects the voltage of the first flying capacitor C1, and the second flying capacitor C2. A voltage sensor for detecting the voltage and a voltage sensor for detecting the voltage of the high-voltage DC unit are provided, and the measured values of each are output to the control unit 40.

The control unit 40 can control the first flying capacitor circuit 31 and the second flying capacitor circuit 32 to transmit DC power from the low-voltage side DC unit to the high-voltage side DC unit by boosting operation. Further, DC power can be transmitted from the high-voltage side DC section to the low-voltage side DC section by step-down operation. More specifically, the control unit 40 supplies a drive signal (PWM (Pulse Width Modulation) signal) to the gate terminal of the first switching element S1-8th switching element S8, so that the first switching element S1-8th. By controlling the switching element S8 on / off, power can be transmitted in both directions by a step-up operation or a step-down operation.

The configuration of the control unit 40 can be realized by the collaboration of hardware resources and software resources, or only by hardware resources. Analog devices, microcomputers, DSPs, ROMs, RAMs, FPGAs, ASICs, and other LSIs can be used as hardware resources. Programs such as firmware can be used as software resources.

FIG. 2 is a diagram summarizing the switching patterns of the first switching element S1 to the eighth switching element S8 of the DC / DC converter 3 according to the first embodiment. In the switching pattern shown in FIG. 2, the set of the first switching element S1 and the eighth switching element S8 and the set of the fourth switching element S4 and the fifth switching element S5 have a complementary relationship. Further, the set of the second switching element S2 and the seventh switching element S7 and the set of the third switching element S3 and the sixth switching element S6 have a complementary relationship.

The control unit 40 executes a step-up operation or a step-down operation using four modes.
In the mode a, the control unit 40 turns on the second switching element S2, the fourth switching element S4, the fifth switching element S5, and the seventh switching element S7, and the first switching element S1, the third switching element S3, and the sixth. The switching element S6 and the eighth switching element S8 are controlled to be in the off state. In the mode a, the voltage between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32 (that is, the input / output voltage _VL on the low voltage side of the flying capacitor portion) is 1 / 2E.

In the mode b, the control unit 40 turns on the first switching element S1, the third switching element S3, the sixth switching element S6, and the eighth switching element S8, and the second switching element S2, the fourth switching element S4, and the fifth. The switching element S5 and the seventh switching element S7 are controlled to be in the off state. In mode b, the input / output voltage _VL on the low voltage side of the flying capacitor section is 1 / 2E.

In the mode c, the control unit 40 turns on the first switching element S1, the second switching element S2, the seventh switching element S7, and the eighth switching element S8, and the third switching element S3, the fourth switching element S4, and the fifth. The switching element S5 and the sixth switching element S6 are controlled to be in the off state. In mode c, the input / output voltage _VL on the low voltage side of the flying capacitor section is E.

In the mode d, the control unit 40 turns on the third switching element S3, the fourth switching element S4, the fifth switching element S5, and the sixth switching element S6, and the first switching element S1, the second switching element S2, and the seventh. The switching element S7 and the eighth switching element S8 are controlled to be in the off state. In mode d, the input / output voltage _VL on the low voltage side of the flying capacitor section becomes 0.

3 (a)-(d) is a circuit diagram showing a current path of each switching pattern at the time of boosting operation. 4 (a)-(d) is a circuit diagram showing a current path of each switching pattern at the time of step-down operation. The MOSFET is drawn with a simple switch symbol to simplify the drawing.

FIG. 3A shows the current path of mode a during boosting operation, FIG. 3B shows the current path of mode b during boosting operation, and FIG. 3C shows the current of mode c during boosting operation. The path is shown, and FIG. 3D shows the current path of the mode d at the time of boosting operation. Similarly, FIG. 4A shows the current path of the mode a during the step-down operation, FIG. 4B shows the current path of the mode b during the step-down operation, and FIG. 4C shows the mode during the step-down operation. The current path of c is shown, and FIG. 4 (d) shows the current path of the mode d at the time of step-down operation.

The direction of the current is opposite between the step-up operation and the step-down operation. In the mode a, the first flying capacitor C1 and the second flying capacitor C2 are charged during the boosting operation as shown in FIG. 3A, but the first flying capacitor C1 is charged during the stepping down operation as shown in FIG. 4A. The flying capacitor C1 and the second flying capacitor C2 are discharged. In the mode b, the first flying capacitor C1 and the second flying capacitor C2 are discharged during the boosting operation as shown in FIG. 3B, but the first flying capacitor C2 is discharged during the stepping down operation as shown in FIG. 4B. The flying capacitor C1 and the second flying capacitor C2 are in the charging operation.

When the control unit 40 transmits power from the low voltage DC unit to the high voltage DC unit by boosting operation, the control unit 40 sets a current command value in the positive direction, and the measured value of the current flowing through the reactor L1 maintains the current command value in the positive direction. The duty ratio (on time) of the first switching element S1 to the eighth switching element S8 is controlled so as to be performed. On the contrary, when the control unit 40 transmits power from the high voltage DC unit to the low voltage DC unit by step-down operation, the control unit 40 sets a current command value in the negative direction, and the measured value of the current flowing through the reactor L1 is the current command value in the negative direction. The duty ratio (on time) of the first switching element S1 to the eighth switching element S8 is controlled so as to maintain the value.

Further, when the ratio of the voltage of the low voltage side DC unit to the voltage of the high voltage side DC unit is smaller than the set value, the control unit 40 transmits power using modes a, mode b, and mode c. Further, when the ratio is larger than the set value, the control unit 40 transmits electric power using modes a, b, and d. Further, when the ratio matches the set value, the control unit 40 uses modes a and b to transmit electric power.

The voltage of the low-voltage side DC section and the voltage of the high-voltage side DC section are measured by voltage sensors, respectively. The above set value is set according to the ratio of the total voltage 1 / 2E of the voltage of the first flying capacitor C1 and the voltage of the second flying capacitor C2 to the voltage E of the first DC power supply 1. In this embodiment, the above setting value is set to 2.

The control unit 40 generates a duty ratio so that the current command value and the measured value of the current flowing through the reactor L1 match, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are 1 / 4E, respectively. .. Specifically, the control unit 40 increases the duty ratio as the measured value of the current flowing through the reactor L1 is smaller than the current command value, and decreases the duty ratio as the measured value is larger.

FIG. 5 is a timing chart showing an example of a switching pattern of the first switching element S1 to the eighth switching element S8 when the step-up ratio is twice or more. FIG. 6 is a timing chart showing an example of the switching pattern of the first switching element S1 to the eighth switching element S8 when the boost ratio is less than twice. The control examples shown in FIGS. 5 and 6 show a control example using the double carrier drive system. In the double carrier drive system, two carrier signals (triangular wave in FIGS. 5 and 6) that are 180 ° out of phase are used. The duty ratio duty is a threshold value to be compared with the two carrier signals. When the boost ratio is 2 times or more, the duty ratio duty takes a value in the range of 0.5 to 1.0, and when the boost ratio is less than 2 times, the duty ratio duty is in the range of 0.0 to 0.5. Take a value.

Based on the comparison result of the carrier signal of the thick wire and the duty ratio duty, the first gate signal supplied to the first switching element S1 and the eighth switching element S8 and the fourth gate supplied to the fourth switching element S4 and the fifth switching element S5. Generate a signal. Specifically, in the region where the carrier signal of the thick line is higher than the duty ratio duty, the first gate signal is turned on and the fourth gate signal is turned off. In the region where the carrier signal of the thick line is lower than the duty ratio duty, the first gate signal is turned off and the fourth gate signal is turned on. The first gate signal and the fourth gate signal are in a complementary relationship. A dead time period is set in which the first gate signal and the fourth gate signal are turned off at the same time when the first gate signal and the fourth gate signal are switched on / off.

Based on the comparison result of the carrier signal of the thin wire and the duty ratio duty, the second gate signal supplied to the second switching element S2 and the seventh switching element S7 and the third gate supplied to the third switching element S3 and the sixth switching element S6. Generate a signal. Specifically, in the region where the carrier signal of the thin wire is higher than the duty ratio duty, the second gate signal is turned on and the third gate signal is turned off. In the region where the carrier signal of the thin wire is lower than the duty ratio duty, the second gate signal is turned off and the third gate signal is turned on. The second gate signal and the third gate signal are in a complementary relationship. A dead time period is set in which the second gate signal and the third gate signal are turned off at the same time when the second gate signal and the third gate signal are switched on / off.

When the boost ratio is twice or more, the control unit 40 alternately switches between the mode a and the mode b, and inserts the mode d while switching between the two. That is, the control unit 40 switches modes in the order of mode a → mode d → mode b → mode d → mode a → mode d → mode b → mode d .... While the duty ratio duty does not change, the periods of mode a and mode b become equal, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are maintained at 1 / 4E, respectively. When the boost ratio is twice or more, as the duty ratio duty increases, the period of mode d with respect to the period of mode a and mode b becomes longer, and the amount of energy transmitted increases.

When the boost ratio is less than twice, the control unit 40 alternately switches between the mode a and the mode b, and inserts the mode c while switching between the two. That is, the control unit 40 switches modes in the order of mode a → mode c → mode b → mode c → mode a → mode c → mode b → mode c .... While the duty ratio duty does not change, the periods of mode a and mode b become equal, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are maintained at 1 / 4E, respectively. When the boost ratio is less than twice, as the duty ratio duty increases, the period of mode c with respect to the period of mode a and mode b becomes shorter, and the amount of energy transmitted increases.

If the boost ratio is ideally maintained at 2 times and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are ideally maintained at 1 / 4E, the duty ratio duty is maintained at 0.5.

When the total voltage of the voltage of the first flying capacitor C1 and the voltage of the second flying capacitor C2 is less than 1 / 2E, the control unit 40 increases the time of the charging mode among the modes a and b. Bring the total voltage closer to 1 / 2E. On the contrary, when the total voltage of the voltage of the first flying capacitor C1 and the voltage of the second flying capacitor C2 exceeds 1 / 2E, the control unit 40 increases the time of the discharging mode among the modes a and b. The total voltage is brought closer to 1 / 2E.

The control unit 40 alternately switches between the mode c and the mode d without using the first flying capacitor C1 and the second flying capacitor C2, so that the DC / DC conversion unit 30 can operate the normal step-up chopper. It is also possible to make it. In this case, the operation mode is not switched depending on the boost ratio.

Hereinafter, detailed switching patterns including the dead time will be described for each of the step-up ratio of 2 times or more, the step-down ratio of 2 times or more, the step-up ratio of less than 2 times, and the step-down ratio of less than 2 times.

7 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is twice or more (No. 1). 8 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is twice or more (No. 2). When the boost ratio is twice or more, the control unit 40 has mode d (FIG. 7 (a)) → dead time 1 (FIG. 7 (b)) → mode a (FIG. 7 (c)) → dead time 1 (FIG. 7 (c)). 7 (d)) → mode d (FIG. 8 (a)) → dead time 2 (FIG. 8 (b)) → mode b (FIG. 8 (c)) → dead time 2 (FIG. 8 (d)) in one cycle As, the switching pattern is switched.

In the dead time 1 when the boost ratio is twice or more, the control unit 40 simultaneously turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7. Since the second switching element S2 and the seventh switching element S7 are in the off state in the dead time 1, the second switching element S2 and the seventh switching element S7 are not synchronous rectification, but the parasitic diode of the second switching element S2 and the seventh. The current returns through the parasitic diode of the switching element S7.

When the dead time 1 (FIG. 7 (d)) is switched to the mode d (FIG. 8 (a)), the third switching element S3 and the sixth switching element S6 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the second switching element S2 and the parasitic diode of the seventh switching element S7 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the third switching element S3 and the sixth switching element S6, so that the current flowing at the time of turn-on of the third switching element S3 and the sixth switching element S6 increases, and the third switching element S3 and the sixth switching element S6 The switching loss of the switching element S6 increases.

In the dead time 2 when the boost ratio is twice or more, the control unit 40 turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8 at the same time. Since the first switching element S1 and the eighth switching element S8 are in the off state in the dead time 2, the first switching element S1 and the eighth switching element S8 are not synchronous rectification, but the parasitic diode of the first switching element S1 and the eighth. The current returns through the parasitic diode of the switching element S8.

When switching from the dead time 2 (FIG. 8 (d)) to the mode d (FIG. 7 (a)), the fourth switching element S4 and the fifth switching element S5 turn on. As a result, a reverse bias voltage is applied to the parasitic diode of the first switching element S1 and the parasitic diode of the eighth switching element S8 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the fourth switching element S4 and the fifth switching element S5, so that the current flowing at the time of turn-on of the fourth switching element S4 and the fifth switching element S5 increases, and the fourth switching element S4 and the fifth switching element S5 and the fifth switching element S5. The switching loss of the switching element S5 increases.

9 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is 2 times or more (No. 1). 10 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is twice or more (No. 2). When the step-down ratio is twice or more, the control unit 40 has mode d (FIG. 9 (a)) → dead time 1 (FIG. 9 (b)) → mode a (FIG. 9 (c)) → dead time 1 (FIG. 9 (c)). 9 (d)) → mode d (FIG. 10 (a)) → dead time 2 (FIG. 10 (b)) → mode b (FIG. 10 (c)) → dead time 2 (FIG. 10 (d)) in one cycle. As the switching pattern is switched.

In the dead time 1 when the step-down ratio is twice or more, the control unit 40 simultaneously turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7. Since the third switching element S3 and the sixth switching element S6 are in the off state in the dead time 1, the third switching element S3 and the sixth switching element S6 are not synchronous rectification, but the parasitic diode of the third switching element S3 and the sixth. The current returns through the parasitic diode of the switching element S6.

When the dead time 1 (FIG. 9 (b)) is switched to the mode a (FIG. 9 (c)), the second switching element S2 and the seventh switching element S7 turn on. As a result, a reverse bias voltage is applied to the parasitic diode of the third switching element S3 and the parasitic diode of the sixth switching element S6 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the second switching element S2 and the seventh switching element S7, so that the current flowing at the time of turn-on of the second switching element S2 and the seventh switching element S7 increases, and the second switching element S2 and the seventh switching element S7. The switching loss of the switching element S7 increases.

In the dead time 2 when the step-down ratio is twice or more, the control unit 40 turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8 at the same time. Since the 4th switching element S4 and the 5th switching element S5 are in the off state in the dead time 2, the 4th switching element S4 and the 5th switching element S5 are not synchronous rectification, but the parasitic diode of the 4th switching element S4 and the 5th. The current returns through the parasitic diode of the switching element S5.

When the dead time 2 (FIG. 10 (b)) is switched to the mode b (FIG. 10 (c)), the first switching element S1 and the eighth switching element S8 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the fourth switching element S4 and the parasitic diode of the fifth switching element S5 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the first switching element S1 and the eighth switching element S8, so that the current flowing at the time of turn-on of the first switching element S1 and the eighth switching element S8 increases, and the first switching element S1 and the eighth The switching loss of the switching element S8 increases.

11 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is less than 2 times (No. 1). 12 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is less than 2 times (No. 2). When the boost ratio is less than twice, the control unit 40 has mode c (FIG. 11 (a)) → dead time 1 (FIG. 11 (b)) → mode a (FIG. 11 (c)) → dead time 1 (FIG. 11 (c)). 11 (d)) → mode c (FIG. 12 (a)) → dead time 2 (FIG. 12 (b)) → mode b (FIG. 12 (c)) → dead time 2 (FIG. 12 (d)) in one cycle. As, the switching pattern is switched.

In the dead time 1 when the boost ratio is less than twice, the control unit 40 turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8 at the same time. Since the first switching element S1 and the eighth switching element S8 are in the off state in the dead time 1, the first switching element S1 and the eighth switching element S8 are not synchronous rectification, but the parasitic diode of the first switching element S1 and the eighth. The current returns through the parasitic diode of the switching element S8.

When the dead time 1 (FIG. 11 (b)) is switched to the mode a (FIG. 11 (c)), the fourth switching element S4 and the fifth switching element S5 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the first switching element S1 and the parasitic diode of the eighth switching element S8 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the fourth switching element S4 and the fifth switching element S5, so that the current flowing at the time of turn-on of the fourth switching element S4 and the fifth switching element S5 increases, and the fourth switching element S4 and the fifth switching element S5 and the fifth switching element S5. The switching loss of the switching element S5 increases.

In the dead time 2 when the boost ratio is less than twice, the control unit 40 turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7 at the same time. Since the second switching element S2 and the seventh switching element S7 are in the off state in the dead time 2, the second switching element S2 and the seventh switching element S7 are not synchronous rectification, but the parasitic diode of the second switching element S2 and the seventh. The current returns through the parasitic diode of the switching element S7.

When switching from the dead time 2 (FIG. 12 (b)) to the mode b (FIG. 12 (c)), the third switching element S3 and the sixth switching element S6 turn on. As a result, a reverse bias voltage is applied to the parasitic diode of the second switching element S2 and the parasitic diode of the seventh switching element S7 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the third switching element S3 and the sixth switching element S6, so that the current flowing at the time of turn-on of the third switching element S3 and the sixth switching element S6 increases, and the third switching element S3 and the sixth switching element S6 The switching loss of the switching element S6 increases.

13 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is less than 2 times (No. 1). 14 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is less than 2 times (No. 2). When the step-down ratio is less than twice, the control unit 40 has mode c (FIG. 13 (a)) → dead time 1 (FIG. 13 (b)) → mode a (FIG. 13 (c)) → dead time 1 (FIG. 13 (c)). 13 (d)) → mode c (FIG. 14 (a)) → dead time 2 (FIG. 14 (b)) → mode b (FIG. 14 (c)) → dead time 2 (FIG. 14 (d)) in one cycle. As the switching pattern is switched.

In the dead time 1 when the step-down ratio is less than twice, the control unit 40 simultaneously turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8. Since the 4th switching element S4 and the 5th switching element S5 are in the off state in the dead time 1, the 4th switching element S4 and the 5th switching element S5 are not synchronous rectification, but the parasitic diode of the 4th switching element S4 and the 5th. The current returns through the parasitic diode of the switching element S5.

When the dead time 1 (FIG. 13 (d)) is switched to the mode c (FIG. 14 (a)), the first switching element S1 and the eighth switching element S8 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the fourth switching element S4 and the parasitic diode of the fifth switching element S5 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the first switching element S1 and the eighth switching element S8, so that the current flowing at the time of turn-on of the first switching element S1 and the eighth switching element S8 increases, and the first switching element S1 and the eighth The switching loss of the switching element S8 increases.

In the dead time 2 when the step-down ratio is less than twice, the control unit 40 turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7 at the same time. Since the third switching element S3 and the sixth switching element S6 are in the off state in the dead time 2, the third switching element S3 and the sixth switching element S6 are not synchronous rectification, but the parasitic diode of the third switching element S3 and the sixth. The current returns through the parasitic diode of the switching element S6.

When switching from the dead time 2 (FIG. 14 (d)) to the mode c (FIG. 13 (a)), the second switching element S2 and the seventh switching element S7 turn on. As a result, a reverse bias voltage is applied to the parasitic diode of the third switching element S3 and the parasitic diode of the sixth switching element S6 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the second switching element S2 and the seventh switching element S7, so that the current flowing at the time of turn-on of the second switching element S2 and the seventh switching element S7 increases, and the second switching element S2 and the seventh switching element S7. The switching loss of the switching element S7 increases.

The recovery loss due to the parasitic diode of the MOSFET used as the switching element is not negligible, and reducing the recovery loss due to the parasitic diode greatly contributes to improving the efficiency of the DC / DC converter 3 as a whole. Hereinafter, a circuit configuration in which recovery loss countermeasures are taken will be described.

FIG. 15 is a diagram for explaining the configuration of the DC / DC converter 3 according to the comparative example of the first embodiment. In the DC / DC converter 3 according to the comparative example of the first embodiment shown in FIG. 15, the first switching element S1 to the eighth switching element S8 of the DC / DC converter 3 shown in FIG. 1 are configured in three parallel positions. Has been done. As a result, the current flowing through one switching element can be reduced to 1/3. Therefore, the permissible current of one switching element can be reduced, and the size of each switching element can be reduced. In addition, the amount of heat generated from one switching element can be reduced. The number of parallels is not limited to 3. By increasing the number of parallels, the amount of heat generated from one switching element can be further reduced. Hereinafter, a plurality of first parallel switching elements S1a-S1c connected in parallel are collectively referred to as first parallel switching elements S1a-S1c. The same applies to the second switching element S2-eighth switching element S8.

FIG. 16 is a diagram for explaining the configuration of the DC / DC converter 3 according to the first embodiment of the first embodiment. In the DC / DC converter 3 according to the first embodiment shown in FIG. 16, the first parallel switching element S1a-S1b, the second parallel switching element S2a-S2b, the seventh parallel switching element S7a-S7b, and the eighth parallel switching element S8a -The number of parallels of S8b is designed to be smaller than the number of parallels of the third parallel switching element S3a-S3c, the fourth parallel switching element S4a-S4c, the fifth parallel switching element S5a-S5c, and the sixth parallel switching element S6a-S6c. There is. Specifically, the number of parallels in the former group is designed to be 2, and the number of parallels in the latter group is designed to 3. The number of parallels in the former group may be 1. Further, the number of parallels in the latter group may be 4 or more.

FIG. 17 is a diagram for explaining the configuration of the DC / DC converter 3 according to the second embodiment of the first embodiment. In the DC / DC converter 3 according to the second embodiment of the first embodiment shown in FIG. 17, the third parallel switching element S3a-S3b, the fourth parallel switching element S4a-S4b, the fifth parallel switching element S5a-S5b, and the third parallel switching element S5a-S5b. 6 The number of parallel switching elements S6a-S6b is the number of parallels of the first parallel switching element S1a-S1c, the second parallel switching element S2a-S2c, the seventh parallel switching element S7a-S7c, and the eighth parallel switching element S8a-S8c. Less designed. Specifically, the number of parallels in the former group is designed to be 3, and the number of parallels in the latter group is designed to 2. The number of parallels in the former group may be 4 or more. Further, the number of parallels in the latter group may be 1.

In the first embodiment of the first embodiment shown in FIG. 16, the recovery loss during the boosting operation can be reduced. During the boosting operation, a recovery current is generated in the first switching element S1, the second switching element S2, the seventh switching element S7, and the eighth switching element S8 (FIGS. 7 (a), 8 (a), and 11 (c)). , See FIG. 12 (c). On the other hand, in the first embodiment of the first embodiment, the first parallel switching element S1a-S1b, the second parallel switching element S2a-S2b, the seventh parallel switching element S7a-S7b, and the eighth parallel switching element S8a-S8b. By reducing the number of parallels, the amount of recovery current can be reduced.

In the second embodiment of the first embodiment shown in FIG. 17, the recovery loss during the step-down operation can be reduced. During the step-down operation, a recovery current is generated in the third switching element S3, the fourth switching element S4, the fifth switching element S5, and the sixth switching element S6 (FIGS. 9 (c), 10 (c), and 13 (a). , See FIG. 14 (a). On the other hand, in the second embodiment of the first embodiment, the third parallel switching element S3a-S3b, the fourth parallel switching element S4a-S4b, the fifth parallel switching element S5a-S5b, and the sixth parallel switching element S6a-S6b. By reducing the number of parallels, the amount of recovery current can be reduced.

FIG. 18 is a diagram for explaining the configuration of the DC / DC converter 3 according to the modified example of the first embodiment of the first embodiment. In the DC / DC converter 3 of the first embodiment shown in FIG. 16, the reactor L1 is connected between the positive terminal of the low-voltage side DC portion and the midpoint of the first flying capacitor circuit 31. In this regard, in the modified example shown in FIG. 18, the first reactor L1 is connected between the positive terminal of the low voltage side DC portion and the midpoint of the first flying capacitor circuit 31, and the negative terminal of the low voltage side DC portion and the second terminal. The second reactor L2 is connected between the midpoints of the flying capacitor circuit 32. The first reactor L1 and the second reactor L2 may be configured by a magnetically coupled reactor having a common core. In this case, the magnetic fluxes of the first reactor L1 and the second reactor L2 can be mutually strengthened when energized.

The reactor L1 may be connected between the negative terminal of the low voltage side DC portion and the midpoint of the second flying capacitor circuit 32. As described above, the reactor L1 has a path connecting the positive terminal of the low-voltage side DC portion and the midpoint of the first flying capacitor circuit 31, and the negative terminal of the low-voltage side DC portion and the inside of the second flying capacitor circuit 32. It suffices if it is inserted in at least one of the paths connecting the points. Although not shown, also in the DC / DC converter 3 of the second embodiment of the first embodiment shown in FIG. 17, the second is between the negative terminal of the low voltage side DC portion and the midpoint of the second flying capacitor circuit 32. The reactor L2 may be connected.

19 (a)-(c) are diagrams showing a configuration example of a flying capacitor circuit. FIG. 19A shows a one-stage flying capacitor circuit. The flying capacitor circuit shown in FIG. 19A is the same as the circuit configuration described in the first embodiment.

FIG. 19B shows a two-stage flying capacitor circuit. The two-stage flying capacitor circuit includes six switching elements S12, S1, S2, S3, S4, and S42 connected in series, and two flying capacitors C11 and C12. The innermost flying capacitor C11 is connected in parallel to the two switching elements S2 and S3, and is controlled to maintain a voltage of 1 / 6E. The second flying capacitor C12 from the inside is connected in parallel to the four switching elements S1, S2, S3, and S4, and is controlled to maintain a voltage of 1 / 6E.

FIG. 19C shows a three-stage flying capacitor circuit. The three-stage flying capacitor circuit includes six switching elements S13, S12, S1, S2, S3, S4, S42, and S43 connected in series, and three flying capacitors C11, C12, and C13. The innermost flying capacitor C11 is connected in parallel to the two switching elements S2 and S3, and is controlled to maintain a voltage of 1 / 8E. The second flying capacitor C12 from the inside is connected in parallel to the four switching elements S1, S2, S3, S4 and controlled to maintain a voltage of 2 / 8E. The third flying capacitor C13 from the inside is connected in parallel to the six switching elements S12, S1, S2, S3, S4, and S42, and is controlled to maintain a voltage of 3 / 8E.

FIG. 20 shows an N (N is a natural number) stage flying capacitor circuit. In the N-stage flying capacitor circuit, N (2N + 2) switching elements S1n, ..., S13, S12, S1, S2, S3, S4, S42, S43, ..., S4n connected in series. The flying capacitors C11, C12, C13, ..., C1n of the above are provided. The innermost flying capacitor C11 is connected in parallel to the two switching elements S2 and S3, and is controlled to maintain a voltage of 1 / (2N + 2) E. The second flying capacitor C12 from the inside is connected in parallel to the four switching elements S1, S2, S3, and S4, and is controlled to maintain a voltage of 2 / (2N + 2) E. The third flying capacitor C13 from the inside is connected in parallel to the six switching elements S12, S1, S2, S3, S4, and S42, and is controlled to maintain a voltage of 3 / (2N + 2) E. The outermost flying capacitor C1n has 2N S1 (n-1), ..., S13, S12, S1, S2, S3, S4, S42, S43, ..., S4 (n-1). They are connected in parallel and controlled to maintain a voltage of N / (2N + 2) E.

In the first flying capacitor circuit 31 and the second flying capacitor circuit 32 shown in FIG. 1, the one-stage flying capacitor circuit shown in FIG. 19A is used. When a one-stage flying capacitor circuit is used, a voltage of three levels (E, 1 / 2E, 0) is generated between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. Is possible. Using the two-stage flying capacitor circuit shown in FIG. 19B, there are five levels (E, 2 / 3E,) between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. It is possible to generate a voltage of 1 / 2E, 1 / 3E, 0). Using the three-stage flying capacitor circuit shown in FIG. 19 (c), there are seven levels (E, 3/4E,) between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. It is possible to generate a voltage of 5 / 8E, 1 / 2E, 3 / 8E, 1 / 4E, 0). By using the N-stage flying capacitor circuit shown in FIG. 20, it is possible to generate a (2N + 1) level voltage between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. It becomes.

As the number of stages of the flying capacitor circuit is increased, switching elements that are inexpensive and have a low breakdown voltage can be used, but the number of switching elements used increases. Therefore, the designer may determine the optimum number of stages of the flying capacitor circuit in consideration of the total cost and the total conversion efficiency. Further, in an application in which the voltage of the DC portion on the high voltage side exceeds 1000 V or in an application in which the voltage exceeds 10,000 V, it is effective to increase the number of stages of the flying capacitor circuit in order to reduce the withstand voltage of each switching element.

In the first embodiment, regardless of the number of stages of the flying capacitor circuit, the number of parallel switching elements including the switching element to which the diode whose recovery current should be reduced is connected is set to the parallel number of other parallel switching elements. Recovery loss can be reduced by designing less than the number.

FIG. 21 is a diagram for explaining the configuration of the DC / DC converter 3 according to the first embodiment of the second embodiment. The DC / DC converter 3 according to the first embodiment of the second embodiment is a chopper type buck-boost DC / DC converter. The DC / DC conversion unit 30 according to the first embodiment of the second embodiment includes an upper switching element S1 and a lower switching element S3. The lower switching element S3 is composed of parallel switching elements S3a-S3b in which two switching elements are connected in parallel.

At the time of boosting, the control unit 40 constantly controls the upper switching element S1 to be off, and PWM controls the lower parallel switching elements S3a-S3b according to the boost ratio. The control unit 40 constantly controls the lower parallel switching elements S3a-S3b to be off at the time of step-down, and PWM-controls the upper switching element S1 according to the step-down ratio.

The larger the boost ratio at the time of boosting, the higher the duty ratio. That is, the on-time of the lower parallel switching elements S3a-S3b becomes longer.

During the period when the lower parallel switching elements S3a-S3b are off, a forward current flows through the diode D1 of the upper switching element S1. When the lower parallel switching elements S3a-S3b are turned on, a reverse bias voltage is applied to the diode D1 of the upper switching element S1 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction. As a result, the recovery current flows into the lower parallel switching elements S3a-S3b, so that the current flowing when the lower parallel switching elements S3a-S3b are turned on increases, and the switching loss of the lower parallel switching elements S3a-S3b. Will increase.

On the other hand, in the first embodiment of the second embodiment, the recovery current amount can be reduced by reducing the number of parallel elements of the upper switching element S1 from the number of parallel elements of the lower switching element S3.

The configuration of the first embodiment of the second embodiment is more effective as the step-up ratio is larger. The larger the boost ratio, the larger the current-time product of the lower switching element S3 than the current-time product of the upper switching element S1. Therefore, the permissible current of the upper switching element S1 can be made lower than the permissible current of the lower switching element S3. That is, the number of parallel elements of the upper switching element S1 can be reduced from the number of parallel elements of the lower switching element S3.

FIG. 22 is a diagram for explaining the configuration of the DC / DC converter 3 according to the second embodiment of the second embodiment. The DC / DC converter 3 according to the second embodiment of the second embodiment is also a chopper type buck-boost DC / DC converter. The DC / DC conversion unit 30 according to the second embodiment of the second embodiment includes an upper switching element S1 and a lower switching element S3. The upper switching element S1 is composed of parallel switching elements S1a-S1b in which two switching elements are connected in parallel.

At the time of boosting, the control unit 40 constantly controls the upper parallel switching elements S1a-S1b to be off, and PWM controls the lower switching element S3 according to the boost ratio. The control unit 40 constantly controls the lower switching element S3 to be off at the time of step-down, and PWM-controls the upper parallel switching elements S1a-S1b according to the step-down ratio.

The smaller the step-down ratio at the time of step-down, the higher the duty ratio. That is, the on-time of the upper parallel switching elements S1a-S1b becomes longer.

During the period when the upper parallel switching elements S1a-S1b are off, a forward current flows through the diode D3 of the lower switching element S3. When the upper parallel switching elements S1a-S1b are turned on, a reverse bias voltage is applied to the diode D3 of the lower switching element S3 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction. As a result, the recovery current flows into the upper parallel switching elements S1a-S1b, so that the current flowing at the turn-on of the upper parallel switching elements S1a-S1b increases, and the switching loss of the upper parallel switching elements S1a-S1b increases. ..

On the other hand, in the second embodiment of the second embodiment, the recovery current amount can be reduced by reducing the number of parallel elements of the lower switching element S3 from the number of parallel elements of the upper switching element S1.

The configuration of Example 2 of the second embodiment is such that the smaller the step-down ratio is, the more effective the configuration is. The smaller the step-down ratio, the larger the current-time product of the upper switching element S1 than the current-time product of the lower switching element S3. Therefore, the permissible current of the lower switching element S3 can be made lower than the permissible current of the upper switching element S1. That is, the number of parallel elements of the lower switching element S3 can be reduced from the number of parallel elements of the upper switching element S1.

FIG. 23 is a diagram for explaining the configuration of the DC / DC converter 3 according to the first embodiment of the third embodiment. The DC / DC converter 3 according to the first embodiment of the third embodiment is an interleaved chopper-type buck-boost DC / DC converter. The DC / DC converter 30 according to the first embodiment of the third embodiment is a switching element S1 on the upper side of the first phase, a switching element S3 on the lower side, and a switching element S2 on the upper side of the second phase and switching on the lower side. Includes element S4. The lower switching element S3 of the first phase is composed of parallel switching elements S3a-S3b in which two switching elements are connected in parallel. The lower switching element S4 of the second phase is also composed of parallel switching elements S4a-S4b in which two switching elements are connected in parallel.

The control unit 40 constantly controls the switching elements S1 and S3 on the upper side of the first phase and the second phase to be off at the time of boosting, and the parallel switching elements S3a-S3b and S4a-S4b on the lower side of the first phase and the second phase. Is PWM controlled according to the boost ratio. In the interleave method, the control unit 40 alternately turns on / off the parallel switching element S3a-S3b on the lower side of the first phase and the parallel switching element S4a-S4b on the lower side of the second phase by shifting the phases by 180 °. do. In the interleave method, the current flowing through the output capacitor C6 can be reduced, so that the capacity of the output capacitor C6 can be reduced. Other explanations are the same as those of the chopper type buck-boost DC / DC converter shown in FIG.

FIG. 24 is a diagram for explaining the configuration of the DC / DC converter 3 according to the second embodiment of the third embodiment. The DC / DC converter 3 according to the second embodiment of the third embodiment is an interleaved chopper-type buck-boost DC / DC converter. The DC / DC converter 30 according to the second embodiment of the third embodiment has a switching element S1 on the upper side of the first phase and a switching element S3 on the lower side, and a switching element S2 on the upper side of the second phase and switching on the lower side. Includes element S4. The switching element S1 on the upper side of the first phase is composed of parallel switching elements S1a-S1b in which two switching elements are connected in parallel. The switching element S2 on the upper side of the second phase is also composed of parallel switching elements S2a-S2b in which two switching elements are connected in parallel.

The control unit 40 constantly controls the switching elements S2 and S4 on the lower side of the first phase and the second phase to be off at the time of step-down, and the parallel switching elements S1a-S1b and S3a-S3b on the upper side of the first phase and the second phase. Is PWM controlled according to the step-down ratio. In the interleave method, the control unit 40 alternately turns on / off the parallel switching element S1a-S1b on the upper side of the first phase and the parallel switching element S3a-S3b on the upper side of the second phase by shifting the phases by 180 °. Other explanations are the same as those of the chopper type buck-boost DC / DC converter shown in FIG.

The present disclosure has been described above based on the embodiments. It is understood by those skilled in the art that the embodiments are exemplary and that various modifications are possible for each of these components and combinations of processing processes, and that such modifications are also within the scope of the present disclosure. ..

In the above-described embodiment, an example in which a MOSFET is used for the first switching element S1 to the eighth switching element S8 has been described. In this respect, the present disclosure can be applied even when a switching element such as an IGBT (Insulated Gate Bipolar Transistor) in which a parasitic diode is not formed is used. In this case as well, the recovery current flowing through the external diode can be reduced, and the recovery loss can be reduced.

The present disclosure can also be applied to the case of using a switching element composed of a wide bandgap semiconductor using silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or the like. Is.

The embodiment may be specified by the following items.

[Item 1]
The parallel switching element (S1) in which at least one switching element (S1a-S1b) is connected in parallel is a power conversion device (3) having a power conversion unit (30) in which a plurality of (S1-S8) are connected in series. hand,
Diodes (D1a-D1b) are formed or connected in antiparallel to each switching element (S1a-S1b).
Among a plurality of parallel switching elements (S1-S8), a parallel switching element (S1) having a smaller number of parallels than other parallel switching elements is included.
Power converter (3).
According to this, the recovery loss due to the diode (D1a-D1b) can be reduced.
[Item 2]
The number of parallel switching elements (S1) including switching elements (S1a-S1b) in which diodes (D1a-D1b) for which recovery current should be reduced are formed or connected in antiparallel is larger than the number of parallel switching elements of other parallel switching elements. Few,
The power conversion device (3) according to item 1.
According to this, the recovery loss due to the target diode (D1a-D1b) can be reduced.
[Item 3]
At least one reactor (L1) connected to the low voltage side DC section,
A first flying capacitor circuit (31) and a second flying capacitor circuit (32) connected in series with a high-voltage side DC unit are provided.
The positive terminal of the low voltage side DC portion and the midpoint of the first flying capacitor circuit (31) are electrically connected, and the negative terminal of the low voltage side DC portion and the second flying capacitor circuit (32) are connected. The midpoints are electrically connected,
The reactor (L1) has a path connecting the positive terminal of the low voltage side DC portion and the midpoint of the first flying capacitor circuit (31), a negative terminal of the low voltage side DC portion, and the second flying. Inserted into at least one of the paths connecting the midpoints of the capacitor circuit (32),
The first flying capacitor circuit (31) and the second flying capacitor circuit (32) include a plurality of the parallel switching elements (S1-S8) connected in series, respectively.
The power conversion device (3) according to item 1 or 2.
According to this, it is possible to reduce the recovery loss of the diode in the multi-level power conversion device (3) using the flying capacitor.
[Item 4]
The first flying capacitor circuit (31) is
A first parallel switching element (S1), a second parallel switching element (S2), a third parallel switching element (S3), and a fourth parallel switching element (S4) connected in series,
A connection between the connection point between the first parallel switching element (S1) and the second parallel switching element (S2) and the connection point between the third parallel switching element (S3) and the fourth parallel switching element (S4). The first flying capacitor (C1), which was made, and included,
The second flying capacitor circuit (32) is
The fifth parallel switching element (S5), the sixth parallel switching element (S6), the seventh parallel switching element (S7), and the eighth parallel switching element (S8) connected in series,
A connection between the connection point between the fifth parallel switching element (S5) and the sixth parallel switching element (S6) and the connection point between the seventh parallel switching element (S7) and the eighth parallel switching element (S8). 2nd flying capacitor (C2), including
The power conversion device (3) according to item 3.
According to this, it is possible to reduce the recovery loss of the diode in the three-level power conversion device (3) using the flying capacitor.
[Item 5]
Number of parallels of the first parallel switching element (S1a-S1b), the second parallel switching element (S2a-S2b), the seventh parallel switching element (S7a-S7b), and the eighth parallel switching element (S8a-S8b). Of the third parallel switching element (S3a-S3c), the fourth parallel switching element (S4a-S4c), the fifth parallel switching element (S5a-S5c), and the sixth parallel switching element (S6a-S6c). Less than the number of parallels,
The power conversion device (3) according to item 4.
According to this, it is possible to reduce the recovery loss due to the diodes (D1-D2, D7-D8) during the boosting operation.
[Item 6]
Number of parallels of the third parallel switching element (S3a-S3b), the fourth parallel switching element (S4a-S4b), the fifth parallel switching element (S5a-S5b), and the sixth parallel switching element (S6a-S6b). Of the first parallel switching element (S1a-S1c), the second parallel switching element (S2a-S2c), the seventh parallel switching element (S7a-S7c), and the eighth parallel switching element (S8a-S8c). Less than the number of parallels,
The power conversion device (3) according to item 4.
According to this, the recovery loss due to the diode (D3-D6) at the time of step-down operation can be reduced.
[Item 7]
By controlling the first flying capacitor circuit (31) and the second flying capacitor circuit (32), power is transmitted from the low voltage side DC section to the high voltage side DC section by a boosting operation, and from the high voltage side DC section to the high voltage side DC section. Further equipped with a control unit (40) capable of executing at least one of power transmission by step-down operation to the low-voltage side DC unit.
The control unit (40)
The second parallel switching element (S2), the fourth parallel switching element (S4), the fifth parallel switching element (S5), and the seventh parallel switching element (S7) are turned on, and the first parallel switching element is turned on. (S1), a first mode for controlling the third parallel switching element (S3), the sixth parallel switching element (S6), and the eighth parallel switching element (S8) in an off state.
The first parallel switching element (S1), the third parallel switching element (S3), the sixth parallel switching element (S6) and the eighth parallel switching element (S8) are turned on, and the second parallel switching element is turned on. (S2), a second mode for controlling the fourth parallel switching element (S4), the fifth parallel switching element (S5), and the seventh parallel switching element (S7) to an off state.
The first parallel switching element (S1), the second parallel switching element (S2), the seventh parallel switching element (S7), and the eighth parallel switching element (S8) are turned on, and the third parallel switching element is turned on. (S3), a third mode for controlling the fourth parallel switching element (S4), the fifth parallel switching element (S5), and the sixth parallel switching element (S6) in an off state.
The third parallel switching element (S3), the fourth parallel switching element (S4), the fifth parallel switching element (S5), and the sixth parallel switching element (S6) are turned on, and the first parallel switching element is turned on. (S1), a fourth mode for controlling the second parallel switching element (S2), the seventh parallel switching element (S7), and the eighth parallel switching element (S8) to an off state.
Performing the step-up operation or the step-down operation using the four modes of
The power conversion device (3) according to any one of items 4 to 6.
According to this, various controls are possible by combining the four modes.
[Item 8]
The switching element (S1-S8) is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
The diode (D1-D8) is a parasitic diode of the N-channel MOSFET.
The power conversion device (3) according to any one of items 1 to 7.
According to this, it is possible to reduce the recovery loss due to the reflux current flowing through the parasitic diode.

1 1st DC power supply, 2 2nd DC power supply, 3 DC / DC converter, 30 DC / DC converter, 31, 32 flying capacitor circuit, 40 control unit, C1, C2 flying capacitor, C3, C4 split capacitor, C5 Input capacitor, C6 output capacitor, L1, L2 reactor, S1-S8 switching element, D1-D8 diode.

Claims (8)

A parallel switching element in which at least one switching element is connected in parallel is a power conversion device having a plurality of power conversion units connected in series.
Diodes are formed or connected in antiparallel to each switching element.
Among a plurality of parallel switching elements, a parallel switching element having a smaller number of parallels than other parallel switching elements is included.
Power converter. The number of parallel switching elements in parallel, including switching elements in which diodes to reduce recovery current are formed or connected in antiparallel, is less than the number of parallels in other parallel switching elements.
The power conversion device according to claim 1. At least one reactor connected to the low voltage side DC section,
A first flying capacitor circuit and a second flying capacitor circuit connected in series with a high-voltage side DC unit are provided.
The positive terminal of the low-voltage side DC section and the midpoint of the first flying capacitor circuit are electrically connected, and the negative terminal of the low-voltage side DC section and the midpoint of the second flying capacitor circuit are electrically connected. Connected to
The reactor has a path connecting the positive terminal of the low-voltage side DC portion and the midpoint of the first flying capacitor circuit, and between the negative terminal of the low-voltage side DC portion and the midpoint of the second flying capacitor circuit. Is inserted in at least one of the routes connecting the
The first flying capacitor circuit and the second flying capacitor circuit each include a plurality of the parallel switching elements connected in series.
The power conversion device according to claim 1 or 2. The first flying capacitor circuit is
A first parallel switching element, a second parallel switching element, a third parallel switching element, and a fourth parallel switching element connected in series,
A first flying capacitor connected between the connection point between the first parallel switching element and the second parallel switching element and the connection point between the third parallel switching element and the fourth parallel switching element is included.
The second flying capacitor circuit is
The fifth parallel switching element, the sixth parallel switching element, the seventh parallel switching element, and the eighth parallel switching element connected in series,
A second flying capacitor connected between the connection point between the fifth parallel switching element and the sixth parallel switching element and the connection point between the seventh parallel switching element and the eighth parallel switching element is included.
The power conversion device according to claim 3. The number of parallels of the first parallel switching element, the second parallel switching element, the seventh parallel switching element, and the eighth parallel switching element is the third parallel switching element, the fourth parallel switching element, and the fifth parallel. Less than the number of switching elements and the number of parallels of the sixth parallel switching element,
The power conversion device according to claim 4. The number of parallels of the third parallel switching element, the fourth parallel switching element, the fifth parallel switching element, and the sixth parallel switching element is the first parallel switching element, the second parallel switching element, and the seventh parallel. Less than the number of switching elements and the eighth parallel switching element in parallel,
The power conversion device according to claim 4. By controlling the first flying capacitor circuit and the second flying capacitor circuit, power is transmitted from the low voltage side DC section to the high voltage side DC section by a boosting operation, and the voltage is stepped down from the high voltage side DC section to the low voltage side DC section. It also has a control unit that can execute at least one of the power transmissions in operation.
The control unit
The second parallel switching element, the fourth parallel switching element, the fifth parallel switching element and the seventh parallel switching element are turned on, and the first parallel switching element, the third parallel switching element, and the sixth parallel. The first mode for controlling the switching element and the eighth parallel switching element to the off state,
The first parallel switching element, the third parallel switching element, the sixth parallel switching element and the eighth parallel switching element are turned on, and the second parallel switching element, the fourth parallel switching element, and the fifth parallel. A second mode that controls the switching element and the seventh parallel switching element to the off state,
The first parallel switching element, the second parallel switching element, the seventh parallel switching element and the eighth parallel switching element are turned on, and the third parallel switching element, the fourth parallel switching element, and the fifth parallel switching element. A third mode that controls the switching element and the sixth parallel switching element to the off state,
The third parallel switching element, the fourth parallel switching element, the fifth parallel switching element and the sixth parallel switching element are turned on, and the first parallel switching element, the second parallel switching element, and the seventh parallel. Fourth mode, which controls the switching element and the eighth parallel switching element to the off state,
Performing the step-up operation or the step-down operation using the four modes of
The power conversion device according to any one of claims 4 to 6. The switching element is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
The diode is a parasitic diode of the N-channel MOSFET.
The power conversion device according to any one of claims 1 to 7.

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