JP2022014645A - Method for manufacturing nitride semiconductor device and nitride semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a nitride semiconductor device and method for manufacturing the nitride semiconductor device in which degradation of characteristics can be suppressed.SOLUTION: A method for manufacturing a nitride semiconductor device includes a step for forming a gate insulating film on a gallium nitride semiconductor layer. The step for forming the gate insulating film includes a step for depositing a Si layer on the gallium nitride semiconductor layer in an atmosphere shut off from the atmosphere, and a step for depositing a SiO2 layer on the Si layer while maintaining the atmosphere.SELECTED DRAWING: Figure 2

Description

The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

In a nitride semiconductor device having a MOS (Metal Oxide Semiconductor) structure, a gallium oxide is formed between a silicon oxide layer (SiO ₂ layer) which is a gate insulating film and a gallium nitride layer (GaN layer) on which a channel is formed. It is known that a layer (Ga oxide layer) is formed (see, for example, Patent Document 1).

JP-A-2019-153627

In the MOS structure, if a Ga oxide layer is present between the SiO ₂ layer, which is a gate insulating film, and the GaN layer, characteristics such as channel mobility may deteriorate. Since the characteristics tend to deteriorate as the film thickness of the Ga oxide layer increases, it is desired to reduce the thickness of the Ga oxide layer.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of suppressing deterioration of characteristics.

In order to solve the above problems, the method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes a step of forming a gate insulating film on a gallium nitride based semiconductor layer. The steps for forming the gate insulating film are a step of forming a Si layer on the gallium nitride semiconductor layer in an atmosphere shielded from the atmosphere and a step of forming a SiO ₂ layer on the Si layer while maintaining the atmosphere. And have.

The nitride semiconductor device according to one aspect of the present invention includes a gate insulating film provided on a gallium nitride based semiconductor layer. The gate insulating film has a SiO ₂ layer and a SiO _X layer (0 <X ≦ 2) provided between the SiO ₂ layer and the gallium nitride based semiconductor layer.

According to the present invention, it is possible to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of suppressing deterioration of characteristics.

FIG. 1 is a cross-sectional view showing a configuration example of a MOS transistor according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing an enlarged view of the vicinity of the interface between the gate insulating film and the GaN layer in the MOS transistor shown in FIG. FIG. 3A is a cross-sectional view showing the manufacturing method of the MOS transistor according to the first embodiment of the present invention in the order of processes. FIG. 3B is a cross-sectional view showing the manufacturing method of the MOS transistor according to the first embodiment of the present invention in the order of processes. FIG. 3C is a cross-sectional view showing the manufacturing method of the MOS transistor according to the first embodiment of the present invention in the order of processes. FIG. 3D is a cross-sectional view showing the manufacturing method of the MOS transistor according to the first embodiment of the present invention in the order of processes. FIG. 3E is a cross-sectional view showing the manufacturing method of the MOS transistor according to the first embodiment of the present invention in the order of processes. FIG. 4A is a cross-sectional view showing the method of forming the gate insulating film according to the first embodiment of the present invention in the order of processes. FIG. 4B is a cross-sectional view showing the method of forming the gate insulating film according to the first embodiment of the present invention in the order of processes. FIG. 4C is a cross-sectional view showing the method of forming the gate insulating film according to the first embodiment of the present invention in the order of processes. FIG. 5 is a time chart showing a film formation sequence of the gate insulating film according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing a configuration example of the MOS capacitor according to the second embodiment of the present invention.

An embodiment of the present invention will be described below. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

Further, in the following description, the direction may be described by using the words in the X-axis direction, the Y-axis direction, and the Z-axis direction. For example, the X-axis direction or the Y-axis direction is a direction parallel to the upper surface 10a of the GaN-based semiconductor layer 10. The Z-axis direction is the normal direction of the upper surface 10a of the GaN-based semiconductor layer 10. The Z-axis direction is also the thickness direction of the GaN-based semiconductor layer 10. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

Further, in the following description, the direction of the arrow on the Z axis may be referred to as "up", and the direction opposite to the arrow on the Z axis may be referred to as "down". "Top" and "bottom" do not necessarily mean vertical to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. "Upper" and "lower" are merely expedient expressions for specifying relative positional relationships in regions, layers, films, substrates, and the like, and do not limit the technical idea of the present invention. For example, if the paper surface is rotated 180 degrees, it goes without saying that "upper" becomes "lower" and "lower" becomes "upper".

Further, in the following description, n or p means that electrons or holes are a large number of carriers, respectively. Further, + and-attached to p and n mean that the impurity concentration is relatively high or low, respectively, as compared with the semiconductor regions to which + and-are not added. However, even if the semiconductor regions have the same p and p, it does not mean that the impurity concentrations of the respective semiconductor regions are exactly the same.

<Embodiment 1>
(Configuration of MOS transistor)
FIG. 1 is a cross-sectional view showing a configuration example of a MOS (Metal Office Semiconductor) transistor 100 according to the first embodiment of the present invention. The nitride semiconductor device according to the embodiment of the present invention is, for example, a power semiconductor device and includes the MOS transistor 100 shown in FIG. FIG. 1 shows the unit structure of the MOS transistor 100. The unit structure extends in the Y-axis direction and is repeatedly provided in the X-axis direction. A region provided with a plurality of unit structures is referred to as an active region. Although not shown, an edge termination structure having a function of preventing electric field concentration in the active region is provided around the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure and a JTE (Junction Termination ExtenSiOn) structure.

As shown in FIG. 1, the MOS transistor 100 includes a GaN-based semiconductor layer 10 (an example of the “gallium nitride-based semiconductor layer” of the present invention), a gate insulating film 20 provided on the GaN-based semiconductor layer 10, and a gate. A gate electrode 30 provided on the insulating film 20, an n + type source region 41 provided on the GaN-based semiconductor layer 10, an n + -type drain region 42 provided on the GaN-based semiconductor layer 10, and a GaN-based semiconductor. It has a source electrode 51 provided on the layer 10 and connected to the source region 41, and a drain electrode 52 provided on the GaN-based semiconductor layer 10 and connected to the drain region 42.

Each of the substrate and the layer constituting the GaN-based semiconductor layer 10 is GaN. For example, the GaN-based semiconductor layer 10 has an n + type GaN substrate 11, an n-type GaN layer 12, and a p-type GaN layer 13. Each of the substrate and the layer constituting the GaN-based semiconductor layer 10 may contain GaN as a main component and may further contain one or more elements of an aluminum (Al) element and an indium (In) element.

In the GaN-based semiconductor layer 10 shown in FIG. 1, the GaN substrate 11 is a single crystal C-plane GaN substrate containing n-type impurities. The GaN layer 12 is a single crystal GaN layer containing n-type impurities provided on the GaN substrate 11 by the epitaxial growth method. The GaN layer 13 is a single crystal GaN layer containing p-type impurities provided on the GaN layer 12 by the epitaxial growth method. In FIG. 1, the upper surface 10a of the GaN-based semiconductor layer 10 is the upper surface of the GaN layer 13, and the lower surface 10b of the GaN-based semiconductor layer 10 is the lower surface of the GaN substrate 11.

The n-type impurity used in the MOS transistor 100 includes, for example, one or more elements of Si (silicon), Ge (germanium), and O (oxygen). For example, Si element is used as the n-type impurity. The p-type impurity used in the MOS transistor 100 contains one or more elements of Mg (magnesium), Ca (calcium), Be (berylium) and Zn (zinc). For example, Mg element is used as the p-type impurity.

The n + type source region 41 and the n + type drain region 42 are provided in the GaN layer 13. The source region 41 and the drain region 42 are exposed on the upper surface 10a of the GaN-based semiconductor layer 10 and are shallower than the bottom surface of the GaN-based semiconductor layer 10 from the upper surface 10a of the GaN-based semiconductor layer 10 (for example, 0. It is provided up to a depth of 1 μm). As shown in FIG. 1, the source region 41 and the drain region 42 are separated from each other in the X-axis direction. In the GaN layer 13, the channel of the MOS transistor 100 is formed in the region 45 sandwiched between the source region 41 and the drain region 42. Hereinafter, the area 45 is referred to as a channel area.

The gate insulating film 20 is provided on the GaN layer 13. For example, the gate insulating film 20 is continuously provided on the channel region 45 sandwiched between the source region 41 and the drain region 42, on a part of the source region 41, and on a part of the drain region 42. There is. The gate insulating film 20 is, for example, a silicon oxide film formed by plasma CVD (chemical vapor deposition).

When the gate insulating film 20 is a silicon oxide film, the film thickness is preferably 30 nm or more, more preferably about 100 nm, from the viewpoint of the withstand voltage required for the power semiconductor device. More specifically, the gate of a power semiconductor device is required to withstand a voltage of about 30 V. The dielectric breakdown electric field of the silicon oxide film is about 10 MV / cm. Therefore, when a silicon oxide film is used as the gate insulating film 20, the thickness of the gate insulating film 20 needs to be about 30 nm in order to obtain a withstand voltage of about 30 V. Further, considering that the withstand voltage of the gate insulating film 20 has a margin of about 3 times, the film thickness of the gate insulating film 20 needs to be about 100 nm.

The gate electrode 30 is provided on the gate insulating film 20. The gate electrode 30 is separated from the source electrode 51 and the drain electrode 52, respectively. Each of the gate electrode 30, the source electrode 51 and the drain electrode 52 is made of, for example, aluminum (Al) or an Al alloy, and has a thickness of 100 nm.

The gate insulating film 20 will be described more specifically. FIG. 2 is an enlarged cross-sectional view showing the vicinity of the interface between the gate insulating film 20 and the GaN layer 13 in the MOS transistor 100 shown in FIG. As shown in FIG. 2, the gate insulating film 20 has a SiO _X layer 21 and a SiO ₂ layer 22 provided on the SiO _X layer. X in the SiO _X layer 21 is a value larger than 0 and smaller than 2 (0 <X ≦ 2). The SiO _X layer 21 is thinner than the SiO ₂ layer 22. The thickness of the SiO _X layer 21 is 0.3 nm or more and 2.4 nm or less, and the thickness of the SiO ₂ layer 22 is 30 nm or more. As will be described later, in the SiO _X layer 21, when the gate insulating film 20 is formed by plasma CVD, the thin silicon (Si) layer previously formed on the GaN layer 13 is oxidized by oxygen radicals or oxygen ions. It is formed by

In the GaN layer 13, a gallium oxide layer (an example of the “gallium-based oxide layer” of the present invention; hereinafter, Ga oxide layer) 131 may be formed in the vicinity of the interface with the SiO _X layer 21. The Ga oxide layer 131 is a transition layer located near the interface between the GaN layer 13 and the SiO _X layer 21 and whose composition changes from the GaN layer 13 to the SiO _X layer 21. The GaN layer 13 and the SiO _X layer 21 may be mixed.

For example, the Si layer of the thin film previously formed on the GaN layer 13 may be completely oxidized and disappear, and the GaN layer 13 and the SiO _X layer 21 may be in a mixed state. The layer in this mixed state may be the Ga oxide layer 131. When the Si layer disappears and the GaN layer 13 and the SiO _X layer 21 are in a mixed state, good characteristics can be obtained.

The Ga oxide layer 131 is formed, for example, by oxidizing the upper surface of the GaN layer 13 with oxygen radicals or oxygen ions. The Ga oxide layer 131 has, for example, GaO having a ratio of the number of atoms of the Ga element and the number of atoms of the O element of 1: 1 and GaO ₂ having the ratio of 1: 2 and the ratio of 2: 3. It may contain any one or more of Ga ₂ O ₃ . The Ga oxide layer 131 may contain other elements (one or more elements such as Si, Al, N, C and H) in addition to Ga and O.

From the viewpoint of the mobility characteristics and the stress voltage characteristics of the MOS transistor 100, the thickness of the Ga oxide layer 131 is preferably thin, more preferably 0.7 nm or less. More specifically, the mobility of the MOS transistor 100 depends on the thickness of the Ga oxide layer 131 formed at the interface between the gate insulating film 20 and the GaN layer 13. The mobility of the MOS transistor 100 tends to increase as the thickness of the Ga oxide layer 131 becomes thinner. Therefore, the thickness of the Ga oxide layer 131 is preferably thin, and more preferably 0.7 nm or less, which is close to the measurement limit of the film thickness.

Further, a maximum voltage of about 30 V is applied to the gate of the MOS transistor 100. In the MOS transistor, electron accumulation occurs due to this positive voltage stress, and as a result, hysteresis occurs in the relationship between the drain current (Id) and the gate voltage (Vg) (hereinafter referred to as Id-Vg characteristic). Hysteresis of the Id-Vg characteristic means that the transistor characteristic changes, so it is important to reduce this. The hysteresis of the Id-Vg characteristic depends on the thickness of the Ga oxide layer 131 formed at the interface between the gate insulating film 20 and the GaN layer 13, and tends to increase as the thickness of the Ga oxide layer 131 increases. be. Therefore, from this viewpoint as well, the thickness of the Ga oxide layer 131 is preferably thin, and more preferably 0.7 nm or less, which is close to the measurement limit of the film thickness.

(Production method)
Next, a method for manufacturing the MOS transistor 100 according to the first embodiment of the present invention will be described. 3A to 3E are cross-sectional views showing the manufacturing method of the MOS transistor 100 according to the first embodiment of the present invention in the order of processes. The MOS transistor 100 is manufactured by various devices such as a film forming device (including an epitaxial growth device, a plasma CVD device, a sputtering device, etc.), an exposure device, an etching device, an ion implantation device, and the like. Hereinafter, these devices are collectively referred to as manufacturing devices.

As shown in FIG. 3A, the manufacturing apparatus sequentially epitaxially forms the n-type GaN layer 12 and the p-type GaN layer 13 on the n + type GaN substrate 11. As a result, the GaN-based semiconductor layer 10 is completed.

Next, as shown in FIG. 3B, the manufacturing apparatus forms an n + type source region 41 and an n + type drain region 42 in the p-type GaN layer 13. For example, the manufacturing apparatus forms a resist mask having openings for forming the source region 41 and the drain region 42 on the GaN layer 13, and ion-implants n-type impurities such as Si into the GaN layer 13 through the resist mask. .. Next, the manufacturing apparatus removes the resist mask. Then, the manufacturing apparatus heats the GaN-based semiconductor layer 10 in an inert gas atmosphere such as nitrogen (N2) gas to activate the n-type impurities ion-implanted into the GaN layer 13. As a result, the source region 41 and the drain region 42 are formed.

Next, as shown in FIG. 3C, the manufacturing apparatus uses a plasma CVD method to form a laminated gate insulating film 20 including the SiO _X layer 21 and the SiO ₂ layer 22 on the GaN layer 13. The method of forming the gate insulating film 20 will be described later with reference to FIGS. 4A to 4C and FIG. Next, as shown in FIG. 3D, the manufacturing apparatus partially etches and removes the gate insulating film 20, and the gate insulating film 20 forms a region where the source electrode 51 and the drain electrode 52 (see FIG. 1) are formed. Expose from below.

Next, as shown in FIG. 3D, the manufacturing apparatus forms a gate electrode 30, a source electrode 51, and a drain electrode 52. For example, in a manufacturing apparatus, an aluminum (Al) film or an Al alloy film is deposited by electron beam (EB) on a GaN layer 13 in which the gate insulating film 20 is partially formed, and the vapor-deposited Al film or Al alloy film is partially deposited. Etching. As a result, the gate electrode 30, the source electrode 51, and the drain electrode 52 are formed. Through the above steps, the MOS transistor 100 shown in FIG. 1 is completed.

Next, the process of forming the gate insulating film 20 shown in FIG. 3C will be described more specifically. 4A to 4C are cross-sectional views showing a method of forming the gate insulating film 20 according to the first embodiment of the present invention in order of steps. In FIG. 4A, the manufacturing apparatus etches the upper surface (upper surface 10a of the GaN-based semiconductor layer 10) of the GaN layer 13 on which the source region 41 and the drain region 42 are formed with dilute hydrofluoric acid or the like to remove the oxide film. Next, the manufacturing apparatus arranges the GaN-based semiconductor layer 10 in the depressurized chamber, and in this chamber, plasma CVD using monosilane (SiH ₄ ) as a raw material gas (the "first plasma CVD" of the present invention). One example) is performed. This raw material gas does not contain oxidized species such as oxygen (O ₂ ), water (H ₂ O) or ozone (O ₃ ). As a result, as shown in FIG. 4B, the manufacturing apparatus forms an ultrathin Si layer 15 on the GaN layer 13. The film thickness of the Si layer 15 is, for example, 0.2 mm or more and 1.6 mm or less. Hereinafter, the plasma CVD raw material gas forming the Si layer 15 is referred to as a first raw material gas.

Next, the manufacturing apparatus performs plasma CVD (an example of the "second plasma CVD" of the present invention) using monosilane (SiH ₄ ) and oxygen (O ₂ ) as raw materials in the depressurized chamber. As a result, as shown in FIG. 4C, the manufacturing apparatus oxidizes the Si layer 15 to form the SiO _X layer 21, and also forms the SiO ₂ layer 22 on the SiO _X layer 21. In this step, the O ₂ gas supplied into the chamber is excited to become oxygen radicals or oxygen ions, and the oxygen radicals or oxygen ions oxidize the Si layer 15 to form the SiO _X layer 21. The SiO _X layer 21 protects the surface of the GaN layer 13. Further, in the chamber, the SiH ₄ gas and the O ₂ gas react with each other to form the SiO ₂ layer 22 on the SiO _X layer 21. Hereinafter, the plasma CVD raw material gas forming the SiO _X layer 21 and the SiO ₂ layer 22 is referred to as a second raw material gas.

In the above production method, the outermost surface of the GaN layer 13 may be oxidized by oxygen radicals or oxygen ions. As a result, in the GaN layer 13, the Ga oxide layer 131 may be formed in the vicinity of the interface with the gate insulating film 20. The film thickness of the Ga oxide layer 131 is, for example, 0.7 nm or less.

Further, even after the film formation of the SiO ₂ layer 22, a part of the Si layer 15 may remain. In this case, the Si layer 15 is left between the SiO _X layer 21 and the GaN layer 13, or between the SiO _X layer 21 and the Ga oxide layer 131.

FIG. 5 is a time chart showing a film forming sequence of the gate insulating film 20 according to the first embodiment of the present invention. The horizontal axis of FIG. 5 is time. In FIG. 5, time T1 indicates the timing at which the valve of the monosilane (SiH ₄ ) supply pipe connected to the chamber opens and the amount of SiH ₄ gas supplied into the chamber reaches a predetermined amount. The time T0 indicates the timing at which the valve of the piping for supplying the inert gas connected to the chamber opens and the amount of the inert gas supplied into the chamber reaches a predetermined amount. Since the pressure in the chamber is adjusted by the inert gas, the time T2 indicates the timing when the pressure in the chamber reaches a predetermined value by the automatic pressure control valve. As the inert gas, for example, argon (Ar) is used. Time T3 indicates when the discharge (ie, plasma generation) in the chamber begins. Time T4 indicates the timing at which the valve of the oxygen (O ₂ ) supply pipe connected to the chamber opens and the amount of O ₂ gas supplied into the chamber reaches a predetermined amount. The time T5 indicates the timing at which the discharge in the chamber is stopped. Time T6 indicates the timing at which the valve of the pipe for supplying O ₂ and the valve of the pipe for supplying SiH ₄ are closed at the same time. Time T7 indicates the timing at which the automatic pressure control valve is opened. The time T8 indicates the timing at which the valve of the piping for supplying the inert gas is closed.

In the film formation sequence shown in FIG. 5, the Si layer 15 (see FIG. 4B) is formed between the times T3 and T4. Further, between the times T4 and T5, the SiO _X layer 21 and the SiO ₂ layer 22 are formed. The SiO _X layer 21 is formed in the initial stage between the times T4 and T5, and then the SiO ₂ layer 22 is formed.

As shown in FIG. 5, SiH ₄ and O ₂ are used as the raw material gas for plasma CVD. Further, Ar is used as the inert gas. Since the raw material gas does not contain organometallic gas, the impurity carbon in each of the SiO _X layer 21 and the SiO ₂ layer 22 is zero (0) or a value close to zero (that is, a value equal to or less than the measurement limit value). For example, in each of the SiO _X layer 21 and the SiO ₂ layer 22, the carbon (C) concentration is 4 × 10 ¹⁷ cm ^-3 or less, respectively.

As described above, the method for manufacturing the MOS transistor 100 according to the first embodiment of the present invention includes a step of forming the gate insulating film 20 on the GaN-based semiconductor layer 10. The steps of forming the gate insulating film 20 include a step of forming a Si layer 15 on the GaN-based semiconductor layer 10 in an atmosphere shielded from the atmosphere (for example, in a decompressed chamber) and a depressurized atmosphere in the chamber. It includes a step of forming a SiO ₂ layer 22 on the Si layer 15 while maintaining the film.

According to this, when the SiO ₂ layer 22 is formed, at least a part of the Si layer 15 is oxidized to form the SiO _X layer 21 (X = <2). As a result, the upper surface 10a of the GaN-based semiconductor layer 10 can be protected by the SiO _X layer 21, and the oxidation of the upper surface 10a can be suppressed. Since the formation of the Ga oxide layer 131 on the upper surface 10a of the GaN-based semiconductor layer 10 can be suppressed, deterioration of the characteristics of the MOS transistor 100 due to the Ga oxide layer 131 (for example, deterioration of channel mobility and Id-Vg). (Hysteresis of characteristics, etc.) can be suppressed.

Further, in the above manufacturing method, in the step of forming the Si layer 15, plasma CVD using the first raw material gas may be performed to form the Si layer 15. In the step of forming the SiO ₂ layer, plasma CVD may be performed to form the SiO ₂ layer. The plasma CVD raw material gas (second raw material gas) that forms the SiO ₂ layer may contain an oxidizing species that oxidizes the Si layer 15. According to this, in plasma CVD, the SiO _X layer 21 and the SiO ₂ layer 22 can be continuously formed by switching the raw material gas, so that the gate insulating film 20 can be easily manufactured. Further, since the SiO _X layer 21 and the SiO ₂ layer 22 can be continuously formed without opening the inside of the chamber to the atmosphere, it is possible to prevent impurities from being mixed between the SiO _X layer 21 and the SiO ₂ layer 22. be able to. As a result, deterioration of the characteristics of the MOS transistor 100 can be further suppressed.

Further, in the step of forming the Si layer 15 into a film, the Si layer 15 may be formed into a film having a thickness of 0.2 nm or more and 1.6 nm or less. In the experiment conducted by the present inventor, the formation of the Ga oxide layer 131 could be suppressed by forming the Si layer 15 at 0.2 nm or more. Further, by forming the Si layer to a thickness of 1.6 nm or less, almost all of the Si layer 15 could be oxidized when the SiO ₂ layer 22 was formed.

The relationship between the thickness Tsi1 of the Si layer 15 at the time of film formation and the thickness of the Ga oxide layer 131 is determined by the plasma CVD apparatus used for film formation of the gate insulating film 20 and the plasma CVD processing conditions (for example, the raw material gas). It may differ depending on the flow rate, high frequency power, etc.). Therefore, the relationship between the thickness Tsi1 of the Si layer 15 at the time of film formation and the thickness of the Ga oxide layer 131 is investigated in advance for each device and treatment condition, and the thickness of the Ga oxide layer 131 is allowed. The lower limit of the thickness Tsi1 at the time of film formation of the Si layer 15 may be set so as to be within the range.

Further, the relationship between the thickness Tsi1 at the time of film formation of the Si layer 15 and the residual thickness Tsi2 of the Si layer 15 after the film formation of the SiO ₂ layer 22 is also determined by the plasma CVD apparatus used for the film formation of the gate insulating film 20. , It is conceivable that it differs depending on the processing conditions of plasma CVD (for example, the flow rate of the raw material gas, the high frequency power, etc.). Therefore, the relationship between the thickness Tsi1 and the residual thickness Tsi2 at the time of film formation of the Si layer 15 is investigated for each device and processing conditions, and the Si layer 15 is formed so that the residual thickness Tsi2 is within the allowable range. The upper limit value of the thickness Tsi1 at the time of the film may be set.

In the experiment conducted by the present inventor, not only the Ga oxide layer 131 but also the Si layer 15 tends to increase the electron storage density due to positive voltage stress as the residual thickness Tsi2 increases. From the viewpoint of reducing the electron storage density due to positive voltage stress and reducing the hysteresis of the Id-Vg characteristic, it is preferable that the residual thickness Tsi2 of the Si layer 15 is as thin as possible.

The MOS transistor 100 according to the first embodiment of the present invention includes a gate insulating film 20 provided on the GaN-based semiconductor layer 10. The gate insulating film 20 has a SiO ₂ layer 22 and a SiO _X layer 21 (0 <X ≦ 2) provided between the SiO ₂ layer 22 and the GaN-based semiconductor layer 10. According to this, the upper surface 10a of the GaN-based semiconductor layer 10 is protected by the SiO _X layer, and the formation of the Ga oxide layer 131 on the upper surface 10a is suppressed. Thereby, deterioration of the characteristics of the MOS transistor 100 (for example, reduction of channel mobility, hysteresis of Id-Vg characteristics, etc.) caused by the Ga oxide layer 131 can be suppressed.

(Modification example)
In the first embodiment, it has been described that as the raw material gas (first raw material gas) for plasma CVD forming the Si layer 15 (see FIG. 4B), a gas containing SiH ₄ and not containing an oxidized species is used. However, in the embodiment of the present invention, the first raw material gas is not limited to this. The first raw material gas may contain disilane (Si ₂ H ₆ ) or may contain both Si H ₄ and Si ₂ H ₆ . In the embodiment of the present invention, the Si layer 15 may be formed by using a first raw material gas containing at least one of SiH ₄ and Si ₂ H ₆ and not containing an oxidized species.

Further, in the first embodiment, a gas containing SiH ₄ and O ₂ is used as the raw material gas (second raw material gas) for plasma CVD forming the SiO _X layer 21 and the SiO ₂ layer 22 (see FIG. 4C). I explained that. However, in the embodiment of the present invention, the second raw material gas is not limited to this. The second raw material gas may contain Si ₂ H ₆ and O ₂ , or may contain both Si H ₄ and Si ₂ H ₆ and O ₂ . Further, the oxidized species contained in the second raw material gas is not limited to O ₂ . The oxidized species contained in the second raw material gas may contain at least one of H ₂ O or O ₃ in addition to O ₂ , or at least one of H ₂ O or O ₃ instead of O ₂ . The above may be included. In the embodiment of the present invention, the SiO _X layer 21 and the SiO ₂ layer 22 may be formed by using a second raw material gas containing at least one of O ₂ , H ₂ O and O ₃ as an oxidizing species.

Further, in the first embodiment, the case where the MOS transistor 100 is a horizontal transistor has been described. However, in the embodiment of the present invention, the MOS transistor included in the nitride semiconductor device is not limited to the horizontal type and may be the vertical type. The vertical MOS transistor has one of the source electrode 51 and the drain electrode 52 on the upper surface 10a side of the GaN-based semiconductor layer 10, and the other of the source electrode 51 and the drain electrode 52 on the lower surface 10b side of the GaN-based semiconductor layer 10. Have. Even in such a case, by providing the above-mentioned gate insulating film 20 in the vertical MOS transistor, the same effect as in the case of the horizontal MOS transistor 100 can be obtained.

(Embodiment 2)
In the first embodiment described above, it has been described that the nitride semiconductor device according to the embodiment of the present invention is a power semiconductor device and includes the MOS transistor 100 shown in FIG. However, the nitride semiconductor device according to the embodiment of the present invention is not limited to this. The nitride semiconductor device may include the MOS capacitor 200 shown in FIG.

FIG. 6 is a cross-sectional view showing a configuration example of the MOS capacitor 200 according to the second embodiment of the present invention. As shown in FIG. 6, the MOS capacitor 200 includes a GaN-based semiconductor layer 10A (an example of the “gallium nitride-based semiconductor layer” of the present invention) and a gate insulating film 20 provided on the upper surface 10Aa of the GaN-based semiconductor layer 10A. A gate electrode 30 provided on the gate insulating film 20 and a back surface electrode 60 provided on the lower surface 10Ab side of the GaN-based semiconductor layer 10A are provided. For example, the back surface electrode 60 is made of Al or an Al alloy, and is in ohmic contact with the bottom surface 10Ab of the GaN-based semiconductor layer 10A.

Each of the substrate and the layer constituting the GaN-based semiconductor layer 10A is GaN. For example, the GaN-based semiconductor layer 10A has an n + type GaN substrate 11 and an n-type GaN layer 12. Each of the substrate and the layer constituting the GaN-based semiconductor layer 10A may contain GaN as a main component and may further contain one or more elements of an aluminum (Al) element and an indium (In) element.

Also in the second embodiment, the configuration of the gate insulating film 20 is the same as the configuration described with reference to FIGS. 1 and 2 in the first embodiment. Further, the manufacturing method of the gate insulating film 20 is the same as the manufacturing method described in the first embodiment with reference to FIGS. 4A to 4C and FIG.

In the GaN layer 12, a Ga oxide layer 121 (an example of the “oxide semiconductor layer” of the present invention) may be formed in the vicinity of the interface with the SiO _X layer 21. The Ga oxide layer 121 is a transition layer located near the interface between the GaN layer 12 and the SiO _X layer 21 and whose composition changes from the GaN layer 12 to the SiO _X layer 21. The Ga oxide layer 121 is formed, for example, by oxidizing the upper surface of the GaN layer 12 with oxygen radicals or oxygen ions. The Ga oxide layer 121 has, for example, GaO having a ratio of the number of atoms of the Ga element and the number of atoms of the O element of 1: 1 and GaO ₂ having the ratio of 1: 2 and the ratio of 2: 3. It may contain any one or more of Ga ₂ O ₃ . The Ga oxide layer 121 may contain other elements (one or more elements such as Si, Al, N, C and H) in addition to Ga and O.

As described above, the MOS capacitor 200 according to the second embodiment of the present invention includes a gate insulating film 20 provided on the GaN-based semiconductor layer 10. The gate insulating film 20 has a SiO ₂ layer 22 and a SiO _X layer 21 (0 <X ≦ 2) provided between the SiO ₂ layer 22 and the GaN-based semiconductor layer 10. According to this, the upper surface 10a of the GaN-based semiconductor layer 10 is protected by the SiO _X layer, and the formation of the Ga oxide layer 131 on the upper surface 10a is suppressed. As a result, deterioration of the characteristics of the MOS capacitor 200 due to the Ga oxide layer 131 can be suppressed.

<Other embodiments>
As mentioned above, the invention has been described by embodiments and variations, but the statements and drawings that form part of this disclosure should not be understood to limit the invention. Various alternative embodiments and modifications will be apparent to those skilled in the art from this disclosure.

For example, the method for forming the gate insulating film 20 is not limited to the plasma CVD method. The gate insulating film 20 may be formed by an atomic layer deposition method (ALD). For example, the manufacturing apparatus may form the Si layer 15 in the chamber by the ALD method, and continuously form the SiO ₂ layer 22 by the ALD method without opening the atmosphere in the chamber to the atmosphere. Even with such a method, when forming the SiO ₂ layer 22, the Si layer 15 can be oxidized to form the SiO _X layer 21 (0 <X ≦ 2).

As described above, it goes without saying that the present invention includes various embodiments not described here. At least one of the various omissions, substitutions and modifications of the components may be made without departing from the gist of the embodiments and modifications described above. Further, the effects described in the present specification are merely exemplary and not limited, and other effects may be obtained. The technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description.

10, 10A GaN-based semiconductor layer 10a, 10Aa Upper surface 10Ab, 10b Lower surface 11 GaN substrate 12, 13 GaN layer 15 Si layer 20 Gate insulating film 21 SiO _X layer 22 SiO ₂ layer 30 Gate electrode 41 Source region 42 Drain region 45 Channel region 51 Source electrode 52 Drain electrode 60 Back side electrode 100 MOS transistor 121, 131 Ga oxide layer 200 MOS capacitor

Claims (13)

A step of forming a gate insulating film on a gallium nitride based semiconductor layer is provided.
The step of forming the gate insulating film is
A process of forming a Si layer on the gallium nitride based semiconductor layer in an atmosphere shielded from the atmosphere, and
A method for manufacturing a nitride semiconductor device, comprising a step of forming a SiO ₂ layer on the Si layer while maintaining the atmosphere. The nitride according to claim 1, wherein in the step of forming the SiO ₂ layer, at least a part of the Si layer is oxidized to form a SiO _X layer (0 <X≤2) thinner than the SiO ₂ layer. Manufacturing method of physical semiconductor equipment. In the step of forming the Si layer,
The first plasma CVD using the first raw material gas was performed to form the Si layer, and the Si layer was formed.
In the step of forming the SiO ₂ layer,
The second plasma CVD using the second raw material gas was performed to form the SiO ₂ layer, and the film was formed.
The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the second raw material gas contains an oxidizing species that oxidizes the Si layer. The method for manufacturing a nitride semiconductor device according to claim 3, wherein the first raw material gas contains at least one of monosilane and disilane and does not contain an oxidized species. The second raw material gas contains at least one of monosilane and disilane and an oxidized species.
The method for manufacturing a nitride semiconductor device according to claim 3 or 4, wherein the oxidized species contains at least one or more of oxygen, water and ozone. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 5, wherein in the step of forming the Si layer, the Si layer is formed into a film having a thickness of 0.2 nm or more and 1.6 nm or less. .. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 6, wherein the gallium nitride based semiconductor layer is GaN. A gate insulating film provided on a gallium nitride based semiconductor layer is provided.
The gate insulating film is
_Two layers of SiO and
A nitride semiconductor device having a SiO _X layer (0 <X≤2) provided between the SiO ₂ layer and the gallium nitride based semiconductor layer. The nitride semiconductor device according to claim 8, wherein the SiO _X layer is thinner than the SiO ₂ layer. The nitride semiconductor device according to claim 8, wherein the thickness of the SiO ₂ layer is 30 nm or more. The nitride semiconductor device according to any one of claims 8 to 10, wherein the C concentration in the SiO _X layer and the C concentration in the SiO ₂ layer are 4 × 10 ¹⁷ cm ^-3 or less, respectively. The nitride semiconductor device according to any one of claims 8 to 11, further comprising a Si layer provided between the SiO _X layer and the gallium nitride based semiconductor layer. A gallium-based oxide layer provided between the gallium nitride-based semiconductor layer and the SiO _X layer is further provided.
The nitride semiconductor device according to any one of claims 8 to 12, wherein the gallium-based oxide layer has a thickness of 0.7 nm or less.

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