JP2022010932A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To provide a semiconductor device capable of suppressing a decrease and variation of a recovery tolerance dose in a peripheral breakdown voltage region, and a method for manufacturing the same.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a first protection film 10 including an upper surface higher than an upper surface of an electrode 8 on a first principal surface 4 in a peripheral breakdown voltage region 3; forming a second protection film 14 covering the electrode 8 and the first protection film 10 and having a first step according to a height difference between an anode electrode 8 and the first protection film 10 on a surface; forming a second step corresponding to the first step on a second principal surface 5 of a semiconductor substrate 1 by grinding the second principal surface 5 with the surface having the first step pressed down; forming an LTC layer 13 by irradiating the second principal surface 5 having the second step with a light ion; flattening the surface of the second protection fil 14 by grinding; and removing the LTC layer 13 of a cell region 2 by grinding the second principal surface 5 of the semiconductor substrate 1 with the flattened surface pressed down.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to a semiconductor device capable of suppressing variation and reduction in the recovery capacity of the peripheral pressure resistant region and a method for manufacturing the same.

The diode having a vertical structure has a problem that an overcurrent flows in the peripheral withstand voltage region during recovery and the breakdown resistance is lowered. As a countermeasure, a lifetime control (hereinafter referred to as LTC) layer is formed only in the peripheral pressure resistant region (see, for example, Patent Document 1). When the LTC layer is formed in the peripheral pressure resistant region, light ions are irradiated using a metal mask in which only the peripheral pressure resistant region is opened. Since the lifetime of the region irradiated with light ions is shortened, the generation of carriers is suppressed and the overcurrent during recovery is suppressed. Therefore, it is possible to suppress a decrease in the fracture resistance.

Japanese Unexamined Patent Publication No. 9-36388

When the LTC layer is formed, the mask is superimposed on the surface pattern and ion-irradiated. This superposition was difficult, and the LTC layer was sometimes formed so as to deviate from the peripheral pressure resistant region. When the LTC layer is formed outside the peripheral pressure resistant region, the generation of carriers generated in the peripheral pressure resistant region cannot be sufficiently suppressed, and the recovery capacity varies. If it deviates significantly, the recovery capacity will decrease.

The present disclosure has been made in order to solve the above-mentioned problems, and an object thereof is to obtain a semiconductor device and a method for manufacturing the same, which can suppress the variation and decrease of the recovery withstand capacity in the peripheral withstand voltage region.

The method for manufacturing a semiconductor device according to the present disclosure includes a step of preparing a first conductive type semiconductor substrate having a cell region and a peripheral withstand voltage region surrounding the cell region in a plan view, and a step of preparing the semiconductor substrate in the cell region. A step of forming a second conductive type anode layer on the first main surface, a step of forming a second conductive type well layer on the first main surface of the semiconductor substrate in the peripheral pressure resistant region, and the first main surface. A step of forming a first conductive type cathode layer on the second main surface of the semiconductor substrate on the opposite side of the surface, and forming an electrode connected to the anode layer on the first main surface in the cell region. A step of forming a first protective film having an upper surface higher than the upper surface of the electrode on the first main surface in the peripheral pressure resistant region, and covering the electrode and the first protective film. In a step of forming a second protective film having a first step on the surface according to the height difference between the electrode and the first protective film, and in a state where the surface having the first step is pressed down. A step of grinding the second main surface of the semiconductor substrate to form a second step corresponding to the first step on the second main surface, and the second main surface having the second step. A step of irradiating the semiconductor with light ions to form a lifetime control layer, a step of grinding and flattening the surface of the second protective film, and a step of pressing the flattened surface to press the semiconductor substrate. It is characterized by comprising a step of grinding the second main surface of the cell region to remove the lifetime control layer in the cell region.

In the present disclosure, a step is formed on the surface of the second protective film by the height difference between the first protective film formed in the peripheral pressure resistant region and the electrode formed in the cell region. With this surface pressed down, the second main surface of the semiconductor substrate is ground to form a step. The second main surface having a step is irradiated with light ions to form an LTC layer. Then, the surface of the second protective film is ground to be flat, and the second main surface is ground in a pressed state to remove the LTC layer in the cell region. As a result, since the LTC layer is self-aligned with reference to the first protective film, it is possible to suppress the positional deviation from the peripheral pressure resistant region. Therefore, it is possible to suppress the variation and decrease in the recovery capacity of the peripheral pressure resistant region.

It is a top view which shows the semiconductor device which concerns on embodiment. It is sectional drawing which follows I-II of FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment.

The semiconductor device and the manufacturing method thereof according to the embodiment will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted. Since the drawings are schematically shown, the interrelationships of size and position are variable.

In addition, in the following description, terms such as "upper", "lower", and "side" may be used to mean a specific position and direction. These terms are used for convenience to facilitate understanding of the contents of the embodiments and do not limit the orientation and position of the embodiment.

The conductive type of the semiconductor will be described with the first conductive type as the n type and the second conductive type as the p type. However, these may be reversed and the first conductive type may be p-type and the second conductive type may be n-type. The n ⁺ type means that the donor concentration is higher than that of the n type, and the n ^- type means that the donor concentration is lower than that of the n type. Similarly, the p ⁺ type means that the acceptor concentration is higher than that of the p type, and the p ^- type means that the acceptor concentration is lower than that of the p type.

FIG. 1 is a plan view showing a semiconductor device according to an embodiment. The semiconductor substrate 1 has a cell region 2 and a peripheral withstand voltage region 3 surrounding the cell region 2 in a plan view. The cell region 2 is an active region that is energized during operation of the semiconductor device. The peripheral pressure resistance region 3 is a region for maintaining the pressure resistance.

FIG. 2 is a cross-sectional view taken along the line I-II of FIG. The semiconductor substrate 1 has a first main surface 4 and a second main surface 5 opposite to each other. The semiconductor substrate 1 has an n ^- type drift layer. The thickness of the semiconductor substrate 1 is Tpi.

In the cell region 2, the p-type anode layer 6 is formed on the first main surface 4 of the semiconductor substrate 1. The anode layer 6 projects from the cell region 2 to the peripheral pressure resistant region 3. The end of the anode layer 6 is located in the peripheral pressure resistant region 3. In the peripheral pressure resistant region 3, the p-type well layer 7 is formed so as to sandwich the anode layer 6 on the first main surface 4 of the semiconductor substrate 1. A plurality of well layers 7 may be provided.

The anode electrode 8 is provided on the first main surface 4 of the semiconductor substrate 1 and is electrically connected to the anode layer 6. An insulating film 9 is provided on the first main surface 4 of the peripheral pressure resistant region 3. The end of the insulating film 9 on the cell region 2 side is the boundary between the cell region 2 and the peripheral pressure resistant region 3. The end of the insulating film 9 on the cell region 2 side is covered with the anode electrode 8. The first protective film 10 covers the end portion of the anode electrode 8 and the insulating film 9. The thickness Tb of the first protective film 10 is thicker than the thickness Ta of the anode electrode 8 and the thickness Td of the insulating film 9.

The n-type cathode layer 11 is formed on the second main surface 5 of the semiconductor substrate 1. The cathode electrode 12 is provided on the second main surface 5 of the semiconductor substrate 1 and is electrically connected to the cathode layer 11.

The LTC layer 13 is formed on the second main surface 5 side of the semiconductor substrate 1 in the peripheral withstand voltage region 3. The LTC layer 13 is a region irradiated with light ions such as He and H. The LTC layer 13 has a flat portion 13a extending in a direction perpendicular to the thickness direction of the semiconductor substrate 1 and parallel to the second main surface 5, and an outer end portion connected to the flat portion 13a and an inner end portion being connected to the second main surface 5. It has an inclined portion 13b to reach.

Subsequently, a method of manufacturing the semiconductor device according to the embodiment will be described. 3 to 9 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment. The drawing on the left side of each drawing shows a cross-sectional view of the wafer, and the right side is a cross-sectional view of one chip extracted.

First, as shown in FIG. 3, a semiconductor substrate 1 in a wafer state is prepared. Since the donor concentration of the semiconductor substrate 1 becomes the donor concentration of the drift layer as it is, an n-type semiconductor substrate 1 corresponding to the donor concentration of the drift layer is prepared.

Next, a mask is formed on the first main surface 4 of the semiconductor substrate 1 and patterned by a photoengraving process. By injecting impurities into the first main surface 4 of the semiconductor substrate 1 through this mask, the anode layer 6 is formed in the cell region 2, and the second conductive type well layer 7 is formed in the peripheral pressure resistant region 3.

Next, in the peripheral pressure resistant region 3, the insulating film 9 is deposited on the first main surface 4 by CVD (chemical vaper deposition) or the like. The processing time is adjusted so that the thickness of the insulating film 9 becomes Td. Next, the insulating film 9 is etched using the mask pattern formed by the photoengraving process to form an opening in the cell region 2.

Next, in the cell region 2, an anode electrode 8 having a thickness Ta connected to the anode layer 6 is formed on the first main surface 4. The anode electrode 8 covers the end portion of the insulating film 9 on the cell region 2 side.

Next, a first protective film 10 that covers the end of the anode electrode 8 is formed on the insulating film 9 of the peripheral pressure resistant region 3. The processing conditions and materials such as time and rotation speed are adjusted so that the thickness of the first protective film 10 becomes Tb.

Next, as shown in FIG. 4, in the peripheral pressure resistant region 3, a second protective film made of tape, resin, or the like is placed on the first main surface 4 so as to cover the anode electrode 8 and the first protective film 10. Form 14. Since the upper surface of the first protective film 10 is higher than the upper surface of the anode electrode 8, there is a height difference Tb + Td between the anode electrode 8 and the first protective film 10. The processing conditions such as time and rotation speed, the tape thickness, and the material are adjusted so that the thickness Tc of the second protective film 14 satisfies Tc> Tb + Td. On the surface of the second protective film 14, a step is formed according to the height difference between the anode electrode 8 and the first protective film 10.

Next, the second main surface 5 of the semiconductor substrate 1 is cut while the surface of the second protective film 14 having a step is pressed by the flat jig 15. The surface of the second protective film 14 may be pressed flat, and may be pressed by a grinding device integrally provided with the same flat portion as the jig 15. The second protective film 14 pressed by the jig 15 is maintained flat, and the semiconductor substrate 1 is distorted accordingly. After that, the jig 15 is removed to release the second protective film 14 from being kept flat. As a result, as shown in FIG. 5, a step corresponding to the step of the second protective film 14 is formed on the second main surface 5 of the semiconductor substrate 1. In the second main surface 5, the cell region 2 is convex and the peripheral pressure resistant region 3 is concave.

Experimentally, the step amount Tdi of the second main surface 5 was 0.6 times the step amount of the first main surface 4. That is, Tdi> 0.6 (Tb + Td). Further, assuming that the initial thickness of the semiconductor substrate 1 is T0 and the substrate thickness of the cell region 2 after grinding is Tci, the grinding amount of the cell region 2 is Tgci = T0-Tci. Assuming that the substrate thickness of the peripheral pressure resistant region 3 after grinding is Tpi, the grinding amount of the peripheral pressure resistant region 3 is Tgpi = T0-Tpi. Therefore, Tdi = Tgpi-Tgci = Tci-Tpi> 0.6 × (Tb + Td)> 0.

Next, as shown in FIG. 6, the second main surface 5 having a step is irradiated with light ions such as He and H, and the LTC layer 13 extends from the second main surface 5 of the semiconductor substrate 1 to a region having a depth of D1 ct. To form.

Next, as shown in FIG. 7, the surface of the second protective film 14 is ground and flattened. At this point, the second main surface 5 has a step.

Next, as shown in FIG. 8, the second main surface 5 of the semiconductor substrate 1 is ground while the surface of the flattened second protective film 14 is pressed by the jig 15, and the LTC of the cell region 2 is obtained. The layer 13 is removed. Here, if the cutting amount in the cell region is Tgcf and the cutting amount in the peripheral pressure resistant region is Tgpf, then Tgcf> Tgpf.

Next, when the second protective film 14 is made of tape, the second protective film 14 is removed by using a tape peeling device. When the second protective film 14 is made of a resin, the second protective film 14 is removed by ashing with oxygen plasma, an alkaline solvent, or an organic solvent.

Next, as shown in FIG. 9, the LTC layer 13 is heat-treated to adjust. An n ⁺ type cathode layer 11 is formed on the second main surface 5 of the semiconductor substrate 1 by injecting impurities or the like. The cathode electrode 12 connected to the cathode layer 11 is formed by using metal sputtering or the like. After that, the semiconductor device according to the present embodiment is manufactured by cutting the wafer for each chip.

As described above, in the present embodiment, there is a step on the surface of the second protective film 14 due to the height difference between the first protective film 10 formed in the peripheral pressure resistant region 3 and the anode electrode 8 formed in the cell region 2. To form. With this surface pressed by the jig 15, the second main surface 5 of the semiconductor substrate 1 is ground to form a step. The second main surface 5 having a step is irradiated with light ions to form the LTC layer 13. Then, the surface of the second protective film 14 is ground to be flat, and the second main surface 5 is ground while being pressed by the jig 15 to remove the LTC layer 13 of the cell region 2.

As a result, the LTC layer 13 is self-aligned with respect to the first protective film 10, so that the displacement from the peripheral pressure resistant region 3 can be suppressed. Therefore, it is possible to suppress variation and decrease in the recovery capacity of the peripheral pressure resistant region 3.

Further, the amount of carriers injected from the second main surface 5 side increases as the amount of carriers supplied from the first main surface 4 side of the cell region 2 increases. Therefore, the closer to the cell region 2, the more heat is generated by the carrier recombination in the LTC layer 13. On the other hand, in the present embodiment, the inclined portion 13b of the LTC layer 13 approaches the second main surface 5 as it is closer to the cell region 2. Therefore, even if heat is generated in the LTC layer 13 near the cell region 2, the distance to the second main surface 5 is short and the thermal resistance is small, so that heat can be efficiently dissipated.

The depth of the LTC layer 13 is determined by process parameters such as effective mass of irradiated particles, radius, irradiation energy, and absorber thickness. Therefore, when the irradiation surface is flat, the LTC layer 13 is formed only at a certain depth from the second main surface. On the other hand, in the present embodiment, the height difference between the anode electrode 8 and the first protective film 10 is used to form a step on the second main surface 5, so that a single ion irradiation can be performed locally. The LTC layers 13 having different depths can be formed.

The film thickness Tc of the second protective film 14 is larger than the height difference (Tb + Td) between the anode electrode 8 and the first protective film 10 (Tc> Tb + Td). As a result, the LTC layer 13 can be formed without damaging the element structure formed on the first main surface 4 side.

The thickness Tb of the first protective film 10 is preferably thicker than the thickness Td of the insulating film 9 (Tb> Td). As a result, the height difference between the anode electrode 8 and the first protective film 10 becomes large, so that a step can be formed on the second main surface 5.

Since the carriers injected into the peripheral withstand voltage region 3 are recombinated in the LTC layer 13, the tail current can be suppressed. Further, since the LTC layer 13 is not formed in the cell region 2, the on-resistance can be reduced.

The semiconductor substrate 1 is not limited to the one formed of silicon, and may be formed of a wide bandgap semiconductor having a larger bandgap than silicon. The wide bandgap semiconductor is, for example, silicon carbide, gallium nitride based material, or diamond. A semiconductor device formed of such a wide bandgap semiconductor has high withstand voltage resistance and allowable current density, and thus can be miniaturized. By using this miniaturized semiconductor device, the semiconductor module incorporating this semiconductor device can also be miniaturized and highly integrated. Further, since the heat resistance of the semiconductor device is high, the heat radiation fins of the heat sink can be miniaturized, and the water-cooled portion can be air-cooled, so that the semiconductor module can be further miniaturized. Further, since the power loss of the semiconductor device is low and the efficiency is high, the efficiency of the semiconductor module can be improved.

1 Semiconductor substrate, 2 cell region, 3 peripheral withstand voltage region, 4 1st main surface, 5th main surface, 6 anode layer, 7 well layer, 8 anode electrode (electrode), 9 insulating film, 10 first protective film , 11 cathode layer, 13 LTC layer (lifetime control layer), 13a flat part, 13b inclined part, 14 second protective film, 15 jig

Claims (6)

A step of preparing a first conductive type semiconductor substrate having a cell region and a peripheral pressure resistant region surrounding the cell region in a plan view.
A step of forming a second conductive type anode layer on the first main surface of the semiconductor substrate in the cell region, and a step of forming the second conductive type anode layer.
A step of forming a second conductive type well layer on the first main surface of the semiconductor substrate in the peripheral pressure resistant region,
A step of forming a first conductive type cathode layer on the second main surface of the semiconductor substrate on the side opposite to the first main surface, and
A step of forming an electrode connected to the anode layer on the first main surface in the cell region, and a step of forming the electrode.
A step of forming a first protective film having an upper surface higher than the upper surface of the electrode on the first main surface in the peripheral pressure resistant region.
A step of covering the electrode and the first protective film and forming a second protective film having a first step on the surface according to the height difference between the electrode and the first protective film.
While the surface having the first step is pressed down, the second main surface of the semiconductor substrate is ground to form a second step corresponding to the first step on the second main surface. Process and
A step of irradiating the second main surface having the second step with light ions to form a lifetime control layer, and a step of forming the lifetime control layer.
The step of grinding and flattening the surface of the second protective film,
Manufacture of a semiconductor device comprising a step of grinding the second main surface of the semiconductor substrate while pressing the flattened surface to remove the lifetime control layer in the cell region. Method. The method for manufacturing a semiconductor device according to claim 1, wherein the film thickness of the second protective film is larger than the height difference between the electrode and the first protective film. Further comprising a step of forming an insulating film on the first main surface in the peripheral pressure resistant region.
The electrode covers the end of the insulating film on the cell region side.
The first protective film is formed on the insulating film and covers the end portion of the electrode.
The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the thickness of the first protective film is thicker than the thickness of the insulating film. A first conductive type semiconductor substrate having a cell region and a peripheral pressure resistant region surrounding the cell region in a plan view.
A second conductive type anode layer formed on the first main surface of the semiconductor substrate in the cell region, and
A second conductive type well layer formed on the first main surface of the semiconductor substrate in the peripheral pressure resistant region,
A first conductive type cathode layer formed on the second main surface of the semiconductor substrate on the side opposite to the first main surface, and
It is provided with a lifetime control layer formed in the peripheral pressure resistant region and irradiated with light ions.
The lifetime control layer is characterized by having a flat portion parallel to the second main surface and an inclined portion in which an outer end portion is connected to the flat portion and an inner end portion reaches the second main surface. Semiconductor device. The semiconductor device according to claim 4, wherein the lifetime control layer is not formed in the cell region. The semiconductor device according to claim 4 or 5, wherein the semiconductor substrate is formed of a wide bandgap semiconductor.

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