JP2022000872A - Optical semiconductor device - Google Patents

Abstract

To provide an optical semiconductor device that can contribute to manufacturing efficiency improvement of the device while downsizing the device.SOLUTION: An optical semiconductor device A10 comprises: an optical semiconductor element 30 that has an optical surface 302 facing to a second direction x being orthogonal to a first direction and a pair of side surfaces 303 facing to opposite sides each other in a third direction y; and a first insulation layer 10 that has a first rear surface 102 facing to the first direction and a first end surface 103 facing to the same side as the optical surface 302 in the second direction x, and that covers a part of the optical semiconductor element 30. In the first insulation layer 10, an opening 12 that penetrates through the first end surface 103 and that exposes an optical region 33 of the optical semiconductor element 30 is formed. The first insulation layer 10 has a pair of opening edges 121 that are positioned being apart from each other in the third direction y, that are connected to the first rear surface 102, and that define the opening 12. The pair of opening edges 121 contact with the optical surface 302 and either of the pair of side surfaces 303.SELECTED DRAWING: Figure 8

Description

The present invention relates to an optical semiconductor device equipped with an optical semiconductor device that emits light or receives light from the outside.

With the miniaturization of electronic devices in recent years, the miniaturization of optical semiconductor devices used in the electronic devices has been promoted. In response to these trends, an optical semiconductor device including an insulating layer in which a wiring layer is arranged and an optical semiconductor element partially covered with the insulating layer is known. By adopting such a configuration, the size of the device can be reduced.

Patent Document 1 discloses an example of such an optical semiconductor device. The optical semiconductor element of the apparatus has an optical region in which light is emitted or incident. The insulating layer of the device is formed with an opening for exposing the optical region from the insulating layer. In order to form the opening in order to reduce the size of the device, it is necessary to form a mask layer covering the optical region. The mask layer needs to be removed in the process of forming the openings. Therefore, there is a problem that the manufacturing efficiency of the device is lowered.

Japanese Unexamined Patent Publication No. 2019-216242

In view of the above circumstances, it is an object of the present invention to provide an optical semiconductor device capable of contributing to an improvement in manufacturing efficiency of the device while reducing the size of the device.

The optical semiconductor device provided by the present invention includes a main surface facing the first direction, an optical surface facing the second direction orthogonal to the first direction and connected to the main surface, the first direction and the optical surface. An optical semiconductor element having a main surface and a pair of side surfaces connected to the optical surface and facing each other in a third direction orthogonal to both of the second directions, and the main surface in the first direction. The first main surface facing the same side as the surface, the first back surface facing the opposite side of the first main surface in the first direction, the first main surface and the first back surface connected to the second surface. It has a first end face that faces the same side as the optical surface in the direction and includes a first insulating layer that covers a part of the optical semiconductor element, and the optical surface emits light or emits light. The first insulating layer has an incident optical region, and an opening is formed in the first insulating layer to penetrate the first end surface and expose the optical region, and the first insulating layers are separated from each other in the third direction. And has a pair of opening edges that are connected to the first back surface and define the opening, and the pair of opening edges are in contact with either the optical surface and the pair of side surfaces. It is characterized by.

In the practice of the present invention, preferably, the pair of opening edges are in contact with the optical surface, the first insulating layer is located apart from each other in the third direction, and the pair of connecting surfaces connected to the first end surface. The pair of connecting surfaces individually include the pair of opening edges, and each of the pair of connecting surfaces is inclined with respect to the first end surface.

In the practice of the present invention, the pair of connecting surfaces are preferably connected to the first main surface.

In the practice of the present invention, the first insulating layer is preferably located between the first main surface and the optical semiconductor element in the first direction, and on the first end surface and the pair of connecting surfaces. It has an intermediate surface to be connected, and the intermediate surface includes an edge in contact with the optical semiconductor element.

In the practice of the present invention, the pair of opening edges are preferably in contact with the pair of side surfaces, and in the second direction, the first end surface is located inside the optical semiconductor device with respect to the optical surface.

Preferably, in practicing the present invention, the first end face comprises the pair of open edges.

In the practice of the present invention, the first insulating layer is preferably located on the side opposite to the first end surface with respect to the optical surface in the second direction, and is the same as the first end surface in the second direction. It has an overhanging surface facing side, an intermediate surface located between the first main surface and the optical semiconductor element in the first direction, and an intermediate surface connected to the overhanging surface and the first end surface. The surface includes an edge in contact with the optical semiconductor element.

In the practice of the present invention, the intermediate surface preferably faces the same side as the first back surface in the first direction and is connected to the first end surface, and the first intermediate surface in the second direction. It has a second intermediate surface connected to a surface, and the second intermediate surface includes the edge and is inclined with respect to the first intermediate surface.

In the practice of the present invention, the intermediate surface preferably faces the same side as the first back surface in the first direction and is connected to the overhanging surface, and the first intermediate surface in the second direction. The second intermediate surface includes the edge and is inclined with respect to the first intermediate surface.

In the practice of the present invention, the second intermediate surface is preferably curved inward of the first insulating layer.

In the practice of the present invention, preferably, in the second direction, the edge is located inside the optical semiconductor device with respect to the optical surface.

In the practice of the present invention, the optical semiconductor device preferably includes a first electrode provided on the main surface and a second electrode provided on the opposite side of the first electrode in the first direction. The first wiring layer connected to the first electrode and arranged on the side where the first main surface is located with respect to the optical semiconductor element in the first direction, and connected to the second electrode and described above. Further, a second wiring layer arranged on the side where the first back surface is located with respect to the optical semiconductor element in the first direction is further provided, and the first wiring layer is in contact with the first insulating layer.

In the practice of the present invention, the first insulating layer preferably has a first penetrating portion extending from the first main surface to the first electrode, and the first wiring layer is housed in the first penetrating portion. It also has a first connecting portion connected to the first electrode and a first main portion connected to the first connecting portion and arranged on the first main surface.

In the practice of the present invention, it is preferable that the second main surface and the second back surface facing each other in the first direction, the first main surface and the first back surface are connected to each other, and the first surface is connected in the second direction. It has a second end surface facing the same side as the end surface, and further includes a second insulating layer in which the second back surface is arranged in contact with the first back surface, and the second wiring layer is the second insulating layer. The second insulating layer is formed with a recess that is recessed from the second end surface toward the second direction, and the recess is connected to the opening.

In the practice of the present invention, the second insulating layer preferably has a second penetrating portion extending from the second main surface to the second electrode, and the second wiring layer is housed in the second penetrating portion. It also has a second connecting portion connected to the second electrode and a second connecting portion connected to the second connecting portion and arranged on the second main surface, and is viewed along the first direction. Therefore, at least a part of the second main portion overlaps with the first main portion.

In the practice of the present invention, the optical semiconductor device is preferably a laser diode, has a source electrode and a drain electrode, and has a switching element in which at least a part thereof is covered with the first insulating layer, and in the first direction. A third wiring layer arranged on the side where the first back surface is located with respect to the optical semiconductor element is further provided, the source electrode conducts to the first wiring layer, and the drain electrode conducts the third wiring. Conducting to the layer.

In carrying out the present invention, it is preferable to further include a translucent resin that covers at least a part of the first insulating layer, and the translucent resin covers the optical region and closes the opening.

According to the optical semiconductor device according to the present invention, it is possible to contribute to the improvement of the manufacturing efficiency of the device while reducing the size of the device.

Other features and advantages of the present invention will be more apparent by the detailed description given below based on the accompanying drawings.

It is a top view of the optical semiconductor device which concerns on 1st Embodiment of this invention, and is transmitted through a plurality of capacitors, a conductive bonding layer, and a translucent resin. It is a plan view corresponding to FIG. 1, and is further transmitted through the first insulating layer and the protective layer. It is a bottom view of the optical semiconductor device shown in FIG. 1, and is transparent to a translucent resin. It is sectional drawing which follows the IV-IV line of FIG. It is sectional drawing which follows the VV line of FIG. It is a partially enlarged view of FIG. It is a partially enlarged view of FIG. It is a partially enlarged view of FIG. It is a left side view corresponding to FIG. FIG. 3 is a cross-sectional view taken along the line XX of FIG. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is a partially enlarged view of FIG. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is a partially enlarged view of FIG. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is a partially enlarged view of FIG. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is a partially enlarged view of FIG. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is sectional drawing explaining the manufacturing process of the optical semiconductor device shown in FIG. 1. It is a circuit diagram of the semiconductor light emitting module equipped with the optical semiconductor device shown in FIG. 1. It is a partially enlarged plan view of the optical semiconductor device which concerns on 2nd Embodiment of this invention, and is transmitted through a plurality of capacitors, a conductive bonding layer, and a translucent resin. It is a left side view corresponding to FIG. 26. FIG. 6 is a cross-sectional view taken along the line XXVIII-XXVIII of FIG. 26. It is a partially enlarged plan view of the optical semiconductor device which concerns on 3rd Embodiment of this invention, and is transmitted through a plurality of capacitors, a conductive bonding layer, and a translucent resin. It is a left side view corresponding to FIG. 29. FIG. 9 is a cross-sectional view taken along the line XXXI-XXXI of FIG. 29. It is a partially enlarged plan view of the optical semiconductor device which concerns on 4th Embodiment of this invention, and is transmitted through a plurality of capacitors, a conductive bonding layer, and a translucent resin. It is a left side view corresponding to FIG. 32. FIG. 3 is a cross-sectional view taken along the line XXXIV-XXXIV of FIG. 32. It is a top view of the optical semiconductor device which concerns on 5th Embodiment of this invention, and is transmitted through a plurality of capacitors, a conductive bonding layer, and a translucent resin. FIG. 3 is a cross-sectional view taken along the line XXXVI-XXXVI of FIG. 35. It is a partially enlarged view of FIG. 35. It is a left side view corresponding to FIG. 37. FIG. 3 is a cross-sectional view taken along the line XXXIX-XXXIX of FIG. 37.

The embodiment for carrying out the present invention will be described with reference to the accompanying drawings.

[First Embodiment]
The optical semiconductor device A10 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 10. The optical semiconductor device A10 includes an optical semiconductor element 30, a first insulating layer 10, a protective layer 29, a first wiring layer 41, a second wiring layer 42, a third wiring layer 43, a switching element 37, a plurality of capacitors 38, and a first. It includes a terminal 51, a second terminal 52, a third terminal 53, a fourth terminal 54, and a translucent resin 60. The optical semiconductor device A10 is surface-mounted on the wiring board of various modules. In the optical semiconductor device A10, when the switching element 37 is driven, the optical semiconductor element 30 emits light in a pulse shape at intervals of several ns. By using such an optical semiconductor device A10, it is possible to search for an object located at a relatively long distance, as in the case of searching using a laser, for example. Such exploration technology is called LiDAR (Laser Imaging Detection and Ranging). Here, for convenience of understanding, FIG. 1 transmits a plurality of capacitors 38, a conductive bonding layer 39 (details will be described later), and a translucent resin 60. FIG. 2 further penetrates the first insulating layer 10 and the protective layer 29 with respect to FIG. 1 for convenience of understanding. In FIG. 1, a plurality of transmitted capacitors 38 and a translucent resin 60 are shown by an imaginary line (dashed-dotted line). In FIG. 2, the transmitted first insulating layer 10 and the translucent resin 60 are shown by imaginary lines. FIG. 10 omits the illustration of the plurality of capacitors 38 and the conductive bonding layer 39.

In the description of the optical semiconductor device A10, the thickness direction of the first insulating layer 10 is referred to as "first direction z". The direction orthogonal to the first direction z is called "second direction x". The direction orthogonal to both the first direction z and the second direction x is referred to as a "third direction y". As shown in FIG. 1, the outer shape of the optical semiconductor device A10 is rectangular when viewed along the first direction z.

The optical semiconductor element 30 is a semiconductor element that emits light or receives light from the outside. In the optical semiconductor device A10, the optical semiconductor element 30 is a laser diode. However, the optical semiconductor element 30 is not limited to the laser diode, and various semiconductor elements can be used depending on the function of the optical semiconductor device A10. As shown in FIGS. 8 and 9, the optical semiconductor device 30 has a main surface 301, an optical surface 302, a pair of side surface 303s, a back surface 304, a first electrode 31 and a second electrode 32.

As shown in FIG. 10, the main surface 301 faces the first direction z. In the optical semiconductor element 30, the main surface 301 is included in the semiconductor layer laminated on the semiconductor substrate. When the optical semiconductor device A10 is mounted on the wiring board, the main surface 301 faces the wiring board. Therefore, the posture of the optical semiconductor element 30 in the optical semiconductor device A10 is in the form of a face-down in which a semiconductor layer is laminated with respect to the semiconductor substrate toward the wiring board. As shown in FIG. 8, the optical surface 302 faces the second direction x and is connected to the main surface 301. The pair of side surfaces 303 face each other in the third direction y and are connected to the main surface 301 and the optical surface 302. The back surface 304 faces the side opposite to the optical surface 302 in the second direction x, and is connected to the main surface 301 and the pair of side surfaces 303. As shown in FIGS. 9 and 10, the first electrode 31 is provided on the main surface 301. The first electrode 31 is the anode of the optical semiconductor device 30. The second electrode 32 is provided on the side opposite to the first electrode 31 in the first direction z. The second electrode 32 is the cathode of the optical semiconductor element 30.

As shown in FIGS. 9 and 10, the optical surface 302 has an optical region 33. On the optical surface 302, the optical region 33 is a region that emits light or is incident with light. In the optical semiconductor device A10, light is emitted from the optical region 33.

As shown in FIGS. 1 and 4, the first insulating layer 10 covers a part of the optical semiconductor element 30. The first insulating layer 10 is a thermosetting synthetic resin and a part of each of the first wiring layer 41, the first terminal 51, the second terminal 52, the third terminal 53, and the fourth terminal 54 (underlying layer described later). It is composed of a material containing 401 and an additive containing a metal element constituting the base layer 501). The synthetic resin is, for example, an epoxy resin or a polyimide. As shown in FIGS. 9 and 10, in the optical semiconductor device A10, the first insulating layer 10 has a first main surface 101, a first back surface 102, a first end surface 103, and a pair of connecting surfaces 104.

As shown in FIG. 10, the first main surface 101 faces the same side as the main surface 301 of the optical semiconductor element 30 in the first direction z. The first back surface 102 faces the side opposite to the first main surface 101 in the first direction z. As shown in FIGS. 8 and 9, the first end surface 103 is connected to the first main surface 101 and the first back surface 102, and faces the same side as the optical surface 302 of the optical semiconductor element 30 in the second direction x. The pair of connecting surfaces 104 are located apart from each other in the third direction y and are connected to the first end surface 103. Each of the pair of connecting surfaces 104 is inclined toward the optical surface 302 with respect to the first end surface 103. Further, in the optical semiconductor device A10, the pair of connecting surfaces 104 are connected to the first main surface 101.

As shown in FIGS. 8 and 9, an opening 12 is formed in the first insulating layer 10. The opening 12 penetrates the first end surface 103 and exposes the optical region 33 of the optical semiconductor device 30. Further, the first insulating layer 10 has a pair of opening edges 121 that define the opening 12. The pair of opening edges 121 are located apart from each other in the third direction y and are connected to the first back surface 102. In the optical semiconductor device A10, the pair of aperture edges 121 are in contact with the optical surface 302 of the optical semiconductor element 30. The pair of connecting surfaces 104 individually include a pair of opening edges 121. In the optical semiconductor device 30, the first electrode 31, the pair of side surfaces 303, and the back surface 304 are covered with the first insulating layer 10. The second electrode 32 is exposed from the first insulating layer 10 on the first back surface 102.

As shown in FIGS. 4 and 6, the first insulating layer 10 has a plurality of first penetrating portions 11. Each of the plurality of first penetration portions 11 reaches either the first electrode 31 of the optical semiconductor element 30 or the source electrode 372 of the switching element 37 (details will be described later) from the first main surface 101 in the first direction z. There is. Each of the plurality of first penetration portions 11 is defined by any one of the plurality of inner peripheral surfaces 111 of the first insulating layer 10. Each of the plurality of inner peripheral surfaces 111 is inclined with respect to the first main surface 101. Each of the plurality of inner peripheral surfaces 111 is directed to the inside of any of the plurality of first penetrating portions 11 defined by the inner peripheral surface 111 from the first main surface 101 to the first back surface 102 in the first direction z. Take a fallen posture. Therefore, the cross-sectional area of each of the plurality of first penetrating portions 11 with respect to the first direction z gradually becomes smaller toward the first main surface 101 and the first back surface 102.

As shown in FIGS. 1 and 4, at least a part of the switching element 37 is covered with the first insulating layer 10. The switching element 37 is located away from the optical semiconductor element 30 in the second direction x. In the optical semiconductor device A10, the switching element 37 is a MOSFET (metal-oxide-semiconductor field-effect transistor) having a vertical structure. As shown in FIGS. 4 and 5, the switching element 37 has a drain electrode 371, a source electrode 372 and a gate electrode 373. The drain electrode 371 is provided closest to the first back surface 102 of the first insulating layer 10. The drain electrode 371 is exposed from the first insulating layer 10 on the first back surface 102. The source electrode 372 and the gate electrode 373 are provided on the opposite side of the drain electrode 371 in the first direction z.

As shown in FIG. 4, the first wiring layer 41 is arranged on the side where the first main surface 101 of the first insulating layer 10 is located with respect to the optical semiconductor element 30 in the first direction z. The first wiring layer 41 is connected to the first electrode 31 of the optical semiconductor element 30 and the source electrode 372 of the switching element 37. As a result, the first wiring layer 41 is conductive to both the first electrode 31 and the source electrode 372. The first wiring layer 41 is in contact with the first insulating layer 10. As shown in FIGS. 2 and 4, the first wiring layer 41 has a first main unit 411 and a plurality of first communication units 412. Each of the plurality of first connecting portions 412 is housed in any of the plurality of first penetrating portions 11 of the first insulating layer 10 and is connected to either the first electrode 31 and the source electrode 372. The first main unit 411 is arranged on the first main surface 101 and is connected to a plurality of first communication units 412.

As shown in FIG. 6, each of the first main portion 411 and the plurality of first connecting portions 412 includes a base layer 401 and a plating layer 402. The base layer 401 is composed of a metal element contained in the additive contained in the first insulating layer 10. The base layer 401 is in contact with the first insulating layer 10. Each of the plurality of inner peripheral surfaces 111 of the first insulating layer 10 is covered with a base layer 401 forming each of the plurality of first connecting portions 412. The plating layer 402 covers the base layer 401. The plating layer 402 is made of a material containing, for example, copper (Cu).

As shown in FIGS. 4 and 5, the second wiring layer 42 is arranged on the side where the first back surface 102 of the first insulating layer 10 is located with respect to the optical semiconductor element 30 in the first direction z. In the optical semiconductor device A10, the second wiring layer 42 is arranged on the first back surface 102 and is in contact with the first insulating layer 10. The second wiring layer 42 is connected to the second electrode 32 of the optical semiconductor element 30. As a result, the second wiring layer 42 is conductive to the second electrode 32. The second wiring layer 42 is made of, for example, a metal thin film containing copper.

As shown in FIGS. 4 and 5, the third wiring layer 43 is arranged on the side where the first back surface 102 of the first insulating layer 10 is located with respect to the optical semiconductor element 30 in the first direction z. In the optical semiconductor device A10, the third wiring layer 43 is arranged on the first back surface 102 and is in contact with the first insulating layer 10. The third wiring layer 43 is located away from the second wiring layer 42. The third wiring layer 43 is connected to the drain electrode 371 of the switching element 37. As a result, the third wiring layer 43 is conducting to the drain electrode 371. The third wiring layer 43 is made of, for example, a metal thin film containing copper.

The plurality of capacitors 38 temporarily store electric charges corresponding to the voltage applied to the optical semiconductor element 30 when the optical semiconductor device A10 is used. As shown in FIGS. 4 and 5, each of the plurality of capacitors 38 is arranged on the side where the first back surface 102 of the first insulating layer 10 is located in the first direction z. Each of the plurality of capacitors 38 is not covered with the first insulating layer 10. Each of the plurality of capacitors 38 is, for example, a ceramic capacitor. Each of the plurality of capacitors 38 has a pair of electrodes 381. One of the pair of electrodes 381, the electrode 381, is bonded to the second wiring layer 42 via the conductive bonding layer 39. The other electrode 381 of the pair of electrodes 381 is bonded to the third wiring layer 43 via the conductive bonding layer 39. The conductive bonding layer 39 is, for example, lead-free solder. As a result, the second electrode 32 of the optical semiconductor element 30 and the drain electrode 371 of the switching element 37 are electrically connected to each other via the second wiring layer 42, the plurality of capacitors 38, and the third wiring layer 43. The optical semiconductor device A10 is configured to include two capacitors 38, but the number of capacitors 38 is not limited to this, and may be, for example, a single capacitor 38.

As shown in FIGS. 4 and 5, the protective layer 29 covers the first main surface 101 of the first insulating layer 10 and the first main portion 411 of the first wiring layer 41. The protective layer 29 has electrical insulation. The protective layer 29 is made of the same material as the first insulating layer 10. The protective layer 29 has a mounting surface 291. The mounting surface 291 faces the same side as the first main surface 101 in the first direction z. When the optical semiconductor device A10 is mounted on a wiring board, the mounting surface 291 corresponds to the wiring board. The dimension (thickness) of the protective layer 29 in the first direction z is smaller than the dimension (thickness) of the first insulating layer 10 in the first direction z.

The first terminal 51 is connected to the third wiring layer 43 as shown in FIGS. 2, 3 and 5. As a result, the first terminal 51 is electrically connected to the drain electrode 371 of the switching element 37 and each of the plurality of capacitors 38. The first terminal 51 has a first base portion 511 and a plurality of first embedded portions 512. The first base portion 511 is arranged on the mounting surface 291 of the protective layer 29 and is in contact with the protective layer 29. Each of the plurality of first embedded portions 512 reaches from the mounting surface 291 to the first back surface 102 of the first insulating layer 10 in the first direction z, and is in contact with both the protective layer 29 and the first insulating layer 10. Embedded in these. Each of the plurality of first embedded portions 512 is connected to the first base portion 511 and the third wiring layer 43.

The second terminal 52 is connected to the second wiring layer 42 as shown in FIGS. 2, 3 and 5. As a result, the second terminal 52 is electrically connected to the second electrode 32 of the optical semiconductor element 30 and each of the plurality of capacitors 38. The second terminal 52 has a second base portion 521 and a plurality of second embedded portions 522. The second base portion 521 is arranged on the mounting surface 291 of the protective layer 29 and is in contact with the protective layer 29. Each of the plurality of second embedded portions 522 reaches from the mounting surface 291 to the first back surface 102 of the first insulating layer 10 in the first direction z, and is in contact with both the protective layer 29 and the first insulating layer 10. Embedded in these. Each of the plurality of second embedded portions 522 is connected to the second base portion 521 and the second wiring layer 42.

As shown in FIGS. 3 and 5, the third terminal 53 is connected to the gate electrode 373 of the switching element 37. As a result, the third terminal 53 is electrically connected to the gate electrode 373. The third terminal 53 has a third base portion 531 and a third embedded portion 532. The third base portion 531 is arranged on the mounting surface 291 of the protective layer 29 and is in contact with the protective layer 29. The third embedded portion 532 extends from the mounting surface 291 to the gate electrode 373 in the first direction z, and is embedded in the protective layer 29 and the first insulating layer 10 in contact with both of them. The third embedded portion 532 is connected to the third base portion 531 and the gate electrode 373.

As shown in FIGS. 3 and 4, the fourth terminal 54 is connected to the source electrode 372 of the switching element 37. As a result, the fourth terminal 54 is conductive to the source electrode 372 and to the first electrode 31 of the optical semiconductor element 30 via the first wiring layer 41. The fourth terminal 54 has a fourth base portion 541 and a plurality of fourth embedded portions 542. The fourth base portion 541 is arranged on the mounting surface 291 of the protective layer 29 and is in contact with the protective layer 29. Each of the plurality of fourth embedded portions 542 extends from the mounting surface 291 to the source electrode 372 in the first direction z and is embedded in the protective layer 29 and the first insulating layer 10 in contact with each other. .. Each of the plurality of fourth embedded portions 542 is connected to the fourth base portion 541 and the source electrode 372.

Each of the first terminal 51, the second terminal 52, the third terminal 53, and the fourth terminal 54 includes the base layer 501 and the plating layer 502 shown in FIG. 7. The underlayer 501 is composed of metal elements contained in the additives contained in each of the first insulating layer 10 and the protective layer 29. The base layer 501 is in contact with both the first insulating layer 10 and the protective layer 29. The plating layer 502 covers the base layer 501. The underlayer 501 is made of, for example, a material containing copper.

As shown in FIGS. 4 and 5, the translucent resin 60 covers the first insulating layer 10, the second wiring layer 42, the third wiring layer 43, the plurality of capacitors 38, and a part of the protective layer 29. ing. Further, the translucent resin 60 covers the optical region 33 of the optical semiconductor element 30 and closes the opening 12 formed in the first insulating layer 10. The translucent resin 60 has a property of transmitting light. The light transmittance of the translucent resin 60 is preferably 80% or more. The translucent resin 60 is made of, for example, a transparent epoxy resin.

Next, an example of a method for manufacturing the optical semiconductor device A10 will be described with reference to FIGS. 11 to 24. Here, the cross-sectional positions of FIGS. 11 to 24 (excluding FIGS. 13, 15, 18 and 20) are the same as the cross-sectional positions of FIG.

First, as shown in FIG. 11, the optical semiconductor element 30 and the switching element 37 are embedded in the insulating layer 81. The insulating layer 81 is made of the same material as the first insulating layer 10. The insulating layer 81 has a main surface 81A and a back surface 81B facing opposite sides in the first direction z. In this step, after arranging the material of the insulating layer 81, the optical semiconductor element 30 and the switching element 37 in the mold, compression molding is performed. As a result, the optical semiconductor element 30 and the switching element 37 are embedded in the insulating layer 81. At this time, the second electrode 32 of the optical semiconductor element 30 and the drain electrode 371 of the switching element 37 are exposed from the insulating layer 81 on the back surface 81B. Further, it is assumed that the optical surface 302 of the optical semiconductor element 30, the first electrode 31 of the optical semiconductor element 30, the source electrode 372 and the gate electrode 373 of the switching element 37 are covered with the insulating layer 81.

Next, as shown in FIGS. 12 to 15, a first wiring layer 41 connected to the first electrode 31 of the optical semiconductor element 30 and the source electrode 372 of the switching element 37 is formed. The step of forming the first wiring layer 41 includes a step of precipitating the base layer 401 on the insulating layer 81 and a step of forming a plating layer 402 covering the base layer 401.

First, as shown in FIG. 13, the base layer 401 is deposited on the insulating layer 81. The base layer 401 is composed of a metal element contained in the additive contained in the insulating layer 81. In this step, as shown in FIG. 12, a plurality of penetration portions 811 are formed in the insulating layer 81. Each of the plurality of penetration portions 811 reaches either the first electrode 31 of the optical semiconductor element 30 or the source electrode 372 of the switching element 37 from the main surface 81A of the insulating layer 81. The plurality of penetrating portions 811 are formed by irradiating the insulating layer 81 with a laser while recognizing the positions of the first electrode 31 and the source electrode 372 by an infrared camera. At this time, the irradiation position of the laser in the insulating layer 81 is corrected one by one based on the position information of each of the first electrode 31 and the source electrode 372 obtained by image recognition. The laser is an ultraviolet laser having a wavelength of 355 nm and a beam diameter of 17 μm. The main surface 81A is patterned by the laser in accordance with the formation of the plurality of penetrating portions 811. The patterning is such that it leads to a plurality of penetrations 811. By irradiating the insulating layer 81 with a laser, the metal element contained in the additive contained in the insulating layer 81 is excited. As a result, a base layer 401 that covers the plurality of inner peripheral surfaces 811A that individually define the plurality of penetrating portions 811 and the main surface 81A is formed.

Next, as shown in FIG. 15, a plating layer 402 that covers the base layer 401 is formed. The plating layer 402 is made of a material containing copper. The plating layer 402 is formed by electroless plating, electrolytic plating, or a combination thereof. As a result, as shown in FIG. 14, one of the plurality of first connecting portions 412 of the first wiring layer 41 is formed in each of the plurality of penetrating portions 811 of the insulating layer 81. At the same time, the first main portion 411 of the first wiring layer 41 is formed on the main surface 81A of the insulating layer 81. As a result, the first wiring layer 41 is formed.

Next, as shown in FIG. 16, a protective layer 82 is formed which is laminated on the main surface 81A of the insulating layer 81 and covers the first main portion 411 of the first wiring layer 41. The protective layer 82 is made of the same material as the protective layer 29. The protective layer 82 has a mounting surface 82A. The mounting surface 82A faces the same side as the main surface 81A of the insulating layer 81 in the first direction z. The protective layer 82 is formed by compression molding.

Next, as shown in FIGS. 17 to 20, the first terminal 51, the second terminal 52, the third terminal 53, and the fourth terminal 54 are formed. In this description, a method of forming the fourth terminal 54 among these will be described. This is because the method of forming the first terminal 51, the second terminal 52, and the third terminal 53 is the same as the method of forming the fourth terminal 54. The step of forming the fourth terminal 54 includes a step of precipitating the base layer 501 on the insulating layer 81 and the protective layer 82, and a step of forming a plating layer 502 covering the base layer 501.

First, as shown in FIG. 18, the underlayer 501 is deposited on the insulating layer 81 and the protective layer 82. The base layer 501 is composed of the metal elements contained in the additives contained in each of the insulating layer 81 and the protective layer 82. In this step, as shown in FIG. 17, a plurality of penetration portions 821 are formed in the insulating layer 81 and the protective layer 82. Each of the plurality of penetration portions 821 reaches from the mounting surface 82A of the protective layer 82 to the source electrode 372 of the switching element 37. The plurality of penetrating portions 821 are formed by performing laser irradiation from the protective layer 82 to the insulating layer 81 while recognizing the position of the source electrode 372 with an infrared camera. The specifications of the laser are the same as the specifications of the laser used for forming the first wiring layer 41 shown in FIGS. 12 to 15. At this time, the irradiation position of the laser on the protective layer 82 is corrected one by one based on the position information of the source electrode 372 obtained by image recognition. The mounting surface 82A is patterned by the laser in accordance with the formation of the plurality of penetrating portions 821. The patterning is such that it leads to a plurality of penetrations 821. By irradiating the protective layer 82 and the insulating layer 81 with a laser, the metal element contained in the additive contained in each of the insulating layer 81 and the protective layer 82 is excited. As a result, a plurality of inner peripheral surfaces 821A that individually define the plurality of penetrating portions 821 and a base layer 501 that covers the mounting surface 82A are formed.

Next, as shown in FIG. 20, a plating layer 502 covering the base layer 501 is formed. The plating layer 502 is made of a material containing copper. The plating layer 502 is formed by electroless plating, electrolytic plating, or a combination thereof. As a result, as shown in FIG. 19, one of the plurality of fourth embedded portions 542 of the fourth terminal 54 is formed in each of the plurality of through portions 821 of the insulating layer 81 and the protective layer 82. At the same time, the fourth base portion 541 of the fourth terminal 54 is formed on the mounting surface 82A of the protective layer 82. As a result, the fourth terminal 54 is formed.

Next, as shown in FIG. 21, the second wiring layer 42 connected to the second electrode 32 and the second terminal 52 of the optical semiconductor element 30, the drain electrode 371 of the switching element 37, and the third connected to the first terminal 51. It forms a wiring layer 43. In the second wiring layer 42 and the third wiring layer 43, a metal thin film covering the second electrode 32 and the drain electrode 371 is formed on the back surface 81B of the insulating layer 81 by a sputtering method, and then the metal thin film is formed. It is formed by applying photolithography patterning. In addition to this method, the second wiring layer 42 and the third wiring layer 43 can adopt the same method as the formation of the first main portion 411 of the first wiring layer 41 shown in FIGS. 12 to 15.

Next, as shown in FIG. 22, a laser aperture 83 that exposes the optical region 33 of the optical semiconductor element 30 from the insulating layer 81 is formed. The laser aperture 83 penetrates the insulating layer 81 and the protective layer 82 in the first direction z. The laser aperture 83 is formed by irradiating a laser from the protective layer 82 to the insulating layer 81. The specifications of the laser are the same as the specifications of the laser used for forming the first wiring layer 41 shown in FIGS. 12 to 15.

Next, as shown in FIG. 23, after each of the plurality of capacitors 38 is joined to the second wiring layer 42 and the third wiring layer 43, the insulating layer 81 and the protective layer 82 are connected to the insulating layer 81 and the protective layer 82 along the cutting line CL with a dicing blade or the like. By cutting, it is divided into a plurality of pieces. Each of the plurality of capacitors 38 is joined by melting lead-free solder by reflow. The lead-free solder solidified by the subsequent cooling becomes the conductive bonding layer 39 of the optical semiconductor device A10. Each of the plurality of pieces includes one optical semiconductor element 30 and a switching element 37, and a plurality of capacitors 38 conducting the same, a first terminal 51, a second terminal 52, a third terminal 53, and a fourth terminal 54. To be included. The insulating layer 81 and the protective layer 82 that have been made into individual pieces by this step correspond to the first insulating layer 10 and the protective layer 29 of the optical semiconductor device A10.

Finally, the translucent resin 60 that covers the first insulating layer 10, the second wiring layer 42, the third wiring layer 43, the plurality of capacitors 38, and a part of the protective layer 29 is formed. The translucent resin 60 is formed by performing transfer molding on a plurality of pieces obtained in the step of FIG. 23. By going through the above steps, the optical semiconductor device A10 is manufactured.

Next, the operation of the semiconductor light emitting module B10 on which the optical semiconductor device A10 is mounted will be described with reference to FIG. 25. The semiconductor light emitting module B10 constitutes LiDAR. The semiconductor light emitting module B10 includes an optical semiconductor device A10, a gate driver 71, a DC power supply 72, a resistor 73, and a diode 74.

The gate driver 71 is electrically connected to the third terminal 53 and the fourth terminal 54. The gate driver 71 controls the gate voltage applied to the gate electrode 373 of the switching element 37. The DC power supply 72 is a power supply for causing the optical semiconductor element 30 to emit light. The positive electrode of the DC power supply 72 is conducting to the first terminal 51 via the resistor 73. The diode 74 is provided between the negative electrode of the DC power supply 72 and the second terminal 52. The diode 74 is for realizing storage in a plurality of capacitors 38 while preventing an excessive reverse bias from being applied to the optical semiconductor element 30.

In the semiconductor light emitting module B10, when the switching element 37 is in the OFF state, the DC power supply 72, the resistor 73, the first terminal 51, the second wiring layer 42, the plurality of capacitors 38, the third wiring layer 43, and the third wiring layer 43. A current IC flows in the order of the two terminals 52 and the diode 74, and charges are stored in the plurality of capacitors 38. When the switching element 37 is in the ON state, the electric charges stored in the plurality of capacitors 38 are the third wiring layer 43, the switching element 37, the first wiring layer 41, the optical semiconductor element 30, and the second wiring layer 42. The current IL flows in this order, and the optical semiconductor device 30 emits light.

Next, the operation and effect of the optical semiconductor device A10 will be described.

The first insulating layer 10 of the optical semiconductor device A10 is formed with an opening 12 that penetrates the first end surface 103 and exposes the optical region 33 of the optical semiconductor element 30. The first insulating layer 10 is located apart from each other in the third direction y, is connected to the first back surface 102, and has a pair of opening edges 121 that define the opening 12. The pair of opening edges 121 are in contact with the optical surface 302 of the optical semiconductor device 30. Such a configuration is realized by forming a laser aperture 83 that exposes the optical region 33 from the insulating layer 81 in the manufacturing process of the optical semiconductor device A10 shown in FIG. 23. When the optical region 33 is exposed from the first insulating layer 10, the pair of opening edges 121 is configured to be separated from the optical surface 302 and the pair of side surfaces 303 in the prior art using a mask layer or the like. As a result, even when the optical semiconductor device A10 is downsized, the optical region 33 can be efficiently exposed from the first insulating layer 10 by forming the laser aperture 83 shown in FIG. 23. Therefore, according to the optical semiconductor device A10, it is possible to contribute to the improvement of the manufacturing efficiency of the optical semiconductor device A10 while reducing the size of the optical semiconductor device A10.

The first insulating layer 10 has a pair of connecting surfaces 104 that are connected to the first end surface 103 and individually include a pair of opening edges 121. Each of the pair of connecting surfaces 104 is inclined with respect to the first end surface 103. As a result, it is possible to prevent the emission and incidence of light in the optical region 33 from being obstructed by the first insulating layer 10 while reducing the size of the opening 12 as much as possible. Further, since the covering area of the first insulating layer 10 with respect to the optical semiconductor element 30 is relatively large, the configuration is suitable from the viewpoint of protection of the optical semiconductor element 30.

In the optical semiconductor device A10, the pair of connecting surfaces 104 are connected to the first main surface 101 of the first insulating layer 10. This means that in the manufacturing process of the optical semiconductor device A10 shown in FIG. 23, it is relatively easy to manage the laser irradiation time and the like for forming the laser aperture 83.

The optical semiconductor device 30 has a first electrode 31 provided on the main surface 301 and a second electrode 32 provided on the side opposite to the first electrode 31 in the first direction z. The optical semiconductor device A10 further includes a first wiring layer 41 and a second wiring layer 42. The first wiring layer 41 is connected to the first electrode 31 and is arranged on the side where the first main surface 101 of the first insulating layer 10 is located with respect to the optical semiconductor element 30 in the first direction z. The second wiring layer 42 is connected to the second electrode 32 and is arranged on the side where the first back surface 102 of the first insulating layer 10 is located with respect to the optical semiconductor element 30 in the first direction z. The first wiring layer 41 is in contact with the first insulating layer 10. As a result, the first wiring layer 41 and the second wiring layer 42, which are conduction paths connected to the first electrode 31 and the second electrode 32 arranged on the front and back surfaces of the optical semiconductor element 30, are efficiently and three-dimensionally arranged. Can be done. Therefore, it is possible to shorten the path of the current flowing when the optical semiconductor element 30 emits light (the path of the current IL shown in FIG. 25), and it is possible to reduce the inductance applied to the path of the current. Thereby, when the optical semiconductor device A10 is applied to the pulse laser light source of LiDAR, faster switching is possible, and the peak current value of the current (current IL) flowing when the optical semiconductor device A10 emits light is further increased. be able to. This is advantageous for emitting a laser beam having a smaller pulse width in a higher output state, and is preferable as a light source device for LiDAR.

The first insulating layer 10 has a first penetrating portion 11 extending from the first main surface 101 to the first electrode 31 of the optical semiconductor element 30. The first wiring layer 41 has a first connecting portion 412 housed in the first penetrating portion 11 and connected to the first electrode 31, and a first main portion 411 arranged on the first main surface 101. As a result, the bonding state of the first connecting portion 412 with respect to the first electrode 31 becomes better than that in the case where the first connecting portion 412 is a wire. Further, the cross-sectional area of the first communication unit 412 with respect to the direction in which the current flows (first direction z) becomes larger. This contributes to the reduction of the inductance applied to the first wiring layer 41.

[Second Embodiment]
The optical semiconductor device A20 according to the second embodiment of the present invention will be described with reference to FIGS. 26 to 28. In these figures, the same or similar elements as the above-mentioned optical semiconductor device A10 are designated by the same reference numerals, and duplicate description will be omitted. Here, for convenience of understanding, FIG. 26 transmits a plurality of capacitors 38, a conductive bonding layer 39, and a translucent resin 60. In FIG. 26, the transmitted translucent resin 60 is shown by an imaginary line. FIG. 28 omits the illustration of the plurality of capacitors 38 and the conductive bonding layer 39.

In the optical semiconductor device A20, the configuration of the first insulating layer 10 related to the opening 12 is different from the configuration of the optical semiconductor device A10 described above.

As shown in FIGS. 26 to 28, in the optical semiconductor device A20, the first insulating layer 10 is added to the first main surface 101, the first back surface 102, the first end surface 103, and the pair of connecting surfaces 104. It further has an intermediate surface 105. The intermediate surface 105 is located between the first main surface 101 and the optical semiconductor element 30 in the first direction z. The intermediate surface 105 is connected to the first end surface 103 and the pair of connecting surfaces 104. The intermediate surface 105 includes an edge 13 in contact with the optical semiconductor element 30. The edge 13 extends along the third direction y. In the optical semiconductor device A20, the edge 13 is in contact with the first electrode 31 of the optical semiconductor element 30.

As shown in FIGS. 26 to 28, the intermediate surface 105 has a first intermediate surface 105A and a second intermediate surface 105B. The first intermediate surface 105A faces the same side as the first back surface 102 in the first direction z and is connected to the first end surface 103. The second intermediate surface 105B is connected to the first intermediate surface 105A in the second direction x and includes the edge 13. The second intermediate surface 105B is inclined with respect to the first intermediate surface 105A.

As shown in FIG. 28, the second intermediate surface 105B is curved inward of the first insulating layer 10. In the second direction x, the edge 13 is located inside the optical semiconductor device 30 with respect to the optical surface 302.

Next, the operation and effect of the optical semiconductor device A20 will be described.

The first insulating layer 10 of the optical semiconductor device A20 is formed with an opening 12 that penetrates the first end surface 103 and exposes the optical region 33 of the optical semiconductor element 30. The first insulating layer 10 is located apart from each other in the third direction y, is connected to the first back surface 102, and has a pair of opening edges 121 that define the opening 12. The pair of opening edges 121 are in contact with the optical surface 302 of the optical semiconductor device 30. Therefore, the optical semiconductor device A20 can also contribute to the improvement of the manufacturing efficiency of the optical semiconductor device A20 while reducing the size of the optical semiconductor device A20.

In the optical semiconductor device A20, the first insulating layer 10 further has an intermediate surface 105. The intermediate surface 105 is located between the first main surface 101 and the optical semiconductor element 30 in the first direction z. The intermediate surface 105 is connected to the first end surface 103 and the pair of connecting surfaces 104. The intermediate surface 105 includes an edge 13 in contact with the optical semiconductor element 30. In such a configuration, in the formation of the laser aperture 83 shown in FIG. 23, the laser irradiation is performed toward the back surface 81B of the insulating layer 81, and the irradiation time of the laser is shortened as compared with the production of the optical semiconductor device A10. It will be embodied. As a result, the removed volume of the first insulating layer 10 required to form the opening 12 becomes smaller than the removed volume of the first insulating layer 10 in the optical semiconductor device A10. This is suitable for reducing the thermal effect on the optical semiconductor element 30 while suppressing the decrease in strength of the first insulating layer 10 due to laser irradiation.

The intermediate surface 105 has a first intermediate surface 105A and a second intermediate surface 105B. The second intermediate surface 105B includes an edge 13 in contact with the optical semiconductor device 30. The second intermediate surface 105B is curved inward of the first insulating layer 10. Further, in the second direction x, the edge 13 is located inside the optical semiconductor element 30 with respect to the optical surface 302. As a result, it is possible to prevent the first insulating layer 10 from adhering to the optical region 33 of the optical semiconductor element 30 while minimizing the removal volume of the first insulating layer 10 required to form the opening 12.

[Third Embodiment]
The optical semiconductor device A30 according to the third embodiment of the present invention will be described with reference to FIGS. 29 to 31. In these figures, the same or similar elements as the above-mentioned optical semiconductor device A10 are designated by the same reference numerals, and duplicate description will be omitted. Here, for convenience of understanding, FIG. 29 transmits a plurality of capacitors 38, a conductive bonding layer 39, and a translucent resin 60. In FIG. 29, the transmitted translucent resin 60 is shown by an imaginary line. FIG. 31 omits the illustration of the plurality of capacitors 38 and the conductive bonding layer 39.

In the optical semiconductor device A30, the configuration of the first insulating layer 10 related to the opening 12 is different from the configuration of the optical semiconductor device A10 described above.

As shown in FIGS. 29 to 31, in the optical semiconductor device A30, the first insulating layer 10 has a first main surface 101, a first back surface 102, and a first end surface 103. In the optical semiconductor device A30, the pair of opening edges 121 defining the opening 12 are in contact with the pair of side surfaces 303 of the optical semiconductor element 30. In the second direction x, the first end surface 103 is located inside the optical semiconductor element 30 with respect to the optical surface 302. The first end face 103 includes a pair of opening edges 121.

Next, the operation and effect of the optical semiconductor device A30 will be described.

The first insulating layer 10 of the optical semiconductor device A30 is formed with an opening 12 that penetrates the first end surface 103 and exposes the optical region 33 of the optical semiconductor device 30. The first insulating layer 10 is located apart from each other in the third direction y, is connected to the first back surface 102, and has a pair of opening edges 121 that define the opening 12. The pair of opening edges 121 are in contact with the pair of side surfaces 303 of the optical semiconductor element 30. Therefore, the optical semiconductor device A30 can also contribute to the improvement of the manufacturing efficiency of the optical semiconductor device A30 while reducing the size of the optical semiconductor device A30.

In the optical semiconductor device A30, the first end surface 103 of the first insulating layer 10 includes a pair of opening edges 121. In the second direction x, the first end surface 103 is located inside the optical semiconductor element 30 with respect to the optical surface 302. As a result, the size of the opening 12 can be made larger than the size of the opening 12 of the optical semiconductor device A10, which is suitable when the area of the optical region 33 occupied by the optical surface 302 is relatively large.

[Fourth Embodiment]
The optical semiconductor device A40 according to the fourth embodiment of the present invention will be described with reference to FIGS. 32 to 34. In these figures, the same or similar elements as the above-mentioned optical semiconductor device A10 are designated by the same reference numerals, and duplicate description will be omitted. Here, for convenience of understanding, FIG. 32 transmits a plurality of capacitors 38, a conductive bonding layer 39, and a translucent resin 60. In FIG. 32, the transmitted translucent resin 60 is shown by an imaginary line. FIG. 34 omits the illustration of the plurality of capacitors 38 and the conductive bonding layer 39.

In the optical semiconductor device A40, the configuration of the first insulating layer 10 related to the opening 12 is different from the configuration of the optical semiconductor device A30 described above.

As shown in FIGS. 32 to 34, in the optical semiconductor device A40, the first insulating layer 10 has an intermediate surface 105 and an overhanging surface 106 in addition to the first main surface 101, the first back surface 102, and the first end surface 103. Further have.

As shown in FIGS. 32 and 34, the overhanging surface 106 is located on the side opposite to the first end surface 103 with respect to the optical surface 302 of the optical semiconductor element 30 in the second direction x. The overhanging surface 106 faces the same side as the first end surface 103 in the second direction x. In the optical semiconductor device A40, the overhanging surface 106 is located between the first main surface 101 and the intermediate surface 105 in the first direction z.

As shown in FIGS. 33 and 34, the intermediate surface 105 is located between the first main surface 101 and the optical semiconductor element 30 in the first direction z. As shown in FIGS. 32 and 33, the intermediate surface 105 is connected to the overhanging surface 106 and the first end surface 103. The intermediate surface 105 includes an edge 13 in contact with the optical semiconductor element 30. The edge 13 extends along the third direction y. In the optical semiconductor device A40, the edge 13 is in contact with the first electrode 31 of the optical semiconductor element 30.

As shown in FIGS. 32 to 34, the intermediate surface 105 has a first intermediate surface 105A and a second intermediate surface 105B. The first intermediate surface 105A faces the same side as the first back surface 102 in the first direction z and is connected to the overhanging surface 106. The second intermediate surface 105B is connected to the first intermediate surface 105A in the second direction x and includes the edge 13. The second intermediate surface 105B is inclined with respect to the first intermediate surface 105A.

As shown in FIG. 34, the second intermediate surface 105B is curved inward of the first insulating layer 10. In the second direction x, the edge 13 is located inside the optical semiconductor device 30 with respect to the optical surface 302.

Next, the operation and effect of the optical semiconductor device A40 will be described.

The first insulating layer 10 of the optical semiconductor device A40 is formed with an opening 12 that penetrates the first end surface 103 and exposes the optical region 33 of the optical semiconductor element 30. The first insulating layer 10 is located apart from each other in the third direction y, is connected to the first back surface 102, and has a pair of opening edges 121 that define the opening 12. The pair of opening edges 121 are in contact with the pair of side surfaces 303 of the optical semiconductor element 30. Therefore, the optical semiconductor device A40 can also contribute to the improvement of the manufacturing efficiency of the optical semiconductor device A40 while reducing the size of the optical semiconductor device A40.

In the optical semiconductor device A40, the first insulating layer 10 further has an intermediate surface 105. The intermediate surface 105 is located between the first main surface 101 and the optical semiconductor element 30 in the first direction z. The intermediate surface 105 is connected to the overhanging surface 106 and the first end surface 103. The intermediate surface 105 includes an edge 13 in contact with the optical semiconductor element 30. In such a configuration, in the formation of the laser aperture 83 shown in FIG. 23, the laser irradiation time is shortened to that of the optical semiconductor device A30 while irradiating the back surface 81B of the insulating layer 81 with the laser. It will be embodied. As a result, the removed volume of the first insulating layer 10 required to form the opening 12 becomes smaller than the removed volume of the first insulating layer 10 in the optical semiconductor device A30. This is suitable for reducing the thermal effect on the optical semiconductor element 30 while suppressing the decrease in strength of the first insulating layer 10 due to laser irradiation.

The intermediate surface 105 has a first intermediate surface 105A and a second intermediate surface 105B. The second intermediate surface 105B includes an edge 13 in contact with the optical semiconductor device 30. The second intermediate surface 105B is curved inward of the first insulating layer 10. Further, in the second direction x, the edge 13 is located inside the optical semiconductor element 30 with respect to the optical surface 302. As a result, it is possible to prevent the first insulating layer 10 from adhering to the optical region 33 of the optical semiconductor element 30 while minimizing the removal volume of the first insulating layer 10 required to form the opening 12.

[Fifth Embodiment]
The optical semiconductor device A50 according to the fifth embodiment of the present invention will be described with reference to FIGS. 35 to 39. In these figures, the same or similar elements as the above-mentioned optical semiconductor device A10 are designated by the same reference numerals, and duplicate description will be omitted. Here, for convenience of understanding, FIG. 35 transmits a plurality of capacitors 38, a conductive bonding layer 39, and a translucent resin 60. In FIG. 35, the transmitted translucent resin 60 is shown by an imaginary line. FIG. 39 omits the illustration of the plurality of capacitors 38 and the conductive bonding layer 39.

In the optical semiconductor device A50, the second insulating layer 20 is further provided, the configuration of the first insulating layer 10 related to the opening 12, and the configurations of the second wiring layer 42 and the third wiring layer 43 are described above. It is different for the optical semiconductor device A10. In the optical semiconductor device A50, the configuration of the first insulating layer 10 related to the opening 12 is the same as the configuration in the optical semiconductor device A20, and thus the description thereof is omitted here.

As shown in FIGS. 35 and 36, the second insulating layer 20 covers the second electrode 32 of the optical semiconductor element 30 and the drain electrode 371 of the switching element 37. The second insulating layer 20 is made of the same material as the first insulating layer 10. As shown in FIGS. 38 and 39, the second insulating layer 20 has a second main surface 201, a second back surface 202, and a second end surface 203.

As shown in FIG. 39, the second main surface 201 faces the same side as the first main surface 101 of the first insulating layer 10 in the first direction z. The second back surface 202 faces the side opposite to the second main surface 201 in the first direction z. In the second insulating layer 20, the second back surface 202 is arranged in contact with the first back surface 102 of the first insulating layer 10. As shown in FIGS. 37 and 38, the second end surface 203 is connected to the second main surface 201 and the second back surface 202, and faces the same side as the first end surface 103 of the first insulating layer 10 in the second direction x.

As shown in FIG. 36, the second insulating layer 20 has a plurality of second penetrating portions 21 and a plurality of third penetrating portions 22. Each of the plurality of second penetrating portions 21 reaches the second electrode 32 of the optical semiconductor element 30 from the second back surface 202 in the first direction z. Each of the plurality of third penetration portions 22 reaches the drain electrode 371 of the switching element 37 from the second back surface 202 in the first direction z.

As shown in FIGS. 37 to 39, the second insulating layer 20 is formed with a recess 23 recessed from the second end surface 203 in the second direction x. The recess 23 is connected to the opening 12.

As shown in FIGS. 35 and 36, the second wiring layer 42 has a second main unit 421 and a plurality of second communication units 422. Each of the plurality of second connecting portions 422 is accommodated in any of the plurality of second penetrating portions 21 of the second insulating layer 20, and is connected to the second electrode 32 of the optical semiconductor element 30. The second main portion 421 is arranged on the second back surface 202 of the second insulating layer 20, and is connected to a plurality of second connecting portions 422. When viewed along the first direction z, at least a part of the second main portion 421 overlaps with the first main portion 411 of the first wiring layer 41. Further, each of the plurality of second embedded portions 522 of the second terminal 52 reaches from the mounting surface 291 of the protective layer 29 to the second back surface 202 in the first direction z, as well as the protective layer 29, the first insulating layer 10, and the first insulating layer 10. It is embedded in the second insulating layer 20 in a state of being in contact with the three parties. Each of the plurality of second embedded portions 522 is connected to the second base portion 521 and the second main portion 421.

As shown in FIGS. 35 and 36, the third wiring layer 43 has a third main unit 431 and a plurality of third communication units 432. Each of the plurality of third connecting portions 432 is accommodated in any of the plurality of third penetrating portions 22 of the second insulating layer 20, and is connected to the drain electrode 371 of the switching element 37. The third main portion 431 is arranged on the second back surface 202 of the second insulating layer 20, and is connected to a plurality of third connecting portions 432. Further, each of the plurality of first embedded portions 512 of the first terminal 51 reaches from the mounting surface 291 of the protective layer 29 to the second back surface 202 in the first direction z, as well as the protective layer 29, the first insulating layer 10, and the first insulating layer 10. It is embedded in the second insulating layer 20 in a state of being in contact with the three parties. Each of the plurality of first embedded portions 512 is connected to the first base portion 511 and the third main portion 431.

Next, the operation and effect of the optical semiconductor device A50 will be described.

The first insulating layer 10 of the optical semiconductor device A50 is formed with an opening 12 that penetrates the first end surface 103 and exposes the optical region 33 of the optical semiconductor element 30. The first insulating layer 10 is located apart from each other in the third direction y, is connected to the first back surface 102, and has a pair of opening edges 121 that define the opening 12. The pair of opening edges 121 are in contact with the optical surface 302 of the optical semiconductor device 30. Therefore, the optical semiconductor device A50 can also contribute to the improvement of the manufacturing efficiency of the optical semiconductor device A50 while reducing the size of the optical semiconductor device A50.

The optical semiconductor device A50 further includes a second insulating layer 20. The second insulating layer 20 has a second penetrating portion 21 extending from the second back surface 202 to the second electrode 32 of the optical semiconductor element 30. The second wiring layer 42 has a second connecting portion 422 housed in the second penetrating portion 21 and connected to the second electrode 32, and a second main portion 421 arranged on the second back surface 202. As a result, the bonding state of the second connecting portion 422 with respect to the second electrode 32 becomes better than in the case where the second connecting portion 422 is a wire. Further, the cross-sectional area of the second connecting portion 422 with respect to the direction in which the current flows (first direction z) becomes larger. This contributes to the reduction of the inductance applied to the second wiring layer 42.

The present invention is not limited to the above-described embodiment. Each of the above-described embodiments may be configured to include a plurality of optical semiconductor devices 30. Each type of the plurality of optical semiconductor elements 30 can be freely selected according to the required application and function. Further, in each of the above-described embodiments, the outer shape is rectangular when viewed along the first direction z, but these outer shapes are not limited to a rectangular shape, and may be, for example, a circular shape or a hexagonal shape. The specific configuration of each part of the present invention can be freely redesigned.

A10, A20, A30, A40, A50: Optical semiconductor device 10: First insulating layer 101: First main surface 102: First back surface 103: First end surface 104: Connection surface 105: Intermediate surface 105A: First intermediate surface 105B : Second intermediate surface 106: Overhanging surface 11: First penetration portion 111: Inner peripheral surface 12: Opening 121: Opening edge 13: Edge edge 20: Second insulating layer 201: Second main surface 202: Second back surface 203: Second end surface 21: Second penetration portion 22: Third penetration portion 29: Protective layer 291: Mounting surface 30: Optical semiconductor device 301: Main surface 302: Optical surface 303: Side surface 304: Back surface 31: First electrode 32: First 2 electrodes 33: Optical region 37: Switching element 371: Drain electrode 372: Source electrode 373: Gate electrode 38: Condenser 381: Electrode 39: Conductive bonding layer 401: Underlayer layer 402: Plating layer 41: First wiring layer 411: 1st 1 Main part 412: 1st communication part 42: 2nd wiring layer 421: 2nd main part 422: 2nd communication part 43: 3rd wiring layer 431: 3rd main part 432: 3rd communication part 501: Base layer 502 : Plating layer 51: 1st terminal 511: 1st base 512: 1st embedded part 52: 2nd terminal 521: 2nd base 522: 2nd embedded part 53: 3rd terminal 531: 3rd base 532: 1st 3 Embedded part 54: 4th terminal 541: 4th base part 542: 4th embedded part 60: Translucent resin 71: Gate driver 72: DC power supply 73: Resistor 74: Diode 81: Insulation layer 81A: Main surface 81B : Back surface 811: Penetration part 811A: Inner peripheral surface 82: Protective layer 82A: Mounting surface 821: Penetration part 821A: Inner peripheral surface 83: Laser opening z: 1st direction x: 2nd direction y: 3rd direction

Claims (17)

The main surface facing the first direction and the optical surface facing the second direction orthogonal to the first direction and connected to the main surface are orthogonal to both the first direction and the second direction. An optical semiconductor element that faces opposite sides in a third direction and has a main surface and a pair of side surfaces connected to the optical surface.
A first main surface facing the same side as the main surface in the first direction, a first back surface facing the opposite side of the first main surface in the first direction, the first main surface and the first back surface. A first end surface that is connected to and faces the same side as the optical surface in the second direction, and has a first insulating layer that covers a part of the optical semiconductor element.
The optical surface has an optical region that emits or is incident on light.
The first insulating layer is formed with an opening that penetrates the first end surface and exposes the optical region.
The first insulating layer is located apart from each other in the third direction, is connected to the first back surface, and has a pair of opening edges defining the opening.
An optical semiconductor device, wherein the pair of aperture edges are in contact with any of the optical surface and the pair of side surfaces. The pair of open edges are in contact with the optical surface and
The first insulating layer has a pair of connecting surfaces that are located apart from each other in the third direction and are connected to the first end surface.
The pair of connecting surfaces individually include the pair of open edges.
The optical semiconductor device according to claim 1, wherein each of the pair of connecting surfaces is inclined with respect to the first end surface. The optical semiconductor device according to claim 2, wherein the pair of connecting surfaces are connected to the first main surface. The first insulating layer is located between the first main surface and the optical semiconductor element in the first direction, and has an intermediate surface connected to the first end surface and the pair of connecting surfaces.
The optical semiconductor device according to claim 2, wherein the intermediate surface includes an edge in contact with the optical semiconductor element. The pair of opening edges touch the pair of side surfaces and
The optical semiconductor device according to claim 1, wherein in the second direction, the first end surface is located inside the optical semiconductor element with respect to the optical surface. The optical semiconductor device according to claim 5, wherein the first end surface includes the pair of open edges. The first insulating layer has an overhanging surface that is located on the side opposite to the first end surface with respect to the optical surface in the second direction and faces the same side as the first end surface in the second direction. It has an overhanging surface and an intermediate surface connected to the first end surface, which is located between the first main surface and the optical semiconductor element in the first direction.
The optical semiconductor device according to claim 6, wherein the intermediate surface includes an edge in contact with the optical semiconductor element. The intermediate surface faces the same side as the first back surface in the first direction and is connected to the first end surface, and a second intermediate surface connected to the first intermediate surface in the second direction. Have,
The optical semiconductor device according to claim 4, wherein the second intermediate surface includes the edge and is inclined with respect to the first intermediate surface. The intermediate surface faces the same side as the first back surface in the first direction and is connected to the overhanging surface, and a second intermediate surface connected to the first intermediate surface in the second direction. Have,
The optical semiconductor device according to claim 7, wherein the second intermediate surface includes the edge and is inclined with respect to the first intermediate surface. The optical semiconductor device according to claim 8 or 9, wherein the second intermediate surface is curved inward of the first insulating layer. The optical semiconductor device according to claim 10, wherein in the second direction, the edge is located inside the optical semiconductor element with respect to the optical surface. The optical semiconductor device has a first electrode provided on the main surface and a second electrode provided on the side opposite to the first electrode in the first direction.
A first wiring layer connected to the first electrode and arranged on the side where the first main surface is located with respect to the optical semiconductor element in the first direction.
Further, a second wiring layer connected to the second electrode and arranged on the side where the first back surface is located with respect to the optical semiconductor element in the first direction is further provided.
The optical semiconductor device according to any one of claims 1 to 11, wherein the first wiring layer is in contact with the first insulating layer. The first insulating layer has a first penetrating portion extending from the first main surface to the first electrode.
The first wiring layer is housed in the first penetration portion and is connected to the first electrode, and is connected to the first contact portion and is arranged on the first main surface. The optical semiconductor device according to claim 12, further comprising a unit. A second surface that is connected to the first main surface and the first back surface and faces the same side as the first end surface in the second direction. Further provided with a second insulating layer having an end face and having the second back surface in contact with the first back surface.
The second wiring layer is in contact with the second insulating layer.
The second insulating layer is formed with a recess recessed from the second end surface toward the second direction.
The optical semiconductor device according to claim 13, wherein the recess is connected to the opening. The second insulating layer has a second penetrating portion extending from the second main surface to the second electrode.
The second wiring layer is housed in the second penetrating portion and is connected to the second electrode, and is connected to the second connecting portion and is arranged on the second main surface. With a part,
The optical semiconductor device according to claim 14, wherein at least a part of the second main portion overlaps the first main portion when viewed along the first direction. The optical semiconductor element is a laser diode and is
A switching element having a source electrode and a drain electrode and having at least a part covered with the first insulating layer.
Further, a third wiring layer arranged on the side where the first back surface is located with respect to the optical semiconductor element in the first direction is further provided.
The source electrode conducts to the first wiring layer and
The optical semiconductor device according to any one of claims 12 to 15, wherein the drain electrode is conductive to the third wiring layer. Further comprising a translucent resin covering at least a part of the first insulating layer,
The optical semiconductor device according to any one of claims 1 to 16, wherein the translucent resin covers the optical region and closes the opening.

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