JP2021532605A - Wiring method of digital integrated circuit by binary code and terminal device - Google Patents

Abstract

The present invention provides a wiring method for a digital integrated circuit using a binary code and a terminal device. In the above method, a predetermined number of first connection methods are determined, the first fitness function value of each first connection method is calculated by the wiring subspace corresponding to each connection line, and each first fitness function value is calculated by each first fitness function value. Select the first quantity of the third connection method in the set formed by the step of acquiring each second connection method by processing the one connection method and the merger of the first connection method and the second connection method. , Select the optimum connection method for all the third connection methods based on the step of calculating the second fitness function value of each third connection method and all the second fitness function values obtained by the calculation, and the optimum connection method. Includes a step to connect the pins of the standard cell depending on the connection method. The present invention can avoid the problem of different cord lengths in non-grids, reduce the range of optimization space, and improve wiring efficiency by adopting even grid binary cords. ..

Description

The present invention belongs to the technical field of digital integrated circuits, and particularly relates to wiring methods and terminal devices for digital integrated circuits using binary codes.

A digital integrated circuit (IC) is also called a chip, which is a microelectronic device based on semiconductor technology. Current digital integrated circuits are usually composed of the standard cells shown in FIG. A standard cell is a circuit module having a predetermined function, and includes, for example, a trigger, a gate circuit, an adder, a buffer, a register, a RAM memory unit, and the like. In the design of digital integrated circuits, the position of the standard cell is determined by the wiring ratio (Routability) of the connection line. Next, the position of the wiring is determined by the position of the standard cell, the input / output pin, and the netlist information. As a result, the total length of the connection line can be minimized under the premise of ensuring the network radiation of the digital integrated circuit.

However, in conventional digital integrated circuits, when standard cells are arranged and then connected, wiring is usually designed by a pull-out method. For example, the wiring is designed by optimizing the particle swarm and the Ant Colony Algorithm. However, since the IC wiring is a large-scale and complicated adaptation process, it cannot be easily processed by the conventional drawing method, so that the wiring efficiency may decrease.

In order to solve the technical problems of the prior art, the object of the present invention is to provide a wiring method of a digital integrated circuit using a binary code and a terminal device.

The technical matters of the present invention are as follows.

A method of wiring a digital integrated circuit using a binary code, wherein the digital integrated circuit includes a substrate on which a plurality of standard cells are arranged, the substrate includes a plurality of connection lines, and the digital integrated circuit is digitally arranged by the binary code. The wiring method of the integrated circuit is
A step of forming a predetermined quantity of binary vectors and forming a predetermined quantity of first connection method from the formed predetermined quantity of binary vectors.
The step of calculating the path cost vector of the first connection method by the wiring subspace corresponding to each connection line, and
Each second connection is calculated by calculating the first fitness function value of each first connection method from each path cost vector, and processing each first connection method by adopting each first fitness function value and binary string genetic algorithm. Steps to acquire the method and
In the set formed by the merger of the first connection method and the second connection method, the step of selecting the third connection method of the first quantity and calculating the second fitness function value of each third connection method, respectively.
It includes a step of selecting the optimum connection method in all the third connection methods based on all the second fitness function values obtained by calculation, and connecting the pins of the standard cell by the optimum connection method.

In the wiring method of the digital integrated circuit using the binary code, the step of forming a predetermined quantity of binary vectors and forming a predetermined quantity of the first connection method by the formed predetermined quantity of binary vectors is specifically described.
Steps to acquire the first dimension of the wiring subspace corresponding to each connection line,
A step of calculating the second dimension from all the acquired first dimensions and forming a predetermined quantity of binary vectors by the second dimension.
A step of forming a predetermined quantity of first connection method by a predetermined quantity of binary vectors formed, the dimension of the binary vector includes a step of being a second dimension.

In the wiring method of the digital integrated circuit using the binary code, the step of calculating the path cost vector of the first connection method by the wiring subspace corresponding to each connection line is specifically described.
Steps to acquire the first dimension of the wiring subspace corresponding to each connection line,
A step that divides each first connection method into multiple subvectors according to the first dimension corresponding to each connection line,
A step of forming a grid intersection set by the grid intersections corresponding to code 1 in each subvector, determining the path lengths of the subvectors corresponding to them by each grid intersection set, and forming a path cost vector by each path length. including.

In the wiring method of a digital integrated circuit using the binary code, before acquiring the first dimension of the wiring subspace corresponding to each connection line,
A step of acquiring the position information of each pin on the board and dividing the board into a plurality of grids based on all the acquired position information.
Acquire the grid intersection corresponding to the two pins connected by each connection line, determine the binary vector of each connection line by the acquired grid intersection, and determine the wiring subspace corresponding to each connection line by each binary vector. Including steps to do.

In the wiring method of the digital integrated circuit using the binary code, the first fitness function value of each first connection method is calculated from each path cost vector, and the first fitness function value and the binary string genetic algorithm are adopted. Specifically, the steps to acquire each second connection method by processing each first connection method are concrete.
In each path cost vector, the step of calculating the sequence value of the path cost in the path cost of the dimension in which the path cost of each dimension corresponds to all the path cost vectors,
A step of forming a path cost sequence vector from the path cost sequence values of each dimension and calculating a first fitness function value of each first connection method from each path cost sequence vector.
Each includes a first fitness function and a step of acquiring each second connection method by processing each first connection method by adopting a binary string genetic algorithm.

In the wiring method of the digital integrated circuit using the binary code, the optimum connection method is selected for all the third connection methods based on all the second fitness function values obtained by calculation, and the standard cell is selected by the optimum connection method. Specifically, the steps to connect the pins
The step of selecting the optimum connection method for all the third connection methods based on all the second fitness function values obtained by calculation, and
It includes a step of calculating the shortest grid path of each connection line in the optimum connection method and connecting the pins of the standard cell by the shortest grid path.

In the wiring method of the digital integrated circuit using the binary code, the optimum connection method is selected for all the third connection methods based on all the second fitness function values obtained by calculation, and the standard cell is selected by the optimum connection method. Specifically, the steps to connect the pins
A step of acquiring the number of iterations corresponding to the third connection method and comparing the number of iterations with the preset number of iterations.
When the number of iterations is equal to the number of preset iterations, the optimum connection method among the third connection methods is selected from all the second fitness function values obtained by calculation, and the standard cell is selected by the optimum connection method. Includes steps to connect pins.

In the wiring method of the digital integrated circuit using the binary code, when the number of iterations is smaller than the preset number of iterations, the process returns to the step of changing the third connection method to the first connection method and forming the first connection method. After that, the step is repeated until the number of iterations reaches a preset number of iterations.

A computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs are executed by one or more processors. In order to carry out the steps in the wiring method of the digital integrated circuit by the binary code.

The terminal device includes a processor, memory and bus, in which the memory stores a computer-readable program that can be executed by the processor.
The bus is responsible for communication between the processor and memory.
The processor performs a step in the method of wiring a digital integrated circuit with a binary code by executing a computer-readable program.

Compared with the prior art, the following invention can be achieved by the wiring method of the digital integrated circuit by the binary code of the present invention and the terminal device. In the wiring method of the digital integrated circuit using the binary code, a predetermined number of first connection methods are determined, and the first fitness function value of each first connection method is calculated from the wiring subspace corresponding to each connection line. The first in the set formed by the step of acquiring each second connection method by processing each first connection method by each first fitness function value and the merger of the first connection method and the second connection method. The step of selecting the third connection method of quantity and calculating the second fitness function value of each third connection method, and the optimum connection in all the third connection methods by all the second fitness function values obtained by the calculation. It includes a step of selecting a method and connecting the pins of the standard cell by the optimum connection method. The present invention avoids the problem of different cord lengths in non-grids by adopting even grid binary cords, reduces the range of optimization space, and improves wiring efficiency. be able to.

It is a figure which shows the arrangement of the standard cell of a digital integrated circuit. It is a flow chart which shows the wiring method of the digital integrated circuit by the binary code of this invention. It is another flow chart which shows the wiring method of the digital integrated circuit by the binary code of this invention. It is a flow chart which shows that the wiring line is determined in the wiring method of the digital integrated circuit by the binary code of this invention. It is a principle diagram which shows the structure of the preferable embodiment of the self-start control system (corresponding to a terminal apparatus) of this invention.

The present invention provides a wiring method for a digital integrated circuit using a binary code and a terminal device. In order to have a clear and detailed understanding of the object, technical features and effects of the invention, examples of the present invention will be described in more detail below with reference to the drawings. The following specific examples explain the present invention, but do not limit the present invention.

In the specification of the present invention, unless otherwise specified, terms such as "one", "one piece", "the above" and "the" in the present specification include not only one matter but also one matter. It can also include multiple items. The term "contains" in the present specification means to include features, integers, steps, operations, parts and / or modules, but one or more features, integers, steps, operations, parts. And / or a combination of modules may be present or may further include those combinations. Note that when a part is "connected" or "connected" to another part, that part is either directly connected or connected to the other part or indirectly connected to the other part by an intermediate part. Or can be connected. The "linkage" or "connection" in this specification can be a wireless connection or a wireless connection. The term "and / or" in this specification can be meant to include any one or more, any combination or all of one or more of the matters involved. ..

In the specification of the present invention, unless otherwise specified, the terms (including technical terms and scientific terms) in the present specification refer to the meanings of terms commonly used by engineers in this technical field. It should be noted that the terms in the present invention and in the prior art can refer to the meanings of the terms in the dictionary, but if there are special definitions, they refer to the specially defined meanings. Can be done.

Hereinafter, the technical features of the present invention will be described in more detail with reference to the drawings and specific examples.

An embodiment of the present invention provides a wiring method for a digital integrated circuit using a binary code. As shown in FIGS. 2-4, the method comprises the following steps.

In step S10, a predetermined quantity of binary vectors is formed, and a predetermined quantity of the first connection method is formed by the formed predetermined quantity of binary vectors.

The binary vector is intended to be formed at random, the binary vector is denoted by S _i, each element in the S _i of which are randomly formed by 0 and 1. That is, the _Si is a second-dimensional vector randomly formed by 0 and 1. The S dimension digital integrated circuits of _i is the first dimension of the dimension of the arrangement subspace of digital integrated circuit that is formed after the standard cells are arranged total, denoted it that it the second dimension. Each arrangement subspace is a routable section corresponding to each connection line. In this embodiment, the first connection method of a predetermined quantity constitutes the _{first evolution population ps = {S 1} , S ₂ , ..., _Sps}.

In the embodiment of the present invention, the steps of forming a predetermined quantity of binary vectors and forming a predetermined quantity of the first connection method from the formed predetermined quantity of binary vectors specifically include the following steps.

Acquire the first dimension of the wiring subspace corresponding to each connection line.

The second dimension is calculated from all the acquired first dimensions, and a predetermined quantity of binary vectors are formed by the second dimension.

A predetermined quantity of binary vectors formed to form a predetermined quantity of first connection method, and the dimension of the binary vector is the second dimension.

The digital integrated circuit includes a substrate, a plurality of standard cells, and a plurality of connection lines, and the plurality of standard cells are arranged on the substrate. That is, the present invention is used in a digital integrated circuit in which a standard cell is arranged. After arranging the standard cell on the board, each pin on the digital integrated circuit is connected by a connection line. The pins include standard cell component pins and port pins on the board. Digital integrated P = pins set on the circuit _{{p 1, p 2, ...} , p m} is denoted by s, m in the formula is the number of pins, m is an integer multiple. E = a set of a plurality of connection lines _{{e 1, e 2, ...} , e n} is denoted by s, n in the formula is the number of connection lines, n represents an integer multiple. Each connecting line in E connects two pins in P. The wiring problem of the digital integrated circuit in which the standard cell is arranged is to minimize the total length TWL of the connection line in the chip space where wiring is possible. The formula for calculating TWL is as follows.

はｅ_ｉの長さである。 Said

Is the length of e _i.

In _{order to calculate the length of e i} , it is necessary to divide the substrate into a plurality of grids in the digital integrated circuit in which the standard cell is arranged. The following steps are further performed before acquiring the first dimension of the wiring subspace corresponding to each connection line.

The position information of each pin on the substrate is acquired, and the substrate is divided into a plurality of grids based on all the acquired position information.

Acquire the grid intersection corresponding to the two pins connected by each connection line, determine the binary vector of each connection line by the acquired grid intersection, and determine the wiring subspace corresponding to each connection line by each binary vector. do.

Specifically, the position information refers to a coordinate point where each pin is located in a preset coordinate. After acquiring the position information, the horizontal coordinate distance for connecting any two pins in P and the coordinate distance for connecting any two pins in P are calculated from each position information, and the horizontal coordinate distance and the vertical are calculated. The greatest common factor (HCF) of the coordinate distance is calculated respectively. The greatest common divisor of the abscissa distance is the width w of the grid, and the greatest common divisor of the abscissa distance is the height h of the grid. The abscissa distance and the abscissa distance are the coordinates in the coordinates formed on the substrate. For example, it can be a coordinate in coordinates formed by an origin located in the left lower corner of the substrate, a lateral axis extending to the right and a lateral axis extending upward. In this embodiment, the formulas for calculating the width of the grid and the height of the grid are as follows.

In this equation, e _{i, j} is a connecting line between the connecting pins p _i and p _{j in E.}

After calculating the width w of the grid and the height h of the grid, the substrate is divided into a plurality of grids having a width and a height of w × h. In that case, each pin is located at the intersection of the grid. In any connecting line in E, the coordinate point of the grid position where the pin connected by the connecting line is located determines the first dimension of the wiring subspace corresponding to the connecting line. In that case, the connection line connecting _{the pins p i} and p _{j is described as e i, j} . The wiring subspace corresponding to _{e i, j} is determined by the coordinate points of the _{pins p i} and p _j. The specific process is as follows. The coordinate points {x _i , y _i } and {x _j , y _j } of the pins p _i and p _j are acquired, and the coordinate points {x _{j, y j} are obtained by the coordinate points {x i} , y _i } and {x _j , y _j }. _i , y _j } and {x _j , y _i } are acquired, and the coordinate points {x _i , y _i }, {x _j , y _j }, {x _i , y _j } and {x _j , y _i } Make the rectangular area at the top of the e _{i, j} wiring subspace. Effective grid intersections are grid intersections that are not covered by standard cells.

である。 e _i, after acquiring wiring subspace _j, detects the effective grid intersections are included in the e _{i, j} of the wiring sub-space. The number of the effective grid intersection to be detected is 1, 2, ... .. .. It is expressed as k, and _{the wiring code of e i, j} is expressed as k-dimensional binary vector C _{i, j} = (c ₁ , c ₂ , ..., c _k ). In any _{l∈k, c} l = 1 means that the e _{i, j} wire passes through the grid intersection _{l, c} l = 0 means that e _{i, j} wiring does not pass through the grid intersection l .. In that case, _{the first dimension of the wiring subspace of the connection lines e i, j} is k, and the second dimension is the same as the sum of the first dimensions. That is, the second dimension is

Is.

In step S20, the path cost vector of the first connection method is calculated by the wiring subspace corresponding to each connection line.

The dimension of the path cost vector is the third dimension, and the third dimension is equal to the quantity n of the connecting lines. That is, the path cost vector is an n-dimensional vector. A plurality of subvectors are acquired by dividing the path cost vector by the dimension of the wiring subspace of each connection line, and the path cost vector is acquired by the plurality of subvectors acquired by the division. That is, when calculating the path cost vector corresponding to each first connection method, it is necessary to divide each path cost vector. The step of calculating the path cost vector of the first connection method from the wiring subspace corresponding to each connection line specifically includes the following steps.

In step S21, the first dimension of the wiring subspace corresponding to each connection line is acquired.

In step S22, each first connection method is divided into a plurality of subvectors according to the first dimension corresponding to each connection line.

In step S23, a grid intersection set is formed by the grid intersections corresponding to the code 1 in each subvector, the path lengths of the subvectors corresponding to them are determined by each grid intersection set, and each path length determines the path length. Form a path cost vector.

である。その式において、ｋ_ｌは接続線ｅ_ｌの配線サブ空間の次元である。サブベクトルを獲得した後、各サブベクトルＣ_ｌ＝｛Ｃ_１,Ｃ_２,...,Ｃ_ｋｌ｝はｋｌの各グリッド交差点を含み、Ｃ_ｌ＝｛Ｃ_１,Ｃ_２,...,Ｃ_ｋｌ｝中の二進コードが１である交差点を検出することにより交差点集合Ｖ＝｛ｖ_ｉ＝ｉ,∀ｉ∈ｋ_ｌ,ｃ_ｉ＝１｝を獲得する。 _{After acquiring the first dimension, Si} = {C1 | C2 | ... | Cn} is acquired by dividing the first connection method into a plurality of subvectors according to each first dimension. The dimension of each subvector in the {C1 | C2 | ... | Cn} corresponds to one dimension of the wiring subspace of each connection line. That is,

Is. In the expression, k _l is the dimension of the wiring sub-space connection line e _l. After acquiring the subvectors, each subvector C _l = {C ₁ , C ₂ , ..., C _kl } includes each grid intersection of kl, and C _l = {C ₁ , C ₂ , ..., C _kl} in binary code intersection set by detects intersection is _{1 V = {v i = i} , ∀i∈k l, acquire _c i = 1}.

だと表記する。グリッドパスの最小値は線形プログラミング等の従来の計算方法により算出することができるが、ここでは再び説明しない。各サブベクトルのパス長を獲得した後、獲得した各パス長によりＳ_ｉのパスコストベクトルを計算する。前記Ｓ_ｉのパスコストベクトルはＦ_ｉ＝｛ｆ_ｉ,１,ｆ_ｉ,２,...,ｆ_ｉ,ｎ｝であり、

はＣ_ｌに対するＳ_ｉのパスコストである。 Intersection set _{V = {v i = i,} ∀i∈k l, c i = 1} After winning, calculates the minimum value of the grid path through each intersection of the intersection set of the smallest of the grid path The path length of the subvector value

Notated as. The minimum value of the grid path can be calculated by a conventional calculation method such as linear programming, but it will not be described again here. After acquiring the path length of each sub-vector, calculates the path cost vector of S _i by the respective path length acquired. Wherein the path cost vector of _{S i F i = {f i} , 1, f i, 2, ..., f i, n} is,

Is the path cost of the _{S i} for _{C l.}

In step S30, the first fitness function value of each first connection method is calculated from each path cost vector, and each first fitness function value and the binary strings genetic algorithm are adopted. By processing each first connection method, each second connection method is acquired.

The first fitness function value is calculated from each pass cost vector. After acquiring the first fitness function value, the second connection method is acquired by processing each first connection method by adopting the first fitness function value and the binary string genetic algorithm. That is, the optimized population is acquired by first performing the optimization on the population. The process performed on the first population by the binary string genetic algorithm is to obtain the optimized population by crossing and mutating the first population. The number of individuals with the optimized population can be equal to the number of individuals with the first population. It should be noted that conventional techniques can be adopted for the crossing and mutation operations, which will not be described again here.

In the embodiment of the present invention, the first fitness box value of each first connection method is calculated from the path cost vector, and each first connection method is adopted by adopting the first fitness function value and the binary string genetic algorithm. The step of acquiring each second connection method by processing specifically includes the following steps.

In step S31, in each path cost vector, the sequence value of the path cost in the dimension path cost in which the path cost of each dimension corresponds to all the path cost vectors is calculated. Specifically, by acquiring the path cost of each dimension of each path cost vector and arranging the path costs, the sequence value of the path cost of each path cost vector of that dimension is calculated. Next, by performing the step in each dimension, the sequence value of the path cost of each path cost vector in that dimension can be grasped.

In step S32, the sequence vector of the path cost is formed by the sequence value of the path cost of each dimension, and the first fitness function value of each first connection method is calculated by the sequence vector of each said path cost.

In step S33, each second connection method is acquired by processing each first connection method by adopting each first fitness function value and a binary string genetic algorithm.

Any path cost vector _{F i = {f i, 1} , f i, 2, ..., f i, n} in the cost of the path cost vector is positioned on the first dimension in all paths vectors Get the sequence value. That is, in any path cost vector A, after acquiring the path cost on the first dimension of the path cost vector, all the other path cost vectors acquire the path cost located on the first dimension. And by sequencing all the acquired path costs, the path cost on the first dimension of the path cost vector A acquires the sequence value in all the path costs on the first dimension. After acquiring the sequence value of the pass cost of the first dimension, the sequence value of the pass cost of the second dimension is acquired, and by repeating this, the sequence value of the pass cost of the nth dimension is acquired. _{The path cost sequence vector Ri} = {ri _{, 1} , ri _{, 2} , ..., ri _{, n} } is formed by the sequence values of the n path costs. In that equation, r _{i, l} = rank (fi _{, l} ), i = 1, 2, ..., | ps |. After acquiring the sequence vector of the path cost, the first fitness function value of the first connection method corresponding to the sequence vector of the path cost is calculated. The first fitness function value is as follows.

In step S40, the third connection method of the first quantity is selected in the set formed by the merger of the first connection method and the second connection method, and the second fitness function value of each third connection method is calculated.

After acquiring each second connection method, each second connection method ^{constitutes an evolutionary population ps *,} and the set composed of each second connection method and the set composed of each first connection method are merged. _{The union set pscomb} of the first connection method and the second connection method is formed by, and the third connection method of the first quantity is selected in the set formed by the merger of the first connection method and the second connection method. After selecting the third connection method of the first quantity, the second fitness function value of each third connection method is calculated by the above-mentioned fitness box value calculation method.

In step S50, the optimum connection method for all the third connection methods is selected from all the second fitness function values obtained by calculation, and the pins of the standard cell are connected by the optimum connection method.

A connection method in which the standard cell of the digital integrated circuit is arranged by calculating the second fitness function value of each third connection method and selecting the third connection method with a smaller second fitness function value to make the connection method. Can be acquired. However, in order to improve the wiring optimization (minimization of the connection line) of the digital integrated circuit in the actual application, after acquiring all the third connection methods, the optimization step of making the third connection method the first arrangement is performed. By repeating this, the third connection method of optimization is acquired. The step of selecting the optimum connection method for all the third connection methods based on all the second fitness function values obtained by calculation and connecting the pins of the standard cell by the optimum connection method specifically includes the following steps. ..

The number of iterations corresponding to the third connection method is acquired, and the number of iterations is compared with the preset number of iterations.

When the number of iterations is equal to the number of preset iterations, the optimum connection method among the third connection methods is selected from all the second fitness function values obtained by calculation, and the standard cell is selected by the optimum connection method. Connect the pins.

When the number of iterations is smaller than the preset number of iterations, the number of iterations reaches the preset number of iterations after returning to the step of changing the third connection method to the first connection method and forming the first connection method. Repeat that step until time.

The preset number of iterations G is a preset value. For example, the preset number of iterations can be 50 or the like. After the number of iterations reaches the preset number of iterations and the optimum third connection method is selected, the shortest path of the third connection method is calculated again, and each connection line in the third connection method becomes a predetermined shortest path. Control to be provided. The step of selecting the optimum connection method for all the third connection methods based on all the second fitness function values obtained by calculation and connecting the pins of the standard cell by the optimum connection method specifically includes the following steps. .. Select the optimum connection method for all third connection methods based on all the second fitness function values obtained by calculation. The shortest grid path of each connection line in the optimum connection method is calculated, and the pins of the standard cell are connected by the shortest grid path. The method of calculating the shortest grid path is the same as the method of calculating the shortest path in the wiring optimization structure.

The present invention further provides a computer-readable storage medium by the wiring method of a digital integrated circuit using the binary code. The computer-readable storage medium stores one or more programs, and the one or more programs are executed by one or more processors, thereby according to the embodiment of the present invention. You can perform the steps in the wiring method of a digital integrated circuit with a binary code.

The present invention further provides the following terminal device by the wiring method of a digital integrated circuit using the binary code. As shown in FIG. 5, the terminal device includes at least one processor 20, a display panel 21, and a memory 22. The terminal device may further include a Communications Interface 23 and a bus 24. The processor 20, the display panel 21, the memory 22, and the communication interface 23 are communicably connected by the bus 24. The display panel 21 is provided to display a preset guidance interface in the initial configuration model. Information can be transmitted by the communication interface 23. The processor 20 can implement the wiring method of the digital integrated circuit by the binary code according to the said embodiment of the present invention by using the logic command in the memory 22.

The logic command in the memory 22 can be executed by the software unit. When the logic command in the memory 22 is sold or used as an independent product, the logic command can be stored in a computer-readable storage medium.

The memory 22 is a computer-readable storage medium and is provided to store a software program, a computer-executable program, for example, a program command or a program module according to an embodiment of the present invention. The processor 20 processes a predetermined function and data by executing a software program, a program command, or a program module stored in the memory 22. For example, a method of wiring a digital integrated circuit using a binary code according to the embodiment of the present invention can be implemented.

The memory 22 can include a program storage area and a data storage area. A program storage area can store an operating system, an application program that performs at least one function, and a data storage area can store data and the like formed by the use of a terminal device. The memory 22 can include high speed random access memory or non-volatile memory. For example, a medium for storing a program code such as a USB flash disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or a write disk. Or can be a temporary storage medium.

The specific process in which the plurality of commands in the storage medium and the terminal device are executed by the processor can be referred to the wiring method of the digital integrated circuit by the binary code, and will not be described again here.

It should be noted that the above embodiments explain the technical matters of the present invention, but do not limit the present invention. Although the technical features of the present invention have been described in detail by the examples of the present invention, the above-mentioned examples are merely examples of the present invention, and the present invention is limited to the configuration of the above-mentioned examples. Not a thing. Engineers in the present technical field can make design changes, substitutions, etc. within the scope of the gist of the present invention, and even if they exist, they are of course included in the present invention.

20 processor
21 Display panel
22 memory
23 Communication interface
24 bus

Claims (10)

A method of wiring a digital integrated circuit using a binary code, wherein the digital integrated circuit includes a substrate on which a plurality of standard cells are arranged, the substrate includes a plurality of connection lines, and the digital integrated circuit is digitally arranged by the binary code. The wiring method of the integrated circuit is
A step of forming a predetermined quantity of binary vectors and forming a predetermined quantity of first connection method from the formed predetermined quantity of binary vectors.
The step of calculating the path cost vector of the first connection method by the wiring subspace corresponding to each connection line, and
Each second connection is calculated by calculating the first fitness function value of each first connection method from each path cost vector, and processing each first connection method by adopting each first fitness function value and binary string genetic algorithm. Steps to acquire the method and
In the set formed by the merger of the first connection method and the second connection method, the step of selecting the third connection method of the first quantity and calculating the second fitness function value of each third connection method, respectively.
It is characterized by including a step of selecting the optimum connection method in all the third connection methods based on all the second fitness function values obtained by calculation, and connecting the pins of the standard cell by the optimum connection method. Wiring method for digital integrated circuits using binary codes. Specifically, the step of forming a predetermined quantity of binary vectors and forming a predetermined quantity of first connection method from the formed predetermined quantity of binary vectors is specifically.
Steps to acquire the first dimension of the wiring subspace corresponding to each connection line,
A step of calculating the second dimension from all the acquired first dimensions and forming a predetermined quantity of binary vectors by the second dimension.
The first aspect of claim 1, wherein the first connection method of a predetermined quantity is formed by the formed binary vectors of a predetermined quantity, and the dimension of the binary vector includes a step of the second dimension. Wiring method of digital integrated circuit by the described binary code. Specifically, the step of calculating the path cost vector of the first connection method by the wiring subspace corresponding to each connection line is concrete.
Steps to acquire the first dimension of the wiring subspace corresponding to each connection line,
A step that divides each first connection method into multiple subvectors according to the first dimension corresponding to each connection line,
A step of forming a grid intersection set by the grid intersections corresponding to code 1 in each subvector, determining the path lengths of the subvectors corresponding to them by each grid intersection set, and forming a path cost vector by each path length. The method for wiring a digital integrated circuit using a binary code according to claim 1, wherein the method comprises. Before acquiring the first dimension of the wiring subspace corresponding to each connection line,
A step of acquiring the position information of each pin on the board and dividing the board into a plurality of grids based on all the acquired position information.
Acquire the grid intersection corresponding to the two pins connected by each connection line, determine the binary vector of each connection line by the acquired grid intersection, and determine the wiring subspace corresponding to each connection line by each binary vector. The method for wiring a digital integrated circuit according to a binary code according to claim 2 or 3, wherein the method includes the steps to be performed. Each first connection method is calculated by calculating the first fitness function value of each first connection method from each path cost vector, and processing each first connection method by adopting each first fitness function value and a binary string genetic algorithm. Specifically, the steps to acquire the two-connection method
In each path cost vector, the step of calculating the sequence value of the path cost in the path cost of the dimension in which the path cost of each dimension corresponds to all the path cost vectors,
A step of forming a path cost sequence vector from the path cost sequence values of each dimension and calculating a first fitness function value of each first connection method from each path cost sequence vector.
2. The second aspect of claim 1, comprising each first fitness function value and a step of acquiring each second connection method by adopting a binary string genetic algorithm and processing each first connection method. Wiring method for digital integrated circuits using forward codes. Specifically, the step of selecting the optimum connection method for all the third connection methods based on all the second fitness function values obtained by calculation and connecting the pins of the standard cell by the optimum connection method is concrete.
The step of selecting the optimum connection method for all the third connection methods based on all the second fitness function values obtained by calculation, and
The digital according to the binary code according to claim 1, wherein the shortest grid path of each connection line in the optimum connection method is calculated, and the step of connecting the pins of the standard cell by the shortest grid path is included. Wiring method for integrated circuits. Specifically, the step of selecting the optimum connection method for all the third connection methods based on all the second fitness function values obtained by calculation and connecting the pins of the standard cell by the optimum connection method is concrete.
A step of acquiring the number of iterations corresponding to the third connection method and comparing the number of iterations with the preset number of iterations.
When the number of iterations is equal to the preset number of iterations, the optimum connection method among the third connection methods is selected from all the second fitness function values obtained by calculation, and the standard cell is selected by the optimum connection method. The method for wiring a digital integrated circuit using a binary code according to claim 1, further comprising a step of connecting pins. When the number of iterations is smaller than the preset number of iterations, the number of iterations reaches the preset number of iterations after returning to the step of changing the third connection method to the first connection method and forming the first connection method. The wiring method for a digital integrated circuit using a binary code according to claim 7, wherein the step is repeated until time. A computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs are executed by one or more processors. A computer-readable storage medium comprising the steps in the method of wiring a digital integrated circuit according to the binary code according to any one of claims 1-8. A terminal device that includes a processor, memory, and bus, in which computer-readable programs that can be executed by the processor are stored.
The bus is responsible for communication between the processor and memory.
The processor comprises executing a computer-readable program to carry out the steps in the wiring method of a digital integrated circuit according to the binary code according to any one of claims 1 to 8. ..

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