JP7175533B2 - DIGITAL INTEGRATED CIRCUIT LAYOUT METHOD AND TERMINAL DEVICE USING DISCRETE OPTIMIZATION - Google Patents

Description

The present invention belongs to the technical field of digital integrated circuits, and more particularly, to a layout method and terminal device for digital integrated circuits by discrete optimizing.

A digital integrated circuit (IC), also called a chip, is a microelectronic device based on semiconductor technology. Current integrated circuits are usually composed of standard cells. Standard cells are circuit modules with certain functions, including triggers, gate circuits, adders, buffers, registers, RAM memory units, and so on. As shown in FIG. 1, the heights of standard cells are usually the same in one layout. Although the height of each standard cell is the same, its width increases as its function increases, its structure becomes more complicated, the number of transistors provided increases, and the overall width also increases. In setting a digital integrated circuit, convenience of connection can be improved by locating a predetermined standard cell near the port depending on the position of the functional port. Internal connection lines are provided between standard cells, and layout results directly affect the completion rate of wire connection. Due to the increase in application demand and chip integration, multifunctional digital integrated circuits consist of tens of thousands or tens of millions of standard cells, and the standard cell layout method is used in the design of large-scale digital integrated circuits. has become an important issue in

SUMMARY OF THE INVENTION To solve the conventional technical problems, the object of the present invention is to provide a digital integrated circuit layout method and a terminal device by discrete optimization.

Technical features of the present invention are as follows.

A layout method for a digital integrated circuit by discrete optimization, the digital integrated circuit comprising a substrate, the substrate comprising a plurality of standard cells, the layout method for a digital integrated circuit by discrete optimization comprising:
pre-randomly forming a first layout of position discrete codes of a predetermined number of standard cells and forming a second layout in which layout conflicts are eliminated by adjusting each first layout;
obtaining a first connecting line total length of each second layout, and obtaining each third layout by optimizing for each second layout with the first connecting line total length and a discrete optimization method;
obtaining a fourth layout by locally optimizing each third layout by greedy algorithm, and respectively calculating the total length of the second connecting line of each fourth layout;
obtaining an optimized layout among all the fourth layouts according to the total length of all second connection lines obtained by calculation, and arranging the standard cells on the substrate according to the optimized layout.

In the method for layout of a digital integrated circuit by discrete optimization, a first layout of position discrete codes of the predetermined number of standard cells is formed randomly in advance, and layout conflicts are eliminated by adjusting the first layout. Specifically, the step of forming a second layout includes:
pre-randomly forming a first layout of positional discrete codes of a predetermined number of standard cells;
allowing any two standard cells in the first layout to have c _i ≠c _j such that y _i =y _j when c _i and c _j satisfy x _i =x _j ; x _i and x _j are the column positions of the standard cells in the first layout and y _i and y _j are the row positions of the standard cells in the first layout;
If so, obtaining a second layout by moving the standard cell at the _xjth column in the _yith row to the right one column and repeating the steps until the first layout contains no layout conflicts. including.

In the method for layout of a digital integrated circuit by discrete optimization, the step of randomly forming a first layout of the position discrete code of the predetermined number of standard cells in advance includes:
The step of making the layout code of the standard cells into a 2m-dimensional vector P _i with a preset quantity n, where m is the quantity of standard cells and i=1, 2, . . . , n; and
obtaining a position set of standard cells by performing reverse coding on the vector _Pi , and determining the first layout according to the position set.

In the method for layout of a digital integrated circuit by discrete optimization, the step of obtaining a position set of standard cells by reverse coding the vector _Pi and determining the first layout by the position set is specifically: to the
forming a sub-vector P _i ={P _x |P _y } by taking the front m values and the rear m values in P _i , where the number in P _x and P _y is one corresponding steps, and
forming a row position vector Y by ordering the numbers in P _y and inserting into the same sub-vector P _xy those numbers whose numbers in P _x match the row position;
obtaining said first layout by forming a column position sub-vector _Xy by ordering the values in each _Pxy and forming a column position vector X by merging all _Xy ; including.

In the method for layout of a digital integrated circuit by discrete optimization, obtaining a first connection line total length of each second layout, and optimizing for each second layout according to the first connection line total length and the discrete optimization method. Specifically, the step of obtaining each third layout by doing
obtaining a preset set of connecting lines, and obtaining a first connecting line total length of each second layout according to the set of connecting lines;
determining a fitness function value of a second layout according to the total length of the first connection line;
obtaining each third layout by optimizing for each second layout by the fitness function value and a discrete optimization method.

In the method for layout of a digital integrated circuit by discrete optimization, a fourth layout is obtained by locally optimizing each third layout according to the greedy algorithm, and the total length of the second connection lines of each fourth layout is determined. Specifically, each calculation step is
In any standard cell c _i ( _xi , y _i ) in the third layout, the connectivity D _upper (c _i ) of the higher unit and the connectivity D _lower (c _i ) of the lower unit of c _i according to a preset rule and calculating
When D _upper (c _i )>D _lower (c _i ), after moving c _i up by one line, calculate the total length of the third connection line in the third layout, and the total length of the third connection line is equal to the total length of the third connection line in the second connection If less than the total line length, after moving c _i up one line, calculate the connectivity D _upper (c _i ) of the higher unit and the connectivity D _lower (c _i ) of the lower unit multiple times, and vice versa: calculating the connectivity D _right (c _i ) of the higher level unit and the connectivity D _left (c _i ) of the lower level unit;
When D _upper (c _i )<D _lower (c _i ), after moving c _i down one row, calculate the total length of the third connecting line in the third layout, and the total length of the third connecting line is equal to the total length of the third connecting line in the second connection When less than the line length, after moving c _i down one row, calculate the connectivity D _upper (c _i ) of the higher unit and the connectivity D _lower (c _i ) of the lower unit multiple times, and vice versa: calculating the connectivity D _right (c _i ) of the higher level unit and the connectivity D _left (c _i ) of the lower level unit;
When D _right (c _i )>D _left (c _i ), after moving c _i to the right row, calculate the total length of the third connection line in the third layout, and the total length of the third connection line is the second connection When it is smaller than the total length of the line, after changing the positions of c _i and the standard cells in the row on the right side, the connectivity D _right (c _i ) of the high-order unit and the connectivity D _left (c _i ) of the low-order unit are repeated several times. calculating and vice versa searching for all standard cells by moving to the next standard cell;
When D _right (c _i )<D _left (c _i ), after moving c _i to the left row, calculate the total length of the third connecting line in the third layout, and the total length of the third connecting line is the second connection When it is smaller than the total length of the line, after changing the positions of c _i and the standard cells in the row on the left side, the connectivity D _right (c _i ) of the high-order unit and the connectivity D _left (c _i ) of the low-order unit are repeated several times. and vice versa, obtaining a fourth layout by searching all standard cells by moving to the next standard cell, and calculating the second connecting line total length of each fourth layout. .

In the method for layout of a digital integrated circuit by discrete optimization, obtaining an optimized layout in all fourth layouts according to the total length of all the second connection lines obtained by the calculation, and using the optimized layout to form a standard cell on a substrate. Specifically, the step to place it on the top is
obtaining an iteration count corresponding to the fourth layout, and comparing the iteration count with a preset iteration count;
When the number of iterations is equal to the preset number of iterations, obtaining an optimized layout in all fourth layouts according to the total length of all the second connection lines obtained by calculation, and arranging the standard cells on the substrate according to the optimized layout. and placing the

In the method for layout of a digital integrated circuit by discrete optimization, obtaining an optimized layout in all fourth layouts according to the total length of all the second connection lines obtained by the calculation, and using the optimized layout to form a standard cell on a substrate. in the placing on top step, when the number of iterations is less than the preset number of iterations, the fourth layout is changed to the first layout and returning to the step of adjusting the first layout, wherein the number of iterations reaches the preset number of iterations; Further comprising stopping the step when it is reached.

A computer-readable storage medium, said computer-readable storage medium storing one or more programs, said one or more programs being executed by one or more processors. performs the steps in any one of the methods for layout of a digital integrated circuit by discrete optimization.

a terminal device, said terminal device comprising a processor, a memory and a bus;
the memory stores a computer readable program executed by the processor;
the bus is responsible for communication between the processor and memory;
The processor performs the steps in any one of the digital integrated circuit layout methods by discrete optimization by executing a computer readable program.

The present invention provides a digital integrated circuit layout method and terminal device by discrete optimization. The method for layout of a digital integrated circuit by discrete optimization includes randomly forming a first layout of a predetermined number of standard cell position discrete codes in advance, and adjusting each first layout to eliminate layout conflicts. forming a second layout; obtaining a first connecting line total length for each second layout; obtaining a third layout; obtaining a fourth layout by locally optimizing each third layout with a greedy algorithm, and respectively calculating the total length of the second connecting line of each fourth layout; obtaining an optimized layout among all fourth layouts according to the total length of all second connection lines obtained by calculation, and arranging the standard cells on the substrate according to the optimized layout. The present invention can improve the performance of the optimized layout and reduce the difficulty of the layout by attaching a positional discrete code to the standard cell and optimizing the layout by the discrete optimization method.

FIG. 2 is a diagram showing the layout of a standard cell of a digital integrated circuit; FIG. 1 is a flow diagram illustrating a method for laying out a digital integrated circuit according to the discrete optimization of the present invention; Fig. 4 is a flow chart of determining layout positions by reverse coding in a method for laying out a digital integrated circuit by discrete optimization according to the present invention; Fig. 4 is a flow chart showing comparing rows by greedy algorithm in the layout method of digital integrated circuit by discrete optimization of the present invention; Fig. 4 is a flow chart showing comparing columns by greedy algorithm in the layout method of digital integrated circuit by discrete optimization of the present invention; 1 is a principle diagram showing the structure of a preferred embodiment of the self-starting control system of the present invention; FIG.

The present invention provides a digital integrated circuit layout method and terminal device by discrete optimization. In order that the objects, technical features and effects of the present invention can be clearly understood in detail, the embodiments of the present invention will be described in more detail below with reference to the drawings. The following specific examples illustrate the invention without, however, limiting it.

In the specification of the present invention, unless otherwise specified, terms such as "one", "one", "said" and "the" in this specification include not only one item, It can also contain multiple items. The term "comprising" in the specification of the present invention means including features, integers, steps, operations, components and/or modules, but includes one or more features, integers, steps, operations, components and/or can also mean that there are or further include combinations of modules. It should be noted that when a component is "coupled" or "connected" to another component, the component may be directly coupled or connected to the other component or indirectly coupled to the other component through an intermediate component. or can be connected. A "coupling" or "connection" in this specification can be a wireless coupling or a wireless connection. The term "and/or" in this specification can be meant to include any one or more, any combination or all of the item or items concerned. .

In the specification of the present invention, unless otherwise specified, the terms (including technical and scientific terms) in this specification refer to terms commonly used by those skilled in the art. It should be noted that the terms in the present invention and the prior art can refer to the meaning of terms listed in dictionaries, but if there is a special definition, it refers to the specially defined meaning. can be done.

The technical features of the present invention will be described in more detail below with reference to the drawings and specific embodiments.

A layout method for a digital integrated circuit by discrete optimizing is provided in an embodiment of the present invention. As shown in FIG. 2, the method includes the following steps.

In step S10, first layouts of position discrete codes of a predetermined number of standard cells are randomly formed in advance, and layout conflicts are eliminated by adjusting each first layout. Form two layouts.

Specifically, the digital integrated circuit includes a substrate, and the area of the substrate is s=h×w, where h is the height of the substrate and w is the width of the substrate. A plurality of standard cells are arranged on the substrate, a set of the standard cells is expressed as C _{= {} c1,c2,..., _cm }, and the number of the standard cells is m. , a set of connection lines included in the digital integrated circuit is denoted by E={e ₁ ,e ₂ ,...,e _p }, and the number of connection lines is p. Two standard cells are connected to each connection line in the set of connection lines, or two standard cells and a predetermined interface are connected to each connection line.

After determining the standard cells and connection lines to be arranged in the digital integrated circuit, a predetermined number of first layouts are randomly formed toward the digital integrated circuit. A discrete code is employed to represent the position of each standard cell in the first layout. That is, the position where each standard cell in the first layout is located in the first layout is represented by one two-dimensional coordinate, and the row position of the place where the standard cell is located in the first layout. and the column position can be expressed. A row position corresponding to each standard cell can be represented by a discrete code, and a column position corresponding to each standard cell can also be represented by a discrete code.

In this embodiment, the step of randomly preforming a first layout of position discrete codes of a predetermined number of standard cells and forming a second layout in which layout conflicts are eliminated by adjusting the first layout includes: Specifically, it includes the following steps.

In step S21, a first layout of position discrete codes of a predetermined number of standard cells is randomly preformed.

In step S22, let c _i ≠c _j for any two standard cells in the first layout, and let y _i =y _j when c _i and c _j satisfy x _i =x _j . x _i and x _j are the column positions of the standard cells in the first layout, and y _i and y _j are the row positions of the standard cells in the first layout.

In step S23, when it is satisfied, the second layout by moving the standard cell at the _xjth column in the _yith row to the right by one column and repeating the steps until the first layout contains no layout conflicts. to get

Specifically, the position discrete code of the standard cell in the first layout can be obtained by randomly forming a 2m-dimensional vector and then performing reverse coding on the 2m-dimensional vector. . Specifically, the step of randomly preforming the first layout of the position discrete code of the predetermined number of standard cells includes the following steps.

The layout code of the standard cell is set in a 2m-dimensional vector P _i with a preset quantity n. m is the number of standard cells, i=1, 2, . . . , n.

A position set of standard cells is obtained by performing reverse coding on the vector _Pi , and the first layout is determined by the position set.

The 2m-dimensional vector P _i is denoted as P _i ={r _x1 ,r _x2 ,...,r _xm , _ry1 , _ry2 ,..., _rym }, and the value of the vector P _i is Randomly forming each vector P _i which is randomly formed and uniformly spaced positive integers and whose predetermined quantity is n according to the method. That is, obtain an evolutionary population ps={P ₁ , P ₂ , . . . , P _n } of the digital integrated circuit layout. After obtaining the vector P _i , reverse coding is performed on the vector P _i , and the position set of standard cells is determined by the reverse coding. As shown in FIG. 3, the step of obtaining a position set of standard cells by reverse coding the vector P _i and determining the first layout according to the position set specifically includes the following steps.

Form a sub-vector P _i ={P _x |P _y } by taking the front m values and the rear m values in P _i . The numbers in P _x and P _y correspond one by one.

A row position vector Y is formed by ordering the numbers in P _y and inserting those numbers whose row position matches the number in P _x into the same subvector P _xy .

_Obtain the first layout by forming a column position sub-vector _Xy by ordering the values in each _Pxy and forming a column position vector X by merging all Xy.

Specifically, for any Pi in ps, take the front m values and the rear m values in Pi, and let the front m values be P _{x = {} r _x1 ,r _x2 , ..., r _xm } and let the rear m values be P _y ={r _y1 ,r _y2 ,...,r _ym }. Said P _x and P _y thereby form a sub-vector P _i ={P _x |P _y }. The arrangement positions of the _m standard cells are determined by corresponding the numerical values in Px and _Py one by one in the order of arrangement. After obtaining the sub-vector P _i ={P _x |P _y }, form the row position vector Y by ordering the values in P _y . Y is Y={y _i =rank(r _yi ),r _yi εP _y }, in particular, when r _yi =r _yj , rank(r _yi )=rank(r _yj ).

After obtaining the position vector, for any r _xi ,r _xj ∈P _x , if there exists a row number match, ie y _i =y _j , then convert said r _xi ,r _xj to the same sub-vector P _xy ={ r _xi ,r _xj ,...}. That is, when the number of rows of each element in _Pxy matches, a plurality of _Pxy are obtained in order. The quantity of P _xy is Y, where Y is the quantity of vectors with different numbers of rows. After obtaining P _xy , form the column position sub-vector X _y by ordering the values in P _xy . When X _y is X _y ={x _i =rank(r _xi ),r _xi εP _xy } and r _xi =r _xj ,y _i =y _j then rank(r _xi )=rank(r _xj ). Finally, get the column position vector X by merging all Xy, get the position set _{ X, _Y } of Pi, and get the first layout by said position set {X,Y}. Each standard cell in the first layout contains no gaps.

In step S20, obtain a first connecting line total length of each second layout, and obtain each third layout by optimizing for each second layout with the first connecting line total length and a discrete optimization method. do.

The total length of the first connection line means the total length of each connection line in the second layout. when obtaining the total length of the first connecting line, calculating the length of each connecting line of the P connecting lines included in the second layout by the half-perimeter method, and obtaining the total length of the first connecting line according to the length of the connecting line; can do. After obtaining the total length of the first connection line, the total length of the first connection line is taken as a fitness function value, and the fitness function value and the discrete optimization method are optimized for each second layout. Said discrete optimization methods can be Discrete differential evolution (DDE) with constraints and Discrete particle swarm optimization (DPSO), etc. The limitations of the optimization method according to the discrete optimization method are as follows.

In this formula, h _cell is the height of the standard cell, w _x,y is the width of the x standard cell in the yεY row, and Y is the row position of m standard cells. .

In an embodiment of the present invention, each third The step of obtaining the layout specifically includes the following steps.

In S21, obtaining a preset set of connection lines, and obtaining a first connection line total length of each second layout according to the set of connection lines.

In S22, the fitness function value of the second layout is determined according to the total length of the first connection line.

In S23, each third layout is obtained by optimizing each second layout according to the fitness function value and the discrete optimization method.

Specifically, the total length of the connection line is taken as a fitness function value, and the fitness function value is as follows.

において、ｅ_ｉは第二レイアウト中の各接続線の長さを表記する。 Said

, _ei denotes the length of each connecting line in the second layout.

In step S30, obtain a fourth layout by locally optimizing each third layout by a greedy algorithm, and calculate the second connecting line total length of each fourth layout respectively.

Specifically, after obtaining the third layout, the total length of the connecting line is minimized according to the target, and the third layout is adjusted by the greedy algorithm to obtain the fourth layout with the smallest total length of the connecting line. Obtaining a fourth layout by locally optimizing each third layout according to the greedy algorithm, and calculating the total length of the second connecting line of each fourth layout, respectively, as shown in FIGS. specifically includes the following steps:

In any standard cell c _i ( _xi , y _i ) in the third layout, the connectivity D _upper (c _i ) of the higher unit of c _i and the connectivity D _lower ( Calculate c _i ).

When D _upper (c _i )>D _lower (c _i ), calculate the total length of the third connecting line in the third layout after moving c _i up one line. When the total length of the third connection line is smaller than the total length of the second connection line, after moving c _i up by one row, the connectivity D _upper (c _i ) of the higher unit and the connectivity D _lower (c _i ) of the lower unit are Compute multiple times, and vice versa, compute the connectivity D _right (c _i ) of the higher unit and the connectivity D _left (c _i ) of the lower unit.

When D _upper (c _i )<D _lower (c _i ), calculate the total length of the third connecting line in the third layout after moving c _i down one line. When the total length of the third connecting line is smaller than the total length of the second connecting line, after moving c _i downward by one row, the connectivity D _upper (c _i ) of the higher unit and the connectivity D _lower (c _i ) of the lower unit are Compute multiple times, and vice versa, compute the connectivity D _right (c _i ) of the higher unit and the connectivity D _left (c _i ) of the lower unit.

When D _right (c _i )>D _left (c _i ), calculate the total length of the third connection line of the third layout after moving c _i to the right column. When the total length of the third connection line is smaller than the total length of the second connection line, after changing the positions of c _i and the standard cells in the row on the right side, the connectivity D _right (c _i ) of the higher unit and the connectivity of the lower unit Search all standard cells by calculating D _left (c _i ) multiple times and moving to the next standard cell in the opposite case.

When D _right (c _i )<D _left (c _i ), calculate the total length of the third connecting line of the third layout after moving c _i to the left one column. When the total length of the third connecting line is smaller than the total length of the second connecting line, after changing the positions of c _i and the standard cells in the left row, the connectivity D _right (c _i ) of the higher unit and the connectivity of the lower unit Obtaining a fourth layout by searching all standard cells by calculating D _left (c _i ) multiple times and moving to the next standard cell in the opposite case, and second connection of each fourth layout Calculate the total line length.

Specifically, in the standard cell c _i (x _i , y _i ) whose position in the third layout is {x _i , y _j }, the connectivity of the higher units of the standard cell is as follows.

The connectivity of the lower units of the standard cell is as follows.

In this equation, e _k,i is the length of the connecting line between standard cells c _k and c _i .

In the standard cell c _i (x _i , y _i ) whose position in the third layout is {x _i , y _j }, the connectivity of the higher units of the standard cell is as follows.

The connectivity of the lower units of the standard cell is as follows.

In this equation, e _k,i is the length of the connecting line between standard cells c _k and c _i .

In step S40, obtaining an optimized layout among all the fourth layouts according to the total length of all the second connection lines obtained by calculation, and arranging the standard cells on the substrate according to the optimized layout.

Specifically, after obtaining the fourth layouts, the total length of the second connection lines of all the fourth layouts is calculated, and the fourth layouts with the smaller total lengths of the second connection lines are made into the optimized layouts, thereby improving the digital integrated circuit. get layout. In practical application, to improve the accuracy of the digital integrated circuit, after obtaining all the fourth layouts, make the fourth layout the first layout and repeat the optimization to obtain the optimized fourth layout. . The step of obtaining an optimized layout among all fourth layouts according to the total length of all second connection lines obtained by calculation, and arranging the standard cells on the substrate according to the optimized layout specifically includes the following steps.

Obtaining an iteration number corresponding to the fourth layout, and comparing the iteration number with a preset iteration number.

When the number of iterations is equal to the preset number of iterations, obtaining an optimized layout in all fourth layouts according to the total length of all the second connection lines obtained by calculation, and arranging the standard cells on the substrate according to the optimized layout. be placed in

when the number of iterations is less than the preset number of iterations, returning to the step of making the fourth layout the first layout and adjusting the first layout, and stopping the step when the number of iterations reaches the preset number of iterations. .

Specifically, the number of iterations is set in advance, and the number of iterations may be, for example, 10 or the like.

The present invention further provides a computer-readable storage medium according to the digital integrated circuit layout method by discrete optimization. The computer-readable storage medium stores one or more programs, and the one or more programs are executed by one or more processors, according to the embodiments of the present invention. A step in a digital integrated circuit layout method by discrete optimization can be implemented.

According to the digital integrated circuit layout method by discrete optimization, the present invention further provides the following terminal device. As shown in FIG. 6, the terminal device includes at least one processor 20, a display panel 21 and a memory 22. FIG. The terminal device may further include a Communications Interface 23 and a Bus 24 . Processor 20 , display panel 21 , memory 22 and communication interface 23 are communicably connected by bus 24 . A display panel 21 is provided to display the preconfigured guidance interface in the initial configuration model. Information can be transmitted through the communication interface 23 . Processor 20 can use the logic instructions in memory 22 to implement the digital integrated circuit layout method by discrete optimization according to the foregoing embodiments of the present invention.

The logic instructions in said memory 22 can be executed by software units. When sold or used as a stand-alone product, the logic instructions in memory 22 can be stored on a computer readable storage medium.

Memory 22 is a computer-readable storage medium provided to store software programs, computer-executable programs, such as program instructions or program modules, in accordance with an embodiment of the present invention. Processor 20 performs predetermined functions and processes data by executing software programs, program instructions, or program modules stored in memory 22 . For example, the method for layout of a digital integrated circuit by discrete optimization according to the embodiment of the present invention can be implemented.

Memory 22 may include program storage areas and data storage areas. The program storage area stores an operating system, an application program that performs at least one function, and the data storage area can store data generated by use of the terminal, and the like. Memory 22 may include high speed random access memory or non-volatile memory. For example, a USB flash disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk, write disk, or other medium that stores the program code or a temporary storage medium.

The specific process of executing the plurality of instructions in the storage medium and the terminal device by the processor can refer to the layout method of the digital integrated circuit according to the discrete optimization, so it will not be described again here.

It should be noted that the above examples illustrate the technical matters of the present invention, but do not limit the present invention. Although the technical features of the present invention have been described in detail with reference to the examples of the present invention, the above examples are only examples of the present invention, and the present invention is limited only to the configurations of the above examples. not a thing Engineers in this technical field can make design changes, substitutions, etc. within the scope of the present invention, and such changes are, of course, included in the present invention.

20 processors
21 Display panel
22 memory
23 Communication interface
24 bus

Claims (10)

pre-randomly forming a first layout of position discrete codes of a predetermined number of standard cells and forming a second layout in which layout conflicts are eliminated by adjusting each first layout;
obtaining a first connecting line total length of each second layout, and obtaining each third layout by optimizing for each second layout with the first connecting line total length and a discrete optimization method;
obtaining a fourth layout by locally optimizing each third layout by greedy algorithm, and respectively calculating the total length of the second connecting line of each fourth layout;
obtaining an optimized layout among all the fourth layouts according to the total length of all the second connection lines obtained by calculation, and arranging the standard cells on the substrate according to the optimized layout. A method of laying out digital integrated circuits by optimization. Specifically, the steps of randomly preforming a first layout of a predetermined number of standard cell position discrete codes and forming a second layout in which layout conflicts are eliminated by adjusting the first layout include:
pre-randomly forming a first layout of positional discrete codes of a predetermined number of standard cells;
allowing any two standard cells in the first layout to have c _i ≠c _j such that y _i =y _j when c _i and c _j satisfy x _i =x _j ; x _i and x _j are the column positions of the standard cells in the first layout and y _i and y _j are the row positions of the standard cells in the first layout;
When the c _i and c _j satisfy x _i =x _j , moving the standard cell at the x _j th column in the y _{i th} row to the right by one column until the first layout contains no layout conflicts. and obtaining a second layout by repeating . Specifically, the step of randomly preforming a first layout of the position discrete code of the predetermined number of standard cells includes:
The step of making the layout code of the standard cells into a 2m-dimensional vector P _i with a preset quantity n, where m is the quantity of standard cells and i=1, 2, . . . , n; and
obtaining a position set of standard cells by performing reverse coding on the vector _Pi , and determining the first layout according to the position set. method of layout of digital integrated circuits by computerization. Specifically, the step of obtaining a position set of standard cells by reverse coding the vector P _i and determining the first layout according to the position set includes:
forming a sub-vector P _i ={P _x |P _y } by taking the front m values and the rear m values in P _i , where the number in P _x and P _y is one corresponding steps, and
forming a row position vector Y by ordering the numbers in P _y and inserting into the same sub-vector P _xy those numbers whose numbers in P _x match the row position;
obtaining said first layout by forming a column position sub-vector _Xy by ordering the values in each _Pxy and forming a column position vector X by merging all _Xy ; 4. The layout method of digital integrated circuit by discrete optimization as claimed in claim 3, characterized by comprising: The step of obtaining each third layout by obtaining a first connecting line total length of each second layout and optimizing for each second layout with the first connecting line total length and a discrete optimization method is specifically: in general,
obtaining a preset set of connecting lines, and obtaining a first connecting line total length of each second layout according to the set of connecting lines;
determining a fitness function value of a second layout according to the total length of the first connection line;
obtaining each third layout by optimizing for each second layout by the fitness function value and the discrete optimization method. A layout method for integrated circuits. The steps of obtaining a fourth layout by locally optimizing each third layout by the greedy algorithm, and respectively calculating the total length of the second connecting line of each fourth layout are specifically:
In any standard cell c _i ( _xi , y _i ) in the third layout, the connectivity D _upper (c _i ) of the higher unit and the connectivity D _lower (c _i ) of the lower unit of c _i according to a preset rule and calculating
When D _upper (c _i )>D _lower (c _i ), after moving c _i up by one line, calculate the total length of the third connection line in the third layout, and the total length of the third connection line is equal to the total length of the third connection line in the second connection If less than the total line length, after moving c _i up one line, calculate the connectivity D _upper (c _i ) of the higher unit and the connectivity D _lower (c _i ) of the lower unit multiple times, and vice versa: calculating the connectivity D _right (c _i ) of the higher level unit and the connectivity D _left (c _i ) of the lower level unit;
When D _upper (c _i )<D _lower (c _i ), after moving c _i down one row, calculate the total length of the third connecting line in the third layout, and the total length of the third connecting line is equal to the total length of the third connecting line in the second connection When less than the line length, after moving c _i down one row, calculate the connectivity D _upper (c _i ) of the higher unit and the connectivity D _lower (c _i ) of the lower unit multiple times, and vice versa: calculating the connectivity D _right (c _i ) of the higher level unit and the connectivity D _left (c _i ) of the lower level unit;
When D _right (c _i )>D _left (c _i ), after moving c _i to the right row, calculate the total length of the third connection line in the third layout, and the total length of the third connection line is the second connection When it is smaller than the total length of the line, after changing the positions of c _i and the standard cells in the row on the right side, the connectivity D _right (c _i ) of the high-order unit and the connectivity D _left (c _i ) of the low-order unit are repeated several times. calculating and vice versa searching for all standard cells by moving to the next standard cell;
When D _right (c _i )<D _left (c _i ), after moving c _i to the left row, calculate the total length of the third connecting line in the third layout, and the total length of the third connecting line is the second connection When it is smaller than the total length of the line, after changing the positions of c _i and the standard cells in the row on the left side, the connectivity D _right (c _i ) of the high-order unit and the connectivity D _left (c _i ) of the low-order unit are repeated several times. and vice versa, obtaining a fourth layout by searching all standard cells by moving to the next standard cell, and calculating the second connecting line total length of each fourth layout. 2. The layout method of digital integrated circuit by discrete optimization as claimed in claim 1, characterized in that: Specifically, the step of obtaining an optimized layout among all the fourth layouts according to the total length of the second connection lines obtained by the calculation, and arranging the standard cells on the substrate according to the optimized layout includes:
obtaining an iteration count corresponding to the fourth layout, and comparing the iteration count with a preset iteration count;
When the number of iterations is equal to the preset number of iterations, obtaining an optimized layout in all fourth layouts according to the total length of all the second connection lines obtained by calculation, and arranging the standard cells on the substrate according to the optimized layout. 2. The method of laying out a digital integrated circuit by discrete optimization as claimed in claim 1, further comprising the step of: The step of obtaining optimized layouts in all fourth layouts from all the second connection line lengths obtained by the calculation, and arranging standard cells on a substrate according to the optimized layouts is performed when the number of iterations is the predetermined further comprising the step of changing the fourth layout to the first layout and returning to the step of adjusting the first layout when the number of iterations is less than a set number of iterations, and stopping the step when the number of iterations reaches a preset number of iterations. 8. The layout method for digital integrated circuits by discrete optimization as claimed in claim 7. A computer-readable storage medium, said computer-readable storage medium storing one or more programs, said one or more programs being executed by one or more processors. A computer-readable storage medium for implementing the steps in the method for layout of a digital integrated circuit by discrete optimization according to any one of claims 1-8. a terminal device, said terminal device comprising a processor, a memory and a bus;
the memory stores a computer readable program executed by the processor;
the bus is responsible for communication between the processor and memory;
A terminal device characterized in that the processor executes the steps in the layout method for a digital integrated circuit by discrete optimization according to any one of claims 1 to 8 by executing a computer-readable program. .

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