JP2008299641A - Parallel solving method of simultaneous linear equations and node sequencing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a node sequencing method for parallel calculation of simultaneous linear equations and a parallel solving method of simultaneous linear equations, capable of executing solving of simultaneous linear equations that is calculation for large-scale system network with real time performance. <P>SOLUTION: For a radial system part, node sequencing is performed by optionally selecting a node to be sequenced first from nodes with minimum branch number connected thereto and performing the following node selection in order in the ascending order of the branch number connected to the node while preferentially selecting a node of node sequencing candidate when the node of node sequencing candidate and a counter end node thereof are nodes not matched with the counter end nodes of sequenced nodes. For a loop-like system part, simulation of the generation number of new non-zero elements which are generated in contraction of nodes is performed by parallel processing, and node sequencing is performed by performing node selection in the ascending order of the new non-zero element generation number while preferentially selecting a node of node sequencing candidate when the node of node sequencing candidate and a counter end node thereof are nodes matched to the counter end nodes of sequenced nodes. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to parallel calculation of simultaneous linear equations appearing in power system calculations, and more particularly to a node ordering method capable of processing parallel calculations at high speed and parallel calculation of forward erasure / backward substitution processing.

  Conventionally, as a method of solving simultaneous linear equations, a direct solution method using trigonometric decomposition is known. When this method is used, solving of simultaneous linear equations involves (1) ordering of nodes and (2) triangular decomposition of coefficient matrix. Three processes are performed: (LDU decomposition) and (3) solution calculation by forward / backward substitution calculation. In addition, parallel computation is used for fast solution of simultaneous linear equations. In parallel calculation, processing is distributed to a plurality of CPUs for calculation, and data exchange between CPUs is performed through communication processing.

  The conventional parallel calculation of simultaneous linear equations is based on creating a tree of forward / backward substitution processing, and at that time, the node ordering method becomes important. In the conventional method, based on the Tinney 2 method, the number of connected branches is selected at a certain stage (each step in parallel processing is referred to as a stage) by selecting from those having a small number of fill-in (non-zero elements) generated by erasing nodes. If two or less nodes are erased, nodes with 3 or more connected branches are not erased in the relevant stage, and nodes that are erased in the same stage within a range from a certain node to 2 branches If there is, the node is not erased (see Non-Patent Document 1).

Masayuki Nagata, Naoyuki Uchida “Development of Parallel Processing Algorithm for Systematic Calculation for Acceleration of Transient Stability Calculation” IEEJ Transactions B, Vol. 120, No. 2, 2000 Hisao Taoka, Shigeru Abe "High-speed solving method of simultaneous linear equations suitable for pipeline processing and its application to power system analysis" IEEJ Transaction B, Vol. 105, No. 5, 1985

  A conventional node ordering method for parallel calculation of simultaneous linear equations is selected when the number of fill-ins generated by node erasure is small, and a node having two or less connected branches is erased at a certain stage. Does not delete nodes with 3 or more connected branches at this stage, and if there is a node to be deleted at the same stage in a range from a certain node to 2 branches, the node is not deleted. Further, in order to assign the processing obtained as a result of the node ordering to each CPU, a balance is made between the reduction in the number of communications and the equalization of calculation processing among the CPUs.

  The conventional method applies the Tinney 2 method to node ordering as described above, and is optimal for a radial system, but not optimal for a loop system, and fill− in increases, processing performance deteriorates, processing for assigning parallel computations to each CPU takes time, and overhead of parallel processing increases. Since the CPU processing amount is determined in consideration of the CPU processing amount, there is a problem that CPU resources are wasted. Because of these problems, and the real-time performance required for application to training simulators other than system analysis work performed offline, online power supply automation systems, etc., conventional methods are in this field. There was a problem that it was difficult to apply.

  The present invention has been made in view of the above, and a node ordering method for parallel calculation of simultaneous linear equations and simultaneous linear that can solve a simultaneous linear equation that is a network calculation of a large-scale system with real-time performance. The purpose is to obtain a parallel solving method of equations.

  In order to solve the above-described problems and achieve the object, a node ordering method according to the present invention has a symmetric multi-CPU configuration having a plurality of CPUs and a shared memory accessible to the CPUs in common. Used in parallel calculation of a solution of simultaneous linear equations in power system analysis based on triangulation of coefficient matrix, forward elimination process, and backward substitution process using a parallel computing device, and the structure of the coefficient matrix and the forward A node ordering method for expressing a procedure of erasure processing and backward substitution processing as a tree composed of nodes and branches connecting the nodes, and belongs to a radial system portion that is a system portion not including a loop in the tree A first step of node ordering for the nodes, and a system part other than the radial system part in the tree And a second step of performing node ordering for nodes belonging to the loop-like system part, wherein in the first step, the first node to be ordered has the smallest number of branches connected to that node. Select any node from the nodes, and then select nodes from the node ordering candidate nodes in order from the node with the fewest number of branches connected to each node. Based on the selection criterion that the adjacent node that is an adjacent node is a node that does not match the other node of the already ordered node, the node ordering candidate node is preferentially selected. Node ordering is performed, and in the second step, the plurality of CPUs are used to A simulation of the number of new non-zero element occurrences occurring at the time of contraction of nodes in forward erasure processing is performed in parallel processing, and a node ordering is selected from the nodes with a low number of new non-zero element occurrences obtained by the simulation. When a candidate node and a partner node that is an adjacent node connected via a branch are nodes that do not match a partner node of a node that has already been ordered, that node is selected with priority. Node ordering is performed for the plurality of CPU units based on a selection criterion.

  According to the node ordering method of the present invention, there is an effect that the execution efficiency of parallel processing in forward erasure / backward substitution processing can be improved, and the processing performance can be increased. ) Can be executed with real-time performance.

  Embodiments of a parallel solution method and a node ordering method for simultaneous linear equations according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing a configuration of a training simulator to which the present embodiment is applied. In FIG. 1, first, a trainer sets up a training management server group 1 and a trainer table 4 for a training scenario including a system configuration state, a generator / load condition, an accident occurrence condition, and the like, which are training problems for performing training. Use to create and register. Next, at the time of training, the trainer selects a training scenario registered from the trainer table 4 and executes it in real time. Along with this, a system simulation is executed in the system simulation server group 2 and the calculation result is obtained. It is displayed on the trainer table 4, the traini table 5, and the large screen system panel 6. Trainees (trainees) use the automated simulation server group 3, trainee table 5, and large screen system board 6 to confirm and grasp the accident occurrence status, recovery commands for recovery operations, recovery operations, etc. To restore the load that caused the power failure. On the other hand, the system simulation during the training is executed by the system simulation server group 2, but the software that simulates the static and dynamic characteristics of the system to which this embodiment is applied is the system simulation server group 2. Implemented and works. Transmission / reception of information among the training management server group 1, the system management server group 2, and the automation server server 3 and data transmission to the trainer table 4, the traini table 5 and the large screen system panel 6 are performed via the system LAN 7. Do it.

  FIG. 2 is a diagram illustrating an example of a computer configuration used for parallel solution of simultaneous linear equations according to the present embodiment. As shown in FIG. 2, the computer in the present embodiment is a computer having a symmetric multi-CPU configuration, for example, a plurality of CPUs CPU1 (8), CPU2 (9), CPU3 (10),. , CPUn (11) and a shared memory 12 that can be commonly accessed by the CPUs. Here, n is an arbitrary integer of 2 or more. Each CPU is mounted with a cache memory, a local memory, and an external storage device, and is connected to the system LAN 7.

  FIG. 3 is a flowchart showing a processing example of dynamic stability calculation that is implemented in the system simulation server group 2 and performs system simulation. The dynamic stability calculation alternately solves the network equation and the generator differential equation every integral step (usually 10 msec), and generates the power system bus voltage, phase angle, frequency, active power, reactive power, and Calculate the internal phase angle of the generator.

  In FIG. 3, first, initialization processing (step S13), Y matrix creation, and triangulation (step S14) are sequentially performed as initial processing. Here, the Y matrix is a coefficient matrix of a network equation. Next, the network network equation is solved. First, it is determined whether or not there is a system configuration change (step S15), and if there is no change, the process branches to step S17. If there is a change, the Y matrix is corrected and triangulated (step S16). Subsequently, the generator equivalent current source, which is the current term of the network equation, is calculated (step S17) and the nonlinear load equivalent current source. (Step S18) and the solution of the network equation (Step S19) is obtained using the results of Steps S16, S17, and S18 to obtain the bus voltage. Then, determination is made on the convergence (V) of the bus voltage (V) of the network as the calculation result. If not converged, the process branches to step S18, and the equivalent current of the nonlinear load is branched using the calculated bus voltage. The source is calculated (step 18), and the solution of the network equation (step S19) is repeated. If the solution of the network equation is converged, then the differential equation of the generator is solved.

  First, the generator oscillation equation is solved (step S21), the generator internal phase angle is calculated, then the generator AVR (automatic voltage regulator), governor control system, and generator armature circuit Etc., the generator differential equation is solved (step S22), the generator internal voltage is calculated, and the internal voltage (V) convergence (step S23) of the generator is determined. If not converged, the process branches to step S17, and the solution of the network network equation and the solution of the generator differential equation are repeated. When the voltage of the circuit network and the internal voltage of the generator converge, the calculation time of dynamic stability calculation is updated (step S24), and the calculation end (step S25) is determined and the calculation end time is not reached. In this case, the process branches to step S15, and the solution of the network network equation and the solution of the generator differential equation are repeated. If the calculation end time has been reached, the process ends. The parallel calculation method for simultaneous linear equations according to the present embodiment is applied to process the solution of the network equation (step S19) at high speed.

  Next, in order to clarify the difference between the present embodiment and the conventional technique, a conventional parallel processing algorithm for system calculation described in Non-Patent Document 1 will be described.

Also in the conventional method, a parallel computer (multi-CPU) is assumed as a computer, and data exchange between CPUs is assumed to be performed by communication processing. In addition, as a method of solving the simultaneous linear equations, a direct solution method using triangular decomposition is used. When using this method,
y = A · x (1)
The simultaneous linear equation is solved by the following three processes.
(1) Node ordering (2) Triangular decomposition (LDU decomposition) of coefficient matrix A
(3) Calculation of x by forward / backward substitution calculation

Stability calculation is composed of system calculation (network calculation) and generator differential equation solution, system calculation accounts for about 40% of the total, of which forward / backward substitution calculation accounts for about 60%, and Multiple calculations are performed. In addition, since the triangulation and forward / backward substitution processing are automatically determined when the node ordering is determined, how to order the nodes is the key to speeding up the direct method in the sequential processing. The forward substitution process in the direct solution of simultaneous linear equations is
xj = xj + xi · Dij (2)
The calculation (2) is a process of deleting the branch Dij connecting the node i and the node j and changing the value of the node j (Dij in the expression (2) is a triangle) Diagonal elements in decomposition (LDU decomposition).) If the branch Dij is deleted for all j with respect to a certain node i, the value xi of the node i is not necessary for the subsequent processing. This corresponds to the erasure of node i. The reverse substitution calculation is the same. For example, in the case of the simple network of FIG. 21A, the processing of the expression (2) is repeated six times for each of forward / backward substitution. The dotted branch in the figure corresponds to fill-in (a non-zero element newly generated by triangulation) resulting from triangulation.

  The forward / backward substitution calculation process can be expressed as a tree structure process as shown in FIG. The horizontal arrow in FIG. 21-2 represents the deletion of a node by forward substitution. Further, the direction of the arrow (from top to bottom) in FIG. 21-2 is the flow of processing in forward substitution. In backward substitution, the tree is traced from the root to the leaf (from bottom to top). It becomes processing.

  In the figure, a portion surrounded by a square means that the node has a plurality of data. For example, when node 1 is deleted, the values of both node 3 and node 5 change, but the value is passed to node 3 with the node number closer to node 1. Therefore, the node 3 has its own data and data for updating the value of the node 5. With this representation method, it is possible to easily grasp what kind of data moves between nodes.

  It should be noted here that the processing of erasing node 1 and erasing node 2 does not affect the calculation result even if the order is changed or they are processed in parallel at the same time. This is because these calculations can be performed independently of each other (no dependency). That is, the horizontal arrows arranged in the tree (deletion of nodes) can be executed in parallel. Therefore, considering node erasure as one processing unit, the forward substitution calculation in the example of FIG. 21-2 is a four-step process in the sequential process, but a three-step process in the parallel process. Become. Hereinafter, each step (simultaneous deletion of a plurality of nodes) in parallel processing is referred to as a stage.

The expression of the forward / backward substitution process using a tree as shown in FIG. 21-2 has been proposed so far, but the tree expression of FIG. 21-2 is more parallel in the forward substitution calculation process than before. The invention has been devised in order to facilitate the extraction of processes that can be executed, and has the following characteristics.
(1) The processing of each stage of the tree always follows the tree from left to right in forward substitution (from right to left in backward substitution), and reverse processing does not occur.
(2) All processing of nodes in the same stage (horizontal arrows) can be performed in parallel.
(3) In the case of parallel processing, for example, in forward substitution, when a node whose value is changed and a node whose value is changed during the node deletion processing are assigned to different CPUs, communication processing occurs. Since this is a horizontal arrow across the CPUs in the tree, the number of communications required for parallel processing can be easily grasped.
(4) It is clearly shown on the tree what kind of data is passed between the nodes. For this reason, the data exchanged by communication at the time of parallel processing can be easily grasped.

  In Non-Patent Document 1, a new node ordering method for parallel processing is devised based on the Tinney 2 method. In order to perform parallel processing of forward / backward substitution calculations efficiently, it is necessary to order so that as many calculations as possible can be executed in parallel. For this purpose, the nodes may be ordered so that the number of stages is as small as possible. Therefore, the ordering of the nodes is performed so that the node erasure process in each stage is as much as possible within a range not interfering with the communication process, and the occurrence of fill-in in the LDU decomposition is minimized. .

  Specifically, the following two selection criteria are provided for the nodes to be erased at each stage.

(1) Select one that has less fill-in generated by erasing the node. However, when a node having two or less connection branches is deleted at a certain stage, a node having three or more connection branches is not deleted at this stage, but is deleted after the next stage.
(2) If there is a node to be erased at the same stage in a range from a certain node to 2 branches, the node is not erased.

  Since the number of fill-ins generated by erasing a node is determined by the number of branches connected to the node, the condition (1) can be satisfied by selecting from the nodes having a small number of connected branches. In addition, if a node with a large number of connected branches is erased at an early stage, the number of fill-in is increased. Therefore, in a stage where a node with two or fewer connected branches is erased, the number of connected branches is three. The above nodes are not deleted.

  Regarding the condition of (2), the reason is as follows. When a node is deleted, the value of the node adjacent to that node is rewritten. If there is a node erased at the same stage from the erased node to the range of 2 branches, there is a possibility that the value is rewritten again. When both of the two rewrites involve a communication process, it is impossible to determine the relationship between the two communication processes. If the scheduling context of the two communication processes is different from the actual context, the communication time will be excessively long, and the communication method between the CPUs of the computers used uses a common bus. In some cases, bus congestion may occur, and a large penalty may occur in communication processing. In order to avoid such inefficiency in communication processing, the condition (2) is provided.

  The node ordering algorithm described above is shown in FIG. 22 (see Non-Patent Document 1). Here, only when there are no nodes with two or less connection branches, a node with three or more connection branches can be selected.

  The ordering of nodes has been described above. This is “a process for extracting a process that can perform parallel processing” from the calculation process of forward / backward substitution, and the process obtained as a result of the ordering is assigned to each CPU. There is a need. Since most of the system analysis calculations are basically processing in node units, Non-Patent Document 1 assigns them to CPUs in node units.

In order to realize efficient parallel processing, it is necessary to consider the following two points.
・ Reduction of communication frequency ・ Equivalent calculation processing among CPUs

  These two purposes are in a trade-off relationship. Therefore, the size of the group of nodes is adjusted when assigning CPUs to the nodes using one parameter (hereinafter referred to as a grouping coefficient) so that the two can be balanced.

  Since the communication process requires more time than the calculation process, it is indispensable to reduce the number of communication as much as possible from the viewpoint of speeding up by parallel processing. Since the communication process is a horizontal arrow across the CPUs on the processing tree, communication is performed at a stage with a large number with few horizontal arrows.

The algorithm for assigning processing to each CPU is as follows.
(1) The forward / backward substitution processing tree is cut at a stage with a large number. However, the number of nodes in the separated branches and leaves should not exceed (total number of nodes) / (grouping coefficient). Each of the separated branches and leaves is made into one group.
(2) From the group boundary lines obtained as a result of (1), (number of CPUs-1) boundary lines are selected and set as the boundary lines for allocation to the CPU. that time,
Σ _i | ni-nTotal / nCPU | (3)
Select the combination of borders that minimizes. Here, ni represents the number of nodes assigned to CPUi, nTotal represents the total number of nodes, and nCPU represents the number of CPUs.

  The method described in Non-Patent Document 1 as described above applies the Tinney 2 method to node ordering, and is optimal for a radial system, but not optimal for a loop system. Processing performance deteriorates due to an increase in fill-in, and it takes time to allocate parallel computations to each CPU, which increases the overhead of parallel processing. The CPU resource is determined in consideration of the balance of the processing amount of each CPU, and there is a problem that CPU resources are wasted. Here, the radial system is a system that does not include a loop structure, and the loop system is a system that includes a loop structure. In an actual system, a power plant or the like is at the end of the system, and therefore a radial system part is always present in the tree. Since such problems and real-time performance are required for application to training simulators other than system analysis work performed offline, online power supply automation systems, etc., the method described in Non-Patent Document 1 Had a problem that it was difficult to apply in this field.

  Therefore, in this embodiment, in order to realize real-time performance, a node ordering method that improves parallel processing of forward erasure / backward substitution processing based on the simultaneous linear equation solving method described in Non-Patent Document 2 is provided. It is disclosed below.

  FIGS. 11A and 11B are flowcharts showing the node ordering method of the present embodiment, and FIG. 11B shows the processing following FIG. In addition, FIG. 11-1 and FIG. 11-2 are connected in the location shown as '1'. In FIG. 11A, first, initialization processing (1) (step S40) is performed to initially set flags, and then a node table such as a partner node number and a partner node number connected to each node is created (step S41) is performed, and the node table rearrangement is performed in the order from the smallest number of counterpart nodes (step S42). When the number of counterpart nodes is the same, rearrangement is performed in the order of the previously processed nodes. The partner node connected to each node refers to an adjacent node connected to each node via a (one) branch. For example, in FIG. 13C, the counterpart node of node 1 is node 5.

  Next, node ordering of the radial system portion is performed first. The radial system part includes a part having one branch connected to a certain node, such as node 1, node 2, node 3, node 4, and node 6 in the radial system of FIG. For such a node, the number of counterpart nodes is also one. For example, when node 1 is arbitrarily selected and ordered, if node 1 is deleted and the branch between node 1 and node 5 is also deleted, the number of connection branches of node 5 becomes one, and the same A structure arises. Then, it is known that optimal node ordering can be performed if the node ordering of the radial system portions is sequentially performed (the concept of the Tinney 2 method). Hereinafter, node ordering is performed based on this feature.

  When forward erasure and backward substitution processing are performed in parallel, each CPU normally performs processing for one node, and therefore, the number of CPUs used for parallel processing (hereinafter referred to as the number of parallel CPUs) is handled at a time. Therefore, it is necessary to perform node ordering for each element processing unit. For this reason, first, in step S43, it is determined whether or not the number of nodes to be simultaneously ordered is equal to or less than the number of parallel CPUs. If No, the element count is initialized by the initialization process (2) (step S44). . In the case of Yes, nothing is processed and the process branches to step S45.

  In step S45, it is determined whether or not the node i to be ordered is a radial system. If Yes, in step S46, it is determined whether or not the node i can be processed in parallel. The determination of whether parallel processing is possible will be described later. If the result of determination in step S46 is Yes, node i is ordered (step S47), various arrays are counted up (1) (step S48), and the process branches to step S43. If the result of the determination in step S46 is No, in this process, the node i is excluded from ordering (step S49), the various arrays are counted up (2) (step S50), and the process branches to step S43.

  In the case of No in step S45, the node table is rearranged in the order of the smaller number of partner end nodes for the nodes that have not been ordered in order to check whether or not the radial system portion as the node to be excluded remains (step S51). ) To perform initialization processing (3) (step S52). Next, with respect to the node after the node table rearrangement, it is determined whether or not the node i is a radial system part (step S53). In the case of Yes, it is further determined whether or not all the radial system parts are to be excluded. (Step S54) is performed, and if the determination result in Step S54 is No, the process branches to Step S46. If the determination result in step S54 is Yes, all the exclusion target nodes are ordered in order (step S55), and the process proceeds to step ‘1’ in FIG. In the case of No in step S53, the process proceeds to the step indicated by "1" in FIG.

  Since the node ordering of the radial system portion has been completed by the above processing, the node ordering of the loop system portion is performed thereafter. For the loop system part, there is no optimal node ordering method. Therefore, the simulation of the generation of new non-zero elements at each node is performed, the order with the least number of new non-zero element occurrences is performed, and it is repeated. It is supposed to be semi-optimized to carry out (concept of Tinney 3 method). Here, node ordering is performed according to the following procedure based on this concept.

  As shown in FIG. 11B, first, initialization processing (4) of various flags and the like is performed in step S56, and then simulation of new non-zero element generation (step S57) is performed for all remaining nodes. Node rearrangement is performed in the order of decreasing number of non-zero elements (step S58). Next, it is determined whether or not the number of ordered nodes is equal to or greater than the number of parallel CPUs (step S59). If Yes, initialization processing (2) (step S60) for the number of ordered arrays is performed, and the process branches to step S61. To do. In No, it branches to step S61, without processing anything. In step S61, it is determined whether or not the node i can be processed in parallel. If yes, the node i is ordered (step S62), the various arrays are counted up (3) (step S63), and then In step S64, it is determined whether or not the ordering of all the nodes has been completed. If No, the various arrays are counted up (4) (step S65), and the process branches to step S57. If the determination result in step S64 is Yes, the process ends. In the case of No in step S61, in this process, node i is excluded (step S66), various arrays are counted up (5) (step S67), and then whether all the remaining nodes are excluded or not is determined. (No in step S68). If No, the various sequences are counted up (6) (step S69), and the process branches to step S59. In the case of Yes in step S68, a simulation of new non-zero element generation (step S70) is performed for the remaining nodes, and node rearrangement (step S71) is performed in the order of the new non-zero element generation number, and Is assigned to the smallest node i (step S72).

  FIG. 12 is a flowchart showing parallel processing of the simulation of new non-zero element generation in FIG. 11-2. In the loop part, for the optimization of node ordering, for all remaining nodes, a simulation is performed to determine how many new nonzero elements are generated when the nodes are ordered. The node with the smallest number is set as the next candidate for the ordering node, and it is determined whether or not the node can be processed in parallel. If parallel processing is possible, the node is ordered, and then the above processing is completed. It repeats until. Therefore, the node ordering of the loop system portion takes processing time. Therefore, for the simulation of new non-zero element generation, parallel processing is performed to increase the processing speed.

  In FIG. 12, it is considered that all nodes in the loop system portion are equally distributed to a plurality of CPUs that perform parallel processing, and the processing is shared. First, calculation of the average processing amount in the case of processing by each CPU (step S73) is performed, and the remainder of the calculation of the average processing amount is calculated (step S74). The CPU 1 takes charge of the surplus processing amount (that is, the CPU 1 takes charge of processing of the average processing amount + the surplus). Next, it is determined whether or not the CPU to be processed is CPU 1 (step S75). If Yes, the processing target (k1, k2) is calculated (step S76), and flags are initialized in the subsequent processing. Processing (step S77) is performed, and the process branches to step S79. In cases other than the CPU 1, the processing target (k1, k2) is calculated (step S78), and the process branches to step S79. In step S79, it is determined whether or not each CPU is ready to execute processing based on whether or not its own CPU processing flag, which is a CPU processing flag for itself, is zero. In the case of Yes in step S79, a new non-zero element generation simulation (step S80) is performed for the processing amount handled by each CPU, and the result is stored in the shared memory. Thereafter, each CPU writes its own CPU number in its own CPU processing flag to indicate to CPU 1 that the processing has been completed (step S81).

  Next, it is determined again whether or not it is CPU 1 (step S 82). In the case of CPU 1, it is determined whether or not the processing flags of all CPUs are positive (step S 83), and the determination result in step S 83 is No. In the case of, check continuously. If the determination result in step S83 is Yes, the CPU calculates the number of new nonzero element occurrences calculated by each CPU, selects the first node with the smallest number (step S84), and then The CPU 1 number is set in the process end flag (step S85), and the process ends. If it is not CPU1 in step S82, it is determined whether or not the process end flag is positive (step S86). If No, the check is continued, and if Yes, the process ends.

  Next, the operation of the present embodiment will be described. In the present embodiment, in order to realize real-time processing for solving simultaneous linear equations described in Non-Patent Document 2, parallel processing can be performed for forward erasure / reverse substitution processing of simultaneous linear equations. The processing efficiency is improved and the processing performance is greatly improved. As shown in FIG. 2, the computer configuration for performing parallel calculation of simultaneous linear equations is assumed to be a symmetric multi-CPU coupled with a shared memory. Is placed in the shared memory, communication means between computers becomes unnecessary, data can be accessed at high speed, and the performance of each CPU can be fully utilized.

  Non-Patent Document 2 is based on the Tinney 2 method as a node ordering method. FIG. 4 is a diagram illustrating a system example described in Non-Patent Document 2, and the numbers in the circles indicate node numbers. FIG. 5 is a diagram showing circuit network equations (simultaneous linear equations) of the system example of FIG. In Non-Patent Document 2, triangulation of a coefficient matrix is performed by the processing flow of FIG. 6, and the result is stored in the table format shown in FIG. In FIG. 6, the process is composed of a triple loop of i, j, and k. In loop i, the processes in steps S26 and S27 are performed, in loop j, the processes in steps S28 and S29 are performed, and in loop k, the steps are performed. The process of S30 is performed. NNmax in FIG. 6 indicates the total number of nodes. In FIG. 7, elements marked with 'are elements that have been changed during the triangulation process, and P (k) and Q (k) are vectors indicating the contraction order of the nodes. Nmax indicates the number of non-diagonal non-zero elements after triangular decomposition of the coefficient matrix. The node ordering indicates that the node indicated by Q (k) is deleted and reduced to the node indicated by P (k). On the other hand, the forward erasure / backward substitution process performed after triangulation of the coefficient matrix is executed according to the processing flow shown in FIG. 8, but the backward substitution process is divided into two stages. In this forward erasure process, there is an obstacle to parallel processing, which will be described with reference to FIG.

  FIG. 9 shows a case where parallel processing is performed by four CPUs, for example. In the first parallel processing, k = 1, 2, 3, and 4 are in charge of CPU1, CPU2, CPU3, and CPU4, respectively. Since Q (2) = 2 coincides with P (1) = 2 of CPU 1 that processes in advance, parallel processing cannot be performed, and processing must be performed in series. Therefore, it is necessary to execute the processing of CPU 2 after the processing of CPU 1 is completed. For CPU4, P (4) = 4 matches P3 (3) = 4 of CPU3, so parallel processing cannot be performed and processing must be performed in series. It is necessary to execute the processing of the CPU 4. Similarly, in the second parallel processing, it is understood that the processing of the CPU 2 cannot be performed in parallel, and in the third parallel processing, the processing of the CPU 2 cannot be performed in parallel processing.

  On the other hand, the obstacle factor of the parallel processing in the backward substitution processing will be described with reference to FIG. As for backward substitution processing, processing is performed in the direction from the larger element number to the smaller element number. First, in the first parallel processing, k = 10, 9, 8, and 7 are handled by CPU1, CPU2, CPU3, and CPU4, respectively, but for CPU2, P (9) = 10 is the Q (1) of CPU1. Since 10) = 10, parallel processing cannot be performed, and processing must be performed in series. Therefore, it is necessary to execute the processing of CPU 2 after the processing of CPU 1 is completed. In the second parallel processing, for CPU2, P (5) = 3 matches Q1 (6) = 3 of CPU1, so parallel processing cannot be performed, and processing must be performed in series. It is necessary to execute the processing of CPU2 after the processing of CPU1 is completed. Furthermore, for CPU4, P (3) = 4 matches P3 (4) = 4 of CPU3, so parallel processing cannot be performed and it is necessary to perform processing in series. It is necessary to execute the processing of the CPU 4. Even in the third parallel processing, for CPU, P (1) = 2 coincides with Q (2) = 2 of CPU1, so parallel processing cannot be performed and processing must be performed in series. After the process is completed, the CPU 2 needs to execute the process. As described above, it can be understood that the obstacle factor of the parallel processing in the backward substitution process is the same as that in the forward erasure process.

  When node ordering of the coefficient matrix is performed, the triangulation, forward elimination, and backward substitution processing are all affected by the same effect. Therefore, it is required to devise a node ordering method that improves the execution efficiency of the parallel processing of forward erasure and backward substitution processing without adversely affecting the triangulation of the coefficient matrix.

  Therefore, in this embodiment, node ordering is performed based on the following basic concept.

(1) Node ordering is performed from the smallest node of fill-in. If this condition is maintained, the process of triangulating the coefficient matrix is the same as the conventional method, and the processing performance is not deteriorated.
(2) Based on (1), node ordering is performed with priority given to nodes capable of parallel processing in forward erasure processing. Thereby, the execution efficiency of the parallel process of the forward erasure process can be improved, and the execution efficiency of the parallel process of the backward substitution process can be improved.

A node ordering method for improving the execution efficiency of the forward erasure process parallel processing will be described below. The obstruction factors of the parallel processing in the forward erasure processing have been described based on FIG. Therefore, this obstruction factor is eliminated and node ordering is performed based on the following concept.
(1) Node ordering is performed from the node with the smallest fill-in.
(2) The first node is arbitrarily selected from the nodes with the smallest fill-in obtained in (1). For the subsequent nodes to be processed in parallel, the node ordering candidate node and its counterpart If the end node is a node that does not match the other end node of the already ordered node, the node ordering is performed with priority. Whether or not the node ordering candidate node and its counterpart node are nodes that do not match the counterpart node of the ordered node is the above-described determination of whether parallel processing is possible.
(3) If all nodes that are preferentially ordered disappear, the remaining nodes are ordered in order from the node with the smallest fill-in.

  FIG. 11A and FIG. 11B represent the above concept by a processing flow. In FIG. 11A, first, the node ordering of the radial system portion where fill-in is minimized is performed, and then the node ordering of the loop system portion is performed in FIG. As for the node ordering method, the Tinney 2 method is applied to the radial system portion, and the Tinney 3 method is applied to the loop system portion, so that the fill-in is minimized.

  In the calculation using the Tinney 3 method, a simulation of new non-zero element generation is performed for all nodes, and a node with the smallest fill-in is selected. This is processed in parallel to achieve high speed. is doing. The processing flow is shown in FIG. In FIG. 12, first, in order for each CPU to calculate its own processing target element, the average processing amount and the remainder of each CPU are calculated, and the CPU 1 shares the element of (average processing amount + remainder) from the top. Subsequent to CPU 2, the subsequent elements of the average processing amount are shared. After that, a simulation of the number of new non-zero elements generated is performed for all the elements shared by each CPU, and when the process is completed, the CPU result is set in the shared memory and the CPU number is set in its own CPU processing flag. The CPU 1 that manages the entire system has completed its own processing when its own processing has been completed and the CPU processing flags of all CPUs have been set. Therefore, the number of new non-zero element occurrences calculated by each CPU is determined. The simulation result is taken out from the shared memory, and is rearranged in the order of the number of new non-zero element occurrences, and the first node is selected as a node ordering candidate. Then, a process end flag is set, and the process ends. On the other hand, the CPUs other than the CPU 1 check the process end flag, and if the process end flag is set, the process ends. With the above method, the simulation of the number of new non-zero element occurrences can be processed in parallel.

  Next, the effect of this node ordering method will be described with reference to FIGS. 13-1 to 13-4. FIG. 13-1 shows a conventional node ordering node number in the system example, and FIG. 13-2 shows a result of triangulation according to the node ordering. FIG. 13-3 shows the result of node ordering based on the node ordering of the present embodiment, and FIG. 13-4 shows the result of triangulation based on the node ordering. FIGS. 13A and 13C represent the structure of the coefficient matrix of the simultaneous linear equations shown in FIG. 5 as a tree, and this tree is composed of nodes and branches connecting the nodes. In FIGS. 13A and 13B, as indicated by arrows, a process that cannot be performed in parallel occurs four times. On the other hand, FIGS. 13-3 and 13-4 show the results of the node ordering method according to the first embodiment, which shows that the processing that cannot be performed in parallel is performed twice and is effective. . In particular, when the node ordering candidate node and its counterpart node are nodes that do not match the counterpart node of the ordered node, which is one of the node ordering criteria in the present embodiment, the node ordering has priority. It can be seen that there is an effect of eliminating the obstacle factor of the parallel processing as shown in FIG.

  As described above, the node ordering method in the parallel calculation method of simultaneous linear equations according to the present embodiment performs node ordering from the node having the smallest fill-in. The first node is a node in the node having the smallest fill-in. As for nodes to be processed in parallel thereafter, node ordering is performed preferentially when the node and its counterpart node are nodes that do not match the counterpart node of the ordered node. Then, when there is no node to be prioritized, the remaining nodes are ordered from the node with the smallest fill-in. According to the present embodiment, there is an effect that the execution efficiency of parallel processing in forward erasure / backward substitution processing can be improved and the processing performance can be increased, and a network equation (simultaneous linear equation) of a large-scale system can be realized. It is possible to execute with time performance.

Embodiment 2. FIG.
FIG. 11A is a flowchart illustrating the node ordering method according to the second embodiment, and FIG. 11B is a flowchart subsequent to FIG. That is, this embodiment also follows the same node ordering method as in the first embodiment. However, in the first embodiment, the simulation of new non-zero element generation in the node ordering of the loop-like system portion is processed in parallel. However, in the second embodiment, this new non-zero element generation simulation is not processed in parallel. Processing is performed by one CPU. In this way, the processing performance cannot be increased, but optimization of node ordering can be realized, and there is an effect that the number of CPUs can be reduced and the training simulator can be configured at low cost.

Embodiment 3 FIG.
14A and 14B are flowcharts illustrating the node ordering method according to the third embodiment. FIG. 14-2 shows the processing following FIG. 14-1, and the processing is connected at the location indicated by “2”. In FIG. 14A, first, initialization processing (1) (step S90) is performed to initially set flags, and then a node table such as the partner node number and the partner node number connected to each node is created (step S91) is performed, and the node table rearrangement is performed in the order of the smaller number of partner end nodes (step S92). If the number of counterpart end nodes is the same, rearrangement is performed in the order of the previously processed nodes.

  Next, node ordering of the radial system portion is performed first. The radial system part includes a part having one branch connected to a certain node, such as node 1, node 2, node 3, node 4, and node 6 in the radial system of FIG. For such a node, the number of counterpart nodes is also one. For example, when node 1 is arbitrarily selected and ordered, if node 1 is deleted and the branch between node 1 and node 5 is also deleted, the number of connection branches of node 5 becomes one, and the same A structure arises. Then, it is known that optimal node ordering can be performed if the node ordering of the radial system portions is sequentially performed (the concept of the Tinney 2 method). Hereinafter, node ordering is performed based on this feature.

  When forward erasure and backward substitution processing are performed in parallel, each CPU performs processing for one node, so the number of CPUs that perform parallel processing must be handled at one time, and node ordering is required for each element processing unit. There is. For this reason, first, in step S93, it is determined whether or not the number of nodes to be simultaneously ordered is equal to or less than the number of parallel CPUs. If No, initialization of the element count is performed by the initialization process (2) (step S94). Do. If the determination result in step S93 is Yes, nothing is processed and the process branches to step S95.

In Step S95, it is determined whether or not the node i to be ordered is a radial system. If Yes, in Step S96, it is determined whether or not the node i can be processed in parallel. If the determination result in step S96 is Yes, node i is ordered (step S97), the various arrays are counted up (1) (step S98), and the process branches to step S93.
If the determination result in step S96 is No, in this process, the node i is excluded from ordering (step S99), the various arrays are counted up (2) (step S100), and the process branches to step S93.

  In the case of No in step S95, the node table is rearranged in the order of the smaller number of counterpart end nodes for the nodes that have not been ordered in order to check whether or not the radial system portion as the exclusion target node remains (step S101). ) To perform initialization processing (3) (step S102). Next, with respect to the node after the node table rearrangement, it is determined whether or not the node i is a radial system part (step S103). In the case of Yes, it is further determined whether or not all the radial system parts are to be excluded. (Step S104) is performed. If No, the process branches to Step S96. In the case of Yes in step S104, all exclusion target nodes are ordered in order (step S105), and the process proceeds to the process illustrated in FIG. Further, in the case of No in step S103, the process proceeds to the process illustrated in FIG.

  Since the node ordering of the radial system portion has been completed by the above processing, the node ordering of the loop system portion is performed thereafter. Node ordering is also performed for the loop system portion in the same way as the radial system portion.

  As shown in FIG. 14B, first, in step S106, initialization processing (4) of various flags and the like is performed, and then the node table is rearranged in order of decreasing number of node connections for all remaining nodes (step S107), the nodes are rearranged in the order of the smaller number of node connections. Next, it is determined whether or not the number of ordered nodes is equal to or greater than the number of parallel CPUs (step S108). If Yes, initialization processing (2) (step S109) such as the number of ordered arrays is performed, and the process branches to step S110. To do. If No in step 108, no processing is performed and the process branches to step S110. In step S110, it is determined whether or not node i can be processed in parallel. If yes, node i is ordered (step S111), various arrays are counted up (3) (step S112), and then In step S113, it is determined whether the ordering of all nodes has been completed. In the case of No in step S113, the various arrays are counted up (4) (step S114), and the process branches to step S107. If Yes in step S113, the process ends.

  In the case of No in step S110, in this process, node i is excluded (step S115), various arrays are counted up (5) (step S116), and then whether all the remaining nodes are excluded or not. (No in step S117), and if No, various sequences are counted up (6) (step S118), and the process branches to step S108. In the case of Yes in step S117, the node table is rearranged in the order of the smaller number of node connections (step S119) for the remaining nodes, and the order of the smallest node i is performed (step S120). If completed, the process is terminated.

  In the first embodiment, the simulation of the number of new non-zero elements is processed in parallel in the node ordering of the loop-like system portion. In this third embodiment, the new non-zero element ordering in the node order of the loop-like system portion is performed. Instead of the zero element generation simulation, the node ordering candidates are set in the order of decreasing number of counterpart nodes connected to a certain node as in the radial system portion. In this way, the degree of optimization of the node ordering is lower than that in the first embodiment, but the node ordering process can be performed at high speed even with one CPU, so that the system configuration state can be achieved even at the training execution stage in the training simulator. When the change occurs, the node ordering can be executed again at high speed, so that the network calculation in the training execution stage can be sub-optimized. Therefore, it is possible to process the simultaneous linear equations at high speed and to construct a training simulator at a low cost. Moreover, there is an effect that it can be applied to a system for online use such as an automatic feeding system.

Embodiment 4 FIG.
A parallel solving method for simultaneous linear equations according to this embodiment will be described. Note that the node ordering is performed using any one of the node ordering methods of the first to third embodiments, and the triangulation of the coefficient matrix is performed by the method of Non-Patent Document 2, and the result of the triangulation The forward erasure process and the backward substitution process are performed using. FIGS. 15-1 and 15-2 are flowcharts showing the parallel solving method of simultaneous linear equations according to the present embodiment, and forward erasure to which the node ordering method of the first, second, or third embodiment is applied; It is a flowchart which shows the parallel processing by multiple CPU of a backward substitution process. FIG. 15-2 shows the flow of processing following FIG. 15-1 and is connected at the locations indicated by “3”.

  15A, first, parallel processing in the forward erasure process is performed. First, it is determined whether or not the CPU 1 is used (step S121). If Yes, flag initialization processing (step S122) is performed. Next, a parallel processing flag indicating whether each CPU can perform parallel processing is created (step S123), and the process proceeds to step S124. If the determination result in step S121 is No, the process branches to step S124. In step S124, the number of processing times L and the processing order k in which a plurality of CPUs perform parallel processing are set, and then a processing target bj element is selected (step S125). Here, bj represents the jth component of the coefficient vector b. Next, it is determined whether or not the bj element can be processed in parallel (step S126). If Yes, the process branches to step S128. If the determination result in step S126 is No, it is determined whether or not the related bi element, which is a related element, necessary for processing the bj element has been processed (step S127), and the determination result in step S127 is If No, the check is continued, and if the determination result in Step S127 is Yes, the process proceeds to Step S128. In step S128, the forward erase process is calculated, then the CPU processing flag is set (step S129), and the end of the forward erase process is determined (step S130). If the determination result in step S130 is No, the CPU processing flag is set to zero (step S131), and the process branches to step S124. If the determination result in step S130 is Yes, the process of the forward erasure process is terminated and the process proceeds to the process of the backward substitution process 1.

As shown in FIG. 15B, in the backward substitution process 1, first, it is determined whether or not the CPU 1 is used (step S132). If Yes, flags are initialized (step S133). If you skip. Next, the processing target xi group is set (step S134), the calculation of the backward substitution process 1 (step S135) is executed, and after completion of the calculation, the CPU processing flag is set (step S136). The end of substitution process 1 is determined (step S137). Here, xi represents the i-th component of the solution x, and in step S135, aii is the i-th diagonal component of the coefficient matrix, bi is the i-th component of the coefficient vector,
C (i) = 1 / aii (see FIG. 6). If the determination result in Step S137 is No, the check is continued. If Yes, the backward substitution process 1 is terminated and the backward substitution process 2 is performed.

  In the backward substitution process 2, first, it is determined whether or not the CPU 1 is used (step S138). If Yes, flags are initialized (step S139). Next, whether or not each CPU can perform parallel processing is determined. A parallel processing flag indicating whether or not is created (step S140), but if No, the process branches to step S141. In step S141, the processing count L and the processing order k are set, the processing target xi element is selected (step S142), and then it is determined whether the xi element can be processed in parallel (step S143). If the determination result in step S143 is No, it is determined whether or not the related xj element, which is a related element, necessary for processing the xi element has been processed (step S144), and the determination result in step S144 is In the case of No, the check is continuously performed, and in the case where the determination result in Step S144 is Yes, the process proceeds to Step S145. If the determination result in step S143 is Yes, the process branches to step S145.

  In step S145, the backward substitution process 2 is calculated, then the CPU processing flag is set (step S146), and finally the completion of the backward substitution process 2 is determined (step S147). A processing flag is set to zero (step S148), and the process branches to step S141. If the determination result in step S147 is Yes, the process of the backward substitution process 2 ends.

  FIGS. 16A and 16B are flowcharts illustrating the parallel processing flag creation process in the forward erasure process of the present embodiment. FIG. 16B is a flowchart subsequent to FIG. 16A and is connected at a position indicated by “4”. In FIG. 16A, first, a parallel processing flag creation target is set (step S150), and then it is determined whether or not the CPU is 1 (step S151). If yes, a CPU execution flag, a CPU reference flag, Initialization processing (step S152) of flags, such as a CPU processing flag and a parallel processing flag creation end flag, is performed. If No, the process branches to step S153. Next, initial values of the processing element array i and the processing CPU numbers km and kn are set (step S153). Next, in FIG. 16B, calculation of elements for parallel processing for forward erasure (step S154) is performed, and thereafter, it is determined whether or not parallel processing is possible for each element. If possible, the CPU execution flag is set. A CPU number is set, and if it is not possible, a CPU number that should refer to the end of processing is set as a CPU reference flag, and a parallel processing flag is created.

  First, it is checked whether or not the selected element array Q matches the already selected element array P. If they match, parallel processing is impossible, and if they do not match, it is determined that parallel processing is possible. This process is composed of a loop of m and n. In the loop of m, all the parallel processing target elements are included, and in step S155, the processing CPU number in the loop of m is counted up. The loop of n always includes the first element, but the subsequent elements are limited to m−1 elements. This is because, for example, the 2nd element is compared with the 1st element, the 3rd element is the 1st, 2nd element, the 4th element is compared with the 1st, 2nd, 3rd element. is there.

  First, in step S156, the processing CPU number in the loop of n is counted up. kn is a CPU number that processes an element selected in advance, and km is a CPU number that performs parallel processing on the element selected in advance.

  Next, it is determined whether km is 1 or not (step S157). If yes, since it is the first element to be processed in parallel, the CPU execution flag is set so that parallel processing can be performed unconditionally, and the CPU is referred to. The flag is cleared (step S162), and the process branches after step S161 (the m loop is updated). If No in step S157, a determination is made as to whether Q (m) and P (n) match (step S159). If yes, parallel processing is impossible, so a CPU reference flag is set. Then, the CPU execution flag is cleared (step S159), but if No, nothing is processed. Then, after the loop of n is completed, it is determined whether Q (m) and all P (n) do not match (step S160). If Yes, parallel processing is possible, so CPU execution The flag is set and the CPU reference flag is cleared (step S161). If No in step S160, no processing is performed.

  Next, as a determination of whether or not parallel processing is possible, it is checked whether or not the array P of elements selected in advance matches the array P of elements selected thereafter. If they do not match, parallel processing is possible, but if they do match, parallel processing is impossible, so the CPU execution flag and CPU reference flag are set corresponding to each.

  First, the processing CPU number in the n loop is set to an initial value (step S163). These processes are composed of m and n loops, and for the m loops, the first element can be processed in parallel unconditionally, so the second element is selected, and for the n loops, Select from the first element to the element of m-1. This is to compare the first element in the second case, the first and second elements in the third element, and the first, second and third elements in the fourth case. is there.

  First, in step S164, the processing CPU number kn is counted up, and it is determined whether P (m) and P (n) match (step S165). If they match, parallel processing is impossible. The CPU reference flag is set, the CPU execution flag is cleared (step S166), and if No, no processing is performed. When the processing of the loop of m and n is completed, it is determined whether or not the processing of all elements has been completed (step S167), and in the case of No, the array i is increased by the number of CPUs (CPUmax) to be processed in parallel. (Step S168), and the processing CPU numbers km and kn are cleared (Step S169), and the process branches to Step S154. In the case of Yes, the CPU number that executed the process is set in the own CPU processing flag (Step S170), and the CPU 1 is determined (Step S171). In the case of Yes, the determination is made as to whether or not all the CPU processing flags are positive ( Step S172) is performed. In step S172, in the case of No, the check is continuously performed, and in the case of Yes, a parallel processing flag creation end flag is set (step S173), and the processing of the CPU 1 is ended. If the CPU is other than CPU1 in step S171, a parallel processing flag creation end flag is determined (step S174). If the determination result is No, the check is continued, and if Yes, the process ends.

  FIGS. 17A and 17B are flowcharts illustrating the parallel processing flag creation process in the backward substitution process of the present embodiment. FIG. 17-2 is a flowchart subsequent to FIG. 17A, and is connected at a location indicated by “5”. In the forward deletion process, the process proceeds from the element 1 in the direction of the maximum element. In the backward substitution process, the process proceeds in the direction from the maximum element to the element 1. This is the biggest difference between the two.

  In FIG. 17A, first, a parallel processing flag creation target is set (step S150), and then it is determined whether or not the CPU is 1 (step S150). If yes, a CPU execution flag, a CPU reference flag, Initialization processing (step S152) of flags such as a CPU processing flag and a parallel processing flag creation end flag is performed. If No, the process branches to step 153. Next, initial values of processing element array i and CPU processing numbers km and kn are set (step S152). Next, in FIG. 17-2, calculation of elements for parallel processing for backward substitution (step S154) is performed, and thereafter, it is determined whether or not parallel processing is possible for each element. If possible, the CPU execution flag is set. A CPU number is set. If it is not possible, a CPU number to be referred to for the end of processing is set as a CPU reference flag, and a parallel processing flag is created.

  First, it is checked whether or not the selected element array Q matches the already selected element array P. If they match, parallel processing is impossible, and if they do not match, it is determined that parallel processing is possible. This process is composed of a loop of m and n. In the loop of m, all the parallel processing target elements are included, and the processing CPU number in the loop of m is counted up in step S155. The loop of n always includes the first element, but the subsequent elements are limited to m−1 elements. This is because the second element is compared with the first element, the third element is compared with the first element, the second element, and the fourth element is compared with the first, second, and third elements.

  First, in step S156, the processing CPU number in the loop of n is counted up. kn is a CPU number that processes an element selected in advance, and km is a CPU number that performs parallel processing on the element selected in advance.

  Next, it is determined whether km is 1 or not (step S157). If yes, since it is the first element to be processed in parallel, the CPU execution flag is set so that parallel processing can be performed unconditionally, and the CPU is referred to. The flag is cleared (step S162), and the process branches after step S162 (m loop is updated). In the case of No, in the case of No in Step S157, it is determined whether P (m) and Q (n) match (Step S159). In the case of Yes, parallel processing is impossible. The CPU reference flag is set and the CPU execution flag is cleared (step 100). If No, nothing is processed. Then, after the loop of n is completed, it is determined whether P (m) and all Q (n) do not match (step S160). If yes, parallel processing is possible, so CPU execution The flag is set and the CPU reference flag is cleared (step S161). If No in step S160, no processing is performed.

  Next, as a determination of whether parallel processing is possible, it is checked whether the array P of elements selected in advance matches the array P of elements selected thereafter. If they do not match, parallel processing is possible, but if they do match, parallel processing is impossible, so the CPU execution flag and CPU reference flag are set corresponding to each.

  First, the processing CPU number in the n loop is set to an initial value (step S163). These processes are composed of m and n loops, and for the m loops, the first element can be processed in parallel unconditionally, so the second element is selected, and for the n loops, Select from the first element to the element of m-1. This is to compare the first element in the second case, the first and second elements in the third element, and the first, second and third elements in the fourth case. is there.

  First, in step S164, the processing CPU number kn is counted up, and it is determined whether P (m) and P (n) match (step S165). If they match, the CPU reference flag is not available because parallel processing is impossible. Is set, the CPU execution flag is cleared (step S166), and if No, no processing is performed. When the processing of the loop of m and n is completed, it is determined whether or not the processing of all elements has been completed (step S167), and if No, the array i is decreased by the number of CPUs (CPUmax) to be processed in parallel. (Step S168), and the processing CPU numbers km and kn are cleared (Step S169), and the process branches to Step S154. In the case of Yes, the CPU number is set in the CPU processing flag (Step S170), and it is determined whether or not the CPU is 1 (Step S171). In the case of Yes, it is determined whether or not all the CPU processing flags are positive (Step S171). S172) is performed. In step S712, if No, the check is continued, and if Yes, a parallel processing flag creation end flag is set (step S173), and the processing of the CPU 1 is ended. If No in step S171, it is determined whether or not the parallel processing flag creation end flag is positive (step S174). If the determination result is No, the check is continued, and if Yes, the process is performed. finish.

  In the first embodiment, the node ordering method for increasing the execution efficiency of the parallel processing of the forward erasure and the backward substitution process has been described. In the fourth embodiment, the forward erasure and backward substitution when the node ordering is applied. A method for realizing parallel processing has been described. Thus, by combining the first embodiment and the fourth embodiment, there is an effect that parallel processing for solving simultaneous linear equations can be realized and high-speed processing can be realized.

Next, the operation will be described. First, the parallel processing of the forward erasure process will be described. When performing parallel processing with multiple CPUs, check whether bi elements can be processed in parallel before processing, and create parallel processing flags (CPU execution flag, CPU reference flag) in parallel with multiple CPUs. In addition, it is necessary to determine the bi and bj elements to be processed by each CPU, and to determine the detection method for the completion of the processing of each CPU in each parallel calculation step, and the detection method for the completion of the processing for all rows. There is.
(A) Creation of parallel processing flag (CPU execution flag, CPU reference flag) (1) Each CPU sets its own parallel processing flag creation target that each CPU is responsible for.
(2) The CPU 1 first initializes the CPU execution flags and CPU reference flags of all the CPUs with “0”.
(3) Next, each CPU checks whether or not the value of Q (m) in the subsequent stage matches the value of all P (n) in the previous stage for the parallel processing target element in the parallel processing. If they match, parallel processing becomes impossible, so a CPU reference flag is set. If not all match, parallel processing is possible, so a CPU execution flag is set.
The first element to be parallel processed can be processed in parallel unconditionally, and the CPU number is set in the CPU execution flag of the CPU.
If the result of checking the subsequent element and all preceding elements match, the CPU number in charge of P (n) of the matched element to be referenced is set in the CPU reference flag of the CPU.
If the result of checking the subsequent element and all preceding elements does not match, the CPU number is set in the CPU execution flag of the CPU in charge of the element Q (m).
(4) Next, each CPU checks whether or not the values of P (m) in the subsequent stage and the values of all P (n) in the previous stage match for the parallel processing target element in the parallel processing. If they match, parallel processing becomes impossible, so a CPU reference flag is set. If all do not match, do nothing.
If they match, the CPU number responsible for P (n) of the matched element to be referenced is set in the CPU reference flag of the CPU.
・ If they do not match, do nothing.
(5) Each CPU sets its own CPU number in its own CPU processing flag when its own processing is completed.
(6) The CPU 1 checks whether or not the processing of all CPUs has been completed using the CPU termination flag, and if completed, sets the parallel processing flag creation termination flag and terminates the processing.
(7) CPUs other than CPU1 also terminate the process if the parallel processing flag creation end flag is set.
(B) Determination of processing target bi and bj elements (1) Bi and bj elements to be processed by each CPU are calculated by the following equation (4). FIG. 18 is a diagram showing a state in which processing is allocated to four CPUs and managed by various flags in parallel processing in the forward erasure process.
k = (L−1) * CPUmax + CPUi (4)
j = P (k)
i = Q (k)
However,
L: Number of calculations for each CPU (CPU1 is initialized. Initial value is 1)
CPUmax: number of CPUs to be processed in parallel CPUi: CPU number (CPU1 = 1,..., CPUn = CPUmax)
(C) Management of CPU processing flag In order for the CPU 1 to update the calculation count L of each CPU, it is necessary to confirm that the processing of each CPU has been completed. This is defined as a CPU processing flag.
(1) Initialization The CPU 1 initializes CPU processing flags of all CPUs with 0.
(2) Setting of CPU processing flag Each CPU writes its own CPU number in the CPU processing flag at the time when the assigned process is completed.
(3) Counting up the number of calculations L When the CPU processing flags of all CPUs become positive, the CPU 1 counts up L by 1, and resets the CPU processing flags of all CPUs.
(D) Management of forward erasure process end flag Each CPU performs the end of the forward erasure process.
(1) Initialization The CPU 1 initializes the forward erasure process end flag with 0.
(2) Detection of the last row If the row number of the bj element processed by each CPU matches the row size nmax, it is determined that the last row has been processed, and the detected CPU sets its own CPU to the forward erase process end flag. Set the number.
(3) End of forward erase process When each forward erase process end flag is positive, each CPU determines that the process of the forward erase process has ended, and enters the process of the next backward substitution process 1.
(E) Parallel processing procedure in the forward erasure process (1) A parallel processing flag creation target for each CPU is set.
(2) The CPU 1 initializes the CPU execution flag, CPU reference flag, CPU processing flag, and forward erasure process end flag of each CPU.
(3) Each CPU creates all CPU execution flags and CPU reference flags in parallel.
(4) Each CPU determines processing target bi and bj elements.
(5) Each CPU checks the CPU execution flag.
If it matches the own CPU number, the bj element is calculated and the CPU processing flag is set. If the D element multiplied by the bi element is zero, the process is skipped.
If the CPU number does not match, check the CPU processing flag for the CPU number indicated by the CPU reference flag.
(I) If the CPU processing flag is positive, the bj element is processed and the CPU processing flag is set.
(Ii) If the CPU processing flag is not positive, a continuation check is performed (waiting for the calculation of the preceding CPU to finish).
(6) The CPU 1 confirms that all CPU processing flags are positive, increases L by 1,
The CPU processing flags of all the CPUs are reset, and the process returns to (4).
(7) Each CPU sets a forward erasure process end flag when it processes the last line.
(8) If the forward erasure process end flag is positive, each CPU ends forward erasure and proceeds to the next backward substitution process 1.

Next, parallel processing in the backward substitution process 1 will be described. The processing of the backward substitution process 1 can be performed in parallel with each CPU sharing all the processing. When parallel processing is performed by a plurality of CPUs, it is necessary to determine an xj element to be processed by each CPU, a detection method that the processing of each CPU is completed, and a detection method that the processing of all rows is completed. .
(A) Determination of processing target xi (1) The xi element which each CPU processes is calculated by the following formula.
-Average processing amount of each CPU k0 = integer value of (nmax / CPUmax)-Remainder k1 = nmax-k0-CPUmax
CPU 1 processing amount i = 1 to k0 + k1
Processing amount of CPU2 to CPUmax i = (k0 + k1) + (CPUi−2) * k0 + 1
~ (K0 + k1) + (CPUi-1) * k0
(B) Management of CPU processing flag and backward substitution process 1 end flag In order to check that the processing of backward substitution process 1 has been completed, it is necessary to confirm that the processing of each CPU has been completed. FIG. 19 is a diagram showing a state in which processing is allocated to four CPUs and managed by the CPU processing flag in the parallel processing of the backward substitution process 1.
(1) Initialization The CPU 1 initializes the CPU processing flag and the backward substitution process 1 end flag of all CPUs with 0.
(2) Setting of CPU processing flag Each CPU writes its own CPU number in the CPU processing flag at the time when the assigned process is completed.
(3) Setting of the backward substitution process 1 end flag The CPU 1 detects that the CPU processing flag of the other CPU has become positive at the time when its own processing is finished, and sets the backward substitution process 1 end flag.
(C) Parallel processing procedure of backward substitution process 1 (1) Initialization CPU 1 initializes the CPU processing flag and backward substitution process 1 end flag of all CPUs with 0.
(2) Determination of processing target xi Each CPU calculates the processing target xi that it is in charge of.
(3) Setting of CPU processing flag Each CPU writes its own CPU number in the CPU processing flag at the time when the assigned process is completed.
(4) Setting of the backward substitution process 1 end flag The CPU 1 detects that the CPU processing flag of the other CPU is positive when its own processing is completed, and sets the backward substitution process 1 end flag.
(5) When the backward substitution process 1 end flag is positive, each CPU recognizes that the process of the backward substitution process 1 has ended, and proceeds to the next backward substitution process 2 process.

Finally, parallel processing in the backward substitution process 2 will be described. When parallel processing is performed by a plurality of CPUs, it is checked whether parallel processing of xi and xj elements is possible before processing, and parallel processing flags (CPU execution flag, CPU reference flag) are parallelized by a plurality of CPUs. Xi, xj element to be processed by each CPU, determination method for detecting the end of processing of each CPU in each parallel calculation step, and detection method for detecting the end of processing of all rows It is necessary to determine.
(A) Creation of parallel processing flag (CPU execution flag, CPU reference flag) (1) Each CPU sets a target element for creating a parallel processing flag that it is responsible for.
(2) The CPU 1 first initializes the CPU execution flags and CPU reference flags of all the CPUs with “0”.
(3) Next, each CPU checks whether or not the value of P (m) in the subsequent stage matches the value of all Q (n) in the previous stage for the current parallel processing target element. If they match, parallel processing becomes impossible, so a CPU reference flag is set. If not all match, parallel processing is possible, so a CPU execution flag is set.
The first element to be parallel processed can be processed in parallel unconditionally, and the CPU number is set in the CPU execution flag of the CPU.
If the result of checking the subsequent element and all preceding elements match, the CPU number in charge of Q (n) of the matched element to be referred to is set in the CPU reference flag of the CPU.
If the result of checking the subsequent element and all preceding elements does not match, the CPU number is set in the CPU execution flag of the CPU in charge of the element P (m).
(4) Next, each CPU checks whether or not the value of P (m) in the subsequent stage matches the value of all P (n) in the previous stage for the current parallel processing target element. If they match, parallel processing becomes impossible, so a CPU reference flag is set. If all do not match, do nothing.
If they match, the CPU number responsible for P (n) of the matched element to be referenced is set in the CPU reference flag of the CPU.
・ If they do not match, do nothing.
(5) Each CPU sets its own CPU number in its own CPU processing flag when the processing that it is in charge of is completed.
(6) The CPU 1 determines whether or not the processing of all the CPUs has been completed from the CPU processing flag. If it has been completed, the CPU 1 sets a parallel processing flag creation end flag and ends the processing.
(7) The CPUs other than the CPU 1 check the end flag for creating the parallel processing flag, and if it has been set, end the processing.
(B) Determination of processing target xi and xj elements (1) xi to be processed by each CPU is calculated by the following equation (5). FIG. 20 is a diagram showing a state in which processing is allocated to four CPUs and managed by various flags in the parallel processing of the backward substitution process 2.
k = nmax− (L−1) · CPUmax−CPUi + 1 (5)
i = Q (k)
j = P (k)
However,
nmax: Maximum number of elements of xi L: Number of calculations of each CPU (initialized by CPU 1; initial value is 1)
CPUmax: number of CPUs to be processed in parallel CPUi: CPU number (CPU1 = 1,..., CPUn = CPUmax)
(C) Management of CPU processing flag In order for the CPU 1 to update the calculation count L of each CPU, it is necessary to confirm that the processing of each CPU has been completed. This is defined as a CPU processing flag.
(1) Initialization The CPU 1 initializes CPU processing flags of all CPUs with 0.
(2) Setting of CPU processing flag Each CPU writes its own CPU number in the CPU processing flag at the time when the assigned process is completed.
(3) Counting up the number of calculations L When the CPU processing flag of all CPUs becomes positive, the CPU 1 sets L to 1,
Counts up and resets CPU processing flags of all CPUs.
(D) Management of Backward Substitution Process 2 End Flag Each CPU performs the end of the backward substitution process 2 processing.
(1) Initialization The CPU 1 initializes the backward substitution process 2 end flag with 0.
(2) Detection of the last row When the row number of xi processed by each CPU matches “1”, it is determined that the last row has been processed, and the detected CPU sets its own CPU in the backward substitution process 2 end flag. Set the number.
(3) End of Backward Substitution Process 2 If the backward substitution process 2 end flag is positive, each CPU determines that the backward substitution process has ended and ends all processes.
(E) Parallel processing procedure of backward substitution process 2 (1) Each CPU sets a target element for creating a parallel processing flag that it is responsible for.
(2) The CPU 1 initializes the CPU execution flag, CPU reference flag, CPU processing flag, and backward substitution process 2 end flag of each CPU.
(3) Each CPU creates all CPU execution flags and CPU reference flags in parallel.
(4) Each CPU determines processing target xi and xj elements.
(5) Each CPU checks the CPU execution flag.
If it matches the CPU number of the user, the xi element is calculated and the CPU processing flag is set. If the D element multiplied by the xj element is zero, the process is skipped.
If the CPU number does not match, check the CPU processing flag for the CPU number indicated by the CPU reference flag.
(I) When the CPU processing flag is positive, the xi element is processed and the CPU processing flag is set.
(Ii) If the CPU processing flag is not positive, a continuation check is performed (waiting for the end of processing of the preceding CPU).
(6) The CPU 1 confirms that all CPU processing flags are positive, increments L by 1, resets the CPU processing flags of all CPUs, and returns to (4).
(7) Each CPU sets the backward substitution process 2 end flag when it processes the first line.
(8) Each CPU ends the backward substitution process 2 if the backward substitution process 2 end flag is positive.

  According to the present embodiment, based on the result of the node ordering in any one of the first to third embodiments, it is determined whether or not the forward erasure / backward substitution process can be performed in parallel before the process is performed. Sets the CPU execution flag, if not possible, sets the CPU number to be referred to the CPU reference flag, and in forward erasure / reverse substitution processing, performs parallel processing when the CPU execution flag is set, If it is not set, the CPU number to be referred to is extracted from the CPU reference flag, and after confirming that the processing of the CPU is completed, the processing of the CPU is performed thereafter. In addition to realizing parallel processing of forward erasure / backward substitution processing processed in series, there is an effect that the execution efficiency of the parallel processing can be improved. Further, based on a computer having a symmetric multi-CPU configuration as shown in FIG. 2, by using the parallel solving method of simultaneous linear equations according to the present embodiment, a parallel solving apparatus for solving solutions of simultaneous linear equations in parallel Can be configured.

It is a block diagram which shows the structure of the training simulator to which Embodiment 1 is applied. 2 is a diagram illustrating an example of a computer configuration used for parallel solution of simultaneous linear equations according to the first embodiment; FIG. In Embodiment 1, it is a flowchart which shows the process example of the dynamic stability calculation which mounts in a system | strain pseudo | simulation server group and performs system simulation. It is a figure which shows the example of a system | strain described in the nonpatent literature 2. It is a figure which shows the network equation (simultaneous linear equation) of the system example of FIG. It is a flowchart which shows the basic process of triangulation. It is a figure which shows the structure of the table which stores the various data of a triangulation result. It is a processing flow figure showing forward erasure / reverse substitution processing. It is a figure which shows the problem of the parallel processing in a forward erasure | elimination process. It is a figure which shows the problem of the parallel processing in a backward substitution process. FIG. 3 is a flowchart showing a node ordering method according to the first embodiment. It is a flowchart following FIG. It is a flowchart which shows the parallel processing of the simulation of new non-zero element generation | occurrence | production in FIG. 11-2. FIG. 10 is a diagram for explaining the effect of node ordering according to the first embodiment. FIG. 10 is a diagram for explaining the effect of node ordering according to the first embodiment. FIG. 10 is a diagram for explaining the effect of node ordering according to the first embodiment. FIG. 10 is a diagram for explaining the effect of node ordering according to the first embodiment. FIG. 10 is a flowchart illustrating a node ordering method according to the third embodiment. It is a flowchart following FIG. FIG. 10 is a flowchart showing a parallel solving method for simultaneous linear equations in the fourth embodiment. It is a flowchart following FIG. FIG. 20 is a flowchart showing parallel processing flag creation processing in the backward substitution process of the fourth embodiment. It is a flowchart following FIG. FIG. 20 is a flowchart showing parallel processing flag creation processing in the backward substitution process of the fourth embodiment. It is a flowchart following FIG. It is a figure which shows a mode that a process is allocated to four CPUs and managed with various flags in the parallel process of a forward erasure process. It is a figure which shows a mode that a process is allocated to four CPUs and managed with a CPU process flag in the parallel process of the backward substitution process 1. FIG. It is a figure which shows a mode that a process is allocated to four CPUs and managed with various flags in the parallel processing of the backward substitution process 2. 1 is a diagram illustrating a simple network described in Non-Patent Document 1. FIG. It is a figure which shows the process of the tree structure of a nonpatent literature 1. It is a flowchart which shows the node ordering algorithm of a nonpatent literature 1.

Explanation of symbols

1 Training management server group 2 System simulation server group 3 Automated simulation server group 4 Trainer table 5 Traini table 6 Large screen system board 7 System LAN
8 CPU1
9 CPU2
10 CPU3
11 CPUn
12 Shared memory

Claims (4)

Using a parallel computer having a symmetric multi-CPU configuration having a plurality of CPUs and a shared memory that can be commonly accessed by the CPUs, and based on triangulation of coefficient matrices, forward erasure processing, and backward substitution processing Used in parallel calculation of solutions of simultaneous linear equations in power system analysis, the structure of the coefficient matrix and the procedure of the forward elimination process and the backward substitution process are represented by a tree composed of nodes and branches connecting the nodes. A node ordering method when expressing,
A first step of performing node ordering for nodes belonging to a radial system part that is a system part not including a loop in the tree;
A second step of performing node ordering for nodes belonging to a loop system part that is a system part other than the radial system part in the tree;
Including
In the first step, the node to be ordered first is arbitrarily selected from the nodes having the smallest number of branches connected to the node, and thereafter, the node is connected to each node among the node ordering candidate nodes. When nodes are selected in order from the node with the smallest number of branches, and the node that is the node ordering candidate and the partner node that is an adjacent node connected to it via the branch is a node that does not match the partner node of the ordered node Node ordering is performed for each of the plurality of CPUs based on a selection criterion that the node ordering candidate node is preferentially selected.
In the second step, a simulation of the number of new non-zero elements generated at the time of contraction of nodes in the forward erasure process is performed in parallel using the plurality of CPUs, and obtained by the simulation. The node is selected from the nodes having a low number of new non-zero elements, and the node that is a node ordering candidate and the partner node connected to the node through a branch are not matched with the partner node of the ordered node. A node ordering method, wherein node ordering is performed for each of the plurality of CPUs based on a selection criterion that a node ordering candidate node is preferentially selected in some cases. Using a parallel computer having a symmetric multi-CPU configuration having a plurality of CPUs and a shared memory that can be commonly accessed by the CPUs, and based on triangulation of coefficient matrices, forward erasure processing, and backward substitution processing Used in parallel calculation of solutions of simultaneous linear equations in power system analysis, the structure of the coefficient matrix and the procedure of the forward elimination process and the backward substitution process are represented by a tree composed of nodes and branches connecting the nodes. A node ordering method when expressing,
A first step of performing node ordering for nodes belonging to a radial system part that is a system part not including a loop in the tree;
A second step of performing node ordering for nodes belonging to a loop system part that is a system part other than the radial system part in the tree;
Including
In the first step, the first node to be ordered is arbitrarily selected from the nodes having the smallest number of branches connected to the node, and thereafter, the node is connected to each node among the node ordering candidate nodes. If nodes are selected in order from the node with the smallest number of branches, and the node that is the node ordering candidate and the other node that is an adjacent node connected via the branch are nodes that do not match the other node of the already ordered node Node ordering is performed for each of the plurality of CPUs based on a selection criterion that a node ordering candidate node is preferentially selected.
In the second step, a simulation of the number of new non-zero elements generated at the time of node contraction in the forward erasure process is performed using a single CPU of the plurality of CPUs. Select from the obtained nodes with a small number of new non-zero elements, and the node ordering candidate node and the adjacent node connected to it via a branch coincide with the other node of the ordered node A node ordering method, wherein node ordering is performed for each of the plurality of CPUs based on a selection criterion that a node that is a node ordering candidate is preferentially selected when the node is not a node. Using a parallel computer having a symmetric multi-CPU configuration having a plurality of CPUs and a shared memory that can be commonly accessed by the CPUs, and based on triangulation of coefficient matrices, forward erasure processing, and backward substitution processing Used in parallel calculation of solutions of simultaneous linear equations in power system analysis, the structure of the coefficient matrix and the procedure of the forward elimination process and the backward substitution process are represented by a tree composed of nodes and branches connecting the nodes. A node ordering method when expressing,
A first step of performing node ordering for nodes belonging to a radial system part that is a system part not including a loop in the tree;
A second step of performing node ordering for nodes belonging to a loop system part that is a system part other than the radial system part in the tree;
Including
In the first step, the first node to be ordered is arbitrarily selected from the nodes having the smallest number of branches connected to the node, and thereafter, the node is connected to each node among the node ordering candidate nodes. If nodes are selected in order from the node with the smallest number of branches, and the node that is the node ordering candidate and the other node that is an adjacent node connected via the branch are nodes that do not match the other node of the already ordered node Node ordering is performed for each of the plurality of CPUs based on a selection criterion that a node ordering candidate node is preferentially selected.
In the second step, processing is performed using a single CPU of the plurality of CPUs, so that nodes are sequentially selected from the nodes with the fewest number of branches connected to each node among the node ordering candidate nodes. When a node ordering candidate node and a neighboring node connected to it via a branch are nodes that do not match the other node of the ordered node, the node ordering candidate node is selected with priority A node ordering method, wherein node ordering is performed for each of the plurality of CPUs based on a selection criterion of The node ordering method according to any one of claims 1 to 3, wherein a parallel computing device having a symmetric multi-CPU configuration including a plurality of CPUs and a shared memory accessible by the CPUs in common. Parallel solution of simultaneous linear equations in power system analysis based on processing procedure including applied node ordering step, triangulation step for triangulating coefficient matrix, forward elimination processing step, backward substitution processing step A parallel solution method for calculating,
In the forward erasure processing step, a parallel processing flag for determining whether or not parallel processing is possible is created in parallel by the plurality of CPUs, and the parallel processing flag can be referred to and the parallel processing flag is referred to Execute parallel processing for forward erasure by performing parallel processing for elements that cannot be processed in parallel and confirming the end of processing of related elements necessary for processing of the elements.
The backward substitution processing step includes a process of substituting the product of the coefficient vector component of the simultaneous linear equation and the inverse of the diagonal component of the coefficient matrix corresponding to this component into the solution vector component to be processed. A substitution first step, and a backward substitution second step that is a process after the backward substitution first step,
In the first backward substitution first step, the processing target is distributed to the plurality of CPUs to perform parallel processing,
In the backward substitution second step, a parallel processing flag for determining whether or not parallel processing is possible is created in parallel by the plurality of CPUs, and parallel processing is possible with reference to the parallel processing flag Execute parallel processing for elements, and for elements that cannot be processed in parallel, execute parallel processing of backward substitution by confirming the end of the processing of the related elements necessary for processing of the element. A parallel solution method for simultaneous linear equations.

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