CN113919277A

CN113919277A - Circuit design method, platform and terminal equipment

Info

Publication number: CN113919277A
Application number: CN202111134884.6A
Authority: CN
Inventors: 涂宏斌; 徐任玉; 郑文耀; 李�杰; 于明; 尹立一; 王昊天; 赵瑞敏
Original assignee: Hunan Great Wall Science And Technology Information Co ltd; China Great Wall Technology Group Co ltd
Current assignee: Hunan Great Wall Science And Technology Information Co ltd; China Great Wall Technology Group Co ltd
Priority date: 2021-09-27
Filing date: 2021-09-27
Publication date: 2022-01-11

Abstract

The embodiment of the application provides a circuit design method, a platform and terminal equipment, wherein the method comprises the following steps: determining the initial coordinates of the unknown nodes according to the initial coordinates of the known nodes; mapping all the nodes to a region to be laid out according to the initial coordinates of all the nodes to generate a layout chart; averagely dividing the area to be distributed into a plurality of sub-areas; and moving the nodes according to the number of the nodes in each subregion, so that the total number of the nodes in all subregions does not exceed the preset number, and updating the layout chart, thereby ensuring higher quality of the layout and avoiding manual intervention.

Description

Circuit design method, platform and terminal equipment

Technical Field

The application belongs to the technical field of circuit design, and particularly relates to a circuit design method, a circuit design platform and a terminal device.

Background

During layout and wiring design, each logic module of a designed circuit needs to be laid out, namely, each logic module or device is placed at a corresponding position on a silicon wafer, and then each logic unit is electrically connected by a lead, namely, the wiring process is carried out, so that the layout design of the integrated circuit is completed.

Common methods of placement and routing generally fall into three categories: automatically laying out and routing, for example, after relevant rule requirements are set in design software, the design software automatically carries out laying out and routing; manual layout and routing, that is, all the layout and routing are manually completed by a designer, which is high in requirement on the designer and extremely time-consuming; the interactive layout and routing is between the former two methods, and manual intervention of a designer is carried out on the basis of automatic layout and routing, or one part of the automatic layout and routing is carried out, and the rest part is manually finished by the designer. In recent years, with the rapid development of circuit manufacturing processes, the degree and complexity of circuit integration are increasing, the number of nets integrated in a circuit is increasing and the density of nets is increasing, so that the difficulty of wiring is increasing.

The existing circuit layout or wiring algorithm needs continuous iteration and is slow in speed, layout or automatic wiring cannot be achieved, and the layout or wiring result still needs manual intervention in many times. Therefore, designing an efficient method for placement or routing that can handle millions of cells has become a critical issue in the automation of electronic circuit design.

Disclosure of Invention

The embodiment of the application provides a circuit design method, a circuit design platform and terminal equipment, which can effectively improve the efficiency of circuit layout and wiring.

In a first aspect, an embodiment of the present application provides a circuit design method, including:

determining the initial coordinates of the unknown nodes according to the initial coordinates of the known nodes;

mapping all the nodes to a region to be laid out according to the initial coordinates of all the nodes to generate a layout chart;

averagely dividing the area to be distributed into a plurality of sub-areas;

and moving the nodes according to the number of the nodes in each subregion, so that the total number of the nodes in all subregions does not exceed the preset number, and updating the layout chart.

In a second aspect, an embodiment of the present application provides a circuit design platform, including:

the coordinate module is used for determining the initial coordinates of the unknown nodes according to the initial coordinates of the known nodes;

the mapping module is used for mapping all the nodes to the area to be laid out according to the initial coordinates of all the nodes to generate a layout chart;

the dividing module is used for averagely dividing the area to be distributed into a plurality of sub-areas;

and the adjusting module is used for moving the nodes according to the number of the nodes in each subregion, so that the total number of the nodes in all subregions does not exceed the preset number, and updating the layout chart.

In a third aspect, an embodiment of the present application provides a terminal device, a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the circuit design method of any one of the above first aspects when executing the computer program.

In a fourth aspect, the present application provides a computer program product, which when run on a terminal device, causes the terminal device to execute the circuit design method according to any one of the first aspect.

It is understood that the beneficial effects of the second to fourth aspects can be seen from the description of the first aspect, and are not described herein again.

Compared with the prior art, the embodiment of the application has the advantages that:

the method comprises the steps of determining an initial coordinate of an unknown node according to the initial coordinate of a known node; mapping all nodes to the region to be laid out according to the initial coordinates of all the nodes to generate a layout chart; averagely dividing a region to be distributed into a plurality of sub-regions; and moving the nodes according to the number of the nodes in each subregion, so that the total number of the nodes in all subregions does not exceed the preset number, and updating the layout chart, thereby ensuring higher quality of the layout and avoiding manual intervention.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a schematic flow chart diagram illustrating a circuit design method according to an embodiment of the present application;

fig. 2 is a schematic node coordinate diagram of a circuit design method according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating node movement of a circuit design method according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a circuit design platform according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a terminal device according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a described condition or event is detected" may be interpreted, depending on the context, to mean "upon determining" or "in response to determining" or "upon detecting a described condition or event" or "in response to detecting a described condition or event".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

In the embodiment of the present application, a pin to be connected in a circuit to be laid out is regarded as a node in the circuit layout range.

Fig. 1 is a schematic flow chart of a circuit design method according to an embodiment of the present application, including:

step S101: and determining the initial coordinates of the unknown nodes according to the initial coordinates of the known nodes. The method specifically comprises the following steps:

first, the initial coordinates of the nodes with determined positions are obtained. For a chip, the positions of some nodes among all the nodes of the wiring to be laid out are determined in advance, and the positions of some nodes are to be laid out. Generally, an input/output IO module needs to be determined in advance according to design requirements, for example, according to the needs of an application scenario, a power input position has been uniquely specified, or a signal output position thereof has been uniquely specified, then a node coordinate position corresponding to the power input or the signal output is determined, a corresponding coordinate is known in advance, and in a subsequent adjustment iteration, the coordinate of each node in the IO module does not change.

And then generating an initial coordinate corresponding to the unknown node to be laid out based on the initial coordinate of the known node.

Fig. 2 shows a schematic diagram of node coordinates, where A, B, E, F is a node for position determination, A, B, E, F includes known coordinates (Xa, Ya), (Xb, Yb), (Xe, Ye), (Xf, Yf), and C, D includes a node to be laid out, and C, D includes corresponding coordinates (Xc, Yc), (Xd, Yd) of a logic unit.

Φ＝(Xc-Xa)²+2(Xc-Xb)²+(Xd-Xe)²+2(Xd-Xf)²

Respectively calculating partial derivatives of Xc and Xd, and making the partial derivatives be 0, namely:

the abscissa of C, D two points can be solved.

In the same way, phi^＇＝(Yc-Ya)²+2(Yc-Yb)²+(Yd-Ye)²+2(Yd-Yf)²

Respectively calculating partial derivatives of Yc and Yd, and making the partial derivatives be 0, namely:

the ordinate of C, D two points can be obtained by solving

At this time, A, B, C, D, E, F are all nodes with determined positions, the corresponding coordinates are known coordinates, and then the logic unit coordinates corresponding to all the nodes to be laid out can be obtained by iteration for many times, so that the initial coordinates of all the nodes to be laid out and wired are determined.

When an initial coordinate of an unknown node is required, at least two known fixed points are required. Alternatively, the initial coordinates of each node are calculated from the same number of fixed points. For example each node is calculated according to 2 known fixed points or each according to 4 known fixed points.

Step S102: and mapping all the nodes to the area to be laid out according to the initial coordinates of all the nodes to generate a layout chart.

Step S103: and averagely dividing the area to be laid into a plurality of sub-areas.

In the embodiment of the present application, the whole region to be laid out is equally divided into a plurality of sub-regions according to the area, each sub-region may also be referred to as a BOX, the number of nodes that each BOX can accommodate is limited, and in the embodiment of the present application, the maximum number of nodes that the BOX can accommodate is referred to as a capacity.

Step S104: and moving the nodes according to the number of the nodes in each subregion, so that the total number of the nodes in all subregions does not exceed the preset number, and updating the layout chart.

If the total number of junction points in some BOX exceeds the preset number after mapping according to the initial coordinates, the BOX is considered to contain dense nodes, and the dense nodes need to be moved to other BOX with less node number, wherein the dense nodes can be called as nodes to be moved, so that all the nodes are reasonably dispersed on the region to be laid out, and are not concentrated on a certain BOX. The method specifically comprises the following steps:

step S1041: and if the total number of the nodes in any sub-area exceeds the preset number, determining the number of the nodes to be moved in any sub-area.

The preset number may be flexibly set, for example, the preset number may be the capacity of the sub-area, or may be smaller than the capacity of the sub-area.

Optionally, as shown in fig. 3, the node movement diagram is as follows:

m is the number of nodes to be moved which need to be moved, Ln is the sum of the number of nodes in the BOX on the left side of the cutting line, Rn is the sum of the number of nodes in the BOX on the right side of the cutting line, Lb is the capacity of the BOX on the left side of the cutting line, and Rb is the capacity of the BOX on the right side of the cutting line.

Step S1042: determining a first new coordinate of the node to be moved according to the number of the node to be moved;

then the equations may hold for the nodes on the left and right sides of the cut line, respectively:

left:

and (3) right:

wherein the content of the first and second substances,

w isWidth of single BOX, C_bIndicating the capacity of a single BOX.

Wherein x is_max,x_minThe leftmost coordinate of the left subregion BOX grid and the rightmost coordinate of the right subregion BOX grid, x, of the cutting line are indicated respectively_ori,x_newRespectively representing the initial coordinate and the first new coordinate of the node, the distance that the node needs to move is: | x_new-x_ori|。

Alternatively, dense nodes that need to be moved are randomly selected. For example, if the number of the nodes in the BOX on the left side of the cutting line is 2 more than the capacity, 2 nodes are randomly selected from all the nodes in the BOX on the left side, and then moved to the right, and if the number of the nodes in the BOX on the right side of the cutting line is 2 more than the preset capacity, 2 nodes are randomly selected from all the nodes in the BOX on the right side, and then moved to the left.

Optionally, after the dense nodes are moved, the difference between the numbers of BOX nodes on the left and right sides of the cutting line meets a preset condition, where Ln-Rn is not greater than N, N can be flexibly set according to an actual condition, and is optionally a natural number greater than 1 and less than 5. That is, after moving the node each time, the number of nodes in the BOX on both sides of the dotted line simultaneously satisfies the preset condition and then the next node is moved. By setting the preset condition, the distribution of the nodes can be more reasonable and uniform, and meanwhile, the number balance of the nodes in the BOX on two sides of the dotted line does not need to be strictly emphasized.

Step S1043: and if the node to be moved moves from the initial coordinate to a first new coordinate, the element to which the node to be moved belongs is overlapped with other elements, and the first new coordinate is adjusted.

The specific adjusting step comprises:

setting a first virtual point in a first direction separated from the first new coordinate, wherein the difference value between the coordinate of the first virtual point and the first new coordinate is equal to the difference value | x between the first new coordinate and the initial coordinate of the node to be moved_new-x_ori|。

Determining a second new coordinate of the node to be moved according to a first distance formula and the coordinate of the first virtual point;

if the node to be moved moves from the first new coordinate to the second new coordinate, the element to which the node to be moved belongs is not overlapped with other elements, and the coordinate of the node to be moved is updated to the second new coordinate;

if the node to be moved moves from the first new coordinate to the second new coordinate, the element to which the node to be moved belongs is overlapped with other elements and F_f+F_rIf the distance is more than 0, returning to the step of determining a second new coordinate of the node to be moved according to the first distance formula and the coordinate of the first virtual point, namely continuously updating d_fTo continue adjusting the position of the node;

if the node to be moved moves from the first new coordinate to the second new coordinate, the element to which the node to be moved belongs is overlapped with other elements and F_f+F_rAnd resetting the position of the node and setting a second virtual point in a second direction separated from the first new coordinate, wherein the position is less than or equal to 0. Wherein the second direction is perpendicular to the first direction. Wherein the virtual point is set in a direction that can separate the coincident nodes, optionally in the left-right direction or in the up-down direction, for example, if F appears after the node position is adjusted in the left-right direction_f+F_rAnd (5) less than or equal to 0, and if the elements of different nodes are still overlapped, resetting the positions of the nodes and setting a second virtual point in the vertical direction. In the embodiment of the present application, the virtual point is not directly arranged in the direction with the angle, because the direction with the angle is moved after the combination of the left-right direction movement and the horizontal direction movement.

Determining a third new coordinate of the node to be moved according to a second distance formula and the coordinate of the second virtual point;

if the node to be moved moves from the first new coordinate to the third new coordinate, the element to which the node to be moved belongs is not overlapped with other elements, and the coordinate of the node to be moved is updated to the third new coordinate;

if the node to be moved moves from the first new coordinate to the third new coordinate, the element and other elements belonging to the node to be movedElements overlap and F_f＇+F_rIf the distance is more than 0, returning to the step of determining a third new coordinate of the node to be moved according to a second distance formula and the coordinate of the second virtual point, namely continuously adjusting the position of the node;

if the node to be moved moves from the first new coordinate to a third new coordinate, the element to which the node to be moved belongs is overlapped with other elements and F_f＇+F_rAnd moving the node to be moved into a sparse subregion of the region to be distributed from a second new coordinate, wherein the sparse subregion is a subregion of the region to be distributed, the number of nodes of which is less than a preset threshold value, or a subregion of which the blank area is greater than the element area to which the node to be moved belongs. Optionally traversing the region to be laid out, and preferentially selecting the sub-regions with small node number and large blank area.

Wherein the first distance formula is:

the second distance formula is:

F_f＝ω_f*d_fn，F_f＇＝ω_f＇*d_fn＇，-3＜ω_f＜0，-3＜ω_f＇＜0

d_fnis the distance of the first virtual point from the second new coordinate, d_fnThe initial value is the difference value between the first new coordinate and the initial coordinate of the node to be moved, d_fn＇Is the distance of the second virtual point from the third new coordinate, d_fn＇The initial value is the difference value between the first new coordinate and the initial coordinate of the node to be moved, Fr is the total fixing force applied to the overlapped node to be moved, and the second direction is perpendicular to the first direction.

F_FAnd F_f＇Is a virtualForce, is negative.

Wherein, if n corresponding known nodes are associated with the node, Fn is the fixing force between the node and the associated known node, Fr is the total fixing force to which the node is subjected, and Fr is the total fixing force

If a node has two corresponding known nodes associated with it, then there are two sets of corresponding holding forces, we assume that the holding forces between the two nodes associated with the node are F1, F2, respectively, and finally the total holding force experienced by the node can be expressed as:

fr is a positive value and can be considered as an intrinsic property of the coincident nodes.

In the embodiment of the present application, when elements to which different nodes belong overlap, the corresponding two different nodes are referred to as overlapping nodes. In the embodiment of the application, the d is continuously increased by setting the virtual point_fThe virtual force is increased, the superposed node is pushed to the direction of separating from superposition, and the superposed element is further pulled open. It will be appreciated that the coincident nodes do not coincide as long as the position of any of the coincident nodes is changed. Each time update d_fThe primary node position is adjusted. After each adjustment, whether the elements of different nodes are overlapped or not is judged, if not, the operation is stopped, and in the process, if F appears_f+F_r≦ 0, and misalignment still cannot be achieved, then reset the node position, reverse set the virtual point, repeat the above operations again, for example: the first time, the element is pulled left and right, and the overlapping element can be selectively pulled up and down under the condition that the purpose of separating the overlapping element is not achieved.

Step S105: and determining an escape route of each node according to the cost function so as to route the updated layout.

Nodes to be laid out and wired all need to determine escape routes, and the escape routes of the nodes need to be determined one by one. The specific process is as follows:

step S1051: and selecting available resource points in the escape direction from the nodes to the boundary points aiming at any node.

Step S1052: and calculating the escape cost of each resource point according to the cost function, and storing the resource point corresponding to the minimum escape cost to the resource point set.

Cost(i)＝(1-ω)·G(i)+ω·D(i)

G (i) is a true moving cost of the node, that is, a true moving cost from the node to the resource point, and d (i) is an estimated moving cost from the resource point to the termination node, optionally, the moving cost is a manhattan distance between the two nodes, and the termination node is a boundary point.

Step S1053: if the resource point corresponding to the minimum escape cost is the boundary point, connecting the resource points in the resource point set according to the sequence of saving the resource point corresponding to the minimum escape cost to the resource point set so as to complete route optimization of the node; if the resource point corresponding to the minimum escape cost is not the boundary point, the resource point corresponding to the minimum escape cost is updated to be the node, and the step S1041 is executed again: and selecting available resource points in the escape direction from the nodes to the boundary points.

If the quality of the layout and wiring meets the preset condition, finishing;

and if the layout and wiring quality does not meet the preset condition, sequentially moving any two nodes with the logic relation to shorten the line length between the two nodes. According to the circuit design diagram, whether each node has a logical relationship can be known, in the embodiment of the application, two nodes having the logical relationship are taken as a logical group, and the two nodes having the logical relationship are sequentially moved in the group. For example, node 1 has a logical relationship with nodes 2, 5, and 11, then nodes 1 and 2 are grouped together, nodes 1 and 5 are grouped together, and nodes 1 and 11 are grouped together in sequence, and each node in the group is moved to shorten the wire length between two nodes in the group. The method specifically comprises the following steps:

in the embodiment of the application, the escape direction of the node A is the boundary direction, the node A is connected with the boundary through the connecting line, and the intersection point of the connecting line and the boundary is used as the boundary point a, X_aIs the abscissa of the point of the boundary point a, Y_aIs the ordinate, X, of the point of the boundary point a_AIs the abscissa, Y, of node A_AIs the ordinate of node a. Wherein, the connecting line is a straight line perpendicular to the boundary.

The process of determining the escape order is as follows:

firstly, according to an estimation function, the escape estimation cost of the node A is determined.

The estimation function is: cost_A＝|X_A-X_a|+|Y_A-Y_a|

Among them, Cost_AAnd representing the escape estimation cost of the node A to be escaped.

Then, all the nodes to be escaped are ranked from low to high according to the escape estimation cost and are taken as the escape sequence of the nodes.

Selecting the node with the lowest escape cost in the ith moving sequence set as a minimum node, and sequentially moving each logic group corresponding to the minimum node by taking a group as a unit, wherein each logic group comprises two nodes with a logic relationship, and specifically comprises the following steps:

setting up a first candidate frame based on the minimum node in the ith moving sequence set, and moving the first candidate frame to a boundary by a first preset step length; if no node is available in the candidate frame, keeping the minimum node still; if the candidate box has available nodes and the escape cost of the available nodes is greater than the escape cost of the minimum node, continuing to move the first candidate box until the available nodes with the escape cost less than the escape cost of the minimum node are encountered. The size of the first candidate box can be flexibly set, and is optionally equal to the size of the element to which the node belongs.

Setting up a second candidate frame based on another node in the logical grouping corresponding to the minimum node, and moving the second candidate frame to the boundary by a second preset step length; if there is no node available in the second candidate box, keeping the other node still; if the second candidate box has an available node and the escape cost of the available node is greater than that of the other node, continuing to move the second candidate box until an available node with the escape cost less than that of the other node is encountered.

For example, if the escape directions of two nodes with logical relationship are both left and right, the candidate box moves up or down simultaneously; if the escape directions of the two nodes with the logical relationship are both up and down, the candidate box moves leftwards or rightwards simultaneously; if the escape directions of the two nodes with the logical relationship are left and upper, the candidate box moves upwards and leftwards respectively; if the escape directions of the two nodes with the logical relationship are left and lower, the candidate box moves downwards and leftwards respectively; if the escape directions of the two nodes with the logical relationship are right and upper, the candidate frame moves upwards and rightwards respectively; and if the escape directions of the two nodes with the logical relationship are right and lower respectively, the candidate frame moves downwards and rightwards respectively.

It is to be understood that the above two steps need not be defined in order.

Removing the minimum node in the ith mobile sequence set, updating the ith mobile sequence set, and taking the node with the lowest escape cost in the updated ith mobile sequence set as a new minimum node;

returning to execute the step of selecting the node with the lowest escape cost in the ith moving sequence set as the minimum node and sequentially moving each logic group corresponding to the minimum node by taking the group as a unit until no node exists in the ith moving sequence set after updating;

and dividing all the nodes into 4 sets according to the escape direction, and respectively calculating the average of the escape costs of all the nodes in each set. For example, the side of the node closest to the boundary is used as the escape direction, for example, the escape directions of the nodes closer to the left side are all left sets, the escape directions of the nodes closer to the right side are all right sets, the escape directions of the nodes closer to the upper side are all upper sets, the escape directions of the nodes closer to the lower side are all lower sets, and optionally, the sequence from low to high of the average is used as the sequence of movement of each set. And after all the nodes of one set are processed, sequentially processing the rest sets, optionally skipping the nodes which are moved, and only operating the nodes which are not moved. After each pair of nodes with logical relationship is moved through the above operation, a wiring diagram with optimized layout and wiring is obtained.

According to the method and the device, the escape estimation cost is calculated and ranked from low to high, so that the escape sequence of the nodes is determined, the escape cost is low, the occupied resources are low, if random escape is not adopted according to the sequence, the original high-cost nodes escape first, the occupied resources are more, the escape paths of the low-cost nodes can be occupied, the original low-cost node escape paths are lengthened, path intersection can also occur, and the escape fails.

Optionally, in this embodiment of the present application, the actual time delay and the expected time delay after the wiring are selected_requThe ratio η represents the quality of the layout:

η＝T/T_requ

where T represents the actual time delay after wiring, T_requIndicating the expected delay that is desired to be achieved. If eta is less than 1, the layout quality meets the preset condition, otherwise, the layout quality does not meet the preset condition.

The wiring tree reveals the logical relationship among all elements in the whole wiring diagram, starting from a source node, the next level of the source node is connected with nodes, and whether the logical connection relationship exists between the nodes can be obtained from the wiring tree, and popular points are that: on a circuit starting from a source node, which node is connected first and then leads to which node, so that the nodes have sequence on the circuit, and the relation can be visually embodied on a wiring tree

Where S represents the source node (the node to which power is input), and n1, n2, n3, and n4 represent the nodes of other chips, the delay of the source node S can be expressed by the following equation:

T_del(S)＝0.5·S_c·S_r

wherein S is_c,S_rRespectively, the capacitance and resistance of the source node itself, the delay of the other nodes of the routing tree can be expressed by the following equation:

T_del(n)＝∑T_del(n_pre)+0.5·n_C·n_R

n_C,n_Rrespectively representing the capacitance and resistance of the current node, n_preFor each routing tree, which is a node one level above the current node, we can use the formula T_tree＝∑T_del(n) represents the time delay of the time delay wiring diagram of the current wiring tree, not only related to the capacitance and resistance of the elements, but also related to the distance between the elements, the elements are as close as possible within an allowable range, and the time required for current conduction is faster, and the embodiment of the application adopts T to represent the time delay in the whole wiring diagram:

wherein T is_lengthThe bus length in the wiring diagram is represented, C represents the circumference of the entire layout range, and n represents the number of nodes.

It should be noted that, within the technical scope of the present disclosure, other sequencing schemes that can be easily conceived by those skilled in the art should also be within the protective scope of the present disclosure, and detailed description is omitted here.

Referring to fig. 4, which is a schematic diagram of a circuit design platform provided in an embodiment of the present application, for convenience of description, only a portion related to the embodiment of the present invention is shown, including:

a coordinate module 41, configured to determine an initial coordinate of an unknown node according to the initial coordinate of the known node;

the mapping module 42 is configured to map all the nodes to the region to be laid out according to the initial coordinates of all the nodes, so as to generate a layout diagram;

a dividing module 43, configured to averagely divide the region to be distributed into a plurality of sub-regions;

and the adjusting module 44 is configured to move the nodes according to the number of the nodes in each sub-area, so that the total number of the nodes in all the sub-areas does not exceed a preset number, and update the layout.

The adjusting module 44 is further configured to determine the number of nodes to be moved in any sub-area if the total number of nodes in any sub-area exceeds a preset number;

determining a first new coordinate of the node to be moved according to the number of the node to be moved;

and if the node to be moved moves from the initial coordinate to the first new coordinate, the element to which the node to be moved belongs is overlapped with other elements, and the first new coordinate is adjusted.

The determining the number of nodes to be moved in any sub-area includes:

the determining a first new coordinate of the node to be moved according to the number of the nodes to be moved includes:

m is the number of nodes to be moved, Ln is the sum of the number of nodes in the sub-region BOX on the left side of the cutting line, Rn is the sum of the number of nodes in the sub-region BOX on the right side of the cutting line, Lb is the capacity of the sub-region BOX on the left side of the cutting line, Rb is the capacity of the sub-region BOX on the right side of the cutting line, and x is_max,x_minThe leftmost coordinate of the left subregion BOX grid and the rightmost coordinate of the right subregion BOX grid, x, of the cutting line are indicated respectively_ori,x_newRespectively representing the initial coordinates of the node and the first new coordinates.

The adjusting module 44 is further configured to set a first virtual point in a first direction separated from the first new coordinate, where a difference between a coordinate of the first virtual point and the first new coordinate is equal to a difference between the first new coordinate and the initial coordinate of the node to be moved;

if the node to be moved moves from the first new coordinate to the second new coordinate, the element to which the node to be moved belongs is overlapped with other elements and F_f+F_rIf the distance is more than 0, returning to the step of determining a second new coordinate of the node to be moved according to a first distance formula and the coordinate of the first virtual point;

if the node to be moved moves from the first new coordinate to the second new coordinate, the element to which the node to be moved belongs is overlapped with other elements and F_f+F_rSetting a second virtual point in a second direction separated from the first new coordinate and less than or equal to 0;

if the node to be moved moves from the first new coordinate to the third new coordinate, the element to which the node to be moved belongs is overlapped with other elements and F_f＇+F_rIf the coordinate of the second virtual point is greater than 0, determining a third new seat of the node to be moved according to a second distance formula and the coordinate of the second virtual pointA step of targeting;

if the node to be moved moves from the first new coordinate to a third new coordinate, the element to which the node to be moved belongs is overlapped with other elements and F_f＇+F_rMoving the node to be moved into a sparse subregion of the region to be distributed from a second new coordinate, wherein the sparse subregion is a subregion of the region to be distributed, the number of nodes of which is less than a preset threshold value, or a subregion of which the blank area is greater than the element area to which the node to be moved belongs;

wherein the first distance formula is:

the second distance formula is:

F_f＝ω_f*d_fn，F_f＇＝ω_f＇*d_fn＇，-3＜ω_f＜0，-3＜ω_f＇＜0

And the routing module is used for determining an escape route of each node according to the cost function so as to route the updated layout diagram.

The routing module is also used for selecting an available resource point in the escape direction from the node to the boundary point aiming at any node;

calculating the escape cost of each resource point according to the cost function, and storing the resource point corresponding to the minimum escape cost to a resource point set;

if the resource point corresponding to the minimum escape cost is the boundary point, connecting the resource points in the resource point set according to the sequence of saving the resource point corresponding to the minimum escape cost to the resource point set;

and if the resource point corresponding to the minimum escape cost is not the boundary point, updating the resource point corresponding to the minimum escape cost into the node, and returning to the execution step to select the available resource point in the escape direction from the node to the boundary point.

The cost function is:

Cost(i)＝(1-ω)·G(i)+ω·D(i)

wherein g (i) is the true moving cost of the node, and d (i) is the estimated moving cost from the resource point to the boundary point.

The wiring module is also used for finishing if the quality of the layout and the wiring meets the preset conditions;

and if the layout and wiring quality does not meet the preset condition, sequentially moving any two nodes with the logic relation to shorten the line length between the two nodes.

The sequentially moving any two nodes having a logical relationship to shorten a line length between the two nodes includes:

selecting a node with the lowest escape cost in the ith moving sequence set as a minimum node, and sequentially moving each logic group corresponding to the minimum node by taking a group as a unit, wherein each logic group comprises two nodes with a logic relationship;

wherein i is 1,2,3, 4.

The selecting a node with the lowest escape cost in the ith moving sequence set as a minimum node, and sequentially moving each logic group corresponding to the minimum node by taking a group as a unit includes:

setting up a first candidate frame based on the minimum node in the ith moving sequence set, and moving the first candidate frame to a boundary by a first preset step length;

if no node is available in the candidate frame, keeping the minimum node still;

if the candidate box has available nodes and the escape cost of the available nodes is greater than the escape cost of the minimum node, continuing to move the first candidate box until an available node with the escape cost less than the escape cost of the minimum node is encountered;

setting up a second candidate frame based on another node in the logical grouping corresponding to the minimum node, and moving the second candidate frame to the boundary by a second preset step length;

if there is no node available in the second candidate box, keeping the other node still;

if the second candidate box has an available node and the escape cost of the available node is greater than that of the other node, continuing to move the second candidate box until an available node with the escape cost less than that of the other node is encountered.

It will be apparent to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely illustrated, and in practical applications, the above function distribution may be performed by different functional units and modules as needed, that is, the internal structure of the mobile terminal is divided into different functional units or modules to perform all or part of the above described functions. Each functional module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional modules are only used for distinguishing one functional module from another, and are not used for limiting the protection scope of the application. The specific working process of the module in the mobile terminal may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.

Fig. 5 is a schematic diagram of a terminal device according to an embodiment of the present invention. As shown in fig. 5, the terminal device 5 of this embodiment includes: a processor 50, a memory 51 and a computer program 52 stored in said memory 51 and executable on said processor 50. The steps of the circuit design method described above, such as steps 101 to 104 shown in fig. 1, are implemented when the processor 50 executes the computer program 52. Alternatively, the processor 50, when executing the computer program 52, implements the functions of the modules/units in the above-mentioned device embodiments, such as the functions of the modules 41 to 44 shown in fig. 4.

Illustratively, the computer program 52 may be partitioned into one or more modules/units that are stored in the memory 51 and executed by the processor 50 to implement the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution process of the computer program 52 in the terminal device 5.

The terminal device 5 may be a desktop computer, a notebook, a palm computer, or other computing devices. The terminal device may include, but is not limited to, a processor 50, a memory 51. Those skilled in the art will appreciate that fig. 5 is merely an example of a terminal device 5 and does not constitute a limitation of terminal device 5 and may include more or fewer components than shown, or some components may be combined, or different components, e.g., the terminal device may also include input-output devices, network access devices, buses, etc.

The Processor 50 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 51 may be an internal storage unit of the terminal device 5, such as a hard disk or a memory of the terminal device 5. The memory 51 may also be an external storage device of the terminal device 5, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the terminal device 5. Further, the memory 51 may also include both an internal storage unit and an external storage device of the terminal device 5. The memory 51 is used for storing the computer program and other programs and data required by the terminal device. The memory 51 may also be used to temporarily store data that has been output or is to be output.

The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the above-mentioned method embodiments.

The embodiments of the present application provide a computer program product, which when running on a mobile terminal, enables the mobile terminal to implement the steps in the above method embodiments when executed.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media which may not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A method of circuit design, comprising:

averagely dividing the area to be distributed into a plurality of sub-areas;

2. The circuit design method of claim 1, wherein moving the nodes according to the number of nodes in each sub-area such that the total number of nodes in all sub-areas does not exceed a preset number comprises:

if the total number of the nodes in any sub-area exceeds a preset number, determining the number of the nodes to be moved in any sub-area;

3. The circuit design method of claim 2,

the determining the number of nodes to be moved in any sub-area includes:

4. The circuit design method of claim 2, wherein the adjusting the first new coordinate comprises:

setting a first virtual point in a first direction separated from the first new coordinate, wherein the difference value between the coordinate of the first virtual point and the first new coordinate is equal to the difference value between the first new coordinate and the initial coordinate of the node to be moved;

if the node to be moved moves from the first new coordinate to the third new coordinate, the element to which the node to be moved belongs is overlapped with other elements and F_f＇+F_rIf the distance is greater than 0, returning to the step of determining a third new coordinate of the node to be moved according to a second distance formula and the coordinate of the second virtual point;

wherein the first distance formula is:

the second distance formula is:

F_f＝ω_f*d_fn，F_f＇＝ω_f＇*d_fn＇，-3＜ω_f＜0，-3＜ω_f＇＜0

5. The circuit design method of claim 1, wherein the moving the nodes according to the number of nodes in each sub-area so that the total number of nodes in all sub-areas does not exceed a preset number to update the layout comprises:

and determining an escape route of each node according to the cost function so as to route the updated layout.

6. The circuit design method of claim 5, wherein the determining an escape route for each node according to the cost function to route the updated layout comprises:

selecting available resource points in the escape direction from the nodes to the boundary points aiming at any node;

7. The circuit design method of claim 6, wherein the cost function is:

Cost(i)＝(1-ω)·G(i)+ω·D(i)

8. The circuit design method according to claim 6, wherein the connecting the resource points in the resource point set according to the order of saving the resource point corresponding to the minimum escape cost to the resource point set further comprises:

if the quality of the layout and wiring meets the preset condition, finishing;

9. The circuit design method of claim 8, wherein said sequentially moving any two nodes having a logical relationship to shorten a line length between the two nodes comprises:

wherein i is 1,2,3, 4.

10. The circuit design method according to claim 9, wherein the selecting a node with the lowest escape cost in the ith moving sequence set as a minimum node, and sequentially moving each logical grouping corresponding to the minimum node by taking a group as a unit comprises:

if no node is available in the candidate frame, keeping the minimum node still;

11. A circuit design platform, comprising:

12. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the circuit design method according to any one of claims 1 to 10 when executing the computer program.