JP2021197618A - Solid-state image sensor, driving method thereof, and electronic device - Google Patents

Abstract

To provide a solid-state image sensor, a driving method thereof, and an electronic device, which can surely prevent the generation of inverted video noise even when there are variations in elements for each row, and can achieve high image quality.SOLUTION: In each column, a pixel signal monitoring unit 43 fixes a conversion code of an AD conversion unit of an ADC 41 to a predetermined code when the signal level LVRST of a read reset signal VRST 11 of a pixel signal VSL read to a vertical signal line LSGN11 exceeds a preset reference voltage Vref (as an example, when the signal level LVRST of the read reset signal VRST11 is lowered by a second reference voltage Vref2).SELECTED DRAWING: Figure 9

Description

The present invention relates to a solid-state image sensor, a method for driving the solid-state image sensor, and an electronic device.

A CMOS (Complementary Metal Oxide Semiconductor) image sensor is put into practical use as a solid-state image sensor (image sensor) using a photoelectric conversion element that detects light and generates electric charges.
CMOS image sensors are widely applied as part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and mobile terminal devices (mobile devices) such as mobile phones. There is.

The CMOS image sensor has an FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD) for each pixel, and its readout selects a certain line in the pixel array. However, the column parallel output type that reads them out in the column direction at the same time is the mainstream.

By the way, as the pixel configuration of the CMOS image sensor, for example, for one photodiode (photoelectric conversion element), a transfer transistor as a transfer element, a reset transistor as a reset element, a source follower transistor as a source follower element, and a source follower transistor as a source follower element. A pixel having a 4-transistor (4Tr) configuration having one selection transistor as a selection element can be exemplified.

The transfer transistor is selected by the control signal TG during a predetermined transfer period to be in a conductive state, and the charge (electrons) photoelectrically converted and accumulated by the photodiode is transferred to the floating diffusion FD.
The reset transistor is selected by the control signal RST during a predetermined reset period to be in a conductive state, and resets the floating diffusion FD to the potential of the power supply line.
The selected transistor is selected at the time of read scan and becomes conductive. As a result, the source follower transistor outputs the read signal Pixout of the column output obtained by converting the charge of the floating diffusion FD into a voltage signal to the vertical signal line LSGN.

For example, in the read scan period, after the floating diffusion FD is reset to the potential of the power line, for example, during the reset period, the charge of the floating diffusion FD is converted into a voltage signal by the source follower transistor as a read reset signal (voltage) VRST. It is output to the vertical signal line LSGN.
Subsequently, during a predetermined transfer period, the charges (electrons) photoelectrically converted and accumulated by the photodiode are transferred to the floating diffusion FD. Then, the charge of the floating diffusion FD is converted into a voltage signal by the source follower transistor, and is output to the vertical signal line LSN1 as a read signal (voltage) VSIG.
The pixel output signal is processed as a difference signal (VSIG-VRST).

However, in a CMOS image sensor having such pixels, when very strong light (high-luminance light) is incident on one or more pixels, the pixel output is saturated, so that the high-luminance signal is erroneously regarded as a low-luminance signal. There is a disadvantage that it is output and so-called inverted video noise (so-called sun black spot) is output.

This subject will be described in more detail in relation to FIGS. 1 to 4.
FIG. 1 is a diagram for explaining a read reset signal and a read signal as pixel signals read from pixels, and a problem that a black-out image is formed when high-luminance light is incident.
FIG. 2 is a diagram showing an example of an underexposed image formed when high-intensity light is incident on a pixel.
FIG. 3 is a diagram showing a configuration example of a pixel signal readout circuit system in which a clamp circuit for suppressing a black level fluctuation that causes the occurrence of blackened pixels is arranged.
FIG. 4 is a diagram for explaining the principle of suppressing the fluctuation of the black level by the clamp circuit.

In the CMOS image sensor, as shown in FIG. 1, the luminance information is represented by the difference ΔV1 between the black level LB1 of the read reset signal VRST of the pixel signal Pixout and the signal level LS of the read signal VSIG.
When high-luminance light is incident on a pixel, a phenomenon occurs in which a signal component leaks into the read reset signal VRST, which is originally near the black level LB1.
As a result, as shown in FIG. 1, the black level LB1 largely fluctuates to the black level LB2, and the difference between the signal level SL and the black level LB is attenuated from ΔV1 to ΔV2 (ΔV1> ΔV2), as shown in FIG. , The image becomes darker than the original brightness (black-level image).

Therefore, in order to prevent the influence of the fluctuation of the black level LB, as shown in FIG. 3, a CMOS image sensor in which a clamp circuit for clamping the black level to a predetermined level is arranged in the pixel signal sequence (column) readout system is used. It has been proposed (see, for example, Patent Document 1).

The clamp circuit 1 of FIG. 3 is formed by connecting a clamp transistor CTr between the vertical signal line SLGN1 from which the pixel signal Pixout is read out and the power supply potential VDD in each column of the pixel array.
The gate voltage of the clamp transistor CTr is controlled by the clamp signal CTP by the clamp level generation circuit 2.

As shown in FIG. 4, the clamp circuit 1 clamps the black level LB1 to the black level LB3 when, for example, very strong light (high-intensity light) is incident on one or more pixels, and the signal level SL and the black level The difference in LB is held in ΔV3 (ΔV1≈ΔV3> ΔV2) to prevent the difference from being attenuated from ΔV1 to ΔV2 (ΔV1> ΔV2) and fluctuating.

Japanese Unexamined Patent Publication No. 2011-160046

However, in the above-mentioned CMOS image sensor, the clamp signal CLP, which is a reference signal for controlling the clamp voltage, is common to all rows (columns) in the signal generated by the clamp level generation circuit 2, so that the element for each row is used. Clamp levels also vary due to variations, etc., and there are rows where the clamps do not work well.
In this case, the data in the column where the clamp is not at the desired level is also converted by the ADC3, so that the variation propagates to the final output.
As a result, the central part of the high-intensity light source becomes a blackened image (see FIG. 2 in the image example).

INDUSTRIAL APPLICABILITY According to the present invention, a solid-state image sensor and a solid-state image sensor capable of reliably preventing the generation of inverted video noise even if there are variations in elements for each row, and thus achieving high image quality. The purpose is to provide a driving method and an electronic device.

The solid-state imaging device according to the first aspect of the present invention converts a pixel portion in which pixels for photoelectric conversion are arranged in a matrix and a pixel signal read as a voltage signal from the pixel into a signal line from an analog signal to a digital signal. The pixel signal read from the pixel includes a read reset signal and a read signal sequentially read from the pixel, and the read circuit includes the signal. The signal level of the AD conversion unit that converts the pixel signal read out on the line from an analog signal to a digital signal and the read reset signal of the pixel signal read out on the signal line exceeds a preset reference voltage. If this is the case, it includes a pixel signal monitoring unit that changes the conversion code of the AD conversion unit to a code different from the normal conversion code.

The second aspect of the present invention is a pixel portion in which pixels for photoelectric conversion are arranged in a matrix, and an analog digital (analog signal) that converts a pixel signal read as a voltage signal from the pixel into a signal line from an analog signal to a digital signal. AD) A method of driving a solid-state imaging device including a readout circuit having a conversion function, wherein the readout circuit includes an AD conversion unit that converts the pixel signal read out on the signal line from an analog signal to a digital signal. The pixel signal read from the pixel includes a read reset signal and a read signal sequentially read from the pixel, and is a read reset signal of the pixel signal read to the signal line in the read circuit. When the signal level exceeds the preset reference voltage, the conversion code of the AD conversion unit is changed to a code different from the normal conversion code.

The electronic device according to the third aspect of the present invention includes a solid-state image pickup device and an optical system for forming a subject image on the solid-state image pickup device, and the solid-state image pickup device has a matrix of pixels for photoelectric conversion. It has a pixel unit arranged in the above and a readout circuit having an analog-digital (AD) conversion function for converting a pixel signal read as a voltage signal from the pixel to a signal line from an analog signal to a digital signal, from the pixel. The pixel signal to be read includes a read reset signal and a read signal sequentially read from the pixel, and the read circuit is an AD conversion unit that converts the pixel signal read into the signal line from an analog signal to a digital signal. When the signal level of the read reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage, the conversion code of the AD conversion unit is changed to a code different from the normal conversion code. Includes a pixel signal monitoring unit.

According to the present invention, it is possible to surely prevent the generation of inverted video noise even if there are variations in the elements for each row, and it is possible to realize high image quality.

It is a figure for demonstrating the problem that a read reset signal and a read signal as a pixel signal read from a pixel, and a black-out image are formed when high-luminance light is incident. It is a figure which shows an example of the black-out image formed when the high-luminance light is incident on a pixel. It is a figure which shows the structural example of the pixel signal reading circuit system in which the clamp circuit which suppresses the black level fluctuation which causes the occurrence of black crushed pixel is arranged. It is a figure for demonstrating the principle of suppressing the fluctuation of a black level by a clamp circuit. It is a block diagram which shows the structural example of the solid-state image sensor which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows an example of the pixel which concerns on this 1st Embodiment. It is a figure which shows the operation timing of the shutter scan and the read scan at the time of a normal pixel read operation in this 1st Embodiment. It is a figure for demonstrating the structural example of the reading system of the column (column) output of the pixel part of the solid-state image pickup apparatus which concerns on 1st Embodiment of this invention. It is a figure for demonstrating the structure of the column reading circuit which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows the structural example of the amplifier as the amplification part which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows one structural example of the pixel signal monitoring part which concerns on 1st Embodiment of this invention. It is a timing chart for demonstrating the pixel signal reading process of the solid-state image pickup apparatus which concerns on 1st Embodiment of this invention. It is a figure which shows the column reading system of the solid-state image pickup apparatus which concerns on 2nd Embodiment of this invention. It is a figure which shows an example of the structure of the electronic device to which the solid-state image sensor which concerns on embodiment of this invention is applied.

Hereinafter, embodiments of the present invention will be described in association with the drawings.

(First Embodiment)
FIG. 5 is a block diagram showing a configuration example of the solid-state image sensor according to the first embodiment of the present invention.
In the present embodiment, the solid-state image sensor 10 is composed of, for example, a CMOS image sensor.

As shown in FIG. 5, the solid-state image sensor 10 includes a pixel unit 20 as an image pickup unit, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column reading circuit) 40, and a horizontal scanning circuit (column scanning). Circuit) 50 and a timing control circuit 60 are included as main components.
Among these components, for example, the vertical scanning circuit 30, the column readout circuit 40, and the timing control circuit 60 constitute a pixel signal readout unit 70.

In the first embodiment, the column readout circuit 40 of the solid-state imaging device 10 outputs a pixel signal read as a voltage signal from a pixel performing photoelectric conversion of the pixel unit 20 to a signal line as an analog signal, as will be described in detail later. It has an analog-to-digital (AD) conversion function that converts from to a digital signal.
In the first embodiment, the pixel signal read from the pixel includes the read reset signal VRST11 and the read signal VSIG11 read in order from the pixel.
Then, the column read circuit 40 is a signal of an AD conversion unit that converts the pixel signal PIXOUT read out to the vertical signal line from an analog signal to a digital signal, and a signal of a read reset signal VRST11 of the pixel signal read out to the vertical signal line. When the level exceeds a preset reference voltage Vref, a pixel signal monitoring unit that changes the conversion code of the AD conversion unit to a code different from the conversion code corresponding to the normal brightness information is included.

In the first embodiment, the pixel signal monitoring unit uses the conversion code of the AD conversion unit when the signal level of the read reset signal VRST11 of the pixel signal read out on the vertical signal line exceeds a preset reference voltage. Is fixed to the specified code. For example, the data for that period is fixed to all "1".

The pixel signal monitoring unit has a comparison unit that compares the reference voltage with the read pixel signal.
In the comparison unit, a first reference voltage Vref1 having a level corresponding to the signal level of the read reset signal VRST11 at reset and a second reference voltage Vref2 having a level higher than the first reference voltage Vref1 can be set. , The read reset signal VRST11 of the pixel signal read out to the vertical signal line input to the signal input unit is compared with the reference voltages Vref1 and Vref2 set in the voltage setting unit.

The comparison unit initializes the potential of the signal input unit with the first reference voltage Vref1 level and the offset voltage during the reset period of the pixel and the predetermined period at the start of reading the read reset signal after the reset is released, and after initialization, the comparison unit is vertical. The read reset signal VRST11 of the pixel signal read out on the signal line is compared with the second reference voltage Vref2 set in the voltage setting unit, and the signal level of the read reset signal VRST11 exceeds the second reference voltage Vref2. In this case, the conversion code of the AD conversion unit is fixed to a predetermined code.

In the first embodiment, the second reference voltage Vref2 is set to a voltage value between the first reference voltage Vref1 and the voltage corresponding to the black level when high-luminance light is incident.
The voltage corresponding to the black level when high-intensity light is incident is the level at which a blackout phenomenon occurs or may occur due to a decrease in (signal-black level) when high-intensity light is incident. ..

In the first embodiment, the read unit 70 reads the read reset signal VRST11 (reset voltage Vrst) in the first read period following the reset period in one read scan period, and the first read following the reset period. In the second read period after the transfer period, which is performed after one read period, it is possible to perform a second read to read the read signal VSIG 11 (signal voltage Vsig) according to the accumulated charge of the photoelectric conversion element. ..

In a normal pixel readout operation, a shutter scan is performed by driving the readout unit 70, and then a readout scan is performed, but the first readout and the second readout are performed during the readout scan period.

Hereinafter, the configuration and functions of each part of the solid-state image sensor 10 will be described in detail, and then the configuration of the clip circuit, the readout process related thereto, and the like will be described in detail.

(Structure of pixel unit 20 and pixel PXL)
In the pixel unit 20, a plurality of pixels including a photodiode (photoelectric conversion element) and an in-pixel amplifier are arranged in a two-dimensional matrix of N rows × M columns.

FIG. 2 is a circuit diagram showing an example of pixels according to the first embodiment.

The pixel PXL has, for example, a photodiode (PD) which is a photoelectric conversion element.
For this photodiode PD, a transfer transistor TG-Tr as a transfer element, a reset transistor RST-Tr as a reset element, a source follower transistor SF-Tr as a source follower element, and a selection transistor SEL-Tr as a selection element. Each has one.

The photodiode PD generates and accumulates a signal charge (here, an electron) in an amount corresponding to the amount of incident light.
Hereinafter, the case where the signal charge is an electron and each transistor is an n-type transistor will be described, but the signal charge may be a hole or each transistor may be a p-type transistor.
Further, the first embodiment is also effective when each transistor is shared among a plurality of photodiodes or when a 3-transistor (3Tr) pixel having no selection transistor is adopted. be.

The transfer transistor TG-Tr is connected between the photodiode PD and the floating diffusion FD (floating diffusion layer), and is controlled by the control signal TG applied to the gate through the control line.
The transfer transistor TG-Tr is selected during the high level (H) period when the control signal is in a conductive state, and is photoelectrically converted by the photodiode PD to transfer the accumulated charge (electrons) to the floating diffusion FD.

The reset transistor RST-Tr is connected between the power supply line VRst and the floating diffusion FD, and is controlled by the control signal RST applied to the gate through the control line.
The reset transistor RST-Tr may be connected between the power supply line Vdd of the power supply voltage VDD and the floating diffusion FD, and may be configured to be controlled by the control signal RST applied to the gate through the control line.
The reset transistor RST-Tr is selected during the period of the H level for the control signal RST to be in a conductive state, and resets the floating diffusion FD to the potential of the power supply line VRst (or the power supply line Vdd of the power supply voltage VDD).

The source follower transistor SF-Tr and the selection transistor SEL-Tr are connected in series between the power supply line Vdd of the power supply voltage VDD and the vertical signal line LSGN11.
A floating diffusion FD is connected to the gate of the source follower transistor SF-Tr, and the selection transistor SEL-Tr is controlled by a control signal SEL applied to the gate through a control line.
The selection transistor SEL-Tr is selected for the control signal SEL during the H level period and becomes conductive. As a result, the source follower transistor SF-Tr outputs the read voltage (signal) VSL (PIXOUT) of the column output obtained by converting the charge of the floating diffusion FD into a voltage signal to the vertical signal line LSGN11.
These operations are performed simultaneously and in parallel for each pixel of one row because, for example, the gates of the transfer transistor TG-Tr, the reset transistor RST-Tr, and the selection transistor SEL-Tr are connected in row units. Will be reset.

Since the pixels PXL are arranged in N rows × M columns in the pixel unit 20, there are N control lines for each of the control signals SEL, RST, and TG, and M lines for the vertical signal lines LSGN 11.
In FIG. 5, the control lines of the control signals SEL, RST, and TG are represented as one row scanning control line.

The vertical scanning circuit 30 drives the pixels through the row scanning control lines in the shutter row and the readout row according to the control of the timing control circuit 60.
Further, the vertical scanning circuit 30 outputs a row selection signal of a lead row that reads out the signal according to the address signal and a row address of the shutter row that resets the charge accumulated in the photodiode PD.

As described above, in the normal pixel readout operation, the shutter scan is performed by the vertical scanning circuit 30 of the readout unit 70, and then the readout scan is performed.

FIG. 7 is a diagram showing the operation timings of the shutter scan and the read scan during the normal pixel read operation in the first embodiment.

The control signal SEL that controls the on (conduction) and off (non-conduction) of the selection transistor SEL-Tr is set to a low level (L) during the shutter scan period PSHT, and the selection transistor SEL-Tr is held in the non-conduction state. Then, the read scan period PRDO is set to the H level, and the selection transistor SEL-Tr is held in the conductive state.
Then, in the shutter scan period PSHT, the control signal TG is set to the high level (H) during the period when the control signal RST is at the high level (H), and the photo is taken through the reset transistor RST-Tr and the transfer transistor TG-Tr. The diode PD and floating diffusion FD are reset.

In the read scan period PRDO, the control line RST is set to the high level (H), the floating diffusion FD is reset through the reset transistor RST-Tr, and the pixel read in the reset state is set to the first read period PRD1 after the reset period PR. The signal VRST11 (reset voltage Vrst) is read out.
After the read period PRD1, the control signal TG is set to the high level (H) for a predetermined period, the accumulated charge of the photodiode PD is transferred to the floating diffusion FD through the transfer transistor TG-Tr, and the second read after the transfer period PT. The pixel read-out signal VSIG 11 (signal voltage Vsig) corresponding to the electrons (charges) accumulated in the period PRD2 is read out.

In the normal pixel readout operation of the first embodiment, as shown in FIG. 7, the storage period (exposure period) EXP resets the photodiode PD and the floating diffusion FD during the shutter scan period PSHT to control signals. The period from when the TG is switched to the L level until the control signal TG is switched to the L level in order to end the transfer period PT of the read scan period PRDO.

The column readout circuit 40 includes a plurality of column signal processing circuits (not shown) arranged corresponding to each column (column) output of the pixel unit 20, and enables column parallel processing by the plurality of column signal processing circuits. It may be configured.

The column readout circuit 40 can be configured to include a Correlated Double Sampling (CDS) circuit, an ADC (analog digital converter; AD converter), an amplifier (AMP, an amplifier), and the like.

As described above, as shown in FIG. 8A, for example, the column readout circuit 40 may include an ADC 41 that converts the readout signal VSL of each column output of the pixel unit 20 into a digital signal.
Alternatively, as shown in FIG. 8B, for example, the column readout circuit 40 may include an amplifier (AMP) 42 as an amplification unit that amplifies the readout signal VSL of each column output of the pixel unit 20.

The column readout circuit 40 of the first embodiment has a pixel signal monitoring unit (PMC) 43.
In each column, the pixel signal monitoring unit 43 is an AD conversion unit of the ADC 41 when the signal level LVRST of the read reset signal VRST11 of the pixel signal VSL read out to the vertical signal line LSGN11 exceeds the preset reference voltage Vref. The conversion code of is fixed to the predetermined code.
The case where the reference voltage Vref is exceeded means, as an example, the case where the signal level LVRST of the read reset signal VRST11 is lowered by the second reference voltage Vref2 in the first embodiment.

Here, an example of a specific configuration and function of the pixel signal monitoring unit 43 will be described in relation to the column readout circuit 40 including the amplifier 42 of FIG. 8B.

FIG. 9 is a diagram for explaining the configuration of the column readout circuit according to the first embodiment of the present invention.

The column readout circuit 40A of FIG. 9 includes an amplifier 42A and an ADC 41A as an amplification unit, and a pixel signal monitoring unit 43A.

The amplifier 42A amplifies the pixel signal VSL (PIXOUT) propagated on the vertical signal line LSGN11, and outputs the amplified pixel signal as an amplifier output AMPout to the ADC 41A and the pixel signal monitoring unit 43A.

FIG. 10 is a circuit diagram showing a configuration example of an amplifier as an amplification unit according to the first embodiment of the present invention.

The amplifier 42A includes an operational amplifier (hereinafter referred to as an operational amplifier) 421, a sampling capacitor (input capacitor: Cc) C421, a feedback capacitor (feedback capacitor: Cf) C422, an auto-zero switch unit SW421, an output node ND421, and a reference potential Vref1. It is configured.

The operational amplifier 421 has two input terminals, a first input terminal, an inverting input terminal (−) in the first embodiment, and a second input terminal, and a non-inverting input terminal (+) in the first embodiment. The difference between the input voltage VSL to the first input terminal (−) and the reference potential Vref1 to the second input terminal (+) is multiplied by the gain A0 (amplified) to obtain an amplifier output AMPout.
The output terminal of the operational amplifier 421 is connected to the output node ND421.

The amplifier 42A sets the control signal AZ42 to the H level for a predetermined period after the read reset signal VRST11 of the pixel signal VSL is input (a predetermined period after the first read period for reading the pixel signal in the reset state is started). Will be done.
As a result, the auto zero switch section SW421 of the amplifier 42A becomes conductive.
As a result, the operational amplifier 421 of the amplifier 42A is reset.
As a result, the output signal (amplifier output) AMPout of the operational amplifier 421 of the amplifier 42A during the auto-zero operation becomes the reference potential Vref1.

The ADC 41 converts (AD conversion) the S analog read reset signal VRST11 and the read signal VSIG11, which are the output of each column of the pixel unit 20 amplified by the amplifier 42A as the amplification unit, into digital signals.
Then, when the ADC 41 of the first embodiment receives a flag signal Col_det indicating that a black level exceeding the reference level has been input by the pixel signal monitoring unit 43A, for example, at an active high level (H), an AD conversion code is obtained. It is configured to include a calculation unit 411 that processes so as to be constant.

In the first embodiment, the calculation unit 411 receives a flag signal Col_det indicating that a reference level (in this example, a (low) black level exceeding the second reference voltage Vref2 is input) by the pixel signal monitoring unit 43A. When received at the active high level (H), the AD conversion code is fixed to all "1" so as to be constant.

When the signal level LVRST of the read reset signal VRST11 of the pixel signal VSL read by the vertical signal line LSGN11 and amplified by the amplifier 42A is lowered by the second reference voltage Vref2, the pixel signal monitoring unit 43A is the AD of the ADC 41. The flag signal Col_det is output to the arithmetic unit 411 of the ADC 41A at, for example, the active high level (H) so that the conversion code of the conversion unit is fixed to a predetermined code.

The pixel signal monitoring unit 43A of FIG. 9 is a comparison unit 431 and a comparison unit that compare the read reset signal VRST 11 input to the signal input unit IS43 with the reference voltage Vref (1, 2) set in the voltage setting unit VS43. The flag signal Col_det is, for example, the operation of the ADC 41A at the active high level (H) so as to latch the comparison result signal S431 of the 431 and fix the conversion code of the AD conversion unit of the ADC 41 to a predetermined code during this latch period. It is configured by a 1-bit compare having a latch portion 432 that outputs to the section 411.

More specifically, the comparison unit 431 has a first reference voltage Vref1 having a level corresponding to the signal level of the read reset signal VRST11 at the time of setting as a reference voltage Vref, and a second reference voltage Vref1 having a level larger than the first reference voltage Vref1. The reference voltage Vref2 and can be set.
The comparison unit 431 compares the read reset signal VRST11 of the pixel signal VSL read by the vertical signal line LSGN11 input to the signal input unit IS43 with the reference voltages Vref1 and Vref2 set in the voltage setting unit VS43.

In the first embodiment, the first reference voltage Vref1 is set to a voltage value equal to the output voltage of the amplifier 42A at the time of auto-zero.

The pixel signal monitoring unit 43 includes the comparison unit 431, and sets the potential of the signal input unit IS43 to the first reference voltage Vref1 during a predetermined period at the start of reading the read reset signal VRST11 after the pixel reset period PR and reset release. Initialized to a level, after initialization, the read reset signal VRST11 of the pixel signal VSL read out to the vertical signal line LSGN11 is compared with the second reference voltage Vrrf2 set in the voltage setting unit VS43, and the read reset signal VRST11 When the signal level of the above exceeds the second reference voltage Vref2, the conversion code of the AD conversion unit of the ADC 41A is fixed to a predetermined code, for example, all “1”.

As described above, the case where the reference voltage Vref is exceeded means, as an example, the case where the signal level LVRST of the read reset signal VRST11 is lowered by the second reference voltage Vref2 in the first embodiment.
Further, the second reference voltage Vref2 is set to a voltage value between the first reference voltage Vref1 and the voltage corresponding to the black level LB when the high-luminance light is incident.
Further, as described above, the voltage corresponding to the black level when the high-luminance light is incident causes or the black crushing phenomenon occurs due to the decrease of (signal-black level) when the high-luminance light is incident. It is a possible level.

FIG. 11 is a circuit diagram showing a configuration example of a pixel signal monitoring unit according to the first embodiment of the present invention.

The comparison unit 431 in the pixel signal monitoring unit 43A of FIG. 11 has a first comparator 4311, an AC coupling capacitor C431, an auto zero switch SW431 that can switch between a connected state and a non-connected state by the first reset signal RST, and the first. The first reference switch SW432, which can switch between the connected state and the disconnected state by the reset signal RST of, and the second reset signal RST_B, which has the opposite phase to the first reset signal RST, can switch between the connected state and the disconnected state. The reference switch SW433 of 2 and the second comparator 4312 for processing the output signal S4311 of the first comparator 4311 are included.

The first reset signal RST is a signal having the same phase as the control signal RST of the pixel reset transistor RST-Tr.

In the first comparator 4311, the first input terminal, that is, the inverting input terminal (−) in the present embodiment is connected to the AC coupling capacitor C431, and the amplified pixel signal of the amplifier 42A is used via the AC coupling capacitor C431. It is connected to the supply line of a certain amplifier output AMPout, and the auto zero switch SW431 is connected between the first input terminal (−) and the output terminal.
In the first comparator 4311, the first reference switch SW432 is connected between the second input terminal, the non-inverting input terminal (+) in the present embodiment, and the supply line of the first reference voltage Vref1. The reference switch SW433 of 2 is connected between the second input terminal (+) and the supply line of the second reference voltage Vref2.

In the comparison unit 431, the first comparator 4311 forming the first comparison stage (stage 1) performs a comparison operation by an active, for example, a high level (H) first enable signal EN1.
The second comparator 4312 forming the second comparison stage (stage 2) performs the comparison operation by the second enable signal EN2 which becomes the active high level (H) after the first enable signal EN1.

The latch portion 432 is formed by, for example, a D-type flip-flop DFF432, and latches the output signal S4312 of the second comparator 4312, which is the output signal of the comparison unit 431, in synchronization with the latch signal latch, and the latch signal latch is at a high level. (H) determines the comparison operation of the comparison unit 431, and outputs the flag signal Col_det to the calculation unit 411 of the ADC 41A at, for example, the active high level (H).

In the first embodiment, the comparison unit 431 determines the first reset signal PST after the first enable signal EN1 becomes the active high level (H) and the first comparator 4311 enters the comparison operation. Reset period The PR active high level (H) is reached.
As a result, in the first comparator 4311, the auto zero switch SW431 is in a conductive state, and the first input terminal (−) and the output terminal are connected to form a voltage follower configuration. At that time, the first reference voltage Vref1 is supplied to the second input terminal (+), the first comparator 4311 performs an auto-zero operation, and the signal input unit IP43 is compared with the first reference voltage Vref1. The 4311 offset voltage Vofs of the instrument is held.
The first reset signal RST becomes the inactive low level (L), the second reset signal RST_B becomes the high level (H), the auto zero switch SW431 and the first reference switch SW432 become disconnected, and the second reset signal SW432 becomes disconnected. The reference switch SW433 becomes conductive and the reference voltage is switched from the first reference voltage Vref1 to the second reference voltage Vref2.
After this switching, the second enable signal EN2 becomes the active high level (H), and the second comparator 4312 enters the comparison operation.
The output signal S4312 of the second comparator 4312 showing the comparison result of the comparison unit 431 is output to the latch unit 432.

The latch unit 432 latches a detection signal that detects that at least the signal level of the read reset signal VRST11 exceeds the second reference voltage Vref2 among the output signals of the comparison unit 431, and AD conversion of the ADC 41A during this latch period. A flag signal Col_det instructing that the conversion code of the unit is fixed to a predetermined code is output to the arithmetic unit 411 of the ADC 41A, for example, at an active high level (H).

The horizontal scanning circuit 50 scans signals processed by a plurality of column signal processing circuits such as the ADC of the column readout circuit 40, transfers them in the horizontal direction, and outputs the signals to a signal processing circuit (not shown).

The timing control circuit 60 generates timing signals necessary for signal processing of the pixel unit 20, the vertical scanning circuit 30, the column readout circuit 40, the horizontal scanning circuit 50, and the like.

The outline of the configuration and function of each part of the solid-state image sensor 10 has been described above.
Next, the pixel signal readout process of the solid-state image sensor 10 according to the first embodiment of the present invention will be described in relation to FIGS. 12 (A) to 12 (J) and FIG. 7.
In the following, a case where light of normal luminance is incident and a case where light of high luminance is incident will be described.

12 (A) to 12 (J) are timing charts for explaining the pixel signal readout process of the solid-state image sensor 10 according to the first embodiment of the present invention.
12 (A) to 12 (J) are shown including the operation of the pixel signal monitoring unit 43A when high-luminance light is incident.
12 (A) shows the read level of the pixel signal PIXOUT, FIG. 12 (B) shows the first reset signal RST, FIG. 12 (C) shows the first enable signal, and FIG. 12 (D) shows the first. The output signal stage1out of the comparator 4311, FIG. 12 (E) shows the second enable signal, FIG. 12 (F) shows RST_B during the second reset sample period, and FIG. 12 (G) shows the second comparator 4312. 12 (H) shows the latch signal latch, FIG. 12 (I) shows the flag signal Col_det, and FIG. 12 (J) shows the output signal (output data) ADC out of the ADC 41.

In the read scan period PRDO, as shown in FIG. 7, in order to select a row in the pixel array, the control signal SEL to the control line connected to each pixel PXL of the selected row is H. The level is set and the selection transistor SEL-Tr of the pixel PXL becomes conductive.
In this selected state, as shown in FIG. 7, the reset transistor RST-Tr is selected during the reset period PR1 and the control signal RST is selected during the H level period to be in the conduction state, and the floating diffusion FD is reset to the power supply potential VDD. ..
After the reset period PR1 has elapsed (the reset transistor RST-Tr is in a non-conducting state), the period until the transfer period PT1 is started is the first read period PRD1 for reading the reset voltage Vrst in the reset state.

As described above, the read reset signal VRST11, which is the pixel read voltage in the reset state, is read through the vertical signal line LSGN11 in the first read period PRD1 after the reset period PR1, and is read to the column read circuit 40 via a load circuit (not shown). It is supplied and retained, for example, after the AD conversion process.

The read reset signal VRST11 input to the column read circuit 40 of each column is first amplified by the amplifier 42A, and the amplifier output AMPout is output to the ADC 41A and the pixel signal monitoring unit 43A.
In the amplifier 42A, the control signal AZ42 becomes H level for a predetermined period after the read reset signal VRST11 of the pixel signal VSL is input (a predetermined period after the first read period for reading the pixel signal in the reset state is started). Set.
As a result, the operational amplifier 421 of the amplifier 42A is reset.
As a result, the output signal (amplifier output) AMPout of the operational amplifier 421 of the amplifier 42A during the auto-zero operation becomes the reference potential Vref1.

(When light of normal brightness is incident)
In the pixel signal monitoring unit 43A, after the first enable signal EN1 becomes the active high level (H) and the first comparator 4311 of the comparison unit 431 enters the comparison operation, the first reset signal PST is predetermined. The reset period is maintained at the high level (H) of PR active.
As a result, in the first comparator 4311, the auto zero switch SW431 is in a conductive state, and the first input terminal (−) and the output terminal are connected to form a voltage follower configuration.
At that time, the first reference voltage Vref1 is supplied to the second input terminal (+), the first comparator 4311 performs an auto-zero operation, and the signal input unit IP43 is compared with the first reference voltage Vref1. The 4311 offset voltage Vofs of the instrument is held.
As a result, the variation for each column is canceled.
Next, the first reset signal RST becomes the inactive low level (L), the second reset signal RST_B becomes the high level (H), the auto zero switch SW431 and the first reference switch SW432 become disconnected, and the first The reference switch SW433 of 2 is in a conductive state, and the reference voltage is switched from the first reference voltage Vref1 to the second reference voltage Vref2.
After this switching, the second enable signal EN2 becomes the active high level (H), and the second comparator 4312 enters the comparison operation.
Then, the output signal S43112 of the second comparator 4312 showing the comparison result of the comparison unit 431 is output to the latch unit 432.

For example, in the latch unit 432 formed by the D-type flip-flop DFF432, the output signal S4312 of the second comparator 4312, which is the output signal of the comparison unit 431, is latched in synchronization with the latch signal latch, and the latch signal latch is at a high level. By (H), the comparison operation of the comparison unit 431 is confirmed, and the flag signal Col_det is output to the calculation unit 411 of the ADC 41A at, for example, the active high level (H) or low level (L).
Here, since it is assumed that light of normal luminance is incident, the black level LB of the read reset signal VRST11 does not exceed the level of the second reference voltage Vref2 (higher than the level of the second reference voltage Vref2). ) The black level has been entered.
Therefore, the output signals of the first comparator 4311 and the second comparator 4312 of the comparator 431 are at the low level (L), and the low level (L) flag signal Col_det is transmitted from the latch portion 432 of the pixel signal monitoring unit 43A. It is output to the arithmetic unit 411 of the ADC 41A.

In the ADC 41, the analog read reset signal VRST11 of each column output of the pixel unit 20 amplified by the amplifier 42A as the amplification unit is converted (AD conversion) into a digital signal.
Then, in the calculation unit 411 of the ADC 41, the pixel signal monitoring unit 43A inputs a flag signal Col_det indicating that a black level that does not exceed the level of the second reference voltage Vref2 (higher than the reference level), which is the reference level, has been input. Is received at a low level (L), for example.
Therefore, when light of normal brightness is incident, the AD conversion code is held in a memory (not shown) as it is converted.

(When high-intensity light is incident)
In this case, since high-intensity light is incident, the black level LB of the read reset signal VRST11 has a black level exceeding the level of the second reference voltage Vref2 (lower than the level of the second reference voltage Vref2). It has been entered.
Therefore, the output signals of the first comparator 4311 and the second comparator 4312 of the comparison unit 431 become high level (H), and the flag signal Col_det of the high level (H) is transmitted from the latch unit 432 of the pixel signal monitoring unit 43A. It is output to the arithmetic unit 411 of the ADC 41A, and the enable signal EN1 is held during the active high level (H) period.

In the ADC 41, the analog read reset signal VRST11 of each column output of the pixel unit 20 amplified by the amplifier 42A as the amplification unit is converted (AD conversion) into a digital signal.
Then, in the calculation unit 411 of the ADC 41, a black level exceeding the level of the second reference voltage Vref2 (lower than the level of the second reference voltage Vref2), which is the reference level, is input by the pixel signal monitoring unit 43A. The flag signal Col_det indicating the above is received at a high level (H).
Therefore, when light of normal brightness is incident, the AD conversion code is a fixed code (fixed to all “1”) and is held in a memory (not shown).

Here, the first read period PRD1 ends, and the transfer period PT1 is set.
As shown in FIG. 7, the transfer transistor TG-Tr is selected during the transfer period PT1 during the period when the control signal TG is at the high level (H) to be in a conductive state, and is photoelectrically converted and accumulated by the photodiode PD. ) Is transferred to the floating diffusion FD.
After the transfer period PT1 has elapsed (the transfer transistor TG-Tr is in a non-conducting state), the second readout period PRD2 is set to read out the signal voltage Vsig corresponding to the charge accumulated by photoelectric conversion by the photodiode PD.

As described above, after the first read period PRD1, the control signal TG is set to the H level for a predetermined period, and the accumulated charge of the photodiode PD is transferred to the floating diffusion FD through the transfer transistor TG-Tr, and after this transfer period PT1. The read signal VSIG11, which is the pixel read voltage corresponding to the electrons (charges) stored in the second read period PRD2, is read by the vertical signal line LSGN11.

The read signal VSIG11 input to the column read circuit 40 of each column is first amplified by the amplifier 42A, and the amplifier output AMPout is output to the ADC 41A and the pixel signal monitoring unit 43A.

In the ADC 41, the analog read signal VSIG 11 of each column output of the pixel unit 20 amplified by the amplifier 42A as the amplification unit is converted (AD conversion) into a digital signal.
The AD conversion code of the read signal VSIG11 is a fixed code and is held in a memory (not shown).

Then, for example, in the read circuit 40 constituting a part of the read unit 70, the read signal VSIG 11 (signal voltage Vsig) read in the second read period PRD2 and the read reset signal VRST11 read in the first read period PRD1. The difference (Vsig-Vrst) from (reset voltage Vrst) is taken and the CDS processing is performed.
Since the decrease in the difference (Vsig-Vrst) between the signal voltage Vsig and the reset voltage (black level) Vrst is extremely small in both the normal luminance and the high luminance, the black crushing caused by this difference is reduced. It is possible to prevent the occurrence of the phenomenon.

As described above, according to the first embodiment, the pixel signal monitoring unit 43 includes the comparison unit 431, and has a pixel reset period PR and a predetermined period at the time of starting reading of the read reset signal VRST 11 after reset release. In addition, the potential of the signal input unit IS43 is initialized to the level of the first reference voltage Vref1, and after the initialization, it is set in the read reset signal VRST11 and the voltage setting unit VS43 of the pixel signal VSL read out to the vertical signal line LSGN11. When the signal level of the read reset signal VRST11 exceeds the second reference voltage Vref2, the conversion code of the AD conversion unit of the ADC 41A is changed to a predetermined code, for example, all "1". Fix it.
When the signal level LVRST of the read reset signal VRST11 of the pixel signal VSL read by the vertical signal line LSGN11 and amplified by the amplifier 42 exceeds the preset reference voltage Vref in each column. (As an example, when the signal level LVRST of the read reset signal VRST11 is lowered by the second reference voltage Vref2), the conversion code of the AD conversion unit of the ADC 41 is fixed to a predetermined code.

Therefore, according to the first embodiment, the decrease in the difference (Vsig-Vrst) between the signal voltage Vsig and the reset voltage (black level) Vrst in the pixel output is extremely small in both the normal luminance and the high luminance. , It is possible to prevent the occurrence of the blackout phenomenon caused by the decrease of this difference.
As described above, according to the first embodiment, it is possible to surely prevent the generation of inverted video noise (prevent sunspots) even if there are variations in the elements for each column. It is possible to achieve high image quality.

(Second embodiment)
FIG. 13 is a diagram showing a column readout system of the solid-state image sensor according to the second embodiment of the present invention.

The difference between the solid-state image sensor 10B according to the second embodiment and the solid-state image sensor 10 according to the first embodiment described above is as follows.
In the solid-state image sensor 10B according to the second embodiment, a clamp circuit 44 for clamping the black level LBRST of the read reset signal VRST11 of the pixel signal VSL read out to the vertical signal line LSGN11 of each column to a predetermined level LBN is arranged. Has been done.
Here, the predetermined level of the black level corresponds to the black level LBNM at the time of normal luminance.

In the clamp circuit 44 of FIG. 13, a clamp transistor CLP-Tr and a selection transistor SL-Tr are connected in series between a vertical signal line SLGN11 from which a pixel signal PIXOUT is read out in each row of a pixel array and a predetermined power source, for example, a power supply potential VDD. It is formed by being connected to.
The gate voltage of the clamp transistor CLP-Tr arranged corresponding to each column is commonly connected to the supply line of the clamp signal CLP by the clamp level generation circuit 200, and the gate voltage of the selection transistor SL-Tr is clamp selection. It is commonly connected to the supply line of the signal CSL.

In the present embodiment, the clamp selection signal CSL is set to the H level active in the reset period PR of the read scan PRDO and the first read period PRD1 by the read unit 70.

As shown in FIG. 4, the clamp circuit 44 clamps the black level LB1 to the black level LB3 when, for example, very strong light (high-intensity light) is incident on one or more pixels, and the signal level SL and the black level The difference in LB is held in ΔV3 (ΔV1≈ΔV3> ΔV2) to prevent the difference from being attenuated from ΔV1 to ΔV2 (ΔV1> ΔV2) and fluctuating.

However, in the above-mentioned CMOS image sensor, since the clamp signal CLP, which is a reference signal for controlling the clamp voltage, is common to all rows, the clamp level also varies due to element variations in each row, and the clamp does not work properly. Can occur.
In the second embodiment, even if such a state occurs, the column read circuit 40 includes the comparison unit 431 and the latch unit 432, and the read reset signal VRST 11 after the pixel reset period PR and the reset release is included. During a predetermined period at the start of reading, the potential of the signal input unit IS43 is initialized to the level of the first reference voltage Vref1, and after initialization, the reading reset signal VRST11 and the voltage of the pixel signal VSL read to the vertical signal line LSGN11. When the signal level of the read reset signal VRST11 exceeds the second reference voltage Vref2 by comparing with the second reference voltage Vrrf2 set in the setting unit VS43, the conversion code of the AD conversion unit of the ADC 41A is changed to a predetermined code. For example, since the pixel signal monitoring unit 43 is fixed to all "1", the following effects can be obtained.
According to the second embodiment, the decrease in the difference (Vsig-Vrst) between the signal voltage Vsig and the reset voltage (black level) Vrst in the pixel output is extremely small in both the normal luminance and the high luminance. It is possible to prevent the occurrence of the blackout phenomenon caused by the decrease in the difference.

As described above, according to the second embodiment, it is possible to surely prevent the generation of inverted video noise even if there are variations in the elements for each column, and eventually, high image quality is realized. It becomes possible to do.

The solid-state imaging device 10 described above can be applied as an imaging device to electronic devices such as digital cameras, video cameras, portable terminals, surveillance cameras, and medical endoscope cameras.

FIG. 14 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which the solid-state image sensor according to the embodiment of the present invention is applied.

As shown in FIG. 14, the electronic device 300 has a CMOS image sensor 310 to which the solid-state image sensor 10 according to the present embodiment can be applied.
Further, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light to the pixel region of the CMOS image sensor 310 (to form an image of a subject image).
The electronic device 300 has a signal processing circuit (PRC) 330 that processes the output signal of the CMOS image sensor 310.

The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310.
The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor including a liquid crystal display or output to a printer, and can be directly recorded on a recording medium such as a memory card. Is possible.

As described above, by mounting the above-mentioned solid-state image sensor 10 as the CMOS image sensor 310, it is possible to provide a high-performance, compact, and low-cost camera system.
Electronic devices such as surveillance cameras and medical endoscope cameras are used in applications where there are restrictions on camera installation requirements such as mounting size, number of connectable cables, cable length, and installation height. Can be realized.

10,10B ... solid-state imaging device, 20 ... pixel unit, 30 ... vertical scanning circuit, 40,40B ... column readout circuit, 41,41A ... ADC, 411 ... arithmetic unit, 42, 42A ... Amplifier, 43, 43A ... Pixel signal monitoring unit, 431 ... Comparison unit, 432 ... Latch unit, 4311 ... First comparator, 4312 ... Second Comparator, SW431 ... auto zero switch, SW432 ... first reference switch, SW433 ... second reference switch, C431 ... sampling capacitor, Vref1 ... first reference voltage, Vref2 ... Second reference voltage, 44 ... clamp circuit, 50 ... horizontal scanning circuit, 60 ... timing control circuit, 70 ... readout unit, 300 ... electronic device, 310 ... CMOS image Sensor, 320 ... Optical system, 330 ... Signal processing circuit (PRC).

Claims (13)

A pixel section in which pixels for photoelectric conversion are arranged in a matrix, and
It has a readout circuit having an analog digital (AD) conversion function that converts a pixel signal read as a voltage signal from the pixel to a signal line from an analog signal to a digital signal.
The pixel signal read from the pixel is
A read reset signal and a read signal read in order from the pixel are included.
The read circuit is
An AD conversion unit that converts the pixel signal read out on the signal line from an analog signal to a digital signal, and
When the signal level of the read reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage, the pixel signal for changing the conversion code of the AD conversion unit to a code different from the normal conversion code. A solid-state image sensor, including a monitoring unit. The pixel signal monitoring unit is
The solid according to claim 1, wherein when the signal level of the read reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage, the conversion code of the AD conversion unit is fixed to a predetermined code. Image sensor. The pixel signal monitoring unit is
A first reference voltage at a level corresponding to the signal level of the read reset signal at the time of reset, and
A second reference voltage at a level higher than the first reference voltage can be set.
Includes a comparison unit that compares the read reset signal of the pixel signal read out to the signal line input to the signal input unit with the reference voltage set in the voltage setting unit.
The comparison unit
The potential of the signal input unit is initialized to the first reference voltage during the reset period of the pixel and the predetermined period at the start of reading the read reset signal after the reset is released, and after the initialization, the signal is read to the signal line. The read reset signal of the pixel signal is compared with the second reference voltage set in the voltage setting unit, and when the signal level of the read reset signal exceeds the second reference voltage, the AD conversion is performed. The solid-state imaging device according to claim 1 or 2, wherein the conversion code of the unit is fixed to a predetermined code. The solid-state imaging device according to claim 3, wherein the second reference voltage is set to a voltage value between the first reference voltage and a voltage corresponding to a black level when high-luminance light is incident. The comparison unit
The first comparator and
With a sampling capacitor
The first auto-zero switch, which can switch between the connected state and the disconnected state by the first reset signal,
The first reference switch, which can switch between the connected state and the disconnected state by the first reset signal,
A second reference switch, which can switch between a connected state and a disconnected state by a second reset signal having a reverse phase to the first reset signal, is included.
The first comparator is
The first input terminal is connected to the sampling switch, and is connected to the pixel signal supply line via the sampling switch.
The auto zero switch is connected between the first input terminal and the output terminal, and the auto zero switch is connected.

The first reference switch is connected between the second input terminal and the supply line of the first reference voltage.
The solid-state image sensor according to claim 3 or 4, wherein the second reference switch is connected between the second input terminal and the supply line of the second reference voltage. The comparison unit
The first comparator includes a second comparator that processes the output signal of the first comparator, and the first comparator performs a comparison operation by an active first enable signal.
The solid-state image sensor according to claim 5, wherein the second comparator performs a comparison operation by a second enable signal that becomes active after the first enable signal. The comparison unit
After the first enable signal becomes active and the first comparator enters the comparison operation,
The first reset signal is activated for a predetermined period, the first input terminal and the output terminal of the first comparator are connected, and the first reference voltage is supplied to the second input terminal. The first comparator performs an auto-zero operation, and the signal input unit holds the first reference voltage and the offset voltage of the first comparator.
The first reset signal becomes inactive, the auto-zero switch and the first reference switch are disconnected, and the reference voltage switches from the first reference voltage to the second reference voltage, and after the switching. , The second enable signal becomes active, the second comparator enters the comparison operation, and the comparison operation is started.
The solid-state image sensor according to claim 6, wherein when the signal level of the read reset signal exceeds the second reference voltage, the conversion code of the AD conversion unit is fixed to a predetermined code. The pixel signal monitoring unit is
Among the output signals of the comparison unit, the detection signal for detecting that the signal level of at least the read reset signal exceeds the second reference voltage is latched, and the conversion code of the AD conversion unit is fixed to a predetermined code. The solid-state imaging device according to any one of claims 3 to 7, further comprising a latch unit that outputs a flag signal instructing that to the AD conversion unit. The read circuit is
Includes an amplifier that amplifies the pixel signal propagated through the signal line and outputs it to the pixel signal monitoring unit and the AD conversion unit.
The solid-state image sensor according to any one of claims 3 to 8, wherein the first reference voltage is set to a voltage value equal to the output voltage at the time of auto zero of the amplifier. The pixel is
A photoelectric conversion element that accumulates the electric charge generated by photoelectric conversion during the accumulation period, and
A transfer element capable of transferring the electric charge accumulated in the photoelectric conversion element during the transfer period, and a transfer element.
Floating diffusion in which the electric charge accumulated in the photoelectric conversion element is transferred through the transfer element, and
A source follower element that converts the charge of the floating diffusion into a voltage signal with a gain corresponding to the amount of charge, and
The solid-state imaging device according to any one of claims 1 to 9, further comprising a reset element that resets the floating diffusion to a predetermined potential during a reset period. The solid-state image sensor according to any one of claims 1 to 10, wherein a clamp circuit for clamping a black level to a predetermined level is arranged in the pixel signal column readout system. A pixel section in which pixels for photoelectric conversion are arranged in a matrix, and
It has a readout circuit having an analog digital (AD) conversion function that converts a pixel signal read as a voltage signal from the pixel to a signal line from an analog signal to a digital signal.
The read circuit is
A method for driving a solid-state image pickup device including an AD conversion unit that converts the pixel signal read out from the signal line from an analog signal to a digital signal.
The pixel signal read from the pixel is
A read reset signal and a read signal read in order from the pixel are included.
In the read circuit
When the signal level of the read reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage, the conversion code of the AD conversion unit is changed to a code different from the normal conversion code. How to drive the device. With a solid-state image sensor,
The solid-state image sensor has an optical system for forming a subject image, and the solid-state image sensor has an optical system.
The solid-state image sensor
A pixel section in which pixels for photoelectric conversion are arranged in a matrix, and
It has a readout circuit having an analog digital (AD) conversion function that converts a pixel signal read as a voltage signal from the pixel to a signal line from an analog signal to a digital signal.
The pixel signal read from the pixel is
A read reset signal and a read signal read in order from the pixel are included.
The read circuit is
An AD conversion unit that converts the pixel signal read out on the signal line from an analog signal to a digital signal, and
When the signal level of the read reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage, the pixel signal for changing the conversion code of the AD conversion unit to a code different from the normal conversion code. Monitoring unit and electronic devices including.

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