JP2021197517A - SiC complementary field effect transistor - Google Patents
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- 230000005669 field effect Effects 0.000 title claims abstract description 60
- 230000000295 complement effect Effects 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 35
- 230000000694 effects Effects 0.000 claims description 5
- 230000005684 electric field Effects 0.000 claims description 3
- 229910052717 sulfur Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 43
- 229910010271 silicon carbide Inorganic materials 0.000 description 42
- 230000037230 mobility Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 239000011593 sulfur Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 235000019788 craving Nutrition 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000284 resting effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
Description
本発明は、炭化珪素（ＳｉＣ）基板を用いて形成されたＳｉＣ相補型電界効果トランジスタに関する。 The present invention relates to a SiC complementary field effect transistor formed using a silicon carbide (SiC) substrate.
現在の半導体集積回路は、主にシリコン（Ｓｉ）で作製されているが、産業分野においては、自動車や航空機のエンジン制御、自動車タイヤのモニター、宇宙用エレクトロニクスなど、Ｓｉでは実現不可能な２００℃以上の高温において動作する集積回路が渇望されている。 Current semiconductor integrated circuits are mainly made of silicon (Si), but in the industrial field, 200 ° C that cannot be realized with Si, such as engine control of automobiles and aircraft, automobile tire monitors, and space electronics, etc. There is a craving for integrated circuits that operate at these high temperatures.
ＳｉＣは、バンドギャップがＳｉに比べて約３倍高いため、５００℃以上の高温環境下で動作する集積回路が作製可能である。 Since the band gap of SiC is about 3 times higher than that of Si, an integrated circuit that operates in a high temperature environment of 500 ° C. or higher can be manufactured.
ＳｉＣ基板を用いて作製した集積回路として、例えば、非特許文献１には、相補型ＭＯＳＦＥＴで構成された集積回路が開示されている。また、特許文献１には、ｎチャネルＪＦＥＴとｐチャネルＪＦＥＴとを半絶縁性のＳｉＣ層で絶縁分離した相補型ＪＦＥＴが開示されている。
As an integrated circuit manufactured by using a SiC substrate, for example, Non-Patent
非特許文献１に開示された相補型ＭＯＳＦＥＴは、ＳｉＣ基板とゲート酸化膜との界面に高密度の欠陥や電荷が存在するため、しきい値電圧が温度により大きく変動し、安定した動作ができないという問題がある。また、ゲート酸化膜が高温で劣化するという問題もある。
Since the complementary MOSFET disclosed in Non-Patent
特許文献１に開示された相補型ＪＦＥＴは、ｎチャネルＪＦＥＴとｐチャネルＪＦＥＴとを、ホットウォールＣＶＤ法で形成されたイントリンシックＳｉＣ層で絶縁分離する構造になっており、微細なトレンチ形成、埋め込み成長、表面平坦化研磨を繰り返す必要があるため、作製プロセスが非常に複雑になるという問題がある。
The complementary JFET disclosed in
今まで、ＳｉＣ基板を用いた相補型電界効果トランジスタに関する研究はいくつか報告されているが、高温動作が確認されたに留まり、広い温度範囲において、安定した動作が可能な相補型電界効果トランジスタは実現できていない。 Although some studies on complementary field-effect transistors using SiC substrates have been reported so far, only complementary field-effect transistors that can operate stably over a wide temperature range have been confirmed to operate at high temperatures. It has not been realized.
本発明は、上記課題に鑑みなされたもので、その主な目的は、広い温度範囲において、安定した動作が可能なＳｉＣ相補型電界効果トランジスタを提供することにある。 The present invention has been made in view of the above problems, and a main object thereof is to provide a SiC complementary field effect transistor capable of stable operation in a wide temperature range.
本発明に係るＳｉＣ相補型電界効果トランジスタは、ＳｉＣ基板に、ノーマリオフ型のｎチャネル電界効果トランジスタ、及びｐチャネル電界効果トランジスタが形成されたＳｉＣ相補型電界効果トランジスタであって、４５０Ｋ以上の温度において、ｎチャネル電界効果トランジスタ、及びｐチャネル電界効果トランジスタの飽和電流が同じ大きさになるように、ｎチャネル電界効果トランジスタのチャネル幅Ｗn、及びｐチャネル電界効果トランジスタのチャネル幅Ｗpの比Ｗn／Ｗp、または、ｎチャネル電界効果トランジスタのチャネル長Ｌn、及びｐチャネル電界効果トランジスタのチャネル長Ｌpの比Ｌn／Ｌpが設定されている。 The SiC complementary field effect transistor according to the present invention is a SiC complementary field effect transistor in which a normally-off type n-channel field effect transistor and a p-channel field effect transistor are formed on a SiC substrate at a temperature of 450 K or higher. , The ratio Wn / Wp of the channel width Wn of the n-channel field-effect transistor and the channel width Wp of the p-channel field-effect transistor so that the saturation currents of the n-channel field-effect transistor and the p-channel field-effect transistor have the same magnitude. Or, the ratio Ln / Lp of the channel length Ln of the n-channel field-effect transistor and the channel length Lp of the p-channel field-effect transistor is set.
本発明に係る他のＳｉＣ相補型電界効果トランジスタは、ＳｉＣ基板に、ノーマリオフ型のｎチャネル電界効果トランジスタ、及びｐチャネル電界効果トランジスタが形成されたＳｉＣ相補型電界効果トランジスタであって、ｐチャネル電界効果トランジスタのチャネル領域にドープされたｐ型不純物がＡｌであって、ｎチャネル電界効果トランジスタのチャネル領域にドープされたｎ型不純物のエネルギー準位が、伝導帯端から０．１３ｅＶ以上離れている。 The other SiC complementary field effect transistor according to the present invention is a SiC complementary field effect transistor in which a normally-off type n-channel field effect transistor and a p-channel field effect transistor are formed on a SiC substrate, and is a p-channel electric field. The p-type impurity doped in the channel region of the effect transistor is Al, and the energy level of the n-type impurity doped in the channel region of the n-channel field effect transistor is 0.13 eV or more away from the conduction band end. ..
本発明によれば、広い温度範囲において、安定した動作が可能なＳｉＣ相補型電界効果トランジスタを提供することができる。 According to the present invention, it is possible to provide a SiC complementary field effect transistor capable of stable operation in a wide temperature range.
本願出願人は、ノーマリオフ化を容易にするＳｉＣ接合型電界効果トランジスタ（以下、「ＳｉＣＪＦＥＴ」という）の構造を、先の出願の明細書（特開２０１９−０９１８７３）に開示している。図１は、その明細書に開示したＳｉＣＪＦＥＴの構造を示した図で、図１（Ａ）は、ｎチャネルＪＦＥＴの平面図、図１（Ｂ）は、図１（Ａ）の線Ｂ−Ｂに沿った断面図、図１（Ｃ）は、図１（Ａ）の線Ｃ−Ｃに沿った断面図である。 The applicant of the present application discloses the structure of a SiC junction type field effect transistor (hereinafter referred to as "SiCJFET") that facilitates normalization in the specification of the previous application (Japanese Patent Laid-Open No. 2019-091873). 1A and 1B are views showing the structure of the SiC JFET disclosed in the specification, FIG. 1A is a plan view of an n-channel JFET, and FIG. 1B is a line BB of FIG. 1A. 1 (C) is a cross-sectional view taken along the line CC of FIG. 1 (A).
図１（Ａ）〜（Ｃ）に示すように、ｎチャネルＪＦＥＴ１は、ＳｉＣ基板１０に形成されたｎ型の埋込チャネル領域１３と、埋込チャネル領域１３を挟んで、互いに対向して形成されたｎ＋型のソース領域１１及びドレイン領域１２と、ソース領域１１及びドレイン領域１２が対向する方向と垂直な方向に形成された一対のｐ＋型のゲート領域１４ａ、１４ｂとを備えている。ｐチャネルＪＦＥＴも、同様の構造を備えている。
As shown in FIGS. 1A to 1C, the n-channel JFET1 is formed so as to face each other with the embedded
ｎチャネルＪＦＥＴ１において、一対のゲート領域１４ａ、１４ｂの幅Ｌがチャネル長、一対のゲート領域１４ａ、１４ｂに挟まれた距離Ｄがチャネル厚さ、埋込チャネル領域１３の深さ方向の距離Ｗがチャネル幅となる。
In the n-
埋込チャネル領域１３内の空乏層の広がりは、埋込チャネル領域１３の両側に形成された一対のゲート領域１４ａ、１４ｂに印加するゲート電圧によって制御される。埋込チャネル領域１３の不純物濃度Ｎ、及び厚さＤを調整することによって、ノーマリオフ型のＳｉＣＪＦＥＴを実現することができる。具体的には、埋込チャネル領域１３の不純物濃度Ｎ（ｃｍ−３）、及び厚さＤ（ｃｍ）を、Ｎ(Ｄ／２）２＜３×１０７ｃｍ−１を満たすように設定すればよい。
The spread of the depletion layer in the embedded
図２は、ノーマリオフ型のｎチャネルＪＦＥＴ１ａと、ノーマリオフ型のｐチャネルＪＦＥＴ１ｂとで構成した相補型ＪＦＥＴからなるインバータ回路を示す。ｎチャネルＪＦＥＴ１ａ及びｐチャネルＪＦＥＴ１ｂのゲート電極は、インバータ回路の入力端子Ｖｉｎに接続されている。ｎチャネルＪＦＥＴ１ａ及びｐチャネルＪＦＥＴ１ｂのドレイン電極Ｄは、インバータ回路の出力端子Ｖoutに接続されている。ｎチャネルＪＦＥＴ１ａのソース電極Ｓはグランドに接続され、ｐチャネルＪＦＥＴ１ｂのソース電極Ｓは電源（ＶＤＤ）に接続されている。 FIG. 2 shows an inverter circuit including a complementary JFET composed of a normally-off type n-channel JFET1a and a normally-off type p-channel JFET1b. The gate electrode of the n-channel JFET1a and p-channel JFET1b is connected to the input terminal V in of the inverter circuit. The drain electrode D of the n-channel JFET1a and the p-channel JFET1b is connected to the output terminal V out of the inverter circuit. The source electrode S of the n-channel JFET1a is connected to the ground, and the source electrode S of the p-channel JFET1b is connected to the power supply (VDD).
通常、インバータ回路は、論理閾値電圧Ｖｔｈが、電源電圧ＶＤＤの１／２になるように設計される。この場合、ｎチャネルＪＦＥＴ１ａ及びｐチャネルＪＦＥＴ１ｂの飽和電流ＩＤｎ、ＩＤｐは等しい。ここで、ＩＤｎ、ＩＤｐは、以下の式（１）、（２）で表される。 Normally, the inverter circuit is designed so that the logic threshold voltage Vth is ½ of the power supply voltage VDD. In this case, the saturation currents I Dn and I Dp of the n-channel JFET1a and the p-channel JFET1b are equal. Here, I Dn and I Dp are represented by the following equations (1) and (2).
上記式（１）、（２）において、ＶＧはゲート電圧、ＶＴｎ、ＶＴｐは、ｎチャネルＪＦＥＴ１ａ及びｐチャネルＪＦＥＴ１ｂの閾値電圧、βｎ、βｐは、ｎチャネルＪＦＥＴ１ａ及びｐチャネルＪＦＥＴ１ｂのベータ値（利得）である。 In the above formula (1), (2), V G is the gate voltage, V Tn, V Tp is n-channel JFET1a and the threshold voltage of the p-channel JFET1b, β n, β p is a n-channel JFET1a and p-channel JFET1b Beta value (gain).
ｎチャネルＪＦＥＴ１ａのゲート電極にはＶｉｎ、ｐチャネルＪＦＥＴ１ｂのゲート電極にはＶｉｎ−ＶＤＤの電圧が印加されるため、上記式（１）、（２）を用いて、ＩＤｎ＝ＩＤｐから、以下の式（３）が得られる。 Since V in the gate electrode of the n-channel JFET1a, voltage V in -V DD to the gate electrode of the p-channel JFET1b is applied, the formula (1), with (2), I Dn = I Dp Therefore, the following equation (3) is obtained.
ＳｉＣ ＪＦＥＴでは、電源電圧ＶＤＤを２．５Ｖ以上にすると、ゲートリークが発生するため、通常、ＶＤＤは２Ｖ程度に設定される。この場合、ＶｔｈはＶＤＤの半分である１Ｖとすることが妥当であるため、上記式（３）は、以下の式（４）で表される。 In a SiC JFET, when the power supply voltage VDD is 2.5V or more, a gate leak occurs, so the VDD is usually set to about 2V. In this case, since it is appropriate that V th is 1 V, which is half of V DD , the above equation (3) is expressed by the following equation (4).
式（４）の左辺は、図１（Ａ）〜（Ｃ）に示した構造のＪＦＥＴにおける物性値や構造寸法を用いて、以下の式（５）で求められる。 The left side of the formula (4) is obtained by the following formula (5) using the physical property values and structural dimensions of the JFET having the structures shown in FIGS. 1 (A) to 1 (C).
上記式（５）において、各パラメータは、以下の通りである。なお、添字ｎ、ｐは、ｎチャネルＪＦＥＴ、ｐチャネルＪＦＥＴのパラメータを示す。 In the above equation (5), each parameter is as follows. The subscripts n and p indicate the parameters of the n-channel JFET and the p-channel JFET.
μｎ、μｐ：電子、正孔の移動度
ｎｎ、ｐｐ：電子密度、正孔密度
Ｗｎ、Ｗｐ：チャネル幅
Ｌｎ、Ｌｐ：チャネル長
Ｄｎ、Ｄｐ：チャネル厚さ
ＮＤ、ＮＡ：チャネル領域１３のドーピング密度
一方、式（４）の右辺は、以下の式（６）で求められる。
μ n, μ p: electrons, hole mobility n n, p p: electron density, hole density W n, W p: channel width L n, L p: channel length D n, D p: channel thickness N D, N a: whereas doping density of the
上記の式（６）において、ψｊｎ、ψｊｐは、ｎチャネルＪＦＥＴ１ａ及びｐチャネルＪＦＥＴ１ｂのゲート部の拡散電位、ψｐｎ、ψｐｐは、ｎチャネルＪＦＥＴ１ａ及びｐチャネルＪＦＥＴ１ｂのピンチオフ電位である。 In the above equation (6), ψ jn and ψ jp are the diffusion potentials of the gate portions of the n-channel JFET1a and p-channel JFET1b, and ψ pn and ψ pp are the pinch-off potentials of the n-channel JFET1a and p-channel JFET1b.
上述したように、論理閾値電圧Ｖｔｈが、電源電圧ＶＤＤの１／２になるように設計するためには、ｎチャネルＪＦＥＴ１ａ及びｐチャネルＪＦＥＴ１ｂの飽和電流ＩＤｎ、ＩＤｐを等しくするために、上記の式（４）が成立するように設計すればよい。この場合、式（６）に示した右辺のパラメータは調整が難しいため、式（５）に示した右辺のパラメータを調整して、式（４）が成立するように設計される。 As described above, in order to design the logic threshold voltage Vth to be 1/2 of the power supply voltage VDD , in order to make the saturation currents I Dn and I Dp of the n-channel JFET1a and the p-channel JFET1b equal. , The above equation (4) may be designed to hold. In this case, since it is difficult to adjust the parameters on the right side shown in the equation (6), the parameters on the right side shown in the equation (5) are adjusted so that the equation (4) is established.
従来、ＭＯＳＦＥＴをＳｉで構成した場合、室温での電子の移動度μｎが、正孔の移動度μｐの約２倍であることから、ｎチャネルＪＦＥＴのチャネル幅Ｗｎを、ｎチャネルＪＦＥＴのチャネル幅Ｗｐの１／２に設定することによって、式（４）が室温で成立するように設計されている。 Conventionally, when the MOSFET is composed of Si, the electron mobility μ n at room temperature is about twice the hole mobility μ p , so that the channel width W n of the n-channel JFET is set to the n-channel JFET. The equation (4) is designed to hold at room temperature by setting the channel width W p to 1/2 of.
ＪＦＥＴをＳｉＣで構成した場合も、Ｓｉの場合と同様の設計指針により、式（４）が室温で成立するように設計することができる。この場合、室温での電子の移動度μｎが、正孔の移動度μｐの約３８倍であることから、ｎチャネルＪＦＥＴのチャネル幅Ｗｎを、ｐチャネルＪＦＥＴのチャネル幅Ｗｐの１／３８（Ｗｎ＝０．４μｍ、Ｗｐ＝１５μｍ）に設定することによって、式（４）が室温で成立するように設計することができる。 Even when the JFET is composed of SiC, it can be designed so that the equation (4) holds at room temperature according to the same design guideline as in the case of Si. In this case, since the electron mobility μ n at room temperature is about 38 times the hole mobility μ p , the channel width W n of the n-channel JFET is 1 of the channel width W p of the p-channel JFET. By setting / 38 (W n = 0.4 μm, W p = 15 μm), the equation (4) can be designed to hold at room temperature.
なお、pチャネルＪＦＥＴのチャネル幅Ｗpを１５μｍに設定する代わりに、例えば、チャネル幅Ｗpを１．５μｍに設定したpチャネルＪＦＥＴを１０個並列に接続してもよい。 Instead of setting the channel width W p of the p-channel JFET to 15 μm, for example, 10 p-channel JFETs having the channel width W p set to 1.5 μm may be connected in parallel.
図３は、図１（Ａ）〜（Ｃ）に示した構造のＳｉＣ ＪＦＥＴを、式（４）が室温で成立するように設計した場合の論理閾値電圧Ｖｔｈの温度特性を計算で求めたグラフ（Ａで示したグラフ）である。また、図４は、インバータ回路の入出力特性の温度特性をシミュレーションにより求めたグラフである。ここで、Ｖｔｈの温度特性は、上記の式（３）を変形して得られる下記の式（７）を用いて計算した。また、インバータ回路の入出力特性の温度特性は、周知の電流−電圧特性の式を用いて計算した。 FIG. 3 shows the temperature characteristics of the logic threshold voltage Vth when the SiC JFET having the structures shown in FIGS. 1 (A) to 1 (C) is designed so that the equation (4) holds at room temperature. It is a graph (graph shown by A). Further, FIG. 4 is a graph obtained by simulating the temperature characteristics of the input / output characteristics of the inverter circuit. Here, the temperature characteristic of V th was calculated using the following equation (7) obtained by modifying the above equation (3). The temperature characteristics of the input / output characteristics of the inverter circuit were calculated using the well-known current-voltage characteristic equation.
なお、計算は、図１（Ａ）〜（Ｃ）に示したＳｉＣ ＪＦＥＴの構造において、下記のパラメータの数値を用いた。なお、移動度μｎ、μｐは、文献（H. Matsuura et al., J. Appl. Phys. 96 (2004) 2708, S. Kagamihara et al., J. Appl. Phys. 96 (2004) 5601）で与えられた式を用いて計算した。また、キャリア密度ｎｎ、ｐｐは、一般の教科書（例えば、S. M. Sze and K. K. Ng, Physics of Semiconductor (John Wiley $ Sons）に載っている周知の方程式を用いて計算した。 In the calculation, the numerical values of the following parameters were used in the structure of the SiC JFET shown in FIGS. 1 (A) to 1 (C). The mobilities μ n and μ p are described in the literature (H. Matsuura et al., J. Appl. Phys. 96 (2004) 2708, S. Kagamihara et al., J. Appl. Phys. 96 (2004) 5601. ) Was calculated using the formula given in. Further, the carrier density n n, p p is generally textbooks (e.g., calculated using well known equations resting on SM Sze and KK Ng, Physics of Semiconductor (John Wiley $ Sons).
Ｗｎ、Ｗｐ：０．４μｍ、１５μｍ
Ｌｎ、Ｌｐ：４μｍ、４μｍ
Ｄｎ、Ｄｐ：４２５ｎｍ、４２８ｎｍ
ＮＤ、ＮＡ：５×１０１６ｃｍ−３、５×１０１６ｃｍ−３
なお、図３には、式（４）の右辺の温度特性を、式（６）を用いて計算した結果（Ｂで示したグラフ）、及び、式（４）の左辺の温度特性を、式（５）を用いて計算した結果（Ｃで示した曲線）も示している。
W n , W p : 0.4 μm, 15 μm
L n , L p : 4 μm, 4 μm
D n , D p : 425 nm, 428 nm
N D, N A: 5 × 10 16 cm -3, 5 × 10 16 cm -3
In FIG. 3, the temperature characteristics on the right side of the equation (4) are calculated using the equation (6) (graph shown by B), and the temperature characteristics on the left side of the equation (4) are shown in the equation. The result calculated using (5) (curve shown by C) is also shown.
図３に示すように、矢印Ｐで示す室温（３００Ｋ）において、Ｂで示したグラフと、Ｃで示したグラフは一致しており、論理閾値電圧Ｖｔｈは１Ｖに設定されている。しかしながら、図３及び図４に示すように、論理閾値電圧Ｖｔｈは、温度が高くなるにつれて、１Ｖから大きくシフトしている。これは、式（４）の右辺と左辺の値が、それぞれ、図３のグラフＢ、Ｃに示すように、異なる温度特性を有するため、式（４）が高温側で成立しなくなったためである。 As shown in FIG. 3, at room temperature (300K) indicated by the arrow P, the graph indicated by B and the graph indicated by C are in agreement, and the logic threshold voltage Vth is set to 1V. However, as shown in FIGS. 3 and 4, the logic threshold voltage Vth largely shifts from 1V as the temperature increases. This is because the values on the right side and the left side of the equation (4) have different temperature characteristics as shown in the graphs B and C of FIG. 3, so that the equation (4) does not hold on the high temperature side. ..
このように、広い温度範囲で、論理閾値電圧Ｖｔｈの変動を抑えるためには、既存のＳｉ論理回路で採用されていた設計指針とは異なる構造設計が必要となる。そのためには、論理閾値電圧Ｖｔｈを決定するパラメータの物性値の温度依存性を考慮した設計を行うことが必要となる。 As described above, in order to suppress the fluctuation of the logic threshold voltage Vth in a wide temperature range, a structural design different from the design guideline adopted in the existing Si logic circuit is required. For that purpose, it is necessary to design in consideration of the temperature dependence of the physical property value of the parameter that determines the logical threshold voltage Vth.
（第１の実施形態）
本願発明者等は、上記の式（７）において、論理閾値電圧Ｖｔｈを決定するパラメータとして、ｎチャネルＪＦＥＴの閾値電圧ＶＴｎ、及びｐチャネルＪＦＥＴの閾値電圧ＶＴｐに着目した。すなわち、室温付近では、ＶＴｎとＶＴｐの差は小さいため、式（４）が成立していなくても、論理閾値電圧Ｖｔｈは、電源電圧ＶＤＤの１／２ほどに定まる。一方、高温では、ＶＴｎとＶＴｐの差が大きくなるが、高温側で、式（４）が成立するように構造設計しておけば、高温側においても、論理閾値電圧Ｖｔｈを、電源電圧ＶＤＤの１／２ほどに定めることができる。
(First Embodiment)
The present inventors have found that in the above formula (7), as a parameter to determine the logical threshold voltage V th, the threshold voltage V Tn of the n-channel JFET, and focused on the threshold voltage V Tp of the p-channel JFET. That is, since the difference between VTn and VTp is small near room temperature, the logic threshold voltage Vth is determined to be about 1/2 of the power supply voltage VDD even if the equation (4) does not hold. On the other hand, at high temperatures, the difference between VTn and VTp becomes large, but if the structure is designed so that equation (4) holds on the high temperature side, the logic threshold voltage Vth can be used as a power source even on the high temperature side. It can be set to about 1/2 of the voltage VDD.
図５は、図１（Ａ）〜（Ｃ）に示した構造のＳｉＣ ＪＦＥＴを、式（４）が高温側（７００Ｋ）で成立するように設計した場合の論理閾値電圧Ｖｔｈの温度特性を上記式（７）を用いて計算で求めたグラフ（Ａで示したグラフ）である。また、図６は、インバータ回路の入出力特性の温度特性を周知の電流−電圧特性の式を用いて計算で求めたグラフである。ここで、７００Ｋでの電子の移動度μｎが、正孔の移動度μｐの約１２倍であることから、ｎチャネルＪＦＥＴのチャネル幅Ｗｎを、ｐチャネルＪＦＥＴのチャネル幅Ｗｐの１／１２（Ｗｎ＝０．４μｍ、Ｗｐ＝５μｍ）に設定することによって、式（４）が７００Ｋで成立するように設計した。それ以外のパラメータは、図３で示した場合と同じである。 FIG. 5 shows the temperature characteristics of the logical threshold voltage Vth when the SiC JFET having the structures shown in FIGS. 1A to 1C is designed so that the equation (4) holds on the high temperature side (700K). It is a graph (graph shown by A) obtained by calculation using the above formula (7). Further, FIG. 6 is a graph obtained by calculating the temperature characteristics of the input / output characteristics of the inverter circuit using a well-known current-voltage characteristic equation. Here, since the electron mobility μ n at 700 K is about 12 times the hole mobility μ p , the channel width W n of the n-channel JFET is 1 of the channel width W p of the p-channel JFET. By setting to / 12 (W n = 0.4 μm, W p = 5 μm), the equation (4) was designed to hold at 700K. Other parameters are the same as those shown in FIG.
なお、pチャネルＪＦＥＴのチャネル幅Ｗpを５μｍに設定する代わりに、例えば、チャネル幅Ｗpを１μｍに設定したpチャネルＪＦＥＴを５個並列に接続してもよい。 Instead of setting the channel width W p of the p-channel JFET in 5 [mu] m, for example, it may be connected to p-channel JFET set the channel width W p to 1μm in five parallel.
また、図５には、式（４）の右辺の温度特性を、式（６）を用いて計算した結果（Ｂで示したグラフ）、及び、式（４）の左辺の温度特性を、式（５）を用いて計算した結果（Ｃで示した曲線）も示している。 Further, in FIG. 5, the temperature characteristics on the right side of the equation (4) are calculated using the equation (6) (graph shown by B), and the temperature characteristics on the left side of the equation (4) are shown in the equation. The result calculated using (5) (curve shown by C) is also shown.
図５に示すように、矢印Ｑで示す高温（７００Ｋ）において、Ｂで示したグラフと、Ｃで示したグラフは一致しており、論理閾値電圧Ｖｔｈは１Ｖに設定されている。また、Ｂで示したグラフと、Ｃで示したグラフが、室温側で一致していなくても、図５及び図６に示すように、論理閾値電圧Ｖｔｈは、室温側でもほぼ１Ｖになっている。 As shown in FIG. 5, at the high temperature (700K) indicated by the arrow Q, the graph indicated by B and the graph indicated by C are in agreement, and the logic threshold voltage Vth is set to 1V. Further, even if the graph shown by B and the graph shown by C do not match on the room temperature side, the logic threshold voltage Vth becomes almost 1 V even on the room temperature side as shown in FIGS. 5 and 6. ing.
このように、高温側で、式（４）が成立するように構造設計することによって、広い温度範囲において、論理閾値電圧Ｖｔｈの変動を大幅に抑制することができる。すなわち、室温よりも高温側において、ｎチャネルＪＦＥＴ、及びｐチャネルＪＦＥＴの飽和電流ＩＤｎ、ＩＤｐが同じ大きさになるように、ｎチャネルＪＦＥＴのチャネル幅Ｗn、及びｐチャネルＪＦＥＴのチャネル幅Ｗpの比Ｗn／Ｗpを設定することによって、広い温度範囲において、論理閾値電圧Ｖｔｈの変動を大幅に抑制することができる。これにより、広い温度範囲において、安定した動作が可能なＳｉＣ相補型電界効果トランジスタが得られる。 As described above, by designing the structure so that the equation (4) holds on the high temperature side, the fluctuation of the logic threshold voltage Vth can be significantly suppressed in a wide temperature range. That is, the channel width Wn of the n-channel JFET and the channel width Wp of the p-channel JFET so that the saturation currents I Dn and I Dp of the n-channel JFET and the p-channel JFET have the same magnitude on the higher temperature side than room temperature. By setting the ratio Wn / Wp of, the fluctuation of the logic threshold voltage Vth can be significantly suppressed in a wide temperature range. As a result, a SiC complementary field effect transistor capable of stable operation over a wide temperature range can be obtained.
なお、図５では、ｎチャネルＪＦＥＴとｐチャネルＪＦＥＴのチャネル比Ｗn／Ｗpを、７００Ｋで式（４）が成立するように設計した例を説明したが、図５において、４５０Ｋ以上では、グラフＢとグラフＣとの差が、４５０Ｋ以下の差に比べて少ないことから、４５０Ｋ以上で、式（４）が成立するように、すなわち、ｎチャネルＪＦＥＴ、及びｐチャネルＪＦＥＴの飽和電流ＩＤｎ、ＩＤｐが同じ大きさになるように設計すればよい。 In addition, in FIG. 5, an example in which the channel ratio Wn / Wp of the n-channel JFET and the p-channel JFET is designed so that the equation (4) holds at 700K has been described. Since the difference between the graph C and the graph C is smaller than the difference of 450K or less, the equation (4) holds at 450K or more, that is, the saturation currents I Dn , I of the n-channel JFET and the p-channel JFET. It may be designed so that Dp has the same size.
また、上記の説明では、ｎチャネルＪＦＥＴとｐチャネルＪＦＥＴのチャネル比Ｗn／Ｗpを、高温側（４５０Ｋ以上）で、ｎチャネルＪＦＥＴ、及びｐチャネルＪＦＥＴの飽和電流ＩＤｎ、ＩＤｐが一致するように設計したが、必ずしも一致させる必要はなく、広い温度範囲で論理閾値電圧Ｖｔｈの変動が抑制できる範囲で、飽和電流ＩＤｎ、ＩＤｐを揃えればよい。 Further, in the above description, the channel ratio Wn / Wp of the n-channel JFET and the p-channel JFET is set so that the saturation currents I Dn and I Dp of the n-channel JFET and the p-channel JFET match on the high temperature side (450 K or more). However, it is not always necessary to match them, and the saturation currents I Dn and I Dp may be aligned within a range in which the fluctuation of the logic threshold voltage Vth can be suppressed in a wide temperature range.
なお、チャネル幅の比Ｗn／Ｗpを設定する代わりに、ｎチャネルＪＦＥＴのチャネル長Ｌn、及びｐチャネルＪＦＥTのチャネル長Ｌpの比Ｌn／Ｌpを設定してもよい。 Instead of setting the ratio Wn / Wp of the channel width, the ratio Ln / Lp of the channel length Ln of the n-channel JFET and the channel length Lp of the p-channel JFET may be set.
（第２の実施形態）
上記実施形態では、論理閾値電圧Ｖｔｈを決定するパラメータとして、ｎチャネルＪＦＥＴの閾値電圧ＶＴｎ、及びｐチャネルＪＦＥＴの閾値電圧ＶＴｐに着目したが、本願発明者等は、上記の式（５）に示したβＲのパラメータのうち、温度変化に最も影響があるパラメータとして、埋込チャネル領域１３にドープされたｐ型不純物の正孔密度ｐｐに着目した。
(Second embodiment)
In the above embodiment, the parameter for determining the logic threshold voltage V th, the threshold voltage V Tn of the n-channel JFET, and was focused on the threshold voltage V Tp of the p-channel JFET, the present inventors have found that the above equation (5 ) to β among the parameters of R shown, as parameters that most affect the temperature change, focusing on the hole density p p a p-type impurity doped in the buried
図７は、ＳｉＣ ＪＦＥＴにおいて、電子及び正孔のキャリア密度の温度依存性を示したグラフである。ここで、Ａで示したグラフが電子密度ｎｎ、Ｂで示したグラフが正孔密度ｐｐを示す。ｎ型不純物は、Ｐ（リン）、ｐ型不純物はＡｌ（アルミニウム）である。 FIG. 7 is a graph showing the temperature dependence of the carrier densities of electrons and holes in a SiC JFET. Here, the graph chart shown in A showed electron density n n, and B represents a hole density p p. The n-type impurity is P (phosphorus) and the p-type impurity is Al (aluminum).
図７に示すように、電子密度ｎｎは、広い温度範囲においてほぼ一定であるのに対し、正孔密度ｐｐは、室温から高温にかけて大きく変化している。これは、ｎ型不純物のエネルギー準位が、伝導帯端から浅く（約０．０６ｅＶ）、イオン化率が大きいのに対し、ｐ型不純物のエネルギー準位が、価電子帯端から深く（約０．２ｅＶ）、イオン化率が小さいためである。そのため、正孔密度ｐｐのみが温度変化が大きく、式（５）に示すように、正孔密度ｐｐの温度変化が、βＲ（∝ｎｎ／ｐｐ）の温度変化に大きく影響する。 As shown in FIG. 7, the electron density n n is contrast is nearly constant over a wide temperature range, a hole density p p is significantly changed over the hot from room. This is because the energy level of the n-type impurity is shallow from the conduction band end (about 0.06 eV) and the ionization rate is large, while the energy level of the p-type impurity is deep from the valence band end (about 0). .2eV), because the ionization rate is small. Therefore, only the hole density p p is the temperature change is large, as shown in Equation (5), the temperature change of the hole density p p greatly affects the temperature change of the beta R (.alpha.n n / p p) ..
そこで、ｎ型不純物として、ｐ型不純物と同じように深いエネルギー準位を有する不純物を用いることによって、電子密度ｎｎの温度変化を、正孔密度ｐｐの温度変化と揃えることができる。 Therefore, the n-type impurity by using the impurity having a similar deep energy levels and the p-type impurity, the temperature variation of the electron density n n, can be aligned with the temperature change of the hole density p p.
図８は、ｎ型不純物のエネルギー準位が、伝導帯端から深い不純物として、Ｓ（硫黄）を用いた場合の電子及び正孔のキャリア密度の温度依存性を示したグラフである。なお、ＳSのエネルギー準位は、伝導帯端から約０．２６ｅＶである。ここで、Ａで示したグラフが正孔密度ｐｐ、Ｂで示したグラフが電子密度ｎｎを示す。図８に示すように、電子密度ｎｎ、及び正孔密度ｐｐは、室温から高温にかけて、広い温度範囲でほぼ同じように変化する。 FIG. 8 is a graph showing the temperature dependence of the carrier density of electrons and holes when the energy level of the n-type impurity is S (sulfur) as an impurity deep from the conduction band end. The energy level of SS is about 0.26 eV from the end of the conduction band. Here, the graph indicated by A indicates the hole density pp , and the graph indicated by B indicates the electron density n n . As shown in FIG. 8, the electron density n n, and hole density p p is toward the high temperature from room temperature, varies in substantially the same manner over a wide temperature range.
図９は、ｎ型不純物としてＳ、ｐ型不純物としてＡｌを用いた場合の論理閾値電圧Ｖｔｈの温度特性を、上記式（７）を用いて計算で求めたグラフ（Ａで示したグラフ）である。また、図１０は、インバータ回路の入出力特性の温度特性を周知の電流−電圧特性の式を用いて計算で求めたグラフである。なお、図１０には、式（４）の右辺の温度特性を、式（６）を用いて計算した結果（Ｂで示したグラフ）、及び、式（４）の左辺の温度特性を、式（５）を用いて計算した結果（Ｃで示した曲線）も示している。 FIG. 9 is a graph (graph shown by A) obtained by calculation using the above equation (7) for the temperature characteristics of the logical threshold voltage Vth when S is used as the n-type impurity and Al is used as the p-type impurity. Is. Further, FIG. 10 is a graph obtained by calculating the temperature characteristics of the input / output characteristics of the inverter circuit using a well-known current-voltage characteristic equation. In FIG. 10, the temperature characteristics on the right side of the equation (4) are calculated using the equation (6) (graph shown by B), and the temperature characteristics on the left side of the equation (4) are shown in the equation. The result calculated using (5) (curve shown by C) is also shown.
図９及び図１０に示すように、論理閾値電圧Ｖｔｈは、広い温度範囲で、約１Ｖになっている。これは、図９に示すように、Ｂで示したグラフと、Ｃで示したグラフが、広い温度範囲でほぼ重なっており、式（４）の右辺の温度特性と、式（４）の左辺の温度特性が、ほぼ一致し、式（４）が、広い温度範囲で成立しているためである。 As shown in FIGS. 9 and 10, the logic threshold voltage Vth is about 1 V over a wide temperature range. As shown in FIG. 9, the graph shown by B and the graph shown by C almost overlap in a wide temperature range, and the temperature characteristics on the right side of the equation (4) and the left side of the equation (4) are substantially overlapped. This is because the temperature characteristics of the above are almost the same, and the equation (4) is established in a wide temperature range.
このように、ｎ型不純物として、ｐ型不純物と同じように深いエネルギー準位を有する不純物を用いることによって、広い温度範囲において、論理閾値電圧Ｖｔｈの変動を大幅に抑制することができる。ここで、ｎチャネルＪＦＥＴの埋込チャネル領域１３にドープされたｎ型不純物のエネルギー準位は、伝導帯端から０．１３ｅＶ以上離れていることが好ましい。
As described above, by using an impurity having a deep energy level as the p-type impurity as the n-type impurity, the fluctuation of the logic threshold voltage Vth can be significantly suppressed in a wide temperature range. Here, the energy level of the n-type impurity doped in the embedded
図８では、深いエネルギー準位を有するｎ型不純物として、Ｓ（硫黄）を用いる例を説明したが、Ｓ以外に、例えばＡｓ（ヒ素）等を用いることができる。ここで、Ａｓのエネルギー準位は、伝導帯端から約０．１３ｅＶである（文献：J. B. Tucker et al., Diamond and Related Materials 9 (2000) 1887）。図７のＡで示したグラフのｎ型不純物（Ｐ）のエネルギー準位が０．０６ｅＶで、図８のＡで示したグラフのｎ型不純物（Ｓ）のエネルギー準位が０．２６ｅＶであることから、エネルギー準位が０．１３ｅＶのＡｓのキャリア密度の温度依存性は、その中間付近であることから、Ｂで示したグラフのｐ型不純物（Ａｌ）のキャリア密度の温度依存性に近くなり、論理閾値電圧Ｖｔｈの変動を抑えることができるものと推定される。 In FIG. 8, an example in which S (sulfur) is used as an n-type impurity having a deep energy level has been described, but for example, As (arsenic) or the like can be used in addition to S. Here, the energy level of As is about 0.13 eV from the end of the conduction band (Reference: JB Tucker et al., Diamond and Related Materials 9 (2000) 1887). The energy level of the n-type impurity (P) in the graph shown in FIG. 7A is 0.06 eV, and the energy level of the n-type impurity (S) in the graph shown in FIG. 8A is 0.26 eV. Therefore, the temperature dependence of the carrier density of As with an energy level of 0.13 eV is near the middle, and is close to the temperature dependence of the carrier density of the p-type impurity (Al) in the graph shown in B. Therefore, it is presumed that the fluctuation of the logic threshold voltage Vth can be suppressed.
本実施形態では、ＳｉＣ ＪＦＥＴの新規な構造設計により、広い温度範囲において、論理閾値電圧Ｖｔｈの変動を大幅に抑制することができるが、ＳｉＣＪＦＥＴの作製プロセスのバラツキにより、デバイスパラメータが設計値からずれることによって、論理閾値電圧Ｖｔｈが変動することがある。本実施形態では、このような場合でも、論理閾値電圧Ｖｔｈの変動を抑制する効果が得られる。以下、ＳｉＣＪＦＥＴのチャネル厚さＤが設計値からずれた場合を例に説明する。 In the present embodiment, the fluctuation of the logic threshold voltage Vth can be significantly suppressed in a wide temperature range by the novel structural design of the SiC JFET, but the device parameters are changed from the design values due to the variation in the manufacturing process of the SiC JFET. The deviation may cause the logic threshold voltage Vth to fluctuate. In the present embodiment, even in such a case, the effect of suppressing the fluctuation of the logic threshold voltage Vth can be obtained. Hereinafter, a case where the channel thickness D of the SiC JFET deviates from the design value will be described as an example.
論理閾値電圧Ｖｔｈは、上記の式（７）で決まるが、式（７）中の閾値電圧ＶＴは、以下の式（８）で求められる。 Logic threshold voltage V th is determined by the above equation (7), the threshold voltage V T in equation (7) is obtained by the following equation (8).
ここで、ψｊは拡散電位、ψｐはピンチオフ電位である。また、ピンチオフ電位ψｐは、以下の式（９）で求められる。 Here, ψ j is the diffusion potential and ψ p is the pinch-off potential. Further, the pinch-off potential ψ p is obtained by the following equation (9).
ここで、ｑは電子の電荷、εsはＳｉＣの誘電率、Ｎは埋込チャネル領域１３の不純物濃度、Ｄは埋込チャネル領域１３の厚さである。
Here, q is the charge of electrons, ε s is the dielectric constant of SiC, N is the impurity concentration of the embedded
式（９）に示すように、チャネル厚みＤが変化すると、ピンチオフ電位ψｐが変化し、式（８）に示すように、ピンチオフ電位ψｐが変化すると、閾値電圧ＶＴも変化する。そのため、式（７）に示すように、論理閾値電圧Ｖｔｈも変化する。 As shown in the equation (9), when the channel thickness D changes, the pinch-off potential ψ p changes, and as shown in the equation (8), when the pinch-off potential ψ p changes, the threshold voltage VT also changes. Therefore, as shown in the equation (7), the logic threshold voltage Vth also changes.
図１１は、チャネル厚さＤが、設計値４２５ｎｍに対して、プロセスバラツキにより５００ｎｍになった場合のインバータ回路の入出力特性を示したグラフである。Ａで示したグラフが、Ｄ＝４２５ｎｍの場合、Ｂに示したグラフが、Ｄ＝５００ｎｍで、ｎ型不純物にＰ（浅いエネルギー準位）を用いた場合、Ｃに示したグラフが、Ｄ＝５００ｎｍで、ｎ型不純物にS（深いエネルギー準位）を用いた場合を、それぞれ示す。 FIG. 11 is a graph showing the input / output characteristics of the inverter circuit when the channel thickness D becomes 500 nm due to process variation with respect to the design value of 425 nm. When the graph shown by A is D = 425 nm, the graph shown by B is D = 500 nm, and when P (shallow energy level) is used for the n-type impurity, the graph shown by C is D =. The case where S (deep energy level) is used for the n-type impurity at 500 nm is shown respectively.
図１１に示すように、ｎ型不純物にSを用いた場合の方が、Ｐを用いた場合よりも、論理閾値電圧Ｖｔｈの変化が小さい。すなわち、エネルギー準位の深いｎ型不純物を用いることによって、プロセスバラツキにより、デバイスパラメータが設計値からずれても、論理閾値電圧Ｖｔｈの変動を抑えることができる。 As shown in FIG. 11, the change in the logic threshold voltage Vth is smaller when S is used as the n-type impurity than when P is used. That is, by using n-type impurities having a deep energy level, it is possible to suppress fluctuations in the logic threshold voltage Vth even if the device parameters deviate from the design values due to process variation.
上記では、チャネル厚みＤの変動を例に説明したが、他のデバイスパラメータが変動した場合にも、同様の効果を得ることができる。 In the above, the variation of the channel thickness D has been described as an example, but the same effect can be obtained even when other device parameters are varied.
（第３の実施形態）
上記実施形態では、ｎチャネルＪＦＥＴの飽和電流ＩＤｎと、ｐチャネルＪＦＥＴの飽和電流ＩＤｐが、広い温度範囲で一致するように、ＪＦＥＴの構造設計を行ったが、図１２に示すように、ＳｉＣ基板１０に、ｎチャネルＪＦＥＴ１の埋込チャネル領域１３と同じｎ型不純物のイオン注入領域２２で抵抗２０を形成し、ＪＦＥＴ１に抵抗２０を直列接続した構成にしてもよい。この場合、イオン注入領域２２のｎ型不純物には、エネルギー準位の深い不純物（例えばS）を使用する。
(Third embodiment)
In the above embodiment , the structure of the JFET is designed so that the saturation current I Dn of the n-channel JFET and the saturation current I Dp of the p-channel JFET match in a wide temperature range. As shown in FIG. A
抵抗２０が直列接続されたｎチャネルＪＦＥＴ１では、抵抗２０による電圧降下分だけドレイン電圧が低下する。そのため、ドレイン電圧は、抵抗２０の温度変化に応じて変化する。その結果、ｎチャネルＪＦＥＴの飽和電流ＩＤｎと、ｐチャネルＪＦＥＴの飽和電流ＩＤｐを、広い温度範囲で一致させることができる。これにより、広い温度範囲で、論理閾値電圧Ｖｔｈの変動を抑えることができる。
In the n-channel JFET1 in which the
以上、本発明を好適な実施形態により説明してきたが、こうした記述は限定事項ではなく、もちろん、種々の改変が可能である。 Although the present invention has been described above in terms of preferred embodiments, such a description is not a limitation, and of course, various modifications can be made.
例えば、上記実施形態では、ＳｉＣ相補型ＪＦＥＴをインバータ回路に適用した例を説明したが、他の論理ゲートにも適用することもできる。 For example, in the above embodiment, the example in which the SiC complementary JFET is applied to the inverter circuit has been described, but it can also be applied to other logic gates.
図１３は、ノーマリオフ型のｎチャネルＪＦＥＴと、ノーマリオフ型のｐチャネルＪＦＥＴとで構成した相補型ＪＦＥＴからなるｎ入力（多入力）ＮＡＮＤ回路を示した図である。 FIG. 13 is a diagram showing an n-input (multi-input) NAND circuit including a complementary JFET composed of a normally-off type n-channel JFET and a normally-off type p-channel JFET.
図１３に示すように、ｎチャネルＪＦＥＴが直列接続され、ｐチャネルＪＦＥＴが並列接続されている。そのため、直列接続されたｎチャネルＪＦＥＴは、チャネル長がｎ倍されたと考えられ、ＩＤｎ＝ＩＤｐを満たすためには、ｎチャネルＪＦＥＴのベータ値βをｎ倍する必要がある。従って、この場合、ＩＤｎ＝ＩＤｐを満たすために、上記式（３）の代わりに、以下の式（１０）が成立するよう、チャネル幅の比Ｗn／Ｗp、または、チャネル長の比Ｌn／Ｌpを調整すればよい。 As shown in FIG. 13, n-channel JFETs are connected in series and p-channel JFETs are connected in parallel. Therefore, it is considered that the channel length of the n-channel JFETs connected in series is multiplied by n, and it is necessary to multiply the beta value β of the n-channel JFET by n in order to satisfy IDn = IDp. Therefore, in this case, in order to satisfy IDn = IDp , the channel width ratio Wn / Wp or the channel length ratio Ln so that the following equation (10) is established instead of the above equation (3). / Lp may be adjusted.
図１４は、ノーマリオフ型のｎチャネルＪＦＥＴと、ノーマリオフ型のｐチャネルＪＦＥＴとで構成した相補型ＪＦＥＴからなるｎ入力ＮＯＲ回路を示した図である。 FIG. 14 is a diagram showing an n-input NOR circuit including a complementary JFET composed of a normally-off type n-channel JFET and a normally-off type p-channel JFET.
図１４に示すように、ｎチャネルＪＦＥＴが並列接続され、ｐチャネルＪＦＥＴが直列接続されている。そのため、直列接続されたｐチャネルＪＦＥＴは、チャネル長がｎ倍されたと考えられ、ＩＤｎ＝ＩＤｐを満たすためには、ｐチャネルＪＦＥＴのベータ値βをｎ倍する必要がある。従って、この場合、ＩＤｎ＝ＩＤｐを満たすために、上記式（３）の代わりに、以下の式（１１）が成立するよう、チャネル幅の比Ｗn／Ｗp、または、チャネル長の比Ｌn／Ｌpを調整すればよい。 As shown in FIG. 14, n-channel JFETs are connected in parallel and p-channel JFETs are connected in series. Therefore, it is considered that the channel length of the p-channel JFETs connected in series is multiplied by n, and it is necessary to multiply the beta value β of the p-channel JFET by n in order to satisfy IDn = IDp. Therefore, in this case, in order to satisfy IDn = IDp , the channel width ratio Wn / Wp or the channel length ratio Ln so that the following equation (11) is established instead of the above equation (3). / Lp may be adjusted.
また、上記実施形態では、上記式（３）から、電源電圧ＶＤＤを２Ｖ、Ｖｔｈを１Ｖとして、式（４）を算出し、高温側（４５０Ｋ以上）において、式（４）が成立するよう、チャネル幅の比Ｗn／Ｗp、または、チャネル長の比Ｌn／Ｌpを調整したが、電源電圧を２．５Ｖ以下の任意の値ＶＤＤとして、以下の式（１０）が高温側で成立するよう、チャネル幅の比Ｗn／Ｗp、または、チャネル長の比Ｌn／Ｌpを調整してもよい。 Further, in the above embodiment, the formula (4) is calculated from the above formula (3) with the power supply voltage VDD as 2V and Vth as 1V, and the formula (4) is established on the high temperature side (450K or higher). The following equation (10) holds on the high temperature side, assuming that the channel width ratio Wn / Wp or the channel length ratio Ln / Lp is adjusted, but the power supply voltage is an arbitrary value VDD of 2.5 V or less. As such, the ratio Wn / Wp of the channel width or the ratio Ln / Lp of the channel length may be adjusted.
また、上記実施形態では、ＳｉＣ相補型ＪＦＥＴを例に説明したが、ＳｉＣ相補型ＭＯＳＦＥＴにも適用することができる。 Further, in the above embodiment, the SiC complementary type JFET has been described as an example, but it can also be applied to the SiC complementary type MOSFET.
また、上記実施形態では、図１に示した構造のＳｉＣ ＪＦＥＴを例に説明したが、勿論、他の構造のＳｉＣ ＪＦＥＴまたはＳｉＣ ＭＯＳＦＥＴに適用することができる。 Further, in the above embodiment, the SiC JFET having the structure shown in FIG. 1 has been described as an example, but of course, it can be applied to a SiC JFET or a SiC MOSFET having another structure.
また、上記実施形態では、ＳｉＣ基板を用いて形成されたＳｉＣ ＪＦＥＴを例に説明したが、ワイドギャップ半導体であるＧａＮやダイヤモンドを基板に用いて形成した電界効果トランジスタにも適用することができる。 Further, in the above embodiment, the SiC JFET formed by using a SiC substrate has been described as an example, but it can also be applied to a field effect transistor formed by using GaN or diamond, which is a wide-gap semiconductor, as an example.
１ ＪＦＥＴ
１ａ ｎチャネルＪＦＥＴ
１ｂ ｐチャネルＪＦＥＴ
１０ ＳｉＣ基板
１１ ソース領域
１２ ドレイン領域
１３ 埋込チャネル領域
１４ａ、１４ｂ ゲート領域
２０ 抵抗
２２ イオン注入領域
1 JFET
1an channel JFET
1b p channel JFET
10 SiC substrate
11 Source area
12 drain area
13 Embedded channel area
14a, 14b Gate area
20 resistance
22 Ion implantation area
Claims (5)
４５０Ｋ以上の温度において、前記ｎチャネル電界効果トランジスタ、及び前記ｐチャネル電界効果トランジスタの飽和電流が同じ大きさになるように、前記ｎチャネル電界効果トランジスタのチャネル幅Ｗn、及び前記ｐチャネル電界効果トランジスタのチャネル幅Ｗpの比Ｗn／Ｗp、または、前記ｎチャネル電界効果トランジスタのチャネル長Ｌn、及び前記ｐチャネル電界効果トランジスタのチャネル長Ｌpの比Ｌn／Ｌpが設定されている、ＳｉＣ相補型電界効果トランジスタ。 A SiC complementary field-effect transistor in which a normally-off type n-channel field-effect transistor and a p-channel field-effect transistor are formed on a SiC substrate.
The channel width Wn of the n-channel field-effect transistor and the p-channel field-effect transistor so that the saturation currents of the n-channel field-effect transistor and the p-channel field-effect transistor have the same magnitude at a temperature of 450 K or higher. The ratio Wn / Wp of the channel width Wp, or the ratio Ln / Lp of the channel length Ln of the n-channel field effect transistor and the channel length Lp of the p-channel field effect transistor is set. Transistor.
前記ｐチャネル電界効果トランジスタのチャネル領域にドープされたｐ型不純物がＡｌであって、
前記ｎチャネル電界効果トランジスタのチャネル領域にドープされたｎ型不純物のエネルギー準位が、伝導帯端から０．１３ｅＶ以上離れている、ＳｉＣ相補型電界効果トランジスタ。 A SiC complementary field-effect transistor in which a normally-off type n-channel field-effect transistor and a p-channel field-effect transistor are formed on a SiC substrate.
The p-type impurity doped in the channel region of the p-channel field effect transistor is Al.
A SiC complementary field effect transistor in which the energy level of the n-type impurity doped in the channel region of the n-channel field effect transistor is separated from the conduction band end by 0.13 eV or more.
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| JP2020104834A JP2021197517A (en) | 2020-06-17 | 2020-06-17 | SiC complementary field effect transistor |
| PCT/JP2021/020585 WO2021256230A1 (en) | 2020-06-17 | 2021-05-31 | SiC COMPLEMENTARY TYPE FIELD EFFECT TRANSISTOR |
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