JP2023155985A - SiC complementary field effect transistor - Google Patents

Abstract

To provide a SiC complementary field effect transistor that can operate stably over a wide temperature range.SOLUTION: In a SiC complementary field effect transistor in which a normally-off type n-channel field effect transistor 1a and a p-channel field effect transistor 1b are formed on a SiC substrate 10, the p-type impurity doped in the channel region of the p-channel field effect transistor is Al (aluminum) or B (boron), the first n-type impurity doped into the channel region 13 of the n-channel field effect transistor is S (sulfur), and a second n-type impurity having a shallower energy level than S (sulfur) is codoped into the first n-type impurity.SELECTED DRAWING: Figure 12

Description

The present invention relates to a SiC complementary field effect transistor formed using a silicon carbide (SiC) substrate.

Current semiconductor integrated circuits are mainly made of silicon (Si), but in the industrial field, they are used for applications such as automobile and aircraft engine control, automobile tire monitors, and space electronics, which are impossible to achieve with Si. There is a need for integrated circuits that operate at higher temperatures.

Since SiC has a bandgap about three times higher than that of Si, it is possible to fabricate an integrated circuit that operates in a high-temperature environment of 500° C. or higher.

As an integrated circuit manufactured using a SiC substrate, for example, Non-Patent Document 1 discloses an integrated circuit configured with complementary MOSFETs. Further, Patent Document 1 discloses a complementary JFET in which an n-channel JFET and a p-channel JFET are insulated and separated by a semi-insulating SiC layer.

Japanese Patent Application Publication No. 2011-166025

S.H. Ryu et al., IEEE Trans. Electron Devices, vol.45 (1998), p.45.

The complementary MOSFET disclosed in Non-Patent Document 1 has a high density of defects and charges at the interface between the SiC substrate and the gate oxide film, so the threshold voltage fluctuates greatly depending on the temperature and cannot operate stably. There is a problem. Another problem is that the gate oxide film deteriorates at high temperatures.

The complementary JFET disclosed in Patent Document 1 has a structure in which an n-channel JFET and a p-channel JFET are insulated and separated by an intrinsic SiC layer formed by a hot-wall CVD method, and the structure is such that a fine trench is formed and buried. There is a problem in that the manufacturing process becomes extremely complicated because growth and surface flattening polishing must be repeated.

Until now, several studies on complementary field effect transistors using SiC substrates have been reported, but high temperature operation has only been confirmed, and complementary field effect transistors that can operate stably over a wide temperature range are It has not been achieved.

The present invention was made in view of the above problems, and its main purpose is to provide a SiC complementary field effect transistor that can operate stably over a wide temperature range.

A SiC complementary field effect transistor according to the present invention is a SiC complementary field effect transistor in which a normally-off type n-channel field effect transistor and a p-channel field effect transistor are formed on a SiC substrate, the p-channel field effect transistor The p-type impurity doped into the channel region of the n-channel field effect transistor is Al (aluminum) or B (boron), and the first n-type impurity doped into the channel region of the n-channel field effect transistor is S (sulfur). , the first n-type impurity is codoped with a second n-type impurity having a shallower energy level than S (sulfur).

According to the present invention, it is possible to provide a SiC complementary field effect transistor that can operate stably over a wide temperature range.

(A) to (C) are diagrams showing the structure of the SiC JFET disclosed in the specification of the previous application. FIG. 2 is a circuit diagram showing an inverter circuit including complementary JFETs. 5 is a graph showing temperature characteristics of input/output characteristics of an inverter circuit. 3 is a graph showing the temperature dependence of carrier density. 3 is a graph showing the temperature dependence of carrier density. 5 is a graph showing temperature characteristics of input/output characteristics of an inverter circuit. (A) and (B) are diagrams showing the structure of an element for measuring the Hall effect. 3 is a graph showing the temperature dependence of carrier density. 7 is a graph showing the temperature dependence of the maximum operating frequency in an inverter circuit. 3 is a graph showing the temperature dependence of carrier density. FIG. 3 is a diagram showing an energy band structure when a channel region is codoped with S and N. 3 is a graph showing the temperature dependence of carrier density. 7 is a graph showing the temperature dependence of the maximum operating frequency in an inverter circuit. 7 is a graph showing the temperature dependence of the logic threshold voltage of an inverter circuit. It is a figure showing the formation process of an n-type codope layer. 3 is a graph showing the distribution of impurity density in the depth direction in an n-type codoped layer. 3 is a graph showing the temperature dependence of carrier density. 3 is a graph showing the temperature dependence of carrier density.

The applicant of the present application has disclosed the structure of a SiC junction field effect transistor (hereinafter referred to as "SiC JFET") that facilitates normally-off operation in the specification of the previous application (Japanese Patent Application Laid-Open No. 2019-091873).

1(A) to 1(C) are diagrams showing the structure of the SiC JFET disclosed in the specification, FIG. 1(A) is a plan view of the n-channel JFET, and FIG. 1(B) is the diagram of FIG. 1(A) is a cross-sectional view taken along line BB, and FIG. 1(C) is a cross-sectional view taken along line CC in FIG. 1(A).

As shown in FIGS. 1A to 1C, the n-channel JFET 1 has an n-type buried channel region 13 formed in a SiC substrate 10, and is formed facing each other with the buried channel region 13 in between. n ⁺ type source region 11 and drain region 12, and a pair of p ⁺ type gate regions 14a and 14b formed in a direction perpendicular to the direction in which the source region 11 and drain region 12 face each other. . A p-channel JFET also has a similar structure.

In the n-channel JFET 1, the width L of the pair of gate regions 14a and 14b is the channel length, the distance D between the pair of gate regions 14a and 14b is the channel thickness, and the distance W in the depth direction of the buried channel region 13 is the channel length. Channel width.

The spread of the depletion layer within the buried channel region 13 is controlled by a gate voltage applied to a pair of gate regions 14a and 14b formed on both sides of the buried channel region 13. By adjusting the impurity concentration N and channel thickness D of the buried channel region 13, a normally-off type SiC JFET can be realized. Specifically, the impurity concentration N (cm ⁻³ ) and channel thickness D (cm) of the buried channel region 13 are set to satisfy N(D/2) ² <3×10 ⁷ cm ⁻¹ . do it.

Note that in the n-channel JFET 1 shown in FIGS. 1A to 1C, the channel region is the buried channel region 13, but the channel region may extend to the surface of the SiC substrate 10.

FIG. 2 shows an inverter circuit composed of complementary JFETs including a normally-off type n-channel JFET 1a and a normally-off type p-channel JFET 1b. The gate electrodes of the n-channel JFET1a and the p-channel JFET1b are connected to the input terminal V _in of the inverter circuit. Drain electrodes D of the n-channel JFET 1a and the p-channel JFET 1b are connected to the output terminal V _out of the inverter circuit. The source electrode S of the n-channel JFET 1a is connected to the ground, and the source electrode S of the p-channel JFET 1b is connected to the power supply (V _DD ).

Typically, an inverter circuit is designed such that the logic threshold voltage V _th is 1/2 of the power supply voltage V _DD . In this case, the saturation currents I _Dn and I _Dp of the n-channel JFET 1a and the p-channel JFET 1b are equal. Here, I _Dn and I _Dp are expressed by the following formulas (1) and (2).

In the above equations (1) and (2), V _G is the gate voltage, V _Tn and V _Tp are the threshold voltages of n-channel JFET1a and p-channel JFET1b, and β _n and β _p are the gate voltages of n-channel JFET1a and p-channel JFET1b. It is the beta value (gain).

Since a voltage of V _in is applied to the gate electrode of the n-channel JFET 1a and a voltage of V _in -V _DD is applied to the gate electrode of the p-channel JFET 1b, using the above equations (1) and (2), I _Dn = I _Dp From this, the following equation (3) is obtained.

From the above equation (3), the logic threshold voltage V _th of the inverter circuit is expressed by the following equation (4).

Further, β _R is determined by the following equation (5) using the physical property values and structural dimensions of the JFET having the structure shown in FIGS. 1(A) to (C).

In the above formula (5), each parameter is as follows. Note that subscripts n and p indicate parameters of the n-channel JFET and the p-channel JFET.

μ _n , μ _p : Mobility of electrons and holes n _n , p _p : Electron density, hole density W _n , W _p : Channel width L _n , L _p : Channel length D _n , D _p : Channel thickness N _D , N _A : impurity density of channel region 13 FIG. 3 is a graph obtained by calculating the temperature characteristics of the input/output characteristics of the inverter circuit shown in FIG. 2 using the above equation (4). Here, the input/output characteristics of the inverter circuit were calculated using a well-known formula for current-voltage characteristics.

As shown in FIG. 3, the logic threshold voltage V _th shifts significantly from 1V as the temperature increases. The main reason for this is that the parameter β _R has a large temperature dependence in the above equation (4).

FIG. 4 is a graph obtained by calculating the temperature dependence of carrier density of electrons and holes in a SiC JFET. Here, the graph indicated by A indicates the electron density n _n and the graph indicated by B indicates the hole density p _p . The n-type impurity (donor) is P (phosphorus), and the p-type impurity (acceptor) is Al (aluminum). Note that n _n and p _p were calculated using the following equations (6) and (7).

In the above formulas (6) and (7), i represents two sites in 4H-SiC (i = h, k site), and each parameter in the formula is as follows.

g _i : degree of degeneracy of donor (acceptor) level
N _di , N _ai : Donor density, acceptor density N _c , N _v : Effective state density of conduction band, effective state of valence band
n _n , p _p : Electron density, hole density ΔE _i : Ionization energy As shown in Figure 4, the electron density n _n is almost constant over a wide temperature range, whereas the hole density p _p is constant at room temperature. It changes greatly from high to high temperatures. This is because the energy level of n-type impurities is shallow from the conduction band edge (ΔE _i : about 60 meV) and has a high ionization rate, whereas the energy level of p-type impurities is deep from the valence band edge (ΔE _i : about 200 meV), and the ionization rate is low. Therefore, only the hole density p _p has a large temperature change, and as shown in equation (5), the temperature change of β _R (∝n _n /p _p ) is dominated by the temperature change of the hole density p _p . Become.

The applicant of the present application has proposed a method for suppressing the temperature change in the logic threshold voltage V _th by using an impurity having a deep energy level similar to the p-type impurity as the n-type impurity in the specification of the previous application ( It is disclosed in JP 2021-197517).

Figure 5 is a calculated graph of the temperature dependence of electron and hole density when a virtual donor with a deep energy level is assumed as the n-type impurity and Al is used as the p-type impurity. be. Note that the energy level of the virtual donor is assumed to be approximately 260 meV from the conduction band edge. Here, the graph indicated by A indicates the hole density p _p and the graph indicated by B indicates the electron density n _n . As shown in FIG. 5, the electron density n _n and the hole density p _p change in almost the same way over a wide temperature range from room temperature to high temperature.

Figure 6 shows the temperature characteristics of the input/output characteristics of an inverter circuit when the above-mentioned virtual donor is used as an n-type impurity and Al is used as a p-type impurity, calculated using a well-known formula for current-voltage characteristics. This is a graph. As shown in FIG. 6, the logical threshold voltage V _th is approximately 1V over a wide temperature range.

In this way, by using an impurity having a deep energy level like the p-type impurity as the n-type impurity, fluctuations in the logic threshold voltage V _th can be significantly suppressed over a wide temperature range.

(Experimental search for n-type impurities with deep energy levels)
The energy levels of S (sulfur), As (arsenic), and Sb (antimony) as impurities other than N (nitrogen) and P (phosphorus), which have conventionally been used as n-type impurities, can be changed using the well-known hole method. It was determined by effect measurement.

7(A) and 7(B) are diagrams showing the structure of the Hall effect measuring element, with FIG. 7(A) being a plan view and FIG. 7(B) being a sectional view.

As shown in FIGS. 7A and 7B, after forming a p-type epitaxial layer 20 on an n-type 4H-SiC (0001) substrate 10, S, As, and Sb are added to the p-type epitaxial layer 20. The formed n-type doped layer 30 was patterned into a clover shape, and four electrodes 40 were formed at each of the four corners of the pattern.

FIG. 8 is a graph showing the temperature dependence of the carrier density of SiC doped with S, As, and Sb impurities, determined by Hall effect measurement.

As shown in FIG. 8, the carrier density of As and Sb had almost no temperature dependence, whereas the carrier density of S had a large temperature dependence. This demonstrated that As and Sb, like N and P, have shallow energy levels, whereas S has a deep energy level.

Next, the ionization energy of S was determined by fitting the measured data to a temperature-dependent equation of carrier density. Note that since S in group 16 has two energy levels for one site, the following equation (8) was used as the temperature dependence equation for carrier density.

Here, f _i,m is expressed by the following equation (9) considering two sites (i = h, k site) and two energy levels (m = 1, 2) in 4H-SiC. Ru.

Here, g' _i,m has the following values for the two energy levels.

Table 1 is a table showing the ionization energy (ΔE _di,m ) of S determined by fitting. Here, i=h and k each represent two sites of 4H-SiC. From Table 1, it was demonstrated that S has a deep energy level of 340 meV or more.

(Maximum operating frequency of inverter circuit)
As described above, by using S, which has a deep energy level, as the n-type impurity doped into the channel region of the n-channel JFET, temperature changes in the logical threshold voltage V _th in the inverter circuit shown in FIG. 2 are suppressed. However, the inventors of the present application have discovered a new problem in that the maximum operating frequency in the inverter circuit is significantly reduced near room temperature.

FIG. 9 is a graph obtained by calculating the temperature dependence of the maximum operating frequency f _max in the inverter circuit using the following equation (10). The graph marked A shows the temperature dependence when N with a shallow energy level is used as the n-type impurity doped into the channel region, and the graph marked B shows the temperature dependence when N is used as the n-type impurity doped into the channel region. The temperature dependence when S, which has a deep energy level, is used as an impurity is shown.

Here, t _r is the rise time, t _f is the fall time, and t _r and t _f are each calculated by the following equation (11).

Here, C is the load capacitance, and in the above calculation, it was assumed that C=550 fF.

As shown in FIG. 9, it can be seen that the maximum operating frequency f _max when S is used as the n-type impurity is significantly lower near room temperature than when N is used.

This is because, as shown in Figure 10, in N with a shallow energy level (low ionization energy), there is almost no change in carrier density with temperature, whereas in S with a deep energy level (high ionization energy), This is thought to be due to the large decrease in carrier density near room temperature.

That is, as shown in the above equation (5), the temperature change in β _n largely depends on the temperature change in the carrier density n, so as shown in the above equation (11), when S is used as the n-type impurity, It is considered that the fall time tf of t _f increases significantly near room temperature, and as a result, the maximum operating frequency f _max decreases significantly.

The inventors of the present application focused on the fact that when S, which has a deep energy level, is used as an n-type impurity, the carrier density near room temperature decreases significantly, and the inventors of the present application focused on using S as an n-type impurity with an energy level of The present invention was conceived based on the idea that by codoping a shallow n-type impurity, the decrease in the maximum operating frequency f _max near room temperature can be suppressed.

FIG. 11 shows S as a deep n-type impurity (first n-type impurity) at energy level E _d1 and shallow n-type impurity (second n-type impurity) at energy level E _d2 in the channel region. FIG. 3 is a diagram showing an energy band structure when N is codoped. Although the impurity density of N and the impurity density of S are not particularly limited, typically the impurity density of N is set lower than the impurity density of S.

As shown in FIG. 11, in the conduction band, there are carriers (electrons) due to ionized S ⁺ and carriers (electrons) due to ionized N ⁺ . Typically, near room temperature, carriers due to N ⁺ There are more (electrons). Therefore, the carrier density near room temperature is dominated by the carrier density due to N ⁺ .

FIG. 12 is a graph obtained by calculation of the temperature dependence of carrier density when the channel region is codoped with deep S at energy level E _d1 and shallow N at energy level E _d2 as n-type impurities. It is.

Here, the graph indicated by A ₁ shows the temperature dependence of the carrier density n 1 of S calculated using the above equation (8), and the graph indicated by A ₂ shows the temperature dependence of the carrier density n ₁ calculated using the above equation (6). The calculated temperature dependence of the carrier density n ₂ of N is shown, and the graph indicated by A shows the temperature dependence of the carrier density n (n=n ₁ +n ₂ ) when S and N are codoped. Further, the graph indicated by B shows the temperature dependence of the carrier density p when doping with Al (p-type impurity) calculated using the above equation (7).

In the above formulas (8), (6), and (7), the impurity concentration N _ds of S is 5.0×10 ¹⁶ cm ⁻³ , and the impurity concentration N _dN of N is 3.0× The impurity concentration N _dN was calculated as 5.0 ^{× 10 16} cm ⁻³ . Further, the compensation defect density, which will be described later, was assumed to be 0 cm ^-3 .

As shown in FIG. 12, near room temperature, the carrier density when S and N are codoped is higher than the carrier density when only S is doped, and the effective It can be said that the ionization energy is decreasing.

FIG. 13 is a graph obtained by calculating the temperature dependence of the maximum operating frequency when the channel region is co-doped with S having a deep energy level and N having a shallow energy level as n-type impurities. Here, the graph shown by A shows the temperature dependence when only S is doped, and the graph shown by B shows the temperature dependence when S and N are co-doped.

As shown in FIG. 13, by codoping N, which has a shallower energy level than S, into a channel region doped with S, which has a deeper energy level, the maximum operating frequency near room temperature can be increased. This makes it possible to realize a circuit that can operate stably and at high speed over a wide temperature range.

Note that the impurity density of codoping N may be set so that the carrier density supplied by ionized N is higher than the carrier density supplied by ionized S at room temperature.

FIG. 14 is a graph obtained by calculating the temperature dependence of the logic threshold voltage V _th when the channel region is co-doped with S with a deep energy level and N with a shallow energy level as n-type impurities. be. Here, the graph shown by A shows the temperature dependence when only S is doped, and the graph shown by B shows the temperature dependence when S and N are co-doped.

As shown in FIG. 14, by codoping N, which has a shallower energy level than S, into the channel region doped with S, which has a deep energy level, fluctuations in the logical threshold voltage V _th are further suppressed over a wide temperature range. can do.

(Actual measurement of carrier density when codoping S and N)
As shown in FIG. 15, S and N are ion-implanted into the p-type epitaxial layer 20 formed on the surface of the n-type 4H-SiC (0001) substrate 10. An n-type codoped layer 30 was formed. Here, the impurity concentration of the p-type epitaxial layer 20 is 5×10 ¹⁴ cm ⁻³ , the implantation dose of S is 3.51×10 ¹² cm ⁻² , and the implantation dose of N is 3.52 ×10 ¹¹ cm ^-2 . Further, the ion implantation energy of S was 10 to 350 keV, and the ion implantation energy of N was 10 to 200 keV.

FIG. 16 is a graph showing the results of measuring the distribution of S and N impurity densities in the depth direction in the n-type codoped layer 30 using secondary ion mass spectrometry (SIMS). The graph labeled A shows the distribution of S impurity density in the depth direction, and the graph labeled B shows the distribution of N impurity density in the depth direction. As shown in FIG. 16, the S impurity density in the n-type codoped layer 30 was 1.0×10 ¹⁷ cm ⁻³ and the N impurity density was 1.0×10 ¹⁶ cm ⁻³ .

FIG. 17 is a graph showing the results of measuring the temperature dependence of the carrier density in the n-type co-doped layer 30 by manufacturing the Hall effect measuring element shown in FIGS. 7(A) and 7(B). Here, the graph shown by A shows the temperature dependence when only S is doped, and the graph shown by B shows the temperature dependence when S and N are co-doped. As shown in FIG. 17, it was demonstrated that the carrier density of the codoped layer 30 codoped with S and N increases near room temperature.

(Compensated defect density dependence of carrier density)
When forming a SiC complementary field effect transistor on a SiC substrate, in order to avoid the effects of recombination on the SiC substrate, a p-type epitaxial layer is formed on the SiC substrate, and a SiC complementary field effect transistor is formed on the p-type epitaxial layer. A transistor may be formed. In this case, the channel region of the n-channel JFET is formed by ion-implanting n-type impurities into the p-type epitaxial layer.

In this case, since the p-type impurity doped in the p-type epitaxial layer exists in the channel region, this p-type impurity becomes a level (compensation defect) that captures carriers (electrons) in the channel region. The carrier density (electron density) in the region decreases.

In FIG. 18, the impurity density of S and N codoped into the channel region is set to 5.0×10 ¹⁶ cm ⁻³ and 3.0×10 ¹⁵ cm ⁻³ , respectively, and the p-type impurity present in the channel region is This is a graph obtained by calculating the temperature dependence of carrier density when the density (compensated defect density) is changed in the range of 0 to 1×10 ¹⁶ cm ⁻³ . Here, the graphs indicated by A ₀ to A ₄ have compensated defect densities of 0, 1×10 ¹⁵ cm ⁻³ , 3×10 ¹⁵ cm ⁻³ , 5×10 ¹⁶ cm ⁻³ , and 1×10 ¹⁶ cm ^-3 case is shown.

As shown in FIG. 18, as the compensation defect density increases, the carrier density near room temperature in the channel region decreases. Therefore, the density of the N impurity codoped into the channel region must be determined in consideration of the compensation defect density existing in the channel region.

Note that although the above example illustrates the case where a SiC complementary field effect transistor is formed on a p-type epitaxial layer, the same applies when forming a SiC complementary field-effect transistor on an n-type epitaxial layer or a semi-insulating substrate. It is necessary to determine the impurity density of N co-doped into the channel region, taking into consideration the compensation defect density present in the channel region.

Although the present invention has been described above with reference to preferred embodiments, such description is not a limitation and, of course, various modifications are possible.

For example, in the above embodiment, an n-type impurity with a shallower energy level than S (second n-type impurity) is added to the channel region doped with S (sulfur) as an n-type impurity with a deep energy level (first n-type impurity). Although an example has been described in which N (nitrogen) is co-doped as an n-type impurity), the present invention is not limited to this, and for example, P (phosphorus), As (arsenic), Sb (antimony), etc. may be co-doped. . Further, at least one type of n-type impurity selected from N, P, As, and Sb may be codoped.

In the present invention, the co-doped n-type impurity is intentionally doped at a controlled and appropriate dose, and does not include n-type impurities that inevitably exist in SiC substrates and the like.

Further, in the above embodiment, Al (aluminum) is used as an example of the p-type impurity, but the effects of the present invention can be similarly achieved even if B (boron), which has a deep energy level, is used.

Further, in the above embodiment, an example in which the SiC complementary JFET is applied to an inverter circuit has been described, but the invention can also be applied to other logic gates, such as a NAND circuit or a NOR circuit. In addition to digital circuits based on the above logic gates, the present invention can also be applied to analog circuits.

Further, in the above embodiment, the SiC complementary field effect transistor is described using a SiC complementary JFET as an example, but the present invention can also be applied to a SiC complementary MOSFET.

Further, in the above embodiment, the SiC JFET having the structure shown in FIG. 1 is used as an example of the transistor constituting the SiC complementary field effect transistor, but it is of course applicable to SiC JFET or SiC MOSFET having other structures. I can do it.

1 JFET
1a n-channel JFET
1b p-channel JFET
10 SiC substrate
11 Source area
12 Drain region
13 Buried channel area
14a, 14b gate region

Claims (5)

A SiC complementary field effect transistor in which a normally-off type n-channel field effect transistor and a p-channel field effect transistor are formed on a SiC substrate,
The p-type impurity doped into the channel region of the p-channel field effect transistor is Al (aluminum) or B (boron),
The first n-type impurity doped into the channel region of the n-channel field effect transistor is S (sulfur),
A SiC complementary field effect transistor, wherein the first n-type impurity is codoped with a second n-type impurity having a shallower energy level than S (sulfur). The SiC complementary type according to claim 1, wherein the second n-type impurity includes at least one impurity selected from N (nitrogen), P (phosphorus), As (arsenic), and Sb (antimony). Field effect transistor. The impurity density of the second n-type impurity is set such that the carrier density due to the second n-type impurity is higher than the carrier density due to the first n-type impurity at room temperature. 3. The SiC complementary field effect transistor according to 1 or 2. 4. The SiC complementary field effect transistor according to claim 3, wherein the impurity density of the second n-type impurity is lower than the impurity density of the first n-type impurity. The SiC complementary field effect transistor according to claim 1, wherein the n-channel field effect transistor and the p-channel field effect transistor are respectively configured of an n-channel junction field effect transistor and a p-channel junction field effect transistor. effect transistor.