JP2021180448A - Master-slave communication system, electronic device, and control method for them - Google Patents

Abstract

To determine the operation state of a plurality of slave nodes in a short time.SOLUTION: A master CPU 100 changes, from an initial address, the slave address of each of a plurality of slave nodes to an intrinsic address different from the initial address, then uses the initial address to try communication with each of the plurality of slave nodes. The master CPU 100 determines the operation state of each slave node on the basis of the result of the try.SELECTED DRAWING: Figure 7

Description

The present invention relates to a master-slave communication system, an electronic device, and a control method thereof.

A master-slave communication system in which a master node as an electronic device communicates with a plurality of slave nodes is known. Generally, for communication between a master node and a slave node, a method is adopted in which an address (slave address) assigned to the slave node is specified and communication between an arbitrary slave node and the master node is established. .. In I2C communication, which is one of the master-slave communication systems, a communication method as shown in FIG. 10 is adopted.

First, the master node transmits a start condition (S) signal, a slave address signal to be connected, and an R / W signal indicating whether the master side is read or write. When the slave node receives the signal, an ACK is returned from the slave node. After that, when the master side becomes a write, a data signal is transmitted from the master node, and when the slave node receives the signal, an ACK is returned from the slave node. On the other hand, when the master side becomes the read, a data signal is transmitted from the slave node, and when the master node receives the signal, ACK is returned from the master node. Finally, the stop condition signal (P) is transmitted from the master node, and the communication with the slave node ends.

If the side receiving the signal does not receive the signal correctly, ACK is not returned and the state becomes NCK. In this master-slave communication system, it is necessary to assign a unique address to each of a plurality of slave nodes. As a method thereof, as described in Patent Document 1, there is known a method of enabling communication to each slave node by setting a slave address unique to each slave node from the master node.

Japanese Unexamined Patent Publication No. 5-292098

However, in order to determine the operating state of whether each slave node is operating normally, the master node specifies the slave address of each slave node and communicates, and confirms whether communication is established. There is a need to. For example, as shown in FIG. 9, it is necessary to confirm the establishment of communication with each of the slave nodes A, B, and C one by one, that is, to confirm that ACK is returned from each of the slave nodes. If the number of slave nodes is large, it will take a long time to confirm. If it takes a long time to determine the operating status of a plurality of slave nodes, smooth control of the entire device equipped with the master-slave communication system may not be possible.

An object of the present invention is to determine the operating state of a plurality of slave nodes in a short time.

In order to achieve the above object, the present invention is a master-slave communication system including a master node and a plurality of slave nodes holding an initial address which is a non-unique address, and the address of each of the plurality of slave nodes is used. A changing means for changing from the initial address to a unique address of each slave node different from the initial address, and after the address is changed by the changing means, an attempt is made to communicate with each slave node using the initial address. It is characterized by having a trial means and a discriminating means for discriminating the operating state of each slave node based on the trial result by the trial means.

According to the present invention, it is possible to determine the operating state of a plurality of slave nodes in a short time.

It is a block diagram which shows schematic structure of a master-slave communication system. It is a block diagram which shows schematic structure of slave node A. It is a timing chart of I2C communication. It is a flowchart which shows the slave address setting process. It is a continuation flowchart of FIG. 4 which shows the slave address setting process. It is a figure explaining the change of a slave address. It is a flowchart which shows the state determination process. It is explanatory drawing of the I2C communication system. It is explanatory drawing of the conventional I2C communication system. It is explanatory drawing of the conventional I2C communication system.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram schematically showing a configuration of a master-slave communication system according to an embodiment of the present invention. In FIG. 1, the master-slave communication system 1000 (hereinafter, communication system 1000) includes a master CPU 100 and a plurality of slave nodes. In the present embodiment, as an example, a configuration in which the communication system 1000 includes three slave nodes, specifically, a slave node A111, a slave node B112, and a slave node C113 will be described. The number of slave nodes included in the communication system 1000 is not limited to three, and may be two or four or more. For example, if the data length of the address of the slave node is 8 bits, the maximum number of slave nodes 2 8 ^-1, i.e., a 255.

The master CPU 100 as an electronic device includes one or more master nodes and a master ROM 104. In the present embodiment, as an example, a configuration in which the communication system 1000 includes one master node, specifically, a master node 101 will be described.

The master node 101 includes a data output terminal (SDA) and a clock output terminal (CLKout). The data output terminal is connected to the serial data bus 102, and the clock output terminal is connected to the clock signal line 103. A slave node A111, a slave node B112, and a slave node C113 are connected in parallel to the serial data bus 102 and the clock signal line 103, respectively. In this way, in the communication system 1000, a plurality of slave nodes are connected so as to hang from one master node.

In the communication system 1000, for example, I2C communication is used as the communication method. In I2C communication, the master node 101 outputs a clock signal for serial communication from the clock output terminal to the clock signal line 103. The serial data is determined by the logic of the serial data bus 102 at the rising edge of the clock signal. That is, among the slave node A111, the slave node B112, and the slave node C113, the slave node designated by the master node 101 reads the data signal of the serial data bus 102 at the rising edge of the clock signal. Hereinafter, the communication performed by the master node 101 with each slave node via the serial data bus 102 and the clock signal line 103 is referred to as "master-slave communication".

The master CPU 100 supplies power to the slave node A111, the slave node B112, and the slave node C113. In FIG. 1, the master CPU 100 supplies power from the power supply line 121 to the slave node A111, supplies power from the power supply line 122 to the slave node B112, and supplies power from the power supply line 123 to the slave node C113. In the following, the power supplied from the power supply line 121 to the slave node A111 is referred to as "Vcc-A". The electric power supplied from the power supply line 122 to the slave node B112 is defined as "Vcc-B". The electric power supplied from the power supply line 123 to the slave node C113 is defined as "Vcc-C". The master CPU 100 can individually perform on / off control of power supply for each power supply line 121 to 123. The master ROM 104 stores a plurality of change addresses. Each changed address is used in the slave address setting process (FIGS. 4 and 5) described later, which sets the address of each slave node used in the master-slave communication. The change address is a unique address (unique address) corresponding to each slave node, and the change address of each slave node is a different address from each other.

In I2C communication, the slave node A111, the slave node B112, and the slave node C113 each have a unique slave address used for communication in the communication system 1000. The master node 101 selects any of the slave node A111, the slave node B112, and the slave node C113 as the communication target by designating the slave address possessed by the slave node to be communicated. The master node 101 communicates with the selected slave node.

In I2C communication, the serial data bus 102 and the clock signal line 103 are pulled up to the power supply Vdd via a resistor. The voltage of this power supply Vdd is equivalent to the voltage (Vcc) supplied to the master node 101 and the slave node. Since a plurality of slave nodes are connected to the serial data bus 102 and the clock signal line 103, the terminals connected to the serial data bus 102 and the clock signal line 103 of each node have an open drain configuration. The terminals of each slave node are always in the input mode and are in a high impedance state.

In the present embodiment, the slave node A111, the slave node B112, and the slave node C113 have the same configuration as each other. Therefore, the configuration of the slave node A111 will be described below as a representative. In the following, for the component of the slave node B112, "A" at the end of the code of the component of the slave node A111 is read as "B". Further, regarding the component of the slave node C113, "A" at the end of the code of the component of the slave node A111 is read as "C".

FIG. 2 is a block diagram schematically showing the configuration of the slave node A111. In FIG. 2, the slave node A111 includes a serial / parallel conversion unit 201A, a reception address register 202A, an internal address register 203A, a slave CPU 204A, and a slave ROM 205A. The serial / parallel conversion unit 201A, the reception address register 202A, and the slave CPU 204A are connected to each other via the internal bus 206A. The slave ROM 205A and the internal address register 203A are connected to the slave CPU 204A.

The serial / parallel conversion unit 201A is connected to the serial data bus 102 and the clock signal line 103. The serial / parallel conversion unit 201A takes in the data signal output from the master node 101 at the timing of the rising edge of the clock signal output from the master node 101. The serial / parallel conversion unit 201A converts the serial data based on the captured data signal into parallel data and outputs the serial data to the internal bus 206A. Further, the serial / parallel conversion unit 201A converts the parallel data received via the internal bus 206A into serial data, and outputs the data signal of the serial data to the serial data bus 102.

The reception address register 202A holds the change address included in the serial information received from the master node 101. The slave CPU 204A is an arithmetic unit that controls the overall operation of the slave node A111. The slave ROM 205A stores various information necessary for control by the slave CPU 204A. The various information includes, for example, the initial address of the slave node A111. The initial address is used to establish initial communication with the master node 101. The initial address is common to each slave node, but is different from any changed address.

Power (Vcc-A) is supplied to the slave node A111 from the master CPU 100 via the power supply line 121. If power is not supplied from the master CPU 100 (Vcc off), each block in the slave node A111 such as the slave CPU 204A and the serial / parallel conversion unit 201A does not operate in the slave node A111. Therefore, the slave node A111 is disconnected from the serial data bus 102 and the clock signal line 103, and cannot communicate with the master node 101. In this state, the slave node A111 is substantially not connected to the master node 101.

When power is supplied from the master CPU 100 (Vcc on), the slave CPU 204A is activated and the initial slave address stored in the slave ROM 205A is transferred to the internal address register 203A. Further, each block in the slave node A111 such as the serial / parallel conversion unit 201A can operate. Therefore, the slave node A111 is in a state of being connected to the serial data bus 102 and the clock signal line 103, and is in a state of being able to communicate with the master node 101. In this state, the slave node A111 is substantially connected to the master node 101.

FIGS. 3 (a) and 3 (b) show the communication timing in the I2C communication method. FIG. 3A is a timing chart of I2C communication. Here, a case where communication is performed with 8 bits as one set will be described. First, the master node 101 outputs a start condition (S) signal. The start condition is a state in which the master node 101 sets the serial data logic on the serial data bus 102 to Low when the clock signal logic on the clock signal line 103 is High. Outputting the start condition (S) signal signals the start of I2C communication.

Subsequently, the master node 101 outputs 8-bit data to the serial data bus 102 in synchronization with the output of the clock signal to the clock signal line 103. The slave node determines the serial data by the serial data logic of the serial data bus 102 at the rising edge of the clock signal. After that, when it is confirmed that the necessary data has been received, the slave node outputs ACK on the serial data bus 102. Here, outputting ACK means setting the signal level of the serial data bus 102 to Low. The serial data bus 102 is in the ACK state.

On the other hand, if it cannot be confirmed that the required data has been received, the slave node has no control over the serial data bus 102. Therefore, the serial data bus 102 is in the NCK state. As shown in FIG. 1, since the serial data bus 102 is pulled up via a resistor, the signal level of the serial data bus 102 becomes High if nothing is controlled for the serial data bus 102. That is, the serial data bus 102 is in the NCK state.

FIG. 3B is a communication timing chart when I2C communication is performed by designating a slave address from the master side. First, the master node 101 outputs a start condition (S) signal. The master node 101 outputs the slave address value to the serial data bus 102 by 7 bits from the high-order bits in synchronization with the output of the clock signal to the clock signal line 103 (A6 to A0). Subsequently, the master node 101 outputs an R / W signal for instructing whether the master side will transmit or receive in the subsequent communication. When the master side is transmitting, the R / W signal is Low, and when the master side is receiving, the R / W signal is High.

The slave node outputs ACK if the slave address received from the serial data bus 102 matches its own slave address. For example, the slave node A111 stores the address information of the parallel data converted via the serial / parallel conversion unit 201A shown in FIG. 2 in the reception address register 202A. Then, the slave node A111 outputs ACK when the address information stored in the reception address register 202A and the address information stored in the internal address register 203A match. Therefore, the serial data bus 102 is in the ACK state.

On the other hand, if the slave address data received from the serial data bus 102 does not match the address information stored in the internal address register 203A, the slave node A111 does not control the serial data bus 102. Therefore, the serial data bus 102 is in the NCK state. Since the operation of data transmission after this is the same as that of the slave address transmission described above, the description thereof is omitted.

4 and 5 are flowcharts showing the slave address setting process executed by the communication system 1000. This process is realized by the collaboration between the master CPU 100 and each slave CPU. Therefore, the master CPU 100 expands and executes the program stored in the master ROM 104 in the RAM provided in the master CPU 100. In addition to this, each slave CPU expands the program stored in each slave ROM into the RAM provided in each slave node and executes it. In this process, the master CPU 100 serves as a changing means in the present invention.

This process is started, for example, when an instruction to start communication is input to the master CPU 100. In the initial state of this processing, it is assumed that the power supply from the master CPU 100 to all the slave nodes is stopped. That is, the slave node A111, the slave node B112, and the slave node C113 are not connected to the master node 101.

In step S301, the communication system 1000 supplies electric power (Vcc-A) from the master CPU 100 to one of the slave node A111, the slave node B112, and the slave node C113, for example, the slave node A111.

In step S302, the communication system 1000 performs initial setting of the slave node A111 to which power is supplied. Specifically, in the slave node A111, the slave CPU 204A transfers the initial address stored in the slave ROM 205A to the internal address register 203A. As a result, the initial address is set as the slave address of the slave node A111. The initial address is, for example, a value represented by a binary number. In the present embodiment, as an example, the initial address is set to "0000100".

In step S303, the communication system 1000 specifies the slave address "0000100" of the slave node A111 by the master node 101, and starts the master-slave communication of the master node 101 and the slave node A111. Therefore, the master node 101 outputs a data signal indicating the address “0000100” of the slave node A111 to the serial data bus 102. In the slave node A111, when the serial / parallel conversion unit 201A receives the data signal, the address indicated by the data signal (hereinafter referred to as "designated address") is stored in the reception address register 202A.

In step S304, the communication system 1000 executes a process for establishing master-slave communication between the master node 101 and the slave node A111. Therefore, in the slave node A111, the slave CPU 204A compares the designated address stored in the receive address register 202A with the address held in the internal address register 203A. Here, the address held in the internal address register 203A is the initial address "0000100" set as the slave address of the slave node A111. Then, as a result of comparing these two addresses, if the two addresses match, the communication system 1000 establishes master-slave communication between the master node 101 and the slave node A111.

In step S305, the communication system 1000 changes the slave address of the slave node A111. Specifically, the master node 101 transmits the first change address stored in the master ROM 104 to the slave node A111 via the serial data bus 102. Here, the first changed address is an address different from the initial address, and is an address unique to the slave node A111 in the master-slave communication, for example, "0000101". The slave node A111 transfers the received first change address to the internal address register 203A. As a result, the slave address of the slave node A111 is switched from the initial address "0000100" to the changed address "0000101" as shown in FIG.

In step S306, the communication system 1000 specifies the first change address "0000101" and executes a process of starting master-slave communication of the master node 101 and the slave node A111.

In step S307, the communication system 1000 determines whether or not master-slave communication between the master node 101 and the slave node A111 has been established. If the slave address of the slave node A111 is normally switched from the initial address "0000100" to the first change address "0000101", communication is established.

As a result of the determination in step S307, when the master-slave communication of the master node 101 and the slave node A111 is not established, the slave address of the slave node A111 is not normally switched from the initial address to the first changed address. In this case, the master CPU 100 returns to the process of step S303. On the other hand, when the master-slave communication of the master node 101 and the slave node A111 is established, the slave address of the slave node A111 is normally switched from the initial address to the first changed address. In this case, the communication system 1000 advances the process to step S308.

In step S308, the communication system 1000 starts setting the address of a slave node other than the slave node A111, for example, the slave node B112. Specifically, the communication system 1000 supplies electric power (Vcc-B) from the master CPU 100 to the slave node B112. At this time, power continues to be supplied to the slave node A111, and the setting of the slave address "000101" of the slave node A111 is maintained.

In step S309, the communication system 1000 performs the initial setting of the slave node B112 to which the power is supplied. Specifically, similarly to step S302, in the slave node B112, the slave CPU sets the initial address stored in the slave ROM as the slave address of the slave node B112. Here, the initial address stored in the slave ROM of the slave node B112 is the same address "0000100" as the initial address stored in the slave ROM 205A of the slave node A111.

In step S310, the communication system 1000 specifies the slave address “0000100” of the slave node B112 by the master node 101, and starts the master-slave communication of the master node 101 and the slave node B112. Therefore, the master node 101 outputs a data signal indicating the address “0000100” of the slave node B112 to the serial data bus 102. In the slave node B112, the designated address indicated by the received data signal is stored in the received address register.

In step S311, a process for establishing master-slave communication between the master node 101 and the slave node B112 is executed. Therefore, in the slave node B112, the slave CPU compares the designated address stored in the receive address register with the address (initial address) stored in the internal address register. Then, as a result of comparing these two addresses, if the two addresses match, the communication system 1000 establishes master-slave communication between the master node 101 and the slave node B112.

In step S312, the communication system 1000 changes the slave address of the slave node B112. Specifically, the master node 101 transmits the second change address stored in the master ROM 104 to the slave node B 112 via the serial data bus 102. Here, the second change address is an address different from both the initial address and the first change address, and is an address unique to the slave node B112 in the master-slave communication system, for example, "0000110". The slave node B112 transfers the received second change address to the internal address register. As a result, the slave address of the slave node B112 is switched from the initial address "0000100" to the second change address "0000110" as shown in FIG.

In step S313, the communication system 1000 specifies the second change address "0000110" and executes a process of starting master-slave communication of the master node 101 and the slave node B112.

In step S314, the communication system 1000 determines whether or not master-slave communication between the master node 101 and the slave node B112 has been established. If the slave address of the slave node B112 is normally switched from the initial address "0000100" to the second change address "0000110", communication is established.

As a result of the determination in step S314, when the master-slave communication of the master node 101 and the slave node B112 is not established, the address of the slave node B112 is not normally switched from the initial address to the second changed address. In this case, the communication system 1000 returns to the process of step S310. On the other hand, when the master-slave communication of the master node 101 and the slave node B112 is established, the address of the slave node B112 is normally switched from the initial address to the second changed address. In this case, the communication system 1000 proceeds to step S315.

In step S315, the communication system 1000 starts setting the address of the slave node C113 which is a slave node other than the slave node A111 and the slave node B112. Specifically, the communication system 1000 supplies electric power (Vcc-C) from the master CPU 100 to the slave node C 113. At this time, power continues to be supplied to the slave node A111 and the slave node B112, and the setting of the address "0000101" of the slave node A111 and the setting of the address "0000110" of the slave node B112 are maintained.

In step S316, the communication system 1000 performs the initial setting of the slave node C113 to which the power is supplied. Specifically, as in step S309, in the slave node C113, the slave CPU sets the initial address stored in the slave ROM as the slave address of the slave node C113. Here, the initial address stored in the slave ROM of the slave node C113 is the same address "0000100" as the initial address stored in the slave ROM 205A of the slave node A111.

In step S317, the communication system 1000 specifies the slave address “0000100” of the slave node C113 by the master node 101, and starts the master-slave communication of the master node 101 and the slave node C113. Therefore, the master node 101 outputs a data signal indicating the address “0000100” of the slave node C113 to the serial data bus 102. In the slave node C113, the designated address indicated by the received data signal is stored in the received address register.

In step S318, a process for establishing master-slave communication between the master node 101 and the slave node C113 is executed. Therefore, in the slave node C113, the slave CPU compares the designated address stored in the receive address register with the address (initial address) stored in the internal address register. Then, as a result of comparing these two addresses, if the two addresses match, the communication system 1000 establishes master-slave communication between the master node 101 and the slave node C113.

In step S319, the communication system 1000 changes the slave address of the slave node C113. Specifically, the master node 101 transmits the third change address stored in the master ROM 104 to the slave node C 113 via the serial data bus 102. Here, the third change address is an address different from any of the initial address and the first and second change addresses, and is an address unique to the slave node C113 in the master-slave communication system, for example, "0000111". .. The slave node C113 transfers the received third change address to the internal address register. As a result, the slave address of the slave node C113 is switched from the initial address "0000100" to the third change address "0000111" as shown in FIG.

In step S320, the communication system 1000 specifies a third change address "0000111" and executes a process of starting master-slave communication of the master node 101 and the slave node C113.

In step S321, the communication system 1000 determines whether or not master-slave communication between the master node 101 and the slave node C113 has been established. If the slave address of the slave node C113 is normally switched from the initial address "0000100" to the third change address "0000111", communication is established.

As a result of the determination in step S321, when the master-slave communication of the master node 101 and the slave node C113 is not established, the address of the slave node C113 is not normally switched from the initial address to the third changed address. In this case, the communication system 1000 returns to the process of step S317. On the other hand, when the master-slave communication of the master node 101 and the slave node C113 is established, the address of the slave node C113 is normally switched from the initial address to the third changed address. In this case, the communication system 1000 ends the process shown in FIGS. 4 and 5.

FIG. 7 is a flowchart showing the state determination process. This process is realized by the master CPU 100 expanding the program stored in the master ROM 104 into the RAM provided in the master CPU 100 and executing the program. This process is executed after the slave address setting process (FIGS. 4 and 5) is executed, that is, after the slave address of each slave node is changed to an address unique to each slave node. This process is started immediately after the execution of the slave address setting process or before attempting to transmit / receive data. It should be noted that this process may be started when an instruction for determining the state is input. In this process, the master CPU 100 serves as a trial means and a discrimination means in the present invention.

By the way, each slave node is reset to the initial state when the power is not supplied or when it is affected by external noise, and is also reset when the power is momentarily interrupted for some reason. Also, when each slave node is reset, its slave address (stored in the internal address register) returns from its unique address to its initial address. The slave address is maintained at the initial address in the reset state of the slave node. Normally, after the slave address setting process (FIGS. 4 and 5) is executed, the slave address is changed from the initial address to the unique address in all the slave nodes. However, if the slave address is not changed properly or if there are circumstances such as the above-mentioned reset, the slave address may have returned to the initial address.

On the other hand, it takes a long time to confirm the establishment of communication with each of the slave nodes one by one. Therefore, in the present embodiment, the master CPU 100 checks for the existence of an abnormal slave node by attempting communication using the initial address.

First, in step S701, the master CPU 100 supplies power to all the slave nodes that try to communicate, and tries to communicate with all the slave nodes at the initial address. That is, as shown in FIG. 8, the master CPU 100 transmits the initial address to the serial data bus 102. As a result, the initial address is transmitted to substantially all the slave nodes (here, slave nodes A111, B112, C113) all at once. In each slave node, the initial address is stored in the receive address register.

In step S702, the master CPU 100 determines whether or not the serial data bus 102 is in the ACK state. Here, each slave CPU outputs ACK to the serial data bus 102 if both the initial address stored in the receive address register and the slave address (address held in the internal address register) match. If each slave node is operating normally, the slave address is a unique address, so ACK is output. However, the slave CPU of the slave node whose two do not match outputs NCK to the serial data bus 102. Therefore, if there is at least one slave node whose slave address is the initial address, the serial data bus 102 is in the ACK state. However, when the slave address is a unique address in all the slave nodes, the serial data bus 102 is in the NCK state.

If the serial data bus 102 is not in the ACK state as a result of the determination in step S702, the master CPU 100 advances the process to step S703. Therefore, when the serial data bus 102 is in the NCK state, the master CPU 100 advances the process to step S703. The fact that the serial data bus 102 is not in the ACK state corresponds to the case where the trial result indicates "communication failure". This means that none of the slave nodes output ACK. Therefore, in step S703, the master CPU 100 determines that the operating states of all the slave nodes are normal. After that, the master CPU 100 ends the process shown in FIG. 7.

On the other hand, if the serial data bus 102 is in the ACK state as a result of the determination in step S702, the master CPU 100 advances the process to step S704. The fact that the serial data bus 102 is in the ACK state corresponds to the case where the trial result indicates "establishment of communication". This means that there was at least one slave node that output an ACK. Therefore, in step S704, the master CPU 100 determines that the operating state of at least one slave node is not normal. In other words, the master CPU 100 determines that at least one of the slave nodes has been reset to the initial state.

In step S705, the master CPU 100 stops the power supply (power off) to all the slave nodes that have tried to communicate. After that, in step S706, the same process as the slave address setting process shown in FIGS. 4 and 5 is executed again. As a result, the master CPU 100 causes the internal address registers of the slave nodes to hold their own unique addresses. After that, the master CPU 100 returns the process to step S701. If the process of returning to step S701 is repeated a predetermined number of times but the process does not proceed to step S703, an error may be notified and the process shown in FIG. 7 may be terminated.

In this way, the master CPU 100 can determine whether at least one slave node is abnormal or all slave nodes are normal by checking whether the serial data bus 102 is in the ACK state.

According to the present embodiment, the master CPU 100 tries to communicate with each slave node by using the initial address after changing the slave address of the slave node from the initial address to the unique address. Then, based on the trial result, the operating state of each slave node is determined. That is, it is possible to determine whether at least one slave node is abnormal or all slave nodes are normal depending on whether or not the state of the serial data bus 102 connected to each slave node is ACK. Therefore, it is possible to determine the operating state of a plurality of slave nodes in a short time.

Although the present invention has been described in detail based on the preferred embodiments thereof, the present invention is not limited to these specific embodiments, and various embodiments within the range not deviating from the gist of the present invention are also included in the present invention. included.

100 master CPU
101 Master node 111 Slave node A
112 Slave node B
113 Slave node C
1000 master-slave communication system

Claims (23)

A master-slave communication system that includes a master node and a plurality of slave nodes that hold an initial address that is a non-unique address.
A changing means for changing the address of each of the plurality of slave nodes from the initial address to a unique address of each slave node different from the initial address.
After the address is changed by the changing means, the trial means for trying to communicate with each of the slave nodes using the initial address, and the trial means.
A master-slave communication system comprising: a discriminating means for discriminating the operating state of each slave node based on a trial result by the trial means. The master-slave communication system according to claim 1, wherein the discriminating means determines that the operating state of each slave node is normal when the trial result indicates that communication is not established. The master-slave according to claim 1 or 2, wherein the discriminating means determines that the operating state of at least one of the slave nodes is not normal when the trial result indicates that the communication is established. Communications system. The master according to claim 3, wherein the discriminating means determines that at least one of the slave nodes has been reset to the initial state when the trial result indicates that communication has been established. Slave communication system. The master node and the plurality of slave nodes are communicated using the I2C communication method, and the master node and the plurality of slave nodes are communicated with each other.
One of claims 1 to 4, wherein the determination means determines that the trial result indicates the establishment of communication when the state of the serial data bus connected to each slave node is ACK. The master-slave communication system according to item 1. The master-slave according to claim 5, wherein the discriminating means determines that the trial result indicates a communication failure when the state of the serial data bus connected to each slave node is NCK. Communications system. The master-slave communication system according to any one of claims 1 to 6, wherein the unique address is different between the slave nodes. One of claims 1 to 7, wherein the trial means attempts to communicate with each of the slave nodes by using the initial address while supplying power to all the slave nodes that attempt to communicate. The master-slave communication system described in the section. When the trial result indicates that the communication is established, the trial means uses the initial address in a state where the power supply to the slave nodes is stopped and then the power is supplied to the slave nodes again. The master-slave communication system according to claim 8, wherein communication with each of the slave nodes is attempted. The master-slave communication system according to any one of claims 1 to 9, wherein the address of each slave node is maintained at the initial address in the reset state of each slave node. An electronic device that communicates with multiple slave nodes that hold an initial address that is a non-unique address.
A changing means for changing the address of each of the plurality of slave nodes from the initial address to a unique address of each slave node different from the initial address.
After the address is changed by the changing means, the trial means for trying to communicate with each of the slave nodes using the initial address, and the trial means.
An electronic device comprising: a discriminating means for discriminating an operating state of each of the slave nodes based on a trial result by the trial means. The electronic device according to claim 11, wherein the discriminating means determines that the operating state of each of the slave nodes is normal when the trial result indicates that the communication is not established. The electronic device according to claim 11 or 12, wherein the discriminating means determines that the operating state of at least one of the slave nodes is not normal when the trial result indicates that the communication is established. .. 13. The electron according to claim 13, wherein the discriminating means determines that at least one of the slave nodes has been reset to the initial state when the trial result indicates that communication has been established. device. The electronic device communicates with the plurality of slave nodes by using an I2C communication method.
One of claims 11 to 14, wherein the determination means determines that the trial result indicates the establishment of communication when the state of the serial data bus connected to each slave node is ACK. The electronic device according to item 1. The electronic device according to claim 15, wherein the determination means determines that the trial result indicates a failure of communication when the state of the serial data bus connected to each slave node is NCK. .. The electronic device according to any one of claims 11 to 16, wherein the unique address is different from each other among the slave nodes. One of claims 11 to 17, wherein the trial means attempts to communicate with each of the slave nodes by using the initial address in a state where power is supplied to all the slave nodes that attempt to communicate. The electronic device described in the section. When the trial result indicates that the communication is established, the trial means uses the initial address in a state where the power supply to the slave nodes is stopped and then the power is supplied to the slave nodes again. The electronic device according to claim 18, wherein the electronic device attempts to communicate with each of the slave nodes. The electronic device according to any one of claims 11 to 19, wherein the address of each slave node is maintained at the initial address in the reset state of each slave node. The electronic device according to any one of claims 11 to 20, wherein the electronic device is a master node. A method of controlling a master-slave communication system that includes a master node and a plurality of slave nodes that hold an initial address that is a non-unique address.
The address of each of the plurality of slave nodes is changed from the initial address to the unique address of each slave node different from the initial address.
After changing the address, the initial address is used to try to communicate with each of the slave nodes.
A control method of a master-slave communication system, characterized in that an operating state of each slave node is determined based on a trial result of communication with each slave node. A method of controlling an electronic device that communicates with multiple slave nodes that hold an initial address that is a non-unique address.
The address of each of the plurality of slave nodes is changed from the initial address to the unique address of each slave node different from the initial address.
After changing the address, the initial address is used to try to communicate with each of the slave nodes.
A method for controlling an electronic device, which comprises determining an operating state of each slave node based on a trial result of communication with each slave node.

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