JP2021170625A - Superjunction semiconductor device and method of manufacturing superjunction semiconductor device - Google Patents

Abstract

To provide a superjunction semiconductor device and a method of manufacturing the superjunction semiconductor device, enabling SJ structure to be easily formed and enabling cost reduction.SOLUTION: A method of manufacturing a semiconductor device comprising an active region 30 where current flows and a terminal end structure portion 40, includes first to eighth steps. In the first step, a first semiconductor layer 2 of a first conductivity type is formed on a front face of a semiconductor substrate 1 of the first conductivity type. In the second step, a first trench is formed. In the third step, a second semiconductor layer 27 of the first conductivity type that has an impurity concentration lower than that of the first semiconductor layer 2 is formed on a surface of the first semiconductor layer 2 and in the first trench. In the fourth step, parallel pn structure 20 is formed. In the fifth step, a second trench 18B is formed. In the sixth step, a second semiconductor region 5 of a second conductivity type is formed. In the seventh step, a gate insulating film 7 and a gate electrode 8 are formed. In the eighth step, a first semiconductor region 6 of the first conductivity type is formed.SELECTED DRAWING: Figure 1

Description

The present invention relates to a superjunction semiconductor device and a method for manufacturing a superjunction semiconductor device.

The electrification of automobiles represented by electric vehicles and hybrid vehicles is increasing more and more, and the demand for low loss (low on-resistance) for power semiconductors is increasing in order to reduce power consumption. Trench gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are predominant in order to reduce on-resistance in the low withstand voltage class. Further, a super junction (SJ) structure is effective for reducing the on-resistance of the trench gate MOSFET. The superjunction structure comprises a parallel pn region in which an n-type column region and a p-type column region are alternately and repeatedly arranged in a direction parallel to the main surface of the semiconductor substrate. As a method for forming the parallel pn region, a multi-stage epitaxial method and a trench embedding method are known.

In the multi-stage epitaxial method, a parallel pn region is formed by the following steps. First, an epitaxial layer is formed on the main surface of the semiconductor substrate. Next, impurities that form n-type regions and p-type regions are ion-implanted into the epitaxial layer. After that, the epitaxial layer formation and the ion implantation are alternately repeated so that a predetermined thickness of the parallel pn region corresponding to the withstand voltage of the superjunction semiconductor device can be obtained. After that, heat treatment is performed to connect each of the n-type region and the p-type region in the depth direction to form a parallel pn region. (For example, see Patent Document 1 below.).

In the trench embedding method, a parallel pn region is formed by the following steps. First, an n-type epitaxial layer is formed on the main surface of the semiconductor substrate. Next, a trench for forming a p-type column region is formed in this n-type epitaxial layer. The region where no trench is formed is the n-type column region. The depth of the trench is set so that the thickness of a predetermined parallel pn region corresponding to the withstand voltage of the superjunction semiconductor device can be obtained. Then, by embedding the inside of the trench with a p-type epitaxial layer, a parallel pn region is formed (see, for example, Patent Documents 1 and 2 below).

Japanese Unexamined Patent Publication No. 2016-21547 Japanese Unexamined Patent Publication No. 2004-241768

However, in the multi-stage epitaxial method, since mask formation and ion implantation by photolithography technology are repeated for each epitaxial growth, there is a high possibility of characteristic fluctuation due to dimensional and alignment variations. Further, mutual diffusion of parallel pn regions in the thermal history for each epitaxial growth may cause concentration compensation in adjacent n-type column regions and p-type column regions, resulting in high on-resistance. In addition, there are many processes, the lead time is long, and the manufacturing cost is high.

Further, in the trench embedding method, when the trench is embedded in the p-type epitaxial layer, the p-type epitaxial layer formed on the surface of the n-type epitaxial layer to be the n-type column region is removed by a CMP (Chemical Mechanical. Policeher) step. , N-type epitaxial layer is formed on the surface. The reason for removing the p-type epitaxial layer is that the withstand voltage cannot be maintained if the p-type layer is present in the edge termination region. Therefore, the trench embedding method requires a CMP apparatus, and the characteristics may vary due to variations in the amount of polishing in the CMP process. Further, the p-type epitaxial growth has a larger variation in the impurity concentration than the n-type epitaxial growth, and it is necessary to control the impurity concentration. Further, since the high-concentration p-type epitaxial layer and the n-type drift layer are joined, the gradient of the impurity concentration is large, the depletion layer is difficult to spread, and the withstand voltage may decrease.

An object of the present invention is to provide a superjunction semiconductor device and a method for manufacturing a superjunction semiconductor device, which can easily form an SJ structure and reduce costs in order to solve the above-mentioned problems caused by the prior art.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a superjunction semiconductor device according to the present invention is arranged in an active region through which an electric current flows and outside the active region, and is arranged around the active region. This is a method for manufacturing a superjunction semiconductor device having a terminal structure portion in which a pressure resistant structure is formed surrounding the device. First, a first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is performed on the front surface of the first conductive type semiconductor substrate. Next, a second step of forming the first trench from the surface of the first semiconductor layer is performed. Next, a third step of forming a first conductive type second semiconductor layer having a lower impurity concentration than the first semiconductor layer is performed on the surface of the first semiconductor layer and in the first trench. Next, by injecting an impurity that becomes the second conductive type into the second semiconductor layer, a well region of the second conductive type is formed inside the second semiconductor layer, and the first conductive type first. A parallel pn structure in which the first column and the second conductive type second column are repeatedly and alternately arranged in a direction parallel to the front surface, and the upper surface of the second column is the bottom surface of the well region. The fourth step of forming the parallel pn structure in contact is performed. Next, a fifth step of forming a second trench that penetrates the second semiconductor layer and reaches the first column is performed. Next, a sixth step of forming the second conductive type second semiconductor region on the surface of the parallel pn structure of the active region is performed. Next, a seventh step of forming the gate insulating film and the gate electrode inside the second trench is performed. Next, the eighth step of selectively forming the first conductive type first semiconductor region on the surface layer of the second semiconductor region of the active region is performed.

Further, the method for manufacturing a superjunction semiconductor device according to the present invention is characterized in that, in the sixth step, the bottom surface of the second semiconductor region is formed to be shallower than the bottom surface of the well region in the above-described invention. do.

Further, in the method for manufacturing a superjunction semiconductor device according to the present invention, in the above-described invention, in the sixth step, the impurity concentration in the well region is formed to be lower than the impurity concentration in the second semiconductor region. It is characterized by.

Further, in the method for manufacturing a superjunction semiconductor device according to the present invention, in the above-described invention, in the fourth step, impurities to be the second conductive type are injected into the second semiconductor layer in the first trench. It is characterized by.

Further, according to the method for manufacturing a superjunction semiconductor device according to the present invention, in the above-described invention, in the fourth step, the second conductive type is formed on the surface layer of the second semiconductor layer on the surface of the first semiconductor layer. It is characterized by injecting an impurity that becomes.

Further, the method for manufacturing a superjunction semiconductor device according to the present invention is characterized in that, in the above-described invention, the second column is also formed in the terminal structure portion in the fourth step.

Further, the method for manufacturing a superjunction semiconductor device according to the present invention is characterized in that, in the above-described invention, the sixth step is performed before the fifth step.

Further, in the method for manufacturing a superjunction semiconductor device according to the present invention, in the above-described invention, in the fourth step, impurities to be the second conductive type are injected only into the second semiconductor layer in the first trench. It is characterized by that.

In order to solve the above-mentioned problems and achieve the object of the present invention, the superjunction semiconductor device according to the present invention has the following features. It is a superjunction semiconductor device having an active region through which an electric current flows and a terminal structure portion arranged outside the active region and having a pressure-resistant structure surrounding the active region. A first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is provided on the front surface of the first conductive type semiconductor substrate. Inside the first semiconductor layer, a parallel pn structure is provided in which the first conductive type first column and the second conductive type second column are repeatedly and alternately arranged in a direction parallel to the front surface. A second conductive type second semiconductor region is provided on the surface layer of the parallel pn structure of the active region. A first conductive type first semiconductor region is selectively provided on the surface layer of the second semiconductor region of the active region. A second trench that penetrates the first semiconductor region and the second semiconductor region and reaches the first column is provided. A gate electrode is provided inside the second trench via a gate insulating film. A second conductive type well region is provided inside the first semiconductor layer, the lower surface of the well region is in contact with the upper surface of the second column, and the bottom surface of the well region is deeper than the bottom surface of the second semiconductor region. The width of the upper surface of the well region is wider than the width of the second column.

Further, the superjunction semiconductor device according to the present invention is characterized in that, in the above-described invention, the impurity concentration in the well region is lower than the impurity concentration in the second semiconductor region.

Further, the superjunction semiconductor device according to the present invention is characterized in that, in the above-described invention, the parallel pn structure is also provided in the terminal structure portion.

Further, the superjunction semiconductor device according to the present invention is characterized in that, in the above-described invention, the repetition pitch of the parallel pn structure of the terminal structure portion is narrower than the repetition pitch of the parallel pn structure of the active region.

Further, in the above-described invention, the superjunction semiconductor device according to the present invention is of the first conductive type having a lower impurity concentration than the first semiconductor layer on the surface layer opposite to the semiconductor substrate side of the terminal structure portion. It is characterized by including a second semiconductor layer.

Further, the superjunction semiconductor device according to the present invention is characterized in that, in the above-described invention, the well region and the second semiconductor region are in contact with the side wall of the second trench.

According to the above-described invention, an n ^- type epitaxial layer (first conductive type second semiconductor layer) is provided in the edge termination region, and a field oxide film is provided on the surface of the ^{n-type epitaxial layer.} With the n ^- type epitaxial layer, the withstand voltage of the SJ-MOSFET can be improved by extending the depletion layer extending from the pn junction between the ^n- type epitaxial layer and the p ^{- type resurf region to the n-type epitaxial layer.} Further, since the n ^- type epitaxial layer has a low impurity concentration, it becomes easy to control the concentration of the p-type base region by ion implantation, and the variation in the gate threshold voltage Vth can be suppressed.

Further, a trench for a p-type column is formed in a region to be a p-type column region, and an n ^- type epitaxial layer having a ^{lower impurity concentration than the n-type drift layer to be an n-type column region is deposited to form an n-} type epitaxial layer. The p-type column region 4 and the p-type well region are formed by ion injection and diffusion of p-type impurities from the surface. As a result, the p-type column region can be formed without depositing the p-type epitaxial layer, so that it is not necessary to remove the p-type epitaxial layer at the edge termination region. Further, the surface portion in which the trench for the p-type column is embedded does not require a step of flattening by using a CMP device or the like. Therefore, the SJ structure can be easily formed, and the manufacturing cost can be reduced.

According to the superjunction semiconductor device and the method for manufacturing a superjunction semiconductor device according to the present invention, it is possible to easily form an SJ structure and reduce costs.

It is sectional drawing which shows the structure of SJ-MOSFET which concerns on embodiment. It is sectional drawing which shows the other structure of SJ-MOSFET which concerns on embodiment. It is sectional drawing which shows the other structure of SJ-MOSFET which concerns on embodiment. It is sectional drawing which shows the other structure of SJ-MOSFET which concerns on embodiment. It is sectional drawing which shows the other structure of SJ-MOSFET which concerns on embodiment. It is a top view which shows the structure of the SJ-MOSFET according to the embodiment. It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET which concerns on embodiment (the 1). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET which concerns on embodiment (the 2). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 3). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 4). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 5). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (No. 6). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 7). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET which concerns on embodiment (the 8). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 9). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 10). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 11). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 12). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (No. 13). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 14). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 15). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (No. 16). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (No. 17). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (the 18). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (No. 19). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (No. 20). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (No. 21). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET which concerns on embodiment (the 22). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET which concerns on embodiment (the 23). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET which concerns on embodiment (the 24). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (No. 25). It is sectional drawing which shows the state in the process of manufacturing by the 1st manufacturing method of SJ-MOSFET according to embodiment (No. 26). It is sectional drawing which shows the state in the process of manufacturing by the 2nd manufacturing method of SJ-MOSFET according to embodiment (the 1). It is sectional drawing which shows the state in the process of manufacturing by the 2nd manufacturing method of SJ-MOSFET according to embodiment (the 2). It is sectional drawing which shows the state in the process of manufacturing by the 2nd manufacturing method of SJ-MOSFET according to embodiment (the 3). It is sectional drawing which shows the state in the process of manufacturing by the 2nd manufacturing method of SJ-MOSFET according to embodiment (the 4). It is sectional drawing which shows the state in the process of manufacturing by the 2nd manufacturing method of SJ-MOSFET according to embodiment (the 5). It is sectional drawing which shows the state in the process of manufacturing by the 3rd manufacturing method of SJ-MOSFET which concerns on embodiment (the 1). It is sectional drawing which shows the state in the process of manufacturing by the 3rd manufacturing method of SJ-MOSFET which concerns on embodiment (the 2). It is sectional drawing which shows the state in the process of manufacturing by the 3rd manufacturing method of SJ-MOSFET according to embodiment (the 3). It is sectional drawing which shows the state in the process of manufacturing by the 3rd manufacturing method of SJ-MOSFET which concerns on embodiment (the 4). It is sectional drawing which shows the state in the process of manufacturing by the 3rd manufacturing method of SJ-MOSFET according to embodiment (the 5). It is sectional drawing which shows the state in the process of manufacturing by the 3rd manufacturing method of SJ-MOSFET according to embodiment (No. 6). It is sectional drawing which shows the state in the process of manufacturing by the 3rd manufacturing method of SJ-MOSFET according to embodiment (the 7). It is sectional drawing which shows the state in the process of manufacturing by the 3rd manufacturing method of SJ-MOSFET which concerns on embodiment (the 8). It is sectional drawing which shows the state in the process of manufacturing by the 3rd manufacturing method of SJ-MOSFET according to embodiment (the 9).

Hereinafter, preferred embodiments of the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. When the notation of n and p including + and-is the same, it indicates that the concentrations are close to each other, and the concentrations are not necessarily the same. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment)
The superjunction semiconductor device according to the present invention will be described by taking SJ-MOSFET as an example. FIG. 1 is a cross-sectional view showing the structure of the SJ-MOSFET according to the embodiment.

The SJ-MOSFET (superjunction semiconductor device) 50 shown in FIG. 1 is located on the front surface (the surface on the p-type base region 5 side, which will be described later) of a semiconductor substrate (silicon substrate: semiconductor chip) made of silicon (Si). It is an SJ-MOSFET 50 provided with a MOS (Metal Oxide Semiconductor) gate. The SJ-MOSFET 50 includes an active region 30 and an edge termination region 40 surrounding the active region 30. The active region 30 is a region through which a current flows when in the ON state. The edge termination region 40 includes a withstand voltage holding region that relaxes the electric field on the front surface side of the semiconductor substrate in the drift region and maintains the withstand voltage. The boundary between the active region 30 and the edge termination region 40 is the center of the trench 18B in which ^{the n + type source region 6 described later is provided on only one side.} In the active region 30 of FIG. 1, only one unit cell (functional unit of the element) is shown, and other unit cells adjacent thereto are not shown. The unit cell indicates from the center of the trench 18B to the center of the adjacent trench 18B.

The n ⁺ type semiconductor substrate (first conductive type semiconductor substrate) 1 is, for example, a silicon single crystal substrate doped with arsenic (As) or phosphorus (P). An n-type drift layer (first conductive type first semiconductor layer) 2 is provided on the ^{n + type semiconductor substrate 1.} The n-type drift layer 2 is a ^{low-concentration n-type layer having a lower impurity concentration than the n +} type semiconductor substrate 1 and, for example, being doped with phosphorus. Hereinafter, the n ⁺ type semiconductor substrate 1 and the n-type drift layer 2 are collectively referred to as a semiconductor substrate. Between the n ⁺ -type semiconductor substrate 1 and the n-type drift layer 2, n-type buffer layer (not shown) may be disposed at a lower impurity concentration than the n-type drift layer 2. The n-type buffer layer is, for example, a low-concentration n-type layer doped with phosphorus. A MOS gate structure (element structure) is formed on the front surface side of the semiconductor substrate. Further, on the back surface of the semiconductor substrate, a back surface electrode 11 serving as a drain electrode is provided.

The active region 30 of the SJ-MOSFET 50 is provided with a parallel pn region 20 in which the n-type column region 3 and the p-type column region 4 are alternately and repeatedly arranged. The edge end region 40 may also be provided with a parallel pn region 20B, which will be described later.

In FIG. 1, the direction in which the n-type column region 3 and the p-type column region 4 of the parallel pn region 20 are alternately and repeatedly arranged is the x direction. A p-type well region 63 is provided above the p-type column region 4 of the active region 30. The bottom surface of the p-type well region 63 of the active region 30 is in contact with the upper surface of the p-type column region 4. P-type well region 63 and the p-type column region 4 the active region 30, n provided on the upper surface of the n-type drift layer 2 ^- from the surface of the type epitaxial layer 27 so as not to reach the n ⁺ -type semiconductor substrate 1 of the surface It is provided. The width of the upper surface of the p-type well region 63 is wider than the width of the p-type column region 4. ^{Here, the surface of the n-} type epitaxial layer 27 provided on the upper surface of the n-type drift layer 2 (above the first main surface of the semiconductor substrate) is referred to as the upper surface 100.

When the width of the upper surface of the p-type well region 63 is wider than the width of the p-type column region 4, the effect of improving the reverse withstand voltage (BVDSS: breakdown voltage between drain and source) can be obtained. As will be described later, the planar shapes of the n-type column region 3 and the p-type column region 4 in the active region 30 and the edge termination region 40 are, for example, stripe shapes. When the plane shape of the p-type column region 4 is a stripe shape, the plane shape of the p-type well region 63 is also a stripe shape.

The impurity concentration of the n-type column region 3 is ^{lower than the impurity concentration of the n +} type semiconductor substrate 1. The impurity concentration in the p-type column region 4 and the impurity concentration in the p-type well region 63 may be equal. Further, the impurity concentration in the n-type column region 3 and the impurity concentration in the p-type column region 4 may be equal.

A p-type base region (second conductive type second semiconductor region) 5 is selectively provided on the upper surface 100 side (above the first main surface of the semiconductor substrate) of the active region 30. The p-type base region 5 is provided so as to overlap the p-type well region 63. The bottom surface of the p-type well region 63 is provided at a position deeper than the bottom surface of the p-type base region 5 in the y direction (depth direction) of FIG. The p-type base region 5 has a higher impurity concentration than the p-type well region 63. Further, the p-type base region 5 has a higher impurity concentration than the p-type column region 4.

^{An n +} type source region (first conductive type first semiconductor region) 6 is selectively provided on the surface side of the p-type base region 5 of the active region 30. ^{A p ++} type contact region 14 in contact ^{with the n +} type source region 6 may be selectively provided on the surface side of the p-type base region 5 of the active region 30.

A trench structure is formed at the boundary between the active region 30 and the active region 30 and the edge termination region 40. Specifically, the trench 18B (second trench) penetrates the p-type base region 5, the p-type base region 5A described later, and the n ⁺ -type source region 6 from the upper surface 100 to reach the n-type column region 3.

^{The p-type base region 5 and the n +} -type source region 6 are in contact with the side wall of the trench 18B provided in the active region 30. ^{Further, a p-type base region 5 and an n +} -type source region 6 are in contact with the active region 30 side on the side wall of the trench 18B provided at the boundary between the active region 30 and the edge termination region 40, and the edge termination region 40 side will be described later. The p-type base region 5A is in contact with the base region 5A. The trench 18B is not provided in the edge end region 40.

The trench 18B of the active region 30 is provided between the selectively provided p-type base region 5, and the trench 18B at the boundary between the active region 30 and the edge termination region 40 is the p-type base region 5 and the p-type base region. It is provided between 5A. The planar shape of the trench 18B is, for example, a stripe shape extending in the depth direction (z direction) of FIG.

In the trench 18B, a gate insulating film 7 is formed along the inner wall of the trench 18B. A gate electrode 8 is provided inside the gate insulating film 7 in the trench 18B. The gate electrode 8 is insulated from the n-type column region 3 (n-type drift layer 2) and the p-type base region 5 by the gate insulating film 7. A part of the gate electrode 8 may be provided with a gate wiring (not shown) protruding from above the trench 18B (the side on which the source electrode 10 described later is provided) toward the source electrode 10. A gate insulating film 7 is provided below the gate wiring. An interlayer insulating film 9 is provided above the gate wiring.

The interlayer insulating film 9 is provided on the upper surface 100 so as to cover the upper surface of the gate electrode 8 embedded in the trench 18B. An insulating film (not shown) is provided between the gate electrode 8 and the interlayer insulating film 9 (the gate insulating film 7 formed along the inner wall of the trench 18B and the interlayer insulating film covering the upper part of the gate electrode 8). The boundary of 9 and the boundary of the insulating film provided between the gate electrode 8 and the interlayer insulating film 9 are not shown). A contact hole 64A is provided between the interlayer insulating film 9 covering the upper surface of the gate electrode 8 embedded in the trench 18B of the active region 30 and the adjacent trench 18B, and the n ⁺ type source region 6 and the p ⁺⁺ type contact are provided. Region 14 is exposed. Similarly, a contact hole 64A is also provided in the interlayer insulating film 9 covering the upper surface of the gate electrode 8 embedded in the trench 18B of the adjacent active region 30 and the trench 18B provided at the boundary between the active region 30 and the edge termination region 40. The n ⁺ type source region 6 and the p ⁺⁺ type contact region 14 are exposed. Hereinafter, the description of the insulating film (not shown) provided between the gate electrode 8 and the interlayer insulating film 9 will be omitted.

^{The source electrode 10 is an n +} type via a contact hole 64A provided on the upper surface of the interlayer insulating film 9 and formed in the interlayer insulating film 9 and the insulating film (not shown) provided on the lower surface of the interlayer insulating film 9. It is electrically connected to the source region 6 and the p ^{++ type contact region 14.} Hereinafter, the description of the insulating film (not shown) provided on the lower surface of the interlayer insulating film 9 will be omitted. The source electrode 10 is electrically insulated from the gate electrode 8 by the interlayer insulating film 9. A barrier metal (not shown) that prevents the diffusion of metal atoms from the source electrode 10 to the gate electrode 8 side may be provided between the source electrode 10 and the interlayer insulating film 9. A protective film (not shown) such as a passivation film made of polyimide is selectively provided on the source electrode 10. In the opening provided in the protective film such as the passivation film provided on the source electrode 10, the region where the source electrode 10 is exposed becomes the source pad region (not shown).

Further, the edge termination region 40 that maintains the withstand voltage is provided with a p-type column region 4A having the same width as the p-type column region 4 of the active region 30 on the side closest to the active region 30. The p-type column region 4 and the p-type column region 4A may have the same depth in the y direction (depth direction) of FIG. A p-type well region 63A is provided above the p-type column region 4A. The upper surface of the p-type column region 4A and the bottom surface of the p-type well region 63A are in contact with each other. The p-type column region 4 and the p-type column region 4A may have the same impurity concentration, and the p-type well region 63 and the p-type well region 63A may also have the same impurity concentration.

The p-type base region 5A is provided so as to overlap the p-type well region 63A, and is in contact with the side wall of the trench 18B provided at the boundary between the active region 30 and the edge termination region 40. The bottom surface of the p-type well region 63A is provided at a position deeper than the bottom surface of the p-type base region 5A in the y direction (depth direction) of FIG. The p-type base region 5A may be formed at the same depth as the p-type base region 5 of the active region 30 in the y direction (depth direction) of FIG. Further, the p-type well region 63A may be formed at the same depth as the p-type well region 63 of the active region 30 in the y direction (depth direction) of FIG.

The impurity concentration of the p-type base region 5A is the same as that of the p-type base region 5. Further, the impurity concentration in the p-type base region 5A is higher than the impurity concentration in the p-type well region 63A. ^{A p ++} type contact region 14A having a higher impurity concentration than the p-type base region 5A may be selectively provided on the surface side of the p-type base region 5A.

A parallel pn region 20B is provided on the outer peripheral side of the SJ-MOSFET 50 from the p-type column 4A of the edge termination region 40. In the parallel pn region 20B, the n-type column region 3B and the p-type column region 4B are alternately and repeatedly arranged. The direction in which the n-type column region 3B and the p-type column region 4B are alternately and repeatedly arranged is the same as the direction in which the n-type column 3 and the p-type column region 4 in the active region 30 are alternately and repeatedly arranged.

In the parallel pn region 20B of the edge termination region 40, the sum of the width of the adjacent n-type column and the width of the p-type column is narrower than that of the parallel pn region 20 of the active region 30. Here, the sum of the widths of adjacent n-type columns and the widths of p-type columns is defined as a repeating pitch. Therefore, the width of the n-type column region 3B and the width of the p-type column region 4B of the edge termination region 40 are narrower than the width of the n-type column region 3 and the width of the p-type column region 4 of the active region 30. As a result, the depletion layer is likely to spread in the edge termination region 40, and the withstand voltage of the edge termination region 40 can be made higher than the withstand voltage of the active region 30.

The edge end region 40 ^{is provided with a p-} type resurf region 12. The p ^- type resurf region 12 extends from the boundary between the active region 30 and the edge termination region 40 to the lower part of the field plate 29 and the field oxide film 13 described later. The planar shape of the p ^- type resurf region 12 is annular.

The p ^- type resurf region 12 is provided deeper than the p-type base region 5A in the y direction (depth direction) of FIG. The p ^- type resurf region 12 has a lower impurity concentration than the p-type well region 63A. Therefore, a p-type well region 63A, a p-type base region 5A, and a p ⁺⁺ type contact region 14A are provided in the p ^{-type resurf region 12.} The p ^- type resurf region 12 is in contact with the trench 18B provided at the boundary between the active region 30 and the edge termination region 40.

The p ^- type resurf region 12 can alleviate the electric field concentration applied to the outer peripheral end of the p-type base region 5A of the SJ-MOSFET 50, and increase the withstand voltage of the edge termination region 40. In the parallel pn structure 20B of the edge termination region 40, the upper surfaces of a part of the n-type column region 3B and the p-type column region 4B on the active region 30 side are in contact with ^{the bottom surface of the p-} type resurf region 12.

The upper surface of the p-type column region 4B of the parallel pn region 20B on the outermost side of the SJ-MOSFET 50 is in contact with the bottom surface of the p-type well region 63B on the outermost side of the SJ-MOSFET 50. ^{An n-} type epitaxial layer 27, which will be ^{described later, is provided between the p-type well region 63B and the p-} type resurf region 12 on the outermost side of the SJ-MOSFET 50 in the x direction of FIG.

Further, in the edge termination region 40, n on the surface of the n-type drift layer 2 (semiconductor substrate) ^- type epitaxial layer (first conductivity type second semiconductor layer) 27 is provided. As will be described later, the n ^- type epitaxial layer 27 is formed on the entire surface of the n-type drift layer 2. The surface layer of the n ^- type epitaxial layer 27 includes the upper portions of the p-type well regions 63, 63A, 63B, the p-type base regions 5, 5A, and the p ^- type resurf region 12, and the n ⁺ type source. Region 6 and p ⁺⁺ type contact regions 14, 14A are provided.

Further, n ^- impurity concentration type epitaxial layer 27 is lower than the impurity concentration of the n-type drift layer 2. ^{Therefore, the p-type impurities injected by ion implantation are more likely to diffuse in the n-} type epitaxial layer 27 than in the n-type drift layer 2 by the heat treatment after ion implantation, and are less likely to diffuse in the n-type drift layer 2. Therefore, it becomes easy to control the diffusion of the p-type base region 5 due to the heat treatment after ion implantation, and the variation in the gate threshold voltage Vth can be suppressed.

In the x direction of FIG. 1, a field oxide film 13 is provided from the outer peripheral side of the SJ-MOSFET 50 ^{over the surfaces of the n-} type epitaxial layer 27, the p-type well region 63B, and the p ^{-type resurf region 12.} The field oxide film 13 may be provided deeper than the upper surface 100 in the y direction of FIG. ^{The field oxide film 13 is continuously covered with a p-} type resurf region 12 from the end portion of the field oxide film 13 on the active region 30 side to a part of the lower surface. A p ^- type resurf region 12, a p-type well region 63B, and an n ^- type epitaxial layer 27 are provided on the lower surface of the field oxide film 13, and are continuous from the other end of the field oxide film 13 to a part of the lower surface. The n ^- type epitaxial layer 27 is provided.

An insulating film 66A connected to the end of the field oxide film 13 on the active region 30 side is provided on the upper surface of the ^{p- type resurf region 12, the p-type well region 63A, and the p-type base region 5A, and is n-} type epitaxial. An insulating film 66B connected to the other end of the field oxide film 13 is provided on the upper surface of the layer 27. The insulating films 66A and 66B may be formed in the same process as the gate insulating film 7.

The field plate 29 is provided on the upper surface of the field oxide film 13 and the insulating film 66A connected to the end of the field oxide film 13 on the active region 30 side. The field plate 29 is electrically connected to the gate electrode 8 and also has a gate wiring function.

The channel stopper 62 is provided on the upper surface of the field oxide film 13 and the insulating film 66B connected to the other end of the field oxide film 13. The field plate 29 and the channel stopper 62 are separated on the field oxide film 13 and are provided at intervals. The interlayer insulating film 9 is provided so as to cover the field oxide film 13, the field plate 29, and the channel stopper 62. An insulating film (not shown) is provided between the interlayer insulating film 9, the field plate 29, and the channel stopper 62. Hereinafter, the description of the insulating film (not shown) provided between the interlayer insulating film 9 and the field plate 29 and the channel stopper 62 will be omitted.

An interlayer insulating film 9 provided so as to cover the upper surface of the gate electrode 8 embedded in the trench 18B provided at the boundary between the active region 30 and the edge termination region 40 and an interlayer insulating film 9 covering the field plate 29. A contact hole 64B is provided between them, and the p ⁺⁺ type contact region 14A is exposed.

A contact hole 64C is provided in the interlayer insulating film 9 that covers the field oxide film 13, the field plate 29, and the channel stopper 62, and the field plate 29 is exposed.

The source electrode 10 provided on the upper surface of the interlayer insulating film 9 extends from the active region 30 to the upper surface of a part of the edge termination region 40, and p ^{+ through the contact hole 64B formed in the interlayer insulating film 9. It} is electrically connected to the + type contact region 14A and the p-type base region 5A.

The metal gate runner 61 is electrically connected to the field plate 29 via a contact hole 64C formed in the interlayer insulating film 9. The interlayer insulating film 9 of the p ^- type resurf region 12, the field oxide film 13, the field plate 29, the channel stopper 62, and the edge termination region 40 may be provided in an annular shape on the outer circumference of the SJ-MOSFET 50. The metal gate runner 61 is electrically insulated from the source electrode 10.

FIG. 2A is a cross-sectional view showing another structure of the SJ-MOSFET 50 according to the embodiment. The difference between FIG. 2A and FIG. 1 is that the parallel pn region 20B on the outer peripheral side of the SJ-MOSFET 50 is not provided from the p-type column region 4A of the edge termination region 40. When the parallel pn region 20B is not provided, the n ^- type epitaxial layer 27 causes the ^{depletion layer extending from the pn junction between the n-} type epitaxial layer 27 and the p ^- type resurf region 12 to be the SJ of the n-type epitaxial layer 27. The withstand voltage of the SJ-MOSFET 50 can be improved by expanding it to the outer peripheral side of the MOSFET 50.

FIG. 2B is a cross-sectional view showing still another structure of the SJ-MOSFET 50 according to the embodiment. The difference between FIG. 2B and FIG. 2A is that the p-type well region 63 in contact with the upper surface of the p-type column region 4 of the active region 30 and the p-type well region 63A in contact with the upper surface of the p-type column region 4A of the edge termination region 40 are provided. It is a point that has not been done. In FIG. 2B, a p-type base region 5 is provided on the upper surface of the p-type column region 4 of the active region 30. The upper surface of the p-type column region 4 of the active region 30 is in contact with the bottom surface of the p-type base region 5. Further, a p-type base region 5A is provided on the upper surface of the p-type column region 4A of the edge termination region 40. The upper surface of the p-type column region 4A of the edge termination region 40 is in contact with the bottom surface of the p-type base region 5A. The difference in cross-sectional shape between FIG. 2B and FIG. 2A is due to the difference in the position of the injection region for injecting the p-type impurity described later for forming the p-type column region 4. The SJ-MOSFET 50 shown in FIG. 2B forms an injection region 92 in the section D2 as shown in FIG. 9C described later. In FIG. 2B, by not providing the p-type well regions 63 and 63A, there is no region that locally narrows the current path formed in the n-type drift layer 2 (n-type column region 3). The current path is narrowed by expanding the depletion layer from the pn junction of the n-type column region 3 and the p-type column regions 4 and 4A due to the on-voltage generated by passing a current, and expanding the depletion layer. When the current path becomes narrower (the depletion layer expands), the on-resistance increases. Therefore, by not providing the p-type well regions 63 and 63A, the on-resistance (resistance in the operating state) can be reduced as compared with FIG. 2A.

FIG. 2C is a cross-sectional view showing still another structure of the SJ-MOSFET 50 according to the embodiment. The difference between FIG. 2C and FIG. 2A is that the contact holes 64D, 64E, 64F formed in the interlayer insulating film 9 are provided with recesses 67A, 67B, 67C (grooves), and the contact plug 19 is provided inside the recesses 67A, 67B, 67C. Is embedded.

The interlayer insulating film 9 covering the upper surface of the gate electrode 8 embedded in the trench 18B of the active region 30 is provided with a recess 67A deeper than the upper surface 100 in the y direction between the interlayer insulating film 9 and the adjacent trench 18B. ^{The n +} type source region 6 and the p ⁺⁺ type contact region are in contact with (exposed) the side wall of the recess 67A. ^{A p ++} type contact region 14 is in contact (exposed) with the bottom of the recess 67A. The recess 67A is a contact hole 64D. An insulating film (not shown) is provided between the gate electrode 8 and the interlayer insulating film 9. Hereinafter, the description of the insulating film (not shown) provided between the gate electrode 8 and the interlayer insulating film 9 will be omitted.

Similarly, the upper surface 100 of the interlayer insulating film 9 covering the upper surface of the gate electrode 8 embedded in the trench 18B of the adjacent active region 30 and the trench 18B provided at the boundary between the active region 30 and the edge termination region 40 is also formed in the y direction. A deeper recess 67A is provided. ^{The n +} type source region 6 and the p ⁺⁺ type contact region 14 are in contact with (exposed) the side wall of the recess 67A. ^{A p ++} type contact region 14 is in contact (exposed) with the bottom of the recess 67A. The recess 67A is a contact hole 64D.

An interlayer insulating film 9 provided so as to cover the upper surface of the gate electrode 8 embedded in the trench 18B provided at the boundary between the active region 30 and the edge termination region 40 and an interlayer insulating film 9 covering the field plate 29. A recess 67B deeper than the upper surface 100 is provided between them in the y direction. ^{A p ++} type contact region 14A is in contact (exposed) with the side wall and the bottom of the recess 67B. The recess 67B is the contact hole 64E.

A recess 67C is provided in the interlayer insulating film 9 that covers the field oxide film 13, the field plate 29, and the channel stopper 62. The recess 67C penetrates the field plate 29 and the surface of the field oxide film 13 is exposed. The field plate 29 is in contact with (exposed) the side wall of the recess 67C. Further, the recess 67C may also be provided with a recess (groove) on the surface of the field oxide film 13, and the field oxide film 13 and the field oxide film 13 may be in contact with (exposed) the side wall of the recess 67C. A field oxide film is in contact with (exposed) the bottom of the recess 67C. The recess 67C is a contact hole 64F. An insulating film (not shown) is provided between the interlayer insulating film 9, the field plate 29, and the channel stopper 62. Hereinafter, the description of the insulating film (not shown) provided between the interlayer insulating film 9 and the field plate 29 and the channel stopper 62 will be omitted.

The contact plug 19 is, for example, a metal film made of tungsten (W) having high embedding property. Further, the contact plug 19 may be provided in the contact holes 64D, 64E, 64F via a barrier metal. The source electrode 10 is electrically connected to the ^{n +} type source region 6 and the p ⁺⁺ type contact region 14 via the contact plug 19 in the contact hole 64D of the active region 30. Further, the source electrode 10 extends to a part of the edge termination region 40 and is electrically connected to the ^{p ++ type contact region 14A via the contact plug 19 in the contact hole 64E of the edge termination region 40.}

The metal gate runner 61 is electrically connected to the field plate 29 via the contact plug 19 in the contact hole 64F. The source electrode 10 and the metal gate runner 61 are electrically insulated from each other.

FIG. 2C shows a case where the parallel pn region 20B on the outer peripheral side of the SJ-MOSFET 50 is not provided from the p-type column region 4A of the edge termination region 40, as in FIG. 2A. In FIG. 2C, a parallel pn region 20B located on the outer peripheral side of the SJ-MOSFET 50 from the p-type column region 4A of the edge termination region 40 may be provided as shown in FIG.

FIG. 2D is a cross-sectional view showing another structure of the SJ-MOSFET 50 according to the embodiment. The difference between FIG. 2D and FIG. 1 is that the p-type well regions 63 and 63A in contact with the upper surfaces of the p-type column regions 4 and 4A are in contact with the side wall of the trench 18B. In FIG. 2D, the p-type well region 63 of the active region 30 extends in the x direction of FIG. 2D and touches the side wall of the trench 18B, and the p-type well region 63A of the edge termination region 40 extends in the x direction of FIG. 2D. It extends to the trench 18B and is in contact with the trench 18B provided at the boundary with the edge termination region 40.

As a result, the p-type well regions 63 and 63A and the p-type base regions 5 and 5A come into contact with the side wall of the trench 18B. Therefore, it becomes easy to prevent defects due to defects in the p-type column regions 4 and 4A and channel defects such as short channels. Further, the electric field in the vicinity of the channel junction is relaxed by the two-step concentration gradient of the p-type well regions 63 and 63A and the p-type base regions 5 and 5A, and it becomes easy to secure a sufficient channel length.

FIG. 3 is a plan view showing the structure of the SJ-MOSFET according to the embodiment, and is a plan view of a cross section taken along the line AA'in FIG. As shown in FIG. 3, the repetition pitch P2 of the parallel pn region 20B of the edge termination region 40 is narrower than the repetition pitch P1 of the parallel pn region 20 of the active region 30.

The repeating pitch P1 of the parallel pn region 20 indicates the sum of the widths of the adjacent n-type column regions 3 and the widths of the p-type column regions 4 in the x direction of FIG. Further, the repeating pitch P2 of the parallel pn region 20B indicates the sum of the widths of the adjacent n-type column regions 3B and the widths of the p-type column regions 4B in the x direction of FIG. In order to secure the avalanche withstand voltage in the SJ-MOSFET 50 (superjunction semiconductor device), it is necessary to make the withstand voltage of the edge termination region 40 higher than the withstand voltage of the active region 30. Therefore, the width of the n-type column region 3B and the width of the p-type column region 4B of the edge termination region 40 may be narrower than the width of the n-type column region 3 and the width of the p-type column region 4 of the active region 30. As a result, the depletion layer is likely to spread in the edge termination region 40, and the withstand voltage of the edge termination region 40 can be made higher than the withstand voltage of the active region 30.

As shown in FIG. 3, the planar shape of the n-type column region 3 and the p-type column region 4 of the active region 30 may be, for example, a striped structure in which the longitudinal direction is parallel to the z direction. Further, the n-type column region 3B and the p-type column region 4B in the edge termination region 40 may also have a striped structure in which the longitudinal direction is parallel to the z direction. Further, the p-type column region 4B of the edge termination region 40 may also have a stripe structure whose longitudinal direction is parallel to the z direction. Further, although not shown, the planar shape of the trench 18B may also be a stripe shape whose longitudinal direction is parallel to the z direction.

(Manufacturing method of superjunction semiconductor device according to the embodiment)
Next, a method of manufacturing the superjunction semiconductor device according to the embodiment will be described. 4 to 21 are cross-sectional views showing a state in the middle of manufacturing the SJ-MOSFET according to the first embodiment according to the first manufacturing method. ^{First, an n +} type semiconductor substrate 1 made of silicon and serving as an n ⁺ type drain layer is prepared.

Then, on the front surface of the n ⁺ -type semiconductor substrate 1, the n ⁺ -type impurity concentration lower than the semiconductor substrate 1 n-type drift layer 2 is epitaxially grown. At this time, the n-type impurities may be doped and epitaxially grown so that the impurity concentration of the n-type drift layer 2 is 1.0 × 10 ¹⁶ / cm ³ or more and 3.0 × 10 ¹⁷ / cm ^{3 or less.} For example, when forming a superjunction semiconductor device having a withstand voltage of 40 V, the impurity concentration of the n-type drift layer 2 ^{may be 1.0 × 10 17} / cm ³ or less. Further, for example, when forming a superjunction semiconductor device having a withstand voltage of 100 V, the impurity concentration of the n-type drift layer 2 may be ^{5.0 × 10 16} / cm ^3. The impurity concentration of the n-type drift layer 2 is constant in the depth direction. Here, the depth direction is the direction from the surface of the n-type drift layer 2 toward the n ⁺ -type semiconductor substrate 1. The state up to this point is shown in FIG.

Next, the oxide film 23 is formed on the surface of the n-type drift layer 2. Next, a resist mask 24 having an opening at a position where the p-type column region 4 is formed is formed on the surface of the oxide film 23 by a photolithography technique. The state up to this point is shown in FIG.

Next, using the resist mask 24 as a mask, an opening in which the n-type drift layer 2 is exposed is formed in the oxide film 23 by dry etching. Next, the resist mask 24 is removed, and for example, anisotropic dry etching is performed using the oxide film 23 having an opening as a mask to form a p-type column trench (first trench) 25A in the n-type drift layer 2. do. The state up to this point is shown in FIG.

Next, isotropic etching and sacrificial oxidation are performed with the oxide film 23 attached. By this step, the damage of the p-type column trench 25A is removed, and the bottom of the p-type column trench 25A is rounded. Either isotropic etching or sacrificial oxidation can be performed first. In addition, either isotropic etching or sacrificial oxidation may be performed.

After that, the oxide film 23 is removed. The oxide film 23 may be removed at the same time as the sacrificial oxide film (not shown). The width of the p-type column trench 25B formed after the removal of the oxide film 23 is defined as W1. The state up to this point is shown in FIG.

Next, cover the surface of the n-type drift layer 2, impurity concentration than the n-type drift layer 2 so as to fill the inside of the p-type column trench 25B lower the n ^- -type epitaxial layer 27 is epitaxially grown. At this time, the n-type impurity may be doped and epitaxially grown so that ^{the impurity concentration of the n-} type epitaxial layer 27 is 1.0 × 10 ¹⁵ / cm ³ or more and 5.0 × 10 ¹⁶ / cm ^{3 or less.} For example, when forming a superjunction semiconductor device having a withstand voltage of 40 V, ^{the impurity concentration of the n-} type epitaxial layer 27 may be ^{2.0 × 10 16} / cm ^3. When forming a superjunction semiconductor device having a withstand voltage of 100 V, ^{the impurity concentration of the n-} type epitaxial layer 27 may be ^{1.0 × 10 16} / cm ^3.

The relationship between the impurity concentration of the n-type drift layer 2 and the impurity concentration of the n ^- type epitaxial layer 27 is that the impurity concentration of the n-type drift layer 2 is a [/ cm ³ ] and the impurity concentration of the n ^- type epitaxial layer 27 is b. When [/ cm ³ ] is set, a> b. The impurity concentration of the n-type drift layer 2 a [/ cm ^3] and impurity concentration of n ^- -type epitaxial layer 27 b [/ cm ^3], the relationship of 2 ≦ a / b ≦ 10 is satisfied.

The thickness of the flat portion of the n ^- type epitaxial layer 27 is defined as the thickness T1. n ^- flat portion of the type epitaxial layer 27, n on the surface of p-type column trench 25B of n-type drift layer 2 is not formed ^- a portion -type epitaxial layer 27 is formed. The ^{surface of the flat portion of the n-} type epitaxial layer 27 is defined as the upper surface 100.

When forming the n ^- type epitaxial layer 27, the thickness T1 is set to be thicker than 1/2 of the width W1 of the p-type column trench 25B (T1> W1 / 2). By making the thickness T1 thicker than 1/2 of the width W1 of the p-type column trench 25B, ^{the upper surface 100 (surface) of the n-} type epitaxial layer 27 is not flattened by using a CMP device or the like. You may. The state up to this point is shown in FIG.

9A to 9C are cross-sectional views of a state in which ion implantation 22 is performed using the ion implantation mask 21 and the implantation regions are formed under different conditions. First, an ion implantation mask 21 having a predetermined opening is formed on the surface (upper surface 100) of ^{the n-type epitaxial layer 27 by a photolithography technique, for example, with a photoresist.} The opening of the ion implantation mask 21 is formed in the upper part of the p-type column trench 25B. Using the ion implantation mask 21 as a mask, ion implantation 22 of p-type impurities is performed. The p-type impurity is, for example, boron (B) or aluminum (Al). The ion implantation 22 may be performed once or multiple times at different implantation depths. When the ion implantation 22 is performed a plurality of times at different depths, the order of the ion implantation 22 can be changed in various ways. Here, the depth indicates the direction from the upper surface 100 (surface) ^{of the n-} type epitaxial layer 27 toward the front surface of the ^{n + type semiconductor substrate 1.} The injection depth is the depth at which ^{impurities are injected from the upper surface 100 (surface) of the n-} type epitaxial layer 27 (the peak position of the impurity concentration distribution).

Further, the implantation regions 90, 91-1, 91-2, and 92, which will be described later and are formed by performing the ion implantation 22, indicate regions (peak positions of the impurity concentration distribution) in which impurities are implanted from the upper surface 100. Therefore, implantation depth, n ^- shows the depth up implantation region 90,91-1,91-2,92 formed -type epitaxial layer 27 ^- n from the upper surface 100 (the surface) of the type epitaxial layer 27 ..

Further, ^{the section D1 between the surface of the n-} type epitaxial layer 27 (upper surface 100) and the surface of the n-type drift layer 2 ( ^{thickness T1 of the flat portion of the n-} type epitaxial layer 27) is set as the n-type drift layer. The section D2 is defined as a section D2 from the surface of 2 (the surface of the semiconductor substrate) to the bottom of the p-type column trench 25B.

In FIG. 9A, the ion implantation 22 is performed once to form the implantation region 90. The injection region 90 is formed in section D1. For example, when the section D1 is 0.8 μm and the section D2 is 1.0 μm, the injection depth of the injection region 90 is 0.4 μm. The section D1 may be 0.5 μm or more and 1.0 μm or less. The injection depth of the injection region 90 may be 0.2 μm or more and 1.0 μm or less. The section D2 may be 0.5 μm or more and 2.0 μm or less. The injection region 90 may be formed at the boundary between the section D1 and the section D2.

In FIG. 9B, the ion implantation 22 is performed twice to form the implantation regions 91-1 and 91-2. The injection region 91-1 is formed in section D1 and the injection region 91-2 is formed in section D2. For example, when the section D1 is 0.8 μm and the section D2 is 1.0 μm, the injection depth of the injection region 91-1 is 0.4 μm and the injection depth of the injection region 91-2 is 1.6 μm. The section D1 may be 0.5 μm or more and 1.5 μm or less. The injection depth of the injection region 91-1 and the injection region 91-2 may be 0.2 μm or more and 2.0 μm or less. The section D2 may be 1.0 μm or more and 4.0 μm or less. Either the injection region 91-1 or the injection region 91-2 may be formed at the boundary between the section D1 and the section D2. Either of the order of forming the injection region 91-1 and the injection region 91-2 may come first.

In FIG. 9C, the ion implantation 22 is performed once to form the implantation region 92. The injection region 92 is formed in section D2. For example, when the section D1 is 0.8 μm and the section D2 is 1.0 μm, the injection depth of the injection region 92 is set to 1.2 μm. The section D1 may be 0.5 μm or more and 1.5 μm or less. The injection depth of the injection region 92 may be 0.4 μm or more and 2.0 μm or less. The injection region 92 may be formed at the boundary between the section D1 and the section D2.

In FIGS. 9A, 9B and 9C, typical examples of the implantation depth and the number of injections of the p-type impurity in the ion implantation 22 are shown, but the implantation depth and the number of injections in the implantation region can be variously changed. be.

FIG. 10A is a cross-sectional view in which the ion implantation mask 21 is removed after the ion implantation 22 of FIG. 9A and the p-type impurities are diffused by heat treatment. Since the n ^- type epitaxial layer 27 has a lower impurity concentration than the n-type drift layer 2, the p-type impurities ^{spread from the injection region 90 to the n-} type epitaxial layer 27 by the ion implantation 22 of the p-type impurities and the subsequent heat treatment. It will be easier. Therefore, the n-type drift layer 2 is formed with a p-type well region 63 in which the width W3 of the upper surface 100 of ^{the n-} type epitaxial layer 27 is wider than the width W2 of the p-type column region 4.

An n-type column region 3 is formed between adjacent p-type column regions 4, and a parallel pn region 20 is formed in the n-type drift layer 2. Further, the p-type column region 4A and the p-type well region 63A of the edge termination region 40 are also formed in the same manner in the same process.

The p-type impurity concentration in FIG. 10A has the highest impurity concentration in the injection region 90 shown in FIG. 9A, and the impurity concentration decreases as the distance from the injection region 90 increases in the depth direction. Here, the depth direction the n ^- is a direction from the surface of the type epitaxial layer 27 to the n ⁺ -type semiconductor substrate 1.

FIG. 10B is a cross-sectional view in which the ion implantation mask 21 is removed after the ion implantation 22 of FIG. 9B and the p-type impurities are diffused by heat treatment. Since the n ^- type epitaxial layer 27 has a lower impurity concentration than the n-type drift layer 2, the p-type impurities are implanted from the implantation region 91-1 and the injection region 91-2 by the ion implantation 22 of the p-type impurity and the subsequent heat treatment. It ^{easily spreads to the n-} type epitaxial layer 27. Therefore, the n-type drift layer 2 is formed with a p-type well region 63 in which the width W3 of the upper surface 100 of ^{the n-} type epitaxial layer 27 is wider than the width W2 of the p-type column region 4.

An n-type column region 3 is formed between adjacent p-type column regions 4, and a parallel pn region 20 is formed in the n-type drift layer 2. Further, the p-type column region 4A and the p-type well region 63A of the edge termination region 40 are also formed in the same manner in the same process.

The p-type impurity concentration in FIG. 10B has the highest impurity concentration in the injection region 91-1 and the injection region 91-2 shown in FIG. 9B, and is separated from the injection region 91-1 and the injection region 91-2 in the depth direction. Therefore, the impurity concentration is low. It should be noted that the p-type impurities increase in the portion of the injection region 91-1 and the injection region 91-2 where the diffusion of the p-type impurities overlaps, and the p-type impurities are separated from the injection region 91-1 and the injection region 91-2 in the depth direction. Also, the impurity concentration becomes high. Here, the depth direction the n ^- is a direction from the surface of the type epitaxial layer 27 to the n ⁺ -type semiconductor substrate 1.

FIG. 10C is a cross-sectional view in which the ion implantation mask 21 is removed after the ion implantation 22 of FIG. 9C and the p-type impurities are diffused by heat treatment. Since the n ^- type epitaxial layer 27 has a lower impurity concentration than the n-type drift layer 2, the p-type impurities ^{spread from the injection region 92 to the n-} type epitaxial layer 27 by the ion implantation 22 of the p-type impurities and the subsequent heat treatment. It will be easier.

The injection region 92 shown in FIG. 9C is formed in a section D2 away from the upper surface 100 side ^{of the n-type epitaxial layer 27.} Therefore, the p-type impurities in the injection region 92 are less likely to diffuse in the direction perpendicular to the depth direction (direction parallel to the widths W2 and W3) on the upper surface 100 side of the ^{n-type epitaxial layer 27.} Therefore, the width W2 of the p-type column region 4 and the width W3 of the upper surface 100 of ^{the n-type epitaxial layer 27 of the p-type well region 63 may be formed with the same width.}

An n-type column region 3 is formed between adjacent p-type column regions 4, and a parallel pn region 20 is formed in the n-type drift layer 2. Further, the p-type column region 4A and the p-type well region 63A of the edge termination region 40 are also formed in the same manner in the same process. The p-type impurity concentration in FIG. 10C has the highest impurity concentration in the injection region 92 shown in FIG. 9C, and the impurity concentration decreases as the distance from the injection region 92 increases. Here, the depth direction the n ^- is a direction from the surface of the type epitaxial layer 27 to the n ⁺ -type semiconductor substrate 1.

10A and 10B have the same cross-sectional shape of the p-shaped well region, but FIG. 10C has a different cross-sectional shape from those of FIGS. 10A and 10B. This is because the positions of the implantation regions formed by the ion implantation 22 are different. The subsequent manufacturing process will be described based on the state of FIG. 10A. Here, the depth direction of the n ^- and direction from -type epitaxial layer 27 surface (upper surface 100) in the n ⁺ -type semiconductor substrate 1. Further, "shallow" and "deep" indicate the depth in the depth direction.

Further, although the case where a photoresist is used as the ion implantation mask 21 has been described, for example, an oxide film may be used. When an oxide film is used, an opening is formed in the oxide film by using a photolithography technique and an etching technique. When an oxide film is used for the ion implantation mask 21, it is also possible to perform a heat treatment for diffusing the injected impurities with the oxide film attached.

Next, an ion implantation mask 65 having an opening for forming the ^p- type resurf region 12 is formed on the surface (upper surface 100) of ^{the n-type epitaxial layer 27 by photolithography technology.} For the ion implantation mask 65, for example, a photoresist is used. Using the ion implantation mask 65 as a mask, ion implantation of p-type impurities is performed. The p-type impurity is, for example, boron (B) or aluminum (Al). The state up to this point is shown in FIG.

Next, after removing the ion implantation mask 65, heat treatment is performed to diffuse the implanted p-type impurities ^{to form a p-} type resurf region 12 on the surface layer of ^{the n-type epitaxial layer 27.} Since the p ^- type resurf region 12 has a lower impurity concentration than the p-type well region 63A, the p ^- type resurf region 12 is not formed in the p-type well region 63A. p ^- bottom type RESURF region 12, n ^- is deeper than the boundary between the type epitaxial layer 27 and the n-type drift layer 2. Further, p ^- bottom type resurf region 12 may be formed shallower than the p-type column regions 4A and the p-type well region 63A of the boundary (dotted line). The state up to this point is shown in FIG.

Next, the oxide film 28 is formed on the upper surface 100. The oxide film 28 may be, for example, a LOCOS film. The thickness of the oxide film 28 in the active region 30 is formed to be thinner than the thick portion of the oxide film 28 formed on the outer peripheral side of the edge termination region 40. The oxide film 28 has a ^{thick portion formed on the upper surface of the n-} type epitaxial layer 27, and the bottom surface of the thick portion of the oxide film 28 is formed to a position deeper than the upper surface 100. The end portion of the thick portion of the oxide film 28 on the active region 30 side is formed so as to be ^{continuously covered with the p-type resurf region 12 from the end portion to a part of the lower surface.} Further, the other end of the thick portion of the oxide film 28 is formed so as to be ^{continuously covered with the n-type epitaxial layer 27 from the other end to a part of the lower surface.} The state up to this point is shown in FIG.

Next, a resist mask (not shown) having a predetermined opening is formed on the surface of the oxide film 28 by a photolithography technique. Next, using the resist mask as a mask, an opening is formed in the oxide film 28 by dry etching. Then the resist mask is removed, an oxide film 28 as a mask, anisotropic dry etching, n ^- -type n from the upper surface 100 of the epitaxial layer 27 ^- -type epitaxial layer 27 through the reach n-type drift layer 2 trenches Form 18A. The state up to this point is shown in FIG.

Next, isotropic etching and sacrificial oxidation are performed with the oxide film 28 attached. By this step, the damage of the trench 18A is removed and the bottom of the trench 18A is rounded. Either isotropic etching or sacrificial oxidation can be performed first. In addition, either isotropic etching or sacrificial oxidation may be performed. After that, the oxide film 28 in the thin portion used as a mask for forming the trench 18A is removed. At this time, the oxide film 28 and the sacrificial oxide film in the thin portion may be removed at the same time. The trench after the oxide film 28 is removed becomes the trench 18B. Since the oxide film 28 has a thin portion and a thick portion in the edge termination region 40, the entire surface is etched to remove the thin portion of the oxide film 28 to obtain the thickness of the edge termination region 40. Leaves a thick oxide film. The sacrificial oxide film (not shown) may be removed together with the thin portion of the oxide film 28. Further, the oxide film 28 may be left in the edge termination region 40 by removing the oxide film 28 by a photolithography technique and an etching technique. The oxide film (the portion where the thickness of the oxide film 28 is thick) remaining in the edge end region 40 becomes the field oxide film 13. The state up to this point is shown in FIG.

Next, ^{the surface (upper surface 100) of the n-} type epitaxial layer 27, the p ^- type resurf region 12 and the p-type well regions 63, 63A, and the gate insulating film 7 are formed along the inner wall of the trench 18B. The gate insulating film 7 may be formed by thermal oxidation at a temperature of about 1000 ° C. in an oxygen atmosphere. Further, the gate insulating film 7 may be formed by a method of depositing by a chemical reaction such as high temperature oxidation (HTO).

Next, a polycrystalline silicon layer doped with, for example, a phosphorus atom is provided on the gate insulating film 7. This polycrystalline silicon layer is formed so as to embed the inside of the trench 18B. This polycrystalline silicon layer is patterned by a photolithography technique and an etching technique to form a gate electrode 8 inside the trench 18B via a gate insulating film 7.

Further, the polycrystalline silicon layer formed in the edge termination region 40 may be selectively left as the field plate 29 and the channel stopper 62.

The field plate 29 includes the ^{upper surface of the gate insulating film 7 (insulating film 66A) and the field oxide film 13 formed on the p-} type resurf region 12, the p-type well region 63A, and the p-type base region 5A (upper surface 100). It is continuously formed on the upper surface of the active region 30 side of the above. The field plate 29 is electrically connected to the gate electrode 8 and also has a gate wiring function.

The channel stopper 62 is continuously formed on the upper surface of the field oxide film 13 on the outer peripheral side and the upper surface of the gate insulating film 7 (insulating film 66B) formed on the ^{n-type epitaxial layer 27 (upper surface 100).} The field plate 29 and the channel stopper 62 are separated on the field oxide film 13.

Next, ion implantation of p-type impurities to form p-type base regions 5, 5A from ^{the upper surface 100 of the n-} type epitaxial layer 27 (the surfaces of the p-type well regions 63 and 63A and the n ^{-type epitaxial layer 27) 22} I do. Examples of the p-type impurity include boron (B) and aluminum (Al). At this time, in ^{the edge termination region 40 on the n-} type epitaxial layer 27, the field plate 29, the channel stopper 62, and the field oxide film 13 function as masks. Therefore, p-type impurities are not injected into ^{the n-type epitaxial layer 27.} The gate electrode 8 also functions as a mask. The state up to this point is shown in FIG. Next, the gate insulating film 7 formed on the upper surface 100 is removed. The removal of the gate insulating film 7 does not have to be performed if the thickness of the gate insulating film 7 does not interfere with ion implantation for forming the ^{n + type source region 6 described later, for example, 500 Å or less.} good.

Next, by diffusing the p-type impurities by heat treatment, the p-type base regions 5, 5A are formed on the surface layers ^{of the n-} type epitaxial layer 27, the p-type well regions 63, 63A, and the p ^{-type resurf region 12.} Form. By this heat treatment, an insulating film 66C is formed so as to cover the upper surface of the gate electrode 8 made of a polycrystalline silicon layer formed so as to embed the trench 18B, the field plate 29, and the channel stopper 62.

The p-type base region 5 and the p-type well region 63 overlap, and the bottom surface of the p-type base region 5 is formed shallower than the bottom surface of the p-type well region 63. The p-type base region 5A and the p-type well region 63A overlap, and the bottom surface of the p-type base region 5A is formed shallower than the bottom surface of the p-type well region 63A.

The impurity concentrations in the p-type base region 5 and the p-type base region 5A may be equal. The impurity concentrations in the p-type well region 63 and the p-type well region 63A may be equal. The impurity concentration of the p-type base region 5 is higher than the impurity concentration of the p-type well region 63. Further, the impurity concentration in the p-type base region 5A is higher than the impurity concentration in the p-type well region 63A. The p-type base regions 5, 5A are formed so as to be in contact with the side wall of the trench 18B.

In the edge termination region 40, the oxide film 28, the field plate 29, and the channel stopper 62 function as masks, so that the n ^- type epitaxial layer 27 and the p ^- type resurf region 12 covered by these function as boron (B). ) Is not injected. As a result, even if heat treatment is performed to diffuse the p-type impurities forming the p-type base regions 5, 5A, the p-type base regions 5, 5A are formed in the n ^- type epitaxial layer 27 and the p ^- type resurf region 12. The p-type impurities that form the above do not diffuse. ^{Therefore, the n-} type epitaxial layer 27 and the p ^- type resurf region 12 remain in the edge termination region 40.

As described above, in the first manufacturing method, the p-type base region 5 in which the channel is formed is formed after the trench 18B is formed. The state up to this point is shown in FIG.

Next, a mask (not shown) having a desired opening is formed on the surface of the p-type base region 5 by a photolithography technique using, for example, a resist. Using this resist mask as a mask, n-type impurities are ion-implanted. By this ion implantation, an n-type impurity is implanted at a location where an ^{n +} -type source region 6 is formed in the surface layer of the p-type base region 5. The n-type impurities to be injected are arsenic (As), phosphorus (P) and the like.

Next, the ion implantation mask used to form the ^{n + type source region 6 is removed.} Further, on the surface of the p-type base region 5, for example, a resist is used to form a mask having a desired opening by photolithography technology, and an n ⁺ type source region 6 is formed on the surface layer of the p-type base region 5. A p-type impurity may be injected to form the ^{p ++} type contact region 14 in contact with the p ++ type contact region 14. Further, the p-type impurity forming the p ⁺⁺ type contact region 14A may be injected into the surface layer of the p-type base region 5A. ^{The n +} type source region 6 is not formed on the surface layer of the p-type base region 5A of the edge termination region 40.

Next, in order to ^{form the n +} type source region 6 and the p ⁺⁺ type contact regions 14, 14A, a heat treatment is performed to activate the injected impurities. Here, the difference between the heat treatment for activating and the heat treatment after ion implantation (heat treatment for diffusing the ion-implanted impurities) will be described. The ion-implanted semiconductor substrate, for example, the n-type drift layer 2 and the like, is damaged by the ion implantation and has defects. All of the ion-implanted impurities are in a state where they do not work as electric charges due to defects. The heat treatment for activating indicates a heat treatment in which a defect generated by ion implantation is recovered and the amount of electric charge (resistance) is adjusted to match the amount of impurities implanted. The heat treatment after ion implantation (the heat treatment for diffusing the ion-implanted impurities) recovers the defects generated by the ion implantation to obtain a charge amount (resistance) commensurate with the amount of the injected impurities, and further, a semiconductor substrate, for example, The heat treatment for diffusing impurities to an arbitrary position such as the n-type drift layer 2 is shown. Therefore, the heat treatment for activating has a smaller thermal history than the heat treatment after ion implantation (heat treatment for diffusing the ion-implanted impurities). A small heat history means, for example, that the heat treatment temperature is low or the heat treatment time is short, the heat treatment temperature is low, and the heat treatment time is short. Either of the order of ion implantation forming the n ⁺ type source region 6 and the p ⁺⁺ type contact regions 14 and 14A may come first. The state up to this point is shown in FIG.

Next, the interlayer insulating film 9 is formed on the entire upper surface of the surface (upper surface 100) of ^{the n-type epitaxial layer 27.} The interlayer insulating film 9 is formed through, for example, the gate insulating film 7, the gate electrode 8, the n ⁺ type source region 6, the p ⁺⁺ type contact region 14, the p type base region 5A, and the p ⁺⁺ type contact via the insulating film 66C. It is formed so as to cover the upper part of the region 14A, the field oxide film 13, the field plate 29 and the channel stopper 62. The interlayer insulating film 9 is formed of, for example, BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), or the like. Further, as the interlayer insulating film 9, for example, under the BPSG (between the BPSG and the gate electrode 8), either an HTO (High Temperature Oxide), an NSG (None-topped Silicate Glass) or a TEOS (tetraethoxysilane) film is formed. It may be formed to form a laminated film. The thickness of the interlayer insulating film 9 may be about 1 μm.

Next, the interlayer insulating film 9 and the insulating film 63C are patterned by a photolithography technique and an etching technique. In the active region 30, ^{a contact hole 64A is formed in which the surfaces of the n +} type source region 6 and the p ⁺⁺ type contact region 14 are exposed (the gate insulating film 7 and the gate formed along the inner wall of the trench 18B). The boundary of the interlayer insulating film 9 that covers the upper part of the electrode 8 is not shown (not shown). Further, in the edge end region 40, a contact hole 64B having an exposed surface ^{of the p ++ type contact region 14A is formed.} Further, in the edge termination region 40, a contact hole 64C having an exposed surface of the field plate 29 is formed. After that, heat treatment (reflow) is performed to flatten the interlayer insulating film 9. The state up to this point is shown in FIG.

Next, by sputtering, a metal film such as aluminum or an alloy containing aluminum as a main component (Al-Si, Al-Cu, Al-Si-Cu) is embedded in the contact holes 64A, 64B, 64C, and further, an interlayer insulating film is formed. A film is formed so as to continuously cover the upper surface of 9. Before forming the metal film, a contact hole is formed with a titanium film (Ti), a titanium nitride film (TiN), or a barrier metal (not shown) composed of a laminated film (for example, Ti / TiN) thereof by sputtering. It may be formed so as to be continuous with the inner wall of 64A, 64B, 64C and on the upper surface of the interlayer insulating film 9. After that, the source electrode 10, the metal gate runner 61, and the gate electrode pad (not shown) are formed by patterning the metal film and the barrier metal (not shown) by a photolithography technique and an etching technique. The barrier metal may be formed only in the contact holes 64A, 64B, 64C.

^{The source electrode 10 is electrically connected to the n +} type source region 6 and the p ⁺⁺ type contact region 14 whose surfaces are exposed in the contact hole 64A in the active region 30. ^{Further, the source electrode 10 is electrically connected to the p ++} type contact region 14A whose surface is exposed by the contact hole 64B in the edge termination region 40. Further, the metal gate runner 61 is electrically connected to the field plate 29 and the gate electrode 8 whose surfaces are exposed in the contact hole 64C. The gate electrode pad (not shown) is electrically connected to the metal gate runner 61 and the gate electrode 8. A tungsten plug or the like may be embedded in the contact holes 64A, 64B, 64C via a barrier metal.

Next, the back surface electrode 11 is formed on the back surface of the n ⁺ type semiconductor substrate 1 (the back surface of the semiconductor substrate) by sputtering. The back surface electrode 11 is, for example, nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy containing aluminum as a main component (Al—Si, Al—Cu, Al−. It may be formed from a metal film such as Si—Cu) or the like. Further, these laminated films (for example, Ti / Ni / Au, Al / Ti / Ni / Au, etc.) may be formed. After the back surface electrode 11 is formed into a film, heat treatment is performed ^{to form an ohmic contact between the n +} type semiconductor substrate 1 and the back surface electrode 11. As a result, the SJ-MOSFET 50 shown in FIG. 2A is completed.

In this way, the p-type column trench 25B is formed in the p-type column regions 4 and 4A, and the n ^- type epitaxial layer 27 having a lower impurity concentration than the n-type drift layer 2 which is the n-type column region 3 is formed. It is formed so as to be embedded in the trench 25 for a p-type column.

Further, ^{ion implantation of p-type impurities from the surface (upper surface 100) of the n-} type epitaxial layer 27 and heat treatment for diffusing the injected impurities are performed to perform p-type column regions 4, 4A and p-type well regions 63, 63A. Is forming. As a result, the p-type column region 4 can be formed without depositing the p-type epitaxial layer, so that the step of removing the p-type epitaxial layer at the edge termination region 40 becomes unnecessary. ^{Further, the surface of the n-} type epitaxial layer 27 embedded in the p-type column trench 25B does not require a step of flattening by using a CMP apparatus or the like. Therefore, the manufacturing cost can be reduced by reducing the number of manufacturing processes.

Further, the widths of the n-type column region 3 and the p-type column region 4 can be miniaturized as compared with the multi-stage epitaxial method. The on-resistance can be reduced. Further, since the p-type column region 4 is formed by ion implantation and diffusion by heat treatment, mutual diffusion occurs at the boundary between the p-type column region 4 and the n-type column region 3. Therefore, the conductive type changes more gently at the boundary between the p-type column region 4 and the n-type column region 3 than when the p-type column region and the n-type column region are formed by the conventional trench embedding method. As a result, the depletion layer is likely to spread, the electric field is relaxed, and the withstand voltage can be improved.

The SJ-MOSFET 50 shown in FIG. 2C is manufactured as follows. First, similarly to the SJ-MOSFET 50 shown in FIG. 2A, the same steps as in FIGS. 4 to 17 are performed to form the p-type base region 5. The contact plug 19 is formed in the steps 20 and 21 instead of the steps 18 and 19.

After the step described in FIG. 17, for example, a resist mask (not shown) having a desired opening is formed by a photolithography technique on the upper portion of the p-type base region 5 via an insulating film 66C. Ion implantation is performed using this resist mask to implant n-type impurities. An n-type impurity that forms an n ⁺ -type source region 6 is injected into the surface layer of the p-type base region 5 of the active region 30. Examples of the n-type impurity include arsenic (As) and phosphorus (P). After that, the resist mask is removed.

Next, for example, a resist mask (not shown) having a desired opening is formed by photolithography technology on the upper part of the p-type base regions 5 and 5A via the insulating film 66C. Ion implantation is performed using this resist mask to implant p-type impurities. ^{P-type impurities forming p ++} type contact regions 14, 14A are injected into the surface layer of the p-type base regions 5, 5A. The p- ^{type impurities forming the p ++} type contact regions 14 and 14A are injected at a position deeper than the n-type impurities forming the n ^{+ type source region 6.}

The p-type impurities forming the p ⁺⁺ type contact region 14A are injected into the surface layer of the p-type base region 5A of the edge termination region 40, and the n-type impurities forming the n ^{+ type source region 6 are not injected.} good.

Next, a heat treatment is performed to activate the impurities injected into ^{the n +} type source region 6 and the p ^{++ type contact region 14.} The heat treatment for activating the injected impurities has a smaller thermal history than the heat treatment for diffusing the injected impurities. The bottom surface of the p ⁺⁺ type contact region 14 is formed deeper than the bottom ^{surface of the n + type source region 6.} Further, ^{the order of ion implantation forming the n +} type source region 6 and the p ⁺⁺ type contact region 14 can be variously changed. The state up to this point is shown in FIG.

Next, the interlayer insulating film 9 is formed on the entire upper surface of the surface (upper surface 100) of ^{the n-type epitaxial layer 27.} The interlayer insulating film 9 is formed through, for example, the gate insulating film 7, the gate electrode 8, the n ⁺ type source region 6, the p ⁺⁺ type contact region 14, the p type base region 5A, and the p ⁺⁺ type contact via the insulating film 66C. It is formed so as to cover the upper part of the region 14A, the field oxide film 13, the field plate 29 and the channel stopper 62. The interlayer insulating film 9 is formed of, for example, BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), or the like. Further, the interlayer insulating film 9 forms, for example, either an HTO (High Temperature Oxide), an NSG (None-topped Silicate Glass) or a TEOS (tetraethoxysilane) film under the BPSG (between the BPSG and the gate electrode 8). It may be used as a laminated film. The thickness of the interlayer insulating film 9 may be about 1 μm.

Next, a resist mask (not shown) having an opening is formed on the surface of the interlayer insulating film 9 by, for example, a photolithography technique. Next, an opening is formed in the interlayer insulating film 9 and the insulating film 66C by anisotropic dry etching using a resist mask (the upper part of the gate insulating film 7 and the gate electrode 8 formed along the inner wall of the trench 18B). The boundary of the insulating film 66C covering the above is not shown). Next, recesses 67D, 67E, 67F are formed by anisotropic dry etching. The recesses 67D, 67E, 67F become the recesses 67A, 67B, 67C of FIG. 2C when the SJ-MOSFET 50 is completed.

A recess 67D deeper than the upper surface 100 is formed between the interlayer insulating film 9 and the insulating film 66C that cover the upper surface of the gate electrode 8 embedded in the trench 18B of the active region 30 and the adjacent trench 18B. ^{The n +} type source region 6 and the p ⁺⁺ type contact region 14 are in contact with (exposed) the side wall of the recess 67D. ^{A p ++} type contact region 14 is in contact (exposed) with the bottom of the recess 67D. The recess 67D is a contact hole 64D.

Similarly, it is embedded in the interlayer insulating film 9 and the insulating film 66C that cover the upper surface of the gate electrode 8 embedded in the trench 18B of the adjacent active regions 30, and in the trench 18B provided at the boundary between the active region 30 and the edge termination region 40. A recess 67D deeper than the upper surface 100 is also formed between the interlayer insulating film 9 and the insulating film 66C covering the upper surface of the gate electrode 8. ^{The n +} type source region 6 and the p ⁺⁺ type contact region 14 are in contact with (exposed) the side wall of the recess 67D. ^{A p ++} type contact region 14 is in contact (exposed) with the bottom of the recess 67D. The recess 67D is a contact hole 64D.

The interlayer insulating film 9 and the insulating film 66C provided so as to cover the upper surface of the gate electrode 8 embedded in the trench 18B provided at the boundary between the active region 30 and the edge termination region 40 and the interlayer insulation covering the field plate 29. A recess 67E deeper than the upper surface 100 is formed between the film 9 and the film 9. ^{A p ++} type contact region 14A is in contact (exposed) with the side wall and the bottom of the recess 67E. The recess 67E is a contact hole 64E.

A recess 67F is formed in the interlayer insulating film 9 and the insulating film 66C that cover the field plate 29 and the channel stopper 62. At the bottom of the recess 67F, the surface of the field oxide film 13 is exposed through the field plate 29. The field plate 29 and the field oxide film 13 are in contact with (exposed) the side wall of the recess 67F. The field oxide film 13 is in contact with (exposed) the bottom of the recess 67F. The recess 67F is a contact hole 64F. The field oxide film 13 may not be in contact with the side wall of the recess 67F.

After dry etching to form the contact holes 64D, 64E, 64F, the resist mask is removed and heat treatment (reflow) is performed to flatten the interlayer insulating film 9.

Next, by sputtering, a titanium film (Ti), a titanium nitride film (TiN), or a laminated film thereof (for example, Ti / TiN) is formed from the surface of the interlayer insulating film 9 along the inner walls of the contact holes 64D, 64E, 64F. Etc.) to form a barrier metal (not shown). Next, for example, a tungsten film (W) is formed so as to be embedded in the contact holes 64D, 64E, 64F via a barrier metal.

Next, the tungsten film is etched back to form the contact plug 19 in the contact holes 64D, 64E, 64F. The contact plug 19 formed in the contact hole 64D is electrically connected to the ^{n +} type source region 6 and the p ^{++ type contact region 14 via a barrier metal (not shown).} Further, the contact plug 19 formed in the contact hole 64E is electrically connected to the ^{p ++ type contact region 14A via a barrier metal (not shown).} Further, the contact plug 19 formed in the contact hole 64F is electrically connected to the field plate 29 via a barrier metal (not shown). The state up to this point is shown in FIG.

Next, by sputtering, a metal film such as aluminum or an alloy containing aluminum as a main component (Al—Si, Al—Cu, Al—Si—Cu) is formed on the upper surface of the SJ-MOSFET (superjunction semiconductor device) shown in FIG. Is formed. Next, the metal film is patterned by a photolithography technique and an etching technique to form a source electrode 10, a metal gate runner 61, and a gate electrode pad (not shown).

The source electrode 10 is electrically connected to a contact plug 19 which is electrically connected to ^{the p ++ type contact region 14.} Further, the metal gate runner 61 is electrically connected to the field plate 29. Further, the metal gate runner 61 is electrically connected to the gate electrode 8, and the gate electrode pad (not shown) is electrically connected to the metal gate runner 61 and the gate electrode 8.

Next, the back surface electrode 11 is formed on the back surface of the n ⁺ type semiconductor substrate 1 (the back surface of the semiconductor substrate) by sputtering. The back surface electrode 11 is, for example, nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy containing aluminum as a main component (Al—Si, Al—Cu, Al−. It may be formed from a metal film such as Si—Cu) or the like. Further, these laminated films (for example, Ti / Ni / Au, Al / Ti / Ni / Au, etc.) may be formed. After the back surface electrode 11 is formed into a film, heat treatment is performed ^{to form an ohmic contact between the n +} type semiconductor substrate 1 and the back surface electrode 11. As a result, the SJ-MOSFET 50 shown in FIG. 2C is completed.

The SJ-MOSFET 50 shown in FIG. 2C can also be manufactured as follows. First, similarly to the SJ-MOSFET 50 shown in FIG. 2A, the same steps from FIGS. 4 to 17 are performed to form the p-type base region 5. The contact plug 19 is formed in the steps 22 to 25 instead of the steps 18 and 19.

After performing the first manufacturing method of the SJ-MOSFET according to the embodiment up to FIG. 17, a mask having a desired opening on the surface of the p-type base region 5 by, for example, a resist and a photolithography technique. (Not shown) is formed. Using this resist mask as a mask, n-type impurities are ion-implanted. By this ion implantation, an n-type impurity is implanted at a location where an ^{n +} -type source region 6 is formed in the surface layer of the p-type base region 5. The n-type impurities to be injected are arsenic (As), phosphorus (P) and the like. It is not necessary to inject the n-type impurities forming the n ⁺ -type source region 6 into the surface layer of the p-type base region 5A of the edge termination region 40. Next, the ion implantation mask used to form the ^{n + type source region 6 is removed.} Next, ^{in order to form the n +} type source region 6, a heat treatment is performed to activate the injected impurities. The state up to this point is shown in FIG.

Next, the interlayer insulating film 9 is formed on the entire upper surface of the surface (upper surface 100) of ^{the n-type epitaxial layer 27.} The interlayer insulating film 9 passes through the insulating film 66C, for example, the gate insulating film 7, the gate electrode 8, the n ⁺ type source region 6, the p ⁺⁺ type contact region 14, the p type base region 5A, and the p ⁺⁺ type contact region. It is formed so as to cover the upper part of 14A, the field oxide film 13, the field plate 29 and the channel stopper 62. The interlayer insulating film 9 is formed of, for example, BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), or the like. Further, as the interlayer insulating film 9, for example, under the BPSG (between the BPSG and the gate electrode 8), either an HTO (High Temperature Oxide), an NSG (None-topped Silicate Glass) or a TEOS (tetraethoxysilane) film is formed. It may be formed to form a laminated film. The thickness of the interlayer insulating film 9 may be about 1 μm. The state up to this point is shown in FIG.

Next, a resist mask (not shown) having an opening is formed on the surface of the interlayer insulating film 9 by, for example, a photolithography technique. Next, an opening is formed in the interlayer insulating film 9 and the insulating film 66C by anisotropic dry etching using a resist mask (the upper part of the gate insulating film 7 and the gate electrode 8 formed along the inner wall of the trench 18B). The boundary of the insulating film 66C covering the above is not shown). Next, recesses 67D, 67E, 67F are formed by anisotropic dry etching. The recesses 67D, 67E, 67F become the recesses 67A, 67B, 67C of FIG. 2C when the SJ-MOSFET 50 is completed.

A recess 67D deeper than the upper surface 100 is formed between the interlayer insulating film 9 and the insulating film 66C that cover the upper surface of the gate electrode 8 embedded in the trench 18B of the active region 30 and the adjacent trench 18B. ^{The n +} type source region 6 and the p-type base region 5 are in contact with (exposed) the side wall of the recess 67D. The p-type base region 5 is in contact with (exposed) the bottom of the recess 67D. The recess 67D is a contact hole 64D.

Similarly, it is embedded in the interlayer insulating film 9 and the insulating film 66C that cover the upper surface of the gate electrode 8 embedded in the trench 18B of the adjacent active regions 30, and in the trench 18B provided at the boundary between the active region 30 and the edge termination region 40. A recess 67D deeper than the upper surface 100 is also formed between the interlayer insulating film 9 and the insulating film 66C covering the upper surface of the gate electrode 8. ^{The n +} type source region 6 and the p-type base region 5 are in contact with (exposed) the side wall of the recess 67D. The p-type base region 5 is in contact with (exposed) the bottom of the recess 67D. The recess 67D is a contact hole 64D.

The interlayer insulating film 9 and the insulating film 66C provided so as to cover the upper surface of the gate electrode 8 embedded in the trench 18B provided at the boundary between the active region 30 and the edge termination region 40 and the interlayer insulation covering the field plate 29. A recess 67E deeper than the upper surface 100 is formed between the film 9 and the film 9. The p-type base region 5A is in contact (exposed) with the side wall and the bottom of the recess 67E. The recess 67E is a contact hole 64E.

A recess 67F is formed in the interlayer insulating film 9 and the insulating film 66C that cover the field plate 29 and the channel stopper 62. At the bottom of the recess 67F, the surface of the field oxide film 13 is exposed through the field plate 29. The field plate 29 and the field oxide film 13 are in contact with (exposed) the side wall of the recess 67F. The field oxide film 13 is in contact with (exposed) the bottom of the recess 67F. The recess 67F is a contact hole 64F. The field oxide film 13 may not be in contact with the side wall of the recess 67F.

Next, ion implantation 22 is performed using the interlayer insulating film 9 as a mask, and p-type impurities are injected. The bottom of the recess 67D and the side surfaces and bottom of the recess 67E are injected with p-type impurities that form ^{p ++ -type contact regions 14, 14A on the surface layer of the p-type base regions 5, 5A.} The p-type impurities forming the p ⁺⁺ type contact region 14A are injected into the surface layer of the p-type base region 5A of the edge termination region 40, and the n-type impurities forming the n ^{+ type source region 6 are not injected.} good. The state up to this point is shown in FIG.

Next, heat treatment (reflow) is performed to flatten the interlayer insulating film 9. Further, the p-type impurities forming ^{the p ++} type contact regions 14, 14A in which the interlayer insulating film 9 is injected at the same time as flattening may be activated.

Next, by sputtering, a titanium film (Ti), a titanium nitride film (TiN), or a laminated film thereof (for example, Ti / TiN) is formed from the surface of the interlayer insulating film 9 along the inner walls of the contact holes 64D, 64E, 64F. Etc.) to form a barrier metal (not shown). Next, for example, a tungsten film (W) is formed so as to be embedded in the contact holes 64D, 64E, 64F via a barrier metal.

Next, the tungsten film is etched back to form the contact plug 19 in the contact holes 64D, 64E, 64F. The contact plug 19 formed in the contact hole 64D is electrically connected to the ^{n +} type source region 6 and the p ^{++ type contact region 14 via a barrier metal (not shown).} Further, the contact plug 19 formed in the contact hole 64E is electrically connected to the ^{p ++ type contact region 14A via a barrier metal (not shown).} Further, the contact plug 19 formed in the contact hole 64F is electrically connected to the field plate 29 via a barrier metal (not shown). The state up to this point is shown in FIG.

Next, by sputtering, a metal film such as aluminum or an alloy containing aluminum as a main component (Al-Si, Al-Cu, Al-Si-Cu) is formed on the upper surface of the SJ-MOSFET (superjunction semiconductor device) shown in FIG. Is formed. Next, the metal film is patterned by a photolithography technique and an etching technique to form a source electrode 10, a metal gate runner 61, and a gate electrode pad (not shown).

The source electrode 10 is electrically connected to a contact plug 19 which is electrically connected to ^{the p ++ type contact region 14.} Further, the metal gate runner 61 is electrically connected to the field plate 29. Further, the metal gate runner 61 is electrically connected to the gate electrode 8, and the gate electrode pad (not shown) is electrically connected to the metal gate runner 61 and the gate electrode 8.

Next, the back surface electrode 11 is formed on the back surface of the n ⁺ type semiconductor substrate 1 (the back surface of the semiconductor substrate) by sputtering. The back surface electrode 11 is, for example, nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy containing aluminum as a main component (Al—Si, Al—Cu, Al−. It may be formed from a metal film such as Si—Cu) or the like. Further, these laminated films (for example, Ti / Ni / Au, Al / Ti / Ni / Au, etc.) may be formed. After the back surface electrode 11 is formed into a film, heat treatment is performed ^{to form an ohmic contact between the n +} type semiconductor substrate 1 and the back surface electrode 11. As a result, the SJ-MOSFET 50 shown in FIG. 2C is completed.

Next, a second manufacturing method different from the first manufacturing method shown in FIGS. 4 to 21 will be described. 26 to 30 are cross-sectional views showing a state in the middle of manufacturing the SJ-MOSFET according to the second embodiment according to the second manufacturing method. The second manufacturing method is the manufacturing method of the SJ-MOSFET shown in FIG. 2D. Since the manufacturing method of the edge termination region 40 is the same as that of the first manufacturing method, FIGS. 26 to 30 show cross-sectional views of the active region 30. In the second manufacturing method, the same steps as those in the first manufacturing method are performed from the steps shown in FIGS. 4 to 8 ^{to form the n-} type epitaxial layer 27.

The difference between the second manufacturing method and the first manufacturing method is the implantation region 93 formed by the ion implantation 22 in ^{the n-type epitaxial layer 27.} Specifically, in the section D1, ion implantation 22 is performed on the entire surface of a predetermined region excluding a part of the edge termination region 40 to form the implantation region 93. The predetermined region is on the active region 30 side from the opening of the ion implantation mask 21 forming the p-type column region 4A shown in FIG. 9A.

Here, the depth indicates the direction from the upper surface 100 (surface) ^{of the n-} type epitaxial layer 27 toward the front surface of the ^{n + type semiconductor substrate 1.} The injection depth is the depth at which ^{impurities are injected from the upper surface 100 (surface) of the n-} type epitaxial layer 27 (the peak position of the impurity concentration distribution).

Further, the implantation region 93 formed by performing the ion implantation 22 indicates a region (peak position of the impurity concentration distribution) into which impurities are implanted from the upper surface 100. Implantation depth, n ^- from the upper surface 100 of the type epitaxial layer 27 (surface) n ^- indicating the depth of up to implanted region 93 formed in the type epitaxial layer 27.

Further, ^{the section D1 between the surface of the n-} type epitaxial layer 27 (upper surface 100) and the surface of the n-type drift layer 2 ( ^{thickness T1 of the flat portion of the n-} type epitaxial layer 27) is set as the n-type drift layer. The section D2 is between the surface of 2 and the bottom of the p-type column trench 25B (depth of the p-type column trench 25B).

After the step of forming the ^n- type epitaxial layer 27 shown in FIG. 8, ion implantation 22 of the p-type impurity is performed from the surface ^{of the n-type epitaxial layer 27 into a predetermined region.} Examples of the p-type impurity include boron (B) and aluminum (Al). In the second manufacturing method, ^{an ion implantation mask is performed in a predetermined region of the n-} type epitaxial layer 27 to form a p-type column region 4A of the edge termination region 40 in which ion implantation is not performed as shown in FIG. 9A. It is not necessary to newly form an ion implantation mask in the region on the outer peripheral side of the opening of 21. The oxide film 23 shown in FIG. 6 may be left as a mask in the outer peripheral region where the ion implantation 22 is not performed to prevent the p-type impurities from being implanted. Further, in the region on the outer peripheral side, an ion implantation mask 21 may be formed on the surface (upper surface 100) of ^{the n-type epitaxial layer 27 with a resist or the like to perform ion implantation 22.}

The implantation region 93 formed by the ion implantation 22 is formed in the section D1. If the interval D1 is 1.0μm a section D2 in 0.8 [mu] m, n ^- a depth from the surface of the type epitaxial layer 27 to the injection region 93 to 0.4 .mu.m. The section D1 (thickness T1) may be 0.5 μm or more and 1.0 μm or less. The injection depth from the surface (upper surface 100) of the n ^- type epitaxial layer 27 to the injection region 93 may be 0.2 μm or more and 1.0 μm or less. Further, the section D2 may be 0.5 μm or more and 2.0 μm or less. The injection region 93 may be formed at the boundary between the section D1 and the section D2. The state up to this point is shown in FIG.

Next, the mask (not shown) used in the ion implantation 22, for example, the oxide film 23, the ion implantation mask 21 formed of the resist, and the like are removed, and then heat treatment is performed to diffuse the p-type impurities. As a result, the p-type column region 4 and the p-type well region 63 are formed.

Here, the n ^- type epitaxial layer 27 is formed with an impurity concentration lower than that of the n-type drift layer 2. The ion implantation 22 of the p-type impurity and the subsequent heat treatment ^{facilitate the spread of the p-type impurity from the implantation region 93 to the n-} type epitaxial layer 27.

An n-type column region 3 is formed between the adjacent p-type column regions 4 and a parallel pn region 20 is formed. The p-type well region 63 is formed on the entire surface of a predetermined region that has been ion-implanted 22.

The impurity concentrations in the p-type well region 63 and the p-type column region 4 are the highest in the injection region 93, and decrease in the depth direction as the distance from the injection region 93 increases. Here, the depth direction the n ^- is a direction from the surface of the type epitaxial layer 27 to the n ⁺ -type semiconductor substrate 1.

An oxide film 28 is formed on the surface (upper surface 100) of the p-type well region 63 after the heat treatment for diffusing the p-type impurities after the ion implantation 22. The oxide film 28 may be formed by heat treatment for diffusing p-type impurities after ion implantation 22.

When heat treatment is performed, the shape of the boundary between the p-type column region 4 and the p-type well region 63 (the corner between the p-type column trench 25B and the surface of the n-type drift layer 2) is rounded due to the diffusion of impurities. The shape to be held may be formed. The state up to this point is shown in FIG.

As described above, in the second manufacturing method, before forming the trench 18A described later, ion implantation 22 is performed on the entire surface of a predetermined region excluding a part of the edge termination region 40 to form the implantation region 93. Heat treatment is performed after the ion implantation 22 to form the p-type column region 4 and the p-type well region 63.

The impurity concentration of n ^- -type epitaxial layer 27 is formed at a lower impurity concentration than the n-type drift layer 2. n ^- is large density difference of the impurity concentration in the type epitaxial layer 27 and the n-type drift layer 2, p-type impurities implanted in the ion implantation 22 is difficult to diffuse the n-type drift layer 2, n ^- the type epitaxial layer 27 It becomes easy to spread.

Since the p-type well region 63 is formed on the entire surface of the predetermined region to which the ion implantation 22 has been implanted and is in contact with the side wall of the trench 18B, it has the same function as the p-type base region 5 formed in a later step. Since the p-type impurities injected by the ion implantation 22 are difficult to diffuse into the n-type drift layer 2, it is possible to prevent the channel length from expanding due to the heat treatment.

Next, a photoresist mask (not shown) having a predetermined opening is formed on the surface of the oxide film 28 by a photolithography technique. Next, using a photoresist mask, an opening is formed in the oxide film 28 by, for example, anisotropic dry etching. Next, the photoresist mask (not shown) is removed, and the oxide film 28 is used as a mask to penetrate the p-type well region 63 by anisotropic dry etching to penetrate the n-type drift layer 2 (n-type column region 3). Form a trench 18A that reaches. In the second manufacturing method, the p-type well region 63 is in contact with the side wall of the trench 18A. The state up to this point is shown in FIG.

Next, isotropic etching and sacrificial oxidation are performed with the oxide film 28 attached. By this step, the damage of the trench 18A is removed and the bottom of the trench 18A is rounded. Either isotropic etching or sacrificial oxidation can be performed first. In addition, either isotropic etching or sacrificial oxidation may be performed. After that, the oxide film 28 is removed. The sacrificial oxide film (not shown) may be removed at the same time as the oxide film 28.

Next, the gate insulating film 7 is formed along the surface of the p-type well region 63 ( ^{upper surface 100 of the n-} type epitaxial layer 27) and the inner wall of the trench 18B. The gate insulating film 7 may be formed by thermal oxidation at a temperature of about 1000 ° C. in an oxygen atmosphere. Further, the gate insulating film 7 may be formed by a method of depositing by a chemical reaction such as high temperature oxidation (HTO).

Next, a polycrystalline silicon layer doped with, for example, a phosphorus atom is provided on the gate insulating film 7. This polycrystalline silicon layer is formed so as to embed the inside of the trench 18B. This polycrystalline silicon layer is patterned by a photolithography technique and an etching technique to form a gate electrode 8 inside the trench 18B via a gate insulating film 7. The p-shaped well region 63 is in contact with the side wall of the trench 18B.

Next, ion implantation 22 of p-type impurities such as boron (B) for forming the p-type base region 5 is performed from the surface of the p-type well region 63 ( ^{upper surface 100 of the n-type epitaxial layer 27).} In the active region 30, the gate electrode 8 functions as a mask. The state up to this point is shown in FIG.

Next, heat treatment is performed to diffuse the p-type impurities injected by ion implantation 22 to form the p-type base region 5. The p-type base region 5 is formed on the surface layer of the p-type well region 63, and the impurity concentration of the p-type base region 5 is higher than the impurity concentration of the p-type well region 63. In the depth direction, the bottom surface of the p-type base region 5 is formed shallower than the bottom surface of the p-type well region 63. The p-type base region 5 and the p-type well region 63 are formed so as to be in contact with the side wall of the trench 18B.

Similarly, on the side wall of the trench 18B (not shown) formed at the boundary between the active region 30 and the edge termination region 40, the p-type base region 5 and the p-type well region 63 are in contact with the active region 30 side, and the edge termination The p-type base region 5A and the p-type well region 63A are in contact with the region 40.

When forming the trench 18B after forming the p-type well region 63, a step of applying heat to the SJ-MOSFET (superjunction semiconductor device) 50, for example, forming an oxide film 28, a sacrificial oxide film, and a gate insulating film 7. As a result, the p-type impurities in the p-type well region 63 may diffuse and the variation in the gate threshold voltage may increase. Therefore, the gate threshold voltage can be stabilized by forming the p-type base region 5 after the trench 18B is formed (after the gate electrode 8 is formed). The state up to this point is shown in FIG.

When the ion implantation 22 of the p-type impurity forming the p-type base region 5 is not performed, the number of ion implantations can be reduced and the manufacturing cost can be reduced. After that, the SJ-MOSFET 50 shown in FIG. 2D is completed by performing the steps after the step of forming the ^{n +} type source region 6 in the same manner as in the first manufacturing method. In the second manufacturing method, the p-type well region 63 is different from the first manufacturing method, and the p-type well region 63 is in contact with the side wall of the trench 18B.

Next, a third manufacturing method different from the second manufacturing method shown in FIGS. 26 to 30 will be described. 31 to 39 are cross-sectional views showing a state in the middle of manufacturing the SJ-MOSFET according to the third embodiment according to the third manufacturing method. The third manufacturing method is the manufacturing method of the SJ-MOSFET shown in FIG. 2B. In the third production method, first, the same steps as those in the first production method are performed up to the steps shown in FIGS. 4 to 8, 9C, and 10C, and the p-type impurities are diffused by heat treatment.

The third manufacturing method differs from the first manufacturing method in that the p-type column region is obtained by implanting the second conductive impurity into the region ^{in which the n-type epitaxial layer 27 is embedded in the p-type column trench 25B.} It is a point that forms 4, 4A.

Next, an ion implantation mask 65 having an opening for forming the ^p- type resurf region 12 is formed on the surface (upper surface 100) of ^{the n-type epitaxial layer 27 by photolithography technology.} For the ion implantation mask 65, for example, a photoresist is used. Using the ion implantation mask 65 as a mask, ion implantation of p-type impurities is performed. The p-type impurity is, for example, boron (B) or aluminum (Al). The state up to this point is shown in FIG.

Next, after removing the ion implantation mask 65, heat treatment is performed to diffuse the implanted p-type impurities ^{to form a p-} type resurf region 12 on the surface layer of ^{the n-type epitaxial layer 27.} Since the p ^- type resurf region 12 has a lower impurity concentration than the p-type well region 63A, the p ^- type resurf region 12 is not formed in the p-type well region 63A. p ^- bottom type RESURF region 12, n ^- is deeper than the boundary between the type epitaxial layer 27 and the n-type drift layer 2. Further, p ^- bottom type RESURF region 12, p-type column regions 4A and the p-type well region 63A of the boundary may be even shallower formed deeper than (dotted line). The state up to this point is shown in FIG.

Next, the oxide film 28 is formed on the upper surface 100. The oxide film 28 may be, for example, a LOCOS film. The thickness of the oxide film 28 in the active region 30 is formed to be thinner than the thick portion of the oxide film 28 formed on the outer peripheral side of the edge termination region 40. The oxide film 28 has a ^{thick portion formed on the upper surface of the n-} type epitaxial layer 27, and the bottom surface of the thick portion of the oxide film 28 is formed to a position deeper than the upper surface 100. The end portion of the thick portion of the oxide film 28 on the active region 30 side is formed so as to be ^{continuously covered with the p-type resurf region 12 from the end portion to a part of the lower surface.} Further, the other end of the thick portion of the oxide film 28 is formed so as to be ^{continuously covered with the n-type epitaxial layer 27 from the other end to a part of the lower surface.} The state up to this point is shown in FIG.

Next, a resist mask (not shown) having a predetermined opening is formed on the surface of the oxide film 28 by a photolithography technique. Next, using the resist mask as a mask, an opening is formed in the oxide film 28 by dry etching. Then the resist mask is removed, an oxide film 28 as a mask, anisotropic dry etching, n ^- -type n from the upper surface 100 of the epitaxial layer 27 ^- -type epitaxial layer 27 through the reach n-type drift layer 2 trenches Form 18A. The state up to this point is shown in FIG.

Next, isotropic etching and sacrificial oxidation are performed with the oxide film 28 attached. By this step, the damage of the trench 18A is removed and the bottom of the trench 18A is rounded. Either isotropic etching or sacrificial oxidation can be performed first. In addition, either isotropic etching or sacrificial oxidation may be performed. After that, the oxide film 28 in the thin portion used as a mask for forming the trench 18A is removed. At this time, the oxide film 28 and the sacrificial oxide film in the thin portion may be removed at the same time. The trench after the oxide film 28 is removed becomes the trench 18B. Since the oxide film 28 has a thin portion and a thick portion in the edge termination region 40, the entire surface is etched to remove the thin portion of the oxide film 28 to obtain the thickness of the edge termination region 40. Leaves a thick oxide film. The sacrificial oxide film (not shown) may be removed together with the thin portion of the oxide film 28. Further, the oxide film 28 may be left in the edge termination region 40 by removing the oxide film 28 by a photolithography technique and an etching technique. The oxide film (the portion where the thickness of the oxide film 28 is thick) remaining in the edge end region 40 becomes the field oxide film 13. The state up to this point is shown in FIG.

Next, ^{the surface (upper surface 100) of the n-} type epitaxial layer 27, the p ^- type resurf region 12 and the p-type well regions 63, 63A, and the gate insulating film 7 are formed along the inner wall of the trench 18B. The gate insulating film 7 may be formed by thermal oxidation at a temperature of about 1000 ° C. in an oxygen atmosphere. Further, the gate insulating film 7 may be formed by a method of depositing by a chemical reaction such as high temperature oxidation (HTO).

Next, a polycrystalline silicon layer doped with, for example, a phosphorus atom is provided on the gate insulating film 7. This polycrystalline silicon layer is formed so as to embed the inside of the trench 18B. This polycrystalline silicon layer is patterned by a photolithography technique and an etching technique to form a gate electrode 8 inside the trench 18B via a gate insulating film 7.

Further, the polycrystalline silicon layer formed in the edge termination region 40 may be selectively left as the field plate 29 and the channel stopper 62.

The field plate 29 includes the ^{upper surface of the gate insulating film 7 (insulating film 66A) and the field oxide film 13 formed on the p-} type resurf region 12, the p-type well region 63A, and the p-type base region 5A (upper surface 100). It is continuously formed on the upper surface of the active region 30 side of the above. The field plate 29 is electrically connected to the gate electrode 8 and also has a gate wiring function.

The channel stopper 62 is continuously formed on the upper surface of the field oxide film 13 on the outer peripheral side and the upper surface of the gate insulating film 7 (insulating film 66B) formed on the ^{n-type epitaxial layer 27 (upper surface 100).} The field plate 29 and the channel stopper 62 are separated on the field oxide film 13.

Next, ion implantation of p-type impurities to form p-type base regions 5, 5A from ^{the upper surface 100 of the n-} type epitaxial layer 27 (the surfaces of the p-type well regions 63 and 63A and the n ^{-type epitaxial layer 27) 22} I do. Examples of the p-type impurity include boron (B) and aluminum (Al). At this time, in ^{the edge termination region 40 on the n-} type epitaxial layer 27, the field plate 29, the channel stopper 62, and the field oxide film 13 function as masks. Therefore, p-type impurities are not injected into ^{the n-type epitaxial layer 27.} The gate electrode 8 also functions as a mask. The state up to this point is shown in FIG.

Next, the gate insulating film 7 formed on the upper surface 100 is removed. The removal of the gate insulating film 7 does not have to be performed if the thickness of the gate insulating film 7 does not interfere with ion implantation for forming the ^{n + type source region 6 described later, for example, 500 Å or less.} good.

Next, by diffusing the p-type impurities by heat treatment, the p-type base regions 5, 5A are formed on the surface layers ^{of the n-} type epitaxial layer 27, the p-type well regions 63, 63A, and the p ^{-type resurf region 12.} Form. By this heat treatment, an insulating film 66C is formed so as to cover the upper surface of the gate electrode 8 made of a polycrystalline silicon layer formed so as to embed the trench 18B, the field plate 29, and the channel stopper 62.

The p-type base region 5 and the p-type well region 63 overlap, and the bottom surface of the p-type base region 5 is formed shallower than the bottom surface of the p-type well region 63. The p-type base region 5A and the p-type well region 63A overlap, and the bottom surface of the p-type base region 5A is formed shallower than the bottom surface of the p-type well region 63A.

The impurity concentrations in the p-type base region 5 and the p-type base region 5A may be equal. The impurity concentrations in the p-type well region 63 and the p-type well region 63A may be equal. The impurity concentration of the p-type base region 5 is higher than the impurity concentration of the p-type well region 63. Further, the impurity concentration in the p-type base region 5A is higher than the impurity concentration in the p-type well region 63A. The p-type base regions 5, 5A are formed so as to be in contact with the side wall of the trench 18B.

In the edge termination region 40, the oxide film 28, the field plate 29, and the channel stopper 62 function as masks, so that the n ^- type epitaxial layer 27 and the p ^- type resurf region 12 covered by these function as boron (B). ) Is not injected. As a result, even if heat treatment is performed to diffuse the p-type impurities forming the p-type base regions 5, 5A, the p-type base regions 5, 5A are formed in the n ^- type epitaxial layer 27 and the p ^- type resurf region 12. The p-type impurities that form the above do not diffuse. ^{Therefore, the n-} type epitaxial layer 27 and the p ^- type resurf region 12 remain in the edge termination region 40.

As described above, in the third manufacturing method, the p-type base region 5 in which the channel is formed is formed after the trench 18B is formed. The state up to this point is shown in FIG. 37.

Next, a mask (not shown) having a desired opening is formed on the surface of the p-type base region 5 by a photolithography technique using, for example, a resist. Using this resist mask as a mask, n-type impurities are ion-implanted. By this ion implantation, an n-type impurity is implanted at a location where an ^{n +} -type source region 6 is formed in the surface layer of the p-type base region 5. The n-type impurities to be injected are arsenic (As), phosphorus (P) and the like.

Next, the ion implantation mask used to form the ^{n + type source region 6 is removed.} Further, on the surface of the p-type base region 5, for example, a resist is used to form a mask having a desired opening by photolithography technology, and an n ⁺ type source region 6 is formed on the surface layer of the p-type base region 5. A p-type impurity may be injected to form the ^{p ++} type contact region 14 in contact with the p ++ type contact region 14. Further, the p-type impurity forming the p ⁺⁺ type contact region 14A may be injected into the surface layer of the p-type base region 5A. ^{The n +} type source region 6 is not formed on the surface layer of the p-type base region 5A of the edge termination region 40.

Next, a heat treatment is performed to activate the impurities injected into ^{the n +} type source region 6 and the p ^{++ type contact regions 14, 14A.} The heat treatment for activating the injected impurities has a smaller thermal history than the heat treatment for diffusing the injected impurities. Either of the order of ion implantation forming the n ⁺ type source region 6 and the p ⁺⁺ type contact regions 14 and 14A may come first. The state up to this point is shown in FIG.

Next, the interlayer insulating film 9 is formed on the entire upper surface of the surface (upper surface 100) of ^{the n-type epitaxial layer 27.} The interlayer insulating film 9 is formed through, for example, the gate insulating film 7, the gate electrode 8, the n ⁺ type source region 6, the p ⁺⁺ type contact region 14, the p type base region 5A, and the p ⁺⁺ type contact via the insulating film 66C. It is formed so as to cover the region 14A, the field oxide film 13, the field plate 29, and the channel stopper 62. The interlayer insulating film 9 is formed of, for example, BPSG, PSG, or the like. Further, the interlayer insulating film 9 may be formed as a laminated film by forming either an HTO, NSG or TEOS film under the BPSG (between the BPSG and the gate electrode 8), for example. The thickness of the interlayer insulating film 9 may be about 1 μm.

Next, the interlayer insulating film 9 and the insulating film 66C are patterned by a photolithography technique and an etching technique. In the active region 30, ^{a contact hole 64A is formed in which the surfaces of the n +} type source region 6 and the p ⁺⁺ type contact region 14 are exposed (the gate insulating film 7 and the gate formed along the inner wall of the trench 18B). The boundary of the interlayer insulating film 9 that covers the upper part of the electrode 8 is not shown (not shown). Further, in the edge end region 40, a contact hole 64B having an exposed surface ^{of the p ++ type contact region 14A is formed.} Further, in the edge termination region 40, a contact hole 64C having an exposed surface of the field plate 29 is formed. After that, heat treatment (reflow) is performed to flatten the interlayer insulating film 9. The state up to this point is shown in FIG.

Next, by sputtering, a metal film such as aluminum or an alloy containing aluminum as a main component (Al-Si, Al-Cu, Al-Si-Cu) is embedded in the contact holes 64A, 64B, 64C, and further, an interlayer insulating film is formed. A film is formed so as to continuously cover the upper surface of 9. Before forming the metal film, a contact hole is formed with a titanium film (Ti), a titanium nitride film (TiN), or a barrier metal (not shown) composed of a laminated film (for example, Ti / TiN) thereof by sputtering. It may be formed so as to be continuous with the inner wall of 64A, 64B, 64C and on the upper surface of the interlayer insulating film 9. After that, the source electrode 10, the metal gate runner 61, and the gate electrode pad (not shown) are formed by patterning the metal film and the barrier metal (not shown) by a photolithography technique and an etching technique. The barrier metal may be formed only in the contact holes 64A, 64B, 64C.

^{The source electrode 10 is electrically connected to the n +} type source region 6 and the p ⁺⁺ type contact region 14 whose surfaces are exposed in the contact hole 64A in the active region 30. ^{Further, the source electrode 10 is electrically connected to the p ++} type contact region 14A whose surface is exposed by the contact hole 64B in the edge termination region 40. Further, the metal gate runner 61 is electrically connected to the field plate 29 and the gate electrode 8 whose surfaces are exposed in the contact hole 64C. The gate electrode pad (not shown) is electrically connected to the metal gate runner 61 and the gate electrode 8. A tungsten plug or the like may be embedded in the contact holes 64A, 64B, 64C via a barrier metal. The contact holes 64A, 64B, 64C may be contact holes provided with recesses as in the first manufacturing method shown in FIG.

Next, the back surface electrode 11 is formed on the back surface of the n ⁺ type semiconductor substrate 1 (the back surface of the semiconductor substrate) by sputtering. The back surface electrode 11 is, for example, nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy containing aluminum as a main component (Al—Si, Al—Cu, Al−. It may be formed from a metal film such as Si—Cu) or the like. Further, these laminated films (for example, Ti / Ni / Au, Al / Ti / Ni / Au, etc.) may be formed. After the back surface electrode 11 is formed into a film, heat treatment is performed ^{to form an ohmic contact between the n +} type semiconductor substrate 1 and the back surface electrode 11. As a result, the SJ-MOSFET 50 shown in FIG. 2B is completed.

In this way, since the ion implantation of the second conductive type impurity is performed only in the region ^{where the n-} type epitaxial layer 27 is embedded in the trench 25B for the p-type column, the p-type well regions 63 and 63A are not formed. Become.

As described above, according to the embodiment, the n ^- type epitaxial layer is provided in the edge termination region 40, and the field oxide film 13 is provided on the surface of the ^{n-type epitaxial layer 27.} The n ^- type epitaxial layer 27 improves the withstand voltage of the SJ-MOSFET 50 by extending the depletion layer extending from the pn junction between the ^n- type epitaxial layer 27 and the p ^{- type resurf region 12 to the n-type epitaxial layer 27.} Can be done.

Further, in another embodiment, the width of the n-type column region 3B and the width of the p-type column region 4B in the edge termination region 40 are larger than the width of the n-type column region 3 and the width of the p-type column region 4 of the active region 30. By providing the narrowed parallel pn structure 20B, the depletion layer is likely to spread in the edge termination region 40, and the withstand voltage of the edge termination region 40 can be made higher than the withstand voltage of the active region 30.

Further, since the n ^- type epitaxial layer 27 has a low impurity concentration, it becomes easy to control the diffusion of the p-type well regions 63 and 63A and the p-type base regions 5 and 5A, and it is possible to suppress variations in the gate threshold voltage Vth.

Further, since the p-type column region 4 can be formed without depositing the p-type epitaxial layer as in the conventional trench embedding method, the p-type epitaxial layer on the surface is removed by using a CMP device or the like, and the p-type epitaxial layer is removed. It is not necessary to form an n-type epitaxial layer on the surface after removal. Further, the surface portion in which the p-type column trench 25B is embedded does not require a step of flattening by using a CMP device or the like. Therefore, the SJ structure can be easily formed, and the manufacturing cost can be reduced.

In the present invention, the case where the MOS gate structure is configured on the first main surface of the silicon substrate has been described as an example, but the present invention is not limited to this, and the type of semiconductor (for example, silicon carbide (SiC), etc.) and the substrate main The surface orientation of the surface can be changed in various ways. Further, in the embodiment of the present invention, the trench type MOSFET has been described as an example, but the present invention is not limited to this, and is not limited to this. It can be applied to semiconductor devices having various configurations such as bonded semiconductor devices. Further, in the present invention, the first conductive type is n-type and the second conductive type is p-type in each embodiment, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. The same holds true.

As described above, the superjunction semiconductor device and the method for manufacturing a superjunction semiconductor device according to the present invention are useful for high withstand voltage semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like.

1 n ⁺ type semiconductor substrate 2 n type drift layer 3,3B n type column area 4, 4A, 4B p type column area 5, 5A p type base area 6 n ⁺ type source area 7 gate insulating film 8 gate electrode 9 interlayer insulation film 10 source electrode 11 back electrode 12 p ^- -type RESURF region 13 field oxide film 14, 14A p ⁺⁺ type contact regions 18A, 18B trench 19 contact plug 20,20B parallel pn regions 21,65 ion implantation mask 22 ion implantation 23 Oxide film 24 Resist mask 25A, 25B P-type column trench 27 n ^- type epitaxial layer 28 Oxide film 29 Field plate 30 Active region 40 Edge termination region 50 SJ-MOSFET
61 Metal Gate Runner 62 Channel Stopper 63, 63A, 63B p-type Well Region 64A, 64B, 64C, 64D, 64E, 64F Contact Hole 66A, 66B, 66C Insulating Film 67A, 67B, 67C, 67D, 67E, 67F Recess 90, 91-1, 91-2, 92, 93 Injection region 100 Top surface W1, W2, W3 Width T1 Thickness D1, D2 Section

Claims (14)

A method for manufacturing a superjunction semiconductor device having an active region through which an electric current flows and a terminal structure portion arranged outside the active region and having a pressure-resistant structure surrounding the active region.
A first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate on the front surface of the first conductive type semiconductor substrate.
The second step of forming the first trench from the surface of the first semiconductor layer, and
A third step of forming a first conductive type second semiconductor layer having a lower impurity concentration than the first semiconductor layer on the surface of the first semiconductor layer and in the first trench.
By injecting an impurity that becomes the second conductive type into the second semiconductor layer, a well region of the second conductive type is formed inside the second semiconductor layer, and the first column of the first conductive type is formed. A parallel pn structure in which the second column of the second conductive type is repeatedly and alternately arranged in a direction parallel to the front surface, and the upper surface of the second column is in contact with the bottom surface of the well region. The fourth step of forming the pn structure and
A fifth step of forming a second trench that penetrates the second semiconductor layer and reaches the first column.
The sixth step of forming the second conductive type second semiconductor region on the surface of the parallel pn structure of the active region, and
The seventh step of forming the gate insulating film and the gate electrode inside the second trench, and
The eighth step of selectively forming the first conductive type first semiconductor region on the surface layer of the second semiconductor region of the active region, and
A method for manufacturing a superjunction semiconductor device, which comprises. The method for manufacturing a superjunction semiconductor device according to claim 1, wherein in the sixth step, the bottom surface of the second semiconductor region is formed so as to be shallower than the bottom surface of the well region. The method for manufacturing a superjunction semiconductor device according to claim 1, wherein in the sixth step, the impurity concentration in the well region is formed to be lower than the impurity concentration in the second semiconductor region. The method for manufacturing a superjunction semiconductor device according to claim 1, wherein in the fourth step, an impurity that becomes the second conductive type is injected into the second semiconductor layer in the first trench. The superjunction semiconductor according to claim 1, wherein in the fourth step, impurities to be the second conductive type are injected into the surface layer of the second semiconductor layer on the surface of the first semiconductor layer. Manufacturing method of the device. The method for manufacturing a superjunction semiconductor device according to claim 1, wherein in the fourth step, the second column is also formed in the terminal structure portion. The method for manufacturing a superjunction semiconductor device according to claim 1, wherein the sixth step is performed before the fifth step. The method for manufacturing a superjunction semiconductor device according to claim 1, wherein in the fourth step, an impurity that becomes the second conductive type is injected only into the second semiconductor layer in the first trench. A superjunction semiconductor device having an active region through which an electric current flows and a terminal structure portion arranged outside the active region and having a pressure-resistant structure surrounding the active region.
A first conductive type first semiconductor layer provided on the front surface of the first conductive type semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, and a first conductive type first semiconductor layer.
A parallel pn structure in which the first conductive type first column and the second conductive type second column provided inside the first semiconductor layer are repeatedly and alternately arranged in a direction parallel to the front surface. ,
A second conductive type second semiconductor region provided on the surface layer of the parallel pn structure of the active region, and
A first conductive type first semiconductor region selectively provided on the surface layer of the second semiconductor region of the active region,
A second trench that penetrates the first semiconductor region and the second semiconductor region and reaches the first column,
A gate electrode provided inside the second trench via a gate insulating film is provided, and a second conductive type well region is provided inside the first semiconductor layer, and the lower surface of the well region is the second column. A superjunction semiconductor device that is in contact with the upper surface of the well region, the bottom surface of the well region is deeper than the bottom surface of the second semiconductor region, and the width of the upper surface of the well region is wider than the width of the second column. The superjunction semiconductor device according to claim 9, wherein the impurity concentration in the well region is lower than the impurity concentration in the second semiconductor region. The superjunction semiconductor device according to claim 9, wherein the parallel pn structure is also provided in the terminal structure portion. The superjunction semiconductor device according to claim 9, wherein the repeating pitch of the parallel pn structure of the terminal structure portion is narrower than the repeating pitch of the parallel pn structure of the active region. The ninth aspect of the present invention, wherein the surface layer of the terminal structure portion on the opposite side of the semiconductor substrate side is provided with a first conductive type second semiconductor layer having a lower impurity concentration than the first semiconductor layer. Superjunction semiconductor device. The superjunction semiconductor device according to claim 9, wherein the well region and the second semiconductor region are in contact with the side wall of the second trench.

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