JP2021170597A - Semiconductor device - Google Patents

Abstract

To perform impedance matching for each of receive and transmit paths, even when the receive and transmit paths for data signals are combined.SOLUTION: A semiconductor device according to one embodiment has an electrode pad PD, a receiving circuit RC1 that receives an input signal via the electrode pad PD, a transmitting circuit TC1 that transmits an output signal via the electrode pad PD, a coil L1 connected between the electrode pad PD and the receiving circuit RC1, a coil L2 connected between the coil L1 and the receiving circuit RC1, and a coil L3 connected between the coil L1 and the transmitter circuit TC1. The coil L3 and parasitic capacitance PCe are connected between coil L1 and coil L2.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device, and relates to, for example, a technique suitable and effective for a semiconductor device on which a semiconductor chip having a data communication circuit is mounted with an external device.

IEEE SOLID-STATE CIRCUITS MAGAZINE, fall 2015, Page 9-13, Behzad Razavi, as "The Bridged T-" consists of two inductors connected and interconnected between two ports and a bridge capacitor. "Coil" is described.

IEEE SOLID-STATE CIRCUITS MAGAZINE, fall 2015, Page 9-13, Behzad Razavi

In an interface circuit that inputs a data signal at high speed, the impedance of the transmission path of the input signal is specified. Further, for example, an ESD (Electro-Static Discharge) circuit or the like is connected to the transmission path of the input signal, and it is necessary to perform impedance matching in consideration of the parasitic capacitance of these circuits. When the data signal reception path and transmission path are provided separately, impedance matching can be performed for each of these circuits.

However, in recent years, as the speed of data communication has increased, there is a demand for using one transmission path as both a reception path and a transmission path. In this case, it is difficult to perform impedance matching because the signal flow differs between the reception operation and the transmission operation.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

The semiconductor device according to the embodiment includes an electrode pad, a receiving circuit that receives an input signal via the electrode pad, a transmitting circuit that transmits an output signal via the electrode pad, and the electrode pad and the receiving circuit. A first coil connected between the first coil, a second coil connected between the first coil and the receiving circuit, and a third coil connected between the first coil and the transmitting circuit. And have. Here, the third coil and the parasitic capacitance are connected between the first coil and the second coil.

According to the above embodiment, impedance matching of each of the reception path and the transmission path can be performed even when the reception path and the transmission path of the data signal are shared. be able to.

FIG. 1 is an explanatory diagram showing a configuration example of a data communication system including a semiconductor device according to an embodiment. FIG. 2 is a circuit diagram showing a configuration example of a circuit for connecting a transmission circuit, a reception circuit, and an electrode pad of the semiconductor device shown in FIG. FIG. 3 is a circuit diagram showing an operation of transmitting an output signal in the circuit shown in FIG. FIG. 4 is a circuit diagram showing an operation of receiving an input signal in a circuit which is an example of examination with respect to FIG. FIG. 5 is a circuit diagram showing an operation of transmitting an output signal in the circuit shown in FIG. FIG. 6 is an enlarged plan view showing an example of the layout around the plurality of coils shown in FIGS. 2 and 3. FIG. 7 is an enlarged cross-sectional view of the electrode pad and the impedance matching circuit shown in FIG. FIG. 8 is an enlarged plan view showing an example of layout around a plurality of coils, which is a modification of FIG. FIG. 9 is an enlarged cross-sectional view of the electrode pad and the impedance matching circuit shown in FIG. FIG. 10 is an enlarged plan view of the coil formed in the second wiring layer shown in FIG. FIG. 11 is a plan view schematically showing an example of a state in which two coils are overlapped in a plan view. FIG. 12 is a plan view schematically showing an example of a state in which the two coils are not overlapped and are magnetically coupled in a plan view. FIG. 13 is a plan view schematically showing an example of a state in which the two coils do not overlap in a plan view and the coil formed in a wiring layer different from the two coils overlaps the two coils. Is. FIG. 14 is an enlarged plan view showing an example of a layout around a plurality of coils, which is another modification of FIG. 6. FIG. 15 is an enlarged cross-sectional view of the electrode pad and the impedance matching circuit shown in FIG. FIG. 16 is an enlarged plan view of the coil formed in the second wiring layer shown in FIG. FIG. 17 is an enlarged plan view showing an example of a layout around a plurality of coils, which is another modification of FIG. FIG. 18 is an enlarged cross-sectional view of the electrode pad and the impedance matching circuit shown in FIG.

<Explanation of description format, basic words, and method in this application>
In the present application, the description of the embodiment is described by dividing it into a plurality of sections or the like for convenience, but these are not independent of each other and are described unless otherwise specified. Each part of a single example, before or after, one is a partial detail or part or all of a variant of the other. Moreover, as a general rule, the repeated description of the same part is omitted. In addition, each component in the embodiment is not essential unless otherwise specified, theoretically limited to that number, or apparently not from the context.

Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., even if it is referred to as "X consisting of A", etc. It does not exclude those containing. For example, when it comes to a component, it means "X containing A as a main component" or the like. For example, "silicon member" is not limited to pure silicon, but is a member containing SiGe (silicon-germanium) alloy, other multi-element alloy containing silicon as a main component, and other additives. Needless to say, it also includes. In addition, gold plating, Cu layer, nickel plating, etc. include not only pure ones but also members containing gold, Cu, nickel, etc. as main components, unless otherwise specified. It shall be muted.

Furthermore, even when referring to a specific numerical value or quantity, if it is clearly stated that this is not the case, unless it is theoretically limited to that number or if it is not apparent from the context, the numerical value exceeds the specific numerical value. It may be present, or it may be a numerical value less than the specific numerical value. Further, in the following description, a certain value and another value may be described as "same" or "same", but the meanings of "same" or "same" are exactly the same. In addition, it also includes cases where there is an error within the range that can be regarded as substantially equivalent.

Further, in each figure of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and the description is not repeated in principle.

Further, in the attached drawing, if it becomes complicated or if the distinction from the void is clear, hatching or the like may be omitted even in the cross section. In relation to this, when it is clear from the explanation or the like, the outline of the background may be omitted even if the hole is closed in a plane. Further, even if it is not a cross section, hatching or a dot pattern may be added to clearly indicate that it is not a gap or to clearly indicate the boundary of a region.

<Data communication system>
First, an outline of a data communication system including the semiconductor device of the present embodiment will be described. FIG. 1 is an explanatory diagram showing a configuration example of a data communication system including a semiconductor device according to an embodiment.

As shown in FIG. 1, the semiconductor device 100 of the present embodiment has a data communication circuit DCC that transmits a data signal to and from the memory device MD1. In the example shown in FIG. 1, the data communication circuit DCC transmits a data signal to and from the memory device MD1. The data communication circuit DCC of the modified example may perform data communication with a plurality of memory devices MD1. The data communication circuit DCC includes a reception circuit RC1 that receives an input signal SGr from the memory device MD1 and a transmission circuit TC1 that transmits an output signal SGt to the memory device MD1.

<Circuit configuration example>
Next, a configuration example of the circuit included in the semiconductor device 100 shown in FIG. 1 will be described. 2 and 3 are circuit diagrams showing a configuration example of a circuit for connecting a transmission circuit, a reception circuit, and an electrode pad of the semiconductor device shown in FIG. Although the circuits are the same in FIGS. 2 and 3, FIG. 2 shows an operation at the time of receiving the input signal SGr, and FIG. 3 shows an operation at the time of transmitting the output signal SGt so as to be easy to understand. FIG. 4 is a circuit diagram showing an operation of receiving an input signal in a circuit which is an example of examination with respect to FIG. FIG. 5 is a circuit diagram showing an operation of transmitting an output signal in the circuit shown in FIG.

The semiconductor device 100 includes an electrode pad PD, a reception circuit RC1 that receives an input signal SGr via the electrode pad PD, and a transmission circuit TC1 that transmits an output signal SGt (see FIG. 3) via the electrode pad PD. Further, the semiconductor device 100 is connected between the coil L1 connected between the electrode pad PD and the receiving circuit RC1, the coil L2 connected between the coil L1 and the receiving circuit, and the coil L1 and the transmitting circuit. It has a coil L3 to be formed. A coil L3 and a parasitic capacitance PCe are connected between the coil L1 and the coil L2.

The circuits shown in FIGS. 4 and 5 differ from the circuits shown in FIGS. 2 and 3 in that the coil L3 (see FIG. 2) does not exist. Considering only the reception operation shown in FIG. 4, the circuit shown in FIG. 4 consists of two inductors (coils L1 and L2) connected and interconnected between the electrode pad PD and the reception circuit RC1 and two inductors. It has a parasitic capacitance PCe connected between them. In other words, the electrode pad PD is connected to the receiving circuit RC1 via the coils L1 and L2. A parasitic impedance PZ1 including a parasitic capacitance PCe is connected between the coil L1 and the coil L2.

In an interface circuit that inputs a data signal at high speed, the impedance of the transmission path of the input signal is specified. Further, for example, an electrostatic protection circuit (ESD; Electro-Static Discharge) circuit or the like is connected to the transmission path of the input signal, and it is necessary to perform impedance matching in consideration of the parasitic capacitance of these circuits. When the data signal reception path and transmission path are provided separately, impedance matching can be performed for each of these circuits.

However, in recent years, as the speed of data communication has increased, there is a demand for using one transmission path as both a reception path and a transmission path. In this case, it is difficult to perform impedance matching because the signal flow differs between the reception operation and the transmission operation. In the case of the circuit shown in FIG. 4, the transmission circuit TC1 is connected between the coils L1 and L2. The parasitic impedance of the transmission circuit TC1 is included in the parasitic impedance PZ1. When only the reception operation is performed in this circuit, the inductance of the coils L1 and L2 can be adjusted according to the value of the parasitic impedance PZ1, so that impedance matching in the path of the reception circuit RC1 from the electrode pad PD can be realized.

However, in the circuits shown in FIGS. 4 and 5, when the transmission operation is performed, the parasitic impedance PZ2 of the path through which the output signal SGt shown in FIG. 5 flows is different from the parasitic impedance PZ1 of the path through which the input signal SGr shown in FIG. 4 flows. The values are different. Therefore, if impedance matching is realized in the receiving operation, impedance matching cannot be realized in the transmitting operation. On the contrary, if impedance matching is realized in the transmission operation, impedance matching cannot be realized in the reception operation.

On the other hand, in the case of the circuit included in the semiconductor device 100 of the present embodiment shown in FIGS. 2 and 3, the values of the parasitic impedance PZ1 shown in FIG. 2 and the parasitic impedance PZ2 shown in FIG. 3 can be made similar. ..

The parasitic impedance PZ1 shown in FIG. 2 includes a parasitic capacitance PCe of an electrostatic protection circuit, a transmission circuit TC1, a capacitance C13 between the coil L1 and the coil L3, a capacitance C23 between the coil L2 and the coil L3, and a coil L3. .. On the other hand, the parasitic impedance PZ2 shown in FIG. 3 is the parasitic capacitance PCe of the electrostatic protection circuit, the receiving circuit RC1, the capacitance C23 between the coil L2 and the coil L3, the capacitance C12 between the coil L1 and the coil L2, and the coil L2. Consists of. The impedance of the transmission circuit TC1 and the impedance of the reception circuit RC1 can be regarded as substantially the same. The impedance of the coil L2 and the impedance of the coil L3 can be regarded as substantially the same. Further, since each of the capacitance C13 and the capacitance C12 is the capacitance at both ends of the two coils, they can be regarded as substantially the same. Therefore, the values of the parasitic impedance PZ1 shown in FIG. 2 and the parasitic impedance PZ2 shown in FIG. 3 are substantially the same.

Even when one signal transmission path is used as both a transmission path and a reception path, if the values of the parasitic impedance PZ1 shown in FIG. 2 and the parasitic impedance PZ2 shown in FIG. 3 are about the same, transmission is performed. Impedance matching of the transmission path can be realized in both the operation and the reception operation.

The parasitic impedance PZ1 shown in FIG. 2 and the parasitic impedance PZ2 shown in FIG. 3 include the parasitic capacitance of the wiring connected to the coils L1, L2, and L3. As shown in FIGS. 2 and 3, when the parasitic capacitance PCe of the electrostatic protection circuit is connected between the coils L1, L2, and L3, the value of the parasitic capacitance PCe has a particularly large effect on impedance matching. ..

The circuits shown in FIGS. 2 and 3 can be expressed as follows. The semiconductor device 100 electrically connects to the electrode pad PD and the electrode pad PD that are electrically connected to each of the receiving circuit RC1 that receives the input signal, the transmitting circuit TC1 that transmits the output signal, the receiving circuit RC1 and the transmitting circuit TC1. It has a parasitic capacitance PCe to be connected and an impedance matching circuit MC1 to be electrically connected to the electrode pad PD. The impedance matching circuit MC1 includes a coil L1 (first inductor) connected to the electrode pad PD, a second inductor (coil L2) connected to the coil L1 and the receiving circuit RC1, a coil L1, a coil L2, and a transmission circuit. It has a coil L3 (third inductor) connected to TC1. Further, the impedance matching circuit MC1 is included in the node ND1 at the midpoint between the electrode pad PD and the coil L1, the node ND2 at the midpoint between the receiving circuit RC1 and the coil L2, and the transmitting circuit TC1 and the coil L3. It has a node ND3 at a point and a node ND4 at the midpoint of each of coil L1, coil L2, and coil L3. The parasitic capacitance PCe is connected to the midpoint of each of the coil L1, the coil L2, and the coil L3.

<Coil layout>
Next, the layout of the coil included in the semiconductor device 100 shown in FIGS. 2 and 3 will be described. In order to achieve impedance matching by the coils L1, L2, and L3 shown in FIGS. 2 and 3, it is preferable that the coils L1, L2, and L3 are magnetically coupled to each other. The state in which each of the coils L1, L2 and L3 is magnetically coupled means a state in which mutual inductance occurs between the coils L1, L2 and L3, respectively. In order to realize the magnetically coupled state, it is preferable that the separation distances of the coils L1, L2 and L3 are small. Further, the degree of coupling of the coils L1, L2 and L3, in other words, the larger the coupling strength, the better the characteristics of the impedance matching circuit MC1. In order to improve the coupling strength, it is preferable to reduce the distance between the coils L1, L2 and L3.

Further, the coils L1, L2 and L3 used in the impedance matching circuit MC1 need to increase the distance of the path through which the current flows to some extent. When the semiconductor device 100 has a plurality of electrode pads PD and each of the plurality of electrode pads PD is connected to the impedance matching circuit MC1, it is preferable to reduce the occupied area of the impedance matching circuit MC1 in a plan view.

Further, as will be described later, the semiconductor device 100 has a plurality of wiring layers. The coils L1, L2 and L3 may be formed in the same wiring layer or different wiring layers among the plurality of wiring layers. When the coils L1, L2 and L3 are formed in different wiring layers, the coils L1, L2 and L3 can be arranged so as to overlap each other, so that the area occupied by the impedance matching circuit MC1 in a plan view can be reduced. Is particularly preferred. However, when the coils L1, L2 and L3 are formed in different wiring layers, the coils are formed in the wiring layers for the three layers. From the viewpoint of securing a space for forming a circuit other than the impedance matching circuit MC1, it is preferable that the coils L1, L2 and L3 are formed in one layer or two layers.

FIG. 6 is an enlarged plan view showing an example of the layout around the plurality of coils shown in FIGS. 2 and 3. In FIG. 6, the coil L2 formed in a wiring layer different from the coil L1 is shown by a dotted line, and the coil L3 is shown by a alternate long and short dash line. Further, in FIG. 6, each of the receiving circuit RC1, the transmitting circuit TC1, and the electrostatic protection circuit ESDC (diode element) formed in a semiconductor layer different from the wiring layer WL1 (see FIG. 7) in which the coil L1 is formed is formed. It is schematically shown by a circuit symbol. Further, in FIG. 6, the wiring WP1 for electrically connecting each of the coils L1, L2, and L3 and the electrostatic protection circuit ESDC is shown by a chain double-dashed line. FIG. 7 is an enlarged cross-sectional view of the electrode pad and the impedance matching circuit shown in FIG. In FIG. 7, each of the receiving circuit RC1, the transmitting circuit TC1, and the electrostatic protection circuit ESDC formed in the semiconductor layer arranged below the wiring layers WL1 to WL4 is schematically shown by circuit symbols.

In the examples shown in FIGS. 6 and 7, the coils L1, L2, and L3 included in the impedance matching circuit MC1 of the semiconductor device 100 are conductor patterns formed in a coil shape, respectively. The coil-shaped conductor pattern is a pattern in which a magnetic force is generated due to an electric current in a region surrounded by the conductor pattern when an electric current is passed through the conductor pattern. In the example shown in FIG. 6, each of the coils L1, L2 and L3 is a coil having three turns, but as a modification, a coil having one or two turns or a coil having four or more turns may be used. The coupling strength can be increased by increasing the number of circumferences of the coil. Further, when the number of rotations of the coil is small and the rotation path distance is short, the occupied area of the coil can be reduced.

In the case of the semiconductor device 100 shown in FIG. 6, the coils L1, L2 and L3 are formed in different wiring layers from each other. As shown in FIG. 7, the coil L1 is arranged in the wiring layer WL1, the coil L2 is arranged in the wiring layer WL2, and the coil L3 is arranged in the wiring layer WL3. The wiring layer WL1 and the wiring layer WL2 are adjacent to each other via the insulating layer IL1. The wiring layer WL2 and the wiring layer WL3 are adjacent to each other via the insulating layer IL2. The wiring layer WL3 and the wiring layer WL4 are adjacent to each other via the insulating layer IL3. Further, the wiring layer WL1 is the uppermost wiring layer of the semiconductor device 100 and is covered with the passivation film PF1. The passivation film PF1 is a protective film that protects the pad-forming surface of the semiconductor device 100, and a part of the electrode pad PD is exposed from the passivation film PF1 at the opening formed in the passivation film PF1. Each of the coils L1, L2, and L3 is electrically connected via a via V1 which is an interlayer conductive path that electrically connects the wiring layers WL1, WL2, and WL3.

In the case of the structures shown in FIGS. 6 and 7, as shown in FIG. 7, the coils L1, L2 and L3 overlap each other in the perspective plan view. Further, since the area where the coils L1, L2 and L3 overlap each other can be increased, the area occupied by the impedance matching circuit MC1 in a plan view can be reduced. Further, when the coils L1, L2 and L3 are formed in different wiring layers, it is easy to make the shapes of the coils L1, L2 and L3 similar. As a result, it is easy to make the values of the parasitic impedances of the coils L1, L2, and L3 comparable.

FIG. 8 is an enlarged plan view showing an example of layout around a plurality of coils, which is a modification of FIG. FIG. 9 is an enlarged cross-sectional view of the electrode pad and the impedance matching circuit shown in FIG. FIG. 10 is an enlarged plan view of the coil formed in the second wiring layer shown in FIG. Although FIG. 10 is a plan view, different types of hatching are provided to make it easier to identify the coils L1 and L2. Although the semiconductor device 101 will be described below, the semiconductor device 101 is the same as the semiconductor device 100 shown in FIGS. 2, 3, 6 and 7, except for the differences described below. Therefore, the semiconductor device 101 has the same circuit configuration as the circuits shown in FIGS. 2 and 3.

In the impedance matching circuit MC1 included in the semiconductor device 101 shown in FIGS. 8 and 9, the coil L3 is formed in the wiring layer WL1, and each of the coils L2 and L3 is formed in the wiring layer WL2. Although not shown, as a modification to the semiconductor device 101, any one of the coils L3, L2 and L3 (for example, the coil L1 or L2) is formed in the wiring layer WL1, and the other two are formed in the wiring layer WL2. It may be formed. In the case of the semiconductor device 101, since any one of the coils L1, L2, and L3 (coil L3 in the case of FIG. 8) is formed in the wiring layer WL1 and the other two are formed in the wiring layer WL2, the coil. The wiring layer in which the is arranged can be fastened to two layers. In this case, a space for forming a circuit other than the impedance matching circuit MC1 can be secured in the wiring layers WL3, WL4 and the like. From the wiring layer WL1 to the wiring layer WL4, it is possible to secure a wider pattern thickness, width, and separation distance between adjacent patterns as compared with the wiring layer on the lower layer side (semiconductor substrate side (not shown)). Therefore, in the wiring layers WL1 to WL4, the characteristics of other circuits can be improved by securing a space for forming a circuit other than the impedance matching circuit MC1.

Further, in the case of the semiconductor device 101, the electrode pad PD is formed on the same wiring layer WL1 as the coil L3. In other words, a part of the coils L1, L2, and L3 is formed in the wiring layer WL1 which is the uppermost wiring layer for forming the electrode pad PD. By utilizing the uppermost wiring layer WL1 for forming the coil L3, it is possible to secure a margin of space between the wiring layer WL2 and the lower wiring layer.

As described above, as a modification of the semiconductor device 101, any one of the coils L1, L2, and L3 (for example, the coil L2 or L1) is formed on the wiring layer WL1, and the other two are formed on the wiring layer WL2. In some cases. For example, although not shown, when the coil L1 is formed in the wiring layer WL1 and the coils L2 and L3 are formed in the wiring layer WL2, the parasitic impedance of the wiring that electrically connects the electrode pad PD and the coil L3, for example. Is preferable in that the amount of

However, in the case of the semiconductor device 101, the coil L3 connected to the electrode pad PD is formed in the wiring layer WL1 which is the same layer as the electrode pad PD. Further, as shown in FIG. 10, the coils L1 and L2 are formed so that the current paths are in the same direction. The coil L1 and the coil L2 are arranged parallel to each other. In this case, an impedance matching circuit MC1 having the same coupling coefficient of the coils L1 and L3 and the coupling coefficient of the coils L2 and L3 can be designed.

Further, the wiring layers WL1 and WL2 are adjacent to each other via the insulating layer IL1. In other words, the wiring layer WL2 on which the coils L1 and L2 are formed is the wiring layer next to the wiring layer WL1 on which the coil L3 is formed. In this way, when the wiring layers on which the plurality of coils L1, L2, and L3 are formed extend over the plurality of layers, the coupling strength can be improved by reducing the distance between the wiring layers. In other words, when the wiring layers on which the plurality of coils L1, L2, and L3 are formed extend over the plurality of layers, the coupling coefficient can be adjusted by controlling the distance between the wiring layers.

Further, as shown in FIGS. 8 and 10, the coil L3 overlaps the coils L1 and L2 in a plan view. In this case, it is possible to suppress an increase in the occupied area due to the impedance matching circuit MC1. Further, when the coil L3 overlaps the coils L1 and L2, the coupling strength (coupling coefficient) between the coils L1 and L2 and the coil L3 is controlled by controlling the degree to which the coil L3 overlaps the coils L1 and L2. ) Can be adjusted.

Further, as shown in FIG. 10, the coils L1 and L2 overlap each other. Here, "in the plan view, the coils L1 and L2 overlap" means that in the plan view, the region where the coil L2 is formed and at least a part of the region where the coil L1 is formed overlap. say. In the example shown in FIG. 10, the circuit path of the coil L1 is arranged outside the circuit path of the coil L2. Therefore, since the region in which the coil L2 is formed is arranged in the region in which the coil L1 is formed, it can be said that the coil L2 overlaps with the coil L1.

FIG. 11 is a plan view schematically showing an example of a state in which two coils are overlapped in a plan view. Further, FIG. 12 is a plan view schematically showing an example of a state in which the two coils are not overlapped and are magnetically coupled in a plan view. FIG. 13 is a plan view schematically showing an example of a state in which the two coils do not overlap in a plan view and the coil formed in a wiring layer different from the two coils overlaps the two coils. Is. As schematically shown in FIG. 11, when a part of the coil L1 formed in the wiring layer WL1 and a part of the coil L2 formed in the wiring layer WL2 overlap in the plan view, the coil in the perspective plan view. It can be said that L3 and the coil L2 overlap. On the other hand, as schematically shown in FIG. 12, in a plan view, there is no overlapping portion between the region where the coil L1 is formed and the region where the coil L2 is formed. In this case, it can be said that the coil L1 and the coil L2 do not overlap. However, if the separation distance between the coil L1 and the coil L2 is short, the magnetic coupling between the coils L1 and L2 is established. In the example shown in FIG. 12, the coils L1 and L2 are magnetically coupled. Further, in the example shown in FIG. 13, the coils L1 and L2 formed in the wiring layer WL2 do not overlap in a plan view and are magnetically coupled. On the other hand, the coil L3 formed in the wiring layer WL1 overlaps each of the coils L1 and L2 in a plan view (specifically, a perspective plan view).

According to the above definition, in the case of the semiconductor device 101 shown in FIGS. 8 and 10, the coils L1, L2, and L3 each overlap each other in a plan view (specifically, a perspective plan view). When the coils L1, L2, and L3 are arranged so as to overlap each other, the coupling coefficient of each coil can be adjusted by adjusting the degree of overlap of the coils L1, L2, and L3, so that an impedance matching circuit can be used. The characteristics as MC1 can be improved. The structure of the semiconductor device 101 is particularly effective when applied to design an impedance matching circuit MC1 having a large coupling coefficient and coupling capacitance between a plurality of coils.

FIG. 14 is an enlarged plan view showing an example of a layout around a plurality of coils, which is another modification of FIG. 6. FIG. 15 is an enlarged cross-sectional view of the electrode pad and the impedance matching circuit shown in FIG. FIG. 16 is an enlarged plan view of the coil formed in the second wiring layer shown in FIG. Although FIG. 16 is a plan view, different types of hatching are provided to make it easier to identify the coils L1 and L2. Hereinafter, the semiconductor device 102 will be described, but the semiconductor device 102 is the same as the semiconductor device 100 shown in FIGS. 2, 3, 6 and 7, except for the differences described below. Therefore, the semiconductor device 102 has the same circuit configuration as the circuits shown in FIGS. 2 and 3.

In the case of the semiconductor device 102, the coil L3 connected to the electrode pad PD is formed in the wiring layer WL1 which is the same layer as the electrode pad PD. Further, as shown in FIG. 16, the coils L1 and L2 are formed so that the current paths are in the same direction. The entire coil L2 is arranged so as to be located inside the coil L1. In this case, the coupling coefficient and coupling capacitance of the coil L1 and the coil L2 are smaller than those of the semiconductor device 101 shown in FIGS. 8 to 10. Further, since the coil L3 overlaps the coils L1 and L2, the coupling strength between the coils L1 and L2 and the coil L3 is adjusted by adjusting the planar positional relationship of the coil L3 with respect to the coils L1 and L2. (Coupling coefficient) can be adjusted.

On the other hand, as shown in FIG. 14, the size of the impedance matching circuit MC1 in a plan view is larger than that of the example shown in FIG. 6 and the example shown in FIG. Therefore, from the viewpoint of reducing the occupied area of the impedance matching circuit MC1 in a plan view, the semiconductor device 100 shown in FIG. 6 or the semiconductor device 101 shown in FIG. 8 is more advantageous.

FIG. 17 is an enlarged plan view showing an example of a layout around a plurality of coils, which is another modification of FIG. FIG. 18 is an enlarged cross-sectional view of the electrode pad and the impedance matching circuit shown in FIG. Although FIG. 17 is a plan view, different types of hatching are provided to make it easier to identify the coils L3, L2, and L3. Hereinafter, the semiconductor device 103 will be described, but the semiconductor device 103 is the same as the semiconductor device 100 shown in FIGS. 2, 3, 6 and 7, except for the differences described below. Therefore, the semiconductor device 103 has the same circuit configuration as the circuits shown in FIGS. 2 and 3.

The semiconductor device 103 differs from the semiconductor device 100 shown in FIG. 6 in that the coils L3, L2, and L2 are each formed in the same wiring layer WL1. In plan view, the coils L1, L2, and L3 each overlap each other. In the case of the semiconductor device 103, the impedance matching circuit MC1 is integrated in the wiring layer WL1. Therefore, as shown in FIG. 18, a wide space can be secured in each of the wiring layers WL2, WL3, and WL4.

On the other hand, as shown in FIG. 17, the size of the impedance matching circuit MC1 in a plan view is larger than that of the example shown in FIG. 6, the example shown in FIG. 8, and the example shown in FIG. Therefore, from the viewpoint of reducing the occupied area of the impedance matching circuit MC1 in a plan view, the semiconductor device 100 shown in FIG. 6, the semiconductor device 101 shown in FIG. 8, or the semiconductor device 102 shown in FIG. 14 is more advantageous.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. Needless to say.

100, 101, 102, 103 Semiconductor devices C12, C13, C23 Capacitive DCC data communication circuit ESDC Electrostatic protection circuit IL1, IL2, IL3 Insulation layer L1, L2, L3 Coil MC1 Impedance matching circuit MD1 Memory device ND1, ND2, ND3, ND4 Node PCe Parasitic capacitance PD Electrode pad PF1 Passion film PZ1, PZ2 Parasitic impedance RC1 Reception circuit SGr Input signal SGt Output signal TC1 Transmission circuit V1 Via WL1, WL2, WL3, WL4 Wiring layer WP1 Wiring

Claims (20)

Semiconductor devices including:
Electrode pad,
A receiving circuit that receives an input signal via the electrode pad,
A transmission circuit that transmits an output signal via the electrode pad,
A first coil connected between the electrode pad and the receiving circuit,
A second coil connected between the first coil and the receiving circuit,
A third coil connected between the first coil and the transmission circuit,
here,
The third coil and parasitic capacitance are connected between the first coil and the second coil. In the semiconductor device according to claim 1,
It further includes an electrostatic protection circuit connected to the electrode pad.
The parasitic capacitance includes the capacitance of the electrostatic protection circuit. In the semiconductor device according to claim 2,
Each of the first coil, the second coil, and the third coil is magnetically coupled. In the semiconductor device according to claim 3,
Any one of the first coil, the second coil, and the third coil is formed in the first wiring layer.
The first coil, the second coil, and the other two of the third coil are formed in a second wiring layer different from the first wiring layer. In the semiconductor device according to claim 4,
The electrode pad is formed on the first wiring layer. In the semiconductor device according to claim 5,
The third coil is formed in the first wiring layer, and is formed on the first wiring layer.
The first coil and the second coil are formed in the second wiring layer, and the first coil and the second coil are formed in the second wiring layer.
The first wiring layer and the second wiring layer are adjacent to each other via an insulating layer. In the semiconductor device according to claim 6,
In a plan view, the third coil overlaps the first coil and the second coil. In the semiconductor device according to claim 7,
The first coil and the second coil overlap each other. In the semiconductor device according to claim 1,
Each of the first coil, the second coil, and the third coil is formed in the same wiring layer. In the semiconductor device according to claim 3,
In a plan view, the first coil, the second coil, and the third coil each overlap each other. Semiconductor devices including:
Receiving circuit that receives the input signal,
Transmission circuit that transmits the output signal,
Electrode pads that are electrically connected to each of the receiving circuit and the transmitting circuit,
Parasitic capacitance electrically connected to the electrode pad, and
Impedance matching circuit electrically connected to the electrode pad;
here,
The impedance matching circuit
The first inductor connected to the electrode pad and
The first inductor and the second inductor connected to the receiving circuit,
The first inductor, the second inductor, and the third inductor connected to the transmission circuit,
A first node at the midpoint between the electrode pad and the first inductor,
A second node at the midpoint between the receiving circuit and the second inductor,
A third node at the midpoint between the transmission circuit and the third inductor,
A fourth node at the midpoint of each of the first inductor, the second inductor, and the third inductor.
Have,
The parasitic capacitance is connected to the midpoint of each of the first inductor, the second inductor, and the third inductor. In the semiconductor device according to claim 11,
It further includes an electrostatic protection circuit connected to the electrode pad.
The parasitic capacitance includes the capacitance of the electrostatic protection circuit. In the semiconductor device according to claim 12,
Each of the first inductor, the second inductor, and the third inductor consists of a conductor pattern formed in a coil shape. In the semiconductor device according to claim 13,
Each of the first inductor, the second inductor, and the third inductor is magnetically coupled. In the semiconductor device according to claim 14,
In a plan view, the first inductor, the second inductor, and the third inductor each overlap each other. In the semiconductor device according to claim 14,
Any one of the first inductor, the second inductor, and the third inductor is formed in the first wiring layer.
The first inductor, the second inductor, and the other two of the third inductor are formed in a second wiring layer different from the first wiring layer. In the semiconductor device according to claim 16,
The electrode pad is formed on the first wiring layer. In the semiconductor device according to claim 17,
The third inductor is formed on the first wiring layer.
The first inductor and the second inductor are formed on the second wiring layer.
The first wiring layer and the second wiring layer are adjacent to each other via an insulating layer. In the semiconductor device according to claim 18,
In a plan view, the third inductor overlaps the first inductor and the second inductor. In the semiconductor device according to claim 19,
The first inductor and the second inductor overlap each other.

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