JP2021163846A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of reducing power consumption.SOLUTION: A semiconductor device 1A comprises: a bulk silicon region 1 where a MOS transistor is formed; a Silicon on Thin Buried Oxide (SOTB) region 2 where an SOTB transistor is formed; and an SOTB region 3 that is separated from the SOTB region 2 and where an SOTB transistor is formed. The SOTB region 2 is always supplied with substrate bias voltages Vbp and Vbn. It can be selected whether to supply the substrate bias voltages Vbp and Vbn to the SOTB region 3.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a substrate bias circuit that generates a substrate bias voltage.

A semiconductor device including a substrate bias circuit is described in, for example, Patent Document 1. For example, FIG. 2 of Patent Document 1 shows a CPU (26), a system controller (24), P-type SOTB transistors (SP1, SP2), N-type SOTB transistors (SN1 to SN4), and a substrate bias circuit (23). ) And a semiconductor device is shown. According to Patent Document 1, when the CPU (26) is operated at a low speed, a substrate bias voltage (Vsp, Vsn) is supplied to the P-type SOTB transistor and the N-type SOTB transistor, and when the CPU (26) is operated at a high speed, the substrate bias voltage is supplied. It is described that the substrate bias voltage (Vsp, Vsn) is not supplied to the P-type SOTB transistor and the N-type SOTB transistor.

Further, Patent Document 2 describes a semiconductor device configured by a CMOS circuit. Patent Document 2 describes controlling the substrate bias of a CMOS circuit.

Japanese Unexamined Patent Publication No. 2016-115891 Japanese Unexamined Patent Publication No. 11-191611

In Patent Document 1, when the CPU is operated at high speed, the substrate bias voltage is not supplied to the SOTB transistor, and at this time, the substrate bias voltage is not supplied to the circuit operating at low speed. As a result, there is a problem that the effect of reducing the current consumption in the circuit operating at a low speed cannot be obtained. Further, in order to operate the circuit normally when transitioning from the non-supply state in which the substrate bias voltage is not supplied to the supply state in which the substrate bias voltage is supplied, and when transitioning from the supply state to the non-supply state. , It is necessary to add a transition time of several μs to several tens of μs.

In Patent Document 2, the substrate bias of the CMOS circuit is controlled. In a semiconductor device composed of a CMOS circuit, if miniaturization is attempted, the leakage current between the source / drain of the transistors constituting the CMOS circuit and the substrate will increase even if the substrate bias is supplied, and the current consumption will be reduced. The effect is limited.

An object of the present invention is to provide a semiconductor device capable of reducing power consumption.

The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.

A brief description of typical inventions disclosed in the present application is as follows.

That is, the semiconductor device includes a bulk region in which the transistor is formed, a first SOTB region in which the SOTB transistor is formed, and a second SOTB region in which the first SOTB region is separated and the SOTB transistor is formed. The substrate bias voltage is always supplied to the first SOTB region, and it is possible to select the supply of the substrate bias voltage to the second SOTB region.

By selecting whether or not to supply the substrate bias voltage, the substrate bias voltage will transition. At the time of this transition, the inventor has found that the circuit block operating is a circuit block operating at a low speed. Based on this knowledge, the inventor considered to reduce power consumption by arranging a circuit operating at a low speed in the first SOTB region and constantly supplying a substrate bias voltage to the first SOTB region.

The effects obtained by representative of the inventions disclosed in the present application will be briefly described as follows.

It is possible to provide a semiconductor device capable of reducing power consumption. For example, by arranging a circuit composed of SOTB transistors and operating at a low speed in the first SOTB region, it is possible to constantly reduce the current consumption in the first SOTB region, and to reduce the power consumption of the semiconductor device. Is possible.

It is a block diagram which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a top view which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 1. FIG. It is a waveform diagram which shows the operation of the semiconductor device which concerns on Embodiment 1. FIG. It is a block diagram which shows the structure of the semiconductor device which concerns on Embodiment 2. It is a waveform diagram which shows the operation of the semiconductor device which concerns on Embodiment 2. It is a block diagram which shows the structure of the semiconductor device which concerns on Embodiment 3. It is a waveform diagram which shows the operation of the semiconductor device which concerns on Embodiment 3. It is a top view which shows the structure of the semiconductor device which concerns on Embodiment 3. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in all the drawings for explaining the embodiment, in principle, the same reference numerals are given to the same parts, and the repeated description thereof will be omitted in principle.

(Embodiment 1)
<Overall layout of semiconductor devices>
FIG. 2 is a plan view showing the configuration of the semiconductor device according to the first embodiment. In FIG. 2, 1A shows a semiconductor device. In the semiconductor device 1A, a plurality of circuit blocks are formed on one semiconductor substrate by a well-known semiconductor manufacturing technique. Here, the semiconductor device 1A will be described by taking a semiconductor device provided with a processor (hereinafter, also referred to as a CPU) as an example, but the present invention is not limited thereto.

Although the semiconductor device 1A includes a plurality of circuit blocks, only the circuit blocks necessary for explanation are shown in FIG. Further, in FIG. 2, the arrangement of the circuit blocks is schematically drawn according to the actual arrangement.

In FIG. 2, the I / O indicates an input / output unit. The input / output unit I / O is not particularly limited, but is arranged along the four sides of the semiconductor device 1A, and is used for transmitting and receiving signals between the inside and the outside of the semiconductor device 1A. In the semiconductor device 1A according to the first embodiment, a bulk silicon (Bulk Si) region 1, a SOTB region 2, and a SOTB region 3 are arranged on a semiconductor substrate. Here, SOTB is an abbreviation for Silicon on Thin Buried Oxide. An example will be described later with reference to FIG. 3, but a silicon substrate is used as the semiconductor substrate. A part of the silicon substrate is allocated as the bulk silicon region 1, and SOTB regions 2 and 3 are arranged in the other part of the silicon substrate. FIG. 2 shows an example in which two SOTB regions are arranged on a silicon substrate, but the present invention is not limited to this, and the number of SOTB regions may be three or more.

The SOTB region 2 and the SOTB region 3 are electrically separated from each other. That is, as shown in FIG. 2, the SOTB region 2 and the SOTB region 3 are separated, and the SOTB region 2 and the SOTB region 3 are separated by a part of the silicon region which is a semiconductor substrate or the bulk silicon region 1. Have been made to.

A circuit block that operates at a low speed (low-speed operation circuit 2A in FIG. 2) is arranged in the SOTB region 2, and a circuit block that operates at a higher speed than the low-speed operation circuit 2A in the SOTB region 3 (in FIG. 2). The high-speed operation circuit 3A and CPU301) are arranged. A plurality of electrodes are formed in each of the SOTB regions 2 and 3, and the voltage in the SOTB region is determined by the voltage supplied to each electrode. Although not particularly limited, in FIG. 2, electrodes 2T are formed at each of the four corners of the SOTB region 2, and the voltage of the SOTB region 2 is determined by the voltage supplied to these electrodes 2T. Similarly, the voltage of the SOTB region 3 is determined by the voltage supplied to the electrodes 3T formed at each of the four corners of the SOTB region 3.

Each of the low-speed operation circuit 2A, the high-speed operation circuit 3A, and the processor 301 is composed of a plurality of SOTB transistors and the like. That is, the low-speed operation circuit 2A is composed of a plurality of SOTB transistors and the like formed in the SOTB region 2. Further, the high-speed operation circuit 3A and the processor 301 are composed of a plurality of SOTB transistors and the like formed in the SOTB region 3.

The voltage supplied to the electrode 2T and determining the voltage in the SOTB region 2 acts as a voltage applied to the substrate gate electrode of the SOTB transistor formed in the SOTB region 2, that is, a back bias voltage. Similarly, the voltage supplied to the electrode 3T and determining the voltage of the SOTB region 3 acts as a voltage applied to the substrate gate electrode of the SOTB transistor formed in the SOTB region 3, that is, a back bias voltage.

The voltage supplied to the electrodes 2T and 3T is formed by a circuit block arranged in the bulk silicon region 1. In FIG. 2, as circuit blocks arranged in the bulk silicon region 1, a board bias changeover switch (switch circuit) 4, a P-type SOTB board bias circuit 5, an N-type SOTB board bias circuit 6, a power supply control circuit 7, and a bias changeover control The circuit 8 and the internal power supply circuit 9 are shown. The input / output unit I / O is also formed in the bulk silicon region 1.

The board bias changeover switch 4, the P-type SOTB board bias circuit 5, the N-type SOTB board bias circuit 6, the power supply control circuit 7, the bias changeover control circuit 8, and the internal power supply circuit 9 will be described below with reference to FIG. Although detailed description is omitted here, it is a circuit block related to voltage generation. That is, a circuit block mainly involved in voltage generation is arranged in the bulk silicon region 1, a circuit operating at a low speed is arranged in the SOTB region 2, and a circuit operating at a high speed is arranged in the SOTB region 3. ing.

Although omitted in FIG. 2, the semiconductor device 1A includes an external power supply terminal to which the external power supply voltage Vcc is supplied and an external power supply terminal to which the ground voltage Vss is supplied. The above-mentioned board bias changeover switch 4, P-type SOTB board bias circuit 5, N-type SOTB board bias circuit 6, power supply control circuit 7, bias changeover control circuit 8 and internal power supply circuit 9 are supplied with power via an external power supply terminal. It operates using the external power supply voltage Vcc as the power supply. The internal power supply circuit 9 steps down the external voltage Vcc to form the internal power supply voltage Vdd. The circuit blocks arranged in the SOTB regions 2 and 3 operate using the internal power supply voltage Vdd as a power supply. Further, the P-type SOTB board bias circuit 5 and the N-type SOTB board bias circuit 6 generate a board bias voltage based on the external voltage Vcc.

In the first embodiment, the substrate bias voltage formed by the P-type SOTB substrate bias circuit 5 and the N-type SOTB substrate bias circuit 6 is constantly supplied to the electrode 2T in the SOTB region 2. On the other hand, the substrate bias voltage or the internal power supply voltage Vdd and the ground voltage Vss formed by the P-type SOTB substrate bias circuit 5 and the N-type SOTB substrate bias circuit 6 are selectively supplied to the electrodes 3T in the SOTB region 3. Will be done. That is, in the first embodiment, the low-speed operation circuit 2A, the high-speed operation circuit 3A, and the processor 301 arranged in the SOTB regions 2 and 3 operate using the internal power supply voltage Vdd as the power supply voltage, but the high-speed operation circuit 3A and the high-speed operation circuit 3A The internal power supply voltage Vdd, the ground voltage Vss, or the substrate bias voltage is selectively supplied to the substrate gate electrode of the SOTB transistor constituting the processor 301. In other words, the substrate bias voltage is always supplied to the SOTB region 2, and it is possible to select whether or not to supply the substrate bias voltage to the SOTB region 3.

When the low-speed operation circuit 2A, the high-speed operation circuit 3A, and the processor 301 transmit and receive signals to and from the outside of the semiconductor device 1A, they are performed via the input / output unit I / O that operates at the external voltage Vcc. Become.

<Circuit configuration of semiconductor device>
FIG. 1 is a block diagram showing a configuration of a semiconductor device according to the first embodiment. FIG. 1 shows the above-mentioned board bias changeover switch 4, P-type SOTB board bias circuit 5, N-type SOTB board bias circuit 6, power supply control circuit 7, bias changeover control circuit 8, and internal power supply circuit 9. FIG. 1 also shows circuit blocks arranged in the SOTB regions 2 and 3 described above.

In FIG. 1, PT_V indicates an external power supply terminal to which the external power supply voltage Vcc is supplied, and PT_G indicates an external power supply terminal to which the ground voltage Vss is supplied. Further, PT_C1 and PT_C2 indicate external terminals to which a smoothing capacitor is connected.

An external power supply voltage Vcc is supplied to the P-type SOTB board bias circuit 5 and the N-type SOTB board bias circuit 6 via the external power supply terminal PT_V. Further, the external power supply voltage Vcc is also supplied to the power supply control circuit 7 and the internal power supply circuit 9. The P-type SOTB substrate bias circuit 5 generates a substrate bias voltage Vbp to be supplied to the substrate gate electrode of the P-type SOTB transistor based on the external power supply voltage Vcc. On the other hand, the N-type SOTB substrate bias circuit 6 generates a substrate bias voltage Vbn to be supplied to the substrate gate electrode of the N-type SOTB transistor based on the external power supply voltage Vcc.

The internal power supply circuit 9 steps down the external power supply voltage Vcc to generate the internal power supply voltage Vdd. The power supply control circuit 7 controls the P-type SOTB board bias circuit 5, the N-type SOTB board bias circuit 6, and the internal power supply circuit 9. In the first embodiment, the power supply control circuit 7 detects the rise of the external power supply voltage Vcc, operates the P-type SOTB board bias circuit 5 and the N-type SOTB board bias circuit 6, and then operates the internal power supply circuit 9. Make it work. This makes it possible to supply the substrate bias voltages Vbp and Vbn to the SOTB regions 2 and 3 before the internal power supply voltage Vdd is supplied to the SOTB regions 2 and 3 as the operating power supply. That is, the circuit block in the SOTB regions 2 and 3 can supply the substrate bias voltage to the SOTB regions 2 and 3 before operating at the internal power supply voltage Vdd, and the circuit block operates in an undesired state. It is possible to prevent this.

The board bias changeover switch 4 includes a plurality of switch sets. In the first embodiment, the substrate bias changeover switch 4 includes four switch sets corresponding to the number of electrodes 3T shown in FIG. 1, although not particularly limited. In FIG. 1, two switch sets S1 and S2 are illustrated out of the four switch sets. Each of the switch sets S1 and S2 includes a switch SW1 corresponding to the board bias voltage Vbp and a switch SW2 corresponding to the board bias voltage Vbn.

The switches SW1 constituting the switch sets S1 and S2 are connected to the P-type SOTB board bias circuit 5, the internal power supply circuit 9 and the SOTB region 3, and the internal power supply voltage Vdd or the board bias voltage Vbp is controlled by the bias switching control circuit 8. Is supplied to the SOTB region 3. Further, the switch SW2 is connected to the N-type SOTB board bias circuit 6, the external power supply terminal PT_G, and the SOTB area 3, and supplies the ground voltage Vss or the board bias voltage Vbn to the SOTB area 3 according to the control of the bias switching control circuit 8. .. The remaining two switch sets are the same as those of the switch sets S1 and S2.

The bias switching control circuit 8 is not particularly limited, but in the first embodiment, an instruction from the processor 301 is supplied. According to the instruction from the processor 301, the bias switching control circuit 8 controls the four switch sets in the same manner.

As shown in FIG. 2, a low-speed operation circuit 2A is arranged in the SOTB region 2. In FIG. 1, two SOTB transistors among the SOTB transistors constituting the low-speed operation circuit 2A are shown as an example. That is, the P-type (P-channel type) SOTB transistor SP2 and the N-type (N-channel type) SOTB transistor SN2 are SOTB transistors included in the low-speed operation circuit 2A. Further, as shown in FIG. 2, a high-speed operation circuit 3A and a processor 301 are arranged in the SOTB region 3. In FIG. 1, two SOTB transistors among the SOTB transistors constituting the high-speed operation circuit 3A are shown as an example. That is, the P-type SOTB transistor SP3 and the N-type SOTB transistor SN3 are SOTB transistors included in the high-speed operation circuit 3A. Although not shown, the processor 301 also includes a P-type SOTB transistor SP3 and a SOTB transistor similar to the N-type SOTB transistor SN3.

Each of the P-type SOTB transistors SP2 and SP3 and the N-type SOTB transistors SN2 and SN3 will be described in detail later with reference to FIG. 3, but the gate electrode G, the source electrode S, the drain electrode D and the substrate (back) gate electrode BG will be described in detail later. It has.

The P-type SOTB transistor SP2 and the N-type SOTB transistor SN2 are connected in series between the internal power supply voltage Vdd and the ground voltage Vss, and operate using the internal power supply voltage Vdd as the power supply voltage. The substrate bias voltage Vbp is constantly supplied to the substrate gate electrode BG of the P-type SOTB transistor SP2, and the substrate bias voltage Vbn is constantly supplied to the substrate gate electrode BG of the N-type SOTB transistor SN2.

Further, the P-type SOTB transistor SP3 and the N-type SOTB transistor SN3 are also connected in series between the internal power supply voltage Vdd and the ground voltage Vss, and operate using the internal power supply voltage Vdd as the power supply voltage. The substrate bias voltage Vbp or the internal power supply voltage Vdd is selectively supplied to the substrate gate electrode BG of the P-type SOTB transistor SP3 via the substrate bias changeover switch 4, and to the substrate gate electrode BG of the N-type SOTB transistor SN3. , The substrate bias voltage Vbn or the ground voltage Vss is selectively supplied via the substrate bias changeover switch 4.

Examples of the low-speed operation circuit 2A include a real-time clock circuit (RTC) and the like. On the other hand, as a high-speed operation circuit, there is a processor or the like.

Further, as shown in FIG. 1, the P-type SOTB board bias circuit 5 is connected to the smoothing capacitor 201 via the external terminal PT_C1, and the N-type SOTB board bias circuit 6 is connected to the smoothing capacitor 201 via the external terminal PT_C2. It is connected to 202. When the substrate bias voltages Vbp and Vbn are supplied to the SOTB region 2 and the SOTB region 3, the smoothing capacitors 201 and 202 function to suppress fluctuations in the substrate bias voltage. Further, the smoothing capacitors 201 and 202 function to shorten the supply time of the substrate bias voltage to the SOTB region 3.

<< Operating mode of semiconductor device >>
The semiconductor device 1A includes, for example, two operation modes, a high-speed mode and a low-speed mode. In the high-speed mode, for example, the semiconductor device operates at several MHz to several tens of MHz or more, and in the low-speed mode, it operates at several MHz or less. The low-speed operation circuit 2A arranged in the SOTB region 2 operates at a low frequency (for example, several MHz or less) in either the high-speed mode or the low-speed mode.

On the other hand, the operating frequency of the high-speed operating circuit 3A and the processor 301 arranged in the SOTB region 3 changes (for example, from several tens of MHz or more to several MHz or less) when the mode is changed from the high-speed mode to the low-speed mode. Change. Further, when the mode is changed from the low speed mode to the high speed mode, the operating frequencies of the high speed operating circuit 3A and the processor 301 arranged in the SOTB region 3 change (for example, change from several MHz or less to several tens of MHz or more).

In the first embodiment, the processor 301 indicates the operation mode to the bias switching control circuit 8. According to this instruction, the bias changeover control circuit 8 controls the board bias changeover switch 4.

<<< Switching operation mode >>>
Following the instruction to switch from high speed mode to low speed mode, the bias changeover switch control circuit 8 is such that the switches SW1 and SW2 select the substrate bias voltages Vbp and Vbn instead of the internal power supply voltage Vdd and the ground voltage Vss. Control the switch. As a result, the substrate bias voltage Vbp is supplied to the substrate gate electrode BG of the P-type SOTB transistor (SP3) formed in the SOTB region 3 instead of the internal power supply voltage Vdd, and the substrate of the N-type SOTB transistor (SN3) is supplied. A substrate bias voltage Vbn is supplied to the gate electrode BG instead of the ground voltage Vss.

The P-type SOTB transistor SP3 and the N-type SOTB transistor SN3 have their respective threshold voltages by supplying the substrate bias voltages Vbp and Vbn to the substrate gate electrode BG instead of the internal power supply voltage Vdd and the ground voltage Vss. The absolute value of is high. This makes it possible to reduce the leakage current in the plurality of P-type SOTB transistors and N-type SOTB transistors formed in the SOTB region 3 in the low-speed mode.

On the other hand, in the first embodiment, the substrate bias voltages Vbp and Vbn are constantly supplied to the SOTB region 2 in both the low speed mode and the high speed mode. That is, a substrate bias voltage Vbp is constantly supplied to the substrate gate electrode BG of the P-type SOTB transistor (SP2) formed in the SOTB region 2, and a substrate is always supplied to the substrate gate electrode BG of the N-type SOTB transistor (SN2). A bias voltage Vbn is supplied. Therefore, the absolute value of the threshold voltage of the plurality of P-type SOTB transistors and N-type SOTB transistors formed in the SPTB region 2 is always high. Thereby, it is possible to reduce the leakage current in the plurality of P-type SOTB transistors and N-type SOTB transistors formed in the SOTB region 2. Since the circuit block arranged in the SOTB region 2 is a circuit block operating at a low speed, even if the threshold voltage (absolute value) of the P-type SOTB transistor and the N-type SOTB transistor constituting the circuit block is high. , It is possible to work well.

As a result, by designating the low-speed mode, the current consumption of the semiconductor device 1A can be reduced, and as a result, the power consumption can be reduced.

When the operation mode of the semiconductor device 1A is switched from the low speed mode to the high speed mode, the processor 301 instructs the bias switching control circuit 8 to switch the operation mode. In response to this instruction, the bias switching control circuit 8 controls the switches SW1 and SW2 so that the switches SW1 and SW2 select the internal power supply voltage Vdd and the ground voltage Vss instead of the substrate bias voltages Vbp and Vbn. do. As a result, the internal power supply voltage Vdd is supplied to the substrate gate electrode BG of the P-type SOTB transistor (SP3) in the SOTB region 3, and the ground voltage Vss is supplied to the substrate gate electrode BG of the N-type SOTB transistor (SN3). Will be done. As a result, the absolute value of the threshold voltage of the plurality of P-type SOTB transistors and N-type SOTB transistors formed in the SOTB region 3 becomes small. Even if the high-speed mode is set and the operating frequency of the high-speed operation circuit and the processor 301 arranged in the SOTB region 3 is changed to, for example, several tens of MHz or more, the threshold values of the P-type SOTB transistor and the N-type SOTB transistor are set. Since the voltage (absolute value) is small, it can be operated sufficiently even at high frequencies.

It is also possible that the plurality of circuit blocks arranged in the SOTB region 3 include circuit blocks that do not require high-speed operation. Even in this case, in order to operate the high-speed operation circuit arranged in the SOTB region 3, when the high-speed mode is specified, the substrate gate electrode of the SOTB transistor formed in the SOTB region 3 is used. , The internal power supply voltage Vdd and the ground voltage Vss are supplied.

In the first embodiment, as shown in FIG. 1, a plurality of electrodes 3T are dispersedly provided in the SOTB region 3, and a plurality of electrodes 2T are dispersedly provided in the SOTB region 2 as well. .. As a result, the substrate bias voltages Vbp and Vpn are supplied to the SOTB region 2 by the plurality of dispersed electrodes 2T. Similarly, the internal power supply voltage Vdd and the ground voltage Vss or the substrate bias voltages Vbp and Vpn are supplied to the SOTB region 3 by the plurality of dispersed electrodes 3T. As a result, even if the SOTB regions 2 and 3 are relatively large, it is possible to suppress the voltage supplied to the substrate gate electrode from fluctuating according to the formation position of the SOTB transistor in the SOTB region.

Further, in the SOTB region 2, the substrate bias voltages Vbp and Vbn are constantly supplied in both the high-speed mode and the low-speed mode. Therefore, it is not necessary to consider the timing of controlling the board bias changeover switch 4 in consideration of the operation of the circuit block arranged in the SOTB region 2. That is, the timing for controlling the board bias changeover switch 4 may be determined by considering the operation of the circuit block arranged in the SOTB region 3, and the transition time required for switching the board bias voltage can be shortened. ..

In FIG. 1, reference numeral 2_1 shown by a broken line indicates a SOTB region in which another low-speed operation circuit is arranged. In this case, the board bias voltages Vbp and Vbn are always supplied to the SOTB region 2_1 as in the SOTB region 2.

In the present specification, the SOTB regions 2 and 2_1 may also be referred to as a first SOTB region, the SOTB region 3 may also be referred to as a second SOTB region, and the bulk silicon region 1 may be simply referred to as a bulk region.

<Structure of semiconductor device>
FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 3 also shows the internal power supply circuit 9, the P-type SOTB board bias circuit 5, the N-type SOTB board bias circuit 6, and the board bias changeover switch 4 shown in FIG. Since these circuit blocks have already been described, they will be omitted here.

In FIG. 3, 100 indicates a silicon substrate which is a semiconductor substrate. In the example shown in FIG. 3, a bulk silicon region 1, a SOTB region 2, and a SOTB region 3 are formed on the silicon substrate 100.

The structures of the P-type SOTB transistor and the N-type SOTB transistor are similar in the SOTB region 2 and the SOTB region 3. Therefore, here, the structure will be described by taking the SOTB transistor formed in the SOTB region 2 as an example.

As the SOTB region 2, the semiconductor region 102 in which the P-type SOTB transistor is formed and the semiconductor region 103 in which the N-type SOTB transistor is formed are formed on the silicon substrate 100. A plurality of P-type SOTB transistors are formed in the semiconductor region 102, and FIG. 3 shows one P-type SOTB transistor SP2 as a representative. Similarly, a plurality of N-type SOTB transistors are formed in the semiconductor region 103, and FIG. 3 shows one N-type SOTB transistor SN2 as a representative.

<< Structure of P-type SOTB transistor >>
The semiconductor region 102 includes a region in which a P-type SOTB transistor is formed and a region in which the electrode 2T_P is connected. Although not particularly limited, an element separation region 101 is formed on the surface side between the regions, and the surfaces of this region are separated. A thin insulating film 108 is formed on the region of the semiconductor region 102 on which the P-type SOTB transistor SP2 is formed, and the source semiconductor region (source region) 106 and the drain semiconductor region (drain) are formed on the thin insulating film 108. Region) 107 is formed. The source region 106 is connected to the source electrode S, and the drain region 107 is connected to the drain electrode D.

The N-type semiconductor region 109 is formed on the thin insulating film 108 between the source region 106 and the drain region 107. A gate electrode G is formed on the N-type semiconductor region 109 via a gate oxide film (not shown). A gate insulating film GSO is interposed between the gate electrode G, the source electrode S, and the drain electrode D. By supplying a negative voltage to the gate electrode G with respect to the source electrode S, a channel is formed in the N-type semiconductor region 109, and the P-type SOTB transistor SP2 becomes conductive. In FIG. 3, the portion of the semiconductor region 102 in which the P-type SOTB transistor SP2 is formed functions as the substrate gate electrode BG of the P-type SOTB transistor SP2. By supplying the substrate bias voltage Vbp to the electrode 2T_P, an electric field acts on the N-type semiconductor region 109 through the thin insulating film 108, and the threshold voltage (absolute value) of the P-type SOTB transistor SP2 becomes high.

Since a plurality of P-type SOTB transistors are formed in the semiconductor region 102, the semiconductor region 102 can be regarded as a substrate gate electrode BG common to the plurality of P-type SOTB transistors.

<< Structure of N-type SOTB transistor >>
The semiconductor region 103 includes a region in which an N-type SOTB transistor is formed and a region in which the electrode 2T_N is connected. Although not particularly limited, the tables in this region are separated by the element separation region 101. A thin insulating film 113 is formed on the region of the semiconductor region 103 in which the N-type SOTB transistor SN2 is formed, and a source region 112 and a drain region 110 are formed on the thin insulating film 113. The source region 112 is connected to the source electrode S, and the drain region 110 is connected to the drain electrode D.

A P-type semiconductor region 111 is formed on the thin insulating film 113 between the source region 112 and the drain region 113. A gate electrode G is formed on the P-type semiconductor region 111 via a gate oxide film (not shown). A gate insulating film GSO is interposed between the gate electrode G, the source electrode S, and the drain electrode D. By supplying a positive voltage to the gate electrode G with respect to the source electrode S, a channel is formed in the P-type semiconductor region 111, and the N-type SOTB transistor SN2 becomes conductive. In FIG. 3, the portion of the semiconductor region 103 in which the N-type SOTB transistor SN2 is formed functions as the substrate gate electrode BG of the N-type SOTB transistor SN2. By supplying the substrate bias voltage Vbn to the electrode 2T_N, an electric field acts on the P-type semiconductor region 111 through the thin insulating film 113, and the threshold voltage (absolute value) of the N-type SOTB transistor SN2 becomes high.

Since a plurality of N-type SOTB transistors are formed in the semiconductor region 103, the semiconductor region 103 can be regarded as a substrate gate electrode BG common to the plurality of N-type SOTB transistors.

The semiconductor region 102 and the semiconductor region 103 are separated by an element separation region 101. In FIG. 1, an electrode 2T is drawn as an electrode connecting the SOTB region 2 with the P-type SOTB substrate bias circuit 5 and the N-type SOTB substrate bias circuit 6, but the electrode 2T is as shown in FIG. It is composed of an electrode 2T_P connected to the semiconductor region 102 and an electrode 2T_N connected to the semiconductor region 103.

As described above, the P-type SOTB transistor (SP3) and the N-type SOTB transistor (SN3) in the SOTB region 3 are the same as the P-type SOTB transistor (SP2) and the N-type SOTB transistor (SN2) in the SOTB region 2. The difference is that the electrode 3T_P is connected to the semiconductor region 102 instead of the electrode 2T_P, and the electrode 3T_N is connected to the semiconductor region 103 instead of the electrode 2T_N. Further, the electrodes 3T_P and 3T_N constitute the electrode 3T shown in FIG.

As shown in FIG. 3, the semiconductor region 103 constituting the SOTB region 2 and the semiconductor region 102 forming the SOTB region 3 are separated from each other on the silicon substrate 100, and further, an element separation region is provided between these semiconductor regions. 101 is formed. As a result, the SOTB region 2 and the SOTB region 3 are electrically separated.

Although not particularly limited, the semiconductor region 102 is composed of an N-type well region formed on the silicon substrate 100, and the semiconductor region 103 is composed of a P-type well region formed on the silicon substrate 100. Further, as shown in FIG. 3, the board bias voltage Vbp formed by the P-type SOTB board bias circuit 5 is higher than the internal power supply voltage Vdd, and the board bias voltage Vbn formed by the N-type SOTB board bias circuit 6 is grounded. It is lower than the voltage Vss.

<< Bulk Transistor >>
Semiconductor regions 104 and 105 are formed in the bulk silicon region 1. A P-channel MOSFET (P-type MOS transistor) is formed in the semiconductor region 104, and an N-channel MOSFET (N-type MOS transistor) is formed in the semiconductor region 105. In FIG. 3, a P-type MOS transistor PM and an N-type MOS transistor NM are shown as examples. In the present specification, the P-type MOS transistor and the N-type MOS transistor are collectively referred to as a transistor.

In the semiconductor region 104, the P-type semiconductor region (source region) 114 and the P-type semiconductor region (drain region) 115 are formed so as to be separated from each other. Also. A gate electrode G is formed on the region between the source region 114 and the drain region 115 via a gate oxide film (not shown), the source region 114 is connected to the source electrode S, and the drain region 115 is connected to the source electrode S. It is connected to the drain electrode D. As a result, a P-type MOS transistor PM having a source region 114, a drain region 115, and a gate electrode G is configured.

In the semiconductor region 105, the N-type semiconductor region (source region) 117 and the N-type semiconductor region (drain region) 116 are formed so as to be separated from each other. Also. A gate electrode G is formed on the region between the source region 117 and the drain region 116 via a gate oxide film (not shown), the source region 117 is connected to the source electrode S, and the drain region 116 is connected to the source electrode S. It is connected to the drain electrode D. As a result, an N-type MOS transistor NM having a source region 117, a drain region 116, and a gate electrode G is configured.

The P-type MOS transistor and the N-type MOS transistor formed in the bulk silicon region 1 constitute a circuit block arranged in the bulk silicon region 1.

The semiconductor region 104 is composed of, for example, an N-type well region formed on the silicon substrate 100, and the semiconductor region 105 is composed of a P-type well region formed on the silicon substrate 100. When the source electrode S of the P-type MOS transistor PM is not connected to the semiconductor region 104, the semiconductor region 104 is connected to the external power supply voltage Vcc. When the source electrode S of the N-type MOS transistor NM is not connected to the semiconductor region 105, the semiconductor region 105 is connected to the ground voltage Vss. That is, when the substrate gate electrode of the transistor is separated from the source electrode S of the corresponding transistor, the ground voltage Vss is supplied to the substrate gate electrode of the N-type MOS transistor and external to the substrate gate electrode of the P-type MOS transistor. The power supply voltage Vcc is supplied.

As shown in FIG. 3, the semiconductor region 104 constituting the bulk silicon region 1 and the semiconductor region 103 forming the SOTB region 3 are also separated from each other, and an element separation region 101 is further formed between them. As a result, the SOTB region 2, the SOTB region 3, and the bulk silicon region 1 to which different substrate bias voltages are supplied can be arranged adjacent to each other on the same silicon substrate 100.

<Operation of semiconductor devices>
FIG. 4 is a waveform diagram showing the operation of the semiconductor device according to the first embodiment.

The semiconductor device 1A includes a standby mode and an active mode. The active mode includes a high-speed mode and a low-speed mode as described above. The high-speed mode is a mode in which one or more circuit blocks such as a circuit block arranged in the SOTB region 3, for example, a processor 301, operate at a high speed, for example. On the other hand, the low speed mode is a mode in which all the circuit blocks arranged in the SOTB region 3 operate or stop at a low speed.

Here, a case will be described in which the semiconductor device 1A is started in the high-speed mode, then shifts to the low-speed mode, and then shifts to the high-speed mode again.

When the external power supply voltage Vcc is supplied from the outside to the external power supply terminal PT_V shown in FIG. 1, the power supply control circuit 7 detects the rise of the external power supply voltage Vcc and biases the P-type SOTB board at time t1. The circuit 5 and the N-type SOTB board bias circuit 6 are changed from the stopped state to the operating state. As a result, the P-type SOTB board bias circuit 5 generates a board bias voltage Vbp higher than the internal power supply voltage Vdd, and the N-type SOTB board bias circuit 6 generates a board bias voltage Vbn lower than the ground voltage Vss.

The substrate bias voltages Vbp and Vbn are supplied to the SOTB region 2. At a subsequent time t2, the power supply control circuit 7 operates the internal power supply circuit 9. When the internal power supply circuit 9 starts operating, the internal power supply voltage Vdd is generated by the internal power supply circuit 9. Since the operation is performed in the high-speed mode (1) after the external power supply voltage Vcc is turned on, the bias switching control circuit 8 is a board bias switching switch 4 so that the internal power supply voltage Vdd and the ground voltage Vss are supplied to the SOTB region 3. To control. In other words, the bias switching control circuit 8 controls the board bias switching switch 4 so that the board bias voltages Vbp and Vbn are not supplied to the SOTB region 3.

At time t1, the supply of the substrate bias voltages Vbp and Vbn to the SOTB region 2 has started. However, the internal power supply voltage Vdd is generated at time t2. Therefore, the circuit blocks arranged in the SOTB regions 2 and 3 start operating after the time t2, for example, at the time t3. At this time, the threshold voltage (absolute value) of the SOTB transistor formed in the SOTB region 2 becomes high because the substrate bias voltages Vbp and Vbn are supplied to the substrate gate electrode BG. On the other hand, the threshold voltage (absolute value) of the SOTB transistor formed in the SOTB region 3 becomes smaller because the internal power supply voltage Vdd and the ground voltage Vss are supplied to the substrate gate electrode BG. As a result, the power consumption can be reduced in the SOTB region 2, and the circuit blocks arranged therein can operate at high speed in the SOTB region 3.

When the low-speed mode is specified in the bias switching control circuit 8 by the instruction from the processor 301, the mode shifts to the low-speed mode (2) at time t4.

When the low-speed mode is specified, the bias switching control circuit 8 controls the board bias switching switch 4 so that the board bias switching switches 4 supply the board bias voltages Vbp and Vbn to the SOTB region 3. do. In other words, the bias switching control circuit 8 controls the board bias switching switch 4 so that the internal power supply voltage Vdd and the ground voltage Vss are not supplied to the SOTB region 3 as the board bias voltage.

At the time t5 when the switching by the board bias changeover switch 4 is performed, the board bias voltages Vbp and Vbn are supplied to the SOTB region 3. As a result, the threshold voltage (absolute value) of the SOTB transistor formed in the SOTB region 3 becomes high, and the power consumption can be reduced also in the SOTB region 3.

Then, at time t6, the processor 301 again designates the high-speed mode in the bias switching control circuit 8. As a result, in the bias switching control circuit 8, the board bias switching switch 4 supplies the internal power supply voltage Vdd and the ground voltage Vss to the SOTB region 3 without supplying the board bias voltages Vbp and Vbn to the SOTB region 3. Control. As a result, from time t6, the internal power supply voltage Vdd is supplied to the substrate gate electrode BG of the P-type SOTB transistor formed in the SOTB region 3, and the ground voltage Vss is supplied to the substrate gate electrode BG of the N-type SOTB transistor. become. As a result, the mode shifts from the low speed mode (2) to the high speed mode (1) again.

FIG. 4 has described an example in which, after the external power supply voltage Vcc is applied, the engine is started in the high-speed mode, and then the mode is changed to the low-speed mode and then the high-speed mode, but the present invention is not limited to this. For example, after the external power supply voltage Vcc is turned on, the engine may be started in the low speed mode, and then the mode may be changed to the high speed mode and then the low speed mode.

Further, although the example in which the processor 301 instructs the bias switching control circuit 8 to instruct the operation mode is described here, the present invention is not limited to this. For example, a register may be provided in the bias switching control circuit 8 and the operation mode may be set in this register. In this case, the bias changeover control circuit 8 controls the board bias changeover switch 4 according to the operation mode set in the register.

According to the first embodiment, the substrate bias voltages Vbp and Vbn are supplied to the SOTB region 2 before the high-speed operating circuit block arranged in the SOTB region 3 starts operating. Therefore, it is possible to reduce the current consumption and the power consumption in the period until the circuit block operating at high speed starts to operate.

Further, the substrate bias voltages Vbp and Vbn are constantly supplied to the SOTB region 2 regardless of the operation mode. Therefore, it is possible to reduce the power consumption in the circuit block arranged in the SOTB region 2 regardless of the operation mode.

The SOTB region in which the SOTB transistor is formed is divided into a SOTB region 3 in which the presence or absence of the substrate bias voltage can be selected according to the speed and a SOTB region 2 in which the substrate bias voltage is supplied regardless of the speed. This makes it possible to reduce the number of circuit blocks arranged in the SOTB region 3. As a result, the size of the SOTB region 3 can be reduced, and the load on the substrate bias changeover switch 4 can be reduced. As a result, it is possible to reduce the time required when switching the substrate bias voltage.

Here, the P-type SOTB board bias circuit 5 and the N-type SOTB board bias circuit 6 have been described as examples of different circuits, but the present invention is not limited thereto. For example, the P-type SOTB board bias circuit 5 and the N-type SOTB board bias circuit 6 may be arranged as one board bias circuit. A plurality of substrate bias voltages Vbp and Vbn may be supplied from one substrate bias circuit.

(Embodiment 2)
FIG. 5 is a block diagram showing a configuration of the semiconductor device according to the second embodiment. In FIG. 5, 1B shows a semiconductor device. Since the semiconductor device 1B is similar to the semiconductor device 1A shown in FIG. 1, the differences will be mainly described here.

The main difference is that the semiconductor device 1B is provided with a SOTB substrate bias circuit for each SOTB region. That is, the semiconductor device 1B includes a P-type SOTB substrate bias circuit 52 and an N-type SOTB substrate bias circuit 62 corresponding to the SOTB region 2, and further includes a P-type SOTB substrate bias circuit 51 and an N-type SOTB substrate corresponding to the SOTB region 3. A bias circuit 61 is provided. Further, the power supply control circuit 7 shown in FIG. 1 has been modified to control these SOTB board bias circuits to become the power supply control circuit 7B. Further, smoothing capacitors 201 to 204 corresponding to the respective substrate bias circuits are connected to the corresponding substrate bias circuits via external terminals PT_C1 to PT_C4.

In FIG. 5, the SOTB region 2_1 shown in FIG. 1 is omitted, and the switch set S2 of the board bias changeover switch 4 is drawn as one circuit block.

The P-type SOTB board bias circuits 51 and 52, the N-type SOTB board bias circuits 61 and 62, and the power supply control circuit 7B are the P-type SOTB board bias circuit 5, the N-type SOTB board bias circuit 6, and the power supply control circuit of the first embodiment. Similar to No. 7, it is arranged in the bulk silicon region 1.

The power supply control circuit 7B detects the rise of the external power supply voltage Vcc and operates the P-type SOTB board bias circuits 51 and 52, the N-type SOTB board bias circuits 61 and 62, and the internal power supply circuit 9 so as to operate the P-type SOTB. It controls the board bias circuits 51 and 52, the N-type SOTB board bias circuits 61 and 62, and the internal power supply circuit 9.

The P-type SOTB substrate bias circuits 51 and 52 generate substrate bias voltages Vbp1 and Vbp2 by initiating operation. Similarly, the N-type SOTB substrate bias circuits 61 and 62 generate substrate bias voltages Vbn1 and Vbn2 by initiating operation. The values of the generated substrate bias voltages Vbp1 and Vbp2 are higher than the internal power supply voltage Vdd, and the values of the substrate bias voltages Vbn1 and Vbn2 are lower than the ground voltage Vss. Further, in the second embodiment, although not particularly limited, the substrate bias voltages Vbp1 and Vbp2 are different values, and the substrate bias voltages Vbn1 and Vbn2 are different values. Of course, the substrate bias voltages Vbp1 and Vbp2 may have the same value, and the substrate bias voltages Vbn1 and Vbn2 may have the same value.

The substrate bias voltages Vbp2 and Vbn2 are constantly supplied to the SOTB region 2. That is, the substrate bias voltage Vbp2 is constantly supplied to the substrate gate electrode BG of the P-type SOTB transistor SP2 formed in the SOTB region 2, and the substrate bias voltage Vbn2 is the N-type SOTB transistor SN2 formed in the SOTB region 2. It is always supplied to the substrate gate electrode BG of.

The substrate bias voltages Vbp1 and Vbn1 are supplied to the substrate bias changeover switch 4 in the same manner as the substrate bias voltages Vbp and Vbn shown in FIG. In the bias switching control circuit 8, similarly to the first embodiment, the board bias switching switch 4 selects the board bias voltage Vbp1, Vbn1 or the internal power supply voltage Vdd, and the ground voltage Vss according to the operation mode, and enters the SOTB region 3. Supply. As a result, when the low-speed mode is specified as the operation mode, the substrate bias voltage Vbp1 is supplied to the substrate gate electrode BG of the P-type SOTB transistor SP3 formed in the SOTB region 3, and the substrate of the N-type SOTB transistor SN3 is supplied. The substrate bias voltage Vbn1 is supplied to the gate electrode BG.

The layout of the semiconductor device 1B according to the second embodiment is similar to that of FIG. That is, in FIG. 2, instead of the P-type SOTB board bias circuit 5 and the N-type SOTB board bias circuit 6, the P-type SOTB board bias circuits 51 and 52 and the N-type SOTB board bias circuits 61 and 62 are located in the bulk silicon region 1. It will be placed. Further, in FIG. 2, the power supply control circuit 7B is arranged in the bulk silicon region 1 instead of the power supply control circuit 7.

In the second embodiment, the SOTB board bias circuit includes a SOTB board bias circuit corresponding to the SOTB area 2 and a SOTB board bias circuit corresponding to the SOTB area 3. Therefore, the SOTB substrate bias circuit can generate a substrate bias voltage of a value suitable for each SOTB region, and can more appropriately reduce power consumption.

FIG. 6 is a waveform diagram showing the operation of the semiconductor device according to the second embodiment. Since FIG. 6 is similar to FIG. 4, the differences will be mainly described.

When the power supply control circuit 7B according to the second embodiment detects the rise of the external power supply voltage Vcc, the power supply control circuit 7B operates the P-type SOTB board bias circuit 52 and the N-type SOTB board bias circuit 62. After that, the power supply control circuit 7B operates the internal power supply circuit 9. Further, after operating the internal power supply circuit 9, the power supply control circuit 7B operates the P-type SOTB board bias circuit 51 and the N-type SOTB board bias circuit 61.

As a result, at time t1, the P-type SOTB board bias circuit 52 and the N-type SOTB board bias circuit 62 start operating, and the board bias voltages Vbp2 and Vbn2 are generated. The generated substrate bias voltages Vbp2 and Vbn2 are supplied to the substrate gate electrodes BG of the P-type SOTB transistor SP2 and the N-type SOTB transistor SN2 formed in the SOTB region 2 (time t1).

Then, at time t2, the internal power supply circuit 9 generates the internal power supply voltage Vdd. Between the time t2 and the time t3, the P-type SOTB board bias circuit 51 and the N-type SOTB board bias circuit 61 start operating, and the board bias voltages Vbp1 and Vbn1 are generated. Since the high-speed mode is specified when the external power supply voltage Vcc is turned on, the board bias changeover switch 4 selects the internal power supply voltage Vdd and the ground voltage Vss at time t2. During the period in which the high-speed mode is specified, the board bias changeover switch 4 continues to select the internal power supply voltage Vdd and the ground voltage Vss. Therefore, even if the substrate bias voltages Vbp1 and Vbn1 are generated, during the period in which the high-speed mode is specified, the substrate gate electrodes BG of the P-type SOTB transistor SP3 and the N-type SOTB transistor SN3 formed in the SOTB region 3 are used. The internal power supply voltage Vdd and the ground voltage Vss are continuously supplied.

At time t4, the operation mode is changed to the low speed mode, and the state of the board bias changeover switch 4 changes. That is, the substrate bias changeover switch 4 changes to a state in which the substrate bias voltages Vbp1 and Vbn1 are selected. As a result, when the low-speed mode is specified, the substrate bias voltages Vbp1 and Vbn1 are supplied to the substrate gate electrodes BG of the P-type SOTB transistor SP3 and the N-type SOTB transistor SN3 formed in the SOTB region 3. .. In other words, the internal power supply voltage Vdd and the ground voltage Vss are not supplied to the substrate gate electrode BG of the P-type SOTB transistor SP3 and the N-type SOTB transistor SN3.

When the high-speed mode is specified again at time t6, the board bias changeover switch 4 selects the internal power supply voltage Vdd and the ground voltage Vss. As a result, the internal power supply voltage Vdd and the ground voltage Vss are supplied to the substrate gate electrodes BG of the SOTB transistors SP3 and SN3 formed in the SOTB region 3 instead of the substrate bias voltages Vbp1 and Vbn1.

On the other hand, the substrate bias voltages Vbp2 and Vbn2 are continuously supplied to the substrate gate electrodes of the P-type SOTB transistor and the N-type SOTB transistor formed in the SOTB region 2 regardless of the operation mode.

In the second embodiment as well, the semiconductor device 1B may be started from the low speed mode when the external power supply voltage Vcc is applied, as in the first embodiment. Further, as in the first embodiment, the bias switching control circuit 8 may be provided with a register for setting the operation mode.

Further, FIG. 6 shows an example in which the P-type SOTB board bias circuit 51 and the N-type SOTB board bias circuit 61 are operated after the internal power supply voltage Vdd is generated, but the present invention is not limited to this. For example, the P-type SOTB board bias circuit 51 and the N-type SOTB board bias circuit 61 may be operated before the internal power supply voltage Vdd is generated. Further, when the mode is changed from the low speed mode to the high speed mode, the P-type SOTB board bias circuit 51 and the N-type SOTB board bias circuit 61 may be stopped to reduce the power consumption.

In the SOTB region 2, a low-speed operation circuit that does not need to switch the substrate bias voltage is arranged. It is desirable to supply a substrate bias voltage to such a SOTB region 2 immediately after startup to reduce power consumption. Therefore, the P-type SOTB board bias circuit 52 and the N-type SOTB board bias circuit 62 can be configured to be able to operate faster than the P-type SOTB board bias circuit 51 and the N-type SOTB board bias circuit 61. desirable.

According to the second embodiment, it is possible to supply different values of substrate bias voltages to a plurality of SOTB regions separated from each other, such as SOTB regions 2 and 3. As a result, it is possible to supply a substrate bias voltage suitable for the SOTB transistors formed in each SOTB region, and it is possible to further reduce power consumption.

Further, when the substrate bias voltage of the same value is generated by a plurality of SOTB substrate bias circuits, each SOTB substrate bias circuit only supplies the substrate bias voltage to the corresponding SOTB region, and thus the SOTB substrate. It is possible to reduce the load on the bias circuit. Further, the SOTB substrate bias circuit can be arranged close to the corresponding SOTB region.

Also in the second embodiment, as shown in FIG. 5, each substrate bias circuit is connected to the smoothing capacitors 201 to 204 via the external terminals PT_C1 to PT_C4. Similar to the first embodiment, these smoothing capacitors function to suppress fluctuations in the substrate bias voltage when the substrate bias voltage is supplied to the SOTB regions 2 and 3. Further, the smoothing capacitor functions to shorten the supply time of the substrate bias voltage to the SOTB region 3. In FIG. 5, the corresponding smoothing capacitors are connected to all the board bias circuits, but since the board bias voltage does not fluctuate due to the switch, the smoothing capacitors 203 and 204 may not be provided. good.

(Embodiment 3)
FIG. 7 is a block diagram showing a configuration of the semiconductor device according to the third embodiment. In FIG. 7, 1C shows a semiconductor device. Since the semiconductor device 1C is similar to the semiconductor device 1B shown in FIG. 5, the differences will be mainly described. The main difference is that the board bias selection circuits 302 and 303 and the board bias selection control circuit 11 are added.

FIG. 9 is a plan view showing the configuration of the semiconductor device according to the third embodiment. As shown in FIG. 9, the board bias selection circuits 302 and 303 and the board bias selection control circuit 11 are arranged in the bulk silicon region 1 and operate using the external power supply voltage Vcc as the power supply voltage.

In the third embodiment, the P-type SOTB board bias circuit 51 and the P-type SOTB board bias circuit 52 generate board bias voltages Vbp1 and Vbp2 which are higher than the internal power supply voltage Vdd and have different values from each other. Further, the N-type SOTB board bias circuit 61 and the N-type SOTB board bias circuit 62 generate board bias voltages Vbn1 and Vbn2 which are lower than the ground voltage Vss and have different values from each other.

As shown in FIG. 7, the substrate bias voltages Vbp1, Vbp2, Vbn1 and Vbn2 are supplied to the substrate bias selection circuits 302 and 303. The board bias selection circuit 302 includes switches SL2_1 and SL2_2 controlled by the board bias selection control circuit 11. Further, the substrate bias selection circuit 303 includes switches SL3_1 and SL3_2 controlled by the substrate bias selection control circuit 11.

In the board bias selection circuit (first selection circuit) 302, one of the board bias voltages Vbp1 and Vbp2 is selected by the switch SL2_1 under the control of the board bias selection control circuit 11, and the board bias voltages Vbn1 and Vbn2 are further selected. One of them is selected by the switch SL2_2. The voltage selected from the substrate bias voltages Vbp1 and Vbp2 is constantly output from the substrate bias selection circuit 302 to the SOTB region 2 as the substrate bias voltage Vbp31. Further, the voltage selected from the substrate bias voltages Vbn1 and Vbn2 is constantly output from the substrate bias selection circuit 302 to the SOTB region 2 as the substrate bias voltage Vbn31.

In the board bias selection circuit (second selection circuit) 303, one of the board bias voltages Vbp1 and Vbp2 is selected by the switch SL3_1 under the control of the board bias selection control circuit 11, and the board bias voltages Vbn1 and Vbn2 are further selected. One of them is selected by the switch SL3_2. The voltage selected from the board bias voltages Vbp1 and Vbp2 is output from the board bias selection circuit 303 to the board bias changeover switch 4 as the board bias voltage Vbp32. Further, the voltage selected from the board bias voltages Vbn1 and Vbn2 is output from the board bias selection circuit 302 to the board bias changeover switch 4 as the board bias voltage Vbn32.

In the board bias changeover switch 4, the internal power supply voltage Vdd and the ground voltage Vss are selected and supplied to the SOTB region 3 during the high-speed mode period, and the board bias voltages Vbp32 and Vbn32 are supplied to the SOTB region during the low-speed mode period. Supply to 3.

The substrate bias voltages Vbp1 and Vbp2 are voltages suitable for the P-type SOTB transistors formed in the SOTB regions 2 and 3, and the substrate bias voltages Vbn1 and Vbn2 are the N-type SOTB transistors formed in the SOTB regions 2 and 3. It is said to be a suitable voltage.

The board bias selection control circuit 11 controls the switches SL2_1, SL2_2, SL3_1, and SL3_2 in the board bias selection circuits 302 and 303 according to the instruction from the processor 301.

FIG. 8 is a waveform diagram showing the operation of the semiconductor device according to the third embodiment. Since FIG. 8 is similar to FIG. 6 and the like, the differences will be mainly described.

When the external power supply voltage Vcc rises, the power supply control circuit 7B controls the P-type SOTB board bias circuits 51 and 52, the N-type SOTB board bias circuits 61 and 62, and the internal power supply circuit 9. That is, upon detecting the rise of the external power supply voltage Vcc, the power supply control circuit 7B operates the P-type SOTB board bias circuits 51 and 52 and the N-type SOTB board bias circuits 61 and 62 at time t1. Then, at time t2, the power supply control circuit 7B operates the internal power supply circuit 9. As a result, the substrate bias voltages Vbp1, Vbp2, Vbn1, Vbn2 and the internal power supply voltage vdd are generated.

At time t2_3, the board bias selection control circuit 11 controls the board bias selection circuits 302 and 303 according to an instruction from the processor 301. By this control, the voltage selected from the substrate bias voltages Vbp1 and Vbp2 by the substrate bias selection circuit 302 is supplied to the SOTB region 2 as the substrate bias voltage Vbp31. Further, the voltage selected from the substrate bias voltages Vbn1 and Vbn2 by the substrate bias selection circuit 302 is supplied to the SOTB region 2 as the substrate bias voltage Vpn31.

Further, at time t2_3, the voltage selected from the substrate bias voltages Vbp1 and Vbp2 by the substrate bias selection circuit 303 is supplied to the substrate bias changeover switch 4 as the substrate bias voltage Vbp32. Further, the voltage selected from the board bias voltages Vbn1 and Vbn2 by the board bias selection circuit 303 is supplied to the board bias changeover switch 4 as the board bias voltage Vbn32.

In the high-speed mode, the board bias changeover switch 4 supplies the internal power supply voltage Vdd and the ground voltage Vss to the SOTB region 3. As a result, in the high-speed mode, the circuit blocks such as the processor 301 arranged in the SOTB area 3 operate at high speed.

When the low speed mode is instructed at time t4, the substrate bias changeover switch 4 supplies the substrate bias voltages Vbp32 and Vbn32 to the SOTB region 3. As a result, in the low speed mode, the power consumption in the circuit block arranged in the SOTB region 3 is suppressed.

When the high-speed mode is specified again at time t6, the board bias changeover switch 4 supplies the internal power supply voltage Vdd and the ground voltage Vss to the SOTB region 3.

On the other hand, the substrate bias voltages Vbp31 and Vbn31 are continuously supplied to the SOTB region 2 regardless of the operation mode.

In the third embodiment as well, the semiconductor device 1C may be started from the low speed mode when the external power supply voltage Vcc is applied, as in the first and second embodiments. Further, as in the first and second embodiments, the bias switching control circuit 8 may be provided with a register for setting the operation mode.

According to the third embodiment, the value of the substrate bias voltage supplied to the SOTB regions 2 and 3 can be further arbitrarily set, and further low power consumption can be achieved.

Here, the case where the substrate bias voltages Vbp1 and Vbp2 are different values and the substrate bias voltages Vbn1 and Vbn2 are different values has been described as an example, but the present invention is not limited to this. For example, the substrate bias voltages Vbp1 and Vbp2 may have the same value, or the substrate bias voltages Vbn1 and Vbn2 may have the same value. Of course, the substrate bias voltages Vbp1 and Vbp2 may have the same value, and the substrate bias voltages Vbn1 and Vbn2 may have the same value.

Further, the voltage value of the substrate bias voltage supplied to the SOTB region 2 may be configured to be switchable between the high-speed mode and the low-speed mode by the substrate bias selection circuit 302. This makes it possible to supply the substrate bias voltage according to the operation mode.

Further, the voltage value of the substrate bias voltage supplied to the SOTB region 3 may be configured to be switchable during the period of operation in the low speed mode.

Also in the third embodiment, as in the second embodiment, the corresponding smoothing capacitors 201 to 204 are connected to each of the substrate bias circuits via the external terminals PT_C1 to PT_C4. In the third embodiment, unlike the second embodiment, it is desirable that the smoothing capacitors 203 and 204 are provided.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say. For example, in the bulk silicon region 1, not only a circuit block related to voltage generation but also a circuit block such as a flash memory may be arranged.

1 Bulk silicon region 1A to 1C Semiconductor device 2, 3 SOTB region 4 Board bias changeover switch 5 P-type SOTB board bias circuit 6 N-type SOTB board bias circuit 7, 7B, 7C Power supply control circuit 8 Bias switching control circuit 9 Internal power supply circuit NM N-type MOS transistor PMP-type MOS transistor SL2_1, SL2_2, SL3_1, SL3_2, SW1, SW2 switch SN2, SN3 N-type SOTB transistor SP2, SP3 P-type SOTB transistor Vbn, Vbn1, Vbn2, Vbn31, Vbn32 Substrate bias voltage Vbp, Vbp1, Vbp2, Vbp31, Vbp32 Board bias voltage Vcc External power supply voltage Vdd Internal power supply voltage

Claims (13)

The bulk area where the transistors were formed and
In the first SOTB region where the SOTB transistor was formed,
The second SOTB region, which is separated from the first SOTB region and in which the SOTB transistor is formed,
With
A semiconductor device in which a substrate bias voltage is constantly supplied to the first SOTB region, and supply of a substrate bias voltage can be selected for the second SOTB region. In the semiconductor device according to claim 1,
A semiconductor device in which the bulk region, the first SOTB region, and the second SOTB region are arranged on a common substrate. In the semiconductor device according to claim 2,
The SOTB transistor formed in the first SOTB region includes a P-type SOTB transistor and an N-type SOTB transistor.
The SOTB transistor formed in the second SOTB region includes a P-type SOTB transistor and an N-type SOTB transistor.
The semiconductor device is
An internal power supply circuit that generates an internal power supply voltage based on the external power supply voltage,
A P-type SOTB board bias circuit that generates a board bias voltage for a P-type SOTB transistor from the external power supply voltage, and a P-type SOTB board bias circuit.
An N-type SOTB board bias circuit that generates a board bias voltage for an N-type SOTB transistor from the external power supply voltage, and an N-type SOTB board bias circuit.
A switch circuit coupled between the second SOTB region, the P-type SOTB board bias circuit, and the N-type SOTB board bias circuit, and
With
A semiconductor device in which the internal power supply circuit, the P-type SOTB board bias circuit, the N-type SOTB board bias circuit, and the switch circuit are arranged in the bulk region. In the semiconductor device according to claim 3,
A semiconductor device in which a substrate bias voltage generated by the P-type SOTB substrate bias circuit and a substrate bias voltage generated by the N-type SOTB substrate bias circuit are constantly supplied to the first SOTB region. In the semiconductor device according to claim 4,
The switch circuit is a semiconductor device that supplies a substrate bias voltage or a predetermined voltage generated by the P-type SOTB substrate bias circuit and the N-type SOTB substrate bias circuit to the second SOTB region. In the semiconductor device according to claim 5,
A semiconductor device in which a processor that controls the switch circuit is arranged in the second SOTB region. In the semiconductor device according to claim 6,
A plurality of electrodes to which a substrate bias voltage generated by the P-type SOTB substrate bias circuit is supplied to each of the first SOTB region and the second SOTB region, and a substrate bias generated by the N-type SOTB substrate bias circuit. A semiconductor device in which a plurality of electrodes to which a voltage is supplied are arranged. In the semiconductor device according to claim 3,
In the bulk region, the P-type SOTB board bias circuit, the N-type SOTB board bias circuit, and the power supply control circuit for controlling the internal power supply circuit are arranged.
The power supply control circuit is a semiconductor device that operates the internal power supply circuit after operating the P-type SOTB board bias circuit and the N-type SOTB board bias circuit. In the semiconductor device according to claim 8,
In the first SOTB region, a real-time clock circuit composed of the SOTB transistors and operating using the internal power supply voltage as a power source is arranged.
A semiconductor device in which a processor composed of the SOTB transistors and operating using the internal power supply voltage as a power source is arranged in the second SOTB region. In the semiconductor device according to claim 1,
A semiconductor device in which the value of the substrate bias voltage supplied to the second SOTB region is different from the value of the substrate bias voltage supplied to the first SOTB region. In the semiconductor device according to claim 3,
Each of the P-type SOTB substrate bias circuit and the N-type SOTB bias circuit generates a plurality of substrate bias voltages having different values from each other.
The first selection circuit that selects the substrate bias voltage supplied to the first SOTB region from the plurality of substrate bias voltages, and the substrate bias voltage supplied to the second SOTB region from the plurality of substrate bias voltages are selected. A semiconductor device further comprising a second selection circuit. In the semiconductor device according to claim 2,
It has a switch circuit for selecting the supply of the substrate bias voltage with respect to the second SOTB region.
The switch circuit is a semiconductor device arranged in the bulk region. In the semiconductor device according to claim 2,
A semiconductor device in which the substrate bias voltage supplied to the first SOTB region is selected and supplied from substrate bias voltages having a plurality of different voltage values.

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