JP2021158563A - Device and method for data processing - Google Patents

Abstract

To substitute the function of a fault part using a redundant circuit to automatically recover data processing, in an integrated circuit in which a variety of types of functional processors are combined.SOLUTION: A data processing device, which performs automatic recovery using a programmable redundant circuit, includes: a plurality of types of processing units which perform data processing; a programmable redundant circuit; and a control unit which, when a fault is detected in one of the processing units, stores a code necessary to exhibit the function of the processing unit having the detected fault, so as to configure a packet route in a manner to divert the processing unit having the detected fault, to pass through the redundant circuit. The redundant circuit executes data processing based on the stored code to substitute the function of the processing unit having the detected fault.SELECTED DRAWING: Figure 1

Description

The present invention relates to a data processing apparatus and a data processing method that automatically recover using a programmable redundant circuit.

Conventionally, a technique for providing an integrated circuit having a repairable logic region has been known. For example, Patent Document 1 discloses a switching process (detour process) for bypassing to a spare line when a failure occurs in a programmable integrated circuit such as an FPGA. More specifically, the integrated circuit described in Patent Document 1 has a logical region having a network of a plurality of rows including a network of spare rows, and each of the plurality of routing segments has a plurality of rows. It has a first end coupled to each one of the networks of a plurality of rows and an opposite second end coupled to an adjacent one of the networks of multiple rows. Also, each of the plurality of detour circuits is coupled between each pair of the plurality of routing segments. The plurality of bypass circuits can then operate to switch to use the spare row if one of the networks of the plurality of rows contains a defective circuit, and each routing segment is among the plurality of bypass circuits. It is driven by an associated routing segment using each one of.

Further, Patent Gazette 2 discloses a technique for changing the association of accelerators to be executed for each application. More specifically, the accelerator management device described in Patent Document 2 has an accelerator association DB that stores the accelerator identifier in association with the application identifier. The accelerator management device has an accelerator mounting information DB that stores the accelerator identifier of the accelerator mounted in the slot in association with each slot identifier that identifies each slot of the extended I / O box. Then, when the accelerator management device receives the execution request of the application from the host, the accelerator management device specifies the accelerator identifier corresponding to the application from the accelerator association DB. The accelerator management device specifies the slot identifier corresponding to the specified accelerator identifier from the accelerator mounting information DB. The accelerator management device assigns the slot identified by the identified slot identifier to the host.

Japanese Unexamined Patent Publication No. 2014-093782 Japanese Unexamined Patent Publication No. 2013-196206

However, in the technique described in Patent Gazette 1, when a failure occurs, the line used when a failure occurs slides down from the failure location and switches / routes so as to bypass the failure location, so that the function can be recovered only by switching control. On the other hand, if the circuit has already been burned, it will be necessary to burn it again in the detour configuration. Further, since the original circuit is written as it is in the spare line, only the same integrated circuit can be used as a spare, and it cannot be used for an integrated circuit composed of a plurality of circuits.

Further, in the technique described in Patent Gazette 2, the accelerator and the server (CPU) that controls the accelerator are separated into a housing (physical). Even if the server (CPU) fails, the CPU-accelerator combination corresponding to the application can be dynamically changed via the management server to continue the application. That is, even if a certain CPU is broken, the accelerator can be continuously used by switching to go through another CPU. However, since this switching method is basically a method of bypassing to the same type of hardware as the failed hardware, the same type of hardware must be prepared.

The present invention has been made in view of such circumstances, and is a data processing apparatus capable of changing the processing path of an internal circuit and dynamically writing to a programmable integrated circuit according to a faulty part. And to provide a data processing method.

(1) In order to achieve the above object, the present invention has taken the following measures. That is, the data processing device of the present invention is a data processing device that automatically recovers using a programmable redundant circuit, and may be a plurality of types of processing units that perform data processing or a programmable redundant circuit. When a failure of the processing unit is detected, the code necessary for exerting the function of the processing unit in which the failure is detected is written in the redundant circuit, and the processing unit in which the failure is detected is bypassed. Then, a control unit for constructing a packet route so as to pass through the redundant circuit is provided, and the redundant circuit performs data processing based on the written code, whereby a failure is detected. It is characterized in that it substitutes the function of the processing unit.
(2) Further, in the data processing apparatus of the present invention, the control unit has a write code storage unit that records a plurality of types of codes necessary for exerting the functions of the respective processing units, and a failure of the respective processing units. A failure detection unit that detects a failure, a failure location determination control unit that determines which processing unit has failed, and a code selection unit that selects a code corresponding to the failed processing unit from the writing code storage unit. It is provided with a writing unit for writing the code to the redundant circuit and a route management unit for constructing a packet route so as to bypass the processing unit in which a failure is detected and pass through the redundant circuit. It is a feature.

(3) Further, in the data processing apparatus of the present invention, each processing unit includes a switching unit that switches a packet output destination based on a route constructed by the route management unit.

(4) Further, the data processing apparatus of the present invention is further provided with a switch circuit connected to each of the processing units and switching between input and output of packets based on a route constructed by the route management unit. ..

(5) Further, in the data processing apparatus of the present invention, the control unit is characterized in that the parameters of the code are adapted based on the performance of the redundant circuit.

(6) Further, the data processing method of the present invention is a data processing method of a data processing apparatus that automatically recovers using a programmable redundant circuit, and is a step of detecting a failure of any one of the processing units. Then, the step of writing the code necessary for exerting the function of the processing unit in which the failure is detected to the redundant circuit and the process bypassing the processing unit in which the failure is detected are bypassed so as to pass through the redundant circuit. , And at least a step of constructing a packet path, characterized in that the redundant circuit substitutes the function of the processing unit in which a failure is detected by performing data processing based on the written code. And.

According to the present invention, even if a part of the processor is damaged, it can be automatically recovered, and the function can be continuously realized. In addition, the scale of the hardware configuration can be reduced.

It is a figure which shows the schematic structure of the data processing apparatus 1 which concerns on this embodiment. It is a figure which shows the schematic structure of the integrated circuit 3 in the data processing apparatus 1. It is a figure which shows the modification 1 of the integrated circuit 3 in the data processing apparatus 1. It is a figure which shows the modification 2 of the integrated circuit 3 in the data processing apparatus 1. It is a flowchart which shows the operation of the data processing apparatus which concerns on this embodiment. It is a figure which shows the processing flow of a normal data processing apparatus. It is a figure which shows the flow of processing when a failure occurs. It is a figure which shows the operation at the time of a failure. It is a figure which shows the operation at the time of a failure. It is a figure which shows the state of failure detection. It is a figure which shows the state of failure detection. It is a figure which shows the state which returned the determination of the output to a test circuit (redundant circuit 15). It is a figure which shows the code for exerting the function of the failure GPU in the redundant circuit 15. As a modification, it is a figure which shows the structure which provided the switch 40.

The present inventors have focused on an FPGA (Field Programmable Gate Array) being a programmable integrated circuit, and in an integrated circuit combining various functional processors such as a chiplet, the failure point of the chiplet is found. Accordingly, they have found that automatic recovery can be performed on a small circuit scale by changing the processing path of the internal circuit and dynamically writing to the FPGA, and have reached the present invention.

That is, the data processing device of the present invention is a data processing device that automatically recovers using a programmable redundant circuit, and may be a plurality of types of processing units that perform data processing or a programmable redundant circuit. When a failure of the processing unit is detected, the code necessary for exerting the function of the processing unit in which the failure is detected is written in the redundant circuit, and the processing unit in which the failure is detected is bypassed. Then, a control unit for constructing a packet route so as to pass through the redundant circuit is provided, and the redundant circuit performs data processing based on the written code, whereby a failure is detected. It is characterized in that it substitutes the function of the processing unit.

As a result, the present inventors have made it possible to automatically recover even if a part of the processor is damaged, and to continuously realize the function. It also made it possible to reduce the scale of the hardware configuration. Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a data processing device 1 according to the present embodiment, and FIG. 2A is a diagram showing a schematic configuration of an integrated circuit 3 of the data processing device 1. The data processing device 1 is composed of an integrated circuit 3 having a plurality of types of chiplets and a control unit 5. The integrated circuit 3 is composed of an FPGA (Field Programmable Gate Array), a chiplet 7 that performs packet filtering processing, and a chiplet 9 that is composed of an ASIC (Application Specific Integrated Circuit) and performs encryption processing, and a GPU (Graphics Processing Unit). The chiplet 11 is composed of a chiplet 11 and performs a routing process, and the chiplet 13 is composed of an FPGA and performs a tunneling process. Each chiplet 7, 9, 11, 13 includes switching 7a, 9a, 11a, 13a and memories 7b, 9b, 11b, 13b, respectively. With this configuration, each chiplet can exert a function of switching between a main circuit and a detour.

Further, it includes a redundant circuit 15 composed of FPGA, a switching circuit 15a, and a memory 15b. The redundant circuit 15 is a programmable FPGA, and by selecting a program according to the failed processor (chip) and burning it into the redundant circuit 15, it is possible to automatically repair the failure. As a result, it is realized as a redundant configuration of "N + 1" regardless of the number of variations of the processor used in the circuit having N functions. Further, as will be described later, it is possible to realize a plurality of detour routes by using the redundant circuit 15 and detect the location of the failed processor from the plurality of output results.

In the present embodiment, by dynamically burning the redundant circuit 15 composed of the FPGA, the redundant part to be prepared in the configuration of a plurality of types of processors can be limited to the FPGA. As a result, spare parts such as GPU and ASIC are not required. In addition, by maintaining switching / routing and physical redundant connections, a plurality of detour processing routes are realized. Further, by using the above-mentioned plurality of detour circuits and sample input, it is possible to identify the failed circuit unit (processor) from the detour route that outputs an unexpected result.

It should be noted that the performance (throughput and delay) is higher than that before the failure because the functions that are originally processed by the hardware (ASIC or GPU) suitable for the processing are processed by the FPGA as the redundant circuit 15. It is possible that it is inferior. However, the detour from FPGA to FPGA is likely to be equivalent.

Further, in the control unit 5 shown in FIG. 1, the writing code storage unit 17 records a plurality of types of codes necessary for exerting the function of each chiplet. The failure detection unit 19 detects the name of each chiplet of the integrated circuit 3, and the failure location determination control unit 21 determines which chiplet has failed. The writing code selection unit 23 selects a code corresponding to the failed chiplet from the writing code storage unit 17. The writing unit 25 writes the code selected by the writing code selection unit 23 to the redundant circuit 15. The integrated circuit route management unit 27 constructs a packet route so as to bypass the chiplet in which a failure is detected and pass through the redundant circuit 15. The redundant FPGA memory copy control unit 29 temporarily records data when writing the code to the redundant circuit 15, and the execution program control unit 31 controls the code to be executed for each chiplet and outputs the result to the chip. Read with a let. Further, the integrated circuit 3 transmits / receives packets to / from the adjacent processors 33 and 37 in order to perform data processing (for example, packet processing). In the above configuration example, the failure detection unit 19 detects the failure and the failure location determination control unit 21 determines the failed chiplet. However, the present invention is not limited to this, and any chiplet is not limited to this. It is also possible to input from an external device whether or not the device has failed, or to input directly by the operator.

FIG. 2B is a diagram showing a modification 1 of the integrated circuit 3 in the data processing device 1, and FIG. 2C is a diagram showing a modification 2 of the integrated circuit 3 in the data processing device 1. As shown in FIGS. 2B and 2C, the integrated circuit 3 may have switching circuits 40 and 42 between the adjacent processors 33 and 37. When the switching circuits 40 and 42 are not recognized by the adjacent processors 33 and 37, the configuration shown in FIG. 2B is adopted so that the switching circuits 40 and 42 can be switched inside the integrated circuit 3. On the other hand, when the switching circuits 40 and 42 are switched by the adjacent processors 33 and 37, the configuration shown in FIG. 2C is adopted. This makes it possible to pass through the redundant circuit 15.

Next, processing when one of the chiplets fails will be described. FIG. 3 is a flowchart showing the operation of the data processing device according to the present embodiment, FIG. 4 is a diagram showing a processing flow of a normal data processing device, and FIG. 5 is a process when a failure occurs. It is a figure which shows the flow of. When a failure occurs in any of the chiplets, the FPGA code corresponding to the function of substituting the failed part is searched for while bypassing the redundant circuit 15 in a form of avoiding the failed chiplet. Write the code to the redundant circuit 15. Here, an example in which the chiplet 11 composed of the GPU fails, a detour circuit is constructed, and the code for demonstrating the function as the GPU is burned into the redundant circuit 15 so that the redundant circuit 15 functions as the GPU. Is shown. After constructing the detour, the failed chiplet 11 may be repaired or replaced to restore the route.

6 and 7 are diagrams showing the operation at the time of failure. When a circuit failure occurs, nothing is output or an invalid output is output. In either case, there is no way to know the failure in the integrated circuit itself unless there is an individual alarm from each processor. Therefore, in reality, it is necessary to detect the entire system in the processing after the chiplet. It can be a service level or a filter at a tunnel destination node. That is, for failure detection, basically, error logs from hardware and so-called "life and death monitoring" in the chip are the basics, but depending on the failure pattern, it may be difficult to output error logs. Even if there is no problem in alive monitoring, there is a possibility that the desired processing is not performed (silent failure), so detection by the entire system is also necessary. If it is systematically known that there is a failure by those means, it can be detected by using the sample input and the test circuit (redundant circuit 15) in the integrated circuit 3.

In FIG. 3, first, the failure detection unit 19 of the control unit 5 detects a failure (step S1), and the failure location determination control unit 21 determines which chiplet has failed (step S2). Here, it is assumed that the chiplet 11 as the GPU has failed. The writing code selection unit 23 selects a code for causing the redundant circuit 15 made of FPGA to function as a GPU (step S3), and the writing unit 25 writes the selected code to the redundant circuit 15 (step S4). Next, as shown in FIG. 5, the integrated circuit route management unit 27 selects a detour so as to bypass the chiplet 11 (step S5), switches the route (step S6), and ends. This makes it possible to automatically recover from the failure.

8 and 9 are diagrams showing a state of failure detection. When there is a suspicion of failure in the chiplet 11 made of GPU, a test code is written to the redundant circuit 15 from the external system, a sample input is generated, and the sample input is input to the suspected circuit (chiplet 11). .. Then, check whether the output is expected on the output side. Select a test code or sample code for each circuit that is expected to fail, and switch the internal bypass connection. In FIGS. 8 and 9, since the chiplet 11 as the GPU that performs the routing process has a failure, no problem occurs in the inspection of the tunneling process in the chiplet 13 (assumed output), but the output is in the routing process. There is no or unexpected output, and it can be seen that there is a problem with the routing process.

FIG. 10 is a diagram showing how the output determination is returned to the test circuit (redundant circuit 15). This method can be used to determine other than the beginning and end of the processing flow. When trying to judge the beginning and the end, it is necessary to judge at the adjacent processor or service level. This time, the tests are conducted in order from the output side circuit, but the number of times can be reduced by a method such as a binary tree search. In addition, since the original function cannot be provided during the test, it is necessary to take measures such as temporarily stopping the service or bypassing to another circuit or housing if the service is to be continued. Further, in the present embodiment, the test is performed in the circuit due to the configuration, but the test may be performed over different housings.

FIG. 11 is a diagram showing a code for the redundant circuit 15 to exert the function of the failed GPU. The redundant circuit 15 composed of FPGA can easily realize the same function in a common language such as OpenCL. Also, the difference in hardware is absorbed by the compiler, so it does not matter. However, considering the performance difference between FPGA and GPU, it may be necessary to change the parameters according to the number of hardware cores and threads. For example, the number of loop unrolls may be explicitly changed, that is, the number of parallels may be changed to increase the speed. In FIG. 11, when the number of cores is large in the failed GPU, it is not necessary to suppress the number of loop unrolls. However, in the FPGA as the redundant circuit 15, the number of look-up tables is not so large, so the number of loop unrolls is large. Since it is necessary to suppress to 4 and compile, change the parameter.

FIG. 12 is a diagram showing a configuration in which the switch 40 is provided as a modified example. The switch 40 makes it possible to switch the route so that the packet flows through the constructed detour.

As described above, according to the present embodiment, the scale of the circuit can be reduced by realizing "N + 1" redundancy in the integrated circuit 3 composed of a plurality of circuits. That is, even if some processors are damaged, the functions can be automatically and continuously realized.

1 Data processing device 3 Integrated circuit 5 Control unit 7, 9, 11, 13 Chiplet 15 Redundant circuit 15a Switching circuit 15b Memory 17 Writing code storage unit 19 Failure detection unit 21 Failure location determination control unit 23 Writing code selection unit 25 Writing unit 27 Integrated circuit route management unit 29 Redundant FPGA memory copy control unit 31 Execution program control unit 40, 42 Switching circuit

Claims (6)

A data processing device that automatically recovers using a programmable redundant circuit.
Multiple types of processing units that perform data processing,
Programmable redundant circuits and
When a failure of any of the processing units is detected, the code necessary for exerting the function of the processing unit in which the failure is detected is written in the redundant circuit, and the processing unit in which the failure is detected is written. A control unit that bypasses and constructs a packet route so as to pass through the redundant circuit is provided.
A data processing apparatus characterized in that the redundant circuit substitutes the function of the processing unit in which a failure is detected by performing data processing based on the written code. The control unit
A writing code storage unit that records a plurality of types of codes necessary for exerting the functions of each processing unit, and a writing code storage unit.
A failure detection unit that detects a failure in each of the processing units,
A failure location determination control unit that determines which processing unit has failed, and a failure location determination control unit.
A code selection unit that selects the code corresponding to the failed processing unit from the writing code storage unit, and
A writing unit that writes the selected code to the redundant circuit,
The data processing device according to claim 1, further comprising a route management unit that constructs a packet route so as to bypass the processing unit in which a failure is detected and pass through the redundant circuit. The data processing apparatus according to claim 2, wherein each processing unit includes a switching unit that switches a packet output destination based on a route constructed by the route management unit. The data processing apparatus according to claim 2, further comprising a switch circuit connected to each of the processing units and switching between input and output of packets based on a route constructed by the route management unit. The data processing device according to claim 1, wherein the control unit adapts parameters of the code based on the performance of the redundant circuit. It is a data processing method of a data processing device that automatically recovers using a programmable redundant circuit.
A step of detecting a failure of any of the processing units, and
The step of writing the code necessary for exerting the function of the processing unit in which the failure is detected to the redundant circuit, and
It includes at least a step of constructing a packet route so as to bypass the processing unit in which a failure is detected and pass through the redundant circuit.
A data processing method characterized in that the redundant circuit substitutes the function of the processing unit in which a failure is detected by performing data processing based on the written code.

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