JP2021156718A - Strain sensor module, method for correcting offset, and program - Google Patents

Abstract

To provide a strain sensor module, a method for correcting an offset, and a program that can precisely correct an offset of a detection signal output from a strain detection unit.SOLUTION: A strain sensor module 1 includes: a strain detection unit 11 forming a Wheatstone bridge circuit and having a first output transistor to a fourth output transistor M1r, M2r, M3r, and M4r, of which electron mobilities change according to the strain of a measurement target object, the strain detection unit outputting a detection signal according to the strain amount of the measurement target object; an offset correction unit 12 for correcting an offset of the detection signal output from the strain detection unit 11; a signal amplification unit 14 for amplifying the detection signal output from the strain detection unit 11; and a signal processing unit 16 for processing the detection signal output from the signal amplification unit 14.SELECTED DRAWING: Figure 1

Description

The present invention relates to a strain sensor module that detects distortion generated in a measurement object, an offset correction method that corrects an offset of a detection signal according to the amount of strain, and a program that executes offset correction.

Conventionally, dynamic strain has been detected for wear deterioration and abnormality diagnosis of structures such as industrial equipment and bridge girders. Specifically, in order to detect minute strain changes with high sensitivity, a strain detection element in which impurities are partially doped into a flaky silicon substrate to form a piezoresistive effect, or a metal thin film is formed on the silicon substrate. A strain detection element is used. Dynamic distortion is detected by adhering these strain detection elements to the object to be measured. Patent Documents 1 and 2 disclose a sensor device having a bridge circuit composed of detection elements in a distortion detection unit.

Since the strain detection element has film stress and manufacturing variation of the film constituting the strain detection element, the Wheatstone bridge circuit constituting the strain detection element does not have the output voltage assumed at the time of design with an extremely high probability, and the initial offset is set. appear. As a method of correcting the initial offset, a method of adjusting the resistance value of the Wheatstone bridge circuit is generally used.

Patent Document 1 describes a semiconductor that is provided separately from the strain gauge resistor that constitutes the bridge circuit and that adjusts the bridge circuit by using an adjustment circuit that is composed of a diffusion resistor, a plurality of wirings, and a plurality of Al pads. A method for adjusting a bridge circuit of a pressure sensor is disclosed.

Japanese Unexamined Patent Publication No. 63-118629 Japanese Unexamined Patent Publication No. 8-327482

The adjustment circuit disclosed in Patent Document 1 has a problem that the correction accuracy of the detection signal is limited because the resistance value of the bridge circuit can be corrected only within a predetermined adjustment interval and adjustment range. ing.

An object of the present invention is to provide a distortion sensor module, an offset correction method, and a program capable of correcting the offset of a detection signal output from a distortion detection unit with high accuracy.

The strain sensor module according to one aspect of the present invention has four field effect transistors that form a Wheatstone bridge circuit and whose electron mobility changes according to the strain of the object to be measured, and corresponds to the amount of strain of the object to be measured. A distortion detection unit that outputs the detection signal, an offset correction unit that corrects the offset of the detection signal output from the distortion detection unit, and a signal amplification unit that amplifies the detection signal output from the distortion detection unit. A signal processing unit that processes the detection signal output from the signal amplification unit is provided.

Further, the offset correction method according to one aspect of the present invention is an offset correction method for correcting the offset of the detection signal of the distortion detection unit that outputs a detection signal according to the amount of distortion of the object to be measured. The threshold voltage of the two electric field effect transistors arranged on the power supply side of the four electric field effect transistors whose electron mobility changes according to the strain of the object to be measured is adjusted to adjust the threshold voltage of the four electric field effect transistors. The two electric field effect transistors are set in a reference state in which no current flows through each of the residual electric field effect transistors arranged on the reference potential side of the effect transistors, and the threshold value of one of the residual electric field effect transistors is set. The voltage is controlled to set one of the electric field effect transistors to a predetermined state, and the threshold voltage of the other of the remaining electric field effect transistors is controlled to set the other electric field effect transistor to a predetermined state. Is set to, and the threshold voltage of one of the two electric field effect transistors is controlled to set the electric field effect transistor of the one to a predetermined state, and the other of the two electric field effect transistors is set to. The threshold voltage is controlled to set the other electric field effect transistor to a predetermined state.

Further, the program according to one aspect of the present invention comprises a computer having four field effect transistors that constitute a Wheatston bridge circuit and whose electron mobility changes according to the strain of the object to be measured, and the strain of the object to be measured. An offset correction unit that corrects the offset of the detection signal output from the distortion detection unit that outputs a detection signal according to the amount, a signal amplification unit that amplifies the detection signal detected by the distortion detection unit, and the signal amplification unit. It functions as a signal processing unit that processes the detection signal input from the unit, and causes the offset correction unit to execute the offset correction method of the present invention.

According to each aspect of the present invention, the offset of the detection signal output from the distortion detection unit can be corrected with high accuracy.

It is a block diagram which shows the schematic structure of the strain sensor module according to 1st Embodiment of this invention. It is a block diagram which shows concretely the schematic structure of the strain sensor module according to 1st Embodiment of this invention. It is a circuit diagram of the main part of the offset correction part provided in the distortion sensor module according to 1st Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the strain detection part provided in the strain sensor module according to 1st Embodiment of this invention. It is a top view of the main part of the output transistor and the writing element provided in the distortion detection part provided in the strain sensor module according to 1st Embodiment of this invention. It is sectional drawing of the writing element provided in the strain sensor module according to 1st Embodiment of this invention. It is sectional drawing of the output transistor which could be provided in the strain sensor module according to 1st Embodiment of this invention. It is a figure (the 1) which shows typically the plane and the cross section which shows the schematic structure of the strain detection part provided in the strain sensor module by 1st Embodiment of this invention. It is a figure (the 2) which shows typically the plane and the cross section which shows the schematic structure of the strain detection part provided in the strain sensor module by 1st Embodiment of this invention. It is a figure (the 1) which shows typically an example of the IV characteristic of the 1st to 4th output transistors provided in the strain sensor module according to 1st Embodiment of this invention. It is a figure (2) which shows typically an example of the IV characteristic of the 1st to 4th output transistors provided in the strain sensor module according to 1st Embodiment of this invention. It is a figure (the 1) for demonstrating the principle of offset correction and distortion erroneous detection in the strain sensor module according to 1st Embodiment of this invention. It is a figure (No. 2) for demonstrating the principle of offset correction and distortion erroneous detection in the strain sensor module according to 1st Embodiment of this invention. It is a flowchart which shows an example of the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a timing chart which shows an example of the setting process of the output voltage in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the 1st adjustment process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the 2nd adjustment process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the confirmation process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the 3rd adjustment process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the 4th adjustment process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the confirmation process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the 5th adjustment process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the 6th adjustment process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the confirmation process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the 7th adjustment process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the 8th adjustment process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the confirmation process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the connection state of the distortion detection part and the switch group in the 9th adjustment process in the offset correction method of the distortion sensor module by 1st Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the strain detection part provided in the strain sensor module by the modification 1 of the 1st Embodiment of this invention. It is a figure which shows typically the plane and the cross section which shows the schematic structure of the strain detection part provided in the strain sensor module by the modification 2 of the 1st Embodiment of this invention. It is a figure which shows typically the plane and the cross section which shows the schematic structure of the strain detection part provided in the strain sensor module by the modification 3 of the 1st Embodiment of this invention. It is a figure which shows typically the plane and the cross section which shows the schematic structure of the strain detection part provided in the strain sensor module by the modification 4 of the 1st Embodiment of this invention. It is a figure which shows typically the plane and the cross section which shows the schematic structure of the strain detection part provided in the strain sensor module by the modification 5 of the 1st Embodiment of this invention. It is a top view of the main part of the output transistor and the writing element provided in the distortion detection part provided in the distortion sensor module by the modification 6 of the 1st Embodiment of this invention. It is a figure which shows typically the plane and the cross section which shows the schematic structure of the strain detection part provided in the strain sensor module by the modification 6 of the 1st Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the distortion detection part provided in the strain sensor module by 2nd Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the strain detection part provided in the strain sensor module by the modification 2 of the 2nd Embodiment of this invention.

[First Embodiment]
The strain sensor module, the offset correction method, and the program according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 35. First, the schematic configuration of the strain sensor module 1 according to the present embodiment will be described with reference to FIGS. 1 to 8. The strain sensor module 1 according to the present embodiment is used by being adhered to and fixed to an object to be measured with, for example, an adhesive.

As shown in FIG. 1, the strain sensor module 1 according to the present embodiment has a strain detection unit 11 that outputs a detection signal according to the amount of strain of a measurement object (not shown), and a detection unit 11 that outputs a detection signal. It is provided with an offset correction unit 12 that corrects the offset of the signal. The offset correction unit 12 has a distortion error detection unit 13 that detects whether or not the strain detection unit 11 normally detects distortion. Further, the distortion sensor module 1 includes a signal amplification unit 14 that amplifies the detection signal output from the distortion detection unit 11, and a signal processing unit 16 that processes the detection signal output from the signal amplification unit 14. Further, the strain sensor module 1 has one of an offset correction operation mode in the offset correction unit 12 and a distortion false detection operation mode by the distortion false detection unit 13 (hereinafter, may be abbreviated as “distortion false detection operation mode”). A mode selection unit 15 for selection is provided.

Although the details will be described later, the mode selection unit 15 is configured to input various signals and voltages (denoted as “IN” in FIG. 1). An offset correction unit 12 is connected to the mode selection unit 15. As a result, various signals output from the mode selection unit 15 can be input to the offset correction unit 12.

The offset correction unit 12 is connected to the distortion detection unit 11 and the signal processing unit 16 in addition to the mode selection unit 15. As a result, a detection signal corresponding to the amount of distortion detected by the distortion detection unit 11 can be input to the offset correction unit 12. The offset correction unit 12 uses the detection signal input from the distortion detection unit 11 to perform an offset correction operation for correcting the offset of the detection signal, and distortion of whether or not the distortion detection unit 11 normally detects the distortion. It is configured to perform false positive actions. The offset correction unit 12 is controlled by a control signal input from the mode selection unit 15 and is configured to execute either an offset correction operation or a distortion error detection operation. The offset correction unit 12 is configured to perform predetermined arithmetic processing (details will be described later) on the detection signal input from the distortion detection unit 11 and output it to the signal processing unit 16.

The signal amplification unit 14 is connected to the distortion detection unit 11 and the signal processing unit 16. As a result, a detection signal corresponding to the amount of distortion detected by the distortion detection unit 11 can be input to the signal amplification unit 14. The signal amplification unit 14 performs predetermined arithmetic processing and amplification processing (details will be described later) on the detection signal input from the distortion detection unit 11, and signals the output signal according to the amount of distortion detected by the distortion detection unit 11. It is configured to be input to the unit 16.

The signal processing unit 16 is configured to convert the analog output signal output from the offset correction unit 12 into a digital output signal OUT1 and output it to the outside. Further, the signal processing unit 16 is configured to convert the analog output signal output from the signal amplification unit 14 into a digital output signal OUT2 and output it to the outside. The output signal OUT1 contains information indicating whether the distortion detected by the distortion detection unit 11 is a normal distortion or an abnormal distortion that is not normal. The output signal OUT2 contains information on the amount of distortion detected by the distortion detection unit 11 (hereinafter, may be referred to as “distortion amount”). Although the details will be described later, the external device connected to the strain sensor module 1 normally detects the strain occurring in the measurement object based on the output signals OUT1 and OUT2 output from the strain sensor module 1. It can be determined whether or not the strain is normally detected due to the secular change occurring in the strain detection unit 11.

Next, a specific configuration of each component provided in the strain sensor module 1 will be described with reference to FIGS. 2 and 3.
As shown in FIG. 2, the power supply voltage VDD, the pulse voltage VPP, the clock signal SCLK, and the data signal DATA are input to the mode selection unit 15 from a predetermined external device. The mode selection unit 15 is configured to operate in synchronization with the clock signal SCLK input from the control unit (not shown) that collectively controls the distortion sensor module. The mode selection unit 15 is configured to generate a comparison signal Sc (details will be described later) used in the offset correction unit 12 using a power supply voltage VDD input from a predetermined external device and output it to the offset correction unit 12. ing. Further, the mode selection unit 15 is configured to output the power supply voltage VDD and the pulse voltage VPP input from a predetermined external device to the distortion detection unit 11. Further, the mode selection unit 15 is configured to input a data signal DATA related to the test mode.

As shown in FIG. 2, the offset correction unit 12 is a current mirror circuit (an example of a current source) that generates a current input to the distortion detection unit 11 when correcting the offset of the detection signal output from the distortion detection unit 11. ) 121. The offset correction unit 12 may have a current source having a configuration other than the current mirror circuit 121 as long as it can generate a direct current. The current mirror circuit 121 is configured to generate a direct current by using a direct current reference current IREF input from the outside. The current mirror circuit 121 has two output terminals connected to the distortion detection unit 11. The current mirror circuit 121 is configured so that a direct current having a predetermined current value generated based on the reference current IREF can be output from each of the two output terminals. Further, the current mirror circuit 121 outputs a direct current from one output terminal and does not output a direct current from the other output terminal, or outputs a direct current from the other output terminal and outputs a direct current from one output terminal. It is configured so that it can not output. Further, the current mirror circuit 121 is configured so that the current value of the direct current output from one output terminal can be changed and the current value of the direct current output from the other output terminal can be changed. There is.

As shown in FIGS. 2 and 3, the offset correction unit 12 has an adder 123 that adds the first detection signal Sd1 and the second detection signal Sd2 output as detection signals from the distortion detection unit 11. The adder 123 is configured to output an addition output signal Sa obtained by adding the first detection signal Sd1 and the second detection signal Sd2.

The offset correction unit 12 is a control signal output from the mode selection unit 15 for either the addition output signal Sa output from the adder 123 or the voltage division signal Sdi obtained by dividing the voltage of the addition output signal Sa. It has a signal selection unit 124 (see FIG. 3) that selects based on Smc. Further, as shown in FIG. 3, the offset correction unit 12 is a differential amplification unit that calculates the difference between the selection output signal Ss output from the signal selection unit 124 and the comparison signal Sc output from the mode selection unit 15. It has 125.

As shown in FIG. 3, the signal selection unit 124 includes a switch 124a and resistance elements R1 and R2. The switch 124a has a two-input, one-output configuration. The resistance element R1 and the resistance element R2 are connected in series between one input terminal of the switch 124a and a reference potential terminal (ground terminal). One terminal of the resistance element R1 is connected to one input terminal of the switch 124a and an output terminal of the adder 123. The other terminals of the resistance element R1 are connected to one terminal of the resistance element R2 and the other input terminal of the switch 124a. The other terminals of the resistance element R2 are connected to the reference potential terminal. The output terminal of the switch 124a is connected to the differential amplification unit 125.

As shown in FIG. 3, the differential amplification unit 125 includes an amplifier 125a and resistance elements R3, R4, R5, and R6. The amplifier 125a is composed of, for example, an operational amplifier. One terminal of the resistance element R3 is connected to a signal output terminal (not shown in FIG. 3) from which the comparison signal Sc of the mode selection unit 15 is output. The other terminals of the resistance element R3 are connected to the non-inverting input terminal (+) of the amplifier 125a and one terminal of the resistance element R5. The other terminals of the resistance element R5 are connected to the reference potential terminal (ground terminal). One terminal of the resistance element R4 is connected to the output terminal of the switch 124a. The other terminals of the resistance element R4 are connected to the inverting input terminal (−) of the amplifier 125a and one terminal of the resistance element R6. The other terminal of the resistance element R6 is connected to the output terminal of the amplifier 125a.

The differential amplification unit 125 subtracts the voltage output from the signal selection unit 124 from the voltage obtained by dividing the voltage of the comparison signal Sc output from the signal output terminal of the mode selection unit 15 by the resistance element R3 and the resistance element R5. The output signal SOUT1 of the voltage is output.

Returning to FIG. 2, the signal amplification unit 14 has a differential amplifier 141 connected to the output terminal of the distortion detection unit 11. The first detection signal output from the distortion detection unit 11 is input to the non-inverting input terminal (not shown) of the differential amplifier 141, and the distortion detection unit is input to the inverting input terminal (not shown) of the differential amplifier 141. The second detection signal output from 11 is input. The differential amplifier 141 is configured to subtract the second detection signal from the first detection signal and output the analog output signal SOUT2 corresponding to the amount of distortion detected by the distortion detection unit 11 to the signal processing unit 16. There is. The strain sensor module 1 uses the output signal SOUT2 calculated and output by the differential amplifier 141 as a signal including information on the amount of strain detected by the strain detection unit 11.

The distortion detection unit 13 includes an adder 123, a signal selection unit 124, and a differential amplification unit 125. That is, the adder 123, the signal selection unit 124, and the differential amplification unit 125 are shared by the distortion error detection unit 13 and the offset correction unit 12. The adder 123, the signal selection unit 124, and the differential amplification unit 125 function as the offset correction unit 12 or are distorted by being controlled by the mode selection unit 15 and switching the switch 124a provided in the signal selection unit 124. It functions as a detection unit 13. The adder 123, the signal selection unit 124, and the differential amplification unit 125 enter an offset correction operation mode for correcting the offset of the detection signal by connecting one input terminal of the switch 124a to the output terminal, and the offset correction unit It functions as a component of twelve. On the other hand, in the adder 123, the signal selection unit 124, and the differential amplification unit 125, whether or not the distortion detection unit 11 normally detects distortion by connecting the other input terminal of the switch 124a to the output terminal. The distortion / error detection operation mode for detecting the above is set and functions as a component of the distortion / error detection unit 13.

As shown in FIG. 2, the signal processing unit 16 has analog-to-digital (AD) converters 161, 162. The input terminal of the AD converter 161 is connected to the output terminal of the offset correction unit 12, that is, the output terminal of the amplifier 125a. As a result, the AD converter 161 can convert the analog output signal SOUT1 output from the amplifier 125a into a digital output signal OUT1 and output it to the outside. The input terminal of the AD converter 162 is connected to the output terminal of the signal amplification unit 14, that is, the output terminal of the differential amplifier 141. As a result, the AD converter 162 can convert the analog output signal SOUT2 output from the differential amplifier 141 into a digital output signal OUT2 and output it to the outside.

Next, a specific configuration of the strain detection unit 11 will be described with reference to FIGS. 4 to 7.
As shown in FIG. 4, the strain detection unit 11 constitutes a Wheatstone bridge circuit and has first to fourth output transistors whose electron mobility changes according to the strain of the object to be measured (an example of four field effect transistors). It has M1r, M2r, M3r, and M4r. The first output transistor M1r and the second output transistor M2r are connected in series between the power supply output terminal from which the power supply voltage VDD is output and the reference potential terminal (ground terminal) serving as the reference potential VSS. The third output transistor M3r and the fourth output transistor M4r are connected in series between the power supply output terminal and the reference potential terminal (ground terminal). The first output transistor M1r and the second output transistor M2r, and the third output transistor M3r and the fourth output transistor M4r are connected in parallel between the power supply output terminal and the reference potential terminal (ground terminal).

The first output transistor M1r corresponds to one of the two field effect transistors arranged on the power supply side. The third output transistor M3r corresponds to the other field effect transistor of the two field effect transistors arranged on the power supply side. The second output transistor M2r corresponds to one of the remaining field effect transistors arranged on the reference potential side. The fourth output transistor M4r corresponds to the other field effect transistor of the residual field effect transistors arranged on the reference potential side.

The first output transistor M1r has a drain D connected to the power supply output terminal and a source S connected to the drain D of the second output transistor M2r. The second output transistor M2r has a source S connected to the reference potential terminal. The third output transistor M3r has a drain D connected to the power output terminal and a source S connected to the drain D of the fourth output transistor M4r. The fourth output transistor M4r has a source S connected to the reference potential terminal. The drain D of the first output transistor M1r and the drain D of the third output transistor M3r are connected. The source S of the second output transistor M2r and the source S of the fourth output transistor M4r are connected.

The first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r each have a floating gate FGr and a control gate CGr (all of which will be described in detail later). The first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r are each composed of a non-volatile storage element. The first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r each have a configuration of a MOS transistor type non-volatile storage element.

Although the details will be described later, the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r control the threshold voltage by adjusting the amount of electric charge accumulated in the floating gate FGr. You can do it. The strain sensor module 1 is output from the distortion detection unit 11 by individually controlling the threshold voltages of the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r. The offset of the detection signal (that is, the first detection signal Sd1 and the second detection signal Sd2) is corrected.

The connection portion to which the source S of the first output transistor M1r and the drain D of the second output transistor M2r are connected becomes an output portion to which the first detection signal Sd1 is output. The connection portions of the first output transistor M1r and the second output transistor M2r are connected to the first output terminal To1. The first output terminal To1 is connected to one input terminal of the adder 123 (see FIGS. 2 and 3) provided in the offset correction unit 12 (see FIG. 2). Therefore, the distortion detection unit 11 inputs the first detection signal Sd1 to one input terminal of the adder 123 via the first output terminal To1.

The connection portion to which the source S of the third output transistor M3r and the drain D of the fourth output transistor M4r are connected becomes an output portion to which the second detection signal Sd2 is output. The connection portions of the third output transistor M3r and the fourth output transistor M4r are connected to the second output terminal To2. The second output terminal To2 is connected to the other input terminal of the adder 123. Therefore, the distortion detection unit 11 inputs the second detection signal Sd2 to the other input terminal of the adder 123 via the second output terminal To2.

Further, the first output terminal To1 is connected to one output terminal of the current mirror circuit 121 (see FIG. 2) provided in the offset correction unit 12. The second output terminal To2 is connected to the other output terminal of the current mirror circuit 121. Although the details will be described later, the strain sensor module 1 uses the direct current generated by the current mirror circuit 121 at the time of offset correction of the detection signal output from the strain detection unit 11 as the first output terminal To1 and the second output terminal To2. Can be entered individually from each of.

As shown in FIG. 4, the strain sensor module 1 is provided in the strain detection unit 11, and is provided with a first charge flow element M1w connected to the first output transistor M1r and a second connected to the second output transistor M2r. It includes a charge flow element M2w, a third charge flow element M3w connected to the third output transistor M3r, and a fourth charge flow element M4w connected to the fourth output transistor M4r. As described above, the charge distribution element is connected to each of the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r in a one-to-one relationship.

The first charge distribution element M1w includes a floating gate FGw connected to the floating gate FGr of the first output transistor M1r, a control gate CGw connected to the control gate CGr of the first output transistor M1r, and a charge capable of distributing electric charges. It has a distribution area 811. The second charge distribution element M2w includes a floating gate FGw connected to the floating gate FGr of the second output transistor M2r, a control gate CGw connected to the control gate CGr of the second output transistor M2r, and an electric charge capable of distributing electric charges. It has a distribution area 811. The third charge distribution element M3w includes a floating gate FGw connected to the floating gate FGr of the third output transistor M3r, a control gate CGw connected to the control gate CGr of the third output transistor M3r, and a charge capable of distributing electric charges. It has a distribution area 811. The fourth charge distribution element M4w includes a floating gate FGw connected to the floating gate FGr of the fourth output transistor M4r, a control gate CGw connected to the control gate CGr of the fourth output transistor M4r, and a charge capable of distributing electric charges. It has a distribution area 811.

The first charge distribution element M1w has an impurity diffusion region IR corresponding to the source S of the first output transistor M1r, but does not have a region corresponding to the drain D of the first output transistor M1r. The second charge distribution element M2w has an impurity diffusion region IR corresponding to the source S of the second output transistor M2r, but does not have a region corresponding to the drain D of the second output transistor M2r. The third charge distribution element M3w has an impurity diffusion region IR corresponding to the source S of the third output transistor M3r, but does not have a region corresponding to the drain D of the third output transistor M3r. The fourth charge distribution element M4w has an impurity diffusion region IR corresponding to the source S of the fourth output transistor M4r, but does not have a region corresponding to the drain D of the fourth output transistor M4r.

The first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w are each composed of a non-volatile storage element. The first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w each have a configuration of a MOS transistor type non-volatile storage element. The first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w are the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output. It is not provided for passing a current like the transistor M4r. The first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w inject charges into the floating gates FGw and FGr via the impurity diffusion region IR, or the floating gate FGw. , Is provided to release an electric charge from FGr.

The first storage element M1 is composed of the first output transistor M1r and the first charge flow element M1w. The second storage element M2 is composed of the second output transistor M2r and the second charge flow element M2w. The third storage element M3 is composed of the third output transistor M3r and the third charge flow element M3w. The fourth storage element M4 is composed of the fourth output transistor M4r and the fourth charge flow element M4w.

As shown in FIG. 4, the strain sensor module 1 includes a switch group 17 connected to the strain detection unit 11. The switch group 17 has a switch SW1, a switch SW3 and a switch SW5 connected to the first charge distribution element M1w, and a switch SW7 connected to the switch SW3. The switch group 17 has a switch SW2, a switch SW4 and a switch SW6 connected to the second charge distribution element M2w, and a switch SW8 connected to the switch SW4. The switch group 17 has a switch SW9, a switch SW11 and a switch SW13 connected to the third charge flow element M3w, and a switch SW15 connected to the switch SW11. The switch group 17 has a switch SW10, a switch SW12, and a switch SW14 connected to the fourth charge flow element M4w, and a switch SW16 connected to the switch SW12.

One terminal of the switch SW1 is connected to the impurity diffusion region IR of the first charge flow element M1w, one of the other terminals of the switch SW1 is connected to the pulse voltage supply terminal from which the pulse voltage VPP is output, and the other terminal of the switch SW1. The other one is connected to a reference potential terminal (ground terminal) that serves as a reference potential VSS. The strain sensor module 1 can apply either the pulse voltage VPP or the reference potential VSS to the impurity diffusion region IR of the first charge flow element M1w by appropriately switching the switch SW1.

One terminal of the switch SW3 is connected to the control gate CGw of the first charge distribution element M1w and one terminal of the switch SW5. The other terminal of the switch SW3 is connected to one terminal of the switch SW7. The other terminals of the switch SW5 are connected to the drain D of the first output transistor M1r. As a result, the strain sensor module 1 can connect the control gate CGw of the first charge flow element M1w and the drain D of the first output transistor M1r to a connected state (short state) or a disconnected state (open state). It has become like. Further, the other terminals of the switch SW5 are also connected to the power supply voltage terminal from which the power supply voltage VDD is output, the other terminals of the switch SW13, and the drain D of the third output transistor M3r.

One of the other terminals of the switch SW7 is connected to the pulse voltage supply terminal to which the pulse voltage VPP is output, and the other one of the other terminals of the switch SW7 is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. ing. The strain sensor module 1 applies either the pulse voltage VPP or the reference potential VSS to the control gate CGw of the first charge flow element M1w by appropriately switching the switch SW7 when the switch SW3 is in the connected state (short state). You can do it.

One terminal of the switch SW2 is connected to the impurity diffusion region IR of the second charge flow element M2w, one of the other terminals of the switch SW2 is connected to the pulse voltage supply terminal from which the pulse voltage VPP is output, and the other terminal of the switch SW2. The other one is connected to a reference potential terminal (ground terminal) that serves as a reference potential VSS. The strain sensor module 1 can apply either one of the pulse voltage VPP and the reference potential VSS to the impurity diffusion region IR of the second charge flow element M2w by appropriately switching the switch SW2.

One terminal of the switch SW4 is connected to the control gate CGw of the second charge distribution element M2w and one terminal of the switch SW6. The other terminal of the switch SW4 is connected to one terminal of the switch SW8. The other terminals of the switch SW6 are connected to the drain D of the second output transistor M2r. As a result, the strain sensor module 1 can connect the control gate CGw of the second charge flow element M2w and the drain D of the second output transistor M2r to a connected state (short state) or a disconnected state (open state). It has become like. The other terminals of the switch SW6 are also connected to the first output terminal To1 and the source S of the first output transistor M1r.

One of the other terminals of the switch SW8 is connected to the pulse voltage supply terminal from which the pulse voltage VPP is output, and the other terminal of the switch SW8 is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. ing. The strain sensor module 1 applies either the pulse voltage VPP or the reference potential VSS to the control gate CGw of the second charge flow element M2w by appropriately switching the switch SW8 when the switch SW4 is in the connected state (short state). You can do it.

One terminal of the switch SW9 is connected to the impurity diffusion region IR of the third charge flow element M3w, one of the other terminals of the switch SW9 is connected to the pulse voltage supply terminal from which the pulse voltage VPP is output, and the other terminal of the switch SW9. The other one is connected to a reference potential terminal (ground terminal) that serves as a reference potential VSS. The strain sensor module 1 can apply either one of the pulse voltage VPP and the reference potential VSS to the impurity diffusion region IR of the third charge flow element M3w by appropriately switching the switch SW9.

One terminal of the switch SW11 is connected to the control gate CGw of the third charge distribution element M3w and one terminal of the switch SW13. The other terminal of the switch SW11 is connected to one terminal of the switch SW15. The other terminals of the switch SW13 are connected to the drain D of the third output transistor M3r. As a result, the strain sensor module 1 can connect the control gate CGw of the third charge flow element M3w and the drain D of the third output transistor M3r to a connected state (short state) or a disconnected state (open state). It has become like. Further, the other terminals of the switch SW13 are also connected to the power supply voltage end from which the power supply voltage VDD is output and the drain D of the first output transistor M1r.

One of the other terminals of the switch SW15 is connected to the pulse voltage supply terminal to which the pulse voltage VPP is output, and the other one of the other terminals of the switch SW15 is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. ing. The strain sensor module 1 applies either the pulse voltage VPP or the reference potential VSS to the control gate CGw of the third charge flow element M3w by appropriately switching the switch SW15 when the switch SW11 is in the connected state (short state). You can do it.

One terminal of the switch SW10 is connected to the impurity diffusion region IR of the fourth charge flow element M4w, one of the other terminals of the switch SW10 is connected to the pulse voltage supply terminal from which the pulse voltage VPP is output, and the other terminal of the switch SW10. The other one is connected to a reference potential terminal (ground terminal) that serves as a reference potential VSS. The strain sensor module 1 can apply either one of the pulse voltage VPP and the reference potential VSS to the impurity diffusion region IR of the fourth charge flow element M4w by appropriately switching the switch SW10.

One terminal of the switch SW12 is connected to the control gate CGw of the fourth charge distribution element M4w and one terminal of the switch SW14. The other terminal of the switch SW12 is connected to one terminal of the switch SW16. The other terminals of the switch SW14 are connected to the drain D of the fourth output transistor M4r. As a result, the strain sensor module 1 can connect the control gate CGw of the fourth charge flow element M4w and the drain D of the fourth output transistor M4r to a connected state (short state) or a disconnected state (open state). It has become like. Further, the other terminals of the switch SW14 are also connected to the source S of the second output terminal To2 and the third output transistor M3r.

One of the other terminals of the switch SW16 is connected to the pulse voltage supply terminal to which the pulse voltage VPP is output, and the other one of the other terminals of the switch SW16 is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. ing. The strain sensor module 1 applies either the pulse voltage VPP or the reference potential VSS to the control gate CGw of the fourth charge flow element M4w by appropriately switching the switch SW16 when the switch SW12 is in the connected state (short state). You can do it.

When the strain sensor module 1 uses the strain detection unit 11 to detect the strain of the object to be measured, the switches SW1 to SW16 are switched to the following states.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Open state (open state)
Switch SW5: Connection state (short state)
Switch SW6: Connection state (short state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 4)
Switch SW8: Arbitrary (reference potential VSS side in FIG. 4)
Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Open state (open state)
Switch SW13: Connection state (short state)
Switch SW14: Connection state (short state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 4)
Switch SW16: Arbitrary (reference potential VSS side in FIG. 4)

Next, the structures of the first storage element M1, the second storage element M2, the third storage element M3, and the fourth storage element M4 will be described with reference to FIGS. 5 to 8. FIG. 5A is a diagram schematically showing a plane of a first example of a main part of the first storage element M1, the second storage element M2, the third storage element M3, and the fourth storage element M4. FIG. 5B is a diagram schematically showing a plane of a second example of a main part of the first storage element M1, the second storage element M2, the third storage element M3, and the fourth storage element M4.

As shown in FIGS. 5 (a) and 5 (b), the first example of the main part of the first storage element M1 to the fourth storage element M4 and the main part of the first storage element M1 to the fourth storage element M4. It has a different planar shape from the second example of the part. Here, the planar shapes of the first storage element M1 to the fourth storage element M4 will be described by taking the first storage element M1 as an example.

As shown in FIG. 5A, in the first storage element M1 of the first example, the first output transistor M1r and the first charge flow element M1w are arranged so as to be offset from each other. The end of the first output transistor M1r on the source S side and the end of the first charge flow element M1w on the side where the impurity diffusion region IR is not provided are arranged adjacent to each other. The control gate CGr provided on the first output transistor M1r and the control gate CGw provided on the first charge flow element M1w are connected by a connection gate NGc. The connection gate NGc is the end of the control gate CGr arranged on the source side of the first output transistor M1r and the end of the control gate CGw arranged on the side of the first charge flow element M1w where the impurity diffusion region IR is not provided. It is formed by stretching the parts. The control gate CGr, the connection gate NGc, and the control gate CGw are integrally formed, for example, in succession.

The floating gate FGr provided in the first output transistor M1r is arranged below the control gate CGr along the control gate CGr. The floating gate FGw provided in the first charge distribution element M1w is arranged below the control gate CGw along the control gate CGw. The floating gate FGr and the floating gate FGw are connected by a connecting gate NGf formed along the connecting gate NGc below the connecting gate NGc. In the first storage element M1, the floating gate FGr, the connecting gate NGf, and the floating gate FGw are integrally formed, for example, in succession.

The charge distribution region 811 provided in the first charge distribution element M1w is unevenly arranged on the end side where the impurity diffusion region IR is arranged at both ends of the first charge distribution element M1w.

As shown in FIG. 5B, in the first storage element M1 of the second example, the first output transistor M1r and the first charge flow element M1w are arranged substantially in parallel without shifting in one direction. .. The control gate CGr provided on the first output transistor M1r and the control gate CGw provided on the first charge flow element M1w are connected by a connection gate NGc. The connection gate NGc is formed by extending the control gate CGr and the control gate CGw substantially at the center. The control gate CGr, the connection gate NGc, and the control gate CGw are integrally formed, for example, in succession.

The floating gate FGr provided in the first output transistor M1r is arranged below the control gate CGr along the control gate CGr. The floating gate FGw provided in the first charge distribution element M1w is arranged below the control gate CGw along the control gate CGw. The floating gate FGr and the floating gate FGw are connected by a connection gate NGf formed along the connection gate NGc below the connection gate NGc. In the second storage element M2, the floating gate FGr, the connecting gate NGf, and the floating gate FGw are integrally formed, for example, in succession.

The charge distribution region 811 provided in the first charge distribution element M1w is unevenly arranged on the end side where the impurity diffusion region IR is arranged at both ends of the first charge distribution element M1w.

Next, the cross-sectional configurations of the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w will be described with reference to FIG. Since the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w have the same cross-sectional structure, the first charge flow element has the same cross-sectional structure. M1w will be described as an example.

As shown in FIG. 6, the first charge distribution element M1w is formed on, for example, a P-type semiconductor substrate (an example of a substrate) 9. The first charge flow element M1w includes a first output transistor M1r, a second storage element M2, a third storage element M3, and a fourth storage element M1r formed on the same semiconductor substrate 9 by an element separation region 97 formed on the semiconductor substrate 9. The element is separated from the storage element M4 (not shown in FIG. 6). The first charge distribution element M1w has at least a part of a charge distribution region 811 formed to a thickness that allows charges to flow when a predetermined voltage is applied, and is a gate insulating film arranged in contact with the semiconductor substrate 9. It has 82 (an example of a second insulating film). The gate insulating film 82 is formed of, for example, silicon dioxide (SiO ₂ ) and is arranged on the semiconductor substrate 9. The gate insulating film 82 is arranged on a predetermined region of the semiconductor substrate 9 in which a well region or the like is not formed. The gate insulating film 82 is not limited to silicon dioxide, and may be formed of silicon nitride (SiN).

A tunnel insulating film 821 is formed in, for example, a part of the gate insulating film 82. The tunnel insulating film 821 is a portion of the gate insulating film 82 formed to have a relatively thin film thickness. The tunnel insulating film 821 is formed to have a film thickness of, for example, 6 nm or more and less than 15 nm. Further, the portion of the gate insulating film 82 excluding the tunnel insulating film 821 is formed to have a film thickness of 15 nm or more.

In the present embodiment, the gate insulating film 82 has a tunnel insulating film 821 having a relatively thin film thickness in a part thereof, but the entire region is formed to have a film thickness of 6 nm or more and less than 15 nm. May be good. Further, the gate insulating film 82 may have a film thickness in the range of 6 nm or more and less than 15 nm as a whole, and may have an uneven shape on the surface. Further, the gate insulating film 82 may have a constant film thickness (for example, a constant film thickness at 6 nm) within a range of 6 nm or more and less than 15 nm, and may have a flat shape on the surface. In these cases, of the entire region of the gate insulating film 82, a region having a film thickness of 6 nm or more and less than 15 nm exhibits a function as a tunnel insulating film.

When the tunnel insulating film 821 has a film thickness thinner than 6 nm, direct tunneling is likely to occur in the tunnel insulating film 821, and the charge retention characteristic (retention characteristic) of the floating gate FGw deteriorates. On the other hand, when the tunnel insulating film 821 has a film thickness thicker than 15 nm, the injection of electric charge into the floating gate FGw and the discharge of electric charge from the floating gate FGw become slow. Therefore, since the first charge flow element M1w has a tunnel insulating film 821 formed with a film thickness of 6 nm or more and less than 15 nm, it is possible to suppress aging by improving the charge retention characteristics of the first storage element M1. , The offset correction can be shortened by improving the charge injection speed and the charge discharge speed between the floating gate FGw and the N-type region 91 (details will be described later).

As shown in FIG. 6, the first charge flow element M1w is arranged in contact with the gate insulating film 82 in an electrically floating state to form a floating gate FGr (an example of the first floating gate, not shown in FIG. 6). It has a connected floating gate FGw (an example of a second floating gate). The first charge distribution element M1w is insulated from the floating gate FGw, arranged above the floating gate FGw, connected to the control gate CGr (an example of the first control gate, not shown in FIG. 6), and above the floating gate FGw. It has an arranged control gate CGw (an example of a second control gate). The first charge flow element M1w has an impurity diffusion region IR formed on one of both sides below the floating gate FGw. The impurity diffusion region IR is formed on the semiconductor substrate 9. The impurity diffusion region IR is not formed in the well region formed in the semiconductor substrate 9, but is directly formed in the semiconductor substrate 9.

The floating gate FGw is composed of a charge holding region 81 and an insulator 80. That is, the insulator 80 is formed so as to surround the entire surface of the charge holding region 81. The insulator 80 is composed of, for example, a combination of a silicon oxide film and a silicon nitride film, and has an oxide / nitride / oxide (ONO) structure. The insulator 80 may have a halogen (for example, fluorine) distributed in at least a part of the region surrounding the entire surface of the charge holding region 81. In the present embodiment, for example, the insulator 80 is arranged so as to surround the charge holding region 81 so that the halogen element is distributed in all directions surrounding the charge holding region 81, and has halogen distributed in the entire region. .. The insulator 80 was formed above the charge holding region 81, the gate insulating film 82 formed below the charge holding region 81, the side wall oxide film 83 formed by oxidizing the side wall of the charge holding region 81, and the side wall oxide film 83 formed by oxidizing the side wall of the charge holding region 81. It is composed of an upper insulating film 84. Each region of the insulator 80 surrounding the charge holding region 81 does not have to be the same material, nor does it need to be an insulator formed at the same time. A sidewall 85 is formed around the gate insulating film 82 and the side wall oxide film 83.

The charge holding region 81 is formed of polysilicon. The portion of the charge holding region 81 on which the tunnel insulating film 821 is formed becomes the charge flow region 811 for injecting charge into the charge holding region 81 and discharging the charge from the charge holding region 81. That is, the gate insulating film 82 has a charge flow region 811 for injecting and discharging charges. The floating gate FGw is configured to hold the charge injected from the impurity diffusion region IR through the charge flow region 811 in the charge holding region 81.

The control gate CGw has a polysilicon film 86 formed on the upper insulating film 84. A sidewall 87 formed on the upper insulating film 84 is formed around the polysilicon film 86.

The impurity diffusion region IR has an N-type region 91 and an N-type N + region 92 having a higher concentration of impurities than the N-type region 91. The N + region 92 is formed in the N-type region 91. The N + region 92 is provided to make ohmic contact between the impurity diffusion region IR and the plug 63 described later. The impurity diffusion region IR is provided below and laterally of the floating gate FGw in a plan view of the first charge flow element M1w. The N-type region 91 is provided below and laterally of the floating gate FGw, and the N + region 92 is provided on the side of the floating gate FGw. The N-shaped region 91 is also arranged below the tunnel insulating film 821.

An interlayer insulating film 61 is formed on the control gate CGw, the floating gate FGw, the sidewalls 85, 87, and the impurity diffusion region IR of the first charge flow element M1w. The interlayer insulating film 61 functions as a protective film that protects the control gate CGw, the floating gate FGw, and the like.

The first charge flow element M1w has a plug 63 having a part of the N + region 92 exposed on the bottom surface and embedded in an opening formed in the interlayer insulating film 61, and a plug 63 electrically connected to the plug 63 on the interlayer insulating film 61. It has a metal wiring (not shown) formed in. The metal wiring and the impurity diffusion region IR are electrically connected via the plug 63. The metal wiring is connected to one terminal of switch SW1 (see FIG. 4). As a result, either low voltage Vss or pulse voltage VPP can be applied from the switch SW1 to the impurity diffusion region IR via the metal wiring and the plug 63.

The first charge flow element M1w has a plug 62 in which a part of the polysilicon film 86 is exposed on the bottom surface and embedded in an opening formed in the interlayer insulating film 61, and an interlayer insulating film 61 that is electrically connected to the plug 62. It has a metal wiring (not shown) formed on the top. The metal wiring and the polysilicon film 86 are electrically connected via the plug 62. The metal wiring is connected to one terminal of the switch SW3 (see FIG. 4). As a result, either low voltage Vss or pulse voltage VPP can be applied to the polysilicon film 86 from the switch SW3 via the metal wiring and the plug 62.

Next, the cross-sectional configurations of the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r will be described with reference to FIG. Since the first output transistor M1r, the second output transistor M2r, the third output transistor M3r and the fourth output transistor M4r have the same electrical surface configuration, the first output transistor M1r is taken as an example for these cross-sectional configurations. explain.

As shown in FIG. 7, the first output transistor M1r is formed on, for example, the same semiconductor substrate 9 as the first charge distribution element M1w. The first output transistor M1r is a second storage element M2, a third storage element M3, and a fourth storage element M4 (in FIG. 7) formed on the same semiconductor substrate 9 by the element separation region 97 formed on the semiconductor substrate 9. The element is separated from (not shown). The first output transistor M1r has a gate insulating film 72 (an example of the first insulating film) arranged in contact with the semiconductor substrate 9. The first output transistor M1r has a floating gate FGr (an example of the first floating gate) arranged in contact with the gate insulating film 72 in an electrically floating state. The first output transistor M1r has a control gate CGr (an example of the first control gate) arranged above the floating gate FGr so as to be insulated from the floating gate FGr.

The gate insulating film 72 is formed in the same manufacturing process as, for example, the gate insulating film 82 (see FIG. 6). The gate insulating film 72 is formed on, for example, silicon dioxide (SiO ₂ ) and is arranged on a predetermined region of the semiconductor substrate 9 in which a well region or the like is not formed. The gate insulating film 72 is not limited to silicon dioxide, and may be formed of silicon nitride (SiN). The entire region of the gate insulating film 72 is formed to have substantially the same film thickness. The gate insulating film 72 is formed to have a film thickness of, for example, 15 nm or more. The gate insulating film 72 may have an uneven shape or an uneven shape on the surface. However, the gate insulating film 72 is formed so as to have a film thickness of, for example, 15 nm or more even at the thinnest portion. As a result, the gate insulating film 72 can prevent electric charges from flowing.

As shown in FIG. 7, the floating gate FGr is composed of a charge holding region 71 and an insulator 70. The charge holding region 71 is formed of polysilicon. The floating gate FGr is configured to hold the charge injected from the floating gate FGw in the charge holding region 71.

The insulator 70 is formed so as to surround the entire surface of the charge holding region 71. The insulator 70 is composed of, for example, a combination of a silicon oxide film and a silicon nitride film, and has an oxide / nitride / oxide (ONO) structure. The insulator 70 may have a halogen (for example, fluorine) distributed in at least a part of the region surrounding the entire surface of the charge holding region 71. In the present embodiment, for example, the insulator 70 is arranged so as to surround the charge holding region 71 so that the halogen element is distributed in all directions surrounding the charge holding region 71, and has halogen distributed in the entire region. .. The insulator 70 was formed above the charge holding region 71, the gate insulating film 72 formed below the charge holding region 71, the side wall oxide film 73 formed by oxidizing the side wall of the charge holding region 71, and the charge holding region 71. It is composed of an upper insulating film 74. Each region of the insulator 70 surrounding the charge holding region 71 does not have to be the same material, nor does it need to be an insulator formed at the same time. A sidewall 75 is formed around the gate insulating film 72 and the side wall oxide film 73.

The control gate CGr has a polysilicon film 66 formed on the upper insulating film 74. A sidewall 67 formed on the upper insulating film 74 is formed around the polysilicon film 66.

The first output transistor M1r has a drain D formed on both sides below the floating gate FGr and a source S formed on both sides below the floating gate FGr. The drain D and the source S are formed on the semiconductor substrate 9. That is, the drain D and the source S are formed in a predetermined region of the semiconductor substrate 9 in which a well region or the like is not formed. As a result, the region directly below the gate insulating film 72 and sandwiched between the drain D and the source S (that is, the channel region of the first output transistor M1r) is compared with the case where the drain D and the source S are formed in the well region. The impurity concentration becomes low. When strain is generated in the strain detection unit 11 and stress is applied to the first output transistor M1r, the change in electron mobility becomes larger as the impurity concentration in the channel region becomes lower. As a result, the detection sensitivity of the strain detection unit 11 is improved.

The drain D has an N-type region 93 and an N-type N + region 94 having a higher concentration of impurities than the N-type region 93. The N + region 94 is formed in the N-type region 93. The N + region 94 is provided to make ohmic contact between the drain D and the plug 65 described later. The drain D is provided so as to extend below and to the side of the floating gate FGr in a plan view of the first output transistor M1r. The N-type region 93 is provided below and laterally of the floating gate FGr, and the N + region 94 is provided on the side of the floating gate FGr.

The source S has an N-type region 95 and an N-type N + region 96 having a higher concentration of impurities than the N-type region 95. The N + region 96 is formed in the N-type region 95. The N + region 96 is provided to make ohmic contact between the source S and the plug 64 described later. The source S is provided so as to straddle the lower side and the side of the floating gate FGr in a plan view of the first output transistor M1r. The N-type region 95 is provided below and laterally of the floating gate FGr, and the N + region 96 is provided on the side of the floating gate FGr.

An interlayer insulating film 61 is formed on the control gate CGr, the floating gate FGr, the sidewalls 75, 77, the drain D, and the source S of the first output transistor M1r. The interlayer insulating film 61 functions as a protective film that protects the control gate CGr, the floating gate FGr, and the like.

The first output transistor M1r has a plug 64 embedded in an opening formed in the interlayer insulating film 61 with a part of the N + region 94 exposed on the bottom surface, and a plug 64 electrically connected to the plug 64 on the interlayer insulating film 61. It has a formed metal wiring (not shown). The metal wiring and the drain D are electrically connected via the plug 64. The metal wiring is connected to another terminal (see FIG. 4) of the switch SW5. One terminal of the switch SW5 is connected to the polysilicon film 86 of the control gate CGw of the first charge distribution element M1w. This makes it possible to connect the drain D and the polysilicon film 86 via the switch SW5, the metal wiring, and the plug 64.

The first output transistor M1r has a plug 65 having a part of the N + region 96 exposed on the bottom surface and embedded in an opening formed in the interlayer insulating film 61, and a plug 65 electrically connected to the plug 65 on the interlayer insulating film 61. It has a formed metal wiring (not shown). The metal wiring and the source S are electrically connected via the plug 65. The metal wiring is connected to the first output terminal To1 (see FIG. 4). As a result, the distortion detection unit 11 can output the voltage of the source S of the first output transistor M1r as the first detection signal Sd1 from the first output terminal To1.

Although not shown, the connecting gate NGf (see FIG. 5A) connecting the floating gate FGw and the floating gate FGr (see FIG. 6) is formed in the interlayer insulating film 61. Like the floating gate FGw and the floating gate FGr, the connecting gate NGf has a charge holding region formed of polysilicon and an insulator formed surrounding the charge holding region. The charge holding region of the connection gate NGf is formed integrally with, for example, the charge holding region 71 and the charge holding region 81 (see FIG. 6). The charge holding region of the connection gate NGf is formed, for example, in the same layer as the charge holding region 71 and the charge holding region 81. The insulator of the connection gate NGf has, for example, the same configuration as the insulator 70 and the insulator 80 (see FIG. 6), and is integrally formed. The insulator of the connection gate NGf is formed, for example, in the same layer as the insulator 70 and the insulator 80. As a result, the charge injected from the floating gate FGw reaches the charge holding region 81, the charge holding region of the connection gate NGf, and the charge holding region 71, and is held in each charge holding region.

Although not shown, the connection gate NGc (see FIG. 5A) connecting the control gate CGw and the control gate CGr (see FIG. 6) is formed in the interlayer insulating film 61. The connection gate NGc has a polysilicon film like the control gate CGw and the control gate CGr. A sidewall formed on the insulating film integrally formed with the upper insulating film 74 and the upper insulating film 84 (see FIG. 6) is formed around the polysilicon film. The sidewall is integrally formed with, for example, a sidewall 67 and a sidewall 87 (see FIG. 6). The polysilicon film of the connection gate NGc is formed integrally with, for example, the polysilicon film 66 and the polysilicon film 86 (see FIG. 6). The polysilicon film of the connection gate NGc is formed in the same layer as the polysilicon film 66 and the polysilicon film 86, for example. As a result, the voltage applied to the polysilicon film 86 of the floating gate FGw is also applied to the polysilicon film and the polysilicon film 66 of the connection gate NGc.

Next, the structure of the strain detection unit 11 will be described with reference to FIGS. 8 and 9. FIG. 8 is a diagram schematically showing a main part of a strain detecting unit 11 having the first storage element M1 to the fourth storage element M4 of the first example shown in FIG. 5A. FIG. 9 is a diagram schematically showing a main part of a strain detecting unit 11 having the first storage element M1 to the fourth storage element M4 of the second example shown in FIG. 5 (b). The plane of the strain detection unit 11 is schematically shown in the upper part of FIGS. 8 and 9, and the lower part of FIGS. 8 and 9 shows the strain cut along the line AA shown in the upper part of FIG. The cross section of the detection unit 11 is schematically shown.

As shown in FIGS. 8 and 9, the semiconductor substrate 9 provided in the strain detection unit 11 is arranged next to the thin portion 911 formed to a predetermined thickness and the thin portion 911, and is more than the thin portion 911. It has a thickly formed thick portion 912. The semiconductor substrate 9 has a square shape when the surface on which the interlayer insulating film 61 is formed (element forming surface) is viewed in an orthogonal direction. When the element forming surface of the semiconductor substrate 9 is viewed in a direction orthogonal to each other, a circular thin portion 911 is arranged in a predetermined region in the center, and a square thick portion 912 is arranged so as to surround the entire circumference of the thin portion 911. There is. The semiconductor substrate 9 when the first storage elements M1 to the fourth storage elements M4 of the first example are used, and the semiconductor substrate 9 when the first storage elements M1 to the fourth storage elements M4 of the second example are used. Have the same shape as.

As shown in FIG. 8, when the first storage element M1 to the fourth storage element M4 of the first example are used, the first storage element M1 and the fourth storage element M4 are, for example, the crystal axis <010 of the semiconductor substrate 9. They are arranged so as to face each other in the direction of>. Further, in this case, the second storage element M2 and the third storage element M3 are arranged so as to face each other in the direction of the crystal axis <100> of the semiconductor substrate 9, for example. As shown in FIG. 9, when the first storage element M1 to the fourth storage element M4 of the first example are used, the first storage element M1 and the fourth storage element M4 are, for example, the crystal axis <100 of the semiconductor substrate 9. They are arranged so as to face each other in the direction of>. Further, in this case, the second storage element M2 and the third storage element M3 are arranged so as to face each other in the direction of the crystal axis <010> of the semiconductor substrate 9, for example.

In both the case where the first memory element M1 to the fourth memory element M4 of the first example are used and the case where the first memory element M1 to the fourth memory element M4 of the second example are used, the first memory element M1 , The second storage element M2, the third storage element M3, and the fourth storage element M4 are arranged at equal intervals with, for example, storage elements adjacent to each other. Specifically, the second storage element M2 is arranged at a location rotated clockwise by about 90 ° with respect to the location where the first storage element M1 is arranged about the center of the thin portion 911 as an axis. The fourth storage element M4 is arranged at a location rotated clockwise by about 90 ° with respect to the location where the second storage element M2 is arranged about the center of the thin portion 911 as an axis. The third storage element M3 is arranged at a location rotated clockwise by about 90 ° with respect to the location where the fourth storage element M4 is arranged about the center of the thin portion 911 as an axis. The first storage element M1 is arranged at a position rotated clockwise by about 90 ° with respect to the place where the third storage element M3 is arranged about the center of the thin portion 911 as an axis.

The first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r are formed in the thin portion 911. The charge distribution regions 811 provided in each of the first charge distribution element M1w, the second charge distribution element M2w, the third charge distribution element M3w, and the fourth charge distribution element M4w are formed above the wall thickness portion 912. .. At least a part of the first charge flow element M1w, at least a part of the second charge flow element M2w, at least a part of the third charge flow element M3w, and at least a part of the fourth charge flow element M4w are formed in the thick portion 912. It is formed. In the example shown in FIG. 8, a part of the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w is formed in the thin portion 911, and the other part. Is formed in the thick portion 912. A charge flow region 811 is included in each part of the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w formed in the thick portion 912. ing. In the example shown in FIG. 9, all of the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w are formed in the thick portion 912.

In this way, in the strain detection unit 11, the charge flow region 811 in which the tunnel insulating film 821 in which the charge accumulated in the floating gate FGw is most easily released is formed is arranged away from the thin portion 911 to which the strain is applied. As a result, the strain sensor module 1 prevents data garbled of the first storage element M1, the second storage element M2, the third storage element M3, and the fourth storage element M4, which are caused by the discharge of charge from the floating gate FGw. False detection of distortion can be suppressed.

Next, the principle of detecting the strain of the object to be measured in the strain sensor module 1 will be described with reference to FIGS. 10 and 11. 10 (a) and 11 (a) are diagrams schematically showing the characteristics of the drain-source current Ids with respect to the gate-source voltage Vgs of the first output transistor M1r and the second output transistor M2r. Hereinafter, the characteristic of the drain-source current Ids with respect to the gate-source voltage Vgs may be abbreviated as “IV characteristic”. The characteristic IV1 shown in FIGS. 10A and 11A shows an example of the IV characteristic of the first output transistor M1r in a state where the semiconductor substrate 9 is not distorted. The characteristic IV11 shown in FIG. 10A is the IV characteristic of the first output transistor M1r in a state where tensile strain in the crystal axis <100> direction or compression strain in the crystal axis <010> direction is generated in the semiconductor substrate 9. An example is shown. The characteristic IV12 shown in FIG. 11A is the IV characteristic of the first output transistor M1r in a state where tensile strain in the crystal axis <010> direction or compression strain in the crystal axis <100> direction is generated in the semiconductor substrate 9. An example is shown.

The characteristic IV2 shown in FIGS. 10A and 11A shows an example of the IV characteristic of the second output transistor M2r in a state where the semiconductor substrate 9 is not distorted. The characteristic IV21 shown in FIG. 10A is the IV characteristic of the second output transistor M2r in a state where tensile strain in the crystal axis <100> direction or compression strain in the crystal axis <010> direction is generated in the semiconductor substrate 9. An example is shown. The characteristic IV22 shown in FIG. 11A is the IV characteristic of the second output transistor M2r in a state where tensile strain in the crystal axis <010> direction or compression strain in the crystal axis <100> direction is generated in the semiconductor substrate 9. An example is shown.

10 (b) and 11 (b) are diagrams showing the characteristics of the drain-source current Ids with respect to the gate-source voltage Vgs of the third output transistor M3r and the fourth output transistor M4r. The characteristic IV3 shown in FIGS. 10B and 11B shows an example of the IV characteristic of the third output transistor M3r in a state where the semiconductor substrate 9 is not distorted. The characteristic IV31 shown in FIG. 10B is the IV characteristic of the third output transistor M3r in a state where tensile strain in the crystal axis <100> direction or compression strain in the crystal axis <010> direction is generated in the semiconductor substrate 9. An example is shown. The characteristic IV32 shown in FIG. 11B is the IV characteristic of the third output transistor M3r in a state where tensile strain in the crystal axis <010> direction or compression strain in the crystal axis <100> direction is generated in the semiconductor substrate 9. An example is shown.

The characteristic IV4 shown in FIGS. 10B and 11B shows an example of the IV characteristic of the fourth output transistor M4r in a state where the semiconductor substrate 9 is not distorted. The characteristic IV41 shown in FIG. 10B is the IV characteristic of the fourth output transistor M4r in a state where tensile strain in the crystal axis <100> direction or compression strain in the crystal axis <010> direction is generated in the semiconductor substrate 9. An example is shown. The characteristic IV42 shown in FIG. 11B is the IV characteristic of the fourth output transistor M4r in a state where tensile strain in the crystal axis <010> direction or compression strain in the crystal axis <100> direction is generated in the semiconductor substrate 9. An example is shown.

Although details will be described later, in the strain sensor module 1 according to the present embodiment, the gate-source voltage Vds of the second output transistor M2r may be the voltage of the first detection signal Sd1 (hereinafter, referred to as “first detection signal voltage Vs1”). The voltage Vds between the gates and sources of the fourth output transistor M4r becomes the voltage of the second detection signal Sd2 (hereinafter, may be referred to as “second detection signal voltage Vs2”). Further, in the distortion sensor module 1, the offsets of the first detection signal Sd1 and the second detection signal Sd2 are corrected so that the voltage value of the first detection signal voltage Vs1 and the voltage value of the second detection signal voltage Vs2 are the same. Will be done. Hereinafter, the reference code “Vs1” of the first detection signal voltage Vs1 is also used as the code of the voltage value of the first detection signal voltage Vs1, and the reference code “Vs2” of the second detection signal voltage Vs2 is the second detection signal voltage. It is also used as a code for the voltage value of Vs2.

As shown in FIGS. 10A and 11A, by adjusting the drain-source current Ids of the first output transistor M1r to, for example, the current value Ip1, the gate-source voltage Vds of the second output transistor M2r can be adjusted. The offset of the first detection signal Sd1 is corrected so that the voltage value becomes the voltage value Vs1. Similarly, as shown in FIGS. 10 (b) and 11 (b), by adjusting the drain-source current Ids of the third output transistor M3r to, for example, the current value Ip3, between the gate and source of the fourth output transistor M4r. The offset of the second detection signal Sd2 is corrected so that the voltage value of the voltage Vds becomes the same voltage value Vs2 as the voltage value Vs1.

The strain sensor module 1 obtains the difference between the first detection signal voltage Vs1 and the second detection signal voltage Vs2 by the signal amplification unit 14, so that the voltage corresponding to the amount of distortion generated in the measurement object (hereinafter, “distortion voltage”). It is designed to detect Vdt. The distortion voltage Vdt can be calculated by the following equation (1).
Vdt = Vs1-Vs2 ... (1)

The distorted voltage Vdt corresponds to the voltage of the output signal SOUT2 output by the differential amplifier 141 provided in the signal amplification unit 14. The voltage value of the first detection signal voltage Vs1 and the voltage value of the second detection signal voltage Vs2 are set to be the same by offset correction of the first detection signal Sd1 and the second detection signal Sd2. Therefore, the distortion voltage Vdt of the first detection signal Sd1 and the second detection signal Sd2 after offset correction is 0V according to the equation (1).

For example, stress in the direction in which the first memory element M1 and the fourth memory element M4 are lined up due to strain in the object to be measured (for example, stress or crystal axis that causes tensile strain in the crystal axis <100> direction of the semiconductor substrate 9). It is assumed that a stress that causes compressive strain in the <010> direction) is applied. As a result, the electron mobilities of the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r change, so that the IV characteristics of each change. As shown in FIG. 10A, the first output transistor M1r has a high electron mobility. Therefore, the IV characteristic of the first output transistor M1r becomes the characteristic IV11 in which a current easily flows as compared with the characteristic IV1 in a state in which no distortion is generated (stress is not applied). As a result, the current value of the drain-source current Ids flowing through the first output transistor M1r rises to the current value Ia1.

On the other hand, the second output transistor M2r has lower electron mobility. Therefore, the IV characteristic of the second output transistor M2r is the characteristic IV21 in which current is less likely to flow as compared with the characteristic IV2 in the state where no distortion is generated (stress is not applied). Similarly, the current value of the drain-source current Ids of the second output transistor M2r also becomes the current value Ia1, so that the voltage value of the gate-source voltage Vgs of the second output transistor M2r increases by ΔV1 to become the voltage value Vs1 + ΔV1. .. Therefore, the voltage value of the first detection signal Sd1 increases by ΔV1.

As shown in FIG. 10B, the third output transistor M3r has lower electron mobility. Therefore, the IV characteristic of the third output transistor M3r is the characteristic IV31 in which current is less likely to flow as compared with the characteristic IV3 in the state where no distortion is generated (stress is not applied). As a result, the current value of the drain-source current Ids flowing through the third output transistor M3r is reduced to the current value Ia3. On the other hand, the fourth output transistor M4r has a high electron mobility. Therefore, the IV characteristic of the fourth output transistor M4r becomes the characteristic IV41 in which a current easily flows as compared with the characteristic IV4 in a state in which distortion is not generated (stress is not applied). Since the current value of the drain-source current Ids of the fourth output transistor M4r is also the current value Ia3, the voltage value of the gate-source voltage Vgs of the fourth output transistor M4r is reduced by ΔV2 to the voltage value Vs2-ΔV2. It becomes. Therefore, the voltage value of the second detection signal Sd2 is reduced by ΔV2.

Stress in the direction in which the first storage element M1 and the fourth storage element M4 are lined up due to strain in the object to be measured (for example, stress that causes tensile strain in the crystal axis <100> direction of the semiconductor substrate 9 or crystal axis <010 > When a stress that causes compression strain in the direction is applied, assuming that the values of the first detection signal voltage Vs1 and the second detection signal voltage Vs2 are the same, the distortion voltage Vdt is "ΔV1 + ΔV2" from the equation (1). It becomes.

Further, for example, a stress or crystal that causes strain in the object to be measured and causes stress in the direction in which the second storage element M2 and the third storage element M3 are arranged (for example, compression strain in the crystal axis <100> direction of the semiconductor substrate 9). It is assumed that a stress that causes tensile strain in the axial <010> direction) is applied. As a result, as shown in FIG. 11A, the electron mobility of the first output transistor M1r becomes small. Therefore, the IV characteristic of the first output transistor M1r becomes the characteristic IV12 in which a current does not easily flow as compared with the characteristic IV1 in a state in which distortion is not generated (stress is not applied). As a result, the current value of the drain-source current Ids flowing through the first output transistor M1r is reduced to the current value Ia2.

On the other hand, the second output transistor M2r has a high electron mobility. Therefore, the IV characteristic of the second output transistor M2r becomes the characteristic IV22 in which a current easily flows as compared with the characteristic IV2 in a state in which no distortion is generated (stress is not applied). Since the current value of the drain-source current Ids of the second output transistor M2r is also the current value Ia2, the voltage value of the gate-source voltage Vgs of the second output transistor M2r is reduced by ΔV3 and the voltage value Vs1-ΔV3. It becomes. Therefore, the voltage value of the first detection signal Sd1 is reduced by ΔV3.

As shown in FIG. 11B, the third output transistor M3r has a high electron mobility. Therefore, the IV characteristic of the third output transistor M3r is the characteristic IV31 in which a current easily flows as compared with the characteristic IV3 in a state in which no distortion is generated (stress is not applied). As a result, the current value of the drain-source current Ids flowing through the third output transistor M3r rises to the current value Ia4. On the other hand, the electron mobility of the fourth output transistor M4r becomes small. Therefore, the IV characteristic of the fourth output transistor M4r becomes the characteristic IV42 in which a current does not easily flow as compared with the characteristic IV4 in a state in which no strain is generated (stress is not applied). Similarly, the current value of the drain-source current Ids of the fourth output transistor M4r also becomes the current value Ia4, so that the voltage value of the gate-source voltage Vgs of the fourth output transistor M4r increases by ΔV4 to become the voltage value Vs2 + ΔV4. .. Therefore, the voltage value of the second detection signal Sd2 increases by ΔV4.

A strain is generated in the object to be measured, and a compression strain in the direction in which the second storage element M2 and the third storage element M3 are arranged (for example, a compression strain in the crystal axis <100> direction of the semiconductor substrate 9 or a tensile strain in the crystal axis <010> direction is applied. When the stress to be generated) is applied and the values of the first detection signal voltage Vs1 and the second detection signal voltage Vs2 are the same, the distortion voltage Vdt becomes “− (ΔV3 + ΔV4)” from the equation (1).

In this way, the strain sensor module 1 detects the strain generated in the object to be measured by the strain detection unit 11, and uses the signal processing unit as a signal of a voltage (distortion voltage Vdt) corresponding to the amount of distortion detected by the strain detection unit 11. The output signal OUT2 can be output from 16.

Next, the principles of offset correction and distortion error detection by the strain sensor module 1 will be described with reference to FIGS. 12 and 13. 12 (a) and 13 (a) are diagrams schematically showing an example of the voltage characteristics of the detection signal of the strain detection unit 11 with respect to the strain generated in the object to be measured. “Vs1” shown in FIGS. 12 (a) and 13 (a) shows the characteristics of the normal first detection signal voltage Vs1. “Vs2” shown in FIGS. 12 (a) and 13 (a) shows the characteristics of the normal second detection signal voltage Vs2. “Vs1e” shown in FIGS. 12 (a) and 13 (a) shows the characteristics of the abnormal first detection signal voltage Vs1 when the characteristics of the corrected first detection signal Sd1 change. As a factor of the change in the characteristics of the first detection signal Sd1 shown in FIG. 12A, the electric charge held in the floating gate leaks and the threshold voltage of at least one of the first output transistor M1r and the second output transistor M2r becomes. It can be mentioned that it has changed. As a factor of the change in the characteristics of the first detection signal Sd1 shown in FIG. 13A, there is a change in the detection sensitivity for distortion of at least one of the first output transistor M1r and the second output transistor M2r.

12 (b) and 13 (b) show that the characteristics of the second detection signal voltage Vs2 are subtracted from the characteristics of the normal and abnormal first detection signal voltage Vs1 shown in FIGS. 12 (a) and 13 (a). It is a figure which shows typically an example of the characteristic (subtraction amplification characteristic) which amplified the voltage M times. That is, FIGS. 12 (b) and 13 (b) are diagrams schematically showing an example of the characteristics of the voltage VOUT2 of the output signal SOUT2 output from the signal amplification unit 14 with respect to the distortion generated in the measurement object. “M * (Vs1-Vs2)” shown in FIGS. 12 (b) and 13 (b) shows the subtraction amplification characteristic when the first detection signal voltage Vs1 is normal. “M * (Vs1e−Vs2)” shown in FIGS. 12 (b) and 13 (b) shows the subtraction amplification characteristic when the first detection signal voltage Vs1 is abnormal.

12 (c) and 13 (c) show the characteristics of the normal and abnormal first detection signal voltage Vs1 and the characteristics of the second detection signal voltage Vs2 shown in FIGS. 12 (a) and 13 (a). It is a figure which shows typically an example of the characteristic (additional amplification characteristic) which amplified the voltage which added up to N times (in this embodiment, for example, N = 1). That is, FIGS. 12 (c) and 13 (c) schematically show an example of the characteristics of the voltage VOUT1 of the adder output signal Sa output from the adder 123 (see FIG. 3) with respect to the distortion generated in the object to be measured. It is a figure. “N * (Vs1 + Vs2)” shown in FIGS. 12 (c) and 13 (c) shows the additive amplification characteristic when the first detection signal voltage Vs1 is normal. “N * (Vs1e + Vs2)” shown in FIGS. 12 (c) and 13 (c) shows the additive amplification characteristic when the first detection signal voltage Vs1 is abnormal.

As shown in FIGS. 12A and 13A, when the first detection signal voltage Vs1 is normal, the first detection signal voltage Vs1 and the second detection signal voltage Vs2 are the same when no distortion occurs. Is the value of. Further, when the object to be measured is distorted in one direction (for example, the positive direction of the horizontal axis of the graph shown in FIGS. 12A and 13A), the first detection signal voltage Vs1 is a monotonous straight line. The second detection signal voltage Vs2 decreases in a monotonous linear manner. On the other hand, when the object to be measured is distorted in the direction opposite to the one direction (for example, the negative direction of the horizontal axis of the graphs shown in FIGS. 12A and 13A), the first detection signal voltage Vs1 decreases in a monotonous linear manner, and the second detection signal voltage Vs2 increases in a monotonous linear shape.

As shown in FIGS. 12 (b) and 13 (b), when the rate of increase / decrease with respect to the strain of the first detection signal voltage Vs1 and the second detection signal voltage Vs2 is the same, the strain and voltage VSOUT2 generated in the measurement object are used as axes. In the Cartesian coordinate system, the subtraction amplification characteristic when the first detection signal voltage Vs1 is normal is a characteristic that monotonically increases through the origin of the coordinate system. On the other hand, as shown in FIG. 12 (a), when an abnormality in which a constant offset voltage is generated with respect to a normal voltage value occurs in the first detection signal voltage Vs1, subtraction amplification is performed as shown in FIG. 12 (b). The characteristic is a characteristic that deviates from the characteristic when the first detection signal voltage Vs1 is normal by a voltage that depends on the offset voltage.

As shown in FIGS. 12 (c) and 13 (c), when the rate of increase / decrease with respect to the strain of the first detection signal voltage Vs1 and the second detection signal voltage Vs2 is the same, the strain and voltage VSOUT1 generated in the measurement object are used as axes. In the Cartesian coordinate system, the addition amplification characteristic when the first detection signal voltage Vs1 is normal is a characteristic of maintaining a constant value Vc regardless of the magnitude and direction of distortion. On the other hand, as shown in FIG. 12 (a), when an abnormality in which a constant offset voltage is generated with respect to a normal voltage value occurs in the first detection signal voltage Vs1, addition amplification is performed as shown in FIG. 12 (c). The characteristic is a characteristic that maintains a constant value Vce regardless of the magnitude and direction of the strain. The constant value Vce is a value deviated from the constant value Vc when the first detection signal voltage Vs1 is normal by a voltage depending on the offset voltage accompanying the abnormality.

As shown in FIG. 13A, when the detection sensitivity of the first detection signal Sd1 with respect to distortion changes due to aging, for example, the rate of increase / decrease of the first detection signal voltage Vs1 (that is, the slope of the voltage) is normal. Change against. Therefore, as shown in FIG. 13B, when the detection sensitivity of the first detection signal Sd1 with respect to distortion changes, the subtraction amplification characteristic depends on the change in the rate of increase / decrease with respect to the distortion of the first detection signal voltage Vs1. However, the characteristics are different from those in the normal case.

Similarly, as shown in FIG. 13C, when the detection sensitivity of the first detection signal Sd1 with respect to distortion changes, the additive amplification characteristic depends on the change in the rate of increase / decrease with respect to the distortion of the first detection signal voltage Vs1. However, the characteristics are changed from the characteristics in the normal case. Therefore, the addition amplification characteristic when the detection sensitivity to the distortion of the first detection signal Sd1 changes does not become a characteristic that maintains a constant value.

Therefore, the voltage value of the first detection signal voltage Vs1 and the voltage value of the second detection signal voltage Vs2 are within a predetermined range in which the detection error of the distortion detection unit 11 and the calculation error of the adder 123 and the like are taken into consideration. By adjusting the first detection signal voltage Vs1 and the second detection signal voltage Vs2 so as to be within the same range, the offsets of the first detection signal Sd1 and the second detection signal Sd2 can be corrected.

Further, the voltage value of the added signal obtained by adding the first detection signal Sd1 and the second detection signal Sd2 is within a predetermined voltage range with respect to a predetermined voltage value (constant value Vc in FIGS. 12 (c) and 13 (c)). If not, it can be determined that the distortion detected by the distortion detection unit 11 is a false detection.

Here, the specific operation of the distortion error detection operation mode in the strain sensor module 1 according to the present embodiment will be described again with reference to FIGS. 2 and 3.
The mode selection unit 15 provided in the distortion sensor module 1 selects the addition output signal Sa in the offset correction operation mode, and selects the voltage division signal Sdi in the distortion error detection operation mode 124 (see FIG. 3). ) Is configured to select. Therefore, when the distortion sensor module 1 operates in the distortion error detection operation mode, the switch 124a provided in the signal selection unit 124 is the other input terminal based on the control signal Smc output from the mode selection unit 15. And the output terminal are connected.

The mode selection unit 15 stores the comparison signal Sc. The voltage value of the comparison signal Sc is set to the same value as the voltage value of the added signal obtained by adding the offset-corrected first detection signal Sd1 and the second detection signal Sd2. In the present embodiment, the offsets of the first detection signal Sd1 and the second detection signal Sd2 are corrected so as to be, for example, 1/2 of the power supply voltage VDD. Therefore, in the present embodiment, the voltage value of the comparison signal Sc is set to the same value as, for example, the voltage value of the power supply voltage VDD. The resistance values of the resistance element R1 and the resistance element R2 are set so that the voltage value of the voltage dividing signal Sdi is, for example, half the voltage value of the power supply voltage VDD. The resistance value of the resistance element R3 and the resistance value of the resistance element R1 are the same, and the resistance value of the resistance element R5 and the resistance value of the resistance element R2 are the same. Therefore, when the offsets of the first detection signal Sd1 and the second detection signal Sd2 are corrected, the non-inverting input terminal (+) and the inverting input terminal (-) of the amplifier 125a of the differential amplification unit 125 are connected. , Signals with the same voltage value (in this embodiment, a voltage value that is 1/2 of the power supply voltage VDD) are input.

As described with reference to FIGS. 12 (c) and 13 (c), when the strain detection unit 11 detects the strain generated in the object to be measured in a normal state, the first detection signal voltage Vs1 and The voltage obtained by adding the second detection signal voltage Vs2 becomes a constant value Vc regardless of whether or not the object to be measured is distorted. Therefore, when the strain detection unit 11 detects the strain generated in the measurement target object in a normal state, the voltage value of the voltage dividing signal Sdi is the voltage value regardless of whether the measurement target object is distorted or not. The differential amplification unit 125 outputs an output signal SOUT1 having a constant value and a voltage value of 0V to the signal processing unit 16.

On the other hand, when the distortion detection unit 11 detects the distortion generated in the object to be measured in an abnormal state, the distortion detection unit 11 determines the voltage obtained by adding the first detection signal voltage Vs1 and the second detection signal voltage Vs2. It changes according to the amount of strain generated in the object to be measured. Therefore, when the strain detection unit 11 detects the strain generated in the measurement object in an abnormal state, the voltage value of the voltage dividing signal Sdi changes depending on whether the strain is generated in the measurement object or the amount of strain. .. As a result, the differential amplification unit 125 outputs the output signal SOUT1 having a voltage value other than 0V to the signal processing unit 16 when the distortion detection unit 11 detects the distortion generated in the measurement object in an abnormal state. do.

As a result, when the distortion detection operation mode is selected by the mode selection unit 15, the signal processing unit 16 receives the output signal SOUT1 (signal of a predetermined voltage) having a voltage value within a predetermined range including 0V by the differential amplification unit 125. When an example) is being output, the distortion detection unit 11 outputs a signal indicating that distortion is normally detected (a digital output signal OUT1 indicating a voltage value within a predetermined range including 0V). Further, when the distortion error detection operation mode is selected by the mode selection unit 15, the signal processing unit 16 tells the signal processing unit 16 that the differential amplification unit 125 outputs an output signal SOUT1 (from a predetermined voltage to a threshold voltage) having a voltage value outside a predetermined range including 0V. When an example of a voltage signal deviated by the above is output, a signal indicating that the distortion detection unit 11 has not detected distortion normally (a digital output indicating a voltage value outside a predetermined range including 0V) is output. Output the signal OUT1).

In this way, the strain sensor module 1 outputs an output signal OUT1 having a different value depending on whether or not the strain detection unit 11 normally detects the strain to an external device, and erroneously detects the strain in the strain detection unit 11. Can be detected.

(Offset correction method)
The offset correction method according to the present embodiment will be described with reference to FIGS. 14 to 28. First, the flow of the offset correction method of the strain sensor module 1 of the present embodiment will be described with reference to FIG. In the present embodiment, each component such as the mode selection unit 15 shown in FIG. 1 is controlled by a control unit (not shown) that collectively controls the strain sensor module 1, and the detection signal output from the strain detection unit 11 The offset is corrected.

(Step S100)
As shown in FIG. 14A, when the offset correction process according to the present embodiment is started, the sensor output target voltage is first determined (step S100), and the process proceeds to step S200. More specifically, as the sensor output target voltage, the set value of the first detection signal voltage Vs1 of the first detection signal Sd1 and the second detection signal of the second detection signal Sd2, which are the detection signals output from the distortion detection unit 11. The set value of the voltage Vs2 is determined. In the present embodiment, for example, the first detection signal voltage Vs1 of the first detection signal Sd1 and the second detection signal voltage Vs2 of the second detection signal Sd2 are set to 1/2 of the voltage value of the power supply voltage VDD as the sensor output target voltage. Will be done.

(Step S200)
In step S200, the first detection signal voltage Vs1 of the first detection signal Sd1 and the second detection signal voltage Vs2 of the second detection signal Sd2 are detected as sensor outputs from the distortion detection unit 11, and the process proceeds to step S300. ..

Steps S100 and S200 are output voltage detection processes of the distortion detection unit, which are executed to detect the voltage of the detection signal at the present time before correcting the offset of the detection signal output from the distortion detection unit 11. be.

(Step S300)
In step S300, the output voltage setting process of the detection signal output from the distortion detection unit 11 is executed, and the offset correction process is completed. In step S300, the respective voltage values of the first detection signal voltage Vs1 of the first detection signal Sd1 and the second detection signal voltage Vs2 of the second detection signal Sd2 are the same as the voltage value of the target voltage set in step S100. Is set to be.

Here, a specific process in the output voltage setting process (step S300) will be described with reference to FIG. 14 (b).

(Step S310)
When the output voltage setting process (step S300) is started, first, in step S310, the first output transistor M1r and the third output transistor M3r are set to the reference state, and the process proceeds to the process of step S320. In step S310, a first output transistor M1r, a second output transistor M2r, a third output transistor M3r, and a fourth output transistor M4r (4 pieces) that form a Wheatstone bridge circuit and change the electron mobility according to the distortion of the object to be measured. Threshold of the first output transistor M1r and the third output transistor M3r (an example of two electric field effect transistors arranged on the power supply side) arranged on the output terminal side of the power supply voltage VDD (an example of the electric field effect transistor). The voltage is adjusted, and the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r are arranged on the reference potential terminal (ground terminal) side connected to the reference potential. The first output transistor M1r and the third output transistor M3r are set in a reference state in which no current flows through each of the second output transistor M2r and the fourth output transistor M4r (an example of the residual electric field effect transistor arranged on the reference potential side). do.

(Step S320)
In step S320, the second output transistor M2r is set, and the process proceeds to step S330. Specifically, the threshold voltage of the second output transistor M2r (an example of one of the residual field effect transistors) is controlled to set the second output transistor M2r to a predetermined state. Here, the predetermined state of the second output transistor M2r is a state in which the gate-source voltage Vgs of the second output transistor M2r becomes the same voltage as the target voltage of the first detection signal voltage Vs1.

(Step S330)
In step S330, the first output transistor M1r is set, and the process proceeds to step S340. Specifically, the threshold voltage of the first output transistor M1r (an example of one of the two field effect transistors) is controlled to set the first output transistor M1r to a predetermined state. Here, the predetermined state of the first output transistor M1r is a state in which the gate-source voltage Vgs of the first output transistor M1r becomes the same voltage value as the voltage obtained by subtracting the first detection signal voltage Vs1 from the power supply voltage VDD. Is. In the present embodiment, the voltage value of the gate-source voltage Vgs of the first output transistor M1r is half the value of the voltage value of the power supply voltage VDD, that is, the same voltage as the target voltage of the first detection signal voltage Vs1. Is set.

(Step S340)
In step S340, the fourth output transistor M4r is set, and the process proceeds to step S350. Specifically, the threshold voltage of the fourth output transistor M4r (another example of the residual field effect transistor) is controlled to set the other field effect transistor in a predetermined state. Here, the predetermined state of the fourth output transistor M4r is a state in which the gate-source voltage Vgs of the fourth output transistor M4r becomes the same voltage as the target voltage of the second detection signal voltage Vs2.

(Step S350)
In step S350, the third output transistor M3r is set, and the output voltage setting process is completed. Specifically, the threshold voltage of the third output transistor M3r (another example of the two field effect transistors) is controlled to set the third output transistor M3r to a predetermined state. Here, the predetermined state of the third output transistor M3r is a state in which the gate-source voltage Vgs of the third output transistor M3r becomes the same voltage value as the voltage obtained by subtracting the second detection signal voltage Vs2 from the power supply voltage VDD. Is. In the present embodiment, the voltage value of the gate-source voltage Vgs of the third output transistor M3r is half the value of the voltage value of the power supply voltage VDD, that is, the same voltage as the target voltage of the second detection signal voltage Vs2. Is set.

Next, the output voltage setting process will be described more specifically with reference to FIGS. 15 to 28. FIG. 15A schematically shows an example of the timing chart of the processes of steps S320 and S330 in the output voltage setting process. FIG. 15B schematically shows an example of the timing chart of the processes of steps S340 and S350 in the output voltage setting process.

In the process of step S310 shown in FIG. 14B, as shown in FIG. 16, in order to set the first output transistor M1r and the third output transistor M3r to the reference state, the switches SW1 to SW16 are in the following states. Switch to.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Connection state (short state)
Switch SW4: Open state (open state)
Switch SW5: Open state (open state)
Switch SW6: Open state (open state)
Switch SW7: Pulse voltage VPP side Switch SW8: Arbitrary (reference potential VSS side in FIG. 16)
Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Connection state (short state)
Switch SW12: Open state (open state)
Switch SW13: Open state (open state)
Switch SW14: Open state (open state)
Switch SW15: Pulse voltage VPP side Switch SW16: Arbitrary (reference potential VSS side in FIG. 16)

As a result, the pulse voltage VPP is applied to the control gate CGw of the first charge flow element M1w, and the impurity diffusion region IR of the first charge flow element M1w is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. Will be done. Therefore, charges (electrons in this embodiment) are injected into the floating gate FGw of the first charge flow element M1w from the reference potential terminal (ground terminal) via the impurity diffusion region IR and the charge flow region 811. Further, an electric charge (electrons in this embodiment) is injected from the floating gate FGw to the floating gate FGr of the first output transistor M1r via the connection gate NGf. As a result, the threshold voltage of the first output transistor M1r becomes high. Even if the pulse voltage VPP is applied to the control gate CGr of the first output transistor M1r and the power supply voltage VDD is applied to the drain D of the first output transistor M1r, the drain-source current Ids does not flow until the first output transistor M1r A charge (electrons in this embodiment) is injected into the floating gate FGr so that the threshold voltage of the above is high. As a result, the first output transistor M1r is adjusted to a reference state in which the drain-source current Ids does not flow.

Similarly, a pulse voltage VPP is applied to the control gate CGw of the third charge flow element M3w, and the impurity diffusion region IR of the third charge flow element M3w is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. Will be done. Therefore, charges (electrons in this embodiment) are injected into the floating gate FGw of the third charge flow element M3w from the reference potential terminal (ground terminal) via the impurity diffusion region IR and the charge flow region 811. Further, an electric charge (electrons in this embodiment) is injected from the floating gate FGw to the floating gate FGr of the third output transistor M3r via the connection gate NGf. As a result, the threshold voltage of the third output transistor M3r becomes high. Even if the pulse voltage VPP is applied to the control gate CGr of the third output transistor M3r and the power supply voltage VDD is applied to the drain D of the third output transistor M3r, the drain-source current Ids does not flow until the third output transistor M3r A charge (electrons in this embodiment) is injected into the floating gate FGr so that the threshold voltage of the above is high. As a result, the third output transistor M3r is adjusted to a reference state in which the drain-source current Ids does not flow. In this way, the first adjustment process in which the first output transistor M1r and the second output transistor M2r are adjusted to the reference state is executed.

In the process of step S320 shown in FIG. 14B, first, as shown in FIG. 17, the second output transistor M2r has a voltage higher than the target voltage Vg1 (for example, 0.1 V to 0.3 V with respect to the target voltage Vg1). The switches SW1 to SW16 are switched to the following states in order to set the voltage (high voltage).
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Connection state (short state)
Switch SW5: Open state (open state)
Switch SW6: Open state (open state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 17)
Switch SW8: Pulse voltage VPP side Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Open state (open state)
Switch SW13: Open state (open state)
Switch SW14: Open state (open state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 17)
Switch SW16: Arbitrary (reference potential VSS side in FIG. 17)

As a result, the pulse voltage VPP is applied to the control gate CGw of the second charge flow element M2w, and the impurity diffusion region IR of the second charge flow element M2w is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. Will be done. Therefore, charges (electrons in this embodiment) are injected into the floating gate FGw of the second charge flow element M2w from the reference potential terminal (ground terminal) via the impurity diffusion region IR and the charge flow region 811. Further, electric charges (electrons in this embodiment) are injected from the floating gate FGw into the floating gate FGr of the second output transistor M2r via the connection gate NGf. As a result, the threshold voltage of the second output transistor M2r becomes high. Charges (electrons in this embodiment) are injected into the floating gate FGr so that the gate-source voltage Vgs of the second output transistor M2r becomes higher than the target voltage Vg1 of the first detection signal voltage Vs1. In this way, the second adjustment process is executed in which the gate-source voltage Vgs of the second output transistor M2r is adjusted to be higher than the target voltage Vg1 of the first detection signal voltage Vs1.

In the process of step S320 shown in FIG. 14B, the adjustment current Iref is seconded from the first output terminal To1 in order to confirm the voltage value of the first detection signal voltage Vs1 as shown in FIG. While inputting to the output transistor M2r, the switches SW1 to SW16 are switched to the following states.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Open state (open state)
Switch SW5: Open state (open state)
Switch SW6: Connection state (short state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 18)
Switch SW8: Arbitrary (reference potential VSS side in FIG. 18)
Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Connection state (short state)
Switch SW13: Open state (open state)
Switch SW14: Connection state (short state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 18)
Switch SW16: Reference potential VSS side

Since the second output terminal To2 is connected to the reference potential terminal (ground terminal) that becomes the reference potential VSS via the switch SW14, the switch SW12, and the switch SW16, the voltage value of the second detection signal voltage Vs2 becomes 0V. .. Therefore, the added signal voltage obtained by adding the first detection signal voltage Vs1 and the second detection signal voltage Vs2 becomes the voltage of the first detection signal voltage Vs1.

In the distortion sensor module 1, in the offset correction operation mode, the switch 124a of the signal selection unit 124 is switched so that the addition output signal Sa output from the adder 123 (see FIG. 3) is input to the differential amplification unit 125. .. The voltage value of the additional output signal Sa is the voltage value of the first detection signal voltage Vs1 (that is, the voltage value of the gate-source voltage Vgs of the second output transistor M2r). An additional output signal Sa is input to the inverting input terminal (-) of the amplifier 125a provided in the differential amplification unit 125, and 1 / of the voltage value of the comparison signal Sc is input to the non-inverting input terminal (+) of the amplifier 125a. A signal with the same value as 2 is input.

The same value as 1/2 of the voltage value of the comparison signal Sc is a value of 1/2 of the voltage value of the power supply voltage VDD in this embodiment. On the other hand, the gate-source voltage Vgs of the second output transistor M2r immediately after the second adjustment process is set to a voltage value larger than 1/2 of the voltage value of the power supply voltage VDD. Therefore, in the first confirmation process, it is determined that the gate-source voltage Vgs of the second output transistor M2r, that is, the first detection signal voltage Vs1, has not reached the target voltage Vg1.

In the process of step S320 shown in FIG. 14B, the switches SW1 to SW16 are switched to the following states in order to bring the second output transistor M2r closer to the target voltage Vg1 as shown in FIG.
Switch SW1: Reference potential VSS side Switch SW2: Pulse voltage VPP side Switch SW3: Open state (open state)
Switch SW4: Connection state (short state)
Switch SW5: Open state (open state)
Switch SW6: Open state (open state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 19)
Switch SW8: Arbitrary (reference potential VSS side in FIG. 19)
Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Connection state (short state)
Switch SW13: Open state (open state)
Switch SW14: Connection state (short state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 19)
Switch SW16: Reference potential VSS side

Since the second output terminal To2 is connected to the reference potential terminal (ground terminal) that becomes the reference potential VSS via the switch SW14, the switch SW12, and the switch SW16, the voltage value of the second detection signal voltage Vs2 becomes 0V. .. Therefore, the added signal voltage obtained by adding the first detection signal voltage Vs1 and the second detection signal voltage Vs2 becomes the voltage of the first detection signal voltage Vs1.

Further, the control gate CGw of the second charge flow element M2w is connected to a reference potential terminal (ground terminal) serving as a reference potential VSS, and a pulse voltage VPP is applied to the impurity diffusion region IR of the second charge flow element M2w. .. Therefore, the charges (electrons in this embodiment) held in the floating gate FGw of the second output transistor M2r, the connection gate NGf, and the floating gate FGw of the first charge flow element M1w are the charge flow region 811 and the impurity diffusion region. It is discharged to the reference potential terminal (ground terminal) via IR. As a result, the threshold voltage of the second output transistor M2r becomes low. In this way, a third adjustment process is executed in which the gate-source voltage Vgs of the second output transistor M2r is adjusted to approach the target voltage Vg1 of the first detection signal voltage Vs1.

Although not shown, after the third adjustment process is completed, the same confirmation process as described with reference to FIG. 18 is executed, and the gate-source voltage Vgs of the second output transistor M2r at the present time, that is, the first The voltage value of the detection signal voltage Vs1 is confirmed. As shown in FIG. 15A, the confirmation process and the third adjustment process are repeatedly executed so that the gate-source voltage Vgs of the second output transistor M2r, that is, the first detection signal voltage Vs1 becomes the same as the target voltage Vg1. The threshold voltage of the second output transistor M2r is adjusted, and the setting process of the second output transistor M2r is completed.

As described above, in the process of confirming the gate-source voltage Vgs of the second output transistor M2r, the floating gate FGr provided in each of the first output transistor M1r and the third output transistor M3r (an example of two electric field effect transistors). In a state where the first output transistor M1r and the third output transistor M3r are set to the reference state while holding a predetermined amount of charge, the fourth output transistor M4r (another example of the residual electric field effect transistor) is designated. The adjustment current Iref is input to the second output transistor M2r (an example of one of the residual electric field effect transistors) without inputting the current value adjustment current, and the floating gate FGr provided in the second output transistor M2r. The amount of charge accumulated in the second output transistor M2r is controlled to set the second output transistor M2r to a predetermined state. Here, the predetermined state is a state in which the gate-source voltage Vgs of the second output transistor M2r is within a predetermined range including the same voltage as the target voltage Vg1.

In the process of step S330 shown in FIG. 14B, first, as shown in FIG. 20, the threshold voltage of the first output transistor M1r is set to a sufficiently low value (for example, 0.1V to 0.3V). (1) In order to set the detection signal voltage Vs1 to a voltage higher than the target voltage Vg1, the switches SW1 to SW16 are switched to the following states.
Switch SW1: Pulse voltage VPP side Switch SW2: Reference potential VSS side Switch SW3: Connection state (short state)
Switch SW4: Open state (open state)
Switch SW5: Open state (open state)
Switch SW6: Open state (open state)
Switch SW7: Reference potential VSS side Switch SW8: Arbitrary (reference potential VSS side in FIG. 20)
Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Open state (open state)
Switch SW13: Open state (open state)
Switch SW14: Open state (open state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 20)
Switch SW16: Arbitrary (reference potential VSS side in FIG. 20)

As a result, the control gate CGw of the first charge flow element M1w is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS, and the pulse voltage VPP is applied to the impurity diffusion region IR of the first charge flow element M1w. NS. Therefore, the charges (electrons in this embodiment) held in the floating gate FGw of the first output transistor M1r, the connection gate NGf, and the floating gate FGw of the first charge flow element M1w are the charge flow region 811 and the impurity diffusion region. It is discharged to the reference potential terminal (ground terminal) via IR. As a result, the threshold voltage of the first output transistor M1r is set to a sufficiently low value. In this way, a fourth adjustment process is executed in which the gate-source voltage Vgs of the first output transistor M1r is adjusted to approach the target voltage Vg1 of the first detection signal voltage Vs1.

In the process of step S330 shown in FIG. 14B, the switches SW1 to SW16 are switched to the following states in order to confirm the voltage value of the first detection signal voltage Vs1 as shown in FIG.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Open state (open state)
Switch SW5: Connection state (short state)
Switch SW6: Connection state (short state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 22)
Switch SW8: Arbitrary (reference potential VSS side in FIG. 22)
Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Connection state (short state)
Switch SW13: Open state (open state)
Switch SW14: Connection state (short state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 22)
Switch SW16: Reference potential VSS side

Since the second output terminal To2 is connected to the reference potential terminal (ground terminal) that becomes the reference potential VSS via the switch SW14, the switch SW12, and the switch SW16, the voltage value of the second detection signal voltage Vs2 becomes 0V. .. Therefore, the added signal voltage obtained by adding the first detection signal voltage Vs1 and the second detection signal voltage Vs2 becomes the voltage of the first detection signal voltage Vs1.

The gate-source voltage Vgs of the first output transistor M1r immediately after the fourth adjustment process is set to a voltage value smaller than 1/2 of the voltage value of the power supply voltage VDD. Therefore, in the first confirmation process after the fourth adjustment process, it is determined that the gate-source voltage Vgs of the first output transistor M1r, that is, the first detection signal voltage Vs1, has not reached the target voltage Vg1.

In the process of step S330 shown in FIG. 14B, the switches SW1 to SW16 are switched to the following states in order to bring the first output transistor M1r closer to the target voltage Vg1 as shown in FIG. 22.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Connection state (short state)
Switch SW4: Open state (open state)
Switch SW5: Open state (open state)
Switch SW6: Open state (open state)
Switch SW7: Pulse voltage VPP side Switch SW8: Arbitrary (reference potential VSS side in FIG. 22)
Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Open state (open state)
Switch SW13: Open state (open state)
Switch SW14: Open state (open state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 22)
Switch SW16: Arbitrary (reference potential VSS side in FIG. 22)

As a result, the pulse voltage VPP is applied to the control gate CGw of the first charge flow element M1w, and the impurity diffusion region IR of the first charge flow element M1w is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. Will be done. Therefore, charges (electrons in this embodiment) are injected into the floating gate FGw of the first charge flow element M1w from the reference potential terminal (ground terminal) via the impurity diffusion region IR and the charge flow region 811. Further, an electric charge (electrons in this embodiment) is injected from the floating gate FGw to the floating gate FGr of the first output transistor M1r via the connection gate NGf. As a result, the threshold voltage of the first output transistor M1r becomes high. In this way, the fifth adjustment process is executed in which the gate-source voltage Vgs of the first output transistor M1r is adjusted so that the first detection signal voltage Vs1 approaches the target voltage Vg1.

Although not shown, after the fifth adjustment process is completed, the same confirmation process as described with reference to FIG. 21 is executed, and the gate-source voltage Vgs of the first output transistor M1r at the present time, that is, the first The voltage value of the detection signal voltage Vs1 is confirmed. As shown in FIG. 15A, the confirmation process and the fifth adjustment process are repeatedly executed so that the gate-source voltage Vgs of the first output transistor M1r, that is, the first detection signal voltage Vs1 becomes the same as the target voltage Vg1. The threshold voltage of the first output transistor M1r is adjusted, and the setting process of the first output transistor M1r is completed.

In this way, the first detection as a detection signal is output from the connection portion of the first output transistor M1r (one example of two electric field effect transistors) and the second output transistor M2r (one example of the remaining electric field effect transistor). The signal Sd1 is output from the connection portion of the third output transistor M3r (the other example of the two electric field effect transistors) and the fourth output transistor M4r (the other example of the residual electric field effect transistor) to be the first detection signal. (Ii) In a state where the adjustment current Iref is not input to the first output transistor M1r and the third output transistor M3r so that the voltage of the added signal obtained by adding the detection signal Sd2 becomes the target voltage Vg1 (an example of a predetermined voltage value). , The amount of charge accumulated in the floating gate FGr provided in the first output transistor M1r is controlled to set the first output transistor M1r in a predetermined state. Here, the predetermined state is a state in which the gate-source voltage Vgs of the second output transistor M2r is within a predetermined range including the same voltage as the target voltage Vg1.

In the process of step S340 shown in FIG. 14B, first, as shown in FIG. 23, the fourth output transistor M4r has a voltage higher than the target voltage Vg2 (for example, 0.1 V to 0.3 V with respect to the target voltage Vg2). The switches SW1 to SW16 are switched to the following states in order to set the voltage (high voltage).
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Open state (open state)
Switch SW5: Open state (open state)
Switch SW6: Open state (open state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 23)
Switch SW8: Arbitrary (reference potential VSS side in FIG. 23)
Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Connection state (short state)
Switch SW13: Open state (open state)
Switch SW14: Open state (open state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 23)
Switch SW16: Pulse voltage VPP side

As a result, the pulse voltage VPP is applied to the control gate CGw of the fourth charge flow element M4w, and the impurity diffusion region IR of the fourth charge flow element M4w is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. Will be done. Therefore, charges (electrons in this embodiment) are injected into the floating gate FGw of the fourth charge flow element M4w from the reference potential terminal (ground terminal) via the impurity diffusion region IR and the charge flow region 811. Further, electric charges (electrons in this embodiment) are injected from the floating gate FGw to the floating gate FGr of the fourth output transistor M4r via the connection gate NGf. As a result, the threshold voltage of the fourth output transistor M4r becomes high. Charges (electrons in this embodiment) are injected into the floating gate FGr so that the gate-source voltage Vgs of the fourth output transistor M4r becomes higher than the target voltage Vg2 of the second detection signal voltage Vs2. In this way, the sixth adjustment process is executed in which the gate-source voltage Vgs of the fourth output transistor M4r is adjusted to be higher than the target voltage Vg2 of the second detection signal voltage Vs2.

In the process of step S340 shown in FIG. 14B, subsequently, as shown in FIG. 24, in order to confirm the voltage value of the second detection signal voltage Vs2, the adjustment current Iref is set from the second output terminal To2 to the fourth. While inputting to the output transistor M4r, the switches SW1 to SW16 are switched to the following states.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Connection state (short state)
Switch SW5: Open state (open state)
Switch SW6: Connection state (short state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 24)
Switch SW8: Reference potential VSS side Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Open state (open state)
Switch SW13: Open state (open state)
Switch SW14: Connection state (short state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 24)
Switch SW16: Arbitrary (reference potential VSS side in FIG. 24)

Since the first output terminal To1 is connected to the reference potential terminal (ground terminal) that becomes the reference potential VSS via the switch SW6, the switch SW4, and the switch SW8, the voltage value of the first detection signal voltage Vs1 becomes 0V. .. Therefore, the added signal voltage obtained by adding the first detection signal voltage Vs1 and the second detection signal voltage Vs2 becomes the voltage of the second detection signal voltage Vs2.

In the distortion sensor module 1, in the offset correction operation mode, the switch 124a of the signal selection unit 124 is switched so that the addition output signal Sa output from the adder 123 (see FIG. 3) is input to the differential amplification unit 125. .. The voltage value of the additional output signal Sa is the voltage value of the second detection signal voltage Vs2 (that is, the voltage value of the gate-source voltage Vgs of the fourth output transistor M4r). An additional output signal Sa is input to the inverting input terminal (-) of the amplifier 125a provided in the differential amplification unit 125, and 1 / of the voltage value of the comparison signal Sc is input to the non-inverting input terminal (+) of the amplifier 125a. A signal with the same value as 2 is input.

The same value as 1/2 of the voltage value of the comparison signal Sc is a value of 1/2 of the voltage value of the power supply voltage VDD in this embodiment. On the other hand, the gate-source voltage Vgs of the fourth output transistor M4r immediately after the sixth adjustment process is set to a voltage value larger than 1/2 of the voltage value of the power supply voltage VDD. Therefore, in the first confirmation process after the sixth adjustment process, it is determined that the gate-source voltage Vgs of the fourth output transistor M4r, that is, the second detection signal voltage Vs2 has not reached the target voltage.

In the process of step S340 shown in FIG. 14B, the switches SW1 to SW16 are switched to the following states in order to bring the fourth output transistor M4r closer to the target voltage as shown in FIG. 25.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Connection state (short state)
Switch SW5: Open state (open state)
Switch SW6: Connection state (short state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 25)
Switch SW8: Reference potential VSS side Switch SW9: Reference potential VSS side Switch SW10: Pulse voltage VPP side Switch SW11: Open state (open state)
Switch SW12: Connection state (short state)
Switch SW13: Open state (open state)
Switch SW14: Open state (open state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 25)
Switch SW16: Reference potential VSS side

Since the first output terminal To1 is connected to the reference potential terminal (ground terminal) that becomes the reference potential VSS via the switch SW6, the switch SW4, and the switch SW8, the voltage value of the first detection signal voltage Vs1 becomes 0V. .. Therefore, the added signal voltage obtained by adding the first detection signal voltage Vs1 and the second detection signal voltage Vs2 becomes the voltage of the second detection signal voltage Vs2.

Further, the control gate CGw of the fourth charge flow element M4w is connected to a reference potential terminal (ground terminal) serving as a reference potential VSS, and a pulse voltage VPP is applied to the impurity diffusion region IR of the fourth charge flow element M4w. .. Therefore, the charges (electrons in this embodiment) held in the floating gate FGw of the fourth output transistor M4r, the connection gate NGf, and the floating gate FGw of the fourth charge flow element M4w are the charge flow region 811 and the impurity diffusion region. It is discharged to the reference potential terminal (ground terminal) via IR. As a result, the threshold voltage of the fourth output transistor M4r becomes low. In this way, a seventh adjustment process is executed in which the gate-source voltage Vgs of the fourth output transistor M4r is adjusted to approach the target voltage Vg2 of the second detection signal voltage Vs2.

Although not shown, after the seventh adjustment process is completed, the same confirmation process as described with reference to FIG. 24 is executed, and the gate-source voltage Vgs of the fourth output transistor M4r at the present time, that is, the second The voltage value of the detection signal voltage Vs2 is confirmed. As shown in FIG. 15B, the confirmation process and the seventh adjustment process are repeatedly executed so that the gate-source voltage Vgs of the fourth output transistor M4r, that is, the second detection signal voltage Vs2 becomes the same as the target voltage Vg2. The threshold voltage of the fourth output transistor M4r is adjusted, and the setting process of the fourth output transistor M4r is completed.

As described above, in the process of confirming the gate-source voltage Vgs of the fourth output transistor M4r, the floating gate FGr provided in each of the first output transistor M1r and the third output transistor M3r (an example of two electric field effect transistors). For adjustment to the second output transistor M2r (one example of the residual electric field effect transistor) with the first output transistor M1r and the third output transistor M3r set to the reference state while holding a predetermined amount of charge. The amount of charge accumulated in the floating gate FGr provided in the fourth output transistor M4r by inputting the adjustment current Iref into the fourth output transistor M4r (another example of the residual electric field effect transistor) without inputting the current Iref. Is controlled to set the fourth output transistor M4r to a predetermined state. Here, the predetermined state is a state in which the gate-source voltage Vgs of the fourth output transistor M4r is within a predetermined range including the same voltage as the target voltage Vg2.

In the process of step S350 shown in FIG. 14B, first, as shown in FIG. 26, the threshold voltage of the third output transistor M3r is set to a sufficiently low value (for example, 0.1V to 0.3V). (Ii) In order to set the detection signal voltage Vs2 to a voltage higher than the target voltage Vg2, the switches SW1 to SW16 are switched to the following states.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Open state (open state)
Switch SW5: Open state (open state)
Switch SW6: Open state (open state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 26)
Switch SW8: Arbitrary (reference potential VSS side in FIG. 26)
Switch SW9: Pulse voltage VPP side Switch SW10: Reference potential VSS side Switch SW11: Connection state (short state)
Switch SW12: Open state (open state)
Switch SW13: Open state (open state)
Switch SW14: Open state (open state)
Switch SW15: Reference potential VSS side Switch SW16: Arbitrary (reference potential VSS side in FIG. 26)

As a result, the control gate CGw of the third charge flow element M3w is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS, and the pulse voltage VPP is applied to the impurity diffusion region IR of the third charge flow element M3w. NS. Therefore, the charges (electrons in this embodiment) held in the floating gate FGw of the third output transistor M3r, the connection gate NGf, and the floating gate FGw of the third charge flow element M3w are the charge flow region 811 and the impurity diffusion region. It is discharged to the reference potential terminal (ground terminal) via IR. As a result, the threshold voltage of the third output transistor M3r is set to a sufficiently low value (for example, 0.1 V to 0.3 V). In this way, the eighth adjustment process in which the gate-source voltage Vgs of the third output transistor M3r is adjusted to approach the target voltage Vg2 of the second detection signal voltage Vs2 is executed.

In the process of step S350 shown in FIG. 14B, the switches SW1 to SW16 are switched to the following states in order to confirm the voltage value of the second detection signal voltage Vs2 as shown in FIG. 26.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Connection state (short state)
Switch SW5: Open state (open state)
Switch SW6: Connection state (short state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 27)
Switch SW8: Reference potential VSS side Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Open state (open state)
Switch SW12: Open state (open state)
Switch SW13: Connection state (short state)
Switch SW14: Connection state (short state)
Switch SW15: Arbitrary (reference potential VSS side in FIG. 27)
Switch SW16: Arbitrary (reference potential VSS side in FIG. 27)

Since the first output terminal To1 is connected to the reference potential terminal (ground terminal) that becomes the reference potential VSS via the switch SW6, the switch SW4, and the switch SW8, the voltage value of the first detection signal voltage Vs1 becomes 0V. .. Therefore, the added signal voltage obtained by adding the first detection signal voltage Vs1 and the second detection signal voltage Vs2 becomes the voltage of the second detection signal voltage Vs2.

The gate-source voltage Vgs of the third output transistor M3r immediately after the eighth adjustment process is set to a voltage value smaller than 1/2 of the voltage value of the power supply voltage VDD. Therefore, in the first confirmation process after the eighth adjustment process, it is determined that the gate-source voltage Vgs of the third output transistor M3r, that is, the second detection signal voltage Vs2 has not reached the target voltage Vg2.

In the process of step S350 shown in FIG. 14B, the switches SW1 to SW16 are switched to the following states in order to bring the third output transistor M3r closer to the target voltage Vg2 as shown in FIG. 28.
Switch SW1: Reference potential VSS side Switch SW2: Reference potential VSS side Switch SW3: Open state (open state)
Switch SW4: Open state (open state)
Switch SW5: Open state (open state)
Switch SW6: Open state (open state)
Switch SW7: Arbitrary (reference potential VSS side in FIG. 28)
Switch SW8: Arbitrary (reference potential VSS side in FIG. 28)
Switch SW9: Reference potential VSS side Switch SW10: Reference potential VSS side Switch SW11: Connection state (short state)
Switch SW12: Open state (open state)
Switch SW13: Open state (open state)
Switch SW14: Open state (open state)
Switch SW15: Pulse voltage VPP side Switch SW16: Arbitrary (reference potential VSS side in FIG. 28)

As a result, the pulse voltage VPP is applied to the control gate CGw of the third charge flow element M3w, and the impurity diffusion region IR of the third charge flow element M3w is connected to the reference potential terminal (ground terminal) which becomes the reference potential VSS. Will be done. Therefore, charges (electrons in this embodiment) are injected into the floating gate FGw of the third charge flow element M3w from the reference potential terminal (ground terminal) via the impurity diffusion region IR and the charge flow region 811. Further, an electric charge (electrons in this embodiment) is injected from the floating gate FGw to the floating gate FGr of the third output transistor M3r via the connection gate NGf. As a result, the threshold voltage of the third output transistor M3r becomes high. In this way, the ninth adjustment process is executed in which the gate-source voltage Vgs of the third output transistor M3r is adjusted so that the second detection signal voltage Vs2 approaches the target voltage.

Although not shown, after the ninth adjustment process is completed, the same confirmation process as described with reference to FIG. 27 is executed, and the gate-source voltage Vgs of the third output transistor M3r at the present time, that is, the second The voltage value of the detection signal voltage Vs2 is confirmed. As shown in FIG. 15B, the confirmation process and the ninth adjustment process are repeatedly executed so that the gate-source voltage Vgs of the third output transistor M3r, that is, the second detection signal voltage Vs2 becomes the same as the target voltage Vg2. The threshold voltage of the third output transistor M3r is adjusted, and the setting process of the third output transistor M3r is completed.

In this way, the first detection as a detection signal is output from the connection portion of the first output transistor M1r (one example of two electric field effect transistors) and the second output transistor M2r (one example of the remaining electric field effect transistor). The signal Sd1 is output from the connection portion of the third output transistor M3r (the other example of the two electric field effect transistors) and the fourth output transistor M4r (the other example of the residual electric field effect transistor) to be the first detection signal. (Ii) Input the adjustment current Iref to the second output transistor M2r and the fourth output transistor M4r so that the voltage of the added signal obtained by adding the detection signal Sd2 becomes the voltage value of the target voltage Vg2 (an example of a predetermined voltage value). In this state, the amount of charge accumulated in the floating gate FGr provided on the third output transistor M3r is controlled to set the third output transistor M3r to a predetermined state. Here, the predetermined state is a state in which the gate-source voltage Vgs of the third output transistor M3r is within a predetermined range including the same voltage as the target voltage Vg2.

As described above, in the offset correction method according to the present embodiment, the charge held in the floating gate FGr provided in each of the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r. The threshold voltage of the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r is adjusted by adjusting the amount of the above.
Further, in the offset correction method according to the present embodiment, the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w inject charge into the floating gate or the floating gate. It functions as a data writing element because it emits electric charge from.

As described above, the strain sensor module 1 according to the present embodiment constitutes the Wheatstone bridge circuit, and the first output transistor M1r, the second output transistor M2r, and the third output transistor M2r whose electron mobility changes according to the strain of the object to be measured A distortion detection unit 11 that has an output transistor M3r and a fourth output transistor M4r and outputs a detection signal according to the amount of distortion of the object to be measured, and an offset correction unit that corrects the offset of the detection signal output from the distortion detection unit 11. A signal amplification unit 14 that amplifies the detection signal output from the distortion detection unit 11 and a signal processing unit 16 that processes the detection signal output from the signal amplification unit 14 are provided.

Further, the offset correction method according to the present embodiment is an offset correction method for correcting the offset of the detection signal of the distortion detection unit 11 that outputs a detection signal according to the amount of distortion of the object to be measured, and constitutes a Wheatston bridge circuit. The first output transistor arranged on the power supply side of the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r whose electron mobility changes according to the distortion of the object to be measured. The threshold voltage of the M1r and the third output transistor M3r is adjusted so that no current flows through each of the second output transistor M2r and the fourth output transistor M4r arranged on the reference potential side. The output transistor M3r is set, the threshold voltage of the second output transistor M2r is controlled to set the second output transistor M2r to a predetermined state, and the threshold voltage of the first output transistor M1r is controlled to control the first output transistor. M1r is set to a predetermined state, the threshold voltage of the fourth output transistor M4r is controlled, the fourth output transistor M4r is set to a predetermined state, and the threshold voltage of the third output transistor M3r is controlled. The third output transistor M3r is set to a predetermined state.

According to the strain sensor module 1 having such a configuration and the offset correction method, the offset of the detection signal output from the strain detection unit 11 can be corrected with high accuracy.

By the way, in the conventional sensor device, since there is a possibility that a sensitivity abnormality may occur in the output voltage, a sensor device to which a function of preventing false detection is added is known (for example, Patent Document 2). The sensor device disclosed in Patent Document 2 adjusts the resistance of the bridge circuit so that the output of the bridge circuit configured by using the detection element becomes a non-zero predetermined value when no pressure is applied, and the detection voltage in this case. Is amplified at a predetermined amplification factor and output. Since the offset voltage is set to a predetermined non-zero value, the output voltage when no pressure is applied also changes. Therefore, by monitoring the output voltage when the pressure is not applied, it is possible to detect an abnormality in the sensitivity of the brake oil pressure detection circuit.

However, the sensor device disclosed in Patent Document 2 is a bridge circuit when an abnormality occurs in a bridge circuit installed in a structure such as a bridge girder for which it is unknown whether the pressure is applied or not. There is a problem that it is not possible to determine whether the output change is due to an abnormality in the sensitivity of the above, or the output change due to the detection of distortion generated in the structure.

On the other hand, the strain sensor module 1 according to the present embodiment has a strain error detection unit 13 that detects whether or not the strain detection unit 11 normally detects the strain. Therefore, the strain sensor module 1 can determine whether or not the strain detection unit 11 erroneously detects the strain. Further, when the distortion sensor module 1 determines that the distortion detection unit 11 erroneously detects the distortion, the offset correction unit 12 corrects the offset of the detection signal output from the distortion detection unit 11 to correct the distortion. False positives can be eliminated.

(Modification example 1)
The strain sensor module according to the first modification of the present embodiment will be described with reference to FIG. 29. In the distortion sensor module according to this modification, the first output transistor M1r and the third output transistor M3r are set to the depletion state in the offset correction operation mode, and the control gate CGr of the first output transistor M1r and the third output transistor M3r is set during operation. Is characterized in that it is connected to the reference potential terminal (ground terminal).

Although detailed description will be omitted, in this modification, the threshold voltage is set so that the first output transistor M1r is in the depletion state in the setting process (step S330) of the first output transistor M1r. Similarly, in this modification, in the setting process (step S350) of the third output transistor M3r, the threshold voltage is set so that the third output transistor M3r is in the depletion state.

When the strain sensor module is operated according to this modification, the switch SW3 is set to the connected state and the switch SW7 is connected to the reference potential VSS side as shown in FIG. As a result, the control gate CGr of the first output transistor M1r is connected to the reference potential VSS side. Similarly, the switch SW11 is set to the connected state, and the switch SW15 is connected to the reference potential VSS side. As a result, the control gate CGr of the third output transistor M3r is connected to the reference potential VSS side.

In the distortion sensor module according to this modification, the first output transistor M1r and the third output transistor M3r can function as constant current sources. As a result, the strain sensor module according to the present modification can reduce the change in current consumption due to the temperature change as compared with the strain sensor module 1 according to the above embodiment.

(Modification 2)
The strain sensor module according to the second modification of the present embodiment will be described with reference to FIG. The strain sensor module according to this modification has the first storage element M1 to the fourth storage element M4 of the first example shown in FIG. 5A, and the shape of the thin portion provided in the strain detection unit is different. It is characterized by points. FIG. 30 is a diagram schematically showing a main part of the strain detection unit 11 in this modified example. The plane of the strain detection unit 11 is schematically shown in the upper part of FIG. 30, and the cross section of the strain detection unit 11 cut along the line AA shown in the upper part of FIG. 30 is shown in the lower part of FIG. It is shown schematically.

As shown in FIG. 30, the strain detection unit 11 provided in the strain sensor module according to the present modification rotates 90 ° with respect to the outer circumference of the square shape when the element forming surface of the semiconductor substrate 9 is viewed in the direction orthogonal to each other. It is provided with a semiconductor substrate 9 having a square-shaped thin portion 911. That is, the thin portion 911 has a rhombic shape with respect to the outer periphery of the semiconductor substrate 9. Even if the thin portion 911 has a square shape (diamond shape with respect to the outer periphery of the semiconductor substrate 9), the first storage element M1 and the second storage element M2 of the first example shown in FIG. Each of the third storage element M3 and the fourth storage element M4 is formed in a state where the charge flow region 811 is arranged in the thick portion 912. In this modification, a part of the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w is formed in the thin portion 911, and the other part is made of meat. It is formed on the thick portion 912. A charge flow region 811 is included in each part of the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w formed in the thick portion 912. ing. Further, the relationship between each of the first storage elements M1 to the fourth storage element M4 of the first example and the direction of the crystal axis of the semiconductor substrate 9 in this modified example is the first storage of the first example shown in FIG. The relationship between each of the elements M1 to the fourth storage element M4 and the direction of the crystal axis of the semiconductor substrate 9 is the same. As a result, the strain sensor module according to the present modification has the same effect as the strain sensor module 1 according to the above embodiment.

(Modification example 3)
The strain sensor module according to the third modification of the present embodiment will be described with reference to FIG. The strain sensor module according to this modification has the first storage elements M1 to the fourth storage elements M4 of the second example shown in FIG. 5B, and is provided in the strain detection unit 11 of the modification 2. It is characterized in that it includes a semiconductor substrate 9 having the same shape as the substrate 9. FIG. 31 is a diagram schematically showing a main part of the strain detection unit 11 in this modified example. The plane of the strain detection unit 11 is schematically shown in the upper part of FIG. 31, and the cross section of the strain detection unit 11 cut along the line AA shown in the upper part of FIG. 31 is shown in the lower part of FIG. 31. It is shown schematically.

As shown in FIG. 31, even if the thin portion 911 has a square shape (diamond shape with respect to the outer circumference of the semiconductor substrate 9), the first storage element M1 of the second example shown in FIG. 5 (b). , The second storage element M2, the third storage element M3, and the fourth storage element M4 are each formed in a state where the charge flow region 811 is arranged in the thick portion 912. In this modification, the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w are all formed in the thick portion 912. Further, the relationship between each of the first storage elements M1 to the fourth storage element M4 of the second example in this modification and the direction of the crystal axis of the semiconductor substrate 9 is the first storage of the second example shown in FIG. The relationship between each of the elements M1 to the fourth storage element M4 and the direction of the crystal axis of the semiconductor substrate 9 is the same. As a result, the strain sensor module according to the present modification has the same effect as the strain sensor module 1 according to the above embodiment.

(Modification example 4)
The strain sensor module according to the third modification of the present embodiment will be described with reference to FIG. 32. The strain sensor module according to this modification is characterized in that the shape of the thin portion provided in the strain detection unit is different from that of the second modification. FIG. 32 is a diagram schematically showing a main part of the strain detection unit 11 in this modified example. The plane of the strain detection unit 11 is schematically shown in the upper part of FIG. 32, and the cross section of the strain detection unit 11 cut along the line AA shown in the upper part of FIG. 32 is shown in the lower part of FIG. It is shown schematically.

As shown in FIG. 32, the strain detecting unit 11 provided in the strain sensor module according to the present modification has a wall-thick portion 912 and a thin portion 911 arranged with a predetermined gap. The strain detection unit 11 has four connecting portions 913 that are stretched between the outer circumference of the thick portion 912 and the inner circumference of the thick portion 912 and are arranged at substantially equal intervals. The thick portion 912 is fixed to the thick portion 912 by four connecting portions 913. The four connecting portions 913 are formed to have substantially the same thickness as the thin portion 911. Two of the four connecting portions 913 are arranged side by side with the thin portion 911 interposed therebetween, for example, in the direction of the crystal axis <100> of the semiconductor substrate 9. Further, the remaining two of the four connecting portions 913 are arranged side by side with the thin portion 911 in the direction of the crystal axis <010> of the semiconductor substrate 9, for example.

In each of the first storage element M1, the second storage element M2, the third storage element M3, and the fourth storage element M4 of the first example shown in FIG. 5A, at least the charge flow region 811 is arranged in the thick portion 912. The first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r are arranged in the connection portion 913. In this modification, the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w are all formed in the thick portion 912. The relationship between each of the first storage element M1 to the fourth storage element M4 of the first example and the direction of the crystal axis of the semiconductor substrate 9 in this modification is the relationship between the first storage element M1 of the first example shown in FIG. The relationship between each of the fourth storage elements M4 and the direction of the crystal axis of the semiconductor substrate 9 is the same. As a result, the strain sensor module according to the present modification has the same effect as the strain sensor module 1 according to the above embodiment.

(Modification 5)
The strain sensor module according to the third modification of the present embodiment will be described with reference to FIG. 33. The strain sensor module according to this modification has the first storage elements M1 to the fourth storage elements M4 of the second example shown in FIG. 5B, and is a semiconductor provided in the strain detection unit 11 of the modification 4. It is characterized in that it includes a semiconductor substrate 9 having the same shape as the substrate 9. FIG. 33 is a diagram schematically showing a main part of the strain detection unit 11 in this modified example. The plane of the strain detection unit 11 is schematically shown in the upper part of FIG. 33, and the cross section of the strain detection unit 11 cut along the line AA shown in the upper part of FIG. 33 is shown in the lower part of FIG. 33. It is shown schematically.

As shown in FIG. 33, the first storage element M1, the second storage element M2, the third storage element M3, and the fourth storage element M4 of the second example shown in FIG. 5B each have at least a charge flow region 811. Is arranged in the thick portion 912, and the first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r are arranged in the connection portion 913. In this modification, the first charge flow element M1w, the second charge flow element M2w, the third charge flow element M3w, and the fourth charge flow element M4w are all formed in the thick portion 912. The relationship between each of the first storage element M1 to the fourth storage element M4 of the second example in this modification and the direction of the crystal axis of the semiconductor substrate 9 is the relationship between the first storage element M1 of the second example shown in FIG. The relationship between each of the fourth storage elements M4 and the direction of the crystal axis of the semiconductor substrate 9 is the same. As a result, the strain sensor module according to the present modification has the same effect as the strain sensor module 1 according to the above embodiment.

(Modification 6)
The strain sensor module according to the modified example 6 of the present embodiment will be described with reference to FIGS. 34 and 35. The strain sensor module according to this modification has a strain detection unit having a semiconductor substrate 9 composed of only a thick portion and four storage elements having output transistors and charge flow elements arranged adjacent to each other. It is characterized by having it. FIG. 34 schematically shows an example of the planes of the main parts of the first memory element M1, the second memory element M2, the third memory element M3, and the fourth memory element M4 provided in the strain sensor module according to this modification. It is a figure. FIG. 35 is a diagram schematically showing a main part of the strain detection unit 11 in this modified example. The plane of the strain detection unit 11 is schematically shown in the upper part of FIG. 35, and the cross section of the strain detection unit 11 cut along the line AA shown in the upper part of FIG. 35 is shown in the lower part of FIG. 35. It is shown schematically.

The planar shapes of the first storage element M1 to the fourth storage element M4 in this modification will be described by taking the first storage element M1 as an example.
As shown in FIG. 34, the first output transistor M1r and the first charge flow element M1w provided in the first storage element M1 are arranged adjacent to each other. The control gate CGr provided on the first output transistor M1r and the control gate CGw provided on the first charge flow element M1w are not connected via a connection gate, but are directly contacted and connected. Similarly, the floating gate FGr provided in the first output transistor M1r and the floating gate FGw provided in the first charge flow element M1w are not connected via the connection gate, but are directly contacted and connected. ing. Thereby, each of the first storage element M1 to the fourth storage element M4 in this modification can be miniaturized.
As shown in FIG. 35, the strain detection unit 11 provided in the strain sensor module according to this modification includes a semiconductor substrate 9 having only a wall thickness portion 912. Therefore, the first memory element M1, the second memory element M2, the third memory element M3, and the fourth memory element M4 are formed in a state where all of them including the charge flow region 811 are arranged in the thick portion 912. There is. Further, the relationship between each of the first storage element M1 to the fourth storage element M4 and the direction of the crystal axis of the semiconductor substrate 9 in this modification is the relationship between the first storage element M1 to the fourth storage element M1 to the fourth in the second example shown in FIG. The relationship between each of the storage elements M4 and the direction of the crystal axis of the semiconductor substrate 9 is the same. As a result, the strain sensor module according to the present modification is inferior in distortion detection sensitivity to the strain sensor module 1 according to the above embodiment because the semiconductor substrate 9 does not have a thin portion, but the manufacturing cost is suppressed and the size is reduced. The effect of being able to achieve this can be obtained.

[Second Embodiment]
The strain sensor module according to the second embodiment of the present invention will be described with reference to FIGS. 36 and 37. The strain sensor module according to the present embodiment has the same configuration as the strain sensor module 1 according to the first embodiment, except that the configuration of the strain detection unit is different. Therefore, regarding the strain sensor module according to the present embodiment, only the configuration of the strain detection unit will be described below, and the description of other components will be omitted.

As shown in FIG. 36, in the strain detection unit 21 provided in the strain sensor module according to the present embodiment, the connection state of the control gates provided in each of the second storage element M2 and the fourth storage element M4 is the first. It is different from the strain detection unit 11 in the embodiment. Specifically, the switch SW6 to which the control gate CGw provided on the second charge distribution element M2w is connected is connected to the connection portion of the third output transistor M3r and the fourth output transistor M4r. The switch SW14 to which the control gate CGw provided on the fourth charge distribution element M4w is connected is connected to the connection portion of the first output transistor M1r and the second output transistor M2r.

For example, when tensile strain occurs in the direction in which the third storage element M3 and the second storage element M2 are lined up, the electron mobility of the first output transistor M1r increases (the resistance value decreases), and the electrons of the second output transistor M2r increase. Mobility decreases (resistance increases). In this case, the voltage value of the first detection signal voltage Vs1 rises (see FIG. 10A). When the voltage value of the first detection signal voltage Vs1 rises, the voltage of the control gate CGr provided in the second output transistor M2r rises. Therefore, in the second output transistor M2r, the decrease in electron mobility due to distortion and the increase in the voltage of the control gate CGr cancel each other out, and the change in electron mobility of the second output transistor M2r due to distortion is less likely to occur. As a result, the sensitivity of the strain detection unit 21 may decrease.

On the other hand, when tensile distortion occurs in the direction in which the third storage element M3 and the second storage element M2 are lined up, the electron mobility of the third output transistor M3r decreases (the resistance value increases), and the fourth output transistor M4r The electron mobility of the transistor increases (the resistance value decreases). In this case, the voltage value of the second detection signal voltage Vs2 decreases (see FIG. 10B). In this modification, the control gate CGr of the second output transistor M2r is the third output transistor M3r and the fourth output transistor M3r via the control gate CGr of the second charge flow element M2w, the connection gate NGc of the second storage element M2, and the switch SW6. It is connected to the connection portion of the output transistor M4r. Therefore, the second detection signal voltage Vs2 is applied to the control gate CGr of the second output transistor M2r.

As a result, when tensile distortion occurs in the direction in which the third storage element M3 and the second storage element M2 are lined up, the second output transistor M2r not only reduces the electron mobility but also the voltage applied to the control gate CGr. descend. As described above, in this modification, the change in electron mobility and the voltage applied to the control gate CGr in the second output transistor M2r do not cancel each other out. As a result, in the strain sensor module according to the present modification, although the wiring structure in the strain detection unit 21 becomes slightly complicated, the distortion detection sensitivity in the strain detection unit 21 can be improved.

The offset correction method according to the present embodiment is the same as the offset correction method according to the first embodiment, except that the states of the switch SW6 and the switch SW14 in the third adjustment process and the seventh adjustment process are reversed. It can be executed by the process of. Specifically, in the third adjustment process, the switch SW6 is set to the connected state (short state), and the switch SW14 is set to the open state (open state). Further, in the seventh adjustment process, the switch SW6 is set to the open state (open state), and the switch SW14 is set to the connected state (short state). As a result, in the offset correction method according to the present embodiment, the connection state between the strain detection unit 21 and the switch group 17 in the third adjustment process and the seventh adjustment process becomes the first in the offset correction method according to the first embodiment. The state is similar to the connection state between the strain detection unit 11 and the switch group 17 in the adjustment process 3 and the 7th adjustment process. As a result, the offset correction method according to the present embodiment can be realized by the same effective method as the offset correction method according to the first embodiment.

As described above, the strain sensor module and the offset correction method according to the present embodiment have the same effects as the strain sensor module and the offset correction method according to the first embodiment.

(Modification example)
A strain sensor module according to a modified example of this embodiment will be described with reference to FIG. 37. In the distortion sensor module according to this modification, the first output transistor M1r and the third output transistor M3r are set to the depletion state in the offset correction operation mode, and the control gate CGr of the first output transistor M1r and the third output transistor M3r is set during operation. Is characterized in that it is connected to the reference potential terminal (ground terminal).

Although detailed description will be omitted, in this modification, the threshold voltage is set so that the first output transistor M1r and the third output transistor M3r are in the depletion state by the same method as in the first modification of the first embodiment. NS.

When the strain sensor module is operated according to this modification, the switch SW3 is set to the connected state and the switch SW7 is connected to the reference potential VSS side as shown in FIG. 37. As a result, the control gate CGr of the first output transistor M1r is connected to the reference potential VSS side. Similarly, the switch SW11 is set to the connected state, and the switch SW15 is connected to the reference potential VSS side. As a result, the control gate CGr of the third output transistor M3r is connected to the reference potential VSS side. As a result, the strain sensor module according to the present modification has the same effect as the strain sensor module according to the modification 1 of the first embodiment.

The offset correction method according to the first embodiment and each modification of the present invention and the second embodiment and modification can be embodied as a computer program. For example, the computer program constitutes a Wheatston bridge circuit, and the electron mobility changes according to the distortion of the object to be measured. The first output transistor M1r, the second output transistor M2r, the third output transistor M3r, and the fourth output transistor M4r. The computer functions as an offset correction unit 12 that corrects the offset of the detection signal output from the distortion detection unit 11 (or distortion detection unit 21) that outputs a detection signal according to the amount of distortion of the object to be measured, and distorts. The computer is made to function as a signal amplification unit 14 that amplifies the detection signal detected by the detection unit 11, and the computer is made to function as a signal processing unit 16 that processes the detection signal input from the signal amplification unit 14. The offset correction unit 12 can execute the offset correction method according to the embodiment and each modification, and the second embodiment and modification. Therefore, the first embodiment and each modification, and a part or all of the second embodiment and modification are incorporated into hardware or software (including firmware, resident software, microcode, state machine, gate array, etc.). be able to. Further, the first embodiment and each modification, and the second embodiment and modification can take the form of a computer program product on a computer-usable or computer-readable storage medium, which medium may contain. , Computer-enabled or computer-readable program code is incorporated. In the context of this specification, computer-enabled or computer-readable media records, stores, communicates, propagates, programs used by or with instruction execution systems, devices or devices. Alternatively, it can be any medium that can be transported.

The present invention is not limited to the above embodiment, and various modifications are possible.
In the first embodiment and the second embodiment, the offset correction unit has a distortion error detection unit, but the present invention is not limited to this. The strain sensor module may separately include an offset correction unit and a distortion false detection unit. In this case, an adder, a signal selection unit, and a differential amplification unit constituting the distortion detection unit may be provided separately from these components of the offset correction unit.

Further, the offset correction unit has a configuration in which the output terminal of the adder is directly connected to the inverting input terminal (-) of the amplifier of the differential amplifier unit, and the distortion error detection unit divides the output of the adder. The voltage dividing signal may have a configuration in which the voltage dividing signal is directly input to the inverting input terminal (−) of the amplifier of the differential amplification unit. Further, in this case, the mode selection unit may appropriately switch between the output of the amplifier of the offset correction unit and the output of the amplifier of the distortion detection unit to output to the signal processing unit. Further, the signal processing unit has an AD converter for the offset correction unit, an AD converter for the distortion error detection unit, and an AD converter for the signal amplification unit, and the distortion sensor module outputs the offset correction unit. And the output of the distortion detection unit may be configured to be input to the signal processing unit without switching.

In the first embodiment and each modification, the first storage element M1 to the fourth storage element M4 have the same shape, but the present invention is not limited to this. For example, the strain detection unit 11 includes the first storage element M1 and the fourth storage element M4 of the first example shown in FIG. 5 (a) and the second storage element M2 of the second example shown in FIG. 5 (b). And may have a third storage element M3. Further, the strain detection unit 11 includes the first storage element M1 and the fourth storage element M4 of the second example shown in FIG. 5 (b) and the second storage element M2 of the first example shown in FIG. 5 (a). And may have a third storage element M3. In any of these cases, the strain that can be detected by the strain detection unit 11 is the tensile strain in the crystal axis <100> direction and the crystal axis <010> direction of the semiconductor substrate 9 or the crystal axis <100> direction of the semiconductor substrate 9 and the strain. The compression strain is in the crystal axis <010> direction. Therefore, in the strain sensor module, a storage element group consisting of two storage elements having the same shape (for example, the first storage element M1 and the fourth storage element M4) and the storage element of the storage element group are A group of storage elements including two storage elements having different shapes and having the same shape as each other (for example, the second storage element M2 and the third storage element M3) are arranged in different crystal axis directions of the semiconductor substrate 9, respectively. Even if the configurations are arranged side by side, the same effect as that of the strain sensor module according to the first embodiment and each modification can be obtained.

The connection gate does not have to be formed in the same layer as the control gate of the output transistor as long as the control gate of the output transistor and the control gate of the charge distribution element can be electrically connected. Further, the sidewall may not be formed around the polysilicon film constituting the connection gate.

The charge holding regions constituting the connection gate are formed in the same layer if they are electrically connected to each of the charge holding region constituting the control gate of the output transistor and the charge holding region constituting the control gate of the charge distribution element. It does not have to be. Further, the charge holding region of the connection gate is insulated from components other than the charge holding region constituting the control gate of the output transistor and the charge holding region constituting the control gate of the charge distribution element to maintain an electrically floating state. If possible, it does not have to be surrounded by an insulator.

In the first embodiment and the second embodiment, the output voltage setting process (step S300) is always executed after the sensor output detection process (step S200). Not limited to. For example, the voltage obtained by subtracting the second detection signal voltage Vs2 from the first detection signal voltage Vs1 detected in the sensor output detection process (step S200) is a voltage within a predetermined range including 0V, and the first detection signal voltage. If the voltage obtained by adding Vs1 and the second detection signal voltage Vs2 is within a predetermined range including the voltage value of the comparison signal Sc (the voltage value of the power supply voltage VDD in each of the above embodiments), the output voltage setting process (step). It may be configured so that S300) is not executed.

1 Strain sensor module 9 Semiconductor substrate 11,21 Strain detection unit 12 Offset correction unit 13 Distortion error detection unit 14 Signal amplification unit 15 Mode selection unit 16 Signal processing unit 17 Switch group 61 Interlayer insulating film 62, 63, 64, 65 Plug 66 , 86 Polysilicon film 67,75,77,85,87 Side wall 70,80 Insulation 71,81 Charge retention region 72,82 Gate insulation film 73,83 Side wall oxide film 74,84 Upper insulation film 91,93,95 N-type region 92, 94, 96 N + region 97 Element separation region 121 Current mirror circuit 123 Adder 124 Signal selection unit 124a Switch 125 Differential amplification unit 125a Amplifier 141 Differential amplifier 161,162 AD converter 811 Charge flow region 821 Tunnel Insulation film 911 Thin part 912 Thick part 913 Connection part CGr, CGw Control gate D Drain FGr, FGw Floating gate IR Impure diffusion region M1 First storage element M1r First output transistor M1w First charge flow element M2 Second storage element M2r Second output transistor M2w Second charge flow element M3 Third storage element M3r Third output transistor M3w Third charge flow element M4 Fourth storage element M4r Fourth output transistor M4w Fourth charge flow element NGc, NGf Connection gate R1, R2 , R3, R4, R5, R6 Resistance element S Source SW1, SW2, SW3, S # 4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW12, SW13, SW14, SW15, SW16 Switch To1 First output Terminal To2 2nd output terminal

Claims (18)

A distortion detection unit that constitutes a Wheatstone bridge circuit and has four field effect transistors whose electron mobility changes according to the strain of the object to be measured, and outputs a detection signal according to the amount of distortion of the object to be measured.
An offset correction unit that corrects the offset of the detection signal output from the distortion detection unit, and an offset correction unit.
A signal amplification unit that amplifies the detection signal output from the distortion detection unit, and
A distortion sensor module including a signal processing unit that processes the detection signal output from the signal amplification unit. Each of the four field effect transistors
The first insulating film placed in contact with the substrate and
A first floating gate arranged in contact with the first insulating film in an electrically floating state,
The strain sensor module according to claim 1, further comprising a first control gate disposed above the first floating gate so as to be insulated from the first floating gate. A second insulating film having at least a part of a charge flow region formed in a film thickness that allows charge to flow when a predetermined voltage is applied and arranged in contact with the substrate.
A second floating gate arranged in contact with the second insulating film in an electrically floating state and connected to the first floating gate,
A charge distribution device having a second control gate disposed above the second floating gate, insulated from the second floating gate, and connected to the first control gate and arranged above the second floating gate. With
The strain sensor module according to claim 2, wherein the charge flow element is connected to each of the four field effect transistors in a one-to-one relationship. The substrate has a thin portion formed to a predetermined thickness and a thick portion arranged adjacent to the thin portion and formed thicker than the thin portion.
The field effect transistor is formed in the thin portion and is formed on the thin portion.
The strain sensor module according to claim 3, wherein the charge flow region is formed above the thick portion. The strain sensor module according to claim 4, wherein at least a part of the charge distribution element is formed in the thick portion. The strain sensor module according to any one of claims 3 to 5, wherein the charge distribution element is composed of a non-volatile storage element. The strain sensor module according to any one of claims 1 to 6, wherein each of the four field effect transistors is composed of a non-volatile memory element. The strain sensor module according to any one of claims 1 to 7, wherein the offset correction unit includes a distortion error detection unit that detects whether or not the strain detection unit normally detects the strain. The distortion sensor module according to claim 8, further comprising a mode selection unit for selecting one of the offset correction operation mode in the offset correction unit and the distortion false detection operation mode by the distortion error detection unit. The offset correction unit
A current source that generates a current input to the distortion detection unit when correcting the offset of the detection signal, and a current source.
An adder that adds the first detection signal and the second detection signal output from the distortion detection unit as the detection signal, and
A signal selection unit that selects either the addition output signal output from the adder or the voltage division signal obtained by dividing the voltage of the addition output signal based on the control signal output from the mode selection unit. When,
The distortion sensor module according to claim 9, further comprising a differential amplification unit that calculates a difference between a selection output signal output from the signal selection unit and a comparison signal output from the mode selection unit. The distortion sensor module according to claim 10, wherein the distortion detection unit includes the adder, the signal selection unit, and the differential amplification unit. 10. The aspect of claim 10 or 11, wherein the mode selection unit selects the additional output signal in the offset correction operation mode, and causes the signal selection unit to select the partial pressure signal in the false detection operation mode. Distortion sensor module. When the false detection operation mode is selected by the mode selection unit, the signal processing unit may perform the signal processing unit.
When the differential amplification unit outputs a signal having a predetermined voltage, the distortion detection unit outputs a signal indicating that the distortion is normally detected.
Claims 10 to 12 output a signal indicating that the distortion detection unit does not normally detect the distortion when the differential amplification unit outputs a signal having a voltage deviating from a predetermined voltage by a threshold value or more. The distortion sensor module according to any one of the items up to. This is an offset correction method for correcting the offset of the detection signal of the distortion detection unit that outputs a detection signal according to the amount of distortion of the object to be measured.
The threshold voltage of two field-effect transistors arranged on the power supply side of the four field-effect transistors whose electron mobility changes according to the strain of the object to be measured, which constitutes the Wheatston bridge circuit, is adjusted. The two field-effect transistors are set in a reference state in which no current flows through each of the remaining field-effect transistors arranged on the reference potential side of the four field-effect transistors.
The threshold voltage of one of the residual field effect transistors is controlled to set the one field effect transistor in a predetermined state.
The threshold voltage of one of the two field-effect transistors is controlled to set the one of the field-effect transistors in a predetermined state.
The threshold voltage of the other of the residual field-effect transistors is controlled to set the other field-effect transistor in a predetermined state.
An offset correction method in which the threshold voltage of the other of the two field-effect transistors is controlled to set the other field-effect transistor in a predetermined state. The offset correction method according to claim 14, wherein the amount of electric charge held in the floating gates provided in each of the four field effect transistors is adjusted to control the threshold voltage of the four field effect transistors. Of the remaining field-effect transistors, in a state where a predetermined amount of electric charge is held in the floating gate provided in each of the two field-effect transistors and the two field-effect transistors are set to the reference state. The adjustment current is input to one of the remaining field effect transistors without inputting the adjustment current of a predetermined current value to the other, and the current is stored in the floating gate provided in the one field effect transistor. By controlling the amount of electric charge to be applied, one of the field effect transistors is set to the predetermined state.
The first detection signal as the detection signal output from one of the two field-effect transistors and one of the residual field-effect transistors, and the other of the two field-effect transistors and the residual electric field. The adjusting current is applied to the two field effect transistors so that the voltage of the added signal output from the other connection of the effect transistors and added to the second detection signal as the detection signal becomes a predetermined voltage value. The claim that the amount of charge accumulated in the floating gate provided in one of the two field effect transistors is controlled to set the one field effect transistor in the predetermined state without inputting. The offset correction method according to 15. Of the remaining field-effect transistors, in a state where a predetermined amount of charge is held in the floating gate provided in each of the two field-effect transistors and the two field-effect transistors are set to the reference state. The adjustment current is input to the other of the residual field effect transistors without inputting the adjustment current to one, and the amount of charge accumulated in the floating gate provided in the other field effect transistor is controlled. Then, the other field effect transistor is set to the predetermined state, and the other field effect transistor is set to the predetermined state.
Accumulates in the floating gate provided on the other side of the two field effect transistors in a state where the adjustment current is not input to the residual field effect transistor so that the voltage of the addition signal becomes a predetermined voltage. The offset correction method according to claim 16, wherein the amount of electric charge is controlled to set the other field effect transistor in a predetermined state. Computer,
It has four field effect transistors that form a Wheatstone bridge circuit and whose electron mobility changes according to the strain of the object to be measured, and outputs a detection signal according to the amount of distortion of the object to be measured. An offset correction unit that corrects the offset of the detected signal.
It functions as a signal amplification unit that amplifies the detection signal detected by the distortion detection unit and a signal processing unit that processes the detection signal input from the signal amplification unit.
A program for causing the offset correction unit to execute the offset correction method according to any one of claims 14 to 17.

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