JP2021145505A - Power supply control circuit and low power device - Google Patents

Abstract

To enable stable supplying of a required operation voltage to a load circuit for a long period even if a power generation amount of a power generation part is weak.SOLUTION: In a power supply control circuit 10, a switching control circuit 24 turns on two switches 18 and 20 when intra-terminal voltages VC of a capacitor 16 becomes a threshold value or larger for starting a power supply during charging, and starts a discharge to the capacitor 16 (the supplying the power to a load circuit 14). Then, when the intra-terminal voltages become the threshold value or less for stopping a power supply during a power supply, the switching control circuit turns off the two switches, and stops the discharge (the power supply) of the capacitor and switches it to the charging. A non-liner bypass circuit 22 includes an intermediate node N22, one or a plurality of n diodes D1....Dn, and a resistor R22, and connects the node to a voltage input terminal 24IN of the switching control circuit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a power supply control circuit that controls power supply from a power generation unit to a load circuit, and particularly relates to a power supply control circuit for a low power device and a low power device.

In recent years, energy harvesting, which converts energy around us such as light, heat, vibration, and radio waves into electric power, has attracted attention. Devices that use energy harvesting generally have a weak and unstable electromotive force in the power generation section (harvester), so connect a capacitor in parallel with the power generation section and temporarily store the power output from the power generation section in the capacitor. Is supplied to the load circuit at the required voltage.

Such low power supply control circuit used in the device is basically two threshold V _TH for the inter-terminal voltage V _C of the _capacitor, to set the V _TL, the higher the inter-terminal voltage V _C threshold V _TH above comes to begin discharging the capacitor (power supply to the load circuit) switches the terminal voltage V _C is more equal to or less than the threshold V _TL of lower stops the discharge of the capacitor to charge the It has become like.

The repeated such charge and discharge, it is necessary to monitor the timing to be less than the threshold V _TL of the terminal voltage V _C of the capacitor is higher towards the timing and lower reaches or exceeds the threshold value V _TH of .. For this purpose, the conventional power supply control circuit uses a hysteresis comparator (for example, Patent Document 1).

In this case, in the hysteresis comparator, the voltage dividing voltage is input to one input terminal (for example, the positive side input terminal) from the resistance voltage dividing circuit connected in parallel with the capacitor, and the other input terminal (negative side input terminal). _{The comparison reference voltage V REF} is input from the reference voltage generation circuit to. In such a hysteresis comparator, assuming that the hysteresis width is 2α, two threshold values represented by _{V REF} + α and V _{REF −α are set, respectively.} Therefore, the terminal voltage _{V C} of the capacitor is _{V TH,} the threshold value _{V REF} + alpha from resistor divider when the _{V TL,} equal divided voltage to _{V REF-.alpha.} to be obtained, respectively. Then, hysteresis comparator outputs a binary signal of the High level when the voltage V _C across the capacitor terminals reaches or exceeds V _TH, and outputs a binary signal of Low level when the voltage V _C across the capacitor terminals is below V _TL .. By using this binary signal to control on / off of a switch connected in series between the capacitor and the load circuit, it is possible to appropriately switch the discharge and charge of the capacitor.

Japanese Unexamined Patent Publication No. 2010-207062

As mentioned above, energy harvesting has attracted a lot of attention in recent years because it is the core technology of IoT (Internet of Things). In the field of IoT, there is a demand for low-power devices that do not require batteries and that can cover their own power consumption by energy harvesting.

The power supply control circuit used as a power management circuit for such a low-power device that does not require a battery must be able to efficiently and stably supply the power generation unit to the load circuit for a long period of time even if the amount of power generated by the power generation unit is weak. .. However, the conventional power supply control circuit as described above consumes a large amount of electric power by itself in the gain circuit in the hysteresis comparator, the peripheral reference voltage generation circuit, the resistance voltage division circuit, etc., so that it is weakly generated from the environmental energy. It is not possible to stably supply a large amount of power to the load circuit at the required operating voltage for a long period of time, and it is not suitable for low-power devices that do not use batteries.

The present invention solves the above-mentioned problems of the prior art, and is a power supply control circuit capable of stably supplying a required operating voltage to a load circuit for a long time even if the amount of power generated by the power generation unit is weak. To provide a low power device having.

The power supply control circuit according to the first aspect of the present invention is a power supply control circuit that controls intermittent power supply from a capacitor connected in parallel to a DC power generation unit to a load circuit, and is a first terminal of the capacitor. It is connected between the first switch and the corresponding input terminal of the load circuit, and the first terminal and the second terminal of the capacitor, has a diode in the middle, and has the first terminal. There is one or more diodes between the terminal and the node, and when the voltage between the terminals of the capacitor becomes equal to or higher than the first threshold value, the diode conducts in the forward direction and the voltage of the node becomes A non-linear bypass circuit that is lower than the first threshold voltage and equal to or higher than the second threshold voltage, is connected to the node of the non-linear bypass circuit, and is connected to the input side terminal or output side of the first switch. The capacitor has a voltage input terminal connected to the terminal via a second switch, and a control output terminal for outputting a control signal for controlling on / off of the first and second switches. The switch control circuit includes a switch control circuit whose operating voltage is a voltage between terminals, and the switch control circuit has a voltage between terminals of the capacitor as the first threshold value when the first and second switches are off. After that, the first and second switches are turned on, and the voltage between the terminals of the capacitor is lower than the first threshold value under the state where the first and second switches are on. After the voltage falls below the threshold value, the first and second switches are turned off.

In the power supply control circuit having the above configuration, while the first and second switches are off by the control of the switch control circuit, the output current of the power generation unit flows into the capacitor, and as the charge amount of the capacitor increases, the capacitor The voltage between terminals rises. At this time, the voltage between the terminals of the capacitor is applied to the nonlinear bypass circuit, and as the voltage between the terminals rises, the voltage applied to the diode also increases. However, due to the non-linear characteristics of the diode, the diode remains substantially non-conducting until the voltage between the terminals of the capacitor reaches the first threshold value, and the voltage of the node remains near the ground potential. At this time, since the second switch is in the off state, the node voltage from the nonlinear bypass circuit is input to the voltage input terminal of the switch control circuit.

Then, when the voltage between the terminals of the capacitor becomes equal to or higher than the first threshold value, in the nonlinear bypass circuit, the diode starts substantially conducting in the forward direction, and the node voltage becomes equal to or higher than the second threshold value. Then, the switch control circuit turns on the first and second switches in response to the voltage input to the voltage input terminal, that is, the node voltage, which exceeds the second threshold value.

When the first switch is turned on, the capacitor is connected to the load circuit via this switch, and discharge (power supply) from the capacitor to the load circuit is started. On the other hand, when the second switch is turned on, the input side terminal or the output side terminal of the first switch is connected to the voltage input terminal of the switch control circuit via the second switch. As a result, the voltage input to the voltage input terminal is switched from the node voltage to the voltage between the terminals of the capacitor. In the nonlinear bypass circuit, the conduction of the diode is stopped and the node voltage becomes the voltage between the terminals of the capacitor.

While the capacitor is discharging (powering) as described above, the voltage between the capacitor terminals gradually decreases and eventually becomes equal to or lower than the third threshold value. Then, the switch control circuit turns off the first and second switches in response to the voltage input to the voltage input terminal, that is, the voltage between the capacitor terminals, which has broken the third threshold value. do.

When the first switch is turned off, this switch separates the capacitor from the load circuit, stops discharging, and allows the output current of the power generator to flow into the capacitor (charging resumes). On the other hand, when the second switch is turned off, the voltage input terminal of the switch control circuit becomes the input side terminal (that is, the first terminal of the capacitor) or the output side terminal (that is, the load circuit correspondence) of the first switch by this switch. Separated from the input terminal). As a result, the voltage input to the voltage input terminal of the switch control circuit is switched from the voltage between the terminals of the capacitor to the node voltage. After that, the same charge / discharge operation as described above is repeated.

The power supply control circuit according to the second aspect of the present invention is a power supply control circuit that controls intermittent power supply from the main capacitor connected in parallel to the DC power generation unit to the load circuit, and is the first of the main capacitors. A first switch connected between the terminal of the load circuit and the corresponding input terminal of the load circuit, an intermediate node, and the first terminal of the first capacitor and the node. It has one or more diodes and a bypass capacitor connected between the node and the output side terminal of the first switch, and the voltage between the terminals of the main capacitor is the first threshold. When the value is equal to or higher than the value, the diode is conducted in the forward direction, and the voltage of the node is connected to the non-linear bypass circuit in which the voltage of the node is lower than the first threshold and is equal to or higher than the second threshold value and the node of the non-linear bypass circuit. At the same time, the on / off of the voltage input terminal connected to the input side terminal or the output side terminal of the first switch via the second switch and the first and second switches is controlled. It has a control output terminal for outputting a control signal for the purpose, and has a switch control circuit having a voltage between terminals of the main capacitor as an operating voltage. The first and second switches are turned on after the voltage between the terminals of the main capacitor becomes equal to or higher than the first threshold value under the off state, and the first and second switches are under the on state. The first and second switches are turned off after the voltage between the terminals of the main capacitor becomes equal to or lower than the third threshold value, which is lower than the first threshold value.

In the power supply control circuit having the above configuration, the same operation as that of the power supply control circuit in the first aspect is performed with respect to charge / discharge control. Further, in this power supply control circuit, a bypass capacitor is provided in series with the diode in the nonlinear bypass circuit via an intermediate node. The current flowing through the nonlinear bypass circuit during charging of the main capacitor is converted into electrostatic energy by the bypass capacitor. Then, when the voltage between the terminals of the main capacitor becomes equal to or higher than the first threshold value and the first and second switches are turned on, the main capacitor is discharged to the load circuit side via the first switch at the same time. , The bypass capacitor discharges to the main capacitor side via the second switch. The discharge current from the bypass capacitor is once absorbed by the main capacitor, or merges with the discharge current from the main capacitor, and is supplied to the load circuit side via the first switch.

The power supply control circuit according to the third aspect of the present invention is a power supply control circuit that controls intermittent power supply from a capacitor connected in parallel to a DC power generation unit to a load circuit, and is an intermediate node and the capacitor. It has at least one diode connected between the first terminal and the node, and when the voltage between the terminals of the capacitor becomes equal to or higher than the first threshold value, the diode conducts in the forward direction. It has a non-linear bypass circuit in which the voltage of the node becomes equal to or higher than the second threshold value lower than the first threshold value, the voltage between the terminals of the capacitor is used as the operating voltage, and the second voltage of the node is used. A third voltage is started to supply power to the load circuit in response to a change in the logic level based on the threshold value of, and is lower than the first threshold value of the voltage between the terminals of the capacitor or the input voltage of the load circuit. The power supply to the load circuit is stopped according to the change in the logic level with reference to the threshold value of.

In the power supply control circuit having the above configuration, the voltage between the terminals of the capacitor is applied to the non-linear bypass circuit during charging of the capacitor, but due to the non-linear characteristics of the diode, the voltage between the terminals of the capacitor reaches the first threshold value. Because the diode remains substantially non-conducting, the current flowing through the non-linear bypass circuit is negligible and the capacitor is charged efficiently. Then, when the voltage between the terminals of the capacitor becomes equal to or higher than the first threshold value, the logical level of the node voltage based on the second threshold value changes, and in response to this, power is supplied to the load circuit ( Discharge of the capacitor) is started.

During power supply (discharge) to the load circuit, the voltage between the terminals of the capacitor and the input voltage of the load circuit gradually decrease, and when the voltage falls below the third threshold value, the logic level changes. Stop the power supply (discharge) to the circuit. As a result, charging of the capacitor is restarted. After that, the same charge / discharge operation as described above is repeated.

In the low power device of the present invention, a power generation unit that converts a given environmental energy into electric power and outputs a direct current, a capacitor connected in parallel to the output terminal of the power generation unit, and a constant operation are intermittently performed. It has a load circuit capable of performing the above and a power supply control circuit of the present invention that controls intermittent power supply from the capacitor to the load circuit.

With the above configuration, the power supply control circuit of the present invention can stably supply the required operating voltage to the load circuit for a long time even if the amount of power generated by the power generation unit is weak, and in particular, the IoT device. It can be suitably adapted to low power devices operating in energy harvesting such as.
Further, the low power device of the present invention can operate stably and correctly for a long time even if the amount of power generated by the power generation unit is weak due to the above configuration.

It is a circuit diagram which shows the circuit structure of the power-source control circuit in the 1st Embodiment of this invention applied to the low-power device which uses energy harvesting. It is a block diagram which shows an example of the load circuit in the low power device of FIG. It is a waveform diagram which shows the waveform of each part for demonstrating the operation of the power-source control circuit in 1st Embodiment. It is a waveform diagram which shows the waveform of each part for demonstrating the operation (the operation when the amount of power generation is lower than the case of FIG. 3) of the power supply control circuit in 1st Embodiment. It is a circuit diagram which shows the structure of the power supply control circuit in 2nd Embodiment. It is a circuit diagram which shows the structure of the power supply control circuit in 3rd Embodiment. It is a circuit diagram which shows the structure of one modification of Embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[Embodiment 1]

FIG. 1 shows the circuit configuration of the power supply control circuit 10 (1) according to the first embodiment of the present invention. The power supply control circuit 10 (1) is configured as a power management circuit that controls power supply from the power generation unit 12 to the load circuit 14 in a low power device such as an IoT device that operates by utilizing energy harvesting.

Power generation unit 12, a given environment energy such as light, heat, vibration, photovoltaic radio waves or the like, the thermoelectric generator, vibration power, consists harvester for converting the power by an electromagnetic wave generator or the like, an output terminal 12 _+, 12 _- the DC It is configured to output the current I _{H of. Normally, the output terminal 12 −} on the negative electrode side of the power generation unit 12 _{and the input terminal 14 −} on the negative electrode side of the load circuit 14 are grounded.

Capacitors 16 having a capacitance of, for example, 1 μF or more are connected in parallel to the output terminals 12 ₊ and 12 _{− of the power generation unit 12.} The capacitor 16 is discharged a current I _H that is output from the power generating section 12 temporarily from stored instead of the electrostatic energy, the load circuit 14 by the power supply control of the electrostatic energy power supply control circuit 10 (1) Or it is designed to discharge. Seen from the load circuit 14, the capacitor 16 is a direct power supply source.

The power supply control circuit 10 (1) has two switches 18 and 20, a non-linear bypass circuit 22 and a switch control circuit 24.

The first switch 18 is connected between one terminal corresponding input terminal (the positive terminal in the example) 16 ₊ a load circuit 14 (the positive-side input terminal) 14 ₊ of the capacitor 16. Switch 18 is a PMOS transistor in this embodiment, the input-side terminal (source) connected to the positive terminal 16 ₊ of the capacitor 16, the positive electrode side input terminal of the output side of the terminal (drain) of the load circuit 14 It is connected to the 14 _+, a control terminal (gate) is connected to the control output terminal _{24 OUT} of the switch control circuit 24. _{The gate voltage threshold value or the on / off threshold value VT18} that influences the on / off of the switch (PM2 transistor) 18 is lower than _{the inverting threshold value VT30} described later in the switch control circuit 24 _(VT18 < It is set to _VT30).

The switch 18 functions as a charge / discharge changeover switch under the control of the switch control circuit 24. More specifically, when the switch 18 is turned on, the capacitor 16 via the switch 18 to discharge to the load circuit 14 side, the terminal voltage V _C of the capacitor 16 is supplied to the load circuit 14 as the operating voltage V _W NS. When the switch 18 is off, the capacitor 16 is separated or cut off from the load circuit 14 by the switch 18 and charged by _{the output current I H of the power generation unit 12.}

The second switch 20 is connected between the voltage input terminal 24 _IN of the input side terminal and the switch control circuit 24 of the positive terminal 16 ₊ or switch 18 of the capacitor 16. The switch 20 in this embodiment is composed of a epitaxial transistor, its input side terminal (source) is _{connected to the positive side terminal 16 + of the} capacitor 16 or the input side terminal of the switch 18, and its output side terminal (drain) is connected. It is connected to the voltage input terminal 24 _IN of the switch control circuit 24, and its control terminal (gate) is connected to _{the control output terminal 24 OUT of the switch control circuit 24. The on / off threshold value VT20 of the} switch (PM2 transistor) 20 is also set to a value lower than _{the inverting threshold value VT30} of the switch control circuit 24 _(VT20 < _VT30).

The switch 20 functions as an input voltage changeover switch for the switch control circuit 24 under the control of the switch control circuit 24. More specifically, the switch 20 is in when it is turned on, the terminal voltage V _C of the capacitor 16 is input to the voltage input terminal 24 _IN of the switch control circuit 24 via the switch 20. When the switch 20 is off, the positive electrode side terminal 16 ₊ of the capacitor 16 is separated or cut off from the _{voltage input terminal 24 IN} by the switch 20, and the voltage _VA input to the _{voltage input terminal 24 IN} is a non-linear bypass circuit 22. It switches to the node voltage _VN22 which will be described later.

The non-linear bypass circuit 22 is connected between _{both terminals 16 +} and 16 _{− of the capacitor 16.} Nonlinear bypass circuit 22, an intermediate in a node _{N 22,} 1 one or more toward the anode of each positive terminal 16 ₊ between the positive terminal 16 ₊ and the node _{N 22} of the capacitor 16 (n) The diodes D ₁ ... D _n are connected in series, and one resistor R ₂₂ is connected _{between the node N 22} and the negative electrode side terminal 16 _{− of the capacitor 16.} The threshold voltage V _f of each diode D ₁ ... D _n is preferably selected to have the same value. A high resistance on the order of MΩ is selected for the resistor R _22.

The diode is a non-linear two-terminal element, and when the applied voltage is _{lower than the constant threshold voltage Vf} , it remains substantially non-conducting, and the flowing current is very small, but the applied voltage is the threshold voltage. When _{it exceeds V f} , it becomes conductive.

In this nonlinear bypass circuit 22, the _{current flowing through the resistor R 22} (hereinafter referred to as “bypass current”) I ₂₂ is the pole _{while the diode D 1} ... D _n is kept in a substantially non-conducting state. It is small, and _{the voltage of the node N 22} , that is, the node voltage _{VN 22} , remains near the ground potential. However, if the inter-terminal voltage V _C charge amount increases the capacitor 16 increases, the applied voltage of the diode D ₁ ‥‥ D _n also increases. The first threshold voltage between terminals V _C of the capacitor 16 is given (hereinafter referred to as "feed start threshold value".) Becomes equal to or larger than V _TH, diodes D ₁ ‥‥ D _n becomes conductive _Therefore , the node voltage VN22 becomes equal to or higher than a predetermined second threshold value (hereinafter, referred to as “node voltage threshold value”) _VTN. This node voltage threshold value V _TN depends on the power supply start threshold value V _TH , the threshold voltage V _{f of the} diode D ₁ ... D _n , and the number (n), and V _TN = V _TH −n ·. It is given by V _f.

The switch control circuit 24 includes an inverter 30 to the operating voltage a voltage V _C across the terminals of the capacitor 16. The inverter 30 is preferably a CMOS inverter and is composed of a epitaxial transistor 26 and an NMOS transistor 28. More specifically, PMOS transistor 26 has its source connected the positive pole side terminal 16 ₊ of the capacitor 16, a drain connected to the control output terminal _{24 OUT,} its gate connected to the voltage input terminal _{24 IN.} On the other hand, the source of the NMOS transistor 28 is _{connected to the negative electrode side terminal 16 −} of the capacitor 16, the drain thereof is connected to the control output terminal 24 _OUT , and the gate thereof is connected to the voltage input terminal 24 _IN . _{The threshold values VT26} and VT28 of both MOS transistors 26 and ₂₈ are set to the same value, and the inverting threshold value _VT30 of _{the CMOS inverter 30 is VT30} = _VT26 = _VT28 .

In the power supply control circuit 10 (1), as will be described later, from the inter-terminal voltage V _C of the capacitor 16 becomes higher feed start threshold value V _TH during charging to discharging (load circuit 14 of the capacitor 16 starts feeding), the inter-terminal voltage V _C in the feed is predetermined third threshold value (hereinafter, referred to as "power supply stop threshold value".) V _TL falls below the discharge of the capacitor 16 (the feed ) Is stopped and switched to charging, and the charging / discharging operation is repeated. In charge and discharge operations of the repetition, the load circuit 14 only while the capacitor 16 is discharged to the load circuit 14 side through the switch 18, the terminal voltage V _C of the capacitor 16 is input as the operation voltage V _W NS.

The load circuit 14 is responsible for the main function of the low power device, and performs the required intermittent operation under the _{operating voltage V W that is intermittently input as described above.} For example, when the low power device is a sensor module, the load circuit 14 has a transmission circuit 34 to which the sensor element 32 is connected, as shown in FIG. _{This transmission circuit 34 includes an oscillating circuit, and oscillates the oscillating circuit only when the operating voltage V W} is supplied from the capacitor 16 via the power supply control circuit 10 (1), and is required through the output transistor 36 and the antenna 38. Data (sensor information) is transmitted and output wirelessly. When the operating voltage V _W is not input, the standby mode is set and the transmission circuit 34 does not operate.

In this embodiment, it is set to the switch control circuit 24 inverting the threshold _{V T30} is equal to the power supply stop threshold value _{V TL} of (CMOS inverter _{30) (V T30 = V TL} ). On the other hand, between the feeding start threshold value _{V TH} and node voltage threshold _{V TN,} a relationship of _{V TN = V TH -n · V} f as described above. Accordingly, as a preferred embodiment, between the feeding start threshold value _{V TH} and the feed stop threshold value _{V TL} and inversion threshold _{V T30,} the former _{(V TH)} of the latter _{(V TL, V T30} ) Higher than n · V _f , that is, V _TH ≧ V _TL + n · V _f , V _TH ≧ V _T30 + n · V _f , or V _TL ≤ V _{TH −} n · V _f , V _T30 ≤ V _TH − The relationship of n · V _{f is set.} In that case, the node voltage threshold value V _TN becomes a value equal to or higher than the power supply stop threshold value V _TL and the inversion threshold value _{VT 30 (V TN} ≧ V _TL , V _TN ≧ V _{30 L} ).

Next, the operation of the power supply control circuit 10 (1) in this embodiment will be described with reference to the waveform diagrams of FIGS. 3 and 4.

In the following description, the node voltage threshold value V _TN , the power supply stop threshold value V _TL , and the inversion threshold value _{VT 30} all have the same value, that is, V _TN = V _TL = _{VT 30.} (However, it is assumed that the relationship of _{(V TN} = V _TH −n · V _{f) is set.} Further, the waveform of each part shown in FIGS. 3 and 4, until the switching-on of the switches 18, 20 since the terminal voltage V _C of the capacitor 16 is raised to the power feeding start threshold value V _TH is completed delay time, and it ignores the delay time from when the terminal voltage V _C of the capacitor 16 drops to the threshold V _TL feeding stopped until switching off both switches 18 and 20 is completed.

In FIG. 3, when the energy of the environmental energy used by the low-power device as a power source is constant, the direct current I _H generated by the power generation unit 12 is output with a certain amount of current.

Capacitor 16 is charged by the output current I _H of the power generation section 12, the terminal voltage V _C of the capacitor 16 rises as the charging amount increases. When the terminal voltage _{V C} of the capacitor 16 exceeds a minimum value, that the feed stop threshold _{V TL} required for operation of the switch control circuit 24 (CMOS inverter 30) and the load circuit 14, the power supply control circuit 10 (1 ) Is enabled, and both switches (PM2 transistors) 18 and 20 are initialized to the off state, respectively. _{At this time, the node voltage VN22} from the nonlinear bypass circuit 22 is _{input to the voltage input terminal 24 IN} of the switch control circuit 24 (CMOS inverter 30) at a substantially ground potential. The switch control circuit 24 within the (CMOS inverter 30), PMOS transistor 26 is turned on, an NMOS transistor 28 is turned off, the control output terminal _{24 OUT} of the voltage (the control output signal) _{V B} is between the capacitor terminal voltage _{V C} (≧ _VTL ), which is a high level for both switches 18 and 20.

Terminal voltage V _C of the capacitor 16 is also applied to the non-linear bypass circuit 22, the applied voltage of the diode D ₁ ‥‥ D _n as the inter-terminal voltage V _C is increased even higher. However, due to the nonlinear characteristic of a diode as described above, until the terminal voltage V _C of the capacitor 16 reaches the feeding start threshold value V _TH, diodes D ₁ ‥‥ D _n is the state of substantially non-conductive Keep, the bypass current I ₂₂ is extremely small. In this way, the capacitor 16 efficiently draws in _{the output current I H of the power generation unit 12.}

When the terminal voltage V _C of the capacitor 16 rises to the power supply start threshold value V _TH, the non-linear bypass circuit within 22, the diode D ₁ ‥‥ D _n starts to substantial conduction, the node voltage V _N22 becomes the node voltage threshold value V _TN (V _TN = V _{TH −} n · V _f ), and a substantial bypass current I ₂₂ flows. Thus, the inversion threshold of the inter-terminal voltage _{V C} of the capacitor 16 becomes equal to or higher than the feed start threshold value _{V TH,} the node voltage _{V N22} is the node voltage threshold _{V TN} or more words the switch control circuit 24 (CMOS inverter 30) The value _{becomes VT30} or more.

_{At this time, the voltage VA} input to _{the voltage input terminal 24 IN} of the switch control circuit 24 (CMOS inverter 30) is the node voltage _VN22 , and this node voltage _VN22 is the node voltage threshold value V as described above. _When it becomes TN or more, that is, the inversion threshold voltage _VT30 or more, the logic level _{of the output (control signal) V B} of the switch control circuit 24 (CMOS inverter 30) is inverted. That is, in the switch control circuit 24 (CMOS inverter 30), the epitaxial transistor 26 changes from the previous on state to the off state, and at the same time, the NMOS transistor 28 changes from the previous off state to the on state, and the output (control signal). ) V _B changes from the voltage between the capacitor terminals _VC (High level) to the ground potential (Low level).

_{When the control signal V B} output from the switch control circuit 24 changes from the voltage between the capacitor terminals _VC (High level) to the ground potential (Low level) in this way, both switches (PMPI transistors) that receive it at the control terminals (gates). 18, 20 are turned on.

When the switch 18 is turned on, the discharge (power supply) from the capacitor 16 to the load circuit 14 is started through the switch 18. Here, the voltage drop of the switch 18 is negligibly small, the inter-terminal voltage V _C of the capacitor 16 is inputted to the load circuit 14 as a substantially intact operating voltage V _W. In the load circuit 14 _{, each part starts operation under the input operating voltage V W} , and the transmission circuit 34 oscillates the internal oscillation circuit to transmit and output sensor information.

On the other hand, when the switch 20 is turned on, ₊ positive terminal of the capacitor 16 16 leading to the node _{N 22} of the voltage input terminal _{24 IN} and the non-linear bypass circuit 22 of the switch control circuit 24 via the switch 20 (CMOS inverter 30). Then, the switch control circuit 24 (CMOS inverter 30), the input voltage _{V A} becomes sufficiently higher than the inversion threshold _{V T30 (V A = V C} ), the on state of the OFF state and the NMOS transistor 28 of the PMOS transistor 26 Is established, and the voltage (control signal) V _{B of} the control output terminal 24 _OUT is maintained at the ground potential (Low level). In this way, the on state of both switches 18 and 20 is maintained.

In the nonlinear bypass circuit 22, the conduction of the diode _{D 1} ‥‥ _{D n} gone potential difference between the positive terminal 16 ₊ and the node _{N N22} of capacitor 16 is stopped. Although bypass current _{I 22} of the resistor _{R 22} becomes a current corresponding to the positive terminal 16 ₊ of the capacitor _{16 (I 22 = V C /} R 22), resistor _{R 22} is the resistance value is far from it to the capacitor 16 Since it is connected in parallel with the resistance in the low load circuit 14, most of the discharge current of the capacitor 16 flows to the load circuit 14 side.

While the capacitor 16 is discharging, the capacitance and the load voltage across the capacitor terminals at a constant time constant corresponding to the resistance of the circuit 14 V _C to the operating voltage V _W of the capacitor 16 is reduced. Thus, a predetermined time after the start of the capacitor 16 is discharged, the voltage V _C to the operating voltage V _W between the capacitor terminals decreases to power supply stop threshold value V _TL.

At this time, the switch control circuit 24 (CMOS inverter 30), the voltage _{V A} which is input to the input terminal _{24 IN} is the inter-terminal voltage _{V C} of the capacitor 16, the input voltage _{V A} is the feed stop threshold value V _{When the} voltage is TL or less, that is, the inverting threshold voltage is _VT30 or less, the NMOS transistor 28 is turned off at the same time as the polyclonal transistor 26 is turned on, and the control output terminal 24 _OUT is the positive terminal of the capacitor 16 via the ON state epitaxial transistor 26. 16 ₊ lead. Thus, it changes to the output (control signal) _{V B} is the ground potential so far between (Low level) from the capacitor terminal voltage _{V C} (≒ _{V TL).}

The output (control signal) V _B of the switch control circuit 24 is applied to the gates of both switches (PM2 transistors) 18 and 20. Here, the threshold value _{V T18, V T20} of both switches (PMOS transistors) 18 and 20, is set lower than the power supply stop threshold value _V TL0 _{(= V T30)} value. _{That is, the power supply stop threshold value VTL} is at the High level for both switches (PM2 transistors) 18 and 20. Therefore, when the control signal _{V B} is changed from the ground potential (Low level) between the capacitor terminal voltage _{V C} (≒ _{V TL),} both switches (PMOS transistors) 18 and 20 are turned off.

When the switch 18 is turned off, the capacitor 16 is separated from the load circuit 14 and also from the voltage input terminal 24 _{IN of} the switch control circuit 24 (CMOS inverter 30) and thus from _{the resistor R 22} of the nonlinear bypass circuit 22. The current I _H from 12 is drawn in (shifts to the charging mode). Thus, the voltage V _C across the terminals of the capacitor 16 starts to rise bottomed at the feed stop threshold V _TL. In the load circuit 14, _{the input of the operating voltage V W} is cut off, and the transmission circuit 34 (FIG. 2) stops the oscillation operation and the data transmission operation (shifts to the standby mode).

On the other hand, when the switch 20 is turned off, the _{voltage VA} input to _{the voltage input terminal 24 IN} of the switch control circuit 24 (CMOS inverter 30) is switched to _{the node voltage VN} 22 of the nonlinear bypass circuit 22 again. At this time, in the nonlinear bypass circuit 22, the diodes D ₁ ... D _n are substantially non-conducting, and the node voltage _{VN 22} remains near the ground potential. In this way, in the switch control circuit 24 (CMOS inverter 30), the input voltage _{VA is switched to the node voltage VN22 which} is sufficiently lower than the inverting threshold _{voltage VT30} , so that the ON state of the epitaxial transistor 26 and the OFF state of the NMOS transistor 28 are changed. established, control output terminal _{24 OUT} of the voltage (control signal) _{V B} is kept at High level _{(V C).} In this way, the off states of both switches 18 and 20 are maintained.

As shown in FIG. 3, _{as long as the output current I H} of the power generation unit 12 is constant, the operation of each unit and the overall operation (charging / discharging operation) as described above in this low power device are repeated in a constant cycle. _{This cycle changes according to the output current I H} of the power generation unit 12, and when the environmental energy decreases and the power generation amount of the power generation unit 12 decreases, _{the current amount of the output current I H} decreases and the cycle becomes longer.

However, as shown in FIG. 4, even if the output current I _H of the power generation unit 12 becomes small, the charging speed of the capacitor 16 becomes slow and the charging time becomes long, and the discharge time and output characteristics of the capacitor 16 are changed. does not change. In the load circuit 14 is only the time of the standby mode becomes longer, the stable supply the required operating voltage V _W lasting intermittently fixed time through the power control circuit 10 (1). As a result, the load circuit 14 can operate stably and correctly for a long time even if the amount of power generated by the power generation unit 12 is weak.

As described above, the power supply control circuit 10 in this embodiment (1), once intermittently feeding supplies to the load circuit 14 from the stored in the capacitor 16 at a required operating voltage V _W electric power output from the power generation portion 12 Can be stably performed without batteries. Further, the power supply control circuit 10 (1) has two threshold values V due to a small-scale circuit configuration of only the switches 18 and 20, the nonlinear bypass circuit 22 and the switch control circuit 24 (CMOS inverter 30) and its logical operation. _The required hysteresis characteristic for switching the charge and discharge of the capacitor 16 by using TH and _{VTL is easily and efficiently realized.}

In addition, the power supply control circuit 10 (1) in this embodiment consumes very little self-power when charging the capacitor 16. That is, since only the switch control circuit 24 (CMOS inverter 30) and the non-linear bypass circuit 22 are used, the power consumption is negligibly small. Nonlinear bypass circuit 22 is constituted by the diode _{D 1} ‥‥ _{D n} and the resistor _{R 22,} the non-linear characteristic of the diode _{D 1} ‥‥ _{D n,} between the terminals of the capacitor 16 to the voltage _{V C} is feed start threshold value _{V TH} After reaching it, a substantial bypass current I ₂₂ is only passed for a moment, and _{the power consumed by the resistor R 22} is significantly higher than that of the reference voltage generation circuit and resistance voltage divider circuit used in the prior art of the comparator system. few. Further, since the switch control circuit 24 is composed of one CMOS inverter 30 and does not allow a steady current to flow inside the switch control circuit 24, the power consumption is extremely small. This is a big difference from the conventional technology of the comparator method, in which a current is constantly passed inside the comparator to consume a large amount of electric power.

In the low power device of this embodiment, the electric power generated by the power generation unit 12 is stored in the capacitor 16 with high charging efficiency without being wasted by the power supply control circuit 10 (1), and the electric power stored in the capacitor 16 is stored in the capacitor 16. It is supplied to the load circuit 14 with high power supply efficiency without being wasted by the power supply control circuit 10 (1). As a result, even if the amount of power generated by the power generation unit 12 is weak, the load circuit 14 is intermittently and stably supplied with the _{required operating voltage V W by the efficient power supply control of the power supply control circuit 10 (1), and is long.} It can operate correctly with time stability.

[Embodiment 2]

FIG. 5 shows the circuit configuration of the power supply control circuit 10 (2) according to the second embodiment of the present invention. In the figure, the same reference numerals are given to the parts common to the power supply control circuit 10 (1) of the first embodiment (FIG. 1) described above.

As shown in FIG. 5, the power supply control circuit 10 (2) in the second embodiment is described in the first embodiment (FIG. 1) in order to stabilize the logical operation and increase the degree of freedom in circuit design. ), It has a configuration in which three MOS transistors 32, 36, and 38 are added as an extension part of the switch control circuit 24.

Among, NMOS transistor 32 constitute a second CMOS inverter 34 to the operating voltage a voltage _{V C} across the terminals of the capacitor 16 in conjunction with the switch (PMOS transistor) 18. More specifically, the source of the NMOS transistor 32 is _{connected to the negative electrode side terminal 16 − of the capacitor 16, the drain thereof is connected to the output terminal 34 OUT} common to the drain of the switch (IMPO transistor) 18, and the gate thereof is a switch. It is connected to _{the input terminal 34 IN} , which is common to the gate of (PM2 transistor) 18. _{The threshold value VT} 32 of the NMOS transistor 32 is set to the same value as _{the threshold value VT} 18 of the switch (PM2 transistor) 18. _{Therefore, assuming} that the inversion threshold value of the second CMOS inverter 34 is _VT34 , VT34 = _VT18 = _VT32 and _VT34 < _VTL = _VT30 .

PMOS transistor 36 and NMOS transistor 38 constitute a third CMOS inverter 40 to the operating voltage a voltage _{V C} across the terminals of the capacitor 16 tied to each other. In this CMOS inverter 40, its input terminal 40 _{IN is connected to the output terminal 34 OUT} of the second CMOS inverter 34, and its output terminal 40 _OUT is connected to the gate of the switch (PMPC transistor) 20. In the CMOS inverter 40 within, PMOS transistor 36 has its source connected the positive pole side terminal 16 ₊ of the capacitor 16, a drain connected to the output terminal _{40 OUT,} a gate connected to the input terminal _{40 IN.} On the other hand, the source of the NMOS transistor 38 is _{connected to the negative electrode side terminal 16 −} of the capacitor 16, the drain thereof is connected to the output terminal 40 _OUT , and the gate thereof is connected to the input terminal 40 _IN . When the threshold value of the MOS transistors 36,38 _{V T36, V T38,} the inversion threshold of the CMOS inverter 40 and _{V T40,} a _{V T40 = V T36 = V T38} , V T40 ≦ V TL = V T30 Conditions are set.

In this power supply control circuit 10 (2), when the terminal voltage _{V C} of the capacitor 16 becomes equal to or higher than the feed start threshold value _{V TH} during charging, the node voltage _{V N22} from the non-linear bypass circuit 22 (≧ _{V TN} = in response to V _T30) changing the first CMOS inverter 30 whose output or control signal _{V B} of the switch control circuit 24 from between the capacitor terminal voltage _V C (High level) to the ground potential (Low level). Then, in response to this, in the second CMOS inverter 34, at the same time that the switch (PM2 transistor) 18 is turned on, the NMOS transistor 32 is turned off.

When the switch (PMOS transistor) 18 is turned on, the terminal voltage _V C of the capacitor 16 (High level) is input to the input terminal _{40 IN} of the third CMOS inverter 40 through which. Thus, in the third CMOS inverter 40, PMOS transistor 36 is the NMOS transistor 38 is turned on at the same time OFF, the output (control signal) _{V K} ground potential from the voltage across the capacitor terminals _V C (High level) (Low Level) It changes to. In this way, when the control signal V _K changes from the voltage between the capacitor terminals _VC (High level) to the ground potential (Low level), the switch (PMPO transistor) 20 using this as the gate voltage is turned on.

Thus, when the terminal voltage _{V C} of the capacitor 16 becomes equal to or higher than the feed start threshold value _{V TH} rises during charging, the non-linear bypass circuit 22, the first CMOS inverter 30, second CMOS inverters 34 and third inverter 40 is turned on a chain in sequence responsive to the switches 18 and 20 at the same time, switching of the input voltage _{V a} relative to the start of the first CMOS inverter 30 of the discharge of the capacitor 16 _{(V N22} → _V C) Are done at the same time.

When the terminal voltage V _C of the capacitor 16 becomes less clogging inversion threshold V _T30 below the feed stop threshold V _TL drops during discharge, the input voltage V _A voltage V _C across the capacitor terminals at this point In the first CMOS inverter 30, the logic level of the _{output (control signal) V B is inverted.} That is, the NMOS transistor 28 is turned off at the same time the PMOS transistor 26 is turned on, changes in the output (control signal) _{V B} is the ground potential between the capacitor terminals from (Low level) voltage _{V C} (≒ _{V TL).}

Then, in the second CMOS inverter 34, the input voltage (control signal V _{B ) exceeds the inverting threshold voltage VT 34} (<V _TL ) from the ground potential (Low level), so that the switch (PMPO transistor) 18 is turned off. then to the NMOS transistor 32 is turned on at the same time, the voltage _{V W} of the output terminal _{34 OUT} is changed from the voltage _{V C} across the capacitor terminals to the ground potential (Low level).

Thus the output of the second CMOS inverter 34 is changed to the ground potential (Low level) from the voltage _{V C} across the capacitor terminals, the third CMOS inverter 40 in response to this, the PMOS transistor 36 is turned on at the same time the NMOS transistor 38 There was off, the output (control signal) _{V K} it to the Low level (ground potential) from the switch (PMOS transistor) between High level capacitor terminal against 20 voltage _{V C} (≒ _{V TL).} As a result, the switch (IMPPO transistor) 20 is turned off.

Thus, when the terminal voltage _{V C} of the capacitor 16 during discharge is to the following power supply stop threshold value _{V TL} lowered, the first CMOS inverter 30, second CMOS inverter 34 and a third inverter 40 There chained to sequentially response off both switches 18 and 20 at the same time, switching of the input voltage _{V a} for the stop of the first CMOS inverter 30 of the discharge of the capacitor 16 _{(V C} → _{V N22)} are carried out simultaneously.

Incidentally, in the power supply control circuit 10 (2), the inversion threshold _{V T40} of the third CMOS inverter 40 first same value as inversion threshold _{V T30} of the CMOS inverter 30 _(V T40 ₌ V _T30) If set, when the terminal voltage _{V C} of the capacitor 16 drops to the vicinity of the feed stop threshold _{V TL} during discharge, that from the first CMOS inverter 30 third CMOS inverter 40 is responsive to previously There can also be.

In that case, in the third CMOS inverter 40, the NMOS transistor 38 is turned off at the same time as the epitaxial transistor 36 is turned on as described above, and the output (control signal) V _K is between the ground potential (Low level) and the capacitor terminals. changes to the voltage _{V C} (≒ _{V TL),} the switch (PMOS transistor) 20 is turned off to receive it as the gate voltage of the High level. When the switch (P community transistor) 20 is turned off, the input voltage _{VA of the first CMOS inverter 30 is switched to the node voltage VN22} from the nonlinear bypass circuit 22, and in response to this, the output (control) of the first CMOS inverter 30. signal) _{V B} changes from the ground potential (Low level) between the capacitor terminal voltage _{V C} (≒ _{V TL),} the switch (PMOS transistor) 18 is turned off to receive it as the gate voltage of the High level. When the switch (PMOS transistor) 18 is turned off, stops discharge of the capacitor 16, the voltage _{V C} across the capacitor terminals turns to rise _{(V C> V TL).}

Although not shown, it is also possible to omit the NMOS transistor 32 which is connected to the switch (PMOP transistor) 18 to form the second CMOS inverter 34. On the other hand, it is also possible configuration in which the resistance of the pull-up between the gate of the positive terminal 16 ₊ and the switch (PMOS transistor) 20 of the capacitor 16. The pull-up resistor, lifting the switch (PMOS transistor) between the gate voltage of the 20 of the capacitor 16 terminal voltage _V C (High level) when the control signal _{V K} is not determined or stable at Low level. Thereby, the hysteresis width can be designed to an arbitrary value.

[Embodiment 3]

FIG. 6 shows the circuit configuration of the power supply control circuit 10 (3) in the second embodiment. In the figure, the same reference numerals are given to the parts common to the power supply control circuits 10 (1) and 10 (2) in the first and second embodiments.

As shown in FIG. 6, in the power supply control circuit 10 (3), a non-linear bypass circuit 42 is provided between _{the positive electrode side terminal 16 +} of the capacitor 16 and the output side terminal 18 _{OUT of the switch (P community transistor) 18.} There is. The nonlinear bypass circuit 42 has one or more (n) diodes D ₁ ... D _n , an intermediate node N _42, and a bypass capacitor C ₄₂ . More specifically, the diode D ₁ ... D _n is connected in series between the positive electrode side terminal 16 ₊ of the main capacitor 16 and the node N ₄₂ with each anode directed toward the positive electrode side terminal 16 ₊ , and the bypass capacitor C _42. Is connected between the node N _{42 and the terminal 18 OUT} on the output side of the switch (P community transistor) 18. The capacitance of the bypass capacitor C ₄₂ is selected to be an order of magnitude smaller (pF order) than that of the main capacitor 16.

In this power supply control circuit 10 (3), when the terminal voltage V _C of the main capacitor 16 becomes equal to or higher than the feed start threshold value V _TH, diodes D ₁ ‥‥ D _n nonlinear bypass circuit 42 conducts during charging Then, the non-linear bypass circuit 42 can be configured so that the node voltage V _N42 becomes equal to or higher than the node voltage threshold value V _TN (V _TN = V _{TH −} n · V _f).

The power supply control circuit 10 (3) uses a hysteresis inverter 44 for the switch control circuit 24. The hysteresis inverter 44 is preferably composed of a CMOS Schmitt trigger inverter, and its input terminal is _{connected to the node N 42} of the non-linear bypass circuit 42 and the output side terminal (drain) of the switch (IMPO transistor) 20 and its output. terminal is connected to the switch control terminal of the (PMOS transistor) 18 (gate), and the operating voltage of the terminal voltage _{V C} of the main capacitor 16, first and second inversion threshold _{V T44L, V T44H} (provided that It _{has VT44L} < _VT44H ).

Also in this embodiment, as described above, a relationship of _{V TN = V TH -n · V} f between the feeding start threshold value _{V TH} and node voltage threshold _{V TN.} Therefore, the preferred embodiment sets a first inversion threshold _{V T44L} hysteresis inverter 44 to the same value as the node voltage threshold _{V TN (V T44L = V TN} ), the second inversion threshold the value _{V T44H} may be set to the same value as the power supply stop threshold value _{V TL (V T44H = V TL} ).

The power supply control circuit 10 (3) is provided with a switch 46 on the operating voltage supply line between the main capacitor 16 and both inverters 40 and 44. The switch 46 is a PMOS transistor, a source connected to the positive terminal 16 ₊ the main capacitor 16, a drain connected to the operating voltage input terminals of both inverters 40 and 42, it outputs the gate of the inverter 40 Connected to the terminal. The resistor 48 is connected between the output terminal of the positive terminal 16 ₊ and the switch (PMOS transistor) gates of 20, 46 and CMOS inverter 40 of the main capacitor 16. The switch control circuit 24 in the power supply control circuit 10 (3) includes a hysteresis inverter 44, a CMOS inverter 40, a switch 46, and a resistor 48.

In the power supply control circuit 10 (3), the higher the voltage applied to the diode D ₁ ‥‥ D _n of the non-linear bypass circuit 42 as inter-terminal voltage V _C of the main capacitor 16 rises during charging. However, due to the nonlinear characteristic of a diode as described above, until the terminal voltage V _C of the main capacitor 16 reaches the feeding start threshold value V _TH, diodes D ₁ ‥‥ D _n is a substantially non-conductive state _{The bypass current I 42} flowing in the non-linear bypass circuit 42 is extremely small, and the bypass current I ₄₂ is taken into the bypass capacitor C ₄₂ and converted into electric power (electrostatic energy).

On the other hand, the switches (PM2 transistors) 18, 20 and 46 are kept off, respectively, and the hysteresis inverter 44 and the CMOS inverter 40 are fed by the leakage current of the switch 46. _{At this time, the voltage of the terminal 18 OUT} on the output side of the switch 18 is at the ground potential, and the epitaxial transistor 36 and the NMOS transistor 38 (FIG. 5) are in the on state and the off state in the CMOS inverter 40, respectively. Thus, it has led the positive terminal of the main capacitor 16 16 ₊ via the PMOS transistor 36 in the ON state of the resistor 48 and the CMOS inverter 40 to the operating voltage input terminal of the hysteresis inverter 44. That is, the switch (PMOS transistor) 46 is not applied to an off state, the hysteresis inverter 44 is operating under the terminal voltage V _C of the main capacitor 16, the output (control signal) V _B is kept to the voltage _{V C} across the capacitor terminals is High level to the switch (PMOS transistor 18).

When the terminal voltage _{V C} of the main capacitor 16 becomes equal to or higher than the feed start threshold value _{V TH,} the nonlinear bypass circuit within 42 diode _{D 1} ‥‥ _{D n} becomes conductive node voltage _{V N22} is the node voltage threshold The value is V _NT (V _NT = V _{TH −} n · V _f ) or more. At this time, the voltage _{V A} which is input to the hysteresis inverter 44 is the node voltage _{V N42,} the node voltage _{V N42} becomes higher node voltage threshold _{V NT} that is more than the first inversion threshold _{V T44L} As a result, the output (control signal) V _B of the hysteresis inverter 44 changes from the voltage between the capacitor terminals _VC (High level) to the ground potential (Low level).

In this way, when the output (control signal) V _{B of the} hysteresis inverter 44 changes from the voltage between the capacitor terminals _VC (High level) to the ground potential (Low level), the switch (IMPRO transistor) 18 is turned on in response to this. Discharge (feeding) from the main capacitor 16 to the load circuit 14 is started. Additionally, it changes from the output of the CMOS inverter 40 (control signal) _{V K} it until the capacitor inter-terminal voltage _V C (High level) to the ground potential (Low level), the switch (PMOS transistor) 20, 46 is also turned on.

When the switch 20 is turned on, the positive terminal of the main capacitor 16 16 ₊ leads to the node _{N 42} of the input terminal and the non-linear bypass circuit 42 of the hysteresis inverter 44 via the switch 20. Accordingly, the hysteresis inverter 44, the internal state or logic level established stable input voltage V _A is switched to the first inversion threshold V _T44L higher across the capacitor terminal voltage V _C, the output (control signal ) V _B is held at the ground potential (Low level).

In the nonlinear bypass circuit 42, at the same time the conduction of the diode _{D 1} ‥‥ _{D n} stops gone potential difference between the positive terminal 16 ₊ and the node _{N 42} of the main capacitor 16, the switch 20 of the on-state bypass capacitor _{C 42} The discharge current is once absorbed by the main capacitor 16 or merged with the discharge current of the main capacitor 16 and then supplied to the load circuit 14 via the switch 18. However, the discharge of the bypass capacitor C ₄₂ is extremely small as compared with that of the main capacitor 16, and the discharge time is instantaneous.

When the terminal voltage _{V C} of the main capacitor 16 by feeding to the load circuit 14 (discharge) becomes less than the feed stop threshold _{V TL} down, the hysteresis inverter 44, the input voltage _V A (= _{V C} ) is a second inversion threshold _V T44H _{(= V TL)} becomes less, the output (control signal) _{V B} it to the ground potential (terminal voltage of the main capacitor 16 from the Low level) _{V C} (≒ It changes to _VTL).

Then, the switch (Pomycin transistor) 18 that inputs this control signal V _B as a high level control voltage (gate voltage) is turned off, and the voltage on the output side drops to the ground potential (Low level). Thus, changes to the output of the CMOS inverter 40 (control signal) _{V K} ground potential terminal voltage of the main capacitor 16 from (Low level) _{V C} (≒ _{V TL),} which High level of the control voltage (gate voltage) The switches (IgG transistor) 20 and 46 to be input as are turned off. At that time, the resistor 48 acts as a pull-up resistor, so that the switching off of both switches (PM2 transistors) 20 and 46 is stably performed.

Thus, with switches to charging stops discharge of the main capacitor 16 (power feed), nonlinear bypass circuit 42 in the diode D ₁ ‥‥ D _n node voltages V _N42 conduction stops the drops to near ground potential, the hysteresis inverter 44 The input voltage _{VA of} is switched to the node voltage _{VN42 again.}

Also in this power supply control circuit 10 (3), the same operation and effect as those of the power supply control circuits 10 (1) and 10 (2) of the first and second embodiments can be obtained with respect to the charge / discharge operation. Further, since the power supply control circuit 10 (3) is provided with a bypass capacitor C ₄₂ instead of providing a resistor in the non-linear bypass circuit 22, most of the electric power is _{supplied even if the bypass current I 42} flows in the non-linear bypass circuit 22. Do not consume. The In low-power devices, even power generation amount of the power generation section 12 is weak, the load circuit 14, the required operating voltage V _W to intermittently by efficient charge and discharge control of the power supply control circuit 10 (3) It is stably supplied and can operate stably and correctly for a long time.

Further, the power supply control circuit 10 (3) uses a hysteresis inverter 44 having _{first and second inversion thresholds VT44L} and _{VT44H in the switch control circuit 24.} And, it first inverted inversion threshold for response main switch control circuit 24 when the terminal voltage V _C of the capacitor 16 becomes equal to or more than feed start threshold value V _TH is through a non-linear bypass circuit 42 assign a threshold value V _T44L, the main capacitor 16 switch control circuit 24 when the terminal voltage V _C is below the feed stop threshold V _TL is oN switch 20 for responding to it through A second inverting threshold _VT44H is assigned to the inverting threshold, which further increases the degree of freedom in circuit design.

It is also possible to make the magnitude relationship of the first and second inversion thresholds _VT44L and _VT44H the opposite of the above ( _VT44L > _VT44H). Further, in the power supply control circuit 10 (3), it is also possible to use a CMOS inverter 30 having a single inversion threshold value instead of the hysteresis inverter 44. Alternatively, the hysteresis inverter 44 can be used instead of the CMOS inverter 30 in the power supply control circuits 10 (1) and 10 (2) of the first and second embodiments. Further, the power supply control circuits 10 (1) and 10 (2) of the first and second embodiments can also be provided with the switch 46.

[Other embodiments or modifications]

Although preferred embodiments of the present invention have been described above, the above-described embodiments do not limit the present invention. Those skilled in the art can make various modifications and changes in specific embodiments without departing from the technical idea and scope of the present invention.

For example, in the first and second embodiment, the feed stop threshold V _TH, during the inversion threshold V _T30 and node voltage threshold V _NT, as a preferred embodiment, they are the same value That is, the relationship of V _TL = V _T30 = V _NT (where V _NT = V _TH −n · V _f ) was set. However, as another aspect, it is also possible to set the relationship of _{V TL} = V _T30 > V _NT (where V _NT = V _{TH −} n · V _f).

In that case, when the terminal voltage _{V C} of the capacitor 16 rises to the power supply start threshold value _{V TH} during charging, the node voltage _{V N22} conducting diode _{D 1} ‥‥ _{D n} is a non-linear bypass circuit within 42 becomes the node voltage threshold _{V NT (V NT = V TH} -n · V f), the relationship between _{V TL = V T30> V NT} , at that time, still switch control circuit 24 (CMOS inverter 30) It does not respond and the logic level of _{its output V B is not inverted.} However, when the terminal voltage _{V C} of the capacitor 16 is further increased, the node voltage _{V N22} with it be even higher _{(V N22>} V _NT), the end will be more than inversion threshold _{V T30,} it responds _{Then, the logic level of the output V B} of the switch control circuit 24 (CMOS inverter 30) is inverted, whereby both switches 18 and 20 are turned on. However, the node until voltage V _N22 consists turned node voltage threshold V _NT to inversion threshold V _T30 or continue substantial bypass current I ₂₂ flows through a non-linear bypass circuit within 42, sentence that There is one aspect that power is consumed by the resistor R _22.

FIG. 7 shows a modified example of the connection position of the switch 20 for switching the input voltage to the switch control circuit 24. In the illustrated power supply control circuit 10 (4) _{, the switch 20 is connected between the output side terminal 18 OUT} of the charge / discharge switching switch 18 and the voltage input terminal of the switch control circuit 24. Even with this configuration, the switch 20 can perform the same input voltage switching function on the switch control circuit 24 as in the first embodiment (FIG. 1).

More specifically, in this configuration, when the switch 18 is off, that is, during charging, up to the start of power supply for the threshold V _TH terminal voltage V _C of the capacitor 16 rises, the non-linear diode D ₁ ‥‥ D _n of the bypass circuit 22 is substantially keeping the non-conducting state, the capacitor 16 is charged efficiently. Then, the terminal voltage _{V C} of the capacitor 16 becomes higher feed start threshold value _{V TH,} the node voltage _{V N22} is the node voltage threshold _{V NT (V TN = V TH} -n · V f) above and the switch It becomes the inversion threshold V _T30 or more control circuits 24, in response to this by inverting the logic level of the output V _B switch control circuit 24 to turn on both switches 18 and 20.

Then, the positive electrode side terminal 16 _{+ of the capacitor 16 is connected to the positive electrode side input terminal 14 +} of the load circuit 14 via the switch 18, and the discharge (power supply) from the capacitor 16 to the load circuit 14 is started. Moreover, positive terminal 16 ₊ is also lead to the voltage input terminal of the switch control circuit 24 via the switch 18, 20, the input voltage _{V A} across the capacitor terminals from the node voltage _{V N22} voltage V of the switch control circuit 24 of the capacitor 16 Switch to _C.

Then, under the switch 18, 20 is on, i.e. during discharge, the voltage V _C across the capacitor terminals drops below the feed stop threshold value V _TL, which in response to the switch control circuit 24 is output V _{Invert the logic level of B} and turn off both switches 18 and 20. Then, discharge with (power supply to the load circuit 14) is stopped, the input voltage _{V A} of the switch control circuit 24 is switched from the voltage _{V C} across the capacitor terminals to the node voltage _{V N22,} the output current I of the capacitor 16 is the power generation portion 12 It will be charged by _H.

In short, when the switch 18 is on, the voltage on the input side of the switch 18 or the voltage between terminals of the capacitor 16 _VC and the voltage on the output side of the switch 18 or the input voltage V _W of the load circuit 14 are substantially the same. Is. Therefore, when viewed from the switch control circuit 24, and when the terminal of the other side of the switch 20 (the input side) is connected positively electrode terminal 16 ₊ input side terminal or the capacitor 16 of the switch 18, the output of the switch 18 in the case that is connected to the positive input terminal 14 ₊ side terminal or a load circuit 14, there is no difference in the input voltage V _a. This also applies to the power supply control circuits 10 (2) and 10 (3) of the second and third embodiments (FIGS. 5 and 6).

As another aspect, in the power supply control circuits (1), (2), and (3) of the above-described embodiment, it is possible to replace the epitaxial transistor of each part with an NMOS transistor and replace the NMOS transistor of each part with a epitaxial transistor. .. Thus, for example, when forming the switch 20 in the NMOS transistor may be provided with resistors for pull-down between the negative terminal 16 ₊ of the gate and the capacitor 16.

The present invention is suitably applicable to low power devices such as IoT devices that operate with energy harvesting as in the above embodiment. However, the present invention is not limited to such applications, and can be applied to any power supply control circuit that controls intermittent power supply from a power generation unit that outputs a direct current to a load circuit in various types of devices capable of intermittent operation. be.

10 (1), 10 (2), 10 (3), 10 (4) Power control circuit 12 Power generation unit 14 Load circuit 16 Capacitor (main capacitor)
18 switch 20 switch 22 non-linear bypass circuit N ₂₂ node D ₁ ‥‥‥ D _n diode R ₂₂ resistance 24 switch control circuit 26 MIMO transistor 28 NMOS transistor 30 CMOS inverter 32 NMOS transistor 34 CMOS inverter 36 ProLiant transistor 38 NMOS transistor 40 CMOS inverter 42 Non-linear bypass circuit N ₄₂ node C ₄₂ bypass capacitor 44 hysteresis inverter

Claims (15)

It is a power supply control circuit that controls the intermittent power supply from the capacitor connected in parallel to the DC power generation unit to the load circuit.
A first switch connected between the first terminal of the capacitor and the corresponding input terminal of the load circuit,
The capacitor is connected between the first terminal and the second terminal of the capacitor, has a node in the middle, and has one or more diodes between the first terminal and the node. With a non-linear bypass circuit in which the diode conducts in the forward direction and the voltage of the node becomes equal to or higher than the second threshold value lower than the first threshold value when the voltage between terminals of the above becomes equal to or higher than the first threshold value. ,
A voltage input terminal connected to the node of the non-linear bypass circuit and connected to an input side terminal or an output side terminal of the first switch via a second switch, and the first and second switches. A switch control circuit that has a control output terminal that outputs a control signal for controlling the on / off of the switch, and uses the voltage between the terminals of the capacitor as an operating voltage.
Equipped with
The switch control circuit turns on the first and second switches after the voltage between the terminals of the capacitor becomes equal to or higher than the first threshold value while the first and second switches are off. The first and second switches are turned on after the voltage between the terminals of the capacitor becomes equal to or lower than the third threshold value lower than the first threshold value. Turn off,
Power control circuit. The power supply control circuit according to claim 1, wherein the nonlinear bypass circuit has a first resistor between the node and the second terminal of the capacitor. In the switch control circuit, the voltage between the terminals of the inverter is used as the operating voltage, the input terminal constitutes the voltage input terminal, the output terminal constitutes the control output terminal, and the inverting threshold value thereof is the second. The power supply control circuit according to claim 1 or 2, further comprising a first inverter having the same value as the threshold value of. The first inverter has a first conductive type first MOS transistor and a second conductive type second MOS transistor connected in series between the first and second terminals of the capacitor.
The source of the first MOS transistor is connected to the first terminal of the capacitor, its drain is connected to the control output terminal, and its gate is connected to the voltage input terminal.
The source of the second MOS transistor is connected to the second terminal of the capacitor, its drain is connected to the control output terminal, and its gate is connected to the voltage input terminal.
The power supply control circuit according to claim 3. The first switch has its source connected to the first terminal of the capacitor, its drain connected to the input terminal of the load circuit, and its gate connected to the control output terminal of the switch control circuit. The power supply control circuit according to claim 4, further comprising a first conductive type third MOS transistor. The switch control circuit has its source connected to the second terminal of the capacitor, its drain connected to the input terminal of the load circuit, and its gate connected to the control output terminal of the switch control circuit. The power supply control circuit according to claim 5, further comprising a second conductive type fourth MOS transistor. The source of the second switch is connected to the first terminal of the capacitor, its drain is connected to the voltage input terminal of the switch control circuit, and its gate is the control output terminal of the switch control circuit. The power supply control circuit according to any one of claims 4 to 6, further comprising a first conductive type fifth MOS transistor connected to. The second switch has a first conductive type fifth MOS transistor whose source is connected to the first terminal of the capacitor and its drain is connected to the voltage input terminal of the switch control circuit. death,
In the switch control circuit, the input terminal is connected to the output side terminal of the first switch, the output terminal is connected to the gate of the fifth MOS transistor, and the voltage between the terminals of the capacitor is defined as the operating voltage. Has a second inverter to
The power supply control circuit according to claim 5 or 6. The second inverter has a first conductive type sixth MOS transistor and a second conductive type seventh MOS transistor connected in series between the first and second terminals of the capacitor.
The source of the sixth MOS transistor is connected to the first terminal of the capacitor, the drain of the sixth MOS transistor is connected to the gate of the fifth MOS transistor, and the gate is on the output side of the first switch. Connected to the terminal,
The source of the seventh MOS transistor is connected to the second terminal of the capacitor, the drain of the seventh MOS transistor is connected to the gate of the fifth MOS transistor, and the gate is on the output side of the first switch. Connected to the terminal,
The power supply control circuit according to claim 8. It is a power supply control circuit that controls intermittent power supply from the main capacitor connected in parallel to the DC power generation unit to the load circuit.
A first switch connected between the first terminal of the main capacitor and the corresponding input terminal of the load circuit, and
Between the intermediate node, one or more diodes connected between the first terminal of the main capacitor and the node, and the output side terminal of the node and the first switch. It has a bypass capacitor to be connected, and when the voltage between the terminals of the main capacitor becomes equal to or higher than the first threshold value, the diode conducts in the forward direction and the voltage of the node becomes higher than the first threshold value. A non-linear bypass circuit that goes above and below the lower second threshold,
A voltage input terminal connected to the node of the nonlinear bypass circuit and connected to an input side terminal or an output side terminal of the first switch via a second switch, and the first and second switches. A switch control circuit that has a control output terminal that outputs a control signal for controlling the on / off of the switch, and uses the voltage between the terminals of the first capacitor as an operating voltage.
Equipped with
The switch control circuit turns on the first and second switches after the voltage between the terminals of the main capacitor becomes equal to or higher than the first threshold value while the first and second switches are off. Then, when the first and second switches are on and the voltage between the terminals of the main capacitor becomes equal to or less than the third threshold value lower than the first threshold value, the first and second switches are turned on. Switch off,
Power control circuit. The switch control circuit has a second resistor connected between the control terminal of the second switch and either the first terminal or the second terminal of the first capacitor. The power supply control circuit according to any one of Items 1 to 10. In the switch control circuit, the voltage between the terminals of the inverter is used as the operating voltage, the input terminal constitutes the voltage input terminal, the output terminal constitutes the control output terminal, and the inverting threshold value thereof is the second. The power supply control circuit according to claim 10, further comprising an inverter having the same value as the threshold value of. In the switch control circuit, the voltage between the terminals of the inverter is used as the operating voltage, the input terminal constitutes the voltage input terminal, the output terminal constitutes the control output terminal, and the inverting threshold value of one of them constitutes the control output terminal. The power supply control circuit according to claim 1 or 10, further comprising a hysteresis inverter having the same value as the third threshold value. It is a power supply control circuit that controls the intermittent power supply from the capacitor connected in parallel to the DC power generation unit to the load circuit.
It has an intermediate node and at least one diode connected between the first terminal of the capacitor and the node, and when the voltage between the terminals of the capacitor becomes equal to or higher than the first threshold value, the above-mentioned It has a non-linear bypass circuit in which the diode conducts in the forward direction so that the voltage of the node becomes equal to or higher than the second threshold value lower than the first threshold value.
The voltage between the terminals of the capacitor is used as the operating voltage, and power supply to the load circuit is started in response to a change in the logic level based on the second threshold voltage of the voltage of the node, and the voltage between the terminals of the capacitor is started. Alternatively, the power supply to the load circuit is stopped in response to a change in the logic level based on a third threshold value lower than the first threshold voltage of the input voltage of the load circuit.
Power control circuit. A power generation unit that converts given environmental energy into electric power and outputs direct current.
A capacitor connected in parallel to the output terminal of the power generation unit,
A load circuit that can perform constant operations intermittently,
A low power device having the power supply control circuit according to any one of claims 1 to 14, which controls intermittent power supply from the capacitor to the load circuit.

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