JP2021145386A - 復号装置および符号化装置 - Google Patents
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Abstract
Description
・特定のラインに対し、弱いフィルタを適用するか否かの決定(輝度)
・p0’iおよびq0’iに対する(弱い)フィルタリング
・p1’iおよびq1’iのフィルタリングの際にも値Δ1を使用
if (delta1>tc)
{
delta1=tc;
}
else if (delta1<−tc)
{
delta1=−tc;
}
if (delta1>0)
{
if (delta1>tc)
{
delta1=tc;
}
}
else
{
if (delta1<−tc)
{
delta1=−tc;
}
}
if (delta>0)
{
delta1=(delta+a)>>4;
if (delta1>tc)
{
delta1=tc;
}
}
else
{
delta1=(delta+b)>>4;
if (delta1<−tc)
{
delta1=−tc;
}
}
Const UChar tctable_8X8 [56] =
{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14
} ;
Const UChar betatable_8X8 [52] =
{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64
};
d = dq + dp < β
図12は、コンテンツ配信サービスを実現するコンテンツ供給システムex100の全体構成を示す図である。通信サービスの提供エリアを所望の大きさに分割し、各セル内にそれぞれ固定無線局である基地局ex106、ex107、ex108、ex109、ex110が設置されている。
上記各実施の形態で示した動画像符号化方法または装置と、MPEG−2、MPEG4−AVC、VC−1など異なる規格に準拠した動画像符号化方法または装置とを、必要に応じて適宜切替えることにより、映像データを生成することも可能である。
上記各実施の形態で示した動画像符号化方法および装置、動画像復号化方法および装置は、典型的には集積回路であるLSIで実現される。一例として、図26に1チップ化されたLSIex500の構成を示す。LSIex500は、以下に説明する要素ex501、ex502、ex503、ex504、ex505、ex506、ex507、ex508、ex509を備え、各要素はバスex510を介して接続している。電源回路部ex505は電源がオン状態の場合に各部に対して電力を供給することで動作可能な状態に起動する。
上記各実施の形態で示した動画像符号化方法または装置によって生成された映像データを復号する場合、従来のMPEG−2、MPEG4−AVC、VC−1などの規格に準拠する映像データを復号する場合に比べ、処理量が増加することが考えられる。そのため、LSIex500において、従来の規格に準拠する映像データを復号する際のCPUex502の駆動周波数よりも高い駆動周波数に設定する必要がある。しかし、駆動周波数を高くすると、消費電力が高くなるという課題が生じる。
テレビや、携帯電話など、上述した機器・システムには、異なる規格に準拠する複数の映像データが入力される場合がある。このように、異なる規格に準拠する複数の映像データが入力された場合にも復号できるようにするために、LSIex500の信号処理部ex507が複数の規格に対応している必要がある。しかし、それぞれの規格に対応する信号処理部ex507を個別に用いると、LSIex500の回路規模が大きくなり、また、コストが増加するという課題が生じる。
Claims (2)
- 処理回路と、
前記処理回路に接続されたメモリとを備え、
前記処理回路は、前記メモリを用いて、
第1ブロックと第2ブロックとの境界に対するフィルタを、複数の候補から選択し、
選択した前記フィルタを用いて、前記境界に垂直に交差する直線上に並んだ複数の画素の値を変更するデブロッキングフィルタ処理を行い、
前記デブロッキングフィルタ処理では、それぞれの前記複数の画素変化量を、プラスのクリッピング値以上、マイナスの前記クリッピング値以下とするクリッピング処理を行い、
前記複数の候補は、第1の数の前記複数の画素の値を変更する第1のフィルタと、前記第1の数より大きい第2の数の前記複数の画素の値を変更する第2のフィルタとを含み、
前記クリッピング値は、前記第1のフィルタを用いる場合と前記第2のフィルタを用いる場合とで値が異なる、
復号装置。 - 処理回路と、
前記処理回路に接続されたメモリとを備え、
前記処理回路は、前記メモリを用いて、
第1ブロックと第2ブロックとの境界に対するフィルタを、複数の候補から選択し、
選択した前記フィルタを用いて、前記境界に垂直に交差する直線上に並んだ複数の画素の値を変更するデブロッキングフィルタ処理を行い、
前記デブロッキングフィルタ処理では、それぞれの前記複数の画素変化量を、プラスのクリッピング値以上、マイナスの前記クリッピング値以下とするクリッピング処理を行い、
前記複数の候補は、第1の数の前記複数の画素の値を変更する第1のフィルタと、前記第1の数より大きい第2の数の前記複数の画素の値を変更する第2のフィルタとを含み、
前記クリッピング値は、前記第1のフィルタを用いる場合と前記第2のフィルタを用いる場合とで値が異なる、
符号化装置。
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US20160165238A1 (en) * | 2014-12-09 | 2016-06-09 | Vixs Systems Inc. | Neighbor tile buffering for deblock filtering across tile boundaries |
WO2017045101A1 (en) * | 2015-09-14 | 2017-03-23 | Mediatek Singapore Pte. Ltd. | Advanced deblocking filter in video coding |
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