JP2021145131A - RF integrated power adjustment capacitor - Google Patents

Abstract

To provide an RF integrated power adjustment capacitor that has a capacitance greater than or equal to 1 nf and less than 1 mm2 corresponding to high voltage and high current.SOLUTION: A method for fabricating an RF integrated power adjustment capacitor includes the steps of creating a region of ceramic material by selectively applying ultraviolet light exposure to a photosensitive glass substrate and then etching it to produce a substrate including one or more two- or three-dimensional capacitive devices.SELECTED DRAWING: None

Description

The present invention relates to a step of making an integrated RF power conditioning capacitor.

Although the scope of the present invention is not limited, the background of the present invention will be described in relation to the power adjustment capacitor.

RF devices are using more power. RF devices of this class generate pulses at voltages above 10 V and currents above 2 amps. Switching the signal on and off at this level of current and voltage creates a significant amount of harmonic signals. These harmonic signals can interfere with the operation of the circuit. Large-value integrated silicon capacitors cannot achieve the required capacitance and suffer from dielectric breakdown.

We have developed a photodefinable glass-ceramic that can be converted from a glass phase to a ceramic phase through a combination of exposure to ultraviolet light and heat treatment. Selective application of UV exposure using a photomask or shadow mask creates an area of ceramic material in the photosensitive glass. The present invention provides one or more two-dimensional or three-dimensional capacitive devices by preparing photosensitive glass substrates with high surface area structures, dielectrics, and coatings with one or more metals. Including a method of manufacturing a substrate to be provided.

In one embodiment of the invention, the method of forming an integrated large capacitance for power regulation on photosensitive glass with a small foam factor is to create one or more vias on the photosensitive glass in the photosensitive glass. One or more in the photosensitive glass substrate, with the step of depositing a conductive seed layer processed to form an opening and placing the photosensitive glass substrate with a metallized seed layer that electroplates the metal. A step of filling the openings to form vias, a step of chemically and mechanically polishing the front and back surfaces of the photosensitive glass substrate to leave only the filled vias, and the perimeter of two adjacent filled vias. A step of exposing and transforming at least one rectangular portion of the photosensitive glass substrate, and a step of etching the rectangular patent to expose at least one pair of adjacent filled vias to form a metal post. A step of flash-coating a non-oxidizing layer on a metal post forming a first electrode, a step of depositing a dielectric layer on or around the post, and a metal coating of the dielectric layer to form a second electrode. A step and a step of connecting the first metal layer in parallel to all of the first electrodes to form a single electrode for a capacitor, and a second metal layer of all of the second electrodes. Includes a step of forming a second electrode for the capacitor by connecting in parallel with the metal. In one aspect, the dielectric layer is a thin film with a thickness of 0.5 nm to 1000 nm. In another aspect, the dielectric layer is a sintered paste with a thickness of 0.05 μm to 100 μm. In another aspect, the dielectric layer has a dielectric constant of 10 to 10,000. In another aspect, the dielectric layer has a dielectric constant of 2-100. In another embodiment, the dielectric layer is deposited by ALD. In another embodiment, the dielectric layer is deposited by a doctor blade. In another aspect, the capacitor has a capacitance density greater than ^{1,000 pf / mm 2.}

In another embodiment of the invention, a method of forming an integrated large capacitance for power regulation on a photosensitive glass substrate with a small foam factor is a step of masking a circular pattern on a photosensitive glass substrate. A step of exposing at least a portion of the photosensitive glass substrate to an activated UV energy source, and a step of heating the photosensitive glass substrate to a heating phase of at least 10 minutes at a temperature higher than its glass transition temperature. The steps of cooling the photosensitive glass substrate and converting at least a portion of the exposed glass into a crystalline material to form a glass-ceramic crystalline substrate and the ceramic phase of the photosensitive glass substrate with an etching solution. A step of partially etching and removing, a step of depositing a conductive seed layer on the photosensitive glass, and a photosensitive glass substrate are arranged together with a metallized seed layer for electroplating a metal to form a photosensitive glass. Two adjacent steps, one is to fill one or more openings in the substrate to form vias, and the other is to chemically and mechanically polish the front and back surfaces of the photosensitive glass substrate to leave only the filled vias. Around the filled vias to be filled, the steps of exposing and transforming at least one rectangular portion of the photosensitive glass substrate and etching the rectangular patent to expose at least one pair of adjacent filled vias to expose the metal. A step of forming a post, a step of flash-coating a non-oxidizing layer on a metal post forming a first electrode, a step of depositing a dielectric layer on or around the post, and a metal coating of the dielectric layer, The step of forming the second electrode, the step of connecting the first metal layer in parallel to all of the first electrodes to form a single electrode for a dielectric, and the step of forming the second metal layer. , Includes a step of connecting in parallel to all of the second electrodes to form a second electrode for the capacitor. In one aspect, the dielectric layer is a thin film with a thickness of 0.5 nm to 1000 nm. In another aspect, the dielectric layer is a sintered paste with a thickness of 0.05 μm to 100 μm. In another aspect, the dielectric layer has a dielectric constant of 10 to 10,000. In another aspect, the dielectric layer has a dielectric constant of 2-100. In another embodiment, the dielectric layer is deposited by ALD. In another embodiment, the dielectric layer is deposited by a doctor blade. In another aspect, the capacitor has a capacitance density greater than ^{1,000 pf / mm 2.}

Yet another embodiment of the present invention includes a step of masking a circular pattern on a photosensitive glass substrate, a step of exposing at least a portion of the photosensitive glass substrate to an activated UV energy source, and a photosensitivity. A step of heating the glass substrate to a heating phase of at least 10 minutes at a temperature higher than its glass transition temperature and cooling the photosensitive glass substrate to convert at least a portion of the exposed glass into a crystalline material. , A step of forming a glass-ceramic crystalline substrate, a step of partially etching and removing the ceramic phase of the photosensitive glass substrate with an etching solution, and a step of depositing a conductive seed layer on the photosensitive glass. A step of arranging the photosensitive glass substrate together with a metallized seed layer for electroplating a metal to fill one or more openings in the photosensitive glass substrate to form vias, and a step of forming a via. A step of chemically mechanically polishing the front and back surfaces to leave only the filled vias, and a step of exposing and transforming at least one rectangular portion of the photosensitive glass substrate around two adjacent filled vias. And the steps of etching the rectangular patent to expose at least one pair of adjacent filled vias to form a metal post and flashcoating a non-oxidizing layer onto the metal post forming the first electrode. A step, a step of depositing a dielectric layer on or around the post, a step of metal-coating the dielectric layer to form a second electrode, and a first metal layer for all of the first electrodes. And the step of connecting in parallel to form a single electrode for the dielectric and the second metal layer connected in parallel to all of the second electrodes to form the second electrode for the dielectric. Includes integrated capacitors made by methods that include. In one aspect, the dielectric layer is a thin film with a thickness of 0.5 nm to 1000 nm. In another aspect, the dielectric layer is a sintered paste with a thickness of 0.05 μm to 100 μm. In another aspect, the dielectric material has a dielectric constant of 10 to 10,000. In another aspect, the dielectric thin film has a dielectric constant of 2-100. In another embodiment, the dielectric thin film is deposited by ALD. In another embodiment, the dielectric paste material is deposited by the doctor blade. In another aspect, the capacitor has a capacitance density greater than ^{1,000 pf / mm 2.}

For a more complete understanding of the features and advantages of the present invention, a detailed description of the present invention will now be referred to in conjunction with the accompanying drawings.
It is an image of a filled through hole via with a seed layer electroplated with copper. FIG. 5 is a cross-sectional view of an RF power adjustment capacitor and a substance key in which the insulating material is HfO _2. It is a top view of the capacitor for RF power adjustment. It is a BaTIO ₃ system integrated power adjustment capacitor. It is a through hole having a diameter of 65 μm and a pitch from center to center of 72 μm.

The fabrication and use of various embodiments of the invention will be discussed in detail below, but the invention provides many applicable inventions, which are in a wide variety of individual situations. It should be understood that it can be embodied in. The individual embodiments discussed herein are merely illustrations of the individual methods of making and using the invention and do not define the scope of the invention.

To facilitate the understanding of the present invention, some terms are defined below. The terms defined herein have meanings commonly understood by those skilled in the art in which the invention relates. For example, terms such as "one (a)", "one (an)", and "the" are not intended to refer to only a single subject, but are individual examples. Is intended to include a general classification of what can be used for illustration. The terminology used herein is used to describe individual embodiments of the invention, but their use limits the invention except as outlined in the claims. It's not something to do.

The photosensitive glass material is processed in a simple three-step process using first-generation semiconductor manufacturing equipment, where the final material is formed into either glass or ceramic, or glass. And can include both areas of ceramic. Photosensitive glass has several advantages for the fabrication of a wide variety of microsystem components, systems on chips, and systems in packages. Microstructures and electronic components are relatively inexpensively manufactured from these types of glass using conventional semiconductor and printed circuit board (PCB) processing equipment. In general, glass has high temperature stability, good mechanical and electrical properties, and better chemical resistance than plastics and many types of metals.

When exposed to ultraviolet light in the absorption band of cerium oxide, cerium oxide acts as a sensitizer by absorbing photons and losing electrons. This reaction reduces nearby silver oxide to form silver atoms. For example, it is as follows.

Ce ³⁺ + Ag ⁺ = □ Ce ⁴⁺ + Ag ⁰

The silver ions coalesce into silver nanoclusters during the heat treatment process and induce nucleation sites in the surrounding glass to form the crystalline ceramic phase. This heat treatment must be performed at a temperature near the glass transition temperature. The ceramic crystalline phase is more soluble in an etching solution such as hydrofluoric acid (HF) than the unexposed vitreous amorphous glassy region. Specifically, the crystalline [ceramic] region of FOTURAN® was etched at 10% HF about 20 times faster than the amorphous region and about 20: 1 when the exposed region was removed. Allows microstructures with wall slope ratios of. See T. R. Dietrich et al., "Fabrication technologies for microsystems utilizing photoetchable glass," Microelectronic Engineering 30, 497 (1996). This is incorporated herein by reference. Photosensitive glasses of other compositions will be etched at different rates.

One method of making a metal device using a photosensitive glass substrate composed of silica, lithium oxide, aluminum oxide, and cerium oxide is to use a mask and UV light to at least in the photosensitive glass substrate. It involves creating a pattern with one, two-dimensional or three-dimensional ceramic phase region.

Preferably, the molded glass structure comprises at least one or more two-dimensional or three-dimensional induction devices. This capacitive device is formed by making a series of connected structures to form a high surface area capacitor for power regulation. These structures can be rectangular, circular, oval, fractal, or any other shape that creates a pattern that produces capacitance. The patterning area of APEX ™ glass can be filled with a metal, alloy, composite, glass, or other magnetic medium by several methods, including plating or vapor deposition. The permittivity of the medium, combined with the dimensions, high surface area, and number of structures in the device, provides the inductance of the device. At higher operating frequencies, materials such as copper or other similar materials are common for inductive devices, as inductive device designs will require materials with different magnetic permeability, depending on the operating frequency. It will be the preferred medium for. Once the capacitive device is created, the supporting APEX ™ glass is either held in place or removed to create an array of capacitive structures that can be mounted in series or in parallel.

This method can be used to create large surface area capacitors with values greater than or equal to 1 nf per ^{mm 2 that exceed the technical requirements desired for integrated power conditioning capacitance densities.} There are different device architectures based on the relative permittivity used and the deposition technique preferred for the dielectric material. The present invention provides a method of creating a device architecture for each dielectric material.

In general, glass-ceramic materials have had limited success in forming microstructures. The formation of microstructures suffers from performance, uniformity, usefulness by others, and availability issues. Etching aspect ratios obtained with past glass-ceramic materials were approximately 15: 1, in contrast, APEX® glass has an average etching aspect ratio of greater than 50: 1. This allows the user to create smaller, deeper features. In addition, our manufacturing method allows for product yields in excess of 90% (yields on glass to date are around 50%). Finally, in conventional glass-ceramics, only about 30% of glass is converted to a ceramic state, while in APEX® glass-ceramic, this conversion rate is around 70%.

The APEX® composition provides three mechanisms due to its enhanced performance. (1) higher amounts of silver result in the formation of smaller ceramic crystals that are etched faster at the grain boundaries, and (2) the content of silica (the main constituent etched by HF acid). The reduction reduces unwanted etching of unexposed material, and (3) higher total weight percent of alkali metals and boron oxide results in a much more homogeneous glass during production.

Ceramicization of glass is achieved by exposing the entire glass substrate to 310 nm light at approximately 20 J / cm ^2. When attempting to create a glass space within a ceramic, the user exposes all of the material except the glass where it should remain glass. In one embodiment, the invention provides a quartz / chrome mask containing various concentric circles with different diameters.

The above-mentioned high surface area capacitor demonstrated by the present inventors uses a thin film metallized via using a CVD method. The metallized vias are then _{coated with a thin film of dielectric material, such as a 20 nm Al 2} O ₃ layer, using the ALD method, and then an upper metal coating is applied to obtain the effective surface area of the vias (s) and the effective surface area of the vias (s). Create a large capacitance due to the ultra-thin coating of dielectric.

The present invention includes methods for making inductive devices in or on glass-ceramic structures in electrical, microwave, and high frequency applications. Glass ceramic substrate may be a light sensitive glass substrate having the composition variation of the wide number, but are not limited to, 60 to 76 wt% of silica; at least 3 wt% of K _{2 O,} 6 weight% to 16 weight%, accompanied by a combination of _{K 2} O and Na ₂ O; of 0.003 wt%, it is selected from the group consisting of Ag2O and Au2O, at least one oxide; 0.003 2 wt% of _Cu 2 O; 0.75 wt% to 7 wt% of B2O3 and 6-7 wt% _Al 2 _{O 3,} the combination of B 2 _{O 3} and _Al 2 _{O 3} is exceed 13 wt% no; 8-15 wt% of _Li 2 O; and 0.001 wt% of CeO ₂ and the like. This composition and various other compositions are commonly referred to as APEX® glass.

The exposed portion of the glass can be converted into a crystalline substance by heating the glass substrate to a temperature near the glass transition temperature. For example, when etching a glass substrate with an etching solution such as hydrofluoric acid, the glass is exposed to an ultraviolet (about 308 to 312 nm) floodlight lamp in a wide spectrum to form a molding having an aspect ratio of at least 30: 1. When a glass structure is provided to create an inductive structure, the anisotropic etching ratio of the exposed portion to the unexposed portion is at least 30: 1. The mask for exposure may be that of a halftone mask that provides continuous grayscale for exposure and forms a curved structure for creating inductive structures / devices. Digital masks can also be used with flood exposure and can be used to result in the creation of inductive structures / devices. The exposed glass is then typically baked in a two-step process. A heating temperature range of 10 minutes to 2 hours at 420 ° C to 520 ° C combines silver ions with silver nanoparticles, and a heating temperature range of 10 minutes to 2 hours at 520 ° C to 620 ° C is that of silver nanoparticles. Form lithium oxide in the surroundings. The glass plate is then etched. The glass substrate is typically etched with an etching solution of 5% by volume to 10% by volume of HF solution, and when exposed to an ultraviolet floodlight in a wide spectrum, the exposed portion with respect to the etching ratio of the unexposed portion. There is provided a molded glass structure having an etching ratio of at least 30: 1 and, when exposed to a laser, greater than 30: 1 and having an anisotropic etching ratio of at least 30: 1. FIG. 1 shows an image of a filled through hole via with a seed layer electroplated with copper.

The present invention includes capacitive structures made up of multiple metal posts on a glass-ceramic substrate, such methods in wafers containing at least one or more two-dimensional or three-dimensional capacitor devices. A photosensitive glass substrate is used. The photosensitive glass wafer may be in the range of 50 μm to 1,000 μm, preferably 250 μm in our case. The photosensitive glass is then patterned in a circular pattern and etched throughout the bulk of the glass. The circular pattern may have a diameter in the range of 5 μm to 250 μm, but is preferably 30 μm in diameter. A uniform titanium seed layer is deposited across the wafer containing vias by the CVD method. The thickness of the seed layer may be in the range of 50 nm to 1000 nm, but is preferably 150 nm. The wafer is then placed in an electroplating bath where copper (Cu) is deposited on the seed layer. The copper layer needs to be sufficient to fill the vias, in this case 25 μm. The front and back sides of the wafer are wrapped and re-polished to photosensitive glass. This can be seen in FIG. 2A. A rectangular pattern is made in photosensitive glass using the method described above to convert 10% to 90% of the glass, preferably 80% of the volume of the photosensitive glass. Vias may also accept additional low concentrations of rinsing with an etchant such as diluted HF. Diluted HF will pattern or texture the ceramic walls of the vias. The texture formation of the ceramic wall significantly increases the surface area of the structure and directly increases the capacitance of the device. The photosensitive glass with exposed copper has a metallized polyimide that is placed on the back side of the garment in physical / electrical contact with copper-filled vias. The photosensitive glass with an exposed copper column in contact with the metallized polyimide is placed in an electroplating bath where a flash coating of non-oxide or metal forming a semiconductor or conductive oxide is applied. , Electroplated on the surface of the metal post. The metal is preferably gold (Au). This thin flash coating prevents oxidation of the copper post during the deposition of dielectric medium / material. Atomic layer (ALD)
An oxidizable metal is deposited using the deposition) method, or for example 10 Å Ta ₂ O
_5. The dielectric is deposited by directly depositing an oxidizing substance such as a dielectric layer of Al ₂ O ₃ or, but not limited to, _{another vapor phase dielectric containing Al 2 O 3. Al 2} O _{3 at} 380 ° C. using TMA and O ₃ , cycle time: 3.5 seconds. The Al ₂ O ₃ layer is then heated to 300 ° C. for 5 minutes in an oxygen atmosphere to completely oxidize the dielectric layer. The thickness of this dielectric layer may be in the range of 5 nm to 1000 nm. The preferred thickness for us is 5 nm, as can be seen in FIG. 2A. Next, copper RLDs are deposited to fill the rectangular holes. The RLD is preferably a copper paste deposited by the silk screening method. The wafer is then placed in a furnace and heated to 450 ° C. to 700 ° C. for 5-60 minutes in an inert gas or vacuum environment. The preferred temperature and time for us is 600 ° C. in argon gas for 20 minutes. The final step is to bring the RLD copper into contact with the front of the die in rows and the back of the wafer in columns. All of the front rows are connected in parallel to create electrodes for large integrated surface area capacitors. Similarly, all the columns on the back of the die are connected in parallel to create a lower electrode for a large integrated surface area capacitor. FIG. 2B shows a top view of the RF power adjustment capacitor.

A second embodiment can be seen in FIG. The present invention includes capacitive structures made up of multiple metal posts on a glass-ceramic substrate, such methods in wafers containing at least one or more two-dimensional or three-dimensional capacitor devices. A photosensitive glass substrate is used. The photosensitive glass wafer may be in the range of 50 μm to 1,000 μm, preferably 250 μm in our case. The photosensitive glass is then patterned in a circular pattern and etched throughout the bulk of the glass. The circular pattern may have a diameter in the range of 5 μm to 250 μm, but is preferably 30 μm in diameter. A uniform titanium seed layer is deposited across the wafer containing vias by the CVD method. The thickness of the seed layer may be in the range of 50 nm to 1000 nm, but is preferably 150 nm. The wafer is then placed in an electroplating bath where copper (Cu) is deposited on the seed layer. The copper layer needs to be sufficient to fill the vias, in this case 25 μm. The front and back sides of the wafer are wrapped and re-polished to photosensitive glass. This can be seen in FIG. A rectangular pattern is made in photosensitive glass using the method described above to convert 10% to 90% of the glass, preferably 80% of the volume of the photosensitive glass. Vias may also accept additional low concentrations of rinsing with an etchant such as diluted HF. The photosensitive glass with an exposed copper column in contact with the metallized polyimide is placed in an electroplating bath where a flash coating of non-oxide or metal forming a semiconductor or conductive oxide is applied. , Electroplated on the surface of the metal post. The metal is preferably gold (Au). This thin flash coating prevents oxidation of the copper post during the deposition of dielectric medium / material. The dielectric region is then created by silk screening this into a rectangular well using _{a commercially available BaTIO 3 paste.} The wafer is then placed in a furnace and heated to 450 ° C.-700 ° C. for 5-60 minutes in an oxygen atmosphere. The preferred temperature and time is 600 ° C. for 30 minutes in an oxygen atmosphere. The final step is to bring the RLD copper into contact with the front of the die in rows and the back of the wafer in rows parallel to the top electrodes. All of the front rows are connected in parallel to create electrodes for large integrated surface area capacitors. Similarly, all the rows on the back of the die are tied in parallel to create a lower electrode for a large integrated surface area capacitor.

FIG. 4 shows a through hole having a diameter of 65 μm and a center-to-center pitch of 72 μm.

Although the present invention and its advantages have been described in detail, various modifications, substitutions and modifications have been made to the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Please understand that you can do it. Also, the scope of this application is limited to specific embodiments of the processes, machines, manufactures, compositions, means, methods, and steps described herein. Not intended. As those skilled in the art will readily appreciate from the disclosure of the present invention, substantially perform the same functions as the corresponding embodiments described herein, or achieve substantially the same results. Processes, machines, manufactures, compositions, means, methods, or steps that currently exist or are developed later can be utilized in accordance with the present invention. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions, means, methods, or steps of a product within them. ..

The present invention creates a cost-effective glass-ceramic 3D capacitor structure or 3D capacitor array device. When a glass-ceramic substrate demonstrates the ability to form such a structure, processing both the vertical and horizontal planes separately or simultaneously results in the formation of two-dimensional or three-dimensional capacitive devices.

The present invention prepares a photosensitive glass substrate with vias or posts and further coats or fills with one or more conductive layers, typically metals, dielectrics, and top conductive layers, typically metals. By doing so, it includes a method of making a substrate with one or more two-dimensional or three-dimensional capacitor devices.

The fabrication and use of various embodiments of the invention will be discussed in detail below, but the invention provides many applicable inventions, which are in a wide variety of individual situations. It should be understood that it can be embodied in. The individual embodiments discussed herein are merely illustrations of the individual methods of making and using the invention and do not limit the scope of the invention.

It is contemplated that any embodiment discussed herein can be implemented with respect to any method, kit, reagent, or composition of the invention, and vice versa. In addition, the compositions of the invention can be used to achieve the methods of the invention.

It will be appreciated that the particular embodiments described herein are provided for illustration purposes only and are not intended to limit the present invention. The main features of the present invention can be adopted in various embodiments without departing from the scope of the present invention. One of ordinary skill in the art will be able to identify a number of equivalents to the individual procedures described herein without using more than recognition or routine experimental work. Such equivalents are considered to be within the scope of the invention and are covered by the claims.

All publications and patent applications referred to herein indicate the level of skill of one of ordinary skill in the art in the art in which the invention relates. All publications and patent applications are incorporated herein by reference to the same extent that each individual publication or patent application is individually and specifically indicated to be incorporated by reference.

The use of the terms "one (a)" or "one (an)" when used in combination with the term "comprising" in the claims and / or in the present specification. May mean "one", but is consistent with the meanings of "one or more", "at least one", and "more than one or one". The use of the term "or" in the claims refers to "and / or" unless it is explicitly stated that the options refer to only one option or that the options are mutually exclusive. As used to mean, the present disclosure employs definitions that refer to only certain options and / or both. Throughout this application, the term "about" is used to indicate that a value includes deviations in errors inherent in the device, method used to determine the value, or deviations present in the subject of study. Has been done.

As used herein and in the claims, "comprising" (and any form of including, such as "comprise" and "comprises"), "comprising".
Any form of having (and any form of having, such as "have" and "has"), "including" (and any form of including, such as "includes"). And "include"), or "containing" (and any form of containing, such as "contains" and "contain") It is inclusive or non-limiting and does not exclude additional, unlisted elements or method steps. In any embodiment of the compositions and methods provided herein, "contains" may be replaced by "becomes essential" or "becomes essential". As used herein, the phrase "becomes essential" is substantially relative to the features or functions of the claimed invention, as well as to the identified perfection (s) or steps. We also need something that does not affect us. As used herein, the term "consisting of" means an enumerated complete field (eg, feature, element, feature, characteristic, method / process step, or limit) or group of perfect fields (eg, feature). Used to indicate the existence of only (s), elements (s), features (s), characteristics (s), methods / process steps, or limits (s).

As used herein, the term "or a combination thereof" refers to all permutations and combinations of listed items that precede this term. For example, "A, B, C, or a combination thereof" is intended to include at least one of A, B, C, AB, AC, BC, or ABC, in a particular context. It is intended to include BA, CA, CB, CBA, BCA, ACB, BAC, or CAB when the order is important. Continuing with this example, combinations involving one or more repetitions of items or terms, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CABABB, and others are explicitly included. Those skilled in the art will appreciate that there are typically no restrictions on the number of items or terms in any combination, unless otherwise apparent from the context.

As used herein, an approximate term, such as, but not limited to, "about," "substantially," or "substantially," a condition is so modified. If so, it means that it does not have to be absolute or complete, but can be considered close enough for a person skilled in the art to warrant that the condition exists. The extent to which the description can vary is to what extent the variation can be set, and those skilled in the art who still have the required features and capabilities of the modified spot color and the unmodified spot color. However, it still depends on whether it can be recognized. The numbers herein, which are generally modified by approximate terms such as "about", are at least ± 1, 2, 3, 4 from the referred values, although it follows the previous discussion. It can fluctuate by 5, 6, 7, 10, 12, or 15%.

All of the compositions and / or methods disclosed and claimed herein can be made and carried out without the experimental work that would be overstated in the light of the present disclosure. The compositions and methods of the present invention have been described from the standpoint of preferred embodiments, but those skilled in the art will not deviate from the concept, purpose and scope of the present invention. It will be apparent that changes can be made to, as well as in the steps or steps of the methods described herein. All such alternatives and modifications that will be apparent to those skilled in the art are deemed to be within the spirit, scope and concept of the invention as defined by the appended claims.

In interpreting the claims attached herein, to assist the Patent Office and all readers of all patents issued under this application, Applicants have "for" in certain claims. Unless the words "means" or "steps for" are explicitly used, all of the appended claims are in Article 112, Paragraph 6 of the US Patent Law, Article 112 (f) of the US Patent Law. It is desired to note that it is not intended to activate a paragraph or equivalent that exists as of the filing date of the invention.

For each of the claims, each dependent claim is an independent claim and the preceding dependent claim for every claim, as long as the previous claim provides a reasonable basis in advance for the terms or elements of the claim. It can be subordinate to each of the terms.

Claims (10)

How to make a capacitive device, including:
Steps to provide a photosensitive glass substrate;
The step of processing the photosensitive glass substrate to form one or more vias;
The step of rinsing the one or more vias with an etching solution to pattern or texture the walls of the one or more vias to increase the surface area of the walls;
A step of depositing a metallized seed layer on the photosensitive glass substrate, wherein the metallized seed layer is deposited in the one or more vias;
A step of depositing a copper layer on the seed layer, wherein the copper layer is deposited in the one or more vias;
The step of exposing the photosensitive glass substrate by removing the seed layer and the copper layer from the first surface of the photosensitive glass substrate and from the second surface of the photosensitive glass substrate. The step of leaving the seed layer and the copper layer in the one or more vias;
One or two or more rectangular wells are made in each of the first surface and the second surface around the one or more vias, and the copper layer is placed in the one or more vias. Steps exposed as a copper column;
The flash coating of (1) a non-oxide metal, (2) a first metal forming a semiconductor oxide, and (3) a second metal forming a conductive oxide is applied to the first metal of the photosensitive glass substrate. The step of electroplating the surface and the second surface;
Steps of depositing a dielectric material on the front and back surfaces of the photosensitive glass substrate;
The step of filling the one or more rectangular wells with a resistor-inductor diode (RLD);
The step of heating the photosensitive glass substrate;
The step of forming the resistor-inductor diode (RLD) in a row on the first surface of the photosensitive glass substrate and connecting the rows in parallel to form a first capacitor electrode; and the resistor-. A step of forming an inductor diode (RLD) in rows or columns on the second surface of the photosensitive glass substrate and connecting the rows or columns in parallel to form a second capacitor electrode. The step of depositing a metallized seed layer on a photosensitive glass substrate is performed by a chemical vapor deposition (CVD) method; or the step of depositing a copper layer on the metallized seed layer electroplates the photosensitive glass substrate. The step of exposing the photosensitive glass substrate by placing it in a bath; or by removing the seed layer and the copper layer is performed by wrapping, by polishing, or by both wrapping and polishing; Alternatively, the step of depositing the dielectric material is performed using atomic layer deposition; or the step of depositing the resistor-inductor diode (RLD) is performed by the silk screening process.
The method according to claim 1. The method of claim 1, wherein the metallized seed layer comprises titanium. The method of claim 1, wherein the metallized seed layer has a thickness of more than 50 nm and less than 1000 nm. The step of creating one or more rectangular wells in each of the first and second surfaces around one or more vias is
The method of claim 1, comprising converting one or more portions of the photosensitive glass substrate into a crystalline ceramic; and etching and removing the crystalline ceramic. Copper layer remaining in one or more vias performed after the step of making one or more rectangular wells and before the step of electroplating the flash coating on the front and back surfaces of the photosensitive glass substrate. The method according to claim 1, further comprising contacting the rear surface of the photosensitive glass substrate containing the above with a metallized polyimide. The step of electroplating the flash coating on the front and back surfaces of the photosensitive glass substrate involves electroplating the gold flash coating; or the step of heating the photosensitive glass substrate is an inert gas, vacuum environment, or Including heating to 450 ° C. to 700 ° C. for 5 to 60 minutes in an oxygen environment.
The method according to claim 1. One or two or more first copper columns each having a patterned or textured surface; and one or more first copper columns in contact with the first copper column to increase the surface area of the surface, coupled in parallel. A row of one or more resistors-inductor diodes (RLDs)
Dielectric material in contact with the one or more first copper columns and in contact with the row of resistors-inductor diodes (RLDs) of the one or more;
A first electrode comprising a; and one or more second copper columns having a patterned or textured surface, respectively; to increase the surface area of the surface; and the one or more second copper. A row of one or more resistors-inductor diodes (RLDs) connected in parallel that contact the column;
A capacitive device comprising a second electrode comprising
The capacitive device, located in or on a photosensitive glass substrate. The thickness of the copper layer is 25 μm; or the thickness of the dielectric layer is 5 nm; or the thickness of the dielectric layer is 1 nm or more and 1000 nm or less.
The capacity device according to claim 8. The dielectric material contains (1) vapor phase dielectric; (2) paste; or (3) a combination thereof; or the dielectric material contains Ta ₂ O ₅ , Al ₂ O ₃ , BaTIO ₃ paste, or a combination thereof. Or the resistor-inductor diode (RLD) contains copper paste;
The capacity device according to claim 8.

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