JP2021141788A - Power inverter circuit - Google Patents

Abstract

To adjust a dead time appropriately.SOLUTION: A power inverter circuit includes a first switching element connected between a first input terminal and a second input terminal to which power is input between them, a second switching element connected in series with the first switching element between the first input terminal and the second input terminal, a driver that alternately turns on and off the first switching element and the second switching element at a switching frequency, a detector that detects an amount related to an input current input to the first input terminal or the second input terminal, and a control unit that controls the length of a dead time during which both the first switching element and the second switching element are turned off, on the basis of the frequency at which the detected amount is a threshold value or more, and the switching frequency.SELECTED DRAWING: Figure 7

Description

The present invention relates to a power conversion circuit, for example, a power conversion circuit having a switching element.

In a power conversion circuit having a switching element, it is known to adjust a dead time in which a pair of vertically connected switching elements are turned off at the same time (for example, Patent Documents 1 to 3). It is known that the dead time is adjusted based on the temperature of the switching element (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2003-284352 Japanese Unexamined Patent Publication No. 2017-11857 Japanese Unexamined Patent Publication No. 2018-102085

Increasing the dead time causes loss. When the dead time is shortened, a through current flows through a pair of vertically connected switching elements. The penetrating current may damage the switching element or the like. In addition, a loss occurs due to the through current. Therefore, by adjusting the dead time so that the through current does not flow, it is possible to suppress the loss and suppress the damage of the switching element or the like due to the through current.

However, the method of adjusting the dead time based on the temperature of the switching element has low temperature followability. Therefore, when the temperature rise of the switching element is detected, the switching element or the like may be damaged. A method of directly measuring the through current can be considered, but if the noise current is judged to be the through current and the dead time is adjusted, the dead time cannot be adjusted appropriately.

The present invention has been made in view of the above problems, and an object of the present invention is to appropriately adjust the dead time.

In the present invention, the first switching element connected between the first input terminal and the second input terminal to which electric power is input between them, and the first switching element between the first input terminal and the second input terminal. A second switching element connected in series with the switching element, a driver that alternately turns on and off the first switching element and the second switching element at a switching frequency, and the first input terminal or the second input terminal. Both the first switching element and the second switching element are based on a detector that detects an amount related to an input current input to the power supply and a frequency at which the detected amount exceeds a threshold value and the switching frequency. It is a power conversion circuit including a control unit that controls the length of the dead time that is turned off.

In the above configuration, the control unit may be configured to shorten the dead time when the detected amount does not exceed the threshold value or the frequency does not substantially match the switching frequency.

In the above configuration, the control unit may be configured to increase the dead time when the frequency substantially matches the switching frequency.

In the above configuration, the detector includes a transformer having a primary winding and a secondary winding through which the input current flows, and the quantity related to the input current is a current value flowing through the secondary winding. be able to.

In the above configuration, the detector comprises a transformer having a primary winding and a secondary winding through which the input current flows, and a resistor connected between both ends of the secondary winding, and the input. The amount related to the current can be configured to be the voltage difference across the resistor.

In the above configuration, the detector may include a resistor through which the input current flows, and the amount related to the input current may be a voltage difference between both ends of the resistor.

In the above configuration, the first input terminal and the second input terminal are provided with an inductor in which one end is connected to a node between the first switching element and the second switching element and the other end is connected to a first output terminal. A configuration may be configured in which DC power is input between the input terminal and DC power is output between the first output terminal and the second output terminal.

In the above configuration, the first input terminal and the second input terminal are provided with an input capacitor connected in parallel with the first switching element and the second switching element, and the detector is the first input terminal. It can be configured to detect an amount related to the input current between the input capacitor and the input capacitor.

In the above configuration, when the control unit controls the length of the period during which both the first switching element and the second switching element are turned off, the control unit is located between the first input terminal and the second input terminal. The voltage to be applied may be lower than the voltage applied between the first input terminal and the second input terminal when the power conversion circuit performs power conversion.

According to the present invention, the dead time can be adjusted appropriately.

FIG. 1 is a diagram showing a circuit diagram of a power conversion circuit according to the first embodiment. 2 (a) to 2 (c) are timing charts showing drive signals of the switching element in the first embodiment. 3 (a) and 3 (b) are circuit diagrams of the detectors used in simulations 1 and 2. 4 (a) to 4 (c) are diagrams showing the drive signal and the input current Iin in the simulation 1, and the drive signals V1, V2 and V1 with respect to the time after the transition from the transient state immediately after the start of the simulation to the steady state are shown. The input current Iin is shown. 5 (a) and 5 (b) are diagrams showing the voltage difference ΔV across the resistor R in simulations 1 and 2, respectively, and are driven with respect to the time after the transition from the transient state immediately after the start of the simulation to the steady state. The signals V1 and V2 and the voltage difference ΔV are shown. 6 (a) to 6 (c) are diagrams showing the drive signal and the voltage difference ΔV in the simulation 2. FIG. 7 is a flowchart showing the control of the control circuit according to the first embodiment.

Hereinafter, examples of the present invention will be described with reference to the drawings.

In the first embodiment, as the power conversion circuit (power supply circuit), a synchronous rectification type step-down DC (Direct Current) -DC converter will be described as an example. FIG. 1 is a diagram showing a circuit diagram of a power conversion circuit according to the first embodiment.

As shown in FIG. 1, the power conversion circuit 100 includes transistors Q1 and Q2, capacitors Cin and Cout, an inductor L0, a control unit 10, a gate driver 12, and a detector 14. A DC input voltage Vin is applied between the input terminals Tin1 and Tin2 as primary power. An input capacitor Cin is connected between the input terminals Tin1 and Tin2.

Transistors Q1 and Q2 connected in series in parallel with the input capacitor Cin are connected. The source S of the transistor Q1 is connected to the node N1, the drain D is connected to the input terminal Tin1, and the gate G is connected to the gate driver 12. The source S of the transistor Q2 is connected to the input terminal Tin2, the drain D is connected to the node N1, and the gate G is connected to the gate driver 12. Transistors Q1 and Q2 have parasitic diodes D1 and D2, respectively.

An inductor L0 is connected between the node N1 and the output terminal Tout1. An output capacitor Cout is connected between the output terminals Tout1 and Tout2. The input terminal Tin2 and the output terminal Tout2 are connected to each other, and have a ground potential, for example. A DC output voltage Vout is output between the output terminals Tout1 and Tout2 as secondary power. For example, an external load Z is connected between the output terminals Tout1 and Tout2.

The detector 14 is provided between the input terminal Tin1 and the node N2 between the input capacitor Cin and the transistor Q1 and detects the input current Iin input from the input terminal Tin1. The detector 14 may be provided between the input terminal Tin2 and the node N3 between the input capacitor Cin and the transistor Q2.

The control unit 10 controls the gate driver 12 based on the voltage of the output terminal Tout1. The gate driver 12 outputs the drive signals V1 and V2 to the gate G of the transistors Q1 and Q2, respectively, so that the transistors Q1 and Q2 are alternately turned on and off at the switching frequency. Further, the control unit 10 adjusts the dead time based on the current detected by the detector 14. Details will be described later.

An adjustment power supply 18 is provided between the input terminals Tin1 and Tin2. When adjusting the dead time, the adjustment power supply 18 applies a DC voltage VDC lower than the input voltage Vin between the input terminals Tin1 and Tin2. When performing power conversion, the adjustment power supply 18 is opened.

Transistor Q1 is the main switch, and transistor Q2 is the diversion switch. As the transistors Q1 and Q2, FETs such as GaN FETs (Field Effect Transistors), SiC FETs and MOS (Metal Oxide Semiconductor) FETs, IGBTs (Insulated Gate Bipolar Transistors), and bipolar transistors can be used. When the transistors Q1 and Q2 are FETs, the input / output terminals are the source and drain, and the control terminals are gates. When the transistors Q1 and Q2 are IGBTs, the input / output terminals are emitters and collectors, and the control terminals are gates. When the transistors Q1 and Q2 are bipolar transistors, the input / output terminals are the emitter and collector, and the control terminal is the base.

2 (a) to 2 (c) are timing charts showing drive signals of the switching element in the first embodiment. FIG. 2A shows a case where the dead time is long, FIG. 2B shows a case where the dead time is medium, and FIG. 2C shows a case where the dead time is short. In reality, the periods TD1 and TD2, which are dead times with respect to the switching cycles TP1 and TP2, are very short (for example, 1/100 or less of TP1 and TP2), but in FIGS. 2 (a) to 2 (c), The periods TD1 and TD2 are shown longer.

As shown in FIG. 2A, the drive signals V1 and V2 alternately become high level H and low level L. When the drive signal V1 is low level L and high level H, the transistor Q1 is turned off and on, respectively. When the drive signal V2 is low level L and high level H, the transistor Q2 is turned off and on, respectively.

At time t1, the drive signal V1 changes from low level to high level. The drive signal V2 is low level. At time t2, the drive signal V1 changes from high level to low level. At time t3, the drive signal V2 changes from low level to high level. The drive signal V1 is low level. At time t4, the drive signal V2 changes from high level to low level. The drive signal V1 is low level. At time t1', the drive signal V1 changes from low level to high level again. After that, the same operation as at times t2', t3', t4'and t1'" is repeated. The period TP1 of the drive signal V1 and the period TP2 of the drive signal V2 are the same. 1 / TP1 and 1 / TP2 are switching frequencies. The period TW1 between the times t1 and t2 is the period during which the transistor Q1 is turned on. The period TD1 between the times t2 and t3 is the dead time when the transistors Q1 and Q2 are both turned off (that is, the voltage of the gate G with respect to the source S is low level (for example, 0V) for both the transistors Q1 and Q2). The period TW2 between the times t3 and t4 is the period during which the transistor Q2 is turned on. The period TD2 between the times t4 and t1'is the dead time when the transistors Q1 and Q2 are both off (that is, the voltage of the gate G with respect to the source S is low level (for example, 0V) for both the transistors Q1 and Q2).

During the period TW1, the control unit 10 causes the gate driver 12 to turn the transistors Q1 and Q2 on and off, respectively. A current flows from the input terminal Tin1 or the input capacitor Cin to the output terminal Tout1 via the transistor Q1 and the inductor L0. A current flows through the load Z, and the output capacitor Cout is charged. At time t2, when the output voltage Vout becomes higher than the desired voltage, the control unit 10 causes the gate driver 12 to turn off the transistor Q1. At time t3 after the lapse of the period TD1, the control unit 10 causes the gate driver 12 to turn on the transistor Q2.

During the period TW2, the magnetic field energy stored in the inductor L0 causes a current to flow from the output capacitor Cout through the transistor Q2 and the inductor L0. As a result, a current is supplied to the load Z and the output voltage Vout is maintained. At time t4, when the output voltage Vout becomes lower than the desired voltage, the control unit 10 causes the gate driver 12 to turn off the transistor Q2. At time t1'after the lapse of the period TD2, the control unit 10 causes the gate driver 12 to turn on the transistor Q1. As described above, the output voltage Vout is maintained constant.

The above control is PWM (Pulse Width Modulation) control in which the periods TP1 and TP2 are constant, that is, the switching frequency is constant, and the ratio of the periods TW1 and TW2 is changed. By providing the periods TD1 and TD2 (dead time), it is possible to suppress the flow of the through current 24 passing through the transistors Q1 and Q2 from the input terminals Tin1 to Tin2. However, during the periods TD1 and TD2, for example, when a current flows through the parasitic diodes D1 and D2, the product of the forward voltage and the current of the parasitic diodes becomes a loss. As a result, the conversion efficiency of the power conversion circuit is lowered. Further, when a current flows through the parasitic diodes D1 and D2, heat is generated.

As shown in FIG. 2 (b), the periods TP1 and TP2 are the same as in FIG. 2 (a), and the periods TD1 and TD2 are shorter than those in FIG. 2 (a). That is, the dead time is shortened. As a result, the period during which the current flows through the parasitic diodes D1 and D2 can be shortened, so that the loss is reduced and the conversion efficiency is improved.

As shown in FIG. 2 (c), the periods TP1 and TP2 are the same as in FIG. 2 (a), and the periods TD1 and TD2 are shorter than those in FIG. 2 (b). For example, the periods TD1 and TD2 are set to approximately 0. Transistors Q1 and Q2 are about to turn on at the same time around times t1 to t4. As a result, the through current 24 starts to flow. When a large through current 24 flows, the transistors Q1 and Q2 generate heat. Even when the transistors Q1 and Q2 are not damaged, when the through current 24 starts to flow, the transistors Q1 and Q2 generate heat, the loss increases, and the conversion efficiency decreases.

[simulation]
It was simulated by using the detector 14 that the through current 24 started to flow when the periods TD1 and TD2 were shortened.

3 (a) and 3 (b) are circuit diagrams of the detectors used in simulations 1 and 2.

As shown in FIG. 3A, in simulation 1, a resistor R is provided between the input terminal Tin1 and the node N2 as the detector 14. The control unit 10 measures the input current Iin from the voltage difference ΔV across the resistor R.

As shown in FIG. 3B, in the simulation 2, the transformer 16 is used as the detector 14. The primary winding L1 of the transformer 16 is connected between the input terminal Tin1 and the node N2. A resistor R is connected between both ends of the secondary winding L2 of the transformer 16. An input current I2 corresponding to an input current Iin flowing through the primary winding L1 flows through the secondary winding L2. The control unit 10 measures the input current I2 from the voltage difference ΔV across the resistor R. By appropriately setting the ratio of the number of turns of the primary winding L1 to the number of turns of the secondary winding L2 (turn ratio), the input current I2 and the resistor R that are easy to measure can be obtained.

[Simulation 1]
The input current Iin was simulated using the detector 14 of FIG. 3 (a). The simulation conditions are as follows.
Input capacitor Cin: 43 μF
Output capacitor Cout: 602 μF
Inductor L0: 2.2 μH
Transistors Q1, Q2: GaN FET
Resistance R: 0.01Ω
Input voltage Vin: 48V
Output voltage Vout: 12V
Adjustment voltage VDC: 3.3V
Switching frequency: 500kHz
Load Z: 1Ω

When the input voltage Vin is applied between the input terminals Tin1 and Tin2 when adjusting the dead time, the through current 24 becomes large. This may damage the transistors Q1 and Q2. In simulations 1 and 2, an adjustment voltage VDC lower than the input voltage Vin is applied between the input terminals Tin1 and Tin2.

4 (a) to 4 (c) are diagrams showing the drive signal and the input current Iin in the simulation 1, and the drive signals V1, V2 and V1 with respect to the time after the transition from the transient state immediately after the start of the simulation to the steady state are shown. The input current Iin is shown. In FIG. 4C, the periods TD1 and TD2 are negative in order to simulate the flow of a through current. For example, in the period TD1, the signal V2 becomes higher than the low level before the signal V1 becomes low level. The threshold value Is is the threshold value of the input current Iin for determining whether or not a through current has flowed.

As shown in FIG. 4A, the periods TD1 and TD2 are 10 nsec. The switching cycles TP1 and TP2 are 2 μsec. The period TW2 corresponding to the width of the drive signal V2 and the period TW1 corresponding to the width of the drive signal V1 are about 1.5 μsec and 0.5 μsec, respectively. The peak of the input current Iin is about 0.5A. The input current Iin peaks at the timing when the drive signal V1 becomes low level and the drive signal V2 becomes high level.

As shown in FIG. 4B, the periods TD1 and TD2 are 0 nsec. The peak of the input current Iin is about 0.7A. The input current Iin peaks at the timing when the drive signal V1 becomes low level and the drive signal V2 becomes high level.

As shown in FIG. 4 (c), the periods TD1 and TD2 are -10 n seconds. The peaks of the input current Iin are about 1.0 A and about 1.3 A. The input current Iin peaks when the drive signal V2 is at a low level and the drive signal V1 is about to switch to a high level, and the drive signals V1 and V2 are both at a high level, and the drive signal V1 is at a low level and is driven. This is the timing when the drive signals V1 and V2 are both at the high level when the signal V2 is about to switch to the high level.

As shown in FIGS. 4A to 4C, the peak of the input current Iin increases as the periods TD1 and TD2 become shorter. When the through current 24 starts to flow, the peak of the input current Iin becomes even larger.

When the through current 24 starts to flow, the peak of the input current Iin exceeds the threshold value Is, which is, for example, 0.8A. The frequency that exceeds the threshold Is is substantially the same as the switching frequency.

When the detector 14 is a resistor R, the resistance value of the resistor R is reduced in order to reduce the loss. Therefore, the voltage difference ΔV across the resistor R is small, and the current detection sensitivity is lowered.

[Simulation 2]
The voltage difference ΔV across the resistor R was simulated using the detector 14 of FIG. 3 (b). The turns ratio (L1: L2) of the transformer 16 was set to 1:10, and the resistance value of the resistor R was set to 1Ω. Other simulation conditions are the same as in simulation 1.

5 (a) and 5 (b) are diagrams showing the voltage difference ΔV across the resistor R in simulations 1 and 2, respectively. As shown in FIG. 5A, in simulation 1, the voltage difference ΔV after the transition from the transient state to the steady state is about 0.01V. As shown in FIG. 5B, in the simulation 2, the voltage difference ΔV after the transition from the transient state to the steady state is about 0.1V. In this way, the voltage difference ΔV can be increased by appropriately selecting the turns ratio using the transformer 16 as the detector 14.

6 (a) to 6 (c) are diagrams showing the drive signal and the voltage difference ΔV in the simulation 2, and the drive signals V1, V2 and the drive signals V1 and V2 with respect to the time after the transition from the transient state immediately after the start of the simulation to the steady state are shown. The voltage difference ΔV is shown. The threshold value Vth is a threshold value of a voltage difference ΔV for determining whether or not a through current has flowed.

As shown in FIG. 6A, the periods TD1 and TD2 are 10 nsec. The switching cycles TP1 and TP2 are 2 μsec. The period TW2 corresponding to the width of the drive signal V2 and the period TW1 corresponding to the width of the drive signal V1 are about 1.5 μsec and 0.5 μsec, respectively. The peak of the voltage difference ΔV is about 0.06V. ΔV peaks at the timing when the drive signal V1 becomes low level and the drive signal V2 becomes high level.

As shown in FIG. 6B, the periods TD1 and TD2 are 0 nsec. The peak of the voltage difference ΔV is about 0.08V. The voltage difference ΔV peaks at the timing when the drive signal V1 becomes low level and the drive signal V2 becomes high level.

As shown in FIG. 6 (c), the periods TD1 and TD2 are -10 n seconds. The peak of the voltage difference ΔV is about 0.24V. The voltage difference ΔV peaks at the timing when the drive signals V1 and V2 both reach the high level when the drive signal V1 is about to switch to the low level and the drive signal V2 is about to switch to the high level.

When the through current 24 starts to flow, the peak of the voltage difference ΔV exceeds the threshold value Vth, which is, for example, 0.1V. The frequency at which the threshold value Vth is exceeded substantially coincides with the switching frequency.

As shown in FIGS. 6 (a) to 6 (c), as the periods TD1 and TD2 become shorter, the peak of ΔV becomes larger. When the through current 24 starts to flow, the peak of the voltage difference ΔV becomes even larger. In Simulation 1, the peaks of the input currents Iin in FIGS. 4 (b) and 4 (c) are about 0.7 A and about 1.3 A, respectively. In simulation 2, the peaks of the voltage difference ΔV in FIGS. 6 (b) and 6 (c) are about 0.08 V and about 0.24 V, respectively. In this way, by using the transformer 16 for the detector 14, the detection accuracy of the through current can be improved.

FIG. 7 is a flowchart showing the control of the control circuit according to the first embodiment.

As shown in FIG. 7, the control unit 10 determines whether to adjust (optimize) the dead time TD (periods TD1 and TD2) (step S10). The dead time TD may be adjusted, for example, when the load Z changes, or may be performed periodically. When No, the process ends and normal voltage conversion is performed.

In step S10, when Yes, the control unit 10 switches the power supply connected between the input terminals Tin1 and Tin2 from the power supply that outputs the input voltage Vin to the adjustment power supply 18 (step S11). As a result, the voltage applied between the input terminals Tin1 and Tin2 is switched from the input voltage Vin to the voltage VDC. This is the mode for adjusting the dead time TD.

The control unit 10 sets the dead time TD to the initial period TD0 (step S12). The period TD0 is preset and is a sufficiently long period during which the through current 24 does not flow. The dead time TD is the period TD1 and TD2, but only one of the period TD1 and TD2 may be used. That is, only one of the periods TD1 and TD2 may be adjusted.

The control unit 10 detects the frequency with which the input current Iin is equal to or higher than the threshold value Is and the voltage difference ΔV is equal to or higher than the threshold value Vth (step S14). For example, in FIGS. 4A to 4C, the frequency with which the input current Iin becomes equal to or higher than the threshold value Is is detected. In FIG. 4A, the input current Iin is not equal to or higher than the threshold value Is. In FIGS. 6 (a) to 6 (c), the frequency at which the voltage difference ΔV becomes equal to or higher than the threshold value Vth is detected. In FIG. 6A, the voltage difference ΔV does not exceed the threshold value Vth.

The control unit 10 determines whether the frequency detected in step S14 substantially matches the switching frequency (step S18). In the examples of FIGS. 4 (a) and 6 (a), since the frequency cannot be detected, it is determined as No. Even when the input current Iin or the voltage difference ΔV becomes equal to or higher than the threshold value Is or Vth due to noise or the like, the frequency of exceeding the threshold value is random. Therefore, the frequency of exceeding does not match the switching frequency. Therefore, the control unit 10 determines No.

The control unit 10 sets the dead time TD to TD−ΔTD1 (step S16). ΔTD1 is preset. As a result, the dead time TD is shortened. After that, the process returns to step S14.

In step S14, the control unit 10 detects the frequency with which the input current Iin or the voltage difference ΔV becomes the threshold value Is or Vth or more. In the examples of FIGS. 4 (c) and 6 (c), the frequency with which the input current Iin becomes equal to or higher than the threshold value Is is approximately the switching frequency.

In step S18, the control unit 10 determines that the frequency detected in step S14 and the switching frequency substantially match (that is, it is determined to be Yes).

The control unit 10 sets the dead time TD to TD + ΔTD2 (step S20). ΔTD2 is preset. This increases the dead time TD.

Similar to step S14, the control unit 10 detects the frequency with which the input current Iin or the voltage difference ΔV becomes equal to or higher than the threshold value Is or Vth (step S22).

Similar to step S18, the control unit 10 determines whether the frequency detected in step S22 substantially matches the switching frequency (step S24). If Yes, the process returns to step S20. The control unit 10 determines No even when the input current Iin or the voltage difference ΔV does not exceed the threshold value Is or Vth for a certain period of time in step S22.

When No, the control unit 10 switches the power supply connected between the input terminals Tin1 and Tin2 from the adjustment power supply 18 to the power supply that outputs the input voltage Vin (step S26). As a result, the voltage applied between the input terminals Tin1 and Tin2 is switched from the voltage VDC to the input voltage Vin. The dead time TD adjustment is completed, and the mode is set to perform voltage conversion.

As described above, the control unit 10 shortens the dead time TD (periods TD1 and TD2) at ΔTD1 intervals (steps S14 to S18). When the control unit 10 determines that the through current 24 has started to flow (that is, determines Yes in step S18), the control unit 10 increases the dead time TD at ΔTD2 intervals (steps S20 to S24). When the control unit 10 determines that the through current 24 has stopped flowing (that is, determines No in step S24), the control unit 10 ends the adjustment of the dead time TD. As a result, the dead time TD can be adjusted so that the through current 24 hardly flows and is not too long. ΔTD1 and ΔTD2 may be the same or different. For example, by making ΔTD2 shorter than ΔTD1, the dead time TD can be adjusted more precisely.

According to the first embodiment, the transistor Q1 (first switching element) and the transistor Q2 (second switching element) are connected in series between the input terminal Tin1 (first input terminal) and the input terminal Tin2 (second input terminal). It is connected. The detector 14 detects an amount (for example, input current Iin or voltage difference ΔV) related to the input current Iin input to the input terminal Tin1 (or input terminal Tin2). The control unit 10 determines the length of the dead time TD in which both the transistors Q1 and Q2 are turned off based on the frequency f2 and the switching frequency f1 at which the detected input current Iin or the voltage difference ΔV becomes the threshold value Is or Vth or more. To control.

As a result, the control unit 10 can determine whether or not the through current 24 is flowing based on the frequency f2 and the switching frequency f1 at which the input current Iin or the voltage difference ΔV becomes the threshold value Is or Vth or more. Even if the input current Iin or the voltage difference ΔV becomes equal to or higher than the threshold value Is or Vth due to noise or the like, it is possible to suppress erroneous determination that the through current 24 has flowed. Further, as compared with the method of adjusting the dead time based on the temperature of the switching element as in Patent Document 1, the followability for detecting the through current can be improved. As described above, the dead time can be adjusted appropriately.

As in step S18 of FIG. 7, when the frequency f2 substantially matches the switching frequency f1, the control unit 10 lengthens the dead time TD as in step S20. As a result, it is possible to suppress the flow of the through current 24. Therefore, it is possible to suppress the increase in heat generation of the transistors Q1 and Q2 or the loss of the power conversion circuit caused by the flow of the through current 24.

As in step S24 of FIG. 7, when the input current Iin or the voltage difference ΔV does not exceed the threshold value Is or Vth, or the frequency f2 does not substantially match the switching frequency f1, as in step S20. Shorten the dead time TD. As a result, the dead time TD becomes long, and it is possible to suppress an increase in loss of the power conversion circuit due to the current flowing through the parasitic diode.

The frequency f2 of the detected input current Iin or the voltage difference ΔV and the switching frequency f1 are substantially the same as long as the through current 24 can be detected. For example, when 2 × | f1-f2 | / (f1 + f2) is equal to or less than a predetermined value, it is determined that the detected frequency and the switching frequency are substantially the same. The predetermined value can be arbitrarily set, for example, 0.1 or 0.01.

As shown in FIG. 3B, the detector 14 includes a transformer 16 having a primary winding L1 and a secondary winding L2 through which an input current Iin flows. At this time, in steps S14 and S22 of FIG. 7, the control unit 10 may detect the frequency at which the current value of the input current I2 flowing through the secondary winding L2 becomes equal to or higher than the threshold value. The detector 14 includes a resistor R connected between both ends of the secondary winding L2, and the control unit 10 may detect the frequency at which the voltage difference ΔV across the resistor R becomes equal to or greater than the threshold value Vth. In this way, by using the transformer 16, the voltage difference ΔV can be increased as shown in FIGS. 5A and 5B. Therefore, the sensitivity for detecting the through current can be improved.

As in steps S11 and S26, the control unit 10 applies a voltage between the input terminals Tin1 and Tin2 when controlling the length of the dead time, and the input voltage when the power conversion circuit performs power conversion. Lower than Vin. As a result, when adjusting the dead time, it is possible to prevent a large through current from flowing and damage the transistors Q1 and Q2. The dead time may be adjusted by applying the input voltage Vin. From the viewpoint of reducing the penetration current, the voltage VDC is preferably 1/5 or less of the input voltage Vin, and more preferably 1/10 or less.

In the first embodiment, the inductor L0, the input capacitor Cin, and the output capacitor Cout are provided, DC power is input between the input terminals Tin1 and Tin2, and the output terminal Tout1 (first output terminal) and the output terminal Tout2 (second output) are provided. The step-down DC-DC converter that outputs DC power to and from the terminal) has been described as an example, but the power conversion circuit is a step-up DC-DC converter, an AC (Alternating Current) -DC converter, or a DC-AC inverter. It may be.

Although the control unit 10 has described an example of PWM control of the transistors Q1 and Q2, the control unit 10 may control the transistors Q1 and Q2 by PFM (Pulse Frequency Modulation). In the case of PFM control, it is preferable that steps S10 to S24 in FIG. 7 are executed when the switching frequency is substantially constant.

Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

10 Control unit 12 Gate driver 14 Detector 16 Transformer

Claims (9)

A first switching element connected between the first input terminal and the second input terminal to which electric power is input between them,
A second switching element connected in series with the first switching element between the first input terminal and the second input terminal,
A driver that alternately turns on and off the first switching element and the second switching element at a switching frequency,
A detector that detects an amount related to the input current input to the first input terminal or the second input terminal, and
A control unit that controls the length of the dead time during which both the first switching element and the second switching element are turned off, based on the frequency at which the detected amount becomes equal to or higher than the threshold value and the switching frequency. Power conversion circuit to be equipped. The power conversion circuit according to claim 1, wherein the control unit shortens the dead time when the detected amount does not exceed the threshold value or the frequency does not substantially match the switching frequency. The power conversion circuit according to claim 1 or 2, wherein the control unit increases the dead time when the frequency substantially matches the switching frequency. The detector includes a transformer having a primary winding and a secondary winding through which the input current flows, and the amount related to the input current is any of claims 1 to 3 which is a current value flowing through the secondary winding. The power conversion circuit according to item 1. The detector includes a transformer having a primary winding and a secondary winding through which the input current flows, and a resistor connected between both ends of the secondary winding, and the amount related to the input current is The power conversion circuit according to any one of claims 1 to 3, which is a voltage difference between both ends of the resistor. The power conversion circuit according to any one of claims 1 to 3, wherein the detector includes a resistor through which the input current flows, and the amount related to the input current is a voltage difference between both ends of the resistor. The inductor includes an inductor in which one end is connected to a node between the first switching element and the second switching element and the other end is connected to a first output terminal.
DC power is input between the first input terminal and the second input terminal,
The power conversion circuit according to any one of claims 1 to 6, wherein DC power is output between the first output terminal and the second output terminal. An input capacitor connected in parallel with the first switching element and the second switching element is provided between the first input terminal and the second input terminal.
The power conversion circuit according to claim 7, wherein the detector detects an amount related to the input current between the first input terminal and the input capacitor. The control unit applies a voltage applied between the first input terminal and the second input terminal when controlling the length of the period during which both the first switching element and the second switching element are turned off. The power conversion circuit according to any one of claims 1 to 8, wherein the voltage is lower than the voltage applied between the first input terminal and the second input terminal when the power conversion circuit performs power conversion.

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