JP2021132143A - Semiconductor device simulation method and manufacturing method - Google Patents

Abstract

To simulate the bias of the operation among a plurality of unit cells in consideration of a horizontal resistance component in an electrode plane connected in common with the plurality of unit cells.SOLUTION: A unit cell 5 includes a front surface unit electrode 40u, and a back surface unit electrode 50u. In a simulation model 2x, the back surface unit electrodes 50u have the same potential among the plurality of unit cells 5. On the other hand, the front surface unit electrodes 40u are electrically connected to each other via a connecting conductor 200 having a resistance component between two adjacent unit cells 5. Further, the front surface unit electrode 40u of one of the plurality of unit cells 5 is provided with a main electrode terminal 210 to which a potential is applied from the outside of the semiconductor device.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to a method for simulating and manufacturing a semiconductor device.

In recent years, in device structure design, efficiency of device structure design has been improved by a technique called TCAD (Technology Computer Aided Design), which uses software necessary for semiconductor device simulation and design on a computer.

As an example, in the design of a power device semiconductor with a vertical structure, a simulation model that simulates the structure and layout of the semiconductor device is created, and the created simulation model is operated on the simulator to obtain electrical characteristics during operation of the device. Can be calculated. As a result, the process from the actual device manufacturing to the measurement can be substituted by the simulation.

Japanese Patent Application Laid-Open No. 2002-373899 (Patent Document 1) provides an example of a method for simulating a vertical power device semiconductor having a repeating structure having periodicity. In Patent Document 1, a configuration in which buffer layers that are in a floating state in an actual device are connected via a resistor between a plurality of unit cells arranged in parallel to have the same potential is actually simulated. It enables characteristic simulation on a chip scale assuming a device.

Japanese Unexamined Patent Publication No. 2002-373899

In a real device, a plurality of unit cells having the same structure are periodically configured in parallel. At this time, each unit cell is connected in parallel by a common electrode, particularly in a device having a vertical structure, by electrodes formed on both main surfaces (front surface and back surface) of the semiconductor. As a method for supplying a voltage to such an electrode, it is known to connect the electrode to a power source by wire bonding.

However, due to the influence of the miniaturization of the device, when the resistance component in the horizontal direction becomes relatively large with the thinning of the electrode, the resistance component between different positions in the electrode surface cannot be ignored. As a result, in wire bonding in which a voltage is supplied to one point on the electrode surface, a potential difference is generated in the electrode surface formed on the main surface depending on the connection position of the wire, so that a plurality of units connected in parallel are connected. There is a concern that the operation (typically, the amount of current) may be biased between cells.

On the other hand, in the simulation method of Patent Document 1, it is clear that the potential of each electrode is common among a plurality of unit cells, so that the bias of the operation between the unit cells in the electrode plane described above is simulated. Can not do it.

The present disclosure has been made to solve such a problem, and an object of the present disclosure is a plurality of units due to the influence of a resistance component in an electrode plane commonly connected to a plurality of unit cells. It is an object of the present invention to provide a simulation method of a semiconductor device capable of simulating a bias of operation between cells.

According to a certain aspect of the present disclosure, in the method of simulating a semiconductor device, the semiconductor device to be analyzed has a plurality of unit cells periodically formed on a semiconductor substrate, and the plurality of unit cells are formed. Electrode surfaces that are electrically connected to each are formed on the main surface of the semiconductor substrate. The simulation method consists of a step in which the simulator accepts an input for forming a plurality of unit cells, and a simulator in which two adjacent unit cells in the plurality of unit cells are included in each of the two unit cells. A resistance component is arranged between the first connection point between the first unit cell and the electrode surface and the second connection point between the second unit cell and the electrode surface of the two unit cells. A step in which the simulator accepts an input for applying a predetermined potential to the connection terminal point on the electrode surface from the outside of the semiconductor device, and a step in which the simulator accepts an input for applying the input to the connection terminal point in advance. Under the specified potentials, the potentials of the connection points between the plurality of unit cells and the electrode surfaces are set as separate ones, and the arithmetic processing for separately analyzing the operation of each of the plurality of unit cells is executed. With steps.

According to another aspect of the present disclosure, in a method for simulating a semiconductor device, the semiconductor device to be analyzed has a plurality of unit cells periodically formed on a semiconductor substrate and has a plurality of units. Electrode surfaces that are electrically connected to each of the cells are formed on the main surface of the semiconductor substrate. In the simulation method, a simulation model is used to apply a predetermined potential to the connection terminal point on the electrode surface from the outside of the semiconductor device, and then the connection point between the plurality of unit cells and the electrode surface is used. The operation of each of the plurality of unit cells is analyzed separately, with the potentials being separate. In the simulation model, in two adjacent unit cells among a plurality of parallel unit cells, the first unit cell of the two unit cells and the first connection point of the electrode surface are used. A resistance component is arranged between the second unit cell of the two unit cells and the second connection point between the electrode surface and the electrode surface.

According to still another aspect of the present disclosure, which is a method of manufacturing a semiconductor device, the step of preparing a semiconductor substrate on which the plurality of unit cells are formed and the main surface of the semiconductor substrate are predetermined by point contact. It includes a step of forming an electrode surface to which a predetermined potential is supplied and a step of bonding a wire for supplying a predetermined potential on the electrode surface. The wire is bonded to a position corresponding to a connection terminal point determined on the electrode surface based on a parameter value for quantifying the bias of the operation of a plurality of unit cells by a method of simulating a semiconductor device.

According to the present disclosure, by performing a simulation in which a resistance component is connected between a connection point between a plurality of unit cells and an electrode surface commonly connected to the plurality of unit cells, the resistance component in the electrode surface can be used. It is possible to simulate the bias of operation among a plurality of unit cells due to the generated potential difference.

It is sectional drawing explaining the structural example of the semiconductor device which is the object of the simulation method of the semiconductor device which concerns on this Embodiment. It is sectional drawing which shows the structural example of each unit cell 5 shown in FIG. It is an equivalent electric circuit diagram of the semiconductor device shown in FIG. It is a schematic plan view which shows an example of the wire-bonded semiconductor device. It is sectional drawing explaining the 1st example of the simulation model of the semiconductor device which concerns on this Embodiment. It is a flowchart which shows an example of the simulation method of the semiconductor device using the simulation model of FIG. It is a graph explaining the illustration example of the simulation result of FIG. It is a circuit diagram explaining the 2nd example of the simulation model of the semiconductor device which concerns on this Embodiment. It is a schematic flowchart explaining the manufacturing method of the semiconductor device which applied the simulation method of the semiconductor device which concerns on this Embodiment.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be designated by the same reference numerals, and the explanations will not be repeated in principle.

FIG. 1 is a cross-sectional view illustrating a structural example of a semiconductor device that is a target of the semiconductor device simulation method according to the present embodiment.

With reference to FIG. 1, the semiconductor device 2 has a vertical structure in which electrodes are formed on the first main surface and the second main surface of the semiconductor substrate 100, respectively. Hereinafter, the first main surface on the upper side of the paper surface is also referred to as a “front surface”, and the second main surface on the lower side of the paper surface is also referred to as a “back surface”.

In the example of FIG. 1, the semiconductor device 2 is an IGBT (Insulated Gate Bipolar Transistor), and a surface electrode 40 as an emitter electrode is formed on the first main surface, and a first surface electrode 40 facing the first main surface is formed. A back surface electrode 50 as a collector electrode is formed on the main surface of 2.

The semiconductor device 2 has a repeating structure of a plurality of unit cells 5. The first main surface side of the plurality of unit cells 5 forms an emitter of an IGBT, and is electrically connected to a common surface electrode 40. Similarly, the second main surface side of the plurality of unit cells 5 forms a collector of the IGBT, and is electrically connected to the common back surface electrode 50. The front electrode 40 and the back electrode 50 are electrically connected to the outside (for example, power supply or ground) of the semiconductor device 2 to supply an electric potential.

In the present embodiment, the description will proceed assuming that the surface electrode (emitter electrode) 40 is supplied with an electric potential in the form of point contact by wire bonding. That is, the surface electrode (emitter electrode) 40 corresponds to one embodiment of the “electrode surface”.

On the other hand, it is assumed that the potential is supplied to the back surface electrode (collector electrode) 50 in the form of surface contact. For example, a metal plate having a thickness of about several hundreds (μm) is contact-fixed to the entire surface of the back surface electrode (collector electrode) 50, and by supplying an electric potential to the metal plate, the back surface electrode (collector electrode) ) 50 is supplied with an electric potential.

FIG. 2 shows a structural example of each unit cell 5 shown in FIG.

With reference to FIG. 2, the unit cell 5 includes an n ^- drift layer 10, a p-base region 60, an n ⁺ emitter region 70, a p ⁺ contact region 80, and a surface unit electrode (emitter) formed on the semiconductor substrate 100. It has a unit electrode) 40u. The p-base region 60, n ⁺ emitter region 70, and p ⁺ contact region 80 are formed on the first main surface side of the semiconductor substrate 100 with ^{respect to the n-drift layer 10.}

The high concentration p ^{+ contact region 80 is selectively formed on the n +} emitter region 70 (first main surface side) in order to obtain good ohmic contact with the emitter unit electrode 40u. The surface unit electrode (emitter unit electrode) 40u corresponds to a part of the surface electrode (emitter electrode) 40 in FIG.

The unit cell 5 further includes a gate insulating film 20, an insulating film 75, and a gate electrode 30. The gate electrode 30 is formed by embedding a conductor in a trench defined by the gate insulating film 20. The insulating film 75 is provided to insulate the gate electrode 30 and the surface electrode (emitter electrode) 40.

^{Further, the unit cell 5 includes an n +} buffer layer 90, a p ⁺ collector layer 95, and a back surface unit electrode (collector electrode) formed on the second main surface side of the semiconductor substrate 100 with respect to the n-drift layer 10. It has 50u. The high-concentration p ⁺ collector layer 95 is formed on the second main surface side of the semiconductor substrate 100 in order to obtain good ohmic contact with the back surface unit electrode (collector unit electrode) 50u. The back surface unit electrode (collector unit electrode) 50u corresponds to a part of the back surface electrode (collector electrode) 50 in FIG. The unit cell 5 constitutes a basic unit of the IGBT in which the collector-emitter current Ice (hereinafter, also simply referred to as the current Ice) is controlled according to the voltage applied to the gate electrode 30.

With reference to FIG. 1 again, on the second main surface side, the n ⁺ buffer layer 90, the p ⁺ collector layer 95, and the back surface electrode (collector electrode) 50 are connected in parallel to a plurality of unit cells 5 (FIG. 1). In 1), it is commonly and continuously formed among 4). That is, the back surface electrode (collector electrode) 50 of FIG. 1 is configured by the aggregate of the back surface unit electrodes 50u of FIG.

Similarly, on the first main surface side, the p-base region 60, n ⁺ emitter region 70, and the surface electrode (emitter electrode) 40 are commonly continuous among a plurality of unit cells 5 connected in parallel. Is formed in. That is, the surface electrode (emitter electrode) 40 of FIG. 1 is formed by the aggregate of the surface unit electrodes 40u of FIG.

As a result, FIG. 3 is obtained as an equivalent electric circuit diagram of the plurality (4) unit cells 5 shown in FIG.

With reference to FIG. 3, each unit cell 5 shown in FIGS. 1 and 2 constitutes an IGBT cell 5x. The semiconductor device 2 is configured by connecting a plurality of IGBT cells 5x in parallel.

Each gate of the plurality of IGBT cells 5x is electrically connected to the power supply voltage side (+ side) of the gate power supply 250 that supplies the gate power supply voltage VG via the gate connection terminal 220. By supplying the gate power supply voltage VG to each gate, it is possible to simulate a state in which a plurality of IGBT cells 5x connected in parallel are turned on.

Each collector of the plurality of IGBT cells 5x is electrically connected to the main circuit power supply 260 that supplies the power supply voltage VDD. On the other hand, each emitter of the plurality of IGBT cells 5x is electrically connected to the ground 265 that supplies the ground voltage GND and the reference voltage side (− side) of the gate power supply 250.

As described above, for the collectors of the plurality of IGBT cells 5x, the back surface electrode (collector electrode) 50 is connected to an external element (for example, a conductor that supplies the power supply voltage VDD) in a surface contact manner. , Power supply voltage VDD is supplied.

On the other hand, in the electrical connection between the emitters of the plurality of IGBT cells 5x and the ground 265, the surface electrode (emitter electrode) 40 common to the emitters of the plurality of IGBT cells 5x is connected to the ground 265 by a wire. It is realized by doing. Hereinafter, the wire connection point between the surface electrode (emitter electrode) 40 and the ground 265 is also referred to as a main electrode terminal 210. The reference voltage side (− side) of the gate power supply 250 is electrically connected to the surface electrode (emitter electrode) 40. In the simulation, the potential on the reference voltage side (-side) of the gate power supply 250 is set to GND, and the gate power supply voltage VG is supplied to each gate electrode 30 from the reference voltage side (+ side).

A small signal electrode terminal 230 for monitoring the emitter potential is provided on the surface electrode (emitter electrode) 40. In the semiconductor device 2, the gate-emitter voltage (hereinafter, also simply referred to as “gate voltage”) and the collector-emitter are measured by measuring the voltage between the small signal electrode terminal 230 and the gate electrode 30 and the collector electrode 50. The inter-voltage can be measured. Usually, the small signal electrode terminal 230 is provided at a position as close as possible to the main electrode terminal 210 within the restrictions from the mounting surface such as bonding.

The emitters of the plurality of IGBT cells 5x are electrically connected to the ground 265 at the connection points 210a to 210d. Each of the connection points 210a to 210d corresponds to an electrical connection point between each unit cell 5 and the common surface electrode (emitter electrode) 40 in FIG. In the example of FIG. 3, the main electrode terminal 210 is provided corresponding to the connection point 210d, and the small signal electrode terminal 230 is provided between the connection point 210a and the connection point 210b.

FIG. 4 is a schematic plan view showing an example of a wire-bonded semiconductor device. FIG. 4 shows a plan view of the semiconductor device 2 of FIG. 1 as viewed from the first main surface side (front surface side).

With reference to FIG. 4, a connection point between the ground 265 and the wire W1 connected to the ground 265 is provided on the surface electrode (emitter electrode) 40. The position of the connection point corresponds to the position of the main electrode terminal 210 in FIG.

Similarly, a connection point between the external voltage measurement node of the semiconductor device 2 and the wire W2 connected to the surface electrode (emitter electrode) 40 is provided on the surface electrode (emitter electrode) 40. The position of the connection point of the wire W2 corresponds to the position of the small signal electrode terminal 230 in FIG.

Further, on the first main surface side, a gate terminal 42 that is insulated from the emitter electrode 40 and electrically connected to the gate electrode 30 of each unit cell 5 is arranged. The gate terminal 42 is connected to the power supply voltage side (+ side) of the gate power supply 250 via the wire W3.

An arbitrary number of unit cells 5 are arranged under the emitter electrode 40 of FIG. 4, and as described with reference to FIG. 1, a common emitter electrode 40 is connected to the emitter region of each unit cell 5. Has been done. The long side of the emitter electrode (surface electrode) 40 has a width W. On the emitter electrode (surface electrode) 40, the distance between the main electrode terminal 210 and the small signal electrode terminal 230 is indicated by L1.

As shown by the dotted line in FIG. 4, the position of the main electrode terminal 210 can be changed by the bonding position of the wire W1.

In the circuit diagram of FIG. 3, the connection points 210a to 210d between the emitters of the plurality of IGBT cells 5x and the ground voltage GND are represented as nodes having the same potential. However, as can be understood from FIG. 4, there is a distance in the electrode plane between the main electrode terminal 210 to which the ground voltage GND is supplied and each of the connection points 210a to 210d in FIG. do.

With the progress of miniaturization of the device, there is a concern that a resistance component depending on the distance is generated in the electrode surface (horizontal direction) due to the influence of the thinning of the surface electrode (emitter electrode) 40. For example, if the thickness of the electrode is on the order of several (μm), it is assumed that the resistance component in the horizontal direction becomes large and the potential difference generated in the electrode surface becomes several (V).

In the presence of such a resistance component, the emitter potential differs among the plurality of IGBT cells 5x. As a result, even if a common gate power supply voltage VG is supplied to the gate electrode 30 of each IGBT cell 5x, there is a concern that the gate-emitter voltage (gate voltage) will differ among the plurality of IGBT cells 5x. NS.

Generally, in the on region of the IGBT, even if the collector-emitter voltage is the same, if the gate voltage is different, the collector-emitter current Ice will be different. Therefore, when the gate voltage imbalance among the plurality of IGBT cells 5x occurs due to the influence of the resistance component in the horizontal direction in the surface electrode (collector electrode) 50 described above, the operation of the plurality of IGBT cells 5x, Specifically, there is a concern that the magnitude of the current Ice may be biased.

On the other hand, based on the device structure of FIG. 1 and the circuit diagram of FIG. 3, the simulation is performed with the emitters of a plurality of IGBT cells 5x to which the ground voltage GND is supplied via the point contact by the wire as the same potential. If this is done, it is difficult to evaluate the current bias between the plurality of IGBT cells 5x described above.

Therefore, in the present embodiment, the simulation of the semiconductor device is executed by using the simulation model described below.

FIG. 5 is a cross-sectional view illustrating a first example of a simulation model of the semiconductor device according to the present embodiment. The simulation model 2x shown in FIG. 5 is assumed to be used for a simulation using a device simulator whose analysis target is the cross-sectional structure or the three-dimensional structure of the device.

With reference to FIG. 5, the simulation model 2x includes a plurality of unit cells 5, a connecting conductor 200 indicating a resistor, a main electrode terminal 210, and a small signal electrode terminal 230. The structure of each unit cell 5 is the same as that in FIG. The connecting conductor 200 connects between the surface unit electrodes (emitter unit electrodes) 40u of the adjacent unit cells 5.

The resistance component (horizontal direction) between the emitters of the unit cell 5 can be simulated by the electric resistance value of the connecting conductor 200. That is, by using a simulation model including the connecting conductor 200, it is possible to perform a simulation in consideration of the resistance component between the emitters of each IGBT cell 5x in the circuit diagram of FIG.

Further, depending on which unit cell 5 the emitter unit electrode 40u is provided with the main electrode terminal 210, a resistance component between the main electrode terminal 210 and the emitter of each IGBT cell 5x in FIG. 3 is provided between the two. It can be simulated by the existing connecting conductor 200. The small signal electrode terminal 230 is provided on the surface unit electrode (emitter unit electrode) 40u of the unit cell 5 located at the arrangement location in accordance with the layout at the time of mounting.

Using the resistivity ρ (Ω · m) of the surface electrode (emitter electrode) 40 and the thickness d, the electrical resistance value R between the two points at the distance L on the emitter electrode 40 is approximately the following equation (1). ).

R = ρ ・ L ・ (W ・ d)… (1)
In the simulation model 2x of FIG. 5, the emitter unit electrode 40u has the same potential in the unit cell 5, while the electrical resistance value of the resistance component between the unit cells 5 in the surface electrode (emitter electrode) 40 is made to correspond to the electric resistance value. , The shape and dimensions of the connecting conductor 200, and the material (resistivity) are set. This enables a simulation that takes into account the horizontal resistance component in the surface electrode (emitter electrode) 40.

In the simulation model 2x of FIG. 5, the front surface unit electrode (emitter unit electrode) 40u and the back surface unit electrode (collector unit electrode) 50u correspond to one embodiment of the “first unit electrode” and the “second unit electrode”. However, the gate electrode 30 corresponds to an embodiment of the “control electrode”. Further, the connecting conductor 200 expresses a "resistive component" in the horizontal direction. Further, the main electrode terminal 210 corresponds to an embodiment of a “connection terminal point” that receives a potential supply from the outside of the semiconductor device 2.

FIG. 6 shows a flowchart showing an example of a method of simulating a semiconductor device using the simulation model 2x of FIG. FIG. 6 shows a control process in a general-purpose device simulator for realizing the simulation method of the semiconductor device according to the present embodiment.

With reference to FIG. 6, the simulator receives an input for creating the unit cell 5 on the device simulator in step 101 (hereinafter, also simply referred to as “S”) 101. For example, an input for defining the structure of FIG. 2 is accepted.

Further, in S102, the simulator accepts an input for arranging a plurality of unit cells 5 connected in parallel in parallel. Thereby, the position of each unit cell 5 in the electrode surface (horizontal plane) with respect to the surface electrode (emitter electrode) 40 in the entire semiconductor device 2 shown in FIGS. 1 and 4 is defined. At this stage, the surface unit electrodes 40u of each unit cell 5 are electrically independent of each other. Similarly, the back surface unit electrodes 50u of each unit cell 5 are also electrically independent of each other.

In S103, the simulator receives an input for connecting the back surface unit electrodes (collector unit electrodes) 50u of adjacent unit cells 5 without using a resistor. As a result, the back surface electrode (collector electrode) 50, which is fed in the form of surface contact, is simulated so that the potentials of the back surface electrodes (collector electrodes) 50 are the same among the unit cells 5.

In S104, the simulator receives an input for connecting the back electrode 50s of adjacent unit cells 5 via a resistor, for example, the connecting conductor 200 shown in FIG.

Further, in S105, the resistance value generated in the horizontal direction is calculated at the surface electrode (emitter electrode) 40 of the actual device. For example, the resistance value in the horizontal direction can be separately obtained by an actual measurement experiment or a simulation of a conductor plate simulating the dimensions and materials of the surface electrode 40.

In S106, the simulator accepts the input of the parameters (dimensions and electric resistance value) indicating the electric resistance value of the resistor (connecting conductor 200) input in S104. At this time, the parameters of each resistor (connecting conductor 200) are determined in correspondence with the resistance value (horizontal direction) of the entire surface electrode 40 obtained in advance in S105.

In S107, as described with reference to FIG. 5, the simulator receives an input for providing the main electrode terminal 210 on the emitter unit electrode (surface unit electrode) 40u of any unit cell 5. As a result, the main electrode terminal 210 is arranged at an arbitrary position of the emitter electrode 40. As a result, a horizontal component resistor due to the connecting conductor 200 exists between the main electrode terminal 210 arranged at an arbitrary position and the emitter (emitter unit electrode 40u) of each unit cell 5. .. Further, in S107, the input for providing the small signal electrode terminal 230 on the surface unit electrode 40u of any unit cell 5 is accepted. As a result, the small signal electrode terminal 230 is arranged at an arbitrary position of the surface electrode (emitter electrode) 40.

In S108, the simulator receives an input for providing a main terminal connected to the main circuit power supply 260 at an arbitrary position of the back surface electrode (collector electrode) 50. Since the collector unit electrodes 50u of each unit cell 5 are connected at the same potential by the input in S103, the simulation does not depend on the position (horizontal direction) of the main terminal in the back surface electrode (collector electrode) 50. The result is the same.

In S109, the simulator receives an input for applying the power supply voltage VDD to the main terminal and applying the ground voltage GND to the main electrode terminal 210. As a result, in the surface electrode (emitter electrode) 40, the simulation is performed in such a manner that the ground voltage GND is applied to the main electrode terminal 210. Further, in S109, an input for applying the power supply voltage of the gate power supply 250 is received to the gate electrode 30 of each unit cell 5. This makes it possible to simulate device operation with a plurality of unit cells 5 connected in parallel turned on.

In S110, the simulator executes arithmetic processing for simulating the current Ice of each of the plurality of unit cells 5 under the voltage applied state by S109. Then, in S111, the calculation result (Ice) obtained in S110 is output.

For example, while fixing the gate power supply voltage VG, the power supply voltage VDD, that is, the current Ice in each of the plurality of unit cells 5 is calculated under the fluctuation of the collector-emitter voltage Vce of the plurality of unit cells 5. be able to. In S111, it is also possible to illustrate the simulation result (Ice) thus obtained.

FIG. 7 is a graph illustrating an illustrated example of simulation results. In FIG. 7, as a simulation result of a semiconductor device in which four unit cells 5 are connected in parallel, the current Ice of each of the four unit cells (IGBT cells) 5 under a change of the power supply voltage VDD. The characteristic lines 301 to 304 are shown.

With reference to FIG. 7, the emitter potential is not uniform between the four unit cells 5 due to the presence of the connecting conductor 200 with respect to the application of the same power supply voltage VDD. As a result, the current Ice differs between the four unit cells 5 with respect to a certain power supply voltage VDD (main circuit power supply 260) and the gate power supply voltage VG.

By plotting the current Ice calculated by each VDD for each of the four unit cells 5 under the change of the power supply voltage VDD, the characteristic lines 301 to 304 shown in FIG. 7 can be obtained. ..

Quantitatively the current bias among the plurality of unit cells 5 by the parameter value Ipr indicating the variation of the current Ice of the four unit cells 5 at a predetermined voltage (for example, VDD = 10 (V)). Can be evaluated. For example, the parameter value Ipr can be defined by the difference between the maximum value and the minimum value of the current Ice of the four unit cells 5, as shown in FIG.

Here, if the position of the main electrode terminal 210 in the surface electrode (emitter electrode) 40 changes, the distance between the main electrode terminal 210 and the emitter (equivalent to the emitter unit electrode 40u) of each unit cell 5 changes. The resistance component in the horizontal direction also changes. Therefore, it is understood that when the position of the main electrode terminal 210 changes, the characteristic lines 301 to 304 shown in FIG. 7 also change, and the parameter value Ipr also changes. In other words, there is a position of the main electrode terminal 210 within the surface electrode 40 that can minimize the parameter value Ipr, that is, the current bias between the plurality of unit cells 5 connected in parallel. ..

With reference to FIG. 5 again, the position of the main electrode terminal 210 in the horizontal plane changes depending on the bonding position of the wire W1 with respect to the surface electrode 40. For example, in the set of candidate points (210 #) of the main electrode terminals shown in FIG. 5, the position of the connection point of the wire W1 (that is, the position of the main electrode terminal 210) is changed to be changed in FIG. By repeatedly executing the simulation processes of S107 to S111, characteristic lines 301 to 304 (FIG. 7) for each candidate point of the main electrode terminal 210 can be obtained. Then, the position of the main electrode terminal 210 when the parameter value Ipr obtained from the characteristic lines 301 to 304 is minimized can be obtained as the "optimal bonding position".

In FIG. 4 and the like, for the sake of simplicity, an example in which the main electrode terminal 210 and the small signal electrode terminal 230 are connected to the ground voltage GND by a single wire has been described, but in reality, there are a plurality of wires. It is also possible to configure the main electrode terminal 210 by using the parallel connection of the wires of the above. In this case, the center position of the plurality of wires and the stitch interval can be used as parameters indicating the position of the main electrode terminal 210.

Although the simulation assuming the device simulation tool has been described in FIGS. 5 and 6, the simulation method of the semiconductor device according to the present embodiment can also be realized by using a circuit simulator for analyzing an electric circuit. be.

FIG. 8 is a circuit diagram illustrating a second example of a simulation model of the semiconductor device according to the present embodiment. The simulation model 2y shown in FIG. 8 can be used for simulation using a circuit simulator whose analysis target is an electric circuit diagram.

With reference to FIG. 8, the simulation model 2y differs from the electric circuit diagram shown in FIG. 3 in that the resistance element Rx is connected between the emitters of the adjacent IGBT cells 5x. The resistance element Rx simulates the resistance component (horizontal direction) between the emitters of the unit cells 5 in the surface electrode (emitter electrode) 40, similarly to the connecting conductor 200 in the simulation model 2x of FIG.

Further, depending on which of the connection points 210a to 210d the main electrode terminal 210 is provided, the resistance component between the main electrode terminal 210 and the emitter of each IGBT cell 5x is set by the resistance element Rx connected between the two. Can be simulated. Similarly, the small signal electrode terminal 230 can be provided corresponding to any of the connection points 210a to 210d.

On the other hand, in the simulation model 2y, the collectors of the plurality of unit cells 5 and the VDD side (+ side) of the main circuit power supply 260 are connected without a resistance element. That is, for the collectors of the respective IGBT cells 5x to which the power supply voltage VDD is supplied in the mode of surface contact, the simulation is performed so that the potentials are the same among the plurality of IGBT cells 5x, as in the simulation model 2x.

In the simulation model 2y of FIG. 8, each IGBT cell 5x corresponds to one embodiment of the “unit element”, and the collector and emitter of each IGBT cell 5x are the “first unit electrode” and the “second unit electrode”. Corresponds to one embodiment of the "control electrode". Further, the resistance element Rx expresses the "resistance component" in the horizontal direction. Further, the main electrode terminal 210 corresponds to one embodiment of the “connection terminal point”.

When executing the flowchart of FIG. 6 using the simulation model 2y of FIG. 8, in S101 (FIG. 6), the circuit simulator receives an input that defines the basic characteristic (Vce-Ice characteristic) of the unit IGBT cell 5x. be able to. Further, in S102 and S103 (FIG. 6), the circuit simulator accepts the input of the configuration of the parallel connection portion of the plurality of IGBT cells 5x in FIG. Then, in S104 (FIG. 6), the circuit simulator receives an input for connecting the resistance element Rx (FIG. 8) between the emitters of the adjacent IGBT cells 5x.

Then, similarly to FIG. 6 (S105), the electric resistance value of each resistance element Rx can be obtained from the resistance value in the horizontal direction of the surface electrode 40 of the actual device obtained in advance. In S106, the circuit simulator accepts the input of the electric resistance value of the resistance element Rx. Further, in S107 and S108, the main electrode terminal 210 and the small signal electrode terminal 230 are provided at arbitrary positions of the surface electrode 40 depending on which node of the IGBT cell 5x has the same potential as the emitter of the main electrode terminal 210 and the small signal electrode terminal 230. A simulation in which the signal electrode terminal 230 is provided becomes possible.

Then, in S109, inputs for applying the power supply voltage VDD, the gate power supply voltage VG, and the ground voltage GND to the simulation model 2y of FIG. 8 are accepted by the circuit simulator. Further, in S110, an arithmetic process for simulating the current Ice of the plurality of IGBT cells 5x is executed by the circuit simulator.

In the arithmetic processing of S110, the emitter potentials of the plurality of IGBT cells 5x become uneven due to the arrangement of the resistance elements Rx, so that the current Ice is set between the plurality of IGBT cells 5x having the same reference characteristic (Vce-Ice). There is a difference. As a result, it is possible to obtain the simulation results (characteristic lines 301 to 304) of FIG. 7 even when the simulation model 2y is analyzed using the circuit simulator.

As a result, the characteristic lines 301 to 304 (parameter value Ipr) with respect to the position of the main electrode terminal 210 can be obtained by the circuit simulation using the simulation model 2y as in the case of using the device simulator. As a result, it is possible to obtain an "optimal bonding position" that can minimize the current bias between the plurality of unit cells 5 connected in parallel.

As described above, according to the simulation method of the semiconductor device according to the present embodiment, the wire bonding formed on the first main surface or the second main surface is common to the plurality of unit cells connected in parallel. It is possible to simulate the current bias between a plurality of unit cells by simulating the electrode to which the potential is supplied in consideration of the resistance component in the horizontal direction (in the electrode plane).

As a result, it is possible to obtain the optimum bonding position in the electrode plane for suppressing the current bias between a plurality of unit cells connected in parallel by simulation.

FIG. 9 is a schematic flowchart illustrating a method of manufacturing a semiconductor device to which the method of simulating a semiconductor device according to the present embodiment is applied.

With reference to FIG. 9, in step 100 (hereinafter, also simply referred to as “P”) 100, a simulation according to the present embodiment in which the simulation model 2x or 2y is analyzed according to the flowchart described in FIG. The method determines the wire bonding position for positioning the main electrode terminal 210. For example, the wire bonding position at P100 can be determined in correspondence with the “optimal bonding position” that minimizes the above-mentioned parameter value Ipr.

In P110, in the structure of FIG. 1, a semiconductor substrate 100 is prepared in which a portion other than the surface electrode (emitter electrode) 40 is manufactured. Then, in P120, a surface electrode (emitter electrode) 40 common to the plurality of unit cells 5 is formed on the surface (first main surface) of the semiconductor substrate 100 prepared in P110.

After that, in P120, the wires W1 to W3 shown in FIG. 5 are bonded to the surface electrode (emitter electrode) 40 according to the wire bonding position determined in P100. As a result, a semiconductor device (for example, an IGBT device) in which the current bias between a plurality of unit cells connected in parallel is suppressed according to the wire bonding position obtained by the semiconductor device simulation method according to the present embodiment is manufactured. It is possible to do.

It is preferable that P100 is completed before P110 and P120, but if it is completed every time more than P130, it can be processed in parallel with P110 and / or P120.

Further, in FIGS. 1 and 2, a cell configuration having a vertical structure having a trench gate is illustrated, but the configuration of the unit cell is not particularly limited, and a plurality of the same repeating units (unit cells) are connected in parallel. The structure of each unit cell is arbitrary as long as it is configured.

Further, in the present embodiment, the simulation in which the resistance component in the horizontal direction is taken into consideration in the surface electrode has been described, but if the electrode surface is to which the potential is supplied in the mode of point contact, the electrode provided on any surface can be used. However, it is possible to execute the same simulation. Further, even in a semiconductor device in which an electric potential is supplied to a plurality of electrode surfaces in a point contact manner, the same simulation model can be applied to each electrode surface.

Further, in the present embodiment, the simulation method and the manufacturing method of the semiconductor device in which the unit cells of the IGBT are connected in parallel have been described, but a plurality of the same repeating units (unit cells) are connected in parallel, and further, the first or the first or On the second main surface, as long as it has a structure common to the plurality of unit cells and having an electrode to which an electric potential is supplied by wire bonding, it can be used as a semiconductor device constituting an arbitrary device other than an IGBT. On the other hand, it is possible to apply the simulation method and the manufacturing method according to the present embodiment.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The technical scope of the present disclosure is indicated by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

2 Semiconductor device, 2x, 2y simulation model, 5 unit cell, 5x cell, 10 n ^- drift layer, 20 gate insulating film, 30 gate electrode, 40 surface electrode (emitter electrode), 40u surface unit electrode (emitter unit electrode), 42 Gate terminal, 50 backside electrode (collector electrode), 50u backside unit electrode (collector unit electrode), 60 p base region, 70 n ⁺ emitter region, 75 insulation film, 80 p ⁺ contact region, 90 n ⁺ buffer layer, 95 p ⁺ collector layer, 100 semiconductor substrate, 200 connecting conductor, 210 main electrode terminal, 210a to 210d connection point, 220 gate connection terminal, 230 small signal electrode terminal, 250 gate power supply, 260 main circuit power supply, 265 ground, 301-304 Characteristic line, GND ground voltage, Ice collector-emitter current, Ipr parameter value (current bias), Rx resistance element, VDD power supply voltage (main circuit), VG gate power supply voltage, W1 to W3 wires.

Claims (7)

Simulation of a semiconductor device having a plurality of unit cells periodically formed on a semiconductor substrate and having an electrode surface electrically connected to each of the plurality of unit cells formed on the main surface of the semiconductor substrate. It ’s a method,
A step in which the simulator accepts inputs for forming the plurality of unit cells,
In the two adjacent unit cells of the plurality of unit cells, the simulator determines that the first unit cell of the two unit cells and the first connection point of the electrode surface are connected to each other. A step of accepting an input for arranging a resistance component between the second unit cell of the two unit cells and the second connection point of the electrode surface, and
A step in which the simulator receives an input for applying a predetermined potential to a connection terminal point on the electrode surface from the outside of the semiconductor device, and
The simulator sets the potentials of the plurality of unit cells and the connection points of the electrode surfaces as separate ones under the condition that the predetermined potentials are applied to the connection terminal points, and the plurality of unit cells. A method of simulating a semiconductor device, which comprises a step of executing an arithmetic process for separately analyzing each operation of the semiconductor device. The simulator is a device simulator for analyzing the cross-sectional structure or the three-dimensional structure of the device.
Each of the plurality of unit cells is formed on a first unit electrode formed on the first main surface of the semiconductor substrate and a second main surface of the semiconductor substrate facing the first main surface. A second unit electrode, a plurality of semiconductor layers formed between the first and second unit electrodes on the semiconductor substrate, and the plurality of semiconductor layers between the first and second unit electrodes. It is input to the simulator so as to have a control electrode into which a voltage for controlling the amount of current flowing through is input.
The resistance component input to the simulator
A connecting conductor connecting the first or second unit electrodes of two adjacent unit cells of the plurality of unit cells on at least one of the first main surface and the second main surface. The method for simulating a semiconductor device according to claim 1. The simulator is a device simulator for analyzing an electric circuit diagram.
The plurality of unit cells are input to the simulator as a plurality of unit elements electrically connected in parallel.
Each of the plurality of unit elements
The first unit electrode and
The second unit electrode and
A plurality of semiconductor layers formed between the first and second unit electrodes, and
It has a control electrode to which a voltage for controlling the amount of current flowing between the first and second unit electrodes is input.
The resistance component input to the simulator connects at least one of the two adjacent unit elements of the plurality of unit elements between the first unit electrode and the second unit electrode. The method for simulating a semiconductor device according to claim 1, further comprising a resistance element. Simulation of a semiconductor device having a plurality of unit cells periodically formed on a semiconductor substrate and having an electrode surface electrically connected to each of the plurality of unit cells formed on the main surface of the semiconductor substrate. It ’s a method,
In two adjacent unit cells of the plurality of unit cells arranged in parallel, a first connection point between the first unit cell of the two unit cells and the electrode surface, and Using a simulation model in which a resistance component is arranged between the second unit cell of the two unit cells and the second connection point between the electrode surface and the electrode surface, a simulation model is used.
Under the condition that a predetermined potential is applied to the connection terminal point on the electrode surface from the outside of the semiconductor device, the potentials of the plurality of unit cells and the connection point between the electrode surface are separate. As a method for simulating a semiconductor device, the operation of each of the plurality of unit cells is analyzed separately. The simulation model is analyzed by a device simulator that analyzes the cross-sectional structure or three-dimensional structure of the device.
Each of the plurality of unit cells is formed on a first unit electrode formed on the first main surface of the semiconductor substrate and a second main surface of the semiconductor substrate facing the first main surface. A second unit electrode, a plurality of semiconductor layers formed between the first and second unit electrodes on the semiconductor substrate, and the plurality of semiconductor layers between the first and second unit electrodes. Modeled to have a control electrode to which a voltage is input to control the amount of current flowing through it.
The resistance component is formed between the first or second unit electrodes of two adjacent unit cells of the plurality of unit cells on at least one of the first main surface and the second main surface. 4. The method of simulating a semiconductor device according to claim 4, which is modeled to have a connecting conductor to connect the two. The simulation model is analyzed by a device simulator that analyzes an electric circuit diagram.
The plurality of unit cells are modeled as a plurality of unit elements electrically connected in parallel, and each of the plurality of unit elements includes a first unit electrode, a second unit electrode, and the first and the first unit electrodes. A model having a plurality of semiconductor layers formed between the second unit electrodes and a control electrode to which a voltage for controlling the amount of current flowing between the first and second unit electrodes is input. Being made
The resistance component has a resistance element that connects at least one of the first unit electrode and the second unit electrode of two adjacent unit elements of the plurality of unit elements. The method for simulating a semiconductor device according to claim 4, which is modeled. The step of preparing the semiconductor substrate on which the plurality of unit cells are formed, and
A step of forming the electrode surface to which the predetermined potential is supplied by point contact on the main surface of the semiconductor substrate, and
The connection terminal point determined on the electrode surface based on a parameter value for quantifying the bias of the operation of the plurality of unit cells by the method of simulating the semiconductor device according to any one of claims 1 to 6. A method for manufacturing a semiconductor device, comprising a step of bonding a wire for supplying a predetermined potential to a position corresponding to the above.

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